Fix ethernet clk_mode for GPIO0_OUT

[jorticus]

What does this implement/fix?

The ethernet component has a bug preventing clk_mode: GPIO0_OUT from working.

This is due to the fact that the IDF enum for clk_mode_t has the same value for EMAC_CLK_IN_GPIO and EMAC_APPL_CLK_OUT_GPIO (both are equal to 0), and so the logic that sets rmii.clock_mode sets the incorrect value - we would expect mode to be set to EMAC_CLK_OUT, but instead it is set to EMAC_CLK_EXT_IN.

Fix is to separate the two enums and select the correct mode+gpio in the python layer.

Types of changes

• Bugfix (non-breaking change which fixes an issue)
• New feature (non-breaking change which adds functionality)
• Breaking change (fix or feature that would cause existing functionality to not work as expected)
• Other

Test Environment

• ESP32
• ESP32 IDF
• ESP8266
• RP2040

Example entry for config.yaml:

# Example config.yaml
ethernet:
  type: RTL8201
  mdc_pin: GPIO23
  mdio_pin: GPIO18
  clk_mode: GPIO0_OUT
  phy_addr: 0

Checklist:

• The code change is tested and works locally.
• Tests have been added to verify that the new code works (under tests/ folder).

If user exposed functionality or configuration variables are added/changed:

• Documentation added/updated in esphome-docs.

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[jorticus]

Apologies, I mixed up my base branch and confused the bot. Things have been fixed now, but let me know if you'd rather me re-submit.