From b26343ab67a07599a400563d948aaee4b1b10a07 Mon Sep 17 00:00:00 2001 From: Lucas Saavedra Vaz <32426024+lucasssvaz@users.noreply.github.com> Date: Wed, 12 Nov 2025 12:56:38 -0300 Subject: [PATCH 1/3] feat(esp32c61): Add support for ESP32-C61 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Co-authored-by: Jan Procházka <90197375+P-R-O-C-H-Y@users.noreply.github.com> --- .github/scripts/find_all_boards.sh | 2 +- .github/workflows/build_component.yml | 11 +- CMakeLists.txt | 2 +- README.md | 2 +- boards.txt | 170 +++++++++++ cores/esp32/Esp.cpp | 21 +- cores/esp32/HardwareSerial.h | 8 +- cores/esp32/chip-debug-report.cpp | 5 +- cores/esp32/esp32-hal-cpu.c | 161 ++++++----- cores/esp32/esp32-hal-cpu.h | 68 +++++ cores/esp32/esp32-hal-gpio.c | 4 + cores/esp32/esp32-hal-i2c-slave.c | 10 +- cores/esp32/esp32-hal-matrix.c | 2 + cores/esp32/esp32-hal-misc.c | 6 +- cores/esp32/esp32-hal-spi.c | 272 +++++++++--------- cores/esp32/esp32-hal-spi.h | 2 +- cores/esp32/esp32-hal.h | 2 +- docs/en/lib_builder.rst | 5 +- idf_component.yml | 10 +- .../Arduino_ESP_Matter_over_OpenThread/ci.yml | 1 + .../ResetReason/ResetReason/ResetReason.ino | 2 + libraries/SPI/src/SPI.cpp | 15 +- platform.txt | 1 + tests/requirements.txt | 8 +- variants/esp32c61/pins_arduino.h | 37 +++ 25 files changed, 583 insertions(+), 244 deletions(-) create mode 100644 variants/esp32c61/pins_arduino.h diff --git a/.github/scripts/find_all_boards.sh b/.github/scripts/find_all_boards.sh index 67b46661ca5..c37d306151e 100755 --- a/.github/scripts/find_all_boards.sh +++ b/.github/scripts/find_all_boards.sh @@ -8,7 +8,7 @@ boards_list=$(grep '.tarch=' boards.txt) while read -r line; do board_name=$(echo "$line" | cut -d '.' -f1 | cut -d '#' -f1) # skip esp32c2 as we dont build libs for it - if [ "$board_name" == "esp32c2" ]; then + if [ "$board_name" == "esp32c2" ] || [ "$board_name" == "esp32c61" ]; then echo "Skipping 'espressif:esp32:$board_name'" continue fi diff --git a/.github/workflows/build_component.yml b/.github/workflows/build_component.yml index e5c0f244f65..7a11ca768ec 100644 --- a/.github/workflows/build_component.yml +++ b/.github/workflows/build_component.yml @@ -4,13 +4,13 @@ on: workflow_dispatch: inputs: idf_ver: - description: "IDF Versions" - default: "release-v5.3,release-v5.4,release-v5.5" + description: "Comma separated list of IDF branches to build" + default: "release-v5.5" type: "string" required: true idf_targets: - description: "IDF Targets" - default: "esp32,esp32s2,esp32s3,esp32c2,esp32c3,esp32c6,esp32h2,esp32p4" + description: "Comma separated list of IDF targets to build" + default: "esp32,esp32s2,esp32s3,esp32c2,esp32c3,esp32c5,esp32c6,esp32c61,esp32h2,esp32p4" type: "string" required: false push: @@ -37,6 +37,7 @@ on: - "variants/esp32c3/**" - "variants/esp32c5/**" - "variants/esp32c6/**" + - "variants/esp32c61/**" - "variants/esp32h2/**" - "variants/esp32p4/**" - "variants/esp32s2/**" @@ -125,7 +126,7 @@ jobs: echo "esp32,esp32s2,esp32s3,esp32c2,esp32c3,esp32c6,esp32h2,esp32p4" ;; "release-v5.5") - echo "esp32,esp32s2,esp32s3,esp32c2,esp32c3,esp32c5,esp32c6,esp32h2,esp32p4" + echo "esp32,esp32s2,esp32s3,esp32c2,esp32c3,esp32c5,esp32c6,esp32c61,esp32h2,esp32p4" ;; *) echo "" diff --git a/CMakeLists.txt b/CMakeLists.txt index d9b295dfa70..a48d0b1ae85 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -378,7 +378,7 @@ set(priv_requires fatfs nvs_flash app_update spiffs bootloader_support bt esp_hi if(NOT CONFIG_ARDUINO_SELECTIVE_COMPILATION OR CONFIG_ARDUINO_SELECTIVE_OpenThread) #if(CONFIG_SOC_IEEE802154_SUPPORTED) # Does not work! #if(CONFIG_OPENTHREAD_ENABLED) # Does not work! - if(IDF_TARGET STREQUAL "esp32c6" OR IDF_TARGET STREQUAL "esp32h2" OR IDF_TARGET STREQUAL "esp32c5") # Sadly only this works + if(IDF_TARGET STREQUAL "esp32c6" OR IDF_TARGET STREQUAL "esp32h2" OR IDF_TARGET STREQUAL "esp32c5" OR IDF_TARGET STREQUAL "esp32c61") # Sadly only this works list(APPEND requires openthread) endif() endif() diff --git a/README.md b/README.md index 51ab98e0af1..e6a0eb2dffb 100644 --- a/README.md +++ b/README.md @@ -76,7 +76,7 @@ Here are the ESP32 series supported by the Arduino-ESP32 project: | ESP32-S3 | Yes | Yes | [ESP32-S3](https://www.espressif.com/sites/default/files/documentation/esp32-s3_datasheet_en.pdf) | > [!NOTE] -> ESP32-C2 is also supported by Arduino-ESP32 but requires using Arduino as an ESP-IDF component or rebuilding the static libraries. +> ESP32-C2 and ESP32-C61 are also supported by Arduino-ESP32 but require using Arduino as an ESP-IDF component or rebuilding the static libraries. > For more information, see the [Arduino as an ESP-IDF component documentation](https://docs.espressif.com/projects/arduino-esp32/en/latest/esp-idf_component.html) or the > [Lib Builder documentation](https://docs.espressif.com/projects/arduino-esp32/en/latest/lib_builder.html), respectively. diff --git a/boards.txt b/boards.txt index 9add21d43e7..f666dbe17ed 100644 --- a/boards.txt +++ b/boards.txt @@ -983,6 +983,176 @@ esp32c6.menu.ZigbeeMode.zczr_debug.build.zigbee_libs=-lesp_zb_api.zczr.debug -lz ############################################################## +esp32c61.name=ESP32C61 Dev Module +esp32c61.hide=true + +esp32c61.bootloader.tool=esptool_py +esp32c61.bootloader.tool.default=esptool_py + +esp32c61.upload.tool=esptool_py +esp32c61.upload.tool.default=esptool_py +esp32c61.upload.tool.network=esp_ota + +esp32c61.upload.maximum_size=1310720 +esp32c61.upload.maximum_data_size=327680 +esp32c61.upload.flags= +esp32c61.upload.extra_flags= +esp32c61.upload.use_1200bps_touch=false +esp32c61.upload.wait_for_upload_port=false + +esp32c61.serial.disableDTR=false +esp32c61.serial.disableRTS=false + +esp32c61.build.tarch=riscv32 +esp32c61.build.target=esp +esp32c61.build.mcu=esp32c61 +esp32c61.build.core=esp32 +esp32c61.build.variant=esp32c61 +esp32c61.build.board=ESP32C61_DEV +esp32c61.build.bootloader_addr=0x0 + +esp32c61.build.cdc_on_boot=0 +esp32c61.build.f_cpu=160000000L +esp32c61.build.flash_size=4MB +esp32c61.build.flash_freq=80m +esp32c61.build.flash_mode=qio +esp32c61.build.boot=qio +esp32c61.build.partitions=default +esp32c61.build.defines= + +## IDE 2.0 Seems to not update the value +esp32c61.menu.JTAGAdapter.default=Disabled +esp32c61.menu.JTAGAdapter.default.build.copy_jtag_files=0 +esp32c61.menu.JTAGAdapter.builtin=Integrated USB JTAG +esp32c61.menu.JTAGAdapter.builtin.build.openocdscript=esp32c61-builtin.cfg +esp32c61.menu.JTAGAdapter.builtin.build.copy_jtag_files=1 +esp32c61.menu.JTAGAdapter.external=FTDI Adapter +esp32c61.menu.JTAGAdapter.external.build.openocdscript=esp32c61-ftdi.cfg +esp32c61.menu.JTAGAdapter.external.build.copy_jtag_files=1 +esp32c61.menu.JTAGAdapter.bridge=ESP USB Bridge +esp32c61.menu.JTAGAdapter.bridge.build.openocdscript=esp32c61-bridge.cfg +esp32c61.menu.JTAGAdapter.bridge.build.copy_jtag_files=1 + +esp32c61.menu.PSRAM.disabled=Disabled +esp32c61.menu.PSRAM.disabled.build.defines= +esp32c61.menu.PSRAM.enabled=Enabled +esp32c61.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM + +esp32c61.menu.CDCOnBoot.default=Disabled +esp32c61.menu.CDCOnBoot.default.build.cdc_on_boot=0 +esp32c61.menu.CDCOnBoot.cdc=Enabled +esp32c61.menu.CDCOnBoot.cdc.build.cdc_on_boot=1 + +esp32c61.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS) +esp32c61.menu.PartitionScheme.default.build.partitions=default +esp32c61.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS) +esp32c61.menu.PartitionScheme.defaultffat.build.partitions=default_ffat +esp32c61.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS) +esp32c61.menu.PartitionScheme.default_8MB.build.partitions=default_8MB +esp32c61.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336 +esp32c61.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS) +esp32c61.menu.PartitionScheme.minimal.build.partitions=minimal +esp32c61.menu.PartitionScheme.no_fs=No FS 4MB (2MB APP x2) +esp32c61.menu.PartitionScheme.no_fs.build.partitions=no_fs +esp32c61.menu.PartitionScheme.no_fs.upload.maximum_size=2031616 +esp32c61.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS) +esp32c61.menu.PartitionScheme.no_ota.build.partitions=no_ota +esp32c61.menu.PartitionScheme.no_ota.upload.maximum_size=2097152 +esp32c61.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS) +esp32c61.menu.PartitionScheme.noota_3g.build.partitions=noota_3g +esp32c61.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576 +esp32c61.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS) +esp32c61.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat +esp32c61.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152 +esp32c61.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS) +esp32c61.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat +esp32c61.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576 +esp32c61.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS) +esp32c61.menu.PartitionScheme.huge_app.build.partitions=huge_app +esp32c61.menu.PartitionScheme.huge_app.upload.maximum_size=3145728 +esp32c61.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS) +esp32c61.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs +esp32c61.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080 +esp32c61.menu.PartitionScheme.rainmaker=RainMaker 4MB +esp32c61.menu.PartitionScheme.rainmaker.build.partitions=rainmaker +esp32c61.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080 +esp32c61.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA +esp32c61.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota +esp32c61.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656 +esp32c61.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB +esp32c61.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB +esp32c61.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4096000 +esp32c61.menu.PartitionScheme.custom=Custom +esp32c61.menu.PartitionScheme.custom.build.partitions= +esp32c61.menu.PartitionScheme.custom.upload.maximum_size=8388608 + +esp32c61.menu.CPUFreq.160=160MHz (WiFi) +esp32c61.menu.CPUFreq.160.build.f_cpu=160000000L +esp32c61.menu.CPUFreq.120=120MHz (WiFi) +esp32c61.menu.CPUFreq.120.build.f_cpu=120000000L +esp32c61.menu.CPUFreq.80=80MHz (WiFi) +esp32c61.menu.CPUFreq.80.build.f_cpu=80000000L +esp32c61.menu.CPUFreq.40=40MHz +esp32c61.menu.CPUFreq.40.build.f_cpu=40000000L +esp32c61.menu.CPUFreq.20=20MHz +esp32c61.menu.CPUFreq.20.build.f_cpu=20000000L +esp32c61.menu.CPUFreq.10=10MHz +esp32c61.menu.CPUFreq.10.build.f_cpu=10000000L + +esp32c61.menu.FlashMode.qio=QIO +esp32c61.menu.FlashMode.qio.build.flash_mode=dio +esp32c61.menu.FlashMode.qio.build.boot=qio +esp32c61.menu.FlashMode.dio=DIO +esp32c61.menu.FlashMode.dio.build.flash_mode=dio +esp32c61.menu.FlashMode.dio.build.boot=dio + +esp32c61.menu.FlashFreq.80=80MHz +esp32c61.menu.FlashFreq.80.build.flash_freq=80m +esp32c61.menu.FlashFreq.40=40MHz +esp32c61.menu.FlashFreq.40.build.flash_freq=40m + +esp32c61.menu.FlashSize.4M=4MB (32Mb) +esp32c61.menu.FlashSize.4M.build.flash_size=4MB +esp32c61.menu.FlashSize.8M=8MB (64Mb) +esp32c61.menu.FlashSize.8M.build.flash_size=8MB +esp32c61.menu.FlashSize.2M=2MB (16Mb) +esp32c61.menu.FlashSize.2M.build.flash_size=2MB + +esp32c61.menu.UploadSpeed.921600=921600 +esp32c61.menu.UploadSpeed.921600.upload.speed=921600 +esp32c61.menu.UploadSpeed.115200=115200 +esp32c61.menu.UploadSpeed.115200.upload.speed=115200 +esp32c61.menu.UploadSpeed.256000.windows=256000 +esp32c61.menu.UploadSpeed.256000.upload.speed=256000 +esp32c61.menu.UploadSpeed.230400.windows.upload.speed=256000 +esp32c61.menu.UploadSpeed.230400=230400 +esp32c61.menu.UploadSpeed.230400.upload.speed=230400 +esp32c61.menu.UploadSpeed.460800.linux=460800 +esp32c61.menu.UploadSpeed.460800.macosx=460800 +esp32c61.menu.UploadSpeed.460800.upload.speed=460800 +esp32c61.menu.UploadSpeed.512000.windows=512000 +esp32c61.menu.UploadSpeed.512000.upload.speed=512000 + +esp32c61.menu.DebugLevel.none=None +esp32c61.menu.DebugLevel.none.build.code_debug=0 +esp32c61.menu.DebugLevel.error=Error +esp32c61.menu.DebugLevel.error.build.code_debug=1 +esp32c61.menu.DebugLevel.warn=Warn +esp32c61.menu.DebugLevel.warn.build.code_debug=2 +esp32c61.menu.DebugLevel.info=Info +esp32c61.menu.DebugLevel.info.build.code_debug=3 +esp32c61.menu.DebugLevel.debug=Debug +esp32c61.menu.DebugLevel.debug.build.code_debug=4 +esp32c61.menu.DebugLevel.verbose=Verbose +esp32c61.menu.DebugLevel.verbose.build.code_debug=5 + +esp32c61.menu.EraseFlash.none=Disabled +esp32c61.menu.EraseFlash.none.upload.erase_cmd= +esp32c61.menu.EraseFlash.all=Enabled +esp32c61.menu.EraseFlash.all.upload.erase_cmd=-e + +############################################################## + esp32s3.name=ESP32S3 Dev Module esp32s3.bootloader.tool=esptool_py diff --git a/cores/esp32/Esp.cpp b/cores/esp32/Esp.cpp index 5f5a7a353e8..023afd80d8b 100644 --- a/cores/esp32/Esp.cpp +++ b/cores/esp32/Esp.cpp @@ -83,6 +83,9 @@ extern "C" { #elif CONFIG_IDF_TARGET_ESP32C5 #include "esp32c5/rom/spi_flash.h" #define ESP_FLASH_IMAGE_BASE 0x2000 // Esp32c5 is located at 0x2000 +#elif CONFIG_IDF_TARGET_ESP32C61 +#include "esp32c61/rom/spi_flash.h" +#define ESP_FLASH_IMAGE_BASE 0x0000 // Esp32c61 is located at 0x0000 #else #error Target CONFIG_IDF_TARGET is not supported #endif @@ -365,7 +368,7 @@ uint32_t EspClass::getFlashChipSpeed(void) { } FlashMode_t EspClass::getFlashChipMode(void) { -#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 +#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61 uint32_t spi_ctrl = REG_READ(PERIPHS_SPI_FLASH_CTRL); #elif CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 uint32_t spi_ctrl = REG_READ(DR_REG_SPI0_BASE + 0x8); @@ -449,6 +452,22 @@ uint32_t EspClass::magicFlashChipSpeed(uint8_t flashByte) { return 0; } +#elif CONFIG_IDF_TARGET_ESP32C61 + /* + FLASH_FREQUENCY = { + "80m": 0xF, + "40m": 0x0, + "20m": 0x2, + } +*/ + switch (flashByte & 0x0F) { + case 0xF: return (80_MHz); + case 0x0: return (40_MHz); + case 0x2: return (20_MHz); + default: // fail? + return 0; + } + #elif CONFIG_IDF_TARGET_ESP32H2 /* diff --git a/cores/esp32/HardwareSerial.h b/cores/esp32/HardwareSerial.h index 9a4eec5ccb4..7f843fef4c8 100644 --- a/cores/esp32/HardwareSerial.h +++ b/cores/esp32/HardwareSerial.h @@ -164,6 +164,8 @@ typedef enum { #define SOC_RX0 (gpio_num_t)38 #elif CONFIG_IDF_TARGET_ESP32C5 #define SOC_RX0 (gpio_num_t)12 +#elif CONFIG_IDF_TARGET_ESP32C61 +#define SOC_RX0 (gpio_num_t)10 #endif #endif @@ -182,7 +184,7 @@ typedef enum { #define SOC_TX0 (gpio_num_t)24 #elif CONFIG_IDF_TARGET_ESP32P4 #define SOC_TX0 (gpio_num_t)37 -#elif CONFIG_IDF_TARGET_ESP32C5 +#elif CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61 #define SOC_TX0 (gpio_num_t)11 #endif #endif @@ -209,6 +211,8 @@ typedef enum { #define RX1 (gpio_num_t)11 #elif CONFIG_IDF_TARGET_ESP32C5 #define RX1 (gpio_num_t)4 +#elif CONFIG_IDF_TARGET_ESP32C61 +#define RX1 (gpio_num_t)8 #endif #endif @@ -231,6 +235,8 @@ typedef enum { #define TX1 (gpio_num_t)10 #elif CONFIG_IDF_TARGET_ESP32C5 #define TX1 (gpio_num_t)5 +#elif CONFIG_IDF_TARGET_ESP32C61 +#define TX1 (gpio_num_t)29 #endif #endif #endif /* SOC_UART_HP_NUM > 1 */ diff --git a/cores/esp32/chip-debug-report.cpp b/cores/esp32/chip-debug-report.cpp index 753e7346775..f4f29a1e005 100644 --- a/cores/esp32/chip-debug-report.cpp +++ b/cores/esp32/chip-debug-report.cpp @@ -69,9 +69,8 @@ static void printPkgVersion(void) { #elif CONFIG_IDF_TARGET_ESP32P4 uint32_t pkg_ver = REG_GET_FIELD(EFUSE_RD_MAC_SYS_2_REG, EFUSE_PKG_VERSION); chip_report_printf("%lu", pkg_ver); -#elif CONFIG_IDF_TARGET_ESP32C5 - // ToDo: Update this line when EFUSE_PKG_VERSION is available again for ESP32-C5 - uint32_t pkg_ver = 0; //REG_GET_FIELD(EFUSE_RD_MAC_SYS2_REG, EFUSE_PKG_VERSION); +#elif CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61 + uint32_t pkg_ver = REG_GET_FIELD(EFUSE_RD_MAC_SYS2_REG, EFUSE_PKG_VERSION); chip_report_printf("%lu", pkg_ver); #else chip_report_printf("Unknown"); diff --git a/cores/esp32/esp32-hal-cpu.c b/cores/esp32/esp32-hal-cpu.c index e9113da4219..fc9e761b59d 100644 --- a/cores/esp32/esp32-hal-cpu.c +++ b/cores/esp32/esp32-hal-cpu.c @@ -19,8 +19,7 @@ #include "esp_attr.h" #include "esp_log.h" #include "soc/rtc.h" -#if !defined(CONFIG_IDF_TARGET_ESP32C2) && !defined(CONFIG_IDF_TARGET_ESP32C6) && !defined(CONFIG_IDF_TARGET_ESP32H2) && !defined(CONFIG_IDF_TARGET_ESP32P4) \ - && !defined(CONFIG_IDF_TARGET_ESP32C5) +#if defined(CONFIG_IDF_TARGET_ESP32) || defined(CONFIG_IDF_TARGET_ESP32S2) || defined(CONFIG_IDF_TARGET_ESP32S3) || defined(CONFIG_IDF_TARGET_ESP32C3) #include "soc/rtc_cntl_reg.h" #include "soc/syscon_reg.h" #endif @@ -35,24 +34,36 @@ #if CONFIG_IDF_TARGET_ESP32 // ESP32/PICO-D4 #include "xtensa_timer.h" #include "esp32/rom/rtc.h" +static const char *clock_source_names[] = { "XTAL", "PLL", "8.5M", "APLL" }; #elif CONFIG_IDF_TARGET_ESP32S2 #include "xtensa_timer.h" #include "esp32s2/rom/rtc.h" +static const char *clock_source_names[] = { "XTAL", "PLL", "8.5M", "APLL" }; #elif CONFIG_IDF_TARGET_ESP32S3 #include "xtensa_timer.h" #include "esp32s3/rom/rtc.h" +static const char *clock_source_names[] = { "XTAL", "PLL", "17.5M" }; #elif CONFIG_IDF_TARGET_ESP32C2 #include "esp32c2/rom/rtc.h" +static const char *clock_source_names[] = { "XTAL", "PLL", "17.5M" }; #elif CONFIG_IDF_TARGET_ESP32C3 #include "esp32c3/rom/rtc.h" +static const char *clock_source_names[] = { "XTAL", "PLL", "17.5M" }; #elif CONFIG_IDF_TARGET_ESP32C6 #include "esp32c6/rom/rtc.h" +static const char *clock_source_names[] = { "XTAL", "PLL", "17.5M" }; #elif CONFIG_IDF_TARGET_ESP32H2 #include "esp32h2/rom/rtc.h" +static const char *clock_source_names[] = { "XTAL", "PLL", "8.5M", "FLASH_PLL" }; #elif CONFIG_IDF_TARGET_ESP32P4 #include "esp32p4/rom/rtc.h" +static const char *clock_source_names[] = { "XTAL", "CPLL", "17.5M" }; #elif CONFIG_IDF_TARGET_ESP32C5 #include "esp32c5/rom/rtc.h" +static const char *clock_source_names[] = { "XTAL", "17.5M", "PLL_F160M", "PLL_F240M" }; +#elif CONFIG_IDF_TARGET_ESP32C61 +#include "esp32c61/rom/rtc.h" +static const char *clock_source_names[] = { "XTAL", "17.5M", "PLL_F160M" }; #else #error Target CONFIG_IDF_TARGET is not supported #endif @@ -182,77 +193,101 @@ static uint32_t calculateApb(rtc_cpu_freq_config_t *conf) { void esp_timer_impl_update_apb_freq(uint32_t apb_ticks_per_us); //private in IDF #endif -bool setCpuFrequencyMhz(uint32_t cpu_freq_mhz) { - rtc_cpu_freq_config_t conf, cconf; - uint32_t capb, apb; - //Get XTAL Frequency and calculate min CPU MHz -#if (!defined(CONFIG_IDF_TARGET_ESP32H2) && !defined(CONFIG_IDF_TARGET_ESP32P4) && !defined(CONFIG_IDF_TARGET_ESP32C5)) - rtc_xtal_freq_t xtal = rtc_clk_xtal_freq_get(); -#endif -#if CONFIG_IDF_TARGET_ESP32 - if (xtal > RTC_XTAL_FREQ_AUTO) { - if (xtal < RTC_XTAL_FREQ_40M) { - if (cpu_freq_mhz <= xtal && cpu_freq_mhz != xtal && cpu_freq_mhz != (xtal / 2)) { - log_e("Bad frequency: %u MHz! Options are: 240, 160, 80, %u and %u MHz", cpu_freq_mhz, xtal, xtal / 2); - return false; - } - } else if (cpu_freq_mhz <= xtal && cpu_freq_mhz != xtal && cpu_freq_mhz != (xtal / 2) && cpu_freq_mhz != (xtal / 4)) { - log_e("Bad frequency: %u MHz! Options are: 240, 160, 80, %u, %u and %u MHz", cpu_freq_mhz, xtal, xtal / 2, xtal / 4); - return false; - } +const char *getClockSourceName(uint8_t source) { + if (source < SOC_CPU_CLK_SRC_INVALID) { + return clock_source_names[source]; } + + return "Invalid"; +} + +const char *getSupportedCpuFrequencyMhz(uint8_t xtal) { + char *supported_frequencies = (char *)calloc(256, sizeof(char)); + int pos = 0; + +#if TARGET_CPU_FREQ_MAX_400 + // P4 does not support 400MHz yet + pos += snprintf(supported_frequencies + pos, 256 - pos, "360"); +#elif TARGET_CPU_FREQ_MAX_240 +#if CONFIG_IDF_TARGET_ESP32 + if (!REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_CPU_FREQ_RATED) || !REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_CPU_FREQ_LOW)) { + pos += snprintf(supported_frequencies + pos, 256 - pos, "160, 80"); + } else #endif -#if (!defined(CONFIG_IDF_TARGET_ESP32H2) && !defined(CONFIG_IDF_TARGET_ESP32P4) && !defined(CONFIG_IDF_TARGET_ESP32C5)) - if (cpu_freq_mhz > xtal && cpu_freq_mhz != 240 && cpu_freq_mhz != 160 && cpu_freq_mhz != 120 && cpu_freq_mhz != 80) { - if (xtal >= RTC_XTAL_FREQ_40M) { - log_e("Bad frequency: %u MHz! Options are: 240, 160, 120, 80, %u, %u and %u MHz", cpu_freq_mhz, xtal, xtal / 2, xtal / 4); - } else { - log_e("Bad frequency: %u MHz! Options are: 240, 160, 120, 80, %u and %u MHz", cpu_freq_mhz, xtal, xtal / 2); - } - return false; + { + pos += snprintf(supported_frequencies + pos, 256 - pos, "240, 160, 80"); } +#elif TARGET_CPU_FREQ_MAX_160 + pos += snprintf(supported_frequencies + pos, 256 - pos, "160, 120, 80"); +#elif TARGET_CPU_FREQ_MAX_120 + pos += snprintf(supported_frequencies + pos, 256 - pos, "120, 80"); +#elif TARGET_CPU_FREQ_MAX_96 + pos += snprintf(supported_frequencies + pos, 256 - pos, "96, 64, 48"); +#else + free(supported_frequencies); + return "Unknown"; #endif + + // Append xtal and its dividers only if xtal is nonzero + if (xtal != 0) { + // We'll show as: , , [, ] MHz + pos += snprintf(supported_frequencies + pos, 256 - pos, ", %u, %u", xtal, xtal / 2); + #if CONFIG_IDF_TARGET_ESP32 - //check if cpu supports the frequency - if (cpu_freq_mhz == 240) { - //Check if ESP32 is rated for a CPU frequency of 160MHz only - if (REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_CPU_FREQ_RATED) && REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_CPU_FREQ_LOW)) { - log_e("Can not switch to 240 MHz! Chip CPU frequency rated for 160MHz."); - cpu_freq_mhz = 160; + // Only append xtal/4 if it's > 0 and meaningful for higher-frequency chips (e.g., ESP32 40MHz/4=10) + if (xtal >= RTC_XTAL_FREQ_40M) { + pos += snprintf(supported_frequencies + pos, 256 - pos, ", %u", xtal / 4); } +#endif } + + pos += snprintf(supported_frequencies + pos, 256 - pos, " MHz"); + return supported_frequencies; +} + +bool setCpuFrequencyMhz(uint32_t cpu_freq_mhz) { + rtc_cpu_freq_config_t conf, cconf; + uint32_t capb, apb; + [[maybe_unused]] uint8_t xtal = 0; + + // ===== Get XTAL Frequency and validate input ===== +#if TARGET_HAS_XTAL_FREQ + xtal = (uint8_t)rtc_clk_xtal_freq_get(); #endif - //Get current CPU clock configuration + + // ===== Get current configuration and check if change is needed ===== rtc_clk_cpu_freq_get_config(&cconf); - //return if frequency has not changed if (cconf.freq_mhz == cpu_freq_mhz) { - return true; + return true; // Frequency already set } - //Get configuration for the new CPU frequency + + // ===== Get configuration for new frequency ===== if (!rtc_clk_cpu_freq_mhz_to_config(cpu_freq_mhz, &conf)) { - log_e("CPU clock could not be set to %u MHz", cpu_freq_mhz); + log_e("CPU clock could not be set to %u MHz. Supported frequencies: %s", cpu_freq_mhz, getSupportedCpuFrequencyMhz(xtal)); return false; } - //Current APB + + // ===== Calculate APB frequencies ===== capb = calculateApb(&cconf); - //New APB apb = calculateApb(&conf); - //Call peripheral functions before the APB change + // ===== Apply frequency change ===== if (apb_change_callbacks) { triggerApbChangeCallback(APB_BEFORE_CHANGE, capb, apb); } - //Make the frequency change + rtc_clk_cpu_freq_set_config_fast(&conf); -#if defined(CONFIG_IDF_TARGET_ESP32) || defined(CONFIG_IDF_TARGET_ESP32S2) || defined(CONFIG_IDF_TARGET_ESP32S3) || defined(CONFIG_IDF_TARGET_ESP32C3) + + // Update APB frequency for targets with dynamic APB +#if TARGET_HAS_DYNAMIC_APB if (capb != apb) { - //Update REF_TICK (uncomment if REF_TICK is different than 1MHz) - //if(conf.freq_mhz < 80){ - // ESP_REG(APB_CTRL_XTAL_TICK_CONF_REG) = conf.freq_mhz / (REF_CLK_FREQ / MHZ) - 1; + // Update REF_TICK (uncomment if REF_TICK is different than 1MHz) + // if (conf.freq_mhz < 80) { + // ESP_REG(APB_CTRL_XTAL_TICK_CONF_REG) = conf.freq_mhz / (REF_CLK_FREQ / MHZ) - 1; // } - //Update APB Freq REG rtc_clk_apb_freq_update(apb); - //Update esp_timer divisor + + // ESP32-specific: Update esp_timer divisor #if CONFIG_IDF_TARGET_ESP32 #if defined(LACT_MODULE) && defined(LACT_TICKS_PER_US) timer_ll_set_lact_clock_prescale(TIMER_LL_GET_HW(LACT_MODULE), apb / MHZ / LACT_TICKS_PER_US); @@ -262,34 +297,20 @@ bool setCpuFrequencyMhz(uint32_t cpu_freq_mhz) { #endif } #endif - //Update FreeRTOS Tick Divisor -#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2 + // Update FreeRTOS Tick Divisor for Xtensa targets +#if TARGET_HAS_XTENSA_TICK uint32_t fcpu = (conf.freq_mhz >= 80) ? (conf.freq_mhz * MHZ) : (apb); _xt_tick_divisor = fcpu / XT_TICK_PER_SEC; #endif - //Call peripheral functions after the APB change + if (apb_change_callbacks) { triggerApbChangeCallback(APB_AFTER_CHANGE, capb, apb); } -#if defined(SOC_CLK_APLL_SUPPORTED) && !defined(CONFIG_IDF_TARGET_ESP32P4) // APLL not yet supported in ESP32-P4 - log_d( - "%s: %u / %u = %u Mhz, APB: %u Hz", - (conf.source == SOC_CPU_CLK_SRC_PLL) ? "PLL" : ((conf.source == SOC_CPU_CLK_SRC_APLL) ? "APLL" : ((conf.source == SOC_CPU_CLK_SRC_XTAL) ? "XTAL" : "8M")), - conf.source_freq_mhz, conf.div, conf.freq_mhz, apb - ); -#elif defined(CONFIG_IDF_TARGET_ESP32C5) - log_d( - "%s: %u / %u = %u Mhz, APB: %u Hz", - (conf.source == SOC_CPU_CLK_SRC_PLL_F240M || conf.source == SOC_CPU_CLK_SRC_PLL_F160M) ? "PLL" : ((conf.source == SOC_CPU_CLK_SRC_XTAL) ? "XTAL" : "8M"), - conf.source_freq_mhz, conf.div, conf.freq_mhz, apb - ); -#else - log_d( - "%s: %u / %u = %u Mhz, APB: %u Hz", (conf.source == SOC_CPU_CLK_SRC_PLL) ? "PLL" : ((conf.source == SOC_CPU_CLK_SRC_XTAL) ? "XTAL" : "17.5M"), - conf.source_freq_mhz, conf.div, conf.freq_mhz, apb - ); -#endif + + // ===== Debug logging ===== + log_d("%s: %u / %u = %u Mhz, APB: %u Hz", getClockSourceName(conf.source), conf.source_freq_mhz, conf.div, conf.freq_mhz, apb); + return true; } diff --git a/cores/esp32/esp32-hal-cpu.h b/cores/esp32/esp32-hal-cpu.h index 59806b460ae..dfae10678a1 100644 --- a/cores/esp32/esp32-hal-cpu.h +++ b/cores/esp32/esp32-hal-cpu.h @@ -23,6 +23,72 @@ extern "C" { #include #include +#include "sdkconfig.h" +#include "soc/soc_caps.h" + +// When adding a new target, update the appropriate group(s) below + +// Targets that support XTAL frequency queries via rtc_clk_xtal_freq_get() +#if (!defined(CONFIG_IDF_TARGET_ESP32C5) && !defined(CONFIG_IDF_TARGET_ESP32P4)) +#define TARGET_HAS_XTAL_FREQ 1 +#else +#define TARGET_HAS_XTAL_FREQ 0 +#endif + +// Targets that need dynamic APB frequency updates via rtc_clk_apb_freq_update() +#if (defined(CONFIG_IDF_TARGET_ESP32) || defined(CONFIG_IDF_TARGET_ESP32S2) || defined(CONFIG_IDF_TARGET_ESP32S3) || defined(CONFIG_IDF_TARGET_ESP32C3)) +#define TARGET_HAS_DYNAMIC_APB 1 +#else +#define TARGET_HAS_DYNAMIC_APB 0 +#endif + +// Xtensa architecture targets that need FreeRTOS tick divisor updates +#if (defined(CONFIG_IDF_TARGET_ESP32) || defined(CONFIG_IDF_TARGET_ESP32S2)) +#define TARGET_HAS_XTENSA_TICK 1 +#else +#define TARGET_HAS_XTENSA_TICK 0 +#endif + +// Targets with APLL support (uses IDF SOC capability macro) +// Note: ESP32-P4 APLL support is not yet fully implemented in IDF +#if (defined(SOC_CLK_APLL_SUPPORTED) && !defined(CONFIG_IDF_TARGET_ESP32P4)) +#define TARGET_HAS_APLL 1 +#else +#define TARGET_HAS_APLL 0 +#endif + +// Targets grouped by maximum CPU frequency support + +#if (defined(CONFIG_IDF_TARGET_ESP32P4)) +#define TARGET_CPU_FREQ_MAX_400 1 +#else +#define TARGET_CPU_FREQ_MAX_400 0 +#endif + +#if (defined(CONFIG_IDF_TARGET_ESP32) || defined(CONFIG_IDF_TARGET_ESP32C5) || defined(CONFIG_IDF_TARGET_ESP32S2) || defined(CONFIG_IDF_TARGET_ESP32S3)) +#define TARGET_CPU_FREQ_MAX_240 1 +#else +#define TARGET_CPU_FREQ_MAX_240 0 +#endif + +#if (defined(CONFIG_IDF_TARGET_ESP32C3) || defined(CONFIG_IDF_TARGET_ESP32C6) || defined(CONFIG_IDF_TARGET_ESP32C61)) +#define TARGET_CPU_FREQ_MAX_160 1 +#else +#define TARGET_CPU_FREQ_MAX_160 0 +#endif + +#if (defined(CONFIG_IDF_TARGET_ESP32C2)) +#define TARGET_CPU_FREQ_MAX_120 1 +#else +#define TARGET_CPU_FREQ_MAX_120 0 +#endif + +#if (defined(CONFIG_IDF_TARGET_ESP32H2)) +#define TARGET_CPU_FREQ_MAX_96 1 +#else +#define TARGET_CPU_FREQ_MAX_96 0 +#endif + typedef enum { APB_BEFORE_CHANGE, APB_AFTER_CHANGE @@ -40,6 +106,8 @@ bool removeApbChangeCallback(void *arg, apb_change_cb_t cb); // 24, 12 <<< For 24MHz XTAL bool setCpuFrequencyMhz(uint32_t cpu_freq_mhz); +const char *getSupportedCpuFrequencyMhz(uint8_t xtal); +const char *getClockSourceName(uint8_t source); uint32_t getCpuFrequencyMhz(); // In MHz uint32_t getXtalFrequencyMhz(); // In MHz uint32_t getApbFrequency(); // In Hz diff --git a/cores/esp32/esp32-hal-gpio.c b/cores/esp32/esp32-hal-gpio.c index 197f789d94d..1b0f21a338d 100644 --- a/cores/esp32/esp32-hal-gpio.c +++ b/cores/esp32/esp32-hal-gpio.c @@ -131,7 +131,11 @@ extern void ARDUINO_ISR_ATTR __pinMode(uint8_t pin, uint8_t mode) { .mode = GPIO_MODE_DISABLE, /*!< GPIO mode: set input/output mode */ .pull_up_en = GPIO_PULLUP_DISABLE, /*!< GPIO pull-up */ .pull_down_en = GPIO_PULLDOWN_DISABLE, /*!< GPIO pull-down */ +#ifndef CONFIG_IDF_TARGET_ESP32C61 .intr_type = gpiohal.dev->pin[pin].int_type /*!< GPIO interrupt type - previously set */ +#else + .intr_type = gpiohal.dev->pinn[pin].pinn_int_type /*!< GPIO interrupt type - previously set */ +#endif }; if (mode < 0x20) { //io conf.mode = mode & (INPUT | OUTPUT); diff --git a/cores/esp32/esp32-hal-i2c-slave.c b/cores/esp32/esp32-hal-i2c-slave.c index 1f23b7832f7..9589995c2c3 100644 --- a/cores/esp32/esp32-hal-i2c-slave.c +++ b/cores/esp32/esp32-hal-i2c-slave.c @@ -44,7 +44,7 @@ #include "soc/periph_defs.h" #include "hal/i2c_ll.h" #include "hal/i2c_types.h" -#ifndef CONFIG_IDF_TARGET_ESP32C5 +#if !defined(CONFIG_IDF_TARGET_ESP32C5) && !defined(CONFIG_IDF_TARGET_ESP32C61) #include "hal/clk_gate_ll.h" #endif #include "esp32-hal-log.h" @@ -328,7 +328,13 @@ esp_err_t i2cSlaveInit(uint8_t num, int sda, int scl, uint16_t slaveID, uint32_t frequency = 100000L; } frequency = (frequency * 5) / 4; -#if !defined(CONFIG_IDF_TARGET_ESP32P4) && !defined(CONFIG_IDF_TARGET_ESP32C5) +#if CONFIG_IDF_TARGET_ESP32 || \ + CONFIG_IDF_TARGET_ESP32C2 || \ + CONFIG_IDF_TARGET_ESP32C3 || \ + CONFIG_IDF_TARGET_ESP32C6 || \ + CONFIG_IDF_TARGET_ESP32H2 || \ + CONFIG_IDF_TARGET_ESP32S2 || \ + CONFIG_IDF_TARGET_ESP32S3 if (i2c->num == 0) { periph_ll_enable_clk_clear_rst(PERIPH_I2C0_MODULE); #if SOC_HP_I2C_NUM > 1 diff --git a/cores/esp32/esp32-hal-matrix.c b/cores/esp32/esp32-hal-matrix.c index 0d81e979f2b..f609d9e1487 100644 --- a/cores/esp32/esp32-hal-matrix.c +++ b/cores/esp32/esp32-hal-matrix.c @@ -36,6 +36,8 @@ #include "esp32p4/rom/gpio.h" #elif CONFIG_IDF_TARGET_ESP32C5 #include "esp32c5/rom/gpio.h" +#elif CONFIG_IDF_TARGET_ESP32C61 +#include "esp32c61/rom/gpio.h" #else #error Target CONFIG_IDF_TARGET is not supported #endif diff --git a/cores/esp32/esp32-hal-misc.c b/cores/esp32/esp32-hal-misc.c index 41e2cf71543..f0195ed1acf 100644 --- a/cores/esp32/esp32-hal-misc.c +++ b/cores/esp32/esp32-hal-misc.c @@ -30,8 +30,7 @@ #endif #include #include "soc/rtc.h" -#if !defined(CONFIG_IDF_TARGET_ESP32C2) && !defined(CONFIG_IDF_TARGET_ESP32C6) && !defined(CONFIG_IDF_TARGET_ESP32H2) && !defined(CONFIG_IDF_TARGET_ESP32P4) \ - && !defined(CONFIG_IDF_TARGET_ESP32C5) +#if defined(CONFIG_IDF_TARGET_ESP32) || defined(CONFIG_IDF_TARGET_ESP32C3) || defined(CONFIG_IDF_TARGET_ESP32S2) || defined(CONFIG_IDF_TARGET_ESP32S3) #include "soc/rtc_cntl_reg.h" #include "soc/syscon_reg.h" #endif @@ -59,7 +58,8 @@ #include "esp32p4/rom/rtc.h" #elif CONFIG_IDF_TARGET_ESP32C5 #include "esp32c5/rom/rtc.h" - +#elif CONFIG_IDF_TARGET_ESP32C61 +#include "esp32c61/rom/rtc.h" #else #error Target CONFIG_IDF_TARGET is not supported #endif diff --git a/cores/esp32/esp32-hal-spi.c b/cores/esp32/esp32-hal-spi.c index 0555dfae095..378ae587858 100644 --- a/cores/esp32/esp32-hal-spi.c +++ b/cores/esp32/esp32-hal-spi.c @@ -26,7 +26,7 @@ #include "soc/io_mux_reg.h" #include "soc/gpio_sig_map.h" #include "soc/rtc.h" -#ifndef CONFIG_IDF_TARGET_ESP32C5 +#if !defined(CONFIG_IDF_TARGET_ESP32C5) && !defined(CONFIG_IDF_TARGET_ESP32C61) #include "hal/clk_gate_ll.h" #endif #include "esp32-hal-periman.h" @@ -66,6 +66,9 @@ #elif CONFIG_IDF_TARGET_ESP32C5 #include "esp32c5/rom/ets_sys.h" #include "esp32c5/rom/gpio.h" +#elif CONFIG_IDF_TARGET_ESP32C61 +#include "esp32c61/rom/ets_sys.h" +#include "esp32c61/rom/gpio.h" #else #error Target CONFIG_IDF_TARGET is not supported #endif @@ -125,18 +128,7 @@ struct spi_struct_t { #define SPI_SS_IDX(p, n) ((p == 0) ? SPI_FSPI_SS_IDX(n) : ((p == 1) ? SPI_HSPI_SS_IDX(n) : 0)) -#elif CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C5 -// ESP32C3 -#define SPI_COUNT (1) - -#define SPI_CLK_IDX(p) FSPICLK_OUT_IDX -#define SPI_MISO_IDX(p) FSPIQ_OUT_IDX -#define SPI_MOSI_IDX(p) FSPID_IN_IDX - -#define SPI_SPI_SS_IDX(n) ((n == 0) ? FSPICS0_OUT_IDX : ((n == 1) ? FSPICS1_OUT_IDX : ((n == 2) ? FSPICS2_OUT_IDX : FSPICS0_OUT_IDX))) -#define SPI_SS_IDX(p, n) SPI_SPI_SS_IDX(n) - -#else +#elif CONFIG_IDF_TARGET_ESP32 // ESP32 #define SPI_COUNT (4) @@ -149,6 +141,17 @@ struct spi_struct_t { #define SPI_VSPI_SS_IDX(n) ((n == 0) ? VSPICS0_OUT_IDX : ((n == 1) ? VSPICS1_OUT_IDX : ((n == 2) ? VSPICS2_OUT_IDX : VSPICS0_OUT_IDX))) #define SPI_SS_IDX(p, n) ((p == 0) ? SPI_SPI_SS_IDX(n) : ((p == 1) ? SPI_SPI_SS_IDX(n) : ((p == 2) ? SPI_HSPI_SS_IDX(n) : ((p == 3) ? SPI_VSPI_SS_IDX(n) : 0)))) +#else +// ESP32C2, C3, C5, C6, C61, H2 +#define SPI_COUNT (1) + +#define SPI_CLK_IDX(p) FSPICLK_OUT_IDX +#define SPI_MISO_IDX(p) FSPIQ_OUT_IDX +#define SPI_MOSI_IDX(p) FSPID_IN_IDX + +#define SPI_SPI_SS_IDX(n) ((n == 0) ? FSPICS0_OUT_IDX : ((n == 1) ? FSPICS1_OUT_IDX : ((n == 2) ? FSPICS2_OUT_IDX : FSPICS0_OUT_IDX))) +#define SPI_SS_IDX(p, n) SPI_SPI_SS_IDX(n) + #endif #if CONFIG_DISABLE_HAL_LOCKS @@ -159,17 +162,13 @@ static spi_t _spi_bus_array[] = { #if CONFIG_IDF_TARGET_ESP32S2 ||CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32P4 {(volatile spi_dev_t *)(DR_REG_SPI2_BASE), 0, -1, -1, -1, -1, false}, {(volatile spi_dev_t *)(DR_REG_SPI3_BASE), 1, -1, -1, -1, -1, false} -#elif CONFIG_IDF_TARGET_ESP32C2 - {(volatile spi_dev_t *)(DR_REG_SPI2_BASE), 0, -1, -1, -1, -1, false} -#elif CONFIG_IDF_TARGET_ESP32C3 - {(volatile spi_dev_t *)(DR_REG_SPI2_BASE), 0, -1, -1, -1, -1, false} -#elif CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C5 - {(spi_dev_t *)(DR_REG_SPI2_BASE), 0, -1, -1, -1, -1, false} -#else +#elif CONFIG_IDF_TARGET_ESP32 {(volatile spi_dev_t *)(DR_REG_SPI0_BASE), 0, -1, -1, -1, -1, false}, {(volatile spi_dev_t *)(DR_REG_SPI1_BASE), 1, -1, -1, -1, -1, false}, {(volatile spi_dev_t *)(DR_REG_SPI2_BASE), 2, -1, -1, -1, -1, false}, {(volatile spi_dev_t *)(DR_REG_SPI3_BASE), 3, -1, -1, -1, -1, false} +#else // ESP32C2, C3, C5, C6, C61, H2 + {(volatile spi_dev_t *)(DR_REG_SPI2_BASE), 0, -1, -1, -1, -1, false} #endif }; // clang-format on @@ -179,22 +178,21 @@ static spi_t _spi_bus_array[] = { } while (xSemaphoreTake(spi->lock, portMAX_DELAY) != pdPASS) #define SPI_MUTEX_UNLOCK() xSemaphoreGive(spi->lock) +// clang-format off static spi_t _spi_bus_array[] = { #if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32P4 - {(volatile spi_dev_t *)(DR_REG_SPI2_BASE), NULL, 0, -1, -1, -1, -1, false}, {(volatile spi_dev_t *)(DR_REG_SPI3_BASE), NULL, 1, -1, -1, -1, -1, false} -#elif CONFIG_IDF_TARGET_ESP32C2 - {(volatile spi_dev_t *)(DR_REG_SPI2_BASE), NULL, 0, -1, -1, -1, -1, false} -#elif CONFIG_IDF_TARGET_ESP32C3 - {(volatile spi_dev_t *)(DR_REG_SPI2_BASE), NULL, 0, -1, -1, -1, -1, false} -#elif CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C5 - {(spi_dev_t *)(DR_REG_SPI2_BASE), NULL, 0, -1, -1, -1, -1, false} -#else + {(volatile spi_dev_t *)(DR_REG_SPI2_BASE), NULL, 0, -1, -1, -1, -1, false}, + {(volatile spi_dev_t *)(DR_REG_SPI3_BASE), NULL, 1, -1, -1, -1, -1, false} +#elif CONFIG_IDF_TARGET_ESP32 {(volatile spi_dev_t *)(DR_REG_SPI0_BASE), NULL, 0, -1, -1, -1, -1, false}, {(volatile spi_dev_t *)(DR_REG_SPI1_BASE), NULL, 1, -1, -1, -1, -1, false}, {(volatile spi_dev_t *)(DR_REG_SPI2_BASE), NULL, 2, -1, -1, -1, -1, false}, {(volatile spi_dev_t *)(DR_REG_SPI3_BASE), NULL, 3, -1, -1, -1, -1, false} +#else // ESP32C2, C3, C5, C6, C61, H2 + {(volatile spi_dev_t *)(DR_REG_SPI2_BASE), NULL, 0, -1, -1, -1, -1, false} #endif }; +// clang-format on #endif static bool spiDetachBus(void *bus) { @@ -701,7 +699,7 @@ spi_t *spiStartBus(uint8_t spi_num, uint32_t clockDiv, uint8_t dataMode, uint8_t spi->dev->clk_gate.clk_en = 1; spi->dev->clk_gate.mst_clk_sel = 1; spi->dev->clk_gate.mst_clk_active = 1; -#if defined(CONFIG_IDF_TARGET_ESP32S3) || defined(CONFIG_IDF_TARGET_ESP32C2) || defined(CONFIG_IDF_TARGET_ESP32C3) +#if defined(CONFIG_IDF_TARGET_ESP32C2) || defined(CONFIG_IDF_TARGET_ESP32C3) || defined(CONFIG_IDF_TARGET_ESP32S3) spi->dev->dma_conf.tx_seg_trans_clr_en = 1; spi->dev->dma_conf.rx_seg_trans_clr_en = 1; spi->dev->dma_conf.dma_seg_trans_en = 0; @@ -712,10 +710,10 @@ spi_t *spiStartBus(uint8_t spi_num, uint32_t clockDiv, uint8_t dataMode, uint8_t spi->dev->user.doutdin = 1; int i; for (i = 0; i < 16; i++) { -#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 - spi->dev->data_buf[i].val = 0x00000000; -#else +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 spi->dev->data_buf[i] = 0x00000000; +#else + spi->dev->data_buf[i].val = 0x00000000; #endif } SPI_MUTEX_UNLOCK(); @@ -760,10 +758,10 @@ void spiWrite(spi_t *spi, const uint32_t *data, uint8_t len) { spi->dev->miso_dlen.usr_miso_dbitlen = 0; #endif for (i = 0; i < len; i++) { -#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 - spi->dev->data_buf[i].val = data[i]; -#else +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 spi->dev->data_buf[i] = data[i]; +#else + spi->dev->data_buf[i].val = data[i]; #endif } #if !defined(CONFIG_IDF_TARGET_ESP32) && !defined(CONFIG_IDF_TARGET_ESP32S2) @@ -787,10 +785,10 @@ void spiTransfer(spi_t *spi, uint32_t *data, uint8_t len) { spi->dev->mosi_dlen.usr_mosi_dbitlen = (len * 32) - 1; spi->dev->miso_dlen.usr_miso_dbitlen = (len * 32) - 1; for (i = 0; i < len; i++) { -#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 - spi->dev->data_buf[i].val = data[i]; -#else +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 spi->dev->data_buf[i] = data[i]; +#else + spi->dev->data_buf[i].val = data[i]; #endif } #if !defined(CONFIG_IDF_TARGET_ESP32) && !defined(CONFIG_IDF_TARGET_ESP32S2) @@ -800,10 +798,10 @@ void spiTransfer(spi_t *spi, uint32_t *data, uint8_t len) { spi->dev->cmd.usr = 1; while (spi->dev->cmd.usr); for (i = 0; i < len; i++) { -#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 - data[i] = spi->dev->data_buf[i].val; -#else +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 data[i] = spi->dev->data_buf[i]; +#else + data[i] = spi->dev->data_buf[i].val; #endif } SPI_MUTEX_UNLOCK(); @@ -818,10 +816,10 @@ void spiWriteByte(spi_t *spi, uint8_t data) { #if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32 spi->dev->miso_dlen.usr_miso_dbitlen = 0; #endif -#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 - spi->dev->data_buf[0].val = data; -#else +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 spi->dev->data_buf[0] = data; +#else + spi->dev->data_buf[0].val = data; #endif #if !defined(CONFIG_IDF_TARGET_ESP32) && !defined(CONFIG_IDF_TARGET_ESP32S2) @@ -840,10 +838,10 @@ uint8_t spiTransferByte(spi_t *spi, uint8_t data) { SPI_MUTEX_LOCK(); spi->dev->mosi_dlen.usr_mosi_dbitlen = 7; spi->dev->miso_dlen.usr_miso_dbitlen = 7; -#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 - spi->dev->data_buf[0].val = data; -#else +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 spi->dev->data_buf[0] = data; +#else + spi->dev->data_buf[0].val = data; #endif #if !defined(CONFIG_IDF_TARGET_ESP32) && !defined(CONFIG_IDF_TARGET_ESP32S2) spi->dev->cmd.update = 1; @@ -851,10 +849,10 @@ uint8_t spiTransferByte(spi_t *spi, uint8_t data) { #endif spi->dev->cmd.usr = 1; while (spi->dev->cmd.usr); -#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 - data = spi->dev->data_buf[0].val & 0xFF; -#else +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 data = spi->dev->data_buf[0] & 0xFF; +#else + data = spi->dev->data_buf[0].val & 0xFF; #endif SPI_MUTEX_UNLOCK(); return data; @@ -881,10 +879,10 @@ void spiWriteWord(spi_t *spi, uint16_t data) { #if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32 spi->dev->miso_dlen.usr_miso_dbitlen = 0; #endif -#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 - spi->dev->data_buf[0].val = data; -#else +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 spi->dev->data_buf[0] = data; +#else + spi->dev->data_buf[0].val = data; #endif #if !defined(CONFIG_IDF_TARGET_ESP32) && !defined(CONFIG_IDF_TARGET_ESP32S2) spi->dev->cmd.update = 1; @@ -905,10 +903,10 @@ uint16_t spiTransferWord(spi_t *spi, uint16_t data) { SPI_MUTEX_LOCK(); spi->dev->mosi_dlen.usr_mosi_dbitlen = 15; spi->dev->miso_dlen.usr_miso_dbitlen = 15; -#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 - spi->dev->data_buf[0].val = data; -#else +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 spi->dev->data_buf[0] = data; +#else + spi->dev->data_buf[0].val = data; #endif #if !defined(CONFIG_IDF_TARGET_ESP32) && !defined(CONFIG_IDF_TARGET_ESP32S2) spi->dev->cmd.update = 1; @@ -916,10 +914,10 @@ uint16_t spiTransferWord(spi_t *spi, uint16_t data) { #endif spi->dev->cmd.usr = 1; while (spi->dev->cmd.usr); -#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 - data = spi->dev->data_buf[0].val; -#else +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 data = spi->dev->data_buf[0]; +#else + data = spi->dev->data_buf[0].val; #endif SPI_MUTEX_UNLOCK(); if (!spi->dev->ctrl.rd_bit_order) { @@ -940,10 +938,10 @@ void spiWriteLong(spi_t *spi, uint32_t data) { #if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32 spi->dev->miso_dlen.usr_miso_dbitlen = 0; #endif -#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 - spi->dev->data_buf[0].val = data; -#else +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 spi->dev->data_buf[0] = data; +#else + spi->dev->data_buf[0].val = data; #endif #if !defined(CONFIG_IDF_TARGET_ESP32) && !defined(CONFIG_IDF_TARGET_ESP32S2) spi->dev->cmd.update = 1; @@ -964,10 +962,10 @@ uint32_t spiTransferLong(spi_t *spi, uint32_t data) { SPI_MUTEX_LOCK(); spi->dev->mosi_dlen.usr_mosi_dbitlen = 31; spi->dev->miso_dlen.usr_miso_dbitlen = 31; -#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 - spi->dev->data_buf[0].val = data; -#else +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 spi->dev->data_buf[0] = data; +#else + spi->dev->data_buf[0].val = data; #endif #if !defined(CONFIG_IDF_TARGET_ESP32) && !defined(CONFIG_IDF_TARGET_ESP32S2) spi->dev->cmd.update = 1; @@ -975,10 +973,10 @@ uint32_t spiTransferLong(spi_t *spi, uint32_t data) { #endif spi->dev->cmd.usr = 1; while (spi->dev->cmd.usr); -#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 - data = spi->dev->data_buf[0].val; -#else +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 data = spi->dev->data_buf[0]; +#else + data = spi->dev->data_buf[0].val; #endif SPI_MUTEX_UNLOCK(); if (!spi->dev->ctrl.rd_bit_order) { @@ -1014,10 +1012,10 @@ static void __spiTransferBytes(spi_t *spi, const uint8_t *data, uint8_t *out, ui spi->dev->miso_dlen.usr_miso_dbitlen = ((bytes * 8) - 1); for (i = 0; i < words; i++) { -#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 - spi->dev->data_buf[i].val = wordsBuf[i]; //copy buffer to spi fifo -#else +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 spi->dev->data_buf[i] = wordsBuf[i]; //copy buffer to spi fifo +#else + spi->dev->data_buf[i].val = wordsBuf[i]; //copy buffer to spi fifo #endif } @@ -1031,10 +1029,10 @@ static void __spiTransferBytes(spi_t *spi, const uint8_t *data, uint8_t *out, ui if (out) { for (i = 0; i < words; i++) { -#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 - wordsBuf[i] = spi->dev->data_buf[i].val; //copy spi fifo to buffer -#else +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 wordsBuf[i] = spi->dev->data_buf[i]; //copy spi fifo to buffer +#else + wordsBuf[i] = spi->dev->data_buf[i].val; //copy spi fifo to buffer #endif } memcpy(out, bytesBuf, bytes); //copy buffer to output @@ -1172,10 +1170,10 @@ void ARDUINO_ISR_ATTR spiWriteByteNL(spi_t *spi, uint8_t data) { #if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32 spi->dev->miso_dlen.usr_miso_dbitlen = 0; #endif -#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 - spi->dev->data_buf[0].val = data; -#else +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 spi->dev->data_buf[0] = data; +#else + spi->dev->data_buf[0].val = data; #endif #if !defined(CONFIG_IDF_TARGET_ESP32) && !defined(CONFIG_IDF_TARGET_ESP32S2) spi->dev->cmd.update = 1; @@ -1191,10 +1189,10 @@ uint8_t spiTransferByteNL(spi_t *spi, uint8_t data) { } spi->dev->mosi_dlen.usr_mosi_dbitlen = 7; spi->dev->miso_dlen.usr_miso_dbitlen = 7; -#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 - spi->dev->data_buf[0].val = data; -#else +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 spi->dev->data_buf[0] = data; +#else + spi->dev->data_buf[0].val = data; #endif #if !defined(CONFIG_IDF_TARGET_ESP32) && !defined(CONFIG_IDF_TARGET_ESP32S2) spi->dev->cmd.update = 1; @@ -1202,10 +1200,10 @@ uint8_t spiTransferByteNL(spi_t *spi, uint8_t data) { #endif spi->dev->cmd.usr = 1; while (spi->dev->cmd.usr); -#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 - data = spi->dev->data_buf[0].val & 0xFF; -#else +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 data = spi->dev->data_buf[0] & 0xFF; +#else + data = spi->dev->data_buf[0].val & 0xFF; #endif return data; } @@ -1221,10 +1219,10 @@ void ARDUINO_ISR_ATTR spiWriteShortNL(spi_t *spi, uint16_t data) { #if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32 spi->dev->miso_dlen.usr_miso_dbitlen = 0; #endif -#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 - spi->dev->data_buf[0].val = data; -#else +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 spi->dev->data_buf[0] = data; +#else + spi->dev->data_buf[0].val = data; #endif #if !defined(CONFIG_IDF_TARGET_ESP32) && !defined(CONFIG_IDF_TARGET_ESP32S2) spi->dev->cmd.update = 1; @@ -1243,10 +1241,10 @@ uint16_t spiTransferShortNL(spi_t *spi, uint16_t data) { } spi->dev->mosi_dlen.usr_mosi_dbitlen = 15; spi->dev->miso_dlen.usr_miso_dbitlen = 15; -#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 - spi->dev->data_buf[0].val = data; -#else +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 spi->dev->data_buf[0] = data; +#else + spi->dev->data_buf[0].val = data; #endif #if !defined(CONFIG_IDF_TARGET_ESP32) && !defined(CONFIG_IDF_TARGET_ESP32S2) spi->dev->cmd.update = 1; @@ -1254,10 +1252,10 @@ uint16_t spiTransferShortNL(spi_t *spi, uint16_t data) { #endif spi->dev->cmd.usr = 1; while (spi->dev->cmd.usr); -#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 - data = spi->dev->data_buf[0].val & 0xFFFF; -#else +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 data = spi->dev->data_buf[0] & 0xFFFF; +#else + data = spi->dev->data_buf[0].val & 0xFFFF; #endif if (!spi->dev->ctrl.rd_bit_order) { MSB_16_SET(data, data); @@ -1276,10 +1274,10 @@ void ARDUINO_ISR_ATTR spiWriteLongNL(spi_t *spi, uint32_t data) { #if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32 spi->dev->miso_dlen.usr_miso_dbitlen = 0; #endif -#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 - spi->dev->data_buf[0].val = data; -#else +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 spi->dev->data_buf[0] = data; +#else + spi->dev->data_buf[0].val = data; #endif #if !defined(CONFIG_IDF_TARGET_ESP32) && !defined(CONFIG_IDF_TARGET_ESP32S2) spi->dev->cmd.update = 1; @@ -1298,10 +1296,10 @@ uint32_t spiTransferLongNL(spi_t *spi, uint32_t data) { } spi->dev->mosi_dlen.usr_mosi_dbitlen = 31; spi->dev->miso_dlen.usr_miso_dbitlen = 31; -#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 - spi->dev->data_buf[0].val = data; -#else +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 spi->dev->data_buf[0] = data; +#else + spi->dev->data_buf[0].val = data; #endif #if !defined(CONFIG_IDF_TARGET_ESP32) && !defined(CONFIG_IDF_TARGET_ESP32S2) spi->dev->cmd.update = 1; @@ -1309,10 +1307,10 @@ uint32_t spiTransferLongNL(spi_t *spi, uint32_t data) { #endif spi->dev->cmd.usr = 1; while (spi->dev->cmd.usr); -#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 - data = spi->dev->data_buf[0].val; -#else +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 data = spi->dev->data_buf[0]; +#else + data = spi->dev->data_buf[0].val; #endif if (!spi->dev->ctrl.rd_bit_order) { MSB_32_SET(data, data); @@ -1340,10 +1338,10 @@ void spiWriteNL(spi_t *spi, const void *data_in, uint32_t len) { spi->dev->miso_dlen.usr_miso_dbitlen = 0; #endif for (size_t i = 0; i < c_longs; i++) { -#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 - spi->dev->data_buf[i].val = data[i]; -#else +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 spi->dev->data_buf[i] = data[i]; +#else + spi->dev->data_buf[i].val = data[i]; #endif } #if !defined(CONFIG_IDF_TARGET_ESP32) && !defined(CONFIG_IDF_TARGET_ESP32S2) @@ -1379,18 +1377,18 @@ void spiTransferBytesNL(spi_t *spi, const void *data_in, uint8_t *data_out, uint spi->dev->miso_dlen.usr_miso_dbitlen = (c_len * 8) - 1; if (data) { for (size_t i = 0; i < c_longs; i++) { -#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 - spi->dev->data_buf[i].val = data[i]; -#else +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 spi->dev->data_buf[i] = data[i]; +#else + spi->dev->data_buf[i].val = data[i]; #endif } } else { for (size_t i = 0; i < c_longs; i++) { -#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 - spi->dev->data_buf[i].val = 0xFFFFFFFF; -#else +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 spi->dev->data_buf[i] = 0xFFFFFFFF; +#else + spi->dev->data_buf[i].val = 0xFFFFFFFF; #endif } } @@ -1403,16 +1401,16 @@ void spiTransferBytesNL(spi_t *spi, const void *data_in, uint8_t *data_out, uint if (result) { if (c_len & 3) { for (size_t i = 0; i < (c_longs - 1); i++) { -#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 - result[i] = spi->dev->data_buf[i].val; -#else +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 result[i] = spi->dev->data_buf[i]; +#else + result[i] = spi->dev->data_buf[i].val; #endif } -#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 - uint32_t last_data = spi->dev->data_buf[c_longs - 1].val; -#else +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 uint32_t last_data = spi->dev->data_buf[c_longs - 1]; +#else + uint32_t last_data = spi->dev->data_buf[c_longs - 1].val; #endif uint8_t *last_out8 = (uint8_t *)&result[c_longs - 1]; uint8_t *last_data8 = (uint8_t *)&last_data; @@ -1421,10 +1419,10 @@ void spiTransferBytesNL(spi_t *spi, const void *data_in, uint8_t *data_out, uint } } else { for (size_t i = 0; i < c_longs; i++) { -#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 - result[i] = spi->dev->data_buf[i].val; -#else +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 result[i] = spi->dev->data_buf[i]; +#else + result[i] = spi->dev->data_buf[i].val; #endif } } @@ -1463,10 +1461,10 @@ void spiTransferBitsNL(spi_t *spi, uint32_t data, uint32_t *out, uint8_t bits) { spi->dev->mosi_dlen.usr_mosi_dbitlen = (bits - 1); spi->dev->miso_dlen.usr_miso_dbitlen = (bits - 1); -#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 - spi->dev->data_buf[0].val = data; -#else +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 spi->dev->data_buf[0] = data; +#else + spi->dev->data_buf[0].val = data; #endif #if !defined(CONFIG_IDF_TARGET_ESP32) && !defined(CONFIG_IDF_TARGET_ESP32S2) spi->dev->cmd.update = 1; @@ -1474,10 +1472,10 @@ void spiTransferBitsNL(spi_t *spi, uint32_t data, uint32_t *out, uint8_t bits) { #endif spi->dev->cmd.usr = 1; while (spi->dev->cmd.usr); -#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 - data = spi->dev->data_buf[0].val; -#else +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 data = spi->dev->data_buf[0]; +#else + data = spi->dev->data_buf[0].val; #endif if (out) { *out = data; @@ -1515,30 +1513,30 @@ void ARDUINO_ISR_ATTR spiWritePixelsNL(spi_t *spi, const void *data_in, uint32_t if (msb) { if (l_bytes && i == (c_longs - 1)) { if (l_bytes == 2) { -#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 - MSB_16_SET(spi->dev->data_buf[i].val, data[i]); -#else +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 MSB_16_SET(spi->dev->data_buf[i], data[i]); +#else + MSB_16_SET(spi->dev->data_buf[i].val, data[i]); #endif } else { -#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 - spi->dev->data_buf[i].val = data[i] & 0xFF; -#else +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 spi->dev->data_buf[i] = data[i] & 0xFF; +#else + spi->dev->data_buf[i].val = data[i] & 0xFF; #endif } } else { -#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 - MSB_PIX_SET(spi->dev->data_buf[i].val, data[i]); -#else +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 MSB_PIX_SET(spi->dev->data_buf[i], data[i]); +#else + MSB_PIX_SET(spi->dev->data_buf[i].val, data[i]); #endif } } else { -#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 - spi->dev->data_buf[i].val = data[i]; -#else +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 spi->dev->data_buf[i] = data[i]; +#else + spi->dev->data_buf[i].val = data[i]; #endif } } diff --git a/cores/esp32/esp32-hal-spi.h b/cores/esp32/esp32-hal-spi.h index 0284fea8829..b83d199c54d 100644 --- a/cores/esp32/esp32-hal-spi.h +++ b/cores/esp32/esp32-hal-spi.h @@ -32,7 +32,7 @@ extern "C" { #define HSPI 2 //SPI 2 bus normally mapped to pins 12 - 15, but can be matrixed to any pins #define VSPI 3 //SPI 3 bus normally attached to pins 5, 18, 19 and 23, but can be matrixed to any pins #else -#define FSPI 0 // ESP32C2, C3, C6, H2, S2, S3, P4 - SPI 2 bus +#define FSPI 0 // ESP32C2, C3, C5, C6, C61, H2, S2, S3, P4 - SPI 2 bus #define HSPI 1 // ESP32S2, S3, P4 - SPI 3 bus #endif diff --git a/cores/esp32/esp32-hal.h b/cores/esp32/esp32-hal.h index 84c73577d3e..1a5503ea3ab 100644 --- a/cores/esp32/esp32-hal.h +++ b/cores/esp32/esp32-hal.h @@ -63,7 +63,7 @@ extern "C" { #if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 static const uint8_t BOOT_PIN = 0; -#elif CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C61 +#elif CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32C61 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C61 static const uint8_t BOOT_PIN = 9; #elif CONFIG_IDF_TARGET_ESP32P4 static const uint8_t BOOT_PIN = 35; diff --git a/docs/en/lib_builder.rst b/docs/en/lib_builder.rst index a8126c18edc..6c0693420ad 100644 --- a/docs/en/lib_builder.rst +++ b/docs/en/lib_builder.rst @@ -153,7 +153,9 @@ This build command will build for the ESP32-S3 target. You can specify other tar * esp32 * esp32c2 * esp32c3 +* esp32c5 * esp32c6 +* esp32c61 * esp32h2 * esp32p4 * esp32s2 @@ -211,7 +213,8 @@ Pre-Configuring the UI The UI can be pre-configured using command line arguments. The following arguments are available: - ``-t, --target ``: Comma-separated list of targets to be compiled. - Choose from: *all*, *esp32*, *esp32s2*, *esp32s3*, *esp32c2*, *esp32c3*, *esp32c6*, *esp32h2*. Default: all except *esp32c2*; + Choose from: *all*, *esp32*, *esp32c2*, *esp32c3*, *esp32c5*, *esp32c6*, *esp32c61*, *esp32h2*, *esp32s2*, *esp32s3*. + Default: all except *esp32c2* and *esp32c61*; - ``--copy, --no-copy``: Enable/disable copying the compiled libraries to ``arduino-esp32``. Enabled by default; - ``-c, --arduino-path ``: Path to ``arduino-esp32`` directory. Default: OS dependent; - ``-A, --arduino-branch ``: Branch of the ``arduino-esp32`` repository to be used. Default: set by the build script; diff --git a/idf_component.yml b/idf_component.yml index 99bf7048c1c..4f26b7cf668 100644 --- a/idf_component.yml +++ b/idf_component.yml @@ -7,6 +7,7 @@ targets: - esp32c3 - esp32c5 - esp32c6 + - esp32c61 - esp32h2 - esp32p4 - esp32s2 @@ -20,6 +21,7 @@ files: - "variants/esp32c3/**/*" - "variants/esp32c5/**/*" - "variants/esp32c6/**/*" + - "variants/esp32c61/**/*" - "variants/esp32h2/**/*" - "variants/esp32p4/**/*" - "variants/esp32s2/**/*" @@ -57,16 +59,16 @@ dependencies: version: "==1.6.4" # compatible with esp-zigbee-lib 1.6.8 require: public rules: - - if: "target not in [esp32c2, esp32p4]" + - if: "target not in [esp32c2, esp32c61, esp32p4]" espressif/esp-zigbee-lib: version: "==1.6.8" require: public rules: - - if: "target not in [esp32c2, esp32p4]" + - if: "target not in [esp32c2, esp32c61, esp32p4]" espressif/esp-dsp: version: "^1.3.4" rules: - - if: "target != esp32c2" + - if: "target not in [esp32c2, esp32c61]" # RainMaker Start (Fixed versions, because Matter supports only Insights 1.0.1) espressif/network_provisioning: version: "1.0.2" @@ -132,4 +134,4 @@ dependencies: examples: - path: ./idf_component_examples/hello_world - path: ./idf_component_examples/hw_cdc_hello_world - - path: ./idf_component_examples/esp_matter_light + - path: ./idf_component_examples/Arduino_ESP_Matter_over_OpenThread diff --git a/idf_component_examples/Arduino_ESP_Matter_over_OpenThread/ci.yml b/idf_component_examples/Arduino_ESP_Matter_over_OpenThread/ci.yml index 8fde8e9096c..b826c20507e 100644 --- a/idf_component_examples/Arduino_ESP_Matter_over_OpenThread/ci.yml +++ b/idf_component_examples/Arduino_ESP_Matter_over_OpenThread/ci.yml @@ -2,6 +2,7 @@ targets: esp32s2: false esp32s3: false esp32c2: false + esp32c61: false esp32p4: false requires: - CONFIG_OPENTHREAD_ENABLED=y diff --git a/libraries/ESP32/examples/ResetReason/ResetReason/ResetReason.ino b/libraries/ESP32/examples/ResetReason/ResetReason/ResetReason.ino index ca7e15bf479..fe047b242e1 100644 --- a/libraries/ESP32/examples/ResetReason/ResetReason/ResetReason.ino +++ b/libraries/ESP32/examples/ResetReason/ResetReason/ResetReason.ino @@ -30,6 +30,8 @@ #include "esp32p4/rom/rtc.h" #elif CONFIG_IDF_TARGET_ESP32C5 #include "esp32c5/rom/rtc.h" +#elif CONFIG_IDF_TARGET_ESP32C61 +#include "esp32c61/rom/rtc.h" #else #error Target CONFIG_IDF_TARGET is not supported #endif diff --git a/libraries/SPI/src/SPI.cpp b/libraries/SPI/src/SPI.cpp index 6229f887553..673301a8e15 100644 --- a/libraries/SPI/src/SPI.cpp +++ b/libraries/SPI/src/SPI.cpp @@ -79,22 +79,21 @@ bool SPIClass::begin(int8_t sck, int8_t miso, int8_t mosi, int8_t ss) { } if (sck == -1 && miso == -1 && mosi == -1 && ss == -1) { -#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 +#if CONFIG_IDF_TARGET_ESP32 + _sck = (_spi_num == VSPI) ? SCK : 14; + _miso = (_spi_num == VSPI) ? MISO : 12; + _mosi = (_spi_num == VSPI) ? MOSI : 13; + _ss = (_spi_num == VSPI) ? SS : 15; +#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 _sck = (_spi_num == FSPI) ? SCK : -1; _miso = (_spi_num == FSPI) ? MISO : -1; _mosi = (_spi_num == FSPI) ? MOSI : -1; _ss = (_spi_num == FSPI) ? SS : -1; -#elif CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 \ - || CONFIG_IDF_TARGET_ESP32C5 +#else _sck = SCK; _miso = MISO; _mosi = MOSI; _ss = SS; -#else - _sck = (_spi_num == VSPI) ? SCK : 14; - _miso = (_spi_num == VSPI) ? MISO : 12; - _mosi = (_spi_num == VSPI) ? MOSI : 13; - _ss = (_spi_num == VSPI) ? SS : 15; #endif } else { _sck = sck; diff --git a/platform.txt b/platform.txt index d715c0e2dca..b2d26a80bd0 100644 --- a/platform.txt +++ b/platform.txt @@ -85,6 +85,7 @@ build.extra_flags.esp32c6=-DARDUINO_USB_MODE=1 -DARDUINO_USB_CDC_ON_BOOT={build. build.extra_flags.esp32h2=-DARDUINO_USB_MODE=1 -DARDUINO_USB_CDC_ON_BOOT={build.cdc_on_boot} build.extra_flags.esp32p4=-DARDUINO_USB_MODE={build.usb_mode} -DARDUINO_USB_CDC_ON_BOOT={build.cdc_on_boot} -DARDUINO_USB_MSC_ON_BOOT={build.msc_on_boot} -DARDUINO_USB_DFU_ON_BOOT={build.dfu_on_boot} build.extra_flags.esp32c5=-DARDUINO_USB_MODE=1 -DARDUINO_USB_CDC_ON_BOOT={build.cdc_on_boot} +build.extra_flags.esp32c61=-DARDUINO_USB_MODE=1 -DARDUINO_USB_CDC_ON_BOOT={build.cdc_on_boot} # This can be overriden in boards.txt build.zigbee_mode= diff --git a/tests/requirements.txt b/tests/requirements.txt index bf7b600352e..93d4ec88208 100644 --- a/tests/requirements.txt +++ b/tests/requirements.txt @@ -1,8 +1,8 @@ cryptography==44.0.1 --only-binary cryptography pytest-cov==5.0.0 -pytest-embedded-serial-esp==2.1.2 -pytest-embedded-arduino==2.1.2 -pytest-embedded-wokwi==2.1.2 -pytest-embedded-qemu==2.1.2 +pytest-embedded-serial-esp==2.4.0 +pytest-embedded-arduino==2.4.0 +pytest-embedded-wokwi==2.4.0 +pytest-embedded-qemu==2.4.0 esptool==5.1.0 diff --git a/variants/esp32c61/pins_arduino.h b/variants/esp32c61/pins_arduino.h new file mode 100644 index 00000000000..dd25d0e53e7 --- /dev/null +++ b/variants/esp32c61/pins_arduino.h @@ -0,0 +1,37 @@ +#ifndef Pins_Arduino_h +#define Pins_Arduino_h + +#include +#include "soc/soc_caps.h" + +#define PIN_RGB_LED 8 +// BUILTIN_LED can be used in new Arduino API digitalWrite() like in Blink.ino +static const uint8_t LED_BUILTIN = SOC_GPIO_PIN_COUNT + PIN_RGB_LED; +#define BUILTIN_LED LED_BUILTIN // backward compatibility +#define LED_BUILTIN LED_BUILTIN // allow testing #ifdef LED_BUILTIN +// RGB_BUILTIN and RGB_BRIGHTNESS can be used in new Arduino API rgbLedWrite() +#define RGB_BUILTIN LED_BUILTIN +#define RGB_BRIGHTNESS 64 + +static const uint8_t TX = 11; +static const uint8_t RX = 10; + +static const uint8_t SDA = 23; +static const uint8_t SCL = 22; + +static const uint8_t SS = 25; +static const uint8_t MOSI = 26; +static const uint8_t MISO = 27; +static const uint8_t SCK = 28; + +static const uint8_t A0 = 0; +static const uint8_t A1 = 1; +static const uint8_t A2 = 2; +static const uint8_t A3 = 3; + +// LP I2C Pins are fixed on ESP32-C61 +#define WIRE1_PIN_DEFINED +static const uint8_t SDA1 = 6; +static const uint8_t SCL1 = 7; + +#endif /* Pins_Arduino_h */ From 7fd1b4c79d754b4b5c01e633cadd7f0db4874d2a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jan=20Proch=C3=A1zka?= <90197375+P-R-O-C-H-Y@users.noreply.github.com> Date: Thu, 13 Nov 2025 14:32:52 +0100 Subject: [PATCH 2/3] Update CMakeLists.txt Co-authored-by: Sugar Glider --- CMakeLists.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index a48d0b1ae85..d9b295dfa70 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -378,7 +378,7 @@ set(priv_requires fatfs nvs_flash app_update spiffs bootloader_support bt esp_hi if(NOT CONFIG_ARDUINO_SELECTIVE_COMPILATION OR CONFIG_ARDUINO_SELECTIVE_OpenThread) #if(CONFIG_SOC_IEEE802154_SUPPORTED) # Does not work! #if(CONFIG_OPENTHREAD_ENABLED) # Does not work! - if(IDF_TARGET STREQUAL "esp32c6" OR IDF_TARGET STREQUAL "esp32h2" OR IDF_TARGET STREQUAL "esp32c5" OR IDF_TARGET STREQUAL "esp32c61") # Sadly only this works + if(IDF_TARGET STREQUAL "esp32c6" OR IDF_TARGET STREQUAL "esp32h2" OR IDF_TARGET STREQUAL "esp32c5") # Sadly only this works list(APPEND requires openthread) endif() endif() From 205aadc92e7a09b2045921a66653c33e5aaee9c5 Mon Sep 17 00:00:00 2001 From: Lucas Saavedra Vaz <32426024+lucasssvaz@users.noreply.github.com> Date: Thu, 13 Nov 2025 11:38:50 -0300 Subject: [PATCH 3/3] fix(psram): Add missing C61 header --- cores/esp32/esp32-hal-psram.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/cores/esp32/esp32-hal-psram.c b/cores/esp32/esp32-hal-psram.c index 0d57a67ede4..9b985e81b2a 100644 --- a/cores/esp32/esp32-hal-psram.c +++ b/cores/esp32/esp32-hal-psram.c @@ -31,6 +31,8 @@ #include "esp32p4/rom/cache.h" #elif CONFIG_IDF_TARGET_ESP32C5 #include "esp32c5/rom/cache.h" +#elif CONFIG_IDF_TARGET_ESP32C61 +#include "esp32c61/rom/cache.h" #else #error Target CONFIG_IDF_TARGET is not supported #endif