diff --git a/components/esp_rom/esp32c2/ld/esp32c2.rom.api.ld b/components/esp_rom/esp32c2/ld/esp32c2.rom.api.ld index 5116ddc3945..058a31ace9a 100644 --- a/components/esp_rom/esp32c2/ld/esp32c2.rom.api.ld +++ b/components/esp_rom/esp32c2/ld/esp32c2.rom.api.ld @@ -20,7 +20,6 @@ PROVIDE ( esp_rom_gpio_connect_in_signal = gpio_matrix_in ); PROVIDE ( esp_rom_gpio_connect_out_signal = gpio_matrix_out ); PROVIDE ( esp_rom_efuse_mac_address_crc8 = esp_crc8 ); -PROVIDE ( esp_rom_efuse_get_flash_wp_gpio = ets_efuse_get_wp_pad ); PROVIDE ( esp_rom_efuse_is_secure_boot_enabled = ets_efuse_secure_boot_enabled ); PROVIDE ( esp_rom_uart_flush_tx = uart_tx_flush ); diff --git a/components/esp_rom/esp32c3/ld/esp32c3.rom.api.ld b/components/esp_rom/esp32c3/ld/esp32c3.rom.api.ld index 98888d17a4b..50461e94ad8 100644 --- a/components/esp_rom/esp32c3/ld/esp32c3.rom.api.ld +++ b/components/esp_rom/esp32c3/ld/esp32c3.rom.api.ld @@ -25,8 +25,6 @@ PROVIDE ( esp_rom_uart_tx_one_char = uart_tx_one_char ); PROVIDE ( esp_rom_uart_tx_wait_idle = uart_tx_wait_idle ); PROVIDE ( esp_rom_uart_rx_one_char = uart_rx_one_char ); PROVIDE ( esp_rom_uart_rx_string = UartRxString ); -PROVIDE ( esp_rom_uart_putc = ets_write_char_uart ); - PROVIDE ( esp_rom_md5_init = MD5Init ); PROVIDE ( esp_rom_md5_update = MD5Update ); diff --git a/components/esp_rom/include/esp32c2/rom/cache.h b/components/esp_rom/include/esp32c2/rom/cache.h index 684c3ffe5b1..30664e58098 100644 --- a/components/esp_rom/include/esp32c2/rom/cache.h +++ b/components/esp_rom/include/esp32c2/rom/cache.h @@ -269,54 +269,6 @@ void Cache_Occupy_ICache_MEMORY(cache_array_t icache_low); */ void Cache_Get_Mode(struct cache_mode * mode); -/** - * @brief set ICache modes: cache size, associate ways and cache line size. - * Please do not call this function in your SDK application. - * - * @param cache_size_t cache_size : the cache size, can be CACHE_SIZE_HALF and CACHE_SIZE_FULL - * - * @param cache_ways_t ways : the associate ways of cache, can be CACHE_4WAYS_ASSOC and CACHE_8WAYS_ASSOC - * - * @param cache_line_size_t cache_line_size : the cache line size, can be CACHE_LINE_SIZE_16B, CACHE_LINE_SIZE_32B and CACHE_LINE_SIZE_64B - * - * return none - */ -void Cache_Set_ICache_Mode(cache_size_t cache_size, cache_ways_t ways, cache_line_size_t cache_line_size); - -/** - * @brief set DCache modes: cache size, associate ways and cache line size. - * Please do not call this function in your SDK application. - * - * @param cache_size_t cache_size : the cache size, can be CACHE_SIZE_8KB and CACHE_SIZE_16KB - * - * @param cache_ways_t ways : the associate ways of cache, can be CACHE_4WAYS_ASSOC and CACHE_8WAYS_ASSOC - * - * @param cache_line_size_t cache_line_size : the cache line size, can be CACHE_LINE_SIZE_16B, CACHE_LINE_SIZE_32B and CACHE_LINE_SIZE_64B - * - * return none - */ -void Cache_Set_DCache_Mode(cache_size_t cache_size, cache_ways_t ways, cache_line_size_t cache_line_size); - -/** - * @brief check if the address is accessed through ICache. - * Please do not call this function in your SDK application. - * - * @param uint32_t addr : the address to check. - * - * @return 1 if the address is accessed through ICache, 0 if not. - */ -uint32_t Cache_Address_Through_ICache(uint32_t addr); - -/** - * @brief check if the address is accessed through DCache. - * Please do not call this function in your SDK application. - * - * @param uint32_t addr : the address to check. - * - * @return 1 if the address is accessed through DCache, 0 if not. - */ -uint32_t Cache_Address_Through_DCache(uint32_t addr); - /** * @brief Init mmu owner register to make i/d cache use half mmu entries. * @@ -374,166 +326,6 @@ void Cache_Invalidate_ICache_All(void); */ void Cache_Mask_All(void); -/** - * @brief Suspend ICache auto preload operation, then you can resume it after some ICache operations. - * Please do not call this function in your SDK application. - * - * @param None - * - * @return uint32_t : 0 for ICache not auto preload before suspend. - */ -uint32_t Cache_Suspend_ICache_Autoload(void); - -/** - * @brief Resume ICache auto preload operation after some ICache operations. - * Please do not call this function in your SDK application. - * - * @param uint32_t autoload : 0 for ICache not auto preload before suspend. - * - * @return None. - */ -void Cache_Resume_ICache_Autoload(uint32_t autoload); - -/** - * @brief Start an ICache manual preload, will suspend auto preload of ICache. - * Please do not call this function in your SDK application. - * - * @param uint32_t addr : start address of the preload region. - * - * @param uint32_t size : size of the preload region, should not exceed the size of ICache. - * - * @param uint32_t order : the preload order, 0 for positive, other for negative - * - * @return uint32_t : 0 for ICache not auto preload before manual preload. - */ -uint32_t Cache_Start_ICache_Preload(uint32_t addr, uint32_t size, uint32_t order); - -/** - * @brief Return if the ICache manual preload done. - * Please do not call this function in your SDK application. - * - * @param None - * - * @return uint32_t : 0 for ICache manual preload not done. - */ -uint32_t Cache_ICache_Preload_Done(void); - -/** - * @brief End the ICache manual preload to resume auto preload of ICache. - * Please do not call this function in your SDK application. - * - * @param uint32_t autoload : 0 for ICache not auto preload before manual preload. - * - * @return None - */ -void Cache_End_ICache_Preload(uint32_t autoload); - -/** - * @brief Config autoload parameters of ICache. - * Please do not call this function in your SDK application. - * - * @param struct autoload_config * config : autoload parameters. - * - * @return None - */ -void Cache_Config_ICache_Autoload(const struct autoload_config * config); - -/** - * @brief Enable auto preload for ICache. - * Please do not call this function in your SDK application. - * - * @param None - * - * @return None - */ -void Cache_Enable_ICache_Autoload(void); - -/** - * @brief Disable auto preload for ICache. - * Please do not call this function in your SDK application. - * - * @param None - * - * @return None - */ -void Cache_Disable_ICache_Autoload(void); - -/** - * @brief Config a group of prelock parameters of ICache. - * Please do not call this function in your SDK application. - * - * @param struct lock_config * config : a group of lock parameters. - * - * @return None - */ - -void Cache_Enable_ICache_PreLock(const struct lock_config *config); - -/** - * @brief Disable a group of prelock parameters for ICache. - * However, the locked data will not be released. - * Please do not call this function in your SDK application. - * - * @param uint16_t group : 0 for group0, 1 for group1. - * - * @return None - */ -void Cache_Disable_ICache_PreLock(uint16_t group); - -/** - * @brief Lock the cache items for ICache. - * Operation will be done CACHE_LINE_SIZE aligned. - * If the region is not in ICache addr room, nothing will be done. - * Please do not call this function in your SDK application. - * - * @param uint32_t addr: start address to lock - * - * @param uint32_t items: cache lines to lock, items * cache_line_size should not exceed the bus address size(16MB/32MB/64MB) - * - * @return None - */ -void Cache_Lock_ICache_Items(uint32_t addr, uint32_t items); - -/** - * @brief Unlock the cache items for ICache. - * Operation will be done CACHE_LINE_SIZE aligned. - * If the region is not in ICache addr room, nothing will be done. - * Please do not call this function in your SDK application. - * - * @param uint32_t addr: start address to unlock - * - * @param uint32_t items: cache lines to unlock, items * cache_line_size should not exceed the bus address size(16MB/32MB/64MB) - * - * @return None - */ -void Cache_Unlock_ICache_Items(uint32_t addr, uint32_t items); - -/** - * @brief Lock the cache items in tag memory for ICache or DCache. - * Please do not call this function in your SDK application. - * - * @param uint32_t addr : start address of lock region. - * - * @param uint32_t size : size of lock region. - * - * @return 0 for success - * 1 for invalid argument - */ -int Cache_Lock_Addr(uint32_t addr, uint32_t size); - -/** - * @brief Unlock the cache items in tag memory for ICache or DCache. - * Please do not call this function in your SDK application. - * - * @param uint32_t addr : start address of unlock region. - * - * @param uint32_t size : size of unlock region. - * - * @return 0 for success - * 1 for invalid argument - */ -int Cache_Unlock_Addr(uint32_t addr, uint32_t size); - /** * @brief Disable ICache access for the cpu. * This operation will make all ICache tag memory invalid, CPU can't access ICache, ICache will keep idle. @@ -711,76 +503,6 @@ uint32_t Cache_Get_IROM_MMU_End(void); */ uint32_t Cache_Get_DROM_MMU_End(void); -/** - * @brief Lock the permission control section configuration. After lock, any - * configuration modification will be bypass. Digital reset will clear the lock! - * Please do not call this function in your SDK application. - * - * @param int ibus : 1 for lock ibus pms, 0 for lock dbus pms - * - * @return None - */ -void Cache_Pms_Lock(int ibus); - -/** - * @brief Set three ibus pms boundary address, which will determine pms reject section and section 1/2. - * Please do not call this function in your SDK application. - * - * @param uint32_t ibus_boundary0_addr : vaddress for split line0 - * - * @param uint32_t ibus_boundary1_addr : vaddress for split line1 - * - * @param uint32_t ibus_boundary2_addr : vaddress for split line2 - * - * @return int : ESP_ROM_ERR_INVALID_ARG for invalid address, 0 for success - */ -int Cache_Ibus_Pms_Set_Addr(uint32_t ibus_boundary0_addr, uint32_t ibus_boundary1_addr, uint32_t ibus_boundary2_addr); - -/** - * @brief Set three ibus pms attribute, which will determine pms in different section and world. - * Please do not call this function in your SDK application. - * - * @param uint32_t ibus_pms_sct2_attr : attr for section2 - * - * @param uint32_t ibus_pms_sct1_attr : attr for section1 - * - * @return None - */ -void Cache_Ibus_Pms_Set_Attr(uint32_t ibus_pms_sct2_attr, uint32_t ibus_pms_sct1_attr); - -/** - * @brief Set three dbus pms boundary address, which will determine pms reject section and section 1/2. - * Please do not call this function in your SDK application. - * - * @param uint32_t dbus_boundary0_addr : vaddress for split line0 - * - * @param uint32_t dbus_boundary1_addr : vaddress for split line1 - * - * @param uint32_t dbus_boundary2_addr : vaddress for split line2 - * - * @return int : ESP_ROM_ERR_INVALID_ARG for invalid address, 0 for success - */ -int Cache_Dbus_Pms_Set_Addr(uint32_t dbus_boundary0_addr, uint32_t dbus_boundary1_addr, uint32_t dbus_boundary2_addr); - -/** - * @brief Set three dbus pms attribute, which will determine pms in different section and world. - * Please do not call this function in your SDK application. - * - * @param uint32_t dbus_pms_sct2_attr : attr for section2 - * - * @param uint32_t dbus_pms_sct1_attr : attr for section1 - * - * @return None - */ -void Cache_Dbus_Pms_Set_Attr(uint32_t dbus_pms_sct2_attr, uint32_t dbus_pms_sct1_attr); - -/** - * @brief Used by SPI flash mmap - * - */ -uint32_t flash_instr_rodata_start_page(uint32_t bus); -uint32_t flash_instr_rodata_end_page(uint32_t bus); - #ifdef __cplusplus } #endif diff --git a/components/esp_rom/include/esp32c2/rom/efuse.h b/components/esp_rom/include/esp32c2/rom/efuse.h index 5e064af72d2..d4f5f8f3900 100644 --- a/components/esp_rom/include/esp32c2/rom/efuse.h +++ b/components/esp_rom/include/esp32c2/rom/efuse.h @@ -47,11 +47,6 @@ typedef enum { */ int ets_efuse_set_timing(uint32_t clock); -/** - * @brief Enable efuse subsystem. Called after reset. Doesn't need to be called again. - */ -void ets_efuse_start(void); - /** * @brief Efuse read operation: copies data from physical efuses to efuse read registers. * @@ -151,37 +146,6 @@ unsigned ets_efuse_count_unused_key_blocks(void); */ void ets_efuse_rs_calculate(const void *data, void *rs_values); -/** - * @brief Read spi flash pads configuration from Efuse - * - * @return - * - 0 for default SPI pins. - * - 1 for default HSPI pins. - * - Other values define a custom pin configuration mask. Pins are encoded as per the EFUSE_SPICONFIG_RET_SPICLK, - * EFUSE_SPICONFIG_RET_SPIQ, EFUSE_SPICONFIG_RET_SPID, EFUSE_SPICONFIG_RET_SPICS0, EFUSE_SPICONFIG_RET_SPIHD macros. - * WP pin (for quad I/O modes) is not saved in efuse and not returned by this function. - */ -uint32_t ets_efuse_get_spiconfig(void); - -/** - * @brief Read spi flash wp pad from Efuse - * - * @return - * - 0x3f for invalid. - * - 0~46 is valid. - */ -uint32_t ets_efuse_get_wp_pad(void); - -/** - * @brief Read opi flash pads configuration from Efuse - * - * @return - * - 0 for default SPI pins. - * - Other values define a custom pin configuration mask. From the LSB, every 6 bits represent a GPIO number which stand for: - * DQS, D4, D5, D6, D7 accordingly. - */ -uint32_t ets_efuse_get_opiconfig(void); - /** * @brief Read if download mode disabled from Efuse * @@ -191,15 +155,6 @@ uint32_t ets_efuse_get_opiconfig(void); */ bool ets_efuse_download_modes_disabled(void); -/** - * @brief Read if legacy spi flash boot mode disabled from Efuse - * - * @return - * - true for efuse disable legacy spi flash boot mode. - * - false for efuse doesn't disable legacy spi flash boot mode. - */ -bool ets_efuse_legacy_spi_boot_mode_disabled(void); - /** * @brief Read if uart print control value from Efuse * @@ -211,45 +166,6 @@ bool ets_efuse_legacy_spi_boot_mode_disabled(void); */ uint32_t ets_efuse_get_uart_print_control(void); -/** - * @brief Read if USB-Serial-JTAG print during rom boot is disabled from Efuse - * - * @return - * - 1 for efuse disable USB-Serial-JTAG print during rom boot. - * - 0 for efuse doesn't disable USB-Serial-JTAG print during rom boot. - */ -uint32_t ets_efuse_usb_serial_jtag_print_is_disabled(void); - -/** - * @brief Read if usb download mode disabled from Efuse - * - * (Also returns true if security download mode is enabled, as this mode - * disables USB download.) - * - * @return - * - true for efuse disable usb download mode. - * - false for efuse doesn't disable usb download mode. - */ -bool ets_efuse_usb_download_mode_disabled(void); - -/** - * @brief Read if tiny basic mode disabled from Efuse - * - * @return - * - true for efuse disable tiny basic mode. - * - false for efuse doesn't disable tiny basic mode. - */ -bool ets_efuse_tiny_basic_mode_disabled(void); - -/** - * @brief Read if usb module disabled from Efuse - * - * @return - * - true for efuse disable usb module. - * - false for efuse doesn't disable usb module. - */ -bool ets_efuse_usb_module_disabled(void); - /** * @brief Read if security download modes enabled from Efuse * @@ -274,26 +190,6 @@ bool ets_efuse_secure_boot_aggressive_revoke_enabled(void); */ bool ets_efuse_cache_encryption_enabled(void); -/** - * @brief Return true if EFuse indicates an external phy needs to be used for USB - */ -bool ets_efuse_usb_use_ext_phy(void); - -/** - * @brief Return true if EFuse indicates USB device persistence is disabled - */ -bool ets_efuse_usb_force_nopersist(void); - -/** - * @brief Return true if OPI pins GPIO33-37 are powered by VDDSPI, otherwise by VDD33CPU - */ -bool ets_efuse_flash_opi_5pads_power_sel_vddspi(void); - -/** - * @brief Return true if EFuse indicates an opi flash is attached. - */ -bool ets_efuse_flash_opi_mode(void); - /** * @brief Return true if EFuse indicates to send a flash resume command. */ @@ -331,21 +227,6 @@ uint32_t ets_efuse_get_flash_delay_us(void); #define EFUSE_SPICONFIG_RET_SPIHD_SHIFT 24 #define EFUSE_SPICONFIG_RET_SPIHD(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPIHD_SHIFT) & EFUSE_SPICONFIG_RET_SPIHD_MASK) -/** - * @brief Enable JTAG temporarily by writing a JTAG HMAC "key" into - * the JTAG_CTRL registers. - * - * Works if JTAG has been "soft" disabled by burning the EFUSE_SOFT_DIS_JTAG efuse. - * - * Will enable the HMAC module to generate a "downstream" HMAC value from a key already saved in efuse, and then write the JTAG HMAC "key" which will enable JTAG if the two keys match. - * - * @param jtag_hmac_key Pointer to a 32 byte array containing a valid key. Supplied by user. - * @param key_block Index of a key block containing the source for this key. - * - * @return ETS_FAILED if HMAC operation fails or invalid parameter, ETS_OK otherwise. ETS_OK doesn't necessarily mean that JTAG was enabled. - */ -int ets_jtag_enable_temporarily(const uint8_t *jtag_hmac_key, ets_efuse_block_t key_block); - /** * @brief A crc8 algorithm used for MAC addresses in efuse * diff --git a/components/esp_rom/include/esp32c2/rom/ets_sys.h b/components/esp_rom/include/esp32c2/rom/ets_sys.h index 2a875b99ab3..6d2e3a4ef4e 100644 --- a/components/esp_rom/include/esp32c2/rom/ets_sys.h +++ b/components/esp_rom/include/esp32c2/rom/ets_sys.h @@ -61,54 +61,9 @@ struct ETSEventTag { typedef void (*ETSTask)(ETSEvent *e); /**< Type of the Task processer*/ typedef void (* ets_idle_cb_t)(void *arg); /**< Type of the system idle callback*/ -/** - * @brief Start the Espressif Task Scheduler, which is an infinit loop. Please do not add code after it. - * - * @param none - * - * @return none - */ -void ets_run(void); -/** - * @brief Set the Idle callback, when Tasks are processed, will call the callback before CPU goto sleep. - * - * @param ets_idle_cb_t func : The callback function. - * - * @param void *arg : Argument of the callback. - * - * @return None - */ -void ets_set_idle_cb(ets_idle_cb_t func, void *arg); -/** - * @brief Init a task with processer, priority, queue to receive Event, queue length. - * - * @param ETSTask task : The task processer. - * - * @param uint8_t prio : Task priority, 0-31, bigger num with high priority, one priority with one task. - * - * @param ETSEvent *queue : Queue belongs to the task, task always receives Events, Queue is circular used. - * - * @param uint8_t qlen : Queue length. - * - * @return None - */ -void ets_task(ETSTask task, uint8_t prio, ETSEvent *queue, uint8_t qlen); -/** - * @brief Post an event to an Task. - * - * @param uint8_t prio : Priority of the Task. - * - * @param ETSSignal sig : Event signal. - * - * @param ETSParam par : Event parameter - * - * @return ETS_OK : post successful - * @return ETS_FAILED : post failed - */ -ETS_STATUS ets_post(uint8_t prio, ETSSignal sig, ETSParam par); /** * @} @@ -134,26 +89,6 @@ extern const char *const exc_cause_table[40]; ///**< excption cause that defin */ void ets_set_user_start(uint32_t start); -/** - * @brief Set Pro cpu Startup code, code can be called when booting is not completed, or in Entry code. - * When Entry code completed, CPU will call the Startup code if not NULL, else call ets_run. - * - * @param uint32_t callback : the Startup code address value in uint32_t - * - * @return None : post successful - */ -void ets_set_startup_callback(uint32_t callback); - -/** - * @brief Set App cpu Entry code, code can be called in PRO CPU. - * When APP booting is completed, APP CPU will call the Entry code if not NULL. - * - * @param uint32_t start : the APP Entry code address value in uint32_t, stored in register APPCPU_CTRL_REG_D. - * - * @return None - */ -void ets_set_appcpu_boot_addr(uint32_t start); - /** * @} */ @@ -179,16 +114,6 @@ void ets_set_appcpu_boot_addr(uint32_t start); */ int ets_printf(const char *fmt, ...); -/** - * @brief Set the uart channel of ets_printf(uart_tx_one_char). - * ROM will set it base on the efuse and gpio setting, however, this can be changed after booting. - * - * @param uart_no : 0 for UART0, 1 for UART1. - * - * @return None - */ -void ets_set_printf_channel(uint8_t uart_no); - /** * @brief Get the uart channel of ets_printf(uart_tx_one_char). * @@ -367,18 +292,6 @@ void ets_delay_us(uint32_t us); */ void ets_update_cpu_frequency(uint32_t ticks_per_us); -/** - * @brief Set the real CPU ticks per us to the ets, so that ets_delay_us will be accurate. - * - * @note This function only sets the tick rate for the current CPU. It is located in ROM, - * so the deep sleep stub can use it even if IRAM is not initialized yet. - * - * @param uint32_t ticks_per_us : CPU ticks per us. - * - * @return None - */ -void ets_update_cpu_frequency_rom(uint32_t ticks_per_us); - /** * @brief Get the real CPU ticks per us to the ets. * This function do not return real CPU ticks per us, just the record in ets. It can be used to check with the real CPU frequency. @@ -496,17 +409,6 @@ void ets_intr_lock(void); */ void ets_intr_unlock(void); -/** - * @brief Unlock the interrupt to level 0, and CPU will go into power save mode(wait interrupt). - * This function direct set the CPU registers. - * In FreeRTOS, please call FreeRTOS apis, never call this api. - * - * @param None - * - * @return None - */ -void ets_waiti0(void); - /** * @brief Attach an CPU interrupt to a hardware source. * We have 4 steps to use an interrupt: diff --git a/components/esp_rom/include/esp32c2/rom/md5_hash.h b/components/esp_rom/include/esp32c2/rom/md5_hash.h deleted file mode 100644 index 3c5e10d1bf6..00000000000 --- a/components/esp_rom/include/esp32c2/rom/md5_hash.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2003-2005, Jouni Malinen - * - * SPDX-License-Identifier: BSD-3-Clause - */ -/* - * MD5 internal definitions - * Copyright (c) 2003-2005, Jouni Malinen - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Alternatively, this software may be distributed under the terms of BSD - * license. - * - * See README and COPYING for more details. - */ - -#ifndef _ROM_MD5_HASH_H_ -#define _ROM_MD5_HASH_H_ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -struct MD5Context { - uint32_t buf[4]; - uint32_t bits[2]; - uint8_t in[64]; -}; - -void MD5Init(struct MD5Context *context); -void MD5Update(struct MD5Context *context, unsigned char const *buf, unsigned len); -void MD5Final(unsigned char digest[16], struct MD5Context *context); - -#ifdef __cplusplus -} -#endif - -#endif /* _ROM_MD5_HASH_H_ */ diff --git a/components/esp_rom/include/esp32c2/rom/newlib.h b/components/esp_rom/include/esp32c2/rom/newlib.h deleted file mode 100644 index 2c84f9e7db2..00000000000 --- a/components/esp_rom/include/esp32c2/rom/newlib.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/* Global variables used by newlib in ROM - - Note that any of these symbols which are used by both ROM & IDF will have duplicate copies - in each "side" of the memory. However they're all pointers, and the pointers will be to the same - thing, so it's not a big memory waste and functionality is the same. - - Some variables which look like they should be here, but aren't: - - - __sf_fake_stdin, __sf_fake_stdout, __sf_fake_stderr - These are defined in ROM because ROM includes findfp.c, - but only used if _REENT_INIT or _REENT_INIT_PTR are ever called and ROM doesn't use these macros anywhere unless - printf() or similar is called without initializing reent first. ESP-IDF sets up its own minimal reent structures. - - - __lock___sinit_recursive_mutex, etc. - these are combined into common_recursive_mutex & common_mutex to save space -*/ -typedef struct { - _LOCK_T common_recursive_mutex; - _LOCK_T common_mutex; - struct _reent *global_reent; -} esp_rom_newlib_global_data_t; - -/* Called from IDF newlib component setup - to initialize common data shared between ROM and IDF -*/ -void esp_rom_newlib_init_global_data(const esp_rom_newlib_global_data_t *data); - -#ifdef __cplusplus -} -#endif diff --git a/components/esp_rom/include/esp32c2/rom/rsa_pss.h b/components/esp_rom/include/esp32c2/rom/rsa_pss.h deleted file mode 100644 index 2ee06a8ef0e..00000000000 --- a/components/esp_rom/include/esp32c2/rom/rsa_pss.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef _ROM_RSA_PSS_H_ -#define _ROM_RSA_PSS_H_ - -#include -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -#define ETS_SIG_LEN 384 /* Bytes */ -#define ETS_DIGEST_LEN 32 /* SHA-256, bytes */ - -typedef struct { - uint8_t n[384]; /* Public key modulus */ - uint32_t e; /* Public key exponent */ - uint8_t rinv[384]; - uint32_t mdash; -} ets_rsa_pubkey_t; - -bool ets_rsa_pss_verify(const ets_rsa_pubkey_t *key, const uint8_t *sig, const uint8_t *digest, uint8_t *verified_digest); - -void ets_mgf1_sha256(const uint8_t *mgfSeed, size_t seedLen, size_t maskLen, uint8_t *mask); - -bool ets_emsa_pss_verify(const uint8_t *encoded_message, const uint8_t *mhash); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/components/esp_rom/include/esp32c2/rom/secure_boot.h b/components/esp_rom/include/esp32c2/rom/secure_boot.h index cbb31ce02cd..023399c07cb 100644 --- a/components/esp_rom/include/esp32c2/rom/secure_boot.h +++ b/components/esp_rom/include/esp32c2/rom/secure_boot.h @@ -9,7 +9,6 @@ #include #include #include "ets_sys.h" -#include "rsa_pss.h" #include "ecdsa.h" #include "esp_assert.h" @@ -30,18 +29,6 @@ typedef enum { } ets_secure_boot_status_t; -/* Verify and stage-load the bootloader image - (reconfigures cache to map, loads trusted key digests from efuse, - copies the bootloader into the staging buffer.) - - If allow_key_revoke is true and aggressive revoke efuse is set, - any failed signature has its associated key revoked in efuse. - - If result is SB_SUCCESS, the "simple hash" of the bootloader - is copied into verified_hash. -*/ -ets_secure_boot_status_t ets_secure_boot_verify_stage_bootloader(uint8_t *verified_hash, bool allow_key_revoke); - /* Verify bootloader image (reconfigures cache to map), with key digests provided as parameters.) @@ -70,11 +57,6 @@ ETS_STATUS ets_secure_boot_read_key_digests(ets_secure_boot_key_digests_t *trust */ ets_secure_boot_status_t ets_secure_boot_verify_signature(const ets_secure_boot_signature_t *sig, const uint8_t *image_digest, const ets_secure_boot_key_digests_t *trusted_keys, uint8_t *verified_digest); -/* Revoke a public key digest in efuse. - @param index Digest to revoke. Must be 0, 1 or 2. - */ -void ets_secure_boot_revoke_public_key_digest(int index); - #define CRC_SIGN_BLOCK_LEN 1196 #define SIG_BLOCK_PADDING 4096 #define ETS_SECURE_BOOT_V2_SIGNATURE_MAGIC 0xE7 diff --git a/components/esp_rom/include/esp32c2/rom/spi_flash.h b/components/esp_rom/include/esp32c2/rom/spi_flash.h index bbac79e7223..4c03ad36e23 100644 --- a/components/esp_rom/include/esp32c2/rom/spi_flash.h +++ b/components/esp_rom/include/esp32c2/rom/spi_flash.h @@ -333,20 +333,6 @@ esp_rom_spiflash_result_t esp_rom_spiflash_read(uint32_t src_addr, uint32_t *des */ void esp_rom_spiflash_write_encrypted_enable(void); -/** - * @brief Prepare 32 Bytes data to encrpto writing, you should Erase it yourself if need. - * Please do not call this function in SDK. - * - * @param uint32_t flash_addr : Address to write, should be 32 bytes aligned. - * - * @param uint32_t *data : The pointer to data which is to write. - * - * @return ESP_ROM_SPIFLASH_RESULT_OK : Prepare OK. - * ESP_ROM_SPIFLASH_RESULT_ERR : Prepare error. - * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Prepare timeout. - */ -esp_rom_spiflash_result_t esp_rom_spiflash_prepare_encrypted_data(uint32_t flash_addr, uint32_t *data); - /** * @brief SPI1 go out of encrypto mode. * Please do not call this function in SDK. diff --git a/components/esp_rom/include/esp32c2/rom/uart.h b/components/esp_rom/include/esp32c2/rom/uart.h index 9b2dca6805d..8a4507e8108 100644 --- a/components/esp_rom/include/esp32c2/rom/uart.h +++ b/components/esp_rom/include/esp32c2/rom/uart.h @@ -188,19 +188,6 @@ void Uart_Init(uint8_t uart_no, uint32_t clock); */ void uart_div_modify(uint8_t uart_no, uint32_t DivLatchValue); -/** - * @brief Init uart0 or uart1 for UART download booting mode. - * Please do not call this function in SDK. - * - * @param uint8_t uart_no : 0 for UART0, 1 for UART1. - * - * @param uint8_t is_sync : 0, only one UART module, easy to detect, wait until detected; - * 1, two UART modules, hard to detect, detect and return. - * - * @return None - */ -int uart_baudrate_detect(uint8_t uart_no, uint8_t is_sync); - /** * @brief Switch printf channel of uart_tx_one_char. * Please do not call this function when printf. @@ -211,16 +198,6 @@ int uart_baudrate_detect(uint8_t uart_no, uint8_t is_sync); */ void uart_tx_switch(uint8_t uart_no); -/** - * @brief Switch message exchange channel for UART download booting. - * Please do not call this function in SDK. - * - * @param uint8_t uart_no : 0 for UART0, 1 for UART1. - * - * @return None - */ -void uart_buff_switch(uint8_t uart_no); - /** * @brief Output a char to printf channel, wait until fifo not full. * @@ -292,16 +269,6 @@ char uart_rx_one_char_block(void); */ STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); -/** - * @brief Process uart recevied information in the interrupt handler. - * Please do not call this function in SDK. - * - * @param void *para : the message receive buffer. - * - * @return None - */ -void uart_rx_intr_handler(void *para); - /** * @brief Get an char from receive buffer. * Please do not call this function in SDK. @@ -363,62 +330,6 @@ void send_packet(uint8_t *p, int len); */ int recv_packet(uint8_t *p, int len, uint8_t is_sync); -/** - * @brief Send an packet to download tool, with SLIP escaping. - * Please do not call this function in SDK. - * - * @param uint8_t *pData : the pointer to input string. - * - * @param uint16_t DataLen : the string length. - * - * @return OK for successful. - * FAIL for failed. - */ -STATUS SendMsg(uint8_t *pData, uint16_t DataLen); - -/** - * @brief Receive an packet from download tool, with SLIP escaping. - * Please do not call this function in SDK. - * - * @param uint8_t *pData : the pointer to input string. - * - * @param uint16_t MaxDataLen : If string length > MaxDataLen, the string will be truncated. - * - * @param uint8_t is_sync : 0, only one UART module; - * 1, two UART modules. - * - * @return OK for successful. - * FAIL for failed. - */ -STATUS RcvMsg(uint8_t *pData, uint16_t MaxDataLen, uint8_t is_sync); - -/** - * @brief Check if this UART is in download connection. - * Please do not call this function in SDK. - * - * @param uint8_t uart_no : 0 for UART0, 1 for UART1. - * - * @return ETS_NO_BOOT = 0 for no. - * SEL_UART_BOOT = BIT(1) for yes. - */ -uint8_t UartConnCheck(uint8_t uart_no); - -/** - * @brief Initialize the USB ACM UART - * Needs to be fed a buffer of at least 128 bytes, plus any rx buffer you may want to have. - * - * @param cdc_acm_work_mem Pointer to work mem for CDC-ACM code - * @param cdc_acm_work_mem_len Length of work mem - */ -void Uart_Init_USB(void *cdc_acm_work_mem, int cdc_acm_work_mem_len); - - -/** - * @brief Install handler to reset the chip when a RTS change has been detected on the CDC-ACM 'UART'. - */ -void uart_usb_enable_reset_on_rts(void); - - extern UartDevice UartDev; /** diff --git a/components/esp_rom/include/esp32c3/rom/aes.h b/components/esp_rom/include/esp32c3/rom/aes.h index d8002ef58cb..b5445e1dae4 100644 --- a/components/esp_rom/include/esp32c3/rom/aes.h +++ b/components/esp_rom/include/esp32c3/rom/aes.h @@ -1,16 +1,8 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _ROM_AES_H_ #define _ROM_AES_H_ @@ -39,10 +31,6 @@ void ets_aes_enable(void); void ets_aes_disable(void); -void ets_aes_set_endian(bool key_word_swap, bool key_byte_swap, - bool in_word_swap, bool in_byte_swap, - bool out_word_swap, bool out_byte_swap); - int ets_aes_setkey(enum AES_TYPE type, const void *key, enum AES_BITS bits); int ets_aes_setkey_enc(const void *key, enum AES_BITS bits); diff --git a/components/esp_rom/include/esp32c3/rom/cache.h b/components/esp_rom/include/esp32c3/rom/cache.h index 487143e695d..a35d992c63f 100644 --- a/components/esp_rom/include/esp32c3/rom/cache.h +++ b/components/esp_rom/include/esp32c3/rom/cache.h @@ -1,16 +1,8 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at - -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _ROM_CACHE_H_ #define _ROM_CACHE_H_ @@ -277,54 +269,6 @@ void Cache_Occupy_ICache_MEMORY(cache_array_t icache_low); */ void Cache_Get_Mode(struct cache_mode * mode); -/** - * @brief set ICache modes: cache size, associate ways and cache line size. - * Please do not call this function in your SDK application. - * - * @param cache_size_t cache_size : the cache size, can be CACHE_SIZE_HALF and CACHE_SIZE_FULL - * - * @param cache_ways_t ways : the associate ways of cache, can be CACHE_4WAYS_ASSOC and CACHE_8WAYS_ASSOC - * - * @param cache_line_size_t cache_line_size : the cache line size, can be CACHE_LINE_SIZE_16B, CACHE_LINE_SIZE_32B and CACHE_LINE_SIZE_64B - * - * return none - */ -void Cache_Set_ICache_Mode(cache_size_t cache_size, cache_ways_t ways, cache_line_size_t cache_line_size); - -/** - * @brief set DCache modes: cache size, associate ways and cache line size. - * Please do not call this function in your SDK application. - * - * @param cache_size_t cache_size : the cache size, can be CACHE_SIZE_8KB and CACHE_SIZE_16KB - * - * @param cache_ways_t ways : the associate ways of cache, can be CACHE_4WAYS_ASSOC and CACHE_8WAYS_ASSOC - * - * @param cache_line_size_t cache_line_size : the cache line size, can be CACHE_LINE_SIZE_16B, CACHE_LINE_SIZE_32B and CACHE_LINE_SIZE_64B - * - * return none - */ -void Cache_Set_DCache_Mode(cache_size_t cache_size, cache_ways_t ways, cache_line_size_t cache_line_size); - -/** - * @brief check if the address is accessed through ICache. - * Please do not call this function in your SDK application. - * - * @param uint32_t addr : the address to check. - * - * @return 1 if the address is accessed through ICache, 0 if not. - */ -uint32_t Cache_Address_Through_ICache(uint32_t addr); - -/** - * @brief check if the address is accessed through DCache. - * Please do not call this function in your SDK application. - * - * @param uint32_t addr : the address to check. - * - * @return 1 if the address is accessed through DCache, 0 if not. - */ -uint32_t Cache_Address_Through_DCache(uint32_t addr); - /** * @brief Init mmu owner register to make i/d cache use half mmu entries. * @@ -782,13 +726,6 @@ int Cache_Dbus_Pms_Set_Addr(uint32_t dbus_boundary0_addr, uint32_t dbus_boundary */ void Cache_Dbus_Pms_Set_Attr(uint32_t dbus_pms_sct2_attr, uint32_t dbus_pms_sct1_attr); -/** - * @brief Used by SPI flash mmap - * - */ -uint32_t flash_instr_rodata_start_page(uint32_t bus); -uint32_t flash_instr_rodata_end_page(uint32_t bus); - #ifdef __cplusplus } #endif diff --git a/components/esp_rom/include/esp32c3/rom/efuse.h b/components/esp_rom/include/esp32c3/rom/efuse.h index d1412c46110..912af40d96c 100644 --- a/components/esp_rom/include/esp32c3/rom/efuse.h +++ b/components/esp_rom/include/esp32c3/rom/efuse.h @@ -63,11 +63,6 @@ typedef enum { */ int ets_efuse_set_timing(uint32_t clock); -/** - * @brief Enable efuse subsystem. Called after reset. Doesn't need to be called again. - */ -void ets_efuse_start(void); - /** * @brief Efuse read operation: copies data from physical efuses to efuse read registers. * @@ -188,16 +183,6 @@ uint32_t ets_efuse_get_spiconfig(void); */ uint32_t ets_efuse_get_wp_pad(void); -/** - * @brief Read opi flash pads configuration from Efuse - * - * @return - * - 0 for default SPI pins. - * - Other values define a custom pin configuration mask. From the LSB, every 6 bits represent a GPIO number which stand for: - * DQS, D4, D5, D6, D7 accordingly. - */ -uint32_t ets_efuse_get_opiconfig(void); - /** * @brief Read if download mode disabled from Efuse * @@ -248,14 +233,6 @@ uint32_t ets_efuse_usb_serial_jtag_print_is_disabled(void); */ bool ets_efuse_usb_download_mode_disabled(void); -/** - * @brief Read if tiny basic mode disabled from Efuse - * - * @return - * - true for efuse disable tiny basic mode. - * - false for efuse doesn't disable tiny basic mode. - */ -bool ets_efuse_tiny_basic_mode_disabled(void); /** * @brief Read if usb module disabled from Efuse @@ -290,26 +267,11 @@ bool ets_efuse_secure_boot_aggressive_revoke_enabled(void); */ bool ets_efuse_cache_encryption_enabled(void); -/** - * @brief Return true if EFuse indicates an external phy needs to be used for USB - */ -bool ets_efuse_usb_use_ext_phy(void); - -/** - * @brief Return true if EFuse indicates USB device persistence is disabled - */ -bool ets_efuse_usb_force_nopersist(void); - /** * @brief Return true if OPI pins GPIO33-37 are powered by VDDSPI, otherwise by VDD33CPU */ bool ets_efuse_flash_opi_5pads_power_sel_vddspi(void); -/** - * @brief Return true if EFuse indicates an opi flash is attached. - */ -bool ets_efuse_flash_opi_mode(void); - /** * @brief Return true if EFuse indicates to send a flash resume command. */ diff --git a/components/esp_rom/include/esp32c3/rom/ets_sys.h b/components/esp_rom/include/esp32c3/rom/ets_sys.h index b2567e925e7..d5489bd835d 100644 --- a/components/esp_rom/include/esp32c3/rom/ets_sys.h +++ b/components/esp_rom/include/esp32c3/rom/ets_sys.h @@ -1,16 +1,8 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _ROM_ETS_SYS_H_ #define _ROM_ETS_SYS_H_ @@ -69,54 +61,9 @@ struct ETSEventTag { typedef void (*ETSTask)(ETSEvent *e); /**< Type of the Task processer*/ typedef void (* ets_idle_cb_t)(void *arg); /**< Type of the system idle callback*/ -/** - * @brief Start the Espressif Task Scheduler, which is an infinit loop. Please do not add code after it. - * - * @param none - * - * @return none - */ -void ets_run(void); -/** - * @brief Set the Idle callback, when Tasks are processed, will call the callback before CPU goto sleep. - * - * @param ets_idle_cb_t func : The callback function. - * - * @param void *arg : Argument of the callback. - * - * @return None - */ -void ets_set_idle_cb(ets_idle_cb_t func, void *arg); -/** - * @brief Init a task with processer, priority, queue to receive Event, queue length. - * - * @param ETSTask task : The task processer. - * - * @param uint8_t prio : Task priority, 0-31, bigger num with high priority, one priority with one task. - * - * @param ETSEvent *queue : Queue belongs to the task, task always receives Events, Queue is circular used. - * - * @param uint8_t qlen : Queue length. - * - * @return None - */ -void ets_task(ETSTask task, uint8_t prio, ETSEvent *queue, uint8_t qlen); -/** - * @brief Post an event to an Task. - * - * @param uint8_t prio : Priority of the Task. - * - * @param ETSSignal sig : Event signal. - * - * @param ETSParam par : Event parameter - * - * @return ETS_OK : post successful - * @return ETS_FAILED : post failed - */ -ETS_STATUS ets_post(uint8_t prio, ETSSignal sig, ETSParam par); /** * @} @@ -142,26 +89,6 @@ extern const char *const exc_cause_table[40]; ///**< excption cause that defin */ void ets_set_user_start(uint32_t start); -/** - * @brief Set Pro cpu Startup code, code can be called when booting is not completed, or in Entry code. - * When Entry code completed, CPU will call the Startup code if not NULL, else call ets_run. - * - * @param uint32_t callback : the Startup code address value in uint32_t - * - * @return None : post successful - */ -void ets_set_startup_callback(uint32_t callback); - -/** - * @brief Set App cpu Entry code, code can be called in PRO CPU. - * When APP booting is completed, APP CPU will call the Entry code if not NULL. - * - * @param uint32_t start : the APP Entry code address value in uint32_t, stored in register APPCPU_CTRL_REG_D. - * - * @return None - */ -void ets_set_appcpu_boot_addr(uint32_t start); - /** * @} */ @@ -187,16 +114,6 @@ void ets_set_appcpu_boot_addr(uint32_t start); */ int ets_printf(const char *fmt, ...); -/** - * @brief Set the uart channel of ets_printf(uart_tx_one_char). - * ROM will set it base on the efuse and gpio setting, however, this can be changed after booting. - * - * @param uart_no : 0 for UART0, 1 for UART1. - * - * @return None - */ -void ets_set_printf_channel(uint8_t uart_no); - /** * @brief Get the uart channel of ets_printf(uart_tx_one_char). * @@ -204,16 +121,6 @@ void ets_set_printf_channel(uint8_t uart_no); */ uint8_t ets_get_printf_channel(void); -/** - * @brief Output a char to uart, which uart to output(which is in uart module in ROM) is not in scope of the function. - * Can not print float point data format, or longlong data format - * - * @param char c : char to output. - * - * @return None - */ -void ets_write_char_uart(char c); - /** * @brief Ets_printf have two output functions： putc1 and putc2, both of which will be called if need ouput. * To install putc1, which is defaulted installed as ets_write_char_uart in none silent boot mode, as NULL in silent mode. @@ -375,17 +282,7 @@ void ets_delay_us(uint32_t us); */ void ets_update_cpu_frequency(uint32_t ticks_per_us); -/** - * @brief Set the real CPU ticks per us to the ets, so that ets_delay_us will be accurate. - * - * @note This function only sets the tick rate for the current CPU. It is located in ROM, - * so the deep sleep stub can use it even if IRAM is not initialized yet. - * - * @param uint32_t ticks_per_us : CPU ticks per us. - * - * @return None - */ -void ets_update_cpu_frequency_rom(uint32_t ticks_per_us); + /** * @brief Get the real CPU ticks per us to the ets. @@ -504,17 +401,6 @@ void ets_intr_lock(void); */ void ets_intr_unlock(void); -/** - * @brief Unlock the interrupt to level 0, and CPU will go into power save mode(wait interrupt). - * This function direct set the CPU registers. - * In FreeRTOS, please call FreeRTOS apis, never call this api. - * - * @param None - * - * @return None - */ -void ets_waiti0(void); - /** * @brief Attach an CPU interrupt to a hardware source. * We have 4 steps to use an interrupt: diff --git a/components/esp_rom/include/esp32c3/rom/rtc.h b/components/esp_rom/include/esp32c3/rom/rtc.h index 1e6100cb106..1750d5119df 100644 --- a/components/esp_rom/include/esp32c3/rom/rtc.h +++ b/components/esp_rom/include/esp32c3/rom/rtc.h @@ -173,16 +173,6 @@ RESET_REASON rtc_get_reset_reason(int cpu_no); */ WAKEUP_REASON rtc_get_wakeup_cause(void); -/** - * @brief Get CRC for Fast RTC Memory. - * - * @param uint32_t start_addr : 0 - 0x7ff for Fast RTC Memory. - * - * @param uint32_t crc_len : 0 - 0x7ff, 0 for 4 byte, 0x7ff for 0x2000 byte. - * - * @return uint32_t : CRC32 result - */ -uint32_t calc_rtc_memory_crc(uint32_t start_addr, uint32_t crc_len); /** * @brief Suppress ROM log by setting specific RTC control register. diff --git a/components/esp_rom/include/esp32c3/rom/secure_boot.h b/components/esp_rom/include/esp32c3/rom/secure_boot.h index 26cd0b4b842..6c1e95974b5 100644 --- a/components/esp_rom/include/esp32c3/rom/secure_boot.h +++ b/components/esp_rom/include/esp32c3/rom/secure_boot.h @@ -28,19 +28,6 @@ typedef enum { SB_FAILED = 0x7533885E, } ets_secure_boot_status_t; - -/* Verify and stage-load the bootloader image - (reconfigures cache to map, loads trusted key digests from efuse, - copies the bootloader into the staging buffer.) - - If allow_key_revoke is true and aggressive revoke efuse is set, - any failed signature has its associated key revoked in efuse. - - If result is SB_SUCCESS, the "simple hash" of the bootloader - is copied into verified_hash. -*/ -ets_secure_boot_status_t ets_secure_boot_verify_stage_bootloader(uint8_t *verified_hash, bool allow_key_revoke); - /* Verify bootloader image (reconfigures cache to map), with key digests provided as parameters.) diff --git a/components/esp_rom/include/esp32c3/rom/spi_flash.h b/components/esp_rom/include/esp32c3/rom/spi_flash.h index 1c75b79eef1..5862ee724bc 100644 --- a/components/esp_rom/include/esp32c3/rom/spi_flash.h +++ b/components/esp_rom/include/esp32c3/rom/spi_flash.h @@ -327,20 +327,6 @@ esp_rom_spiflash_result_t esp_rom_spiflash_read(uint32_t src_addr, uint32_t *des */ void esp_rom_spiflash_write_encrypted_enable(void); -/** - * @brief Prepare 32 Bytes data to encrpto writing, you should Erase it yourself if need. - * Please do not call this function in SDK. - * - * @param uint32_t flash_addr : Address to write, should be 32 bytes aligned. - * - * @param uint32_t *data : The pointer to data which is to write. - * - * @return ESP_ROM_SPIFLASH_RESULT_OK : Prepare OK. - * ESP_ROM_SPIFLASH_RESULT_ERR : Prepare error. - * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Prepare timeout. - */ -esp_rom_spiflash_result_t esp_rom_spiflash_prepare_encrypted_data(uint32_t flash_addr, uint32_t *data); - /** * @brief SPI1 go out of encrypto mode. * Please do not call this function in SDK. diff --git a/components/esp_rom/include/esp32c3/rom/uart.h b/components/esp_rom/include/esp32c3/rom/uart.h index 4e7e5b8ee62..0cd91b06d57 100644 --- a/components/esp_rom/include/esp32c3/rom/uart.h +++ b/components/esp_rom/include/esp32c3/rom/uart.h @@ -1,16 +1,8 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _ROM_UART_H_ #define _ROM_UART_H_ @@ -196,39 +188,6 @@ void Uart_Init(uint8_t uart_no, uint32_t clock); */ void uart_div_modify(uint8_t uart_no, uint32_t DivLatchValue); -/** - * @brief Init uart0 or uart1 for UART download booting mode. - * Please do not call this function in SDK. - * - * @param uint8_t uart_no : 0 for UART0, 1 for UART1. - * - * @param uint8_t is_sync : 0, only one UART module, easy to detect, wait until detected; - * 1, two UART modules, hard to detect, detect and return. - * - * @return None - */ -int uart_baudrate_detect(uint8_t uart_no, uint8_t is_sync); - -/** - * @brief Switch printf channel of uart_tx_one_char. - * Please do not call this function when printf. - * - * @param uint8_t uart_no : 0 for UART0, 1 for UART1. - * - * @return None - */ -void uart_tx_switch(uint8_t uart_no); - -/** - * @brief Switch message exchange channel for UART download booting. - * Please do not call this function in SDK. - * - * @param uint8_t uart_no : 0 for UART0, 1 for UART1. - * - * @return None - */ -void uart_buff_switch(uint8_t uart_no); - /** * @brief Output a char to printf channel, wait until fifo not full. * @@ -300,16 +259,6 @@ char uart_rx_one_char_block(void); */ STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); -/** - * @brief Process uart recevied information in the interrupt handler. - * Please do not call this function in SDK. - * - * @param void *para : the message receive buffer. - * - * @return None - */ -void uart_rx_intr_handler(void *para); - /** * @brief Get an char from receive buffer. * Please do not call this function in SDK. @@ -323,17 +272,6 @@ void uart_rx_intr_handler(void *para); */ STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); -/** - * @brief Get all chars from receive buffer. - * Please do not call this function in SDK. - * - * @param uint8_t *pCmdLn : the pointer to store the string. - * - * @return OK for successful. - * FAIL for failed. - */ -STATUS UartGetCmdLn(uint8_t *pCmdLn); - /** * @brief Get uart configuration struct. * Please do not call this function in SDK. @@ -371,62 +309,6 @@ void send_packet(uint8_t *p, int len); */ int recv_packet(uint8_t *p, int len, uint8_t is_sync); -/** - * @brief Send an packet to download tool, with SLIP escaping. - * Please do not call this function in SDK. - * - * @param uint8_t *pData : the pointer to input string. - * - * @param uint16_t DataLen : the string length. - * - * @return OK for successful. - * FAIL for failed. - */ -STATUS SendMsg(uint8_t *pData, uint16_t DataLen); - -/** - * @brief Receive an packet from download tool, with SLIP escaping. - * Please do not call this function in SDK. - * - * @param uint8_t *pData : the pointer to input string. - * - * @param uint16_t MaxDataLen : If string length > MaxDataLen, the string will be truncated. - * - * @param uint8_t is_sync : 0, only one UART module; - * 1, two UART modules. - * - * @return OK for successful. - * FAIL for failed. - */ -STATUS RcvMsg(uint8_t *pData, uint16_t MaxDataLen, uint8_t is_sync); - -/** - * @brief Check if this UART is in download connection. - * Please do not call this function in SDK. - * - * @param uint8_t uart_no : 0 for UART0, 1 for UART1. - * - * @return ETS_NO_BOOT = 0 for no. - * SEL_UART_BOOT = BIT(1) for yes. - */ -uint8_t UartConnCheck(uint8_t uart_no); - -/** - * @brief Initialize the USB ACM UART - * Needs to be fed a buffer of at least 128 bytes, plus any rx buffer you may want to have. - * - * @param cdc_acm_work_mem Pointer to work mem for CDC-ACM code - * @param cdc_acm_work_mem_len Length of work mem - */ -void Uart_Init_USB(void *cdc_acm_work_mem, int cdc_acm_work_mem_len); - - -/** - * @brief Install handler to reset the chip when a RTS change has been detected on the CDC-ACM 'UART'. - */ -void uart_usb_enable_reset_on_rts(void); - - extern UartDevice UartDev; /** diff --git a/components/esp_rom/include/esp32c6/rom/aes.h b/components/esp_rom/include/esp32c6/rom/aes.h index 82c263522ba..0af20666374 100644 --- a/components/esp_rom/include/esp32c6/rom/aes.h +++ b/components/esp_rom/include/esp32c6/rom/aes.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -31,10 +31,6 @@ void ets_aes_enable(void); void ets_aes_disable(void); -void ets_aes_set_endian(bool key_word_swap, bool key_byte_swap, - bool in_word_swap, bool in_byte_swap, - bool out_word_swap, bool out_byte_swap); - int ets_aes_setkey(enum AES_TYPE type, const void *key, enum AES_BITS bits); int ets_aes_setkey_enc(const void *key, enum AES_BITS bits); diff --git a/components/esp_rom/include/esp32c6/rom/cache.h b/components/esp_rom/include/esp32c6/rom/cache.h index 8f030f207af..03e32c2ecee 100644 --- a/components/esp_rom/include/esp32c6/rom/cache.h +++ b/components/esp_rom/include/esp32c6/rom/cache.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -223,17 +223,6 @@ int Cache_MSPI_MMU_Set(uint32_t sensitive, uint32_t ext_ram, uint32_t vaddr, uin */ int Cache_Dbus_MMU_Set(uint32_t ext_ram, uint32_t vaddr, uint32_t paddr, uint32_t psize, uint32_t num, uint32_t fixed); -/** - * @brief Count the pages in the bus room address which map to Flash. - * Please do not call this function in your SDK application. - * - * @param uint32_t bus : the bus to count with. - * - * @param uint32_t * page0_mapped : value should be initial by user, 0 for not mapped, other for mapped count. - * - * return uint32_t : the number of pages which map to Flash. - */ -uint32_t Cache_Count_Flash_Pages(uint32_t bus, uint32_t * page0_mapped); /** * @brief Get cache mode of ICache or DCache. @@ -245,26 +234,6 @@ uint32_t Cache_Count_Flash_Pages(uint32_t bus, uint32_t * page0_mapped); */ void Cache_Get_Mode(struct cache_mode * mode); -/** - * @brief check if the address is accessed through ICache. - * Please do not call this function in your SDK application. - * - * @param uint32_t addr : the address to check. - * - * @return 1 if the address is accessed through ICache, 0 if not. - */ -uint32_t Cache_Address_Through_ICache(uint32_t addr); - -/** - * @brief check if the address is accessed through DCache. - * Please do not call this function in your SDK application. - * - * @param uint32_t addr : the address to check. - * - * @return 1 if the address is accessed through DCache, 0 if not. - */ -uint32_t Cache_Address_Through_DCache(uint32_t addr); - /** * @brief Set cache page mode. * @@ -615,13 +584,6 @@ uint32_t Cache_Get_IROM_MMU_End(void); */ uint32_t Cache_Get_DROM_MMU_End(void); -/** - * @brief Used by SPI flash mmap - * - */ -uint32_t flash_instr_rodata_start_page(uint32_t bus); -uint32_t flash_instr_rodata_end_page(uint32_t bus); - #define Cache_Dbus_MMU_Set(ext_ram, vaddr, paddr, psize, num, fixed) \ Cache_MSPI_MMU_Set(ets_efuse_cache_encryption_enabled() ? MMU_SENSITIVE : 0, ext_ram, vaddr, paddr, psize, num, fixed) diff --git a/components/esp_rom/include/esp32c6/rom/efuse.h b/components/esp_rom/include/esp32c6/rom/efuse.h index a095f45568f..6cd9f4b377e 100644 --- a/components/esp_rom/include/esp32c6/rom/efuse.h +++ b/components/esp_rom/include/esp32c6/rom/efuse.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -54,20 +54,6 @@ typedef enum { ETS_EFUSE_BLOCK_MAX, } ets_efuse_block_t; -/** - * @brief set timing accroding the apb clock, so no read error or write error happens. - * - * @param clock: apb clock in HZ, only accept 5M(in FPGA), 10M(in FPGA), 20M, 40M, 80M. - * - * @return : 0 if success, others if clock not accepted - */ -int ets_efuse_set_timing(uint32_t clock); - -/** - * @brief Enable efuse subsystem. Called after reset. Doesn't need to be called again. - */ -void ets_efuse_start(void); - /** * @brief Efuse read operation: copies data from physical efuses to efuse read registers. * @@ -167,37 +153,6 @@ unsigned ets_efuse_count_unused_key_blocks(void); */ void ets_efuse_rs_calculate(const void *data, void *rs_values); -/** - * @brief Read spi flash pads configuration from Efuse - * - * @return - * - 0 for default SPI pins. - * - 1 for default HSPI pins. - * - Other values define a custom pin configuration mask. Pins are encoded as per the EFUSE_SPICONFIG_RET_SPICLK, - * EFUSE_SPICONFIG_RET_SPIQ, EFUSE_SPICONFIG_RET_SPID, EFUSE_SPICONFIG_RET_SPICS0, EFUSE_SPICONFIG_RET_SPIHD macros. - * WP pin (for quad I/O modes) is not saved in efuse and not returned by this function. - */ -uint32_t ets_efuse_get_spiconfig(void); - -/** - * @brief Read spi flash wp pad from Efuse - * - * @return - * - 0x3f for invalid. - * - 0~46 is valid. - */ -uint32_t ets_efuse_get_wp_pad(void); - -/** - * @brief Read opi flash pads configuration from Efuse - * - * @return - * - 0 for default SPI pins. - * - Other values define a custom pin configuration mask. From the LSB, every 6 bits represent a GPIO number which stand for: - * DQS, D4, D5, D6, D7 accordingly. - */ -uint32_t ets_efuse_get_opiconfig(void); - /** * @brief Read if download mode disabled from Efuse * @@ -207,15 +162,6 @@ uint32_t ets_efuse_get_opiconfig(void); */ bool ets_efuse_download_modes_disabled(void); -/** - * @brief Read if legacy spi flash boot mode disabled from Efuse - * - * @return - * - true for efuse disable legacy spi flash boot mode. - * - false for efuse doesn't disable legacy spi flash boot mode. - */ -bool ets_efuse_legacy_spi_boot_mode_disabled(void); - /** * @brief Read if uart print control value from Efuse * @@ -227,15 +173,6 @@ bool ets_efuse_legacy_spi_boot_mode_disabled(void); */ uint32_t ets_efuse_get_uart_print_control(void); -/** - * @brief Read if USB-Serial-JTAG print during rom boot is disabled from Efuse - * - * @return - * - 1 for efuse disable USB-Serial-JTAG print during rom boot. - * - 0 for efuse doesn't disable USB-Serial-JTAG print during rom boot. - */ -uint32_t ets_efuse_usb_serial_jtag_print_is_disabled(void); - /** * @brief Read if usb download mode disabled from Efuse * @@ -248,24 +185,6 @@ uint32_t ets_efuse_usb_serial_jtag_print_is_disabled(void); */ bool ets_efuse_usb_download_mode_disabled(void); -/** - * @brief Read if tiny basic mode disabled from Efuse - * - * @return - * - true for efuse disable tiny basic mode. - * - false for efuse doesn't disable tiny basic mode. - */ -bool ets_efuse_tiny_basic_mode_disabled(void); - -/** - * @brief Read if usb module disabled from Efuse - * - * @return - * - true for efuse disable usb module. - * - false for efuse doesn't disable usb module. - */ -bool ets_efuse_usb_module_disabled(void); - /** * @brief Read if security download modes enabled from Efuse * @@ -290,26 +209,6 @@ bool ets_efuse_secure_boot_aggressive_revoke_enabled(void); */ bool ets_efuse_cache_encryption_enabled(void); -/** - * @brief Return true if EFuse indicates an external phy needs to be used for USB - */ -bool ets_efuse_usb_use_ext_phy(void); - -/** - * @brief Return true if EFuse indicates USB device persistence is disabled - */ -bool ets_efuse_usb_force_nopersist(void); - -/** - * @brief Return true if OPI pins GPIO33-37 are powered by VDDSPI, otherwise by VDD33CPU - */ -bool ets_efuse_flash_opi_5pads_power_sel_vddspi(void); - -/** - * @brief Return true if EFuse indicates an opi flash is attached. - */ -bool ets_efuse_flash_opi_mode(void); - /** * @brief Return true if EFuse indicates to send a flash resume command. */ diff --git a/components/esp_rom/include/esp32c6/rom/ets_sys.h b/components/esp_rom/include/esp32c6/rom/ets_sys.h index afd3467728f..48a724d54b8 100644 --- a/components/esp_rom/include/esp32c6/rom/ets_sys.h +++ b/components/esp_rom/include/esp32c6/rom/ets_sys.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -61,54 +61,9 @@ struct ETSEventTag { typedef void (*ETSTask)(ETSEvent *e); /**< Type of the Task processer*/ typedef void (* ets_idle_cb_t)(void *arg); /**< Type of the system idle callback*/ -/** - * @brief Start the Espressif Task Scheduler, which is an infinit loop. Please do not add code after it. - * - * @param none - * - * @return none - */ -void ets_run(void); -/** - * @brief Set the Idle callback, when Tasks are processed, will call the callback before CPU goto sleep. - * - * @param ets_idle_cb_t func : The callback function. - * - * @param void *arg : Argument of the callback. - * - * @return None - */ -void ets_set_idle_cb(ets_idle_cb_t func, void *arg); -/** - * @brief Init a task with processer, priority, queue to receive Event, queue length. - * - * @param ETSTask task : The task processer. - * - * @param uint8_t prio : Task priority, 0-31, bigger num with high priority, one priority with one task. - * - * @param ETSEvent *queue : Queue belongs to the task, task always receives Events, Queue is circular used. - * - * @param uint8_t qlen : Queue length. - * - * @return None - */ -void ets_task(ETSTask task, uint8_t prio, ETSEvent *queue, uint8_t qlen); -/** - * @brief Post an event to an Task. - * - * @param uint8_t prio : Priority of the Task. - * - * @param ETSSignal sig : Event signal. - * - * @param ETSParam par : Event parameter - * - * @return ETS_OK : post successful - * @return ETS_FAILED : post failed - */ -ETS_STATUS ets_post(uint8_t prio, ETSSignal sig, ETSParam par); /** * @} @@ -134,26 +89,6 @@ extern const char *const exc_cause_table[40]; ///**< excption cause that defin */ void ets_set_user_start(uint32_t start); -/** - * @brief Set Pro cpu Startup code, code can be called when booting is not completed, or in Entry code. - * When Entry code completed, CPU will call the Startup code if not NULL, else call ets_run. - * - * @param uint32_t callback : the Startup code address value in uint32_t - * - * @return None : post successful - */ -void ets_set_startup_callback(uint32_t callback); - -/** - * @brief Set App cpu Entry code, code can be called in PRO CPU. - * When APP booting is completed, APP CPU will call the Entry code if not NULL. - * - * @param uint32_t start : the APP Entry code address value in uint32_t, stored in register APPCPU_CTRL_REG_D. - * - * @return None - */ -void ets_set_appcpu_boot_addr(uint32_t start); - /** * @} */ @@ -179,16 +114,6 @@ void ets_set_appcpu_boot_addr(uint32_t start); */ int ets_printf(const char *fmt, ...); -/** - * @brief Set the uart channel of ets_printf(uart_tx_one_char). - * ROM will set it base on the efuse and gpio setting, however, this can be changed after booting. - * - * @param uart_no : 0 for UART0, 1 for UART1. - * - * @return None - */ -void ets_set_printf_channel(uint8_t uart_no); - /** * @brief Get the uart channel of ets_printf(uart_tx_one_char). * @@ -367,17 +292,7 @@ void ets_delay_us(uint32_t us); */ void ets_update_cpu_frequency(uint32_t ticks_per_us); -/** - * @brief Set the real CPU ticks per us to the ets, so that ets_delay_us will be accurate. - * - * @note This function only sets the tick rate for the current CPU. It is located in ROM, - * so the deep sleep stub can use it even if IRAM is not initialized yet. - * - * @param uint32_t ticks_per_us : CPU ticks per us. - * - * @return None - */ -void ets_update_cpu_frequency_rom(uint32_t ticks_per_us); + /** * @brief Get the real CPU ticks per us to the ets. @@ -389,40 +304,6 @@ void ets_update_cpu_frequency_rom(uint32_t ticks_per_us); */ uint32_t ets_get_cpu_frequency(void); -/** - * @brief Get xtal_freq value, If value not stored in RTC_STORE5, than store. - * - * @param None - * - * @return uint32_t : if stored in efuse(not 0) - * clock = ets_efuse_get_xtal_freq() * 1000000; - * else if analog_8M in efuse - * clock = ets_get_xtal_scale() * 625 / 16 * ets_efuse_get_8M_clock(); - * else clock = 40M. - */ -uint32_t ets_get_xtal_freq(void); - -/** - * @brief Get the apb divior by xtal frequency. - * When any types of reset happen, the default value is 2. - * - * @param None - * - * @return uint32_t : 1 or 2. - */ -uint32_t ets_get_xtal_div(void); - -/** - * @brief Get apb_freq value, If value not stored in RTC_STORE5, than store. - * - * @param None - * - * @return uint32_t : if rtc store the value (RTC_STORE5 high 16 bits and low 16 bits with same value), read from rtc register. - * clock = (REG_READ(RTC_STORE5) & 0xffff) << 12; - * else store ets_get_detected_xtal_freq() in. - */ -uint32_t ets_get_apb_freq(void); - /** * @} */ @@ -496,16 +377,6 @@ void ets_intr_lock(void); */ void ets_intr_unlock(void); -/** - * @brief Unlock the interrupt to level 0, and CPU will go into power save mode(wait interrupt). - * This function direct set the CPU registers. - * In FreeRTOS, please call FreeRTOS apis, never call this api. - * - * @param None - * - * @return None - */ -void ets_waiti0(void); /** * @brief Attach an CPU interrupt to a hardware source. diff --git a/components/esp_rom/include/esp32c6/rom/secure_boot.h b/components/esp_rom/include/esp32c6/rom/secure_boot.h index f6ee4e25737..63e0b968660 100644 --- a/components/esp_rom/include/esp32c6/rom/secure_boot.h +++ b/components/esp_rom/include/esp32c6/rom/secure_boot.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -28,19 +28,6 @@ typedef enum { SB_FAILED = 0x7533885E, } ets_secure_boot_status_t; - -/* Verify and stage-load the bootloader image - (reconfigures cache to map, loads trusted key digests from efuse, - copies the bootloader into the staging buffer.) - - If allow_key_revoke is true and aggressive revoke efuse is set, - any failed signature has its associated key revoked in efuse. - - If result is SB_SUCCESS, the "simple hash" of the bootloader - is copied into verified_hash. -*/ -ets_secure_boot_status_t ets_secure_boot_verify_stage_bootloader(uint8_t *verified_hash, bool allow_key_revoke); - /* Verify bootloader image (reconfigures cache to map), with key digests provided as parameters.) diff --git a/components/esp_rom/include/esp32c6/rom/spi_flash.h b/components/esp_rom/include/esp32c6/rom/spi_flash.h index 61de15fb52b..2d782dee4f3 100644 --- a/components/esp_rom/include/esp32c6/rom/spi_flash.h +++ b/components/esp_rom/include/esp32c6/rom/spi_flash.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -95,19 +95,6 @@ typedef struct { uint16_t data; } esp_rom_spiflash_common_cmd_t; -/** - * @brief SPI Flash init, clock divisor is 4, use 1 line Slow read mode. - * Please do not call this function in SDK. - * - * @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping - * else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd - * - * @param uint8_t legacy: always keeping false. - * - * @return None - */ -void esp_rom_spiflash_attach(uint32_t ishspi, bool legacy); - /** * @brief SPI Read Flash status register. We use CMD 0x05 (RDSR). * Please do not call this function in SDK. @@ -333,20 +320,6 @@ esp_rom_spiflash_result_t esp_rom_spiflash_read(uint32_t src_addr, uint32_t *des */ void esp_rom_spiflash_write_encrypted_enable(void); -/** - * @brief Prepare 32 Bytes data to encrpto writing, you should Erase it yourself if need. - * Please do not call this function in SDK. - * - * @param uint32_t flash_addr : Address to write, should be 32 bytes aligned. - * - * @param uint32_t *data : The pointer to data which is to write. - * - * @return ESP_ROM_SPIFLASH_RESULT_OK : Prepare OK. - * ESP_ROM_SPIFLASH_RESULT_ERR : Prepare error. - * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Prepare timeout. - */ -esp_rom_spiflash_result_t esp_rom_spiflash_prepare_encrypted_data(uint32_t flash_addr, uint32_t *data); - /** * @brief SPI1 go out of encrypto mode. * Please do not call this function in SDK. diff --git a/components/esp_rom/include/esp32c6/rom/uart.h b/components/esp_rom/include/esp32c6/rom/uart.h index 6b1a3a2c603..380f19a4e56 100644 --- a/components/esp_rom/include/esp32c6/rom/uart.h +++ b/components/esp_rom/include/esp32c6/rom/uart.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -188,19 +188,6 @@ void Uart_Init(uint8_t uart_no, uint32_t clock); */ void uart_div_modify(uint8_t uart_no, uint32_t DivLatchValue); -/** - * @brief Init uart0 or uart1 for UART download booting mode. - * Please do not call this function in SDK. - * - * @param uint8_t uart_no : 0 for UART0, 1 for UART1. - * - * @param uint8_t is_sync : 0, only one UART module, easy to detect, wait until detected; - * 1, two UART modules, hard to detect, detect and return. - * - * @return None - */ -int uart_baudrate_detect(uint8_t uart_no, uint8_t is_sync); - /** * @brief Switch printf channel of uart_tx_one_char. * Please do not call this function when printf. @@ -211,16 +198,6 @@ int uart_baudrate_detect(uint8_t uart_no, uint8_t is_sync); */ void uart_tx_switch(uint8_t uart_no); -/** - * @brief Switch message exchange channel for UART download booting. - * Please do not call this function in SDK. - * - * @param uint8_t uart_no : 0 for UART0, 1 for UART1. - * - * @return None - */ -void uart_buff_switch(uint8_t uart_no); - /** * @brief Output a char to printf channel, wait until fifo not full. * @@ -363,62 +340,6 @@ void send_packet(uint8_t *p, int len); */ int recv_packet(uint8_t *p, int len, uint8_t is_sync); -/** - * @brief Send an packet to download tool, with SLIP escaping. - * Please do not call this function in SDK. - * - * @param uint8_t *pData : the pointer to input string. - * - * @param uint16_t DataLen : the string length. - * - * @return OK for successful. - * FAIL for failed. - */ -STATUS SendMsg(uint8_t *pData, uint16_t DataLen); - -/** - * @brief Receive an packet from download tool, with SLIP escaping. - * Please do not call this function in SDK. - * - * @param uint8_t *pData : the pointer to input string. - * - * @param uint16_t MaxDataLen : If string length > MaxDataLen, the string will be truncated. - * - * @param uint8_t is_sync : 0, only one UART module; - * 1, two UART modules. - * - * @return OK for successful. - * FAIL for failed. - */ -STATUS RcvMsg(uint8_t *pData, uint16_t MaxDataLen, uint8_t is_sync); - -/** - * @brief Check if this UART is in download connection. - * Please do not call this function in SDK. - * - * @param uint8_t uart_no : 0 for UART0, 1 for UART1. - * - * @return ETS_NO_BOOT = 0 for no. - * SEL_UART_BOOT = BIT(1) for yes. - */ -uint8_t UartConnCheck(uint8_t uart_no); - -/** - * @brief Initialize the USB ACM UART - * Needs to be fed a buffer of at least 128 bytes, plus any rx buffer you may want to have. - * - * @param cdc_acm_work_mem Pointer to work mem for CDC-ACM code - * @param cdc_acm_work_mem_len Length of work mem - */ -void Uart_Init_USB(void *cdc_acm_work_mem, int cdc_acm_work_mem_len); - - -/** - * @brief Install handler to reset the chip when a RTS change has been detected on the CDC-ACM 'UART'. - */ -void uart_usb_enable_reset_on_rts(void); - - extern UartDevice UartDev; /** diff --git a/components/esp_rom/include/esp32h2/rom/aes.h b/components/esp_rom/include/esp32h2/rom/aes.h index 82c263522ba..0af20666374 100644 --- a/components/esp_rom/include/esp32h2/rom/aes.h +++ b/components/esp_rom/include/esp32h2/rom/aes.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -31,10 +31,6 @@ void ets_aes_enable(void); void ets_aes_disable(void); -void ets_aes_set_endian(bool key_word_swap, bool key_byte_swap, - bool in_word_swap, bool in_byte_swap, - bool out_word_swap, bool out_byte_swap); - int ets_aes_setkey(enum AES_TYPE type, const void *key, enum AES_BITS bits); int ets_aes_setkey_enc(const void *key, enum AES_BITS bits); diff --git a/components/esp_rom/include/esp32h2/rom/cache.h b/components/esp_rom/include/esp32h2/rom/cache.h index c3be5fc0d09..1b5589b3010 100644 --- a/components/esp_rom/include/esp32h2/rom/cache.h +++ b/components/esp_rom/include/esp32h2/rom/cache.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -227,18 +227,6 @@ int Cache_MSPI_MMU_Set(uint32_t sensitive, uint32_t ext_ram, uint32_t vaddr, uin */ int Cache_Dbus_MMU_Set(uint32_t ext_ram, uint32_t vaddr, uint32_t paddr, uint32_t psize, uint32_t num, uint32_t fixed); -/** - * @brief Count the pages in the bus room address which map to Flash. - * Please do not call this function in your SDK application. - * - * @param uint32_t bus : the bus to count with. - * - * @param uint32_t * page0_mapped : value should be initial by user, 0 for not mapped, other for mapped count. - * - * return uint32_t : the number of pages which map to Flash. - */ -uint32_t Cache_Count_Flash_Pages(uint32_t bus, uint32_t * page0_mapped); - /** * @brief Get cache mode of ICache or DCache. * Please do not call this function in your SDK application. @@ -249,26 +237,6 @@ uint32_t Cache_Count_Flash_Pages(uint32_t bus, uint32_t * page0_mapped); */ void Cache_Get_Mode(struct cache_mode * mode); -/** - * @brief check if the address is accessed through ICache. - * Please do not call this function in your SDK application. - * - * @param uint32_t addr : the address to check. - * - * @return 1 if the address is accessed through ICache, 0 if not. - */ -uint32_t Cache_Address_Through_ICache(uint32_t addr); - -/** - * @brief check if the address is accessed through DCache. - * Please do not call this function in your SDK application. - * - * @param uint32_t addr : the address to check. - * - * @return 1 if the address is accessed through DCache, 0 if not. - */ -uint32_t Cache_Address_Through_DCache(uint32_t addr); - /** * @brief Set cache page mode. * @@ -619,12 +587,6 @@ uint32_t Cache_Get_IROM_MMU_End(void); */ uint32_t Cache_Get_DROM_MMU_End(void); -/** - * @brief Used by SPI flash mmap - * - */ -uint32_t flash_instr_rodata_start_page(uint32_t bus); -uint32_t flash_instr_rodata_end_page(uint32_t bus); #define Cache_Dbus_MMU_Set(ext_ram, vaddr, paddr, psize, num, fixed) \ Cache_MSPI_MMU_Set(ets_efuse_cache_encryption_enabled() ? MMU_SENSITIVE : 0, ext_ram, vaddr, paddr, psize, num, fixed) diff --git a/components/esp_rom/include/esp32h2/rom/efuse.h b/components/esp_rom/include/esp32h2/rom/efuse.h index a095f45568f..6cd9f4b377e 100644 --- a/components/esp_rom/include/esp32h2/rom/efuse.h +++ b/components/esp_rom/include/esp32h2/rom/efuse.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -54,20 +54,6 @@ typedef enum { ETS_EFUSE_BLOCK_MAX, } ets_efuse_block_t; -/** - * @brief set timing accroding the apb clock, so no read error or write error happens. - * - * @param clock: apb clock in HZ, only accept 5M(in FPGA), 10M(in FPGA), 20M, 40M, 80M. - * - * @return : 0 if success, others if clock not accepted - */ -int ets_efuse_set_timing(uint32_t clock); - -/** - * @brief Enable efuse subsystem. Called after reset. Doesn't need to be called again. - */ -void ets_efuse_start(void); - /** * @brief Efuse read operation: copies data from physical efuses to efuse read registers. * @@ -167,37 +153,6 @@ unsigned ets_efuse_count_unused_key_blocks(void); */ void ets_efuse_rs_calculate(const void *data, void *rs_values); -/** - * @brief Read spi flash pads configuration from Efuse - * - * @return - * - 0 for default SPI pins. - * - 1 for default HSPI pins. - * - Other values define a custom pin configuration mask. Pins are encoded as per the EFUSE_SPICONFIG_RET_SPICLK, - * EFUSE_SPICONFIG_RET_SPIQ, EFUSE_SPICONFIG_RET_SPID, EFUSE_SPICONFIG_RET_SPICS0, EFUSE_SPICONFIG_RET_SPIHD macros. - * WP pin (for quad I/O modes) is not saved in efuse and not returned by this function. - */ -uint32_t ets_efuse_get_spiconfig(void); - -/** - * @brief Read spi flash wp pad from Efuse - * - * @return - * - 0x3f for invalid. - * - 0~46 is valid. - */ -uint32_t ets_efuse_get_wp_pad(void); - -/** - * @brief Read opi flash pads configuration from Efuse - * - * @return - * - 0 for default SPI pins. - * - Other values define a custom pin configuration mask. From the LSB, every 6 bits represent a GPIO number which stand for: - * DQS, D4, D5, D6, D7 accordingly. - */ -uint32_t ets_efuse_get_opiconfig(void); - /** * @brief Read if download mode disabled from Efuse * @@ -207,15 +162,6 @@ uint32_t ets_efuse_get_opiconfig(void); */ bool ets_efuse_download_modes_disabled(void); -/** - * @brief Read if legacy spi flash boot mode disabled from Efuse - * - * @return - * - true for efuse disable legacy spi flash boot mode. - * - false for efuse doesn't disable legacy spi flash boot mode. - */ -bool ets_efuse_legacy_spi_boot_mode_disabled(void); - /** * @brief Read if uart print control value from Efuse * @@ -227,15 +173,6 @@ bool ets_efuse_legacy_spi_boot_mode_disabled(void); */ uint32_t ets_efuse_get_uart_print_control(void); -/** - * @brief Read if USB-Serial-JTAG print during rom boot is disabled from Efuse - * - * @return - * - 1 for efuse disable USB-Serial-JTAG print during rom boot. - * - 0 for efuse doesn't disable USB-Serial-JTAG print during rom boot. - */ -uint32_t ets_efuse_usb_serial_jtag_print_is_disabled(void); - /** * @brief Read if usb download mode disabled from Efuse * @@ -248,24 +185,6 @@ uint32_t ets_efuse_usb_serial_jtag_print_is_disabled(void); */ bool ets_efuse_usb_download_mode_disabled(void); -/** - * @brief Read if tiny basic mode disabled from Efuse - * - * @return - * - true for efuse disable tiny basic mode. - * - false for efuse doesn't disable tiny basic mode. - */ -bool ets_efuse_tiny_basic_mode_disabled(void); - -/** - * @brief Read if usb module disabled from Efuse - * - * @return - * - true for efuse disable usb module. - * - false for efuse doesn't disable usb module. - */ -bool ets_efuse_usb_module_disabled(void); - /** * @brief Read if security download modes enabled from Efuse * @@ -290,26 +209,6 @@ bool ets_efuse_secure_boot_aggressive_revoke_enabled(void); */ bool ets_efuse_cache_encryption_enabled(void); -/** - * @brief Return true if EFuse indicates an external phy needs to be used for USB - */ -bool ets_efuse_usb_use_ext_phy(void); - -/** - * @brief Return true if EFuse indicates USB device persistence is disabled - */ -bool ets_efuse_usb_force_nopersist(void); - -/** - * @brief Return true if OPI pins GPIO33-37 are powered by VDDSPI, otherwise by VDD33CPU - */ -bool ets_efuse_flash_opi_5pads_power_sel_vddspi(void); - -/** - * @brief Return true if EFuse indicates an opi flash is attached. - */ -bool ets_efuse_flash_opi_mode(void); - /** * @brief Return true if EFuse indicates to send a flash resume command. */ diff --git a/components/esp_rom/include/esp32h2/rom/ets_sys.h b/components/esp_rom/include/esp32h2/rom/ets_sys.h index afd3467728f..b9ac5a13f41 100644 --- a/components/esp_rom/include/esp32h2/rom/ets_sys.h +++ b/components/esp_rom/include/esp32h2/rom/ets_sys.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -61,54 +61,9 @@ struct ETSEventTag { typedef void (*ETSTask)(ETSEvent *e); /**< Type of the Task processer*/ typedef void (* ets_idle_cb_t)(void *arg); /**< Type of the system idle callback*/ -/** - * @brief Start the Espressif Task Scheduler, which is an infinit loop. Please do not add code after it. - * - * @param none - * - * @return none - */ -void ets_run(void); -/** - * @brief Set the Idle callback, when Tasks are processed, will call the callback before CPU goto sleep. - * - * @param ets_idle_cb_t func : The callback function. - * - * @param void *arg : Argument of the callback. - * - * @return None - */ -void ets_set_idle_cb(ets_idle_cb_t func, void *arg); -/** - * @brief Init a task with processer, priority, queue to receive Event, queue length. - * - * @param ETSTask task : The task processer. - * - * @param uint8_t prio : Task priority, 0-31, bigger num with high priority, one priority with one task. - * - * @param ETSEvent *queue : Queue belongs to the task, task always receives Events, Queue is circular used. - * - * @param uint8_t qlen : Queue length. - * - * @return None - */ -void ets_task(ETSTask task, uint8_t prio, ETSEvent *queue, uint8_t qlen); -/** - * @brief Post an event to an Task. - * - * @param uint8_t prio : Priority of the Task. - * - * @param ETSSignal sig : Event signal. - * - * @param ETSParam par : Event parameter - * - * @return ETS_OK : post successful - * @return ETS_FAILED : post failed - */ -ETS_STATUS ets_post(uint8_t prio, ETSSignal sig, ETSParam par); /** * @} @@ -134,26 +89,6 @@ extern const char *const exc_cause_table[40]; ///**< excption cause that defin */ void ets_set_user_start(uint32_t start); -/** - * @brief Set Pro cpu Startup code, code can be called when booting is not completed, or in Entry code. - * When Entry code completed, CPU will call the Startup code if not NULL, else call ets_run. - * - * @param uint32_t callback : the Startup code address value in uint32_t - * - * @return None : post successful - */ -void ets_set_startup_callback(uint32_t callback); - -/** - * @brief Set App cpu Entry code, code can be called in PRO CPU. - * When APP booting is completed, APP CPU will call the Entry code if not NULL. - * - * @param uint32_t start : the APP Entry code address value in uint32_t, stored in register APPCPU_CTRL_REG_D. - * - * @return None - */ -void ets_set_appcpu_boot_addr(uint32_t start); - /** * @} */ @@ -179,16 +114,6 @@ void ets_set_appcpu_boot_addr(uint32_t start); */ int ets_printf(const char *fmt, ...); -/** - * @brief Set the uart channel of ets_printf(uart_tx_one_char). - * ROM will set it base on the efuse and gpio setting, however, this can be changed after booting. - * - * @param uart_no : 0 for UART0, 1 for UART1. - * - * @return None - */ -void ets_set_printf_channel(uint8_t uart_no); - /** * @brief Get the uart channel of ets_printf(uart_tx_one_char). * @@ -367,17 +292,7 @@ void ets_delay_us(uint32_t us); */ void ets_update_cpu_frequency(uint32_t ticks_per_us); -/** - * @brief Set the real CPU ticks per us to the ets, so that ets_delay_us will be accurate. - * - * @note This function only sets the tick rate for the current CPU. It is located in ROM, - * so the deep sleep stub can use it even if IRAM is not initialized yet. - * - * @param uint32_t ticks_per_us : CPU ticks per us. - * - * @return None - */ -void ets_update_cpu_frequency_rom(uint32_t ticks_per_us); + /** * @brief Get the real CPU ticks per us to the ets. @@ -389,40 +304,6 @@ void ets_update_cpu_frequency_rom(uint32_t ticks_per_us); */ uint32_t ets_get_cpu_frequency(void); -/** - * @brief Get xtal_freq value, If value not stored in RTC_STORE5, than store. - * - * @param None - * - * @return uint32_t : if stored in efuse(not 0) - * clock = ets_efuse_get_xtal_freq() * 1000000; - * else if analog_8M in efuse - * clock = ets_get_xtal_scale() * 625 / 16 * ets_efuse_get_8M_clock(); - * else clock = 40M. - */ -uint32_t ets_get_xtal_freq(void); - -/** - * @brief Get the apb divior by xtal frequency. - * When any types of reset happen, the default value is 2. - * - * @param None - * - * @return uint32_t : 1 or 2. - */ -uint32_t ets_get_xtal_div(void); - -/** - * @brief Get apb_freq value, If value not stored in RTC_STORE5, than store. - * - * @param None - * - * @return uint32_t : if rtc store the value (RTC_STORE5 high 16 bits and low 16 bits with same value), read from rtc register. - * clock = (REG_READ(RTC_STORE5) & 0xffff) << 12; - * else store ets_get_detected_xtal_freq() in. - */ -uint32_t ets_get_apb_freq(void); - /** * @} */ @@ -496,17 +377,6 @@ void ets_intr_lock(void); */ void ets_intr_unlock(void); -/** - * @brief Unlock the interrupt to level 0, and CPU will go into power save mode(wait interrupt). - * This function direct set the CPU registers. - * In FreeRTOS, please call FreeRTOS apis, never call this api. - * - * @param None - * - * @return None - */ -void ets_waiti0(void); - /** * @brief Attach an CPU interrupt to a hardware source. * We have 4 steps to use an interrupt: diff --git a/components/esp_rom/include/esp32h2/rom/secure_boot.h b/components/esp_rom/include/esp32h2/rom/secure_boot.h index 26cd0b4b842..6c1e95974b5 100644 --- a/components/esp_rom/include/esp32h2/rom/secure_boot.h +++ b/components/esp_rom/include/esp32h2/rom/secure_boot.h @@ -28,19 +28,6 @@ typedef enum { SB_FAILED = 0x7533885E, } ets_secure_boot_status_t; - -/* Verify and stage-load the bootloader image - (reconfigures cache to map, loads trusted key digests from efuse, - copies the bootloader into the staging buffer.) - - If allow_key_revoke is true and aggressive revoke efuse is set, - any failed signature has its associated key revoked in efuse. - - If result is SB_SUCCESS, the "simple hash" of the bootloader - is copied into verified_hash. -*/ -ets_secure_boot_status_t ets_secure_boot_verify_stage_bootloader(uint8_t *verified_hash, bool allow_key_revoke); - /* Verify bootloader image (reconfigures cache to map), with key digests provided as parameters.) diff --git a/components/esp_rom/include/esp32h2/rom/spi_flash.h b/components/esp_rom/include/esp32h2/rom/spi_flash.h index 0341f59776d..2d782dee4f3 100644 --- a/components/esp_rom/include/esp32h2/rom/spi_flash.h +++ b/components/esp_rom/include/esp32h2/rom/spi_flash.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -95,19 +95,6 @@ typedef struct { uint16_t data; } esp_rom_spiflash_common_cmd_t; -/** - * @brief SPI Flash init, clock divisor is 4, use 1 line Slow read mode. - * Please do not call this function in SDK. - * - * @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping - * else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd - * - * @param uint8_t legacy: always keeping false. - * - * @return None - */ -void esp_rom_spiflash_attach(uint32_t ishspi, bool legacy); - /** * @brief SPI Read Flash status register. We use CMD 0x05 (RDSR). * Please do not call this function in SDK. @@ -333,20 +320,6 @@ esp_rom_spiflash_result_t esp_rom_spiflash_read(uint32_t src_addr, uint32_t *des */ void esp_rom_spiflash_write_encrypted_enable(void); -/** - * @brief Prepare 32 Bytes data to encrpto writing, you should Erase it yourself if need. - * Please do not call this function in SDK. - * - * @param uint32_t flash_addr : Address to write, should be 32 bytes aligned. - * - * @param uint32_t *data : The pointer to data which is to write. - * - * @return ESP_ROM_SPIFLASH_RESULT_OK : Prepare OK. - * ESP_ROM_SPIFLASH_RESULT_ERR : Prepare error. - * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Prepare timeout. - */ -esp_rom_spiflash_result_t esp_rom_spiflash_prepare_encrypted_data(uint32_t flash_addr, uint32_t *data); - /** * @brief SPI1 go out of encrypto mode. * Please do not call this function in SDK. @@ -437,19 +410,6 @@ esp_rom_spiflash_result_t esp_rom_spiflash_write_enable(esp_rom_spiflash_chip_t */ void esp_rom_spiflash_fix_dummylen(uint8_t spi, uint8_t freqdiv); -/** - * @brief Select SPI Flash to QIO mode when WP pad is read from Flash. - * Please do not call this function in SDK. - * - * @param uint8_t wp_gpio_num: WP gpio number. - * - * @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping - * else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd - * - * @return None - */ -void esp_rom_spiflash_select_qiomode(uint8_t wp_gpio_num, uint32_t ishspi); - /** * @brief Set SPI Flash pad drivers. * Please do not call this function in SDK. diff --git a/components/esp_rom/include/esp32h2/rom/uart.h b/components/esp_rom/include/esp32h2/rom/uart.h index 6b1a3a2c603..380f19a4e56 100644 --- a/components/esp_rom/include/esp32h2/rom/uart.h +++ b/components/esp_rom/include/esp32h2/rom/uart.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -188,19 +188,6 @@ void Uart_Init(uint8_t uart_no, uint32_t clock); */ void uart_div_modify(uint8_t uart_no, uint32_t DivLatchValue); -/** - * @brief Init uart0 or uart1 for UART download booting mode. - * Please do not call this function in SDK. - * - * @param uint8_t uart_no : 0 for UART0, 1 for UART1. - * - * @param uint8_t is_sync : 0, only one UART module, easy to detect, wait until detected; - * 1, two UART modules, hard to detect, detect and return. - * - * @return None - */ -int uart_baudrate_detect(uint8_t uart_no, uint8_t is_sync); - /** * @brief Switch printf channel of uart_tx_one_char. * Please do not call this function when printf. @@ -211,16 +198,6 @@ int uart_baudrate_detect(uint8_t uart_no, uint8_t is_sync); */ void uart_tx_switch(uint8_t uart_no); -/** - * @brief Switch message exchange channel for UART download booting. - * Please do not call this function in SDK. - * - * @param uint8_t uart_no : 0 for UART0, 1 for UART1. - * - * @return None - */ -void uart_buff_switch(uint8_t uart_no); - /** * @brief Output a char to printf channel, wait until fifo not full. * @@ -363,62 +340,6 @@ void send_packet(uint8_t *p, int len); */ int recv_packet(uint8_t *p, int len, uint8_t is_sync); -/** - * @brief Send an packet to download tool, with SLIP escaping. - * Please do not call this function in SDK. - * - * @param uint8_t *pData : the pointer to input string. - * - * @param uint16_t DataLen : the string length. - * - * @return OK for successful. - * FAIL for failed. - */ -STATUS SendMsg(uint8_t *pData, uint16_t DataLen); - -/** - * @brief Receive an packet from download tool, with SLIP escaping. - * Please do not call this function in SDK. - * - * @param uint8_t *pData : the pointer to input string. - * - * @param uint16_t MaxDataLen : If string length > MaxDataLen, the string will be truncated. - * - * @param uint8_t is_sync : 0, only one UART module; - * 1, two UART modules. - * - * @return OK for successful. - * FAIL for failed. - */ -STATUS RcvMsg(uint8_t *pData, uint16_t MaxDataLen, uint8_t is_sync); - -/** - * @brief Check if this UART is in download connection. - * Please do not call this function in SDK. - * - * @param uint8_t uart_no : 0 for UART0, 1 for UART1. - * - * @return ETS_NO_BOOT = 0 for no. - * SEL_UART_BOOT = BIT(1) for yes. - */ -uint8_t UartConnCheck(uint8_t uart_no); - -/** - * @brief Initialize the USB ACM UART - * Needs to be fed a buffer of at least 128 bytes, plus any rx buffer you may want to have. - * - * @param cdc_acm_work_mem Pointer to work mem for CDC-ACM code - * @param cdc_acm_work_mem_len Length of work mem - */ -void Uart_Init_USB(void *cdc_acm_work_mem, int cdc_acm_work_mem_len); - - -/** - * @brief Install handler to reset the chip when a RTS change has been detected on the CDC-ACM 'UART'. - */ -void uart_usb_enable_reset_on_rts(void); - - extern UartDevice UartDev; /** diff --git a/components/esp_rom/include/esp32h4/rom/aes.h b/components/esp_rom/include/esp32h4/rom/aes.h index a9ae04b2fa6..e593c7b9407 100644 --- a/components/esp_rom/include/esp32h4/rom/aes.h +++ b/components/esp_rom/include/esp32h4/rom/aes.h @@ -31,10 +31,6 @@ void ets_aes_enable(void); void ets_aes_disable(void); -void ets_aes_set_endian(bool key_word_swap, bool key_byte_swap, - bool in_word_swap, bool in_byte_swap, - bool out_word_swap, bool out_byte_swap); - int ets_aes_setkey(enum AES_TYPE type, const void *key, enum AES_BITS bits); int ets_aes_setkey_enc(const void *key, enum AES_BITS bits); diff --git a/components/esp_rom/include/esp32h4/rom/cache.h b/components/esp_rom/include/esp32h4/rom/cache.h index 105a778e6d3..b9504ab942d 100644 --- a/components/esp_rom/include/esp32h4/rom/cache.h +++ b/components/esp_rom/include/esp32h4/rom/cache.h @@ -269,54 +269,6 @@ void Cache_Occupy_ICache_MEMORY(cache_array_t icache_low); */ void Cache_Get_Mode(struct cache_mode * mode); -/** - * @brief set ICache modes: cache size, associate ways and cache line size. - * Please do not call this function in your SDK application. - * - * @param cache_size_t cache_size : the cache size, can be CACHE_SIZE_HALF and CACHE_SIZE_FULL - * - * @param cache_ways_t ways : the associate ways of cache, can be CACHE_4WAYS_ASSOC and CACHE_8WAYS_ASSOC - * - * @param cache_line_size_t cache_line_size : the cache line size, can be CACHE_LINE_SIZE_16B, CACHE_LINE_SIZE_32B and CACHE_LINE_SIZE_64B - * - * return none - */ -void Cache_Set_ICache_Mode(cache_size_t cache_size, cache_ways_t ways, cache_line_size_t cache_line_size); - -/** - * @brief set DCache modes: cache size, associate ways and cache line size. - * Please do not call this function in your SDK application. - * - * @param cache_size_t cache_size : the cache size, can be CACHE_SIZE_8KB and CACHE_SIZE_16KB - * - * @param cache_ways_t ways : the associate ways of cache, can be CACHE_4WAYS_ASSOC and CACHE_8WAYS_ASSOC - * - * @param cache_line_size_t cache_line_size : the cache line size, can be CACHE_LINE_SIZE_16B, CACHE_LINE_SIZE_32B and CACHE_LINE_SIZE_64B - * - * return none - */ -void Cache_Set_DCache_Mode(cache_size_t cache_size, cache_ways_t ways, cache_line_size_t cache_line_size); - -/** - * @brief check if the address is accessed through ICache. - * Please do not call this function in your SDK application. - * - * @param uint32_t addr : the address to check. - * - * @return 1 if the address is accessed through ICache, 0 if not. - */ -uint32_t Cache_Address_Through_ICache(uint32_t addr); - -/** - * @brief check if the address is accessed through DCache. - * Please do not call this function in your SDK application. - * - * @param uint32_t addr : the address to check. - * - * @return 1 if the address is accessed through DCache, 0 if not. - */ -uint32_t Cache_Address_Through_DCache(uint32_t addr); - /** * @brief Init mmu owner register to make i/d cache use half mmu entries. * @@ -774,13 +726,6 @@ int Cache_Dbus_Pms_Set_Addr(uint32_t dbus_boundary0_addr, uint32_t dbus_boundary */ void Cache_Dbus_Pms_Set_Attr(uint32_t dbus_pms_sct2_attr, uint32_t dbus_pms_sct1_attr); -/** - * @brief Used by SPI flash mmap - * - */ -uint32_t flash_instr_rodata_start_page(uint32_t bus); -uint32_t flash_instr_rodata_end_page(uint32_t bus); - #ifdef __cplusplus } #endif diff --git a/components/esp_rom/include/esp32h4/rom/efuse.h b/components/esp_rom/include/esp32h4/rom/efuse.h index d1412c46110..5117ffadf3f 100644 --- a/components/esp_rom/include/esp32h4/rom/efuse.h +++ b/components/esp_rom/include/esp32h4/rom/efuse.h @@ -63,11 +63,6 @@ typedef enum { */ int ets_efuse_set_timing(uint32_t clock); -/** - * @brief Enable efuse subsystem. Called after reset. Doesn't need to be called again. - */ -void ets_efuse_start(void); - /** * @brief Efuse read operation: copies data from physical efuses to efuse read registers. * @@ -188,16 +183,6 @@ uint32_t ets_efuse_get_spiconfig(void); */ uint32_t ets_efuse_get_wp_pad(void); -/** - * @brief Read opi flash pads configuration from Efuse - * - * @return - * - 0 for default SPI pins. - * - Other values define a custom pin configuration mask. From the LSB, every 6 bits represent a GPIO number which stand for: - * DQS, D4, D5, D6, D7 accordingly. - */ -uint32_t ets_efuse_get_opiconfig(void); - /** * @brief Read if download mode disabled from Efuse * @@ -207,15 +192,6 @@ uint32_t ets_efuse_get_opiconfig(void); */ bool ets_efuse_download_modes_disabled(void); -/** - * @brief Read if legacy spi flash boot mode disabled from Efuse - * - * @return - * - true for efuse disable legacy spi flash boot mode. - * - false for efuse doesn't disable legacy spi flash boot mode. - */ -bool ets_efuse_legacy_spi_boot_mode_disabled(void); - /** * @brief Read if uart print control value from Efuse * @@ -248,14 +224,6 @@ uint32_t ets_efuse_usb_serial_jtag_print_is_disabled(void); */ bool ets_efuse_usb_download_mode_disabled(void); -/** - * @brief Read if tiny basic mode disabled from Efuse - * - * @return - * - true for efuse disable tiny basic mode. - * - false for efuse doesn't disable tiny basic mode. - */ -bool ets_efuse_tiny_basic_mode_disabled(void); /** * @brief Read if usb module disabled from Efuse @@ -290,26 +258,11 @@ bool ets_efuse_secure_boot_aggressive_revoke_enabled(void); */ bool ets_efuse_cache_encryption_enabled(void); -/** - * @brief Return true if EFuse indicates an external phy needs to be used for USB - */ -bool ets_efuse_usb_use_ext_phy(void); - -/** - * @brief Return true if EFuse indicates USB device persistence is disabled - */ -bool ets_efuse_usb_force_nopersist(void); - /** * @brief Return true if OPI pins GPIO33-37 are powered by VDDSPI, otherwise by VDD33CPU */ bool ets_efuse_flash_opi_5pads_power_sel_vddspi(void); -/** - * @brief Return true if EFuse indicates an opi flash is attached. - */ -bool ets_efuse_flash_opi_mode(void); - /** * @brief Return true if EFuse indicates to send a flash resume command. */ diff --git a/components/esp_rom/include/esp32h4/rom/ets_sys.h b/components/esp_rom/include/esp32h4/rom/ets_sys.h index 9a94c642591..902127abfbb 100644 --- a/components/esp_rom/include/esp32h4/rom/ets_sys.h +++ b/components/esp_rom/include/esp32h4/rom/ets_sys.h @@ -61,54 +61,9 @@ struct ETSEventTag { typedef void (*ETSTask)(ETSEvent *e); /**< Type of the Task processer*/ typedef void (* ets_idle_cb_t)(void *arg); /**< Type of the system idle callback*/ -/** - * @brief Start the Espressif Task Scheduler, which is an infinit loop. Please do not add code after it. - * - * @param none - * - * @return none - */ -void ets_run(void); -/** - * @brief Set the Idle callback, when Tasks are processed, will call the callback before CPU goto sleep. - * - * @param ets_idle_cb_t func : The callback function. - * - * @param void *arg : Argument of the callback. - * - * @return None - */ -void ets_set_idle_cb(ets_idle_cb_t func, void *arg); -/** - * @brief Init a task with processer, priority, queue to receive Event, queue length. - * - * @param ETSTask task : The task processer. - * - * @param uint8_t prio : Task priority, 0-31, bigger num with high priority, one priority with one task. - * - * @param ETSEvent *queue : Queue belongs to the task, task always receives Events, Queue is circular used. - * - * @param uint8_t qlen : Queue length. - * - * @return None - */ -void ets_task(ETSTask task, uint8_t prio, ETSEvent *queue, uint8_t qlen); -/** - * @brief Post an event to an Task. - * - * @param uint8_t prio : Priority of the Task. - * - * @param ETSSignal sig : Event signal. - * - * @param ETSParam par : Event parameter - * - * @return ETS_OK : post successful - * @return ETS_FAILED : post failed - */ -ETS_STATUS ets_post(uint8_t prio, ETSSignal sig, ETSParam par); /** * @} @@ -134,25 +89,6 @@ extern const char *const exc_cause_table[40]; ///**< excption cause that defin */ void ets_set_user_start(uint32_t start); -/** - * @brief Set Pro cpu Startup code, code can be called when booting is not completed, or in Entry code. - * When Entry code completed, CPU will call the Startup code if not NULL, else call ets_run. - * - * @param uint32_t callback : the Startup code address value in uint32_t - * - * @return None : post successful - */ -void ets_set_startup_callback(uint32_t callback); - -/** - * @brief Set App cpu Entry code, code can be called in PRO CPU. - * When APP booting is completed, APP CPU will call the Entry code if not NULL. - * - * @param uint32_t start : the APP Entry code address value in uint32_t, stored in register APPCPU_CTRL_REG_D. - * - * @return None - */ -void ets_set_appcpu_boot_addr(uint32_t start); /** * @} @@ -179,16 +115,6 @@ void ets_set_appcpu_boot_addr(uint32_t start); */ int ets_printf(const char *fmt, ...); -/** - * @brief Set the uart channel of ets_printf(uart_tx_one_char). - * ROM will set it base on the efuse and gpio setting, however, this can be changed after booting. - * - * @param uart_no : 0 for UART0, 1 for UART1, 2 for UART2. - * - * @return None - */ -void ets_set_printf_channel(uint8_t uart_no); - /** * @brief Get the uart channel of ets_printf(uart_tx_one_char). * @@ -367,17 +293,7 @@ void ets_delay_us(uint32_t us); */ void ets_update_cpu_frequency(uint32_t ticks_per_us); -/** - * @brief Set the real CPU ticks per us to the ets, so that ets_delay_us will be accurate. - * - * @note This function only sets the tick rate for the current CPU. It is located in ROM, - * so the deep sleep stub can use it even if IRAM is not initialized yet. - * - * @param uint32_t ticks_per_us : CPU ticks per us. - * - * @return None - */ -void ets_update_cpu_frequency_rom(uint32_t ticks_per_us); + /** * @brief Get the real CPU ticks per us to the ets. @@ -496,17 +412,6 @@ void ets_intr_lock(void); */ void ets_intr_unlock(void); -/** - * @brief Unlock the interrupt to level 0, and CPU will go into power save mode(wait interrupt). - * This function direct set the CPU registers. - * In FreeRTOS, please call FreeRTOS apis, never call this api. - * - * @param None - * - * @return None - */ -void ets_waiti0(void); - /** * @brief Attach an CPU interrupt to a hardware source. * We have 4 steps to use an interrupt: diff --git a/components/esp_rom/include/esp32h4/rom/secure_boot.h b/components/esp_rom/include/esp32h4/rom/secure_boot.h index b7dd24b00cb..4d329d8adce 100644 --- a/components/esp_rom/include/esp32h4/rom/secure_boot.h +++ b/components/esp_rom/include/esp32h4/rom/secure_boot.h @@ -28,19 +28,6 @@ typedef enum { SB_FAILED = 0x7533885E, } ets_secure_boot_status_t; - -/* Verify and stage-load the bootloader image - (reconfigures cache to map, loads trusted key digests from efuse, - copies the bootloader into the staging buffer.) - - If allow_key_revoke is true and aggressive revoke efuse is set, - any failed signature has its associated key revoked in efuse. - - If result is SB_SUCCESS, the "simple hash" of the bootloader - is copied into verified_hash. -*/ -ets_secure_boot_status_t ets_secure_boot_verify_stage_bootloader(uint8_t *verified_hash, bool allow_key_revoke); - /* Verify bootloader image (reconfigures cache to map), with key digests provided as parameters.) diff --git a/components/esp_rom/include/esp32h4/rom/spi_flash.h b/components/esp_rom/include/esp32h4/rom/spi_flash.h index f972f6861dd..6915de9671b 100644 --- a/components/esp_rom/include/esp32h4/rom/spi_flash.h +++ b/components/esp_rom/include/esp32h4/rom/spi_flash.h @@ -95,19 +95,6 @@ typedef struct { uint16_t data; } esp_rom_spiflash_common_cmd_t; -/** - * @brief SPI Flash init, clock divisor is 4, use 1 line Slow read mode. - * Please do not call this function in SDK. - * - * @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping - * else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd - * - * @param uint8_t legacy: always keeping false. - * - * @return None - */ -void esp_rom_spiflash_attach(uint32_t ishspi, bool legacy); - /** * @brief SPI Read Flash status register. We use CMD 0x05 (RDSR). * Please do not call this function in SDK. @@ -333,20 +320,6 @@ esp_rom_spiflash_result_t esp_rom_spiflash_read(uint32_t src_addr, uint32_t *des */ void esp_rom_spiflash_write_encrypted_enable(void); -/** - * @brief Prepare 32 Bytes data to encrpto writing, you should Erase it yourself if need. - * Please do not call this function in SDK. - * - * @param uint32_t flash_addr : Address to write, should be 32 bytes aligned. - * - * @param uint32_t *data : The pointer to data which is to write. - * - * @return ESP_ROM_SPIFLASH_RESULT_OK : Prepare OK. - * ESP_ROM_SPIFLASH_RESULT_ERR : Prepare error. - * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Prepare timeout. - */ -esp_rom_spiflash_result_t esp_rom_spiflash_prepare_encrypted_data(uint32_t flash_addr, uint32_t *data); - /** * @brief SPI1 go out of encrypto mode. * Please do not call this function in SDK. diff --git a/components/esp_rom/include/esp32h4/rom/uart.h b/components/esp_rom/include/esp32h4/rom/uart.h index d8af1310bd1..d271893d761 100644 --- a/components/esp_rom/include/esp32h4/rom/uart.h +++ b/components/esp_rom/include/esp32h4/rom/uart.h @@ -188,19 +188,6 @@ void Uart_Init(uint8_t uart_no, uint32_t clock); */ void uart_div_modify(uint8_t uart_no, uint32_t DivLatchValue); -/** - * @brief Init uart0 or uart1 for UART download booting mode. - * Please do not call this function in SDK. - * - * @param uint8_t uart_no : 0 for UART0, 1 for UART1. - * - * @param uint8_t is_sync : 0, only one UART module, easy to detect, wait until detected; - * 1, two UART modules, hard to detect, detect and return. - * - * @return None - */ -int uart_baudrate_detect(uint8_t uart_no, uint8_t is_sync); - /** * @brief Switch printf channel of uart_tx_one_char. * Please do not call this function when printf. @@ -211,16 +198,6 @@ int uart_baudrate_detect(uint8_t uart_no, uint8_t is_sync); */ void uart_tx_switch(uint8_t uart_no); -/** - * @brief Switch message exchange channel for UART download booting. - * Please do not call this function in SDK. - * - * @param uint8_t uart_no : 0 for UART0, 1 for UART1. - * - * @return None - */ -void uart_buff_switch(uint8_t uart_no); - /** * @brief Output a char to printf channel, wait until fifo not full. * @@ -292,16 +269,6 @@ char uart_rx_one_char_block(void); */ STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); -/** - * @brief Process uart recevied information in the interrupt handler. - * Please do not call this function in SDK. - * - * @param void *para : the message receive buffer. - * - * @return None - */ -void uart_rx_intr_handler(void *para); - /** * @brief Get an char from receive buffer. * Please do not call this function in SDK. @@ -363,62 +330,6 @@ void send_packet(uint8_t *p, int len); */ int recv_packet(uint8_t *p, int len, uint8_t is_sync); -/** - * @brief Send an packet to download tool, with SLIP escaping. - * Please do not call this function in SDK. - * - * @param uint8_t *pData : the pointer to input string. - * - * @param uint16_t DataLen : the string length. - * - * @return OK for successful. - * FAIL for failed. - */ -STATUS SendMsg(uint8_t *pData, uint16_t DataLen); - -/** - * @brief Receive an packet from download tool, with SLIP escaping. - * Please do not call this function in SDK. - * - * @param uint8_t *pData : the pointer to input string. - * - * @param uint16_t MaxDataLen : If string length > MaxDataLen, the string will be truncated. - * - * @param uint8_t is_sync : 0, only one UART module; - * 1, two UART modules. - * - * @return OK for successful. - * FAIL for failed. - */ -STATUS RcvMsg(uint8_t *pData, uint16_t MaxDataLen, uint8_t is_sync); - -/** - * @brief Check if this UART is in download connection. - * Please do not call this function in SDK. - * - * @param uint8_t uart_no : 0 for UART0, 1 for UART1. - * - * @return ETS_NO_BOOT = 0 for no. - * SEL_UART_BOOT = BIT(1) for yes. - */ -uint8_t UartConnCheck(uint8_t uart_no); - -/** - * @brief Initialize the USB ACM UART - * Needs to be fed a buffer of at least 128 bytes, plus any rx buffer you may want to have. - * - * @param cdc_acm_work_mem Pointer to work mem for CDC-ACM code - * @param cdc_acm_work_mem_len Length of work mem - */ -void Uart_Init_USB(void *cdc_acm_work_mem, int cdc_acm_work_mem_len); - - -/** - * @brief Install handler to reset the chip when a RTS change has been detected on the CDC-ACM 'UART'. - */ -void uart_usb_enable_reset_on_rts(void); - - extern UartDevice UartDev; /** diff --git a/components/esp_rom/include/esp32s2/rom/efuse.h b/components/esp_rom/include/esp32s2/rom/efuse.h index ae887278bdf..6f4e8812b36 100644 --- a/components/esp_rom/include/esp32s2/rom/efuse.h +++ b/components/esp_rom/include/esp32s2/rom/efuse.h @@ -1,16 +1,8 @@ -// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at - -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _ROM_EFUSE_H_ #define _ROM_EFUSE_H_ @@ -257,14 +249,6 @@ uint32_t ets_efuse_get_uart_print_channel(void); */ bool ets_efuse_usb_download_mode_disabled(void); -/** - * @brief Read if tiny basic mode disabled from Efuse - * - * @return - * - true for efuse disable tiny basic mode. - * - false for efuse doesn't disable tiny basic mode. - */ -bool ets_efuse_tiny_basic_mode_disabled(void); /** * @brief Read if usb module disabled from Efuse diff --git a/components/esp_rom/include/esp32s2/rom/ets_sys.h b/components/esp_rom/include/esp32s2/rom/ets_sys.h index 1d4763dbf99..a2cf1adce34 100644 --- a/components/esp_rom/include/esp32s2/rom/ets_sys.h +++ b/components/esp_rom/include/esp32s2/rom/ets_sys.h @@ -1,16 +1,8 @@ -// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at - -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2010-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _ROM_ETS_SYS_H_ #define _ROM_ETS_SYS_H_ @@ -71,54 +63,9 @@ struct ETSEventTag { typedef void (*ETSTask)(ETSEvent *e); /**< Type of the Task processer*/ typedef void (* ets_idle_cb_t)(void *arg); /**< Type of the system idle callback*/ -/** - * @brief Start the Espressif Task Scheduler, which is an infinit loop. Please do not add code after it. - * - * @param none - * - * @return none - */ -void ets_run(void); -/** - * @brief Set the Idle callback, when Tasks are processed, will call the callback before CPU goto sleep. - * - * @param ets_idle_cb_t func : The callback function. - * - * @param void *arg : Argument of the callback. - * - * @return None - */ -void ets_set_idle_cb(ets_idle_cb_t func, void *arg); -/** - * @brief Init a task with processer, priority, queue to receive Event, queue length. - * - * @param ETSTask task : The task processer. - * - * @param uint8_t prio : Task priority, 0-31, bigger num with high priority, one priority with one task. - * - * @param ETSEvent *queue : Queue belongs to the task, task always receives Events, Queue is circular used. - * - * @param uint8_t qlen : Queue length. - * - * @return None - */ -void ets_task(ETSTask task, uint8_t prio, ETSEvent *queue, uint8_t qlen); -/** - * @brief Post an event to an Task. - * - * @param uint8_t prio : Priority of the Task. - * - * @param ETSSignal sig : Event signal. - * - * @param ETSParam par : Event parameter - * - * @return ETS_OK : post successful - * @return ETS_FAILED : post failed - */ -ETS_STATUS ets_post(uint8_t prio, ETSSignal sig, ETSParam par); /** * @} @@ -144,26 +91,6 @@ extern const char *const exc_cause_table[40]; ///**< excption cause that defin */ void ets_set_user_start(uint32_t start); -/** - * @brief Set Pro cpu Startup code, code can be called when booting is not completed, or in Entry code. - * When Entry code completed, CPU will call the Startup code if not NULL, else call ets_run. - * - * @param uint32_t callback : the Startup code address value in uint32_t - * - * @return None : post successful - */ -void ets_set_startup_callback(uint32_t callback); - -/** - * @brief Set App cpu Entry code, code can be called in PRO CPU. - * When APP booting is completed, APP CPU will call the Entry code if not NULL. - * - * @param uint32_t start : the APP Entry code address value in uint32_t, stored in register APPCPU_CTRL_REG_D. - * - * @return None - */ -void ets_set_appcpu_boot_addr(uint32_t start); - /** * @} */ @@ -377,17 +304,7 @@ void ets_delay_us(uint32_t us); */ void ets_update_cpu_frequency(uint32_t ticks_per_us); -/** - * @brief Set the real CPU ticks per us to the ets, so that ets_delay_us will be accurate. - * - * @note This function only sets the tick rate for the current CPU. It is located in ROM, - * so the deep sleep stub can use it even if IRAM is not initialized yet. - * - * @param uint32_t ticks_per_us : CPU ticks per us. - * - * @return None - */ -void ets_update_cpu_frequency_rom(uint32_t ticks_per_us); + /** * @brief Get the real CPU ticks per us to the ets. diff --git a/components/esp_rom/include/esp32s2/rom/opi_flash.h b/components/esp_rom/include/esp32s2/rom/opi_flash.h index bb209f67f05..c7e789b0201 100644 --- a/components/esp_rom/include/esp32s2/rom/opi_flash.h +++ b/components/esp_rom/include/esp32s2/rom/opi_flash.h @@ -192,104 +192,6 @@ void esp_rom_opiflash_exec_cmd(int spi_num, esp_rom_spiflash_read_mode_t mode, */ void esp_rom_opiflash_soft_reset(int spi_num, esp_rom_spiflash_read_mode_t mode); -/** - * @brief to read opi flash ID(for MX25UM25645G) - * @param spi_num spi port - * @param mode Flash Operation Mode - * @return opi flash id - */ -uint32_t esp_rom_opiflash_read_id(int spi_num, esp_rom_spiflash_read_mode_t mode); - -/** - * @brief to read opi flash status register(for MX25UM25645G) - * @param spi_num spi port - * @param mode Flash Operation Mode - * @return opi flash status value - */ -uint8_t esp_rom_opiflash_rdsr(int spi_num, esp_rom_spiflash_read_mode_t mode); - -/** - * @brief wait opi flash status register to be idle - * @param spi_num spi port - * @param mode Flash Operation Mode - */ -void esp_rom_opiflash_wait_idle(int spi_num, esp_rom_spiflash_read_mode_t mode); - -/** - * @brief to read the config register2(for MX25UM25645G) - * @param spi_num spi port - * @param mode Flash Operation Mode - * @param addr the address of configure register - * @return value of config register2 - */ -uint8_t esp_rom_opiflash_rdcr2(int spi_num, esp_rom_spiflash_read_mode_t mode, uint32_t addr); - -/** - * @brief to write the config register2(for MX25UM25645G) - * @param spi_num spi port - * @param mode Flash Operation Mode - * @param addr the address of config register - * @param val the value to write - */ -void esp_rom_opiflash_wrcr2(int spi_num, esp_rom_spiflash_read_mode_t mode, uint32_t addr, uint8_t val); - -/** - * @brief to erase flash sector(for MX25UM25645G) - * @param spi_num spi port - * @param address the sector address to be erased - * @param mode Flash operation mode - * @return flash operation result - */ -esp_rom_spiflash_result_t esp_rom_opiflash_erase_sector(int spi_num, uint32_t address, esp_rom_spiflash_read_mode_t mode); - -/** - * @brief to erase flash block(for MX25UM25645G) - * @param spi_num spi port - * @param address the block address to be erased - * @param mode Flash operation mode - * @return flash operation result - */ -esp_rom_spiflash_result_t esp_rom_opiflash_erase_block_64k(int spi_num, uint32_t address, esp_rom_spiflash_read_mode_t mode); - -/** - * @brief to erase a flash area define by start address and length(for MX25UM25645G) - * @param spi_num spi port - * @param start_addr the start address to be erased - * @param area_len the erea length to be erased - * @param mode flash operation mode - * @return flash operation result - */ -esp_rom_spiflash_result_t esp_rom_opiflash_erase_area(int spi_num, uint32_t start_addr, uint32_t area_len, esp_rom_spiflash_read_mode_t mode); - -/** - * @brief to read data from opi flash(for MX25UM25645G) - * @param spi_num spi port - * @param mode flash operation mode - * @param flash_addr flash address to read data from - * @param data_addr data buffer to accept the data - * @param len data length to be read - * @return flash operation result - */ -esp_rom_spiflash_result_t esp_rom_opiflash_read(int spi_num, esp_rom_spiflash_read_mode_t mode, uint32_t flash_addr, uint8_t *data_addr, int len); - -/** - * @brief to write data to opi flash(for MX25UM25645G) - * @param spi_num spi port - * @param mode flash operation mode - * @param flash_addr flash address to write data to - * @param data_addr data buffer to write to flash - * @param len data length to write - * @return flash operation result - */ -esp_rom_spiflash_result_t esp_rom_opiflash_write(int spi_num, esp_rom_spiflash_read_mode_t mode, uint32_t flash_addr, uint8_t *data_addr, uint32_t len); - -/** - * @brief to set opi flash operation mode(for MX25UM25645G) - * @param spi_num spi port - * @param cur_mode current operation mode - * @param target the target operation mode to be set - */ -void esp_rom_opiflash_set_mode(int spi_num, esp_rom_spiflash_read_mode_t cur_mode, esp_rom_spiflash_read_mode_t target_mode); #endif #ifdef __cplusplus diff --git a/components/esp_rom/include/esp32s2/rom/rtc.h b/components/esp_rom/include/esp32s2/rom/rtc.h index 15b6b97b9c2..1a6ba64acbe 100644 --- a/components/esp_rom/include/esp32s2/rom/rtc.h +++ b/components/esp_rom/include/esp32s2/rom/rtc.h @@ -166,16 +166,6 @@ RESET_REASON rtc_get_reset_reason(int cpu_no); */ WAKEUP_REASON rtc_get_wakeup_cause(void); -/** - * @brief Get CRC for Fast RTC Memory. - * - * @param uint32_t start_addr : 0 - 0x7ff for Fast RTC Memory. - * - * @param uint32_t crc_len : 0 - 0x7ff, 0 for 4 byte, 0x7ff for 0x2000 byte. - * - * @return uint32_t : CRC32 result - */ -uint32_t calc_rtc_memory_crc(uint32_t start_addr, uint32_t crc_len); /** * @brief Set CRC of Fast RTC memory 0-0x7ff into RTC STORE7. diff --git a/components/esp_rom/include/esp32s2/rom/spi_flash.h b/components/esp_rom/include/esp32s2/rom/spi_flash.h index 7642791860a..b496bc1b991 100644 --- a/components/esp_rom/include/esp32s2/rom/spi_flash.h +++ b/components/esp_rom/include/esp32s2/rom/spi_flash.h @@ -144,20 +144,6 @@ esp_rom_spiflash_result_t esp_rom_spiflash_read_status(esp_rom_spiflash_chip_t * */ esp_rom_spiflash_result_t esp_rom_spiflash_read_statushigh(esp_rom_spiflash_chip_t *spi, uint32_t *status); -/** - * @brief Write status to Flash status register. - * Please do not call this function in SDK. - * - * @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file. - * - * @param uint32_t status_value : Value to . - * - * @return ESP_ROM_SPIFLASH_RESULT_OK : write OK. - * ESP_ROM_SPIFLASH_RESULT_ERR : write error. - * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : write timeout. - */ -esp_rom_spiflash_result_t esp_rom_spiflash_write_status(esp_rom_spiflash_chip_t *spi, uint32_t status_value); - /** * @brief Use a command to Read Flash status register. * Please do not call this function in SDK. @@ -247,18 +233,6 @@ esp_rom_spiflash_result_t esp_rom_spiflash_unlock(void); esp_rom_spiflash_result_t esp_rom_spiflash_config_param(uint32_t deviceId, uint32_t chip_size, uint32_t block_size, uint32_t sector_size, uint32_t page_size, uint32_t status_mask); -/** - * @brief Erase whole flash chip. - * Please do not call this function in SDK. - * - * @param None - * - * @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK. - * ESP_ROM_SPIFLASH_RESULT_ERR : Erase error. - * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout. - */ -esp_rom_spiflash_result_t esp_rom_spiflash_erase_chip(void); - /** * @brief Erase a 64KB block of flash * Uses SPI flash command D8H. @@ -341,20 +315,6 @@ esp_rom_spiflash_result_t esp_rom_spiflash_read(uint32_t src_addr, uint32_t *des */ void esp_rom_spiflash_write_encrypted_enable(void); -/** - * @brief Prepare 32 Bytes data to encrpto writing, you should Erase it yourself if need. - * Please do not call this function in SDK. - * - * @param uint32_t flash_addr : Address to write, should be 32 bytes aligned. - * - * @param uint32_t *data : The pointer to data which is to write. - * - * @return ESP_ROM_SPIFLASH_RESULT_OK : Prepare OK. - * ESP_ROM_SPIFLASH_RESULT_ERR : Prepare error. - * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Prepare timeout. - */ -esp_rom_spiflash_result_t esp_rom_spiflash_prepare_encrypted_data(uint32_t flash_addr, uint32_t *data); - /** * @brief SPI1 go out of encrypto mode. * Please do not call this function in SDK. diff --git a/components/esp_rom/include/esp32s2/rom/usb/cdc_acm.h b/components/esp_rom/include/esp32s2/rom/usb/cdc_acm.h index 90d71e81772..38161d7a313 100644 --- a/components/esp_rom/include/esp32s2/rom/usb/cdc_acm.h +++ b/components/esp_rom/include/esp32s2/rom/usb/cdc_acm.h @@ -58,17 +58,6 @@ typedef void(*uart_irq_callback_t)(cdc_acm_device *dev, int status); int cdc_acm_rx_fifo_cnt(cdc_acm_device *dev); - -/* - * @brief Poll the device for input. - * - * @return -ENOTSUP Since underlying USB device controller always uses - * interrupts, polled mode UART APIs are not implemented for the UART interface - * exported by CDC ACM driver. Apps should use fifo_read API instead. - */ - -int cdc_acm_poll_in(cdc_acm_device *dev, unsigned char *c); - /* * @brief Output a character in polled mode. * diff --git a/components/esp_rom/include/esp32s3/rom/aes.h b/components/esp_rom/include/esp32s3/rom/aes.h index 1df00a1d6d8..06e834fff3f 100644 --- a/components/esp_rom/include/esp32s3/rom/aes.h +++ b/components/esp_rom/include/esp32s3/rom/aes.h @@ -1,16 +1,8 @@ -// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once @@ -36,10 +28,6 @@ void ets_aes_enable(void); void ets_aes_disable(void); -void ets_aes_set_endian(bool key_word_swap, bool key_byte_swap, - bool in_word_swap, bool in_byte_swap, - bool out_word_swap, bool out_byte_swap); - int ets_aes_setkey(enum AES_TYPE type, const void *key, enum AES_BITS bits); int ets_aes_setkey_enc(const void *key, enum AES_BITS bits); diff --git a/components/esp_rom/include/esp32s3/rom/efuse.h b/components/esp_rom/include/esp32s3/rom/efuse.h index 3d347f48330..c34ca57de10 100644 --- a/components/esp_rom/include/esp32s3/rom/efuse.h +++ b/components/esp_rom/include/esp32s3/rom/efuse.h @@ -64,11 +64,6 @@ typedef enum { */ int ets_efuse_set_timing(uint32_t clock); -/** - * @brief Enable efuse subsystem. Called after reset. Doesn't need to be called again. - */ -void ets_efuse_start(void); - /** * @brief Efuse read operation: copies data from physical efuses to efuse read registers. * @@ -189,16 +184,6 @@ uint32_t ets_efuse_get_spiconfig(void); */ uint32_t ets_efuse_get_wp_pad(void); -/** - * @brief Read opi flash pads configuration from Efuse - * - * @return - * - 0 for default SPI pins. - * - Other values define a custom pin configuration mask. From the LSB, every 6 bits represent a GPIO number which stand for: - * DQS, D4, D5, D6, D7 accordingly. - */ -uint32_t ets_efuse_get_opiconfig(void); - /** * @brief Read if download mode disabled from Efuse * @@ -249,14 +234,6 @@ uint32_t ets_efuse_usb_serial_jtag_print_is_disabled(void); */ bool ets_efuse_usb_download_mode_disabled(void); -/** - * @brief Read if tiny basic mode disabled from Efuse - * - * @return - * - true for efuse disable tiny basic mode. - * - false for efuse doesn't disable tiny basic mode. - */ -bool ets_efuse_tiny_basic_mode_disabled(void); /** * @brief Read if usb module disabled from Efuse @@ -291,26 +268,11 @@ bool ets_efuse_secure_boot_aggressive_revoke_enabled(void); */ bool ets_efuse_cache_encryption_enabled(void); -/** - * @brief Return true if EFuse indicates an external phy needs to be used for USB - */ -bool ets_efuse_usb_use_ext_phy(void); - -/** - * @brief Return true if EFuse indicates USB device persistence is disabled - */ -bool ets_efuse_usb_force_nopersist(void); - /** * @brief Return true if OPI pins GPIO33-37 are powered by VDDSPI, otherwise by VDD33CPU */ bool ets_efuse_flash_opi_5pads_power_sel_vddspi(void); -/** - * @brief Return true if EFuse indicates an opi flash is attached. - */ -bool ets_efuse_flash_opi_mode(void); - /** * @brief Return true if EFuse indicates to send a flash resume command. */ diff --git a/components/esp_rom/include/esp32s3/rom/ets_sys.h b/components/esp_rom/include/esp32s3/rom/ets_sys.h index edf9627c68f..9047442c36e 100644 --- a/components/esp_rom/include/esp32s3/rom/ets_sys.h +++ b/components/esp_rom/include/esp32s3/rom/ets_sys.h @@ -1,16 +1,8 @@ -// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2010-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once @@ -69,54 +61,9 @@ struct ETSEventTag { typedef void (*ETSTask)(ETSEvent *e); /**< Type of the Task processer*/ typedef void (* ets_idle_cb_t)(void *arg); /**< Type of the system idle callback*/ -/** - * @brief Start the Espressif Task Scheduler, which is an infinit loop. Please do not add code after it. - * - * @param none - * - * @return none - */ -void ets_run(void); -/** - * @brief Set the Idle callback, when Tasks are processed, will call the callback before CPU goto sleep. - * - * @param ets_idle_cb_t func : The callback function. - * - * @param void *arg : Argument of the callback. - * - * @return None - */ -void ets_set_idle_cb(ets_idle_cb_t func, void *arg); -/** - * @brief Init a task with processer, priority, queue to receive Event, queue length. - * - * @param ETSTask task : The task processer. - * - * @param uint8_t prio : Task priority, 0-31, bigger num with high priority, one priority with one task. - * - * @param ETSEvent *queue : Queue belongs to the task, task always receives Events, Queue is circular used. - * - * @param uint8_t qlen : Queue length. - * - * @return None - */ -void ets_task(ETSTask task, uint8_t prio, ETSEvent *queue, uint8_t qlen); -/** - * @brief Post an event to an Task. - * - * @param uint8_t prio : Priority of the Task. - * - * @param ETSSignal sig : Event signal. - * - * @param ETSParam par : Event parameter - * - * @return ETS_OK : post successful - * @return ETS_FAILED : post failed - */ -ETS_STATUS ets_post(uint8_t prio, ETSSignal sig, ETSParam par); /** * @} @@ -142,16 +89,6 @@ extern const char *const exc_cause_table[40]; ///**< excption cause that defin */ void ets_set_user_start(uint32_t start); -/** - * @brief Set Pro cpu Startup code, code can be called when booting is not completed, or in Entry code. - * When Entry code completed, CPU will call the Startup code if not NULL, else call ets_run. - * - * @param uint32_t callback : the Startup code address value in uint32_t - * - * @return None : post successful - */ -void ets_set_startup_callback(uint32_t callback); - /** * @brief Set App cpu Entry code, code can be called in PRO CPU. * When APP booting is completed, APP CPU will call the Entry code if not NULL. @@ -187,16 +124,6 @@ void ets_set_appcpu_boot_addr(uint32_t start); */ int ets_printf(const char *fmt, ...); -/** - * @brief Set the uart channel of ets_printf(uart_tx_one_char). - * ROM will set it base on the efuse and gpio setting, however, this can be changed after booting. - * - * @param uart_no : 0 for UART0, 1 for UART1, 2 for UART2. - * - * @return None - */ -void ets_set_printf_channel(uint8_t uart_no); - /** * @brief Get the uart channel of ets_printf(uart_tx_one_char). * @@ -375,17 +302,7 @@ void ets_delay_us(uint32_t us); */ void ets_update_cpu_frequency(uint32_t ticks_per_us); -/** - * @brief Set the real CPU ticks per us to the ets, so that ets_delay_us will be accurate. - * - * @note This function only sets the tick rate for the current CPU. It is located in ROM, - * so the deep sleep stub can use it even if IRAM is not initialized yet. - * - * @param uint32_t ticks_per_us : CPU ticks per us. - * - * @return None - */ -void ets_update_cpu_frequency_rom(uint32_t ticks_per_us); + /** * @brief Get the real CPU ticks per us to the ets. @@ -520,17 +437,6 @@ void ets_intr_lock(void); */ void ets_intr_unlock(void); -/** - * @brief Unlock the interrupt to level 0, and CPU will go into power save mode(wait interrupt). - * This function direct set the CPU registers. - * In FreeRTOS, please call FreeRTOS apis, never call this api. - * - * @param None - * - * @return None - */ -void ets_waiti0(void); - /** * @brief Attach an CPU interrupt to a hardware source. * We have 4 steps to use an interrupt: diff --git a/components/esp_rom/include/esp32s3/rom/secure_boot.h b/components/esp_rom/include/esp32s3/rom/secure_boot.h index 3c374fe3016..fde5e99102a 100644 --- a/components/esp_rom/include/esp32s3/rom/secure_boot.h +++ b/components/esp_rom/include/esp32s3/rom/secure_boot.h @@ -28,17 +28,6 @@ typedef enum { SB_FAILED = 0x7533885E, } secure_boot_status_t; -/* Verify bootloader image (reconfigures cache to map, - loads trusted key digests from efuse) - - If allow_key_revoke is true and aggressive revoke efuse is set, - any failed signature has its associated key revoked in efuse. - - If result is ETS_OK, the "simple hash" of the bootloader - is copied into verified_hash. -*/ -int ets_secure_boot_verify_bootloader(uint8_t *verified_hash, bool allow_key_revoke); - /* Verify bootloader image (reconfigures cache to map), with key digests provided as parameters.) diff --git a/components/esp_rom/include/esp32s3/rom/spi_flash.h b/components/esp_rom/include/esp32s3/rom/spi_flash.h index e5004a5eec1..069fc7dbf3b 100644 --- a/components/esp_rom/include/esp32s3/rom/spi_flash.h +++ b/components/esp_rom/include/esp32s3/rom/spi_flash.h @@ -364,20 +364,6 @@ esp_rom_spiflash_result_t esp_rom_spiflash_read(uint32_t src_addr, uint32_t *des */ void esp_rom_spiflash_write_encrypted_enable(void); -/** - * @brief Prepare 32 Bytes data to encrpto writing, you should Erase it yourself if need. - * Please do not call this function in SDK. - * - * @param uint32_t flash_addr : Address to write, should be 32 bytes aligned. - * - * @param uint32_t *data : The pointer to data which is to write. - * - * @return ESP_ROM_SPIFLASH_RESULT_OK : Prepare OK. - * ESP_ROM_SPIFLASH_RESULT_ERR : Prepare error. - * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Prepare timeout. - */ -esp_rom_spiflash_result_t esp_rom_spiflash_prepare_encrypted_data(uint32_t flash_addr, uint32_t *data); - /** * @brief SPI1 go out of encrypto mode. * Please do not call this function in SDK. diff --git a/components/esp_rom/include/esp32s3/rom/uart.h b/components/esp_rom/include/esp32s3/rom/uart.h index 0c45e92cb3f..3486886ad54 100644 --- a/components/esp_rom/include/esp32s3/rom/uart.h +++ b/components/esp_rom/include/esp32s3/rom/uart.h @@ -1,16 +1,8 @@ -// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2010-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once @@ -194,19 +186,6 @@ void Uart_Init(uint8_t uart_no, uint32_t clock); */ void uart_div_modify(uint8_t uart_no, uint32_t DivLatchValue); -/** - * @brief Init uart0 or uart1 for UART download booting mode. - * Please do not call this function in SDK. - * - * @param uint8_t uart_no : 0 for UART0, 1 for UART1. - * - * @param uint8_t is_sync : 0, only one UART module, easy to detect, wait until detected; - * 1, two UART modules, hard to detect, detect and return. - * - * @return None - */ -int uart_baudrate_detect(uint8_t uart_no, uint8_t is_sync); - /** * @brief Switch printf channel of uart_tx_one_char. * Please do not call this function when printf. @@ -217,16 +196,6 @@ int uart_baudrate_detect(uint8_t uart_no, uint8_t is_sync); */ void uart_tx_switch(uint8_t uart_no); -/** - * @brief Switch message exchange channel for UART download booting. - * Please do not call this function in SDK. - * - * @param uint8_t uart_no : 0 for UART0, 1 for UART1. - * - * @return None - */ -void uart_buff_switch(uint8_t uart_no); - /** * @brief Output a char to printf channel, wait until fifo not full. * @@ -298,16 +267,6 @@ char uart_rx_one_char_block(void); */ STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); -/** - * @brief Process uart recevied information in the interrupt handler. - * Please do not call this function in SDK. - * - * @param void *para : the message receive buffer. - * - * @return None - */ -void uart_rx_intr_handler(void *para); - /** * @brief Get an char from receive buffer. * Please do not call this function in SDK. @@ -321,17 +280,6 @@ void uart_rx_intr_handler(void *para); */ STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); -/** - * @brief Get all chars from receive buffer. - * Please do not call this function in SDK. - * - * @param uint8_t *pCmdLn : the pointer to store the string. - * - * @return OK for successful. - * FAIL for failed. - */ -STATUS UartGetCmdLn(uint8_t *pCmdLn); - /** * @brief Get uart configuration struct. * Please do not call this function in SDK. @@ -369,46 +317,6 @@ void send_packet(uint8_t *p, int len); */ int recv_packet(uint8_t *p, int len, uint8_t is_sync); -/** - * @brief Send an packet to download tool, with SLIP escaping. - * Please do not call this function in SDK. - * - * @param uint8_t *pData : the pointer to input string. - * - * @param uint16_t DataLen : the string length. - * - * @return OK for successful. - * FAIL for failed. - */ -STATUS SendMsg(uint8_t *pData, uint16_t DataLen); - -/** - * @brief Receive an packet from download tool, with SLIP escaping. - * Please do not call this function in SDK. - * - * @param uint8_t *pData : the pointer to input string. - * - * @param uint16_t MaxDataLen : If string length > MaxDataLen, the string will be truncated. - * - * @param uint8_t is_sync : 0, only one UART module; - * 1, two UART modules. - * - * @return OK for successful. - * FAIL for failed. - */ -STATUS RcvMsg(uint8_t *pData, uint16_t MaxDataLen, uint8_t is_sync); - -/** - * @brief Check if this UART is in download connection. - * Please do not call this function in SDK. - * - * @param uint8_t uart_no : 0 for UART0, 1 for UART1. - * - * @return ETS_NO_BOOT = 0 for no. - * SEL_UART_BOOT = BIT(1) for yes. - */ -uint8_t UartConnCheck(uint8_t uart_no); - /** * @brief Initialize the USB ACM UART * Needs to be fed a buffer of at least 128 bytes, plus any rx buffer you may want to have. @@ -418,13 +326,6 @@ uint8_t UartConnCheck(uint8_t uart_no); */ void Uart_Init_USB(void *cdc_acm_work_mem, int cdc_acm_work_mem_len); - -/** - * @brief Install handler to reset the chip when a RTS change has been detected on the CDC-ACM 'UART'. - */ -void uart_usb_enable_reset_on_rts(void); - - extern UartDevice UartDev; /** diff --git a/components/esp_rom/include/esp32s3/rom/usb/cdc_acm.h b/components/esp_rom/include/esp32s3/rom/usb/cdc_acm.h index 90d71e81772..04e313d8584 100644 --- a/components/esp_rom/include/esp32s3/rom/usb/cdc_acm.h +++ b/components/esp_rom/include/esp32s3/rom/usb/cdc_acm.h @@ -59,16 +59,6 @@ typedef void(*uart_irq_callback_t)(cdc_acm_device *dev, int status); int cdc_acm_rx_fifo_cnt(cdc_acm_device *dev); -/* - * @brief Poll the device for input. - * - * @return -ENOTSUP Since underlying USB device controller always uses - * interrupts, polled mode UART APIs are not implemented for the UART interface - * exported by CDC ACM driver. Apps should use fifo_read API instead. - */ - -int cdc_acm_poll_in(cdc_acm_device *dev, unsigned char *c); - /* * @brief Output a character in polled mode. * diff --git a/tools/ci/check_copyright_ignore.txt b/tools/ci/check_copyright_ignore.txt index 16db65e504c..468c20ae40a 100644 --- a/tools/ci/check_copyright_ignore.txt +++ b/tools/ci/check_copyright_ignore.txt @@ -485,26 +485,20 @@ components/esp_rom/include/esp32/rom/libc_stubs.h components/esp_rom/include/esp32/rom/sha.h components/esp_rom/include/esp32/rom/tbconsole.h components/esp_rom/include/esp32/rom/tjpgd.h -components/esp_rom/include/esp32c3/rom/aes.h components/esp_rom/include/esp32c3/rom/bigint.h -components/esp_rom/include/esp32c3/rom/cache.h components/esp_rom/include/esp32c3/rom/crc.h components/esp_rom/include/esp32c3/rom/digital_signature.h components/esp_rom/include/esp32c3/rom/esp_flash.h -components/esp_rom/include/esp32c3/rom/ets_sys.h components/esp_rom/include/esp32c3/rom/hmac.h components/esp_rom/include/esp32c3/rom/libc_stubs.h components/esp_rom/include/esp32c3/rom/rom_layout.h components/esp_rom/include/esp32c3/rom/rsa_pss.h components/esp_rom/include/esp32c3/rom/sha.h components/esp_rom/include/esp32c3/rom/tjpgd.h -components/esp_rom/include/esp32c3/rom/uart.h components/esp_rom/include/esp32s2/rom/aes.h components/esp_rom/include/esp32s2/rom/bigint.h components/esp_rom/include/esp32s2/rom/crc.h components/esp_rom/include/esp32s2/rom/digital_signature.h -components/esp_rom/include/esp32s2/rom/efuse.h -components/esp_rom/include/esp32s2/rom/ets_sys.h components/esp_rom/include/esp32s2/rom/hmac.h components/esp_rom/include/esp32s2/rom/libc_stubs.h components/esp_rom/include/esp32s2/rom/opi_flash.h @@ -522,12 +516,10 @@ components/esp_rom/include/esp32s2/rom/usb/usb_device.h components/esp_rom/include/esp32s2/rom/usb/usb_dfu.h components/esp_rom/include/esp32s2/rom/usb/usb_os_glue.h components/esp_rom/include/esp32s2/rom/usb/usb_persist.h -components/esp_rom/include/esp32s3/rom/aes.h components/esp_rom/include/esp32s3/rom/bigint.h components/esp_rom/include/esp32s3/rom/cache.h components/esp_rom/include/esp32s3/rom/crc.h components/esp_rom/include/esp32s3/rom/digital_signature.h -components/esp_rom/include/esp32s3/rom/ets_sys.h components/esp_rom/include/esp32s3/rom/hmac.h components/esp_rom/include/esp32s3/rom/libc_stubs.h components/esp_rom/include/esp32s3/rom/opi_flash.h @@ -535,7 +527,6 @@ components/esp_rom/include/esp32s3/rom/rom_layout.h components/esp_rom/include/esp32s3/rom/rsa_pss.h components/esp_rom/include/esp32s3/rom/sha.h components/esp_rom/include/esp32s3/rom/tjpgd.h -components/esp_rom/include/esp32s3/rom/uart.h components/esp_rom/include/esp32s3/rom/usb/cdc_acm.h components/esp_rom/include/esp32s3/rom/usb/chip_usb_dw_wrapper.h components/esp_rom/include/esp32s3/rom/usb/cpio.h