From 0fb0be381763332007c269a558e5df9b23f69c18 Mon Sep 17 00:00:00 2001 From: Armando Date: Fri, 24 Feb 2023 19:21:51 +0800 Subject: [PATCH] ld: fixed bootloader and app potential overlap issue --- .../subproject/main/ld/esp32c2/bootloader.ld | 8 ++++++++ .../subproject/main/ld/esp32c3/bootloader.ld | 8 ++++++++ .../subproject/main/ld/esp32c6/bootloader.ld | 13 +++++++++---- .../subproject/main/ld/esp32h2/bootloader.ld | 8 ++++++++ components/esp_system/ld/esp32c2/memory.ld.in | 2 +- components/esp_system/ld/esp32c3/memory.ld.in | 2 +- components/esp_system/ld/esp32c6/memory.ld.in | 2 +- components/esp_system/ld/esp32h2/memory.ld.in | 2 +- 8 files changed, 37 insertions(+), 8 deletions(-) diff --git a/components/bootloader/subproject/main/ld/esp32c2/bootloader.ld b/components/bootloader/subproject/main/ld/esp32c2/bootloader.ld index a95fd1ea463..e2502dee522 100644 --- a/components/bootloader/subproject/main/ld/esp32c2/bootloader.ld +++ b/components/bootloader/subproject/main/ld/esp32c2/bootloader.ld @@ -42,6 +42,14 @@ MEMORY dram_seg (RW) : org = bootloader_dram_seg_start, len = bootloader_dram_seg_len } +/* The app may use RAM for static allocations up to the start of iram_loader_seg. + * If you have changed something above and this assert fails: + * 1. Check what the new value of bootloader_iram_loader_seg start is. + * 2. Update the value in this assert. + * 3. Update (SRAM_DRAM_END + I_D_SRAM_OFFSET) in components/esp_system/ld/esp32c2/memory.ld.in to the same value. + */ +ASSERT(bootloader_iram_loader_seg_start == 0x403aeb70, "bootloader_iram_loader_seg_start inconsistent with SRAM_DRAM_END"); + /* Default entry point: */ ENTRY(call_start_cpu0); diff --git a/components/bootloader/subproject/main/ld/esp32c3/bootloader.ld b/components/bootloader/subproject/main/ld/esp32c3/bootloader.ld index bf3415f9106..68e3a1c38f0 100644 --- a/components/bootloader/subproject/main/ld/esp32c3/bootloader.ld +++ b/components/bootloader/subproject/main/ld/esp32c3/bootloader.ld @@ -42,6 +42,14 @@ MEMORY dram_seg (RW) : org = bootloader_dram_seg_start, len = bootloader_dram_seg_len } +/* The app may use RAM for static allocations up to the start of iram_loader_seg. + * If you have changed something above and this assert fails: + * 1. Check what the new value of bootloader_iram_loader_seg start is. + * 2. Update the value in this assert. + * 3. Update (SRAM_DRAM_END + I_D_SRAM_OFFSET) in components/esp_system/ld/esp32c3/memory.ld.in to the same value. + */ +ASSERT(bootloader_iram_loader_seg_start == 0x403ce710, "bootloader_iram_loader_seg_start inconsistent with SRAM_DRAM_END"); + /* Default entry point: */ ENTRY(call_start_cpu0); diff --git a/components/bootloader/subproject/main/ld/esp32c6/bootloader.ld b/components/bootloader/subproject/main/ld/esp32c6/bootloader.ld index ba4a1b2af96..8922baf6ce2 100644 --- a/components/bootloader/subproject/main/ld/esp32c6/bootloader.ld +++ b/components/bootloader/subproject/main/ld/esp32c6/bootloader.ld @@ -15,9 +15,6 @@ * buffers area (0x4087c610). */ -/* The offset between Dbus and Ibus. Used to convert between 0x403xxxxx and 0x3fcxxxxx addresses. */ -iram_dram_offset = 0x0; - /* We consider 0x4087c610 to be the last usable address for 2nd stage bootloader stack overhead, dram_seg, * and work out iram_seg and iram_loader_seg addresses from there, backwards. */ @@ -32,7 +29,7 @@ bootloader_iram_seg_len = 0x2100; /* Start of the lower region is determined by region size and the end of the higher region */ bootloader_dram_seg_end = bootloader_usable_dram_end - bootloader_stack_overhead; bootloader_dram_seg_start = bootloader_dram_seg_end - bootloader_dram_seg_len; -bootloader_iram_loader_seg_start = bootloader_dram_seg_start - bootloader_iram_loader_seg_len + iram_dram_offset; +bootloader_iram_loader_seg_start = bootloader_dram_seg_start - bootloader_iram_loader_seg_len; bootloader_iram_seg_start = bootloader_iram_loader_seg_start - bootloader_iram_seg_len; MEMORY @@ -42,6 +39,14 @@ MEMORY dram_seg (RW) : org = bootloader_dram_seg_start, len = bootloader_dram_seg_len } +/* The app may use RAM for static allocations up to the start of iram_loader_seg. + * If you have changed something above and this assert fails: + * 1. Check what the new value of bootloader_iram_loader_seg start is. + * 2. Update the value in this assert. + * 3. Update SRAM_DRAM_END in components/esp_system/ld/esp32c6/memory.ld.in to the same value. + */ +ASSERT(bootloader_iram_loader_seg_start == 0x4086E610, "bootloader_iram_loader_seg_start inconsistent with SRAM_DRAM_END"); + /* Default entry point: */ ENTRY(call_start_cpu0); diff --git a/components/bootloader/subproject/main/ld/esp32h2/bootloader.ld b/components/bootloader/subproject/main/ld/esp32h2/bootloader.ld index 2f7cea0b2d5..b40c4ed46ab 100644 --- a/components/bootloader/subproject/main/ld/esp32h2/bootloader.ld +++ b/components/bootloader/subproject/main/ld/esp32h2/bootloader.ld @@ -40,6 +40,14 @@ MEMORY dram_seg (RW) : org = bootloader_dram_seg_start, len = bootloader_dram_seg_len } +/* The app may use RAM for static allocations up to the start of iram_loader_seg. + * If you have changed something above and this assert fails: + * 1. Check what the new value of bootloader_iram_loader_seg start is. + * 2. Update the value in this assert. + * 3. Update SRAM_DRAM_END in components/esp_system/ld/esp32h2/memory.ld.in to the same value. + */ +ASSERT(bootloader_iram_loader_seg_start == 0x4083EFD0, "bootloader_iram_loader_seg_start inconsistent with SRAM_DRAM_END"); + /* Default entry point: */ ENTRY(call_start_cpu0); diff --git a/components/esp_system/ld/esp32c2/memory.ld.in b/components/esp_system/ld/esp32c2/memory.ld.in index 79ea40cdb3f..9a91b24f3d1 100644 --- a/components/esp_system/ld/esp32c2/memory.ld.in +++ b/components/esp_system/ld/esp32c2/memory.ld.in @@ -13,7 +13,7 @@ #define SRAM_DRAM_START 0x3FCA0000 #define ICACHE_SIZE 0x4000 /* ICache size is fixed to 16KB on ESP32-C2 */ #define I_D_SRAM_OFFSET (SRAM_IRAM_START - SRAM_DRAM_START + ICACHE_SIZE) -#define SRAM_DRAM_END 0x403B0000 - I_D_SRAM_OFFSET /* 2nd stage bootloader iram_loader_seg start address */ +#define SRAM_DRAM_END 0x403AEB70 - I_D_SRAM_OFFSET /* 2nd stage bootloader iram_loader_seg start address */ #define SRAM_IRAM_ORG (SRAM_IRAM_START + ICACHE_SIZE) #define SRAM_DRAM_ORG (SRAM_DRAM_START) diff --git a/components/esp_system/ld/esp32c3/memory.ld.in b/components/esp_system/ld/esp32c3/memory.ld.in index cdf136d2cfb..b16f855b1f3 100644 --- a/components/esp_system/ld/esp32c3/memory.ld.in +++ b/components/esp_system/ld/esp32c3/memory.ld.in @@ -31,7 +31,7 @@ #define SRAM_DRAM_START 0x3FC7C000 #define ICACHE_SIZE 0x4000 /* ICache size is fixed to 16KB on ESP32-C3 */ #define I_D_SRAM_OFFSET (SRAM_IRAM_START - SRAM_DRAM_START) -#define SRAM_DRAM_END 0x403CF600 - I_D_SRAM_OFFSET /* 2nd stage bootloader iram_loader_seg start address */ +#define SRAM_DRAM_END 0x403CE710 - I_D_SRAM_OFFSET /* 2nd stage bootloader iram_loader_seg start address */ #define SRAM_IRAM_ORG (SRAM_IRAM_START + ICACHE_SIZE) #define SRAM_DRAM_ORG (SRAM_DRAM_START + ICACHE_SIZE) diff --git a/components/esp_system/ld/esp32c6/memory.ld.in b/components/esp_system/ld/esp32c6/memory.ld.in index 686a964df01..86a0c117e1d 100644 --- a/components/esp_system/ld/esp32c6/memory.ld.in +++ b/components/esp_system/ld/esp32c6/memory.ld.in @@ -31,7 +31,7 @@ #define SRAM_DRAM_START 0x40800000 #define I_D_SRAM_OFFSET (SRAM_IRAM_START - SRAM_DRAM_START) -#define SRAM_DRAM_END 0x40880000 - I_D_SRAM_OFFSET /* 2nd stage bootloader iram_loader_seg start address */ +#define SRAM_DRAM_END 0x4086E610 - I_D_SRAM_OFFSET /* 2nd stage bootloader iram_loader_seg start address */ #define SRAM_IRAM_ORG (SRAM_IRAM_START) #define SRAM_DRAM_ORG (SRAM_DRAM_START) diff --git a/components/esp_system/ld/esp32h2/memory.ld.in b/components/esp_system/ld/esp32h2/memory.ld.in index 36887dcfbc9..83f4b5ce007 100644 --- a/components/esp_system/ld/esp32h2/memory.ld.in +++ b/components/esp_system/ld/esp32h2/memory.ld.in @@ -31,7 +31,7 @@ #define SRAM_DRAM_START 0x40800000 #define I_D_SRAM_OFFSET (SRAM_IRAM_START - SRAM_DRAM_START) -#define SRAM_DRAM_END 0x40850000 - I_D_SRAM_OFFSET /* 2nd stage bootloader iram_loader_seg start address */ +#define SRAM_DRAM_END 0x4083EFD0 - I_D_SRAM_OFFSET /* 2nd stage bootloader iram_loader_seg start address */ #define SRAM_IRAM_ORG (SRAM_IRAM_START) #define SRAM_DRAM_ORG (SRAM_DRAM_START)