From 5998130eb98f605969b799c8de56db0f265b0bf8 Mon Sep 17 00:00:00 2001 From: cje Date: Tue, 30 Aug 2022 11:32:07 +0800 Subject: [PATCH] sleep: fix sleep time inaccurate bug when select 8MD256 as rtc slow clock on ESP32 Related to: https://github.com/espressif/esp-idf/issues/6687 --- components/esp_hw_support/port/esp32/rtc_sleep.c | 4 +++- components/soc/esp32/include/soc/rtc.h | 1 + components/soc/esp32/include/soc/rtc_cntl_reg.h | 1 + 3 files changed, 5 insertions(+), 1 deletion(-) diff --git a/components/esp_hw_support/port/esp32/rtc_sleep.c b/components/esp_hw_support/port/esp32/rtc_sleep.c index b341165c56d..2a9981c9349 100644 --- a/components/esp_hw_support/port/esp32/rtc_sleep.c +++ b/components/esp_hw_support/port/esp32/rtc_sleep.c @@ -108,11 +108,13 @@ void rtc_sleep_get_default_config(uint32_t sleep_flags, rtc_sleep_config_t *out_ out_config->dig_dbias_slp = RTC_CNTL_DBIAS_0V90; out_config->rtc_dbias_wak = RTC_CNTL_DBIAS_1V10; out_config->rtc_dbias_slp = RTC_CNTL_DBIAS_0V90; + out_config->dbg_atten_slp = !(sleep_flags & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBG_ATTEN_NODROP : RTC_CNTL_DBG_ATTEN_DEFAULT; } else { out_config->dig_dbias_wak = RTC_CNTL_DBIAS_1V10; out_config->dig_dbias_slp = !((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBIAS_1V10 : RTC_CNTL_DBIAS_0V90; out_config->rtc_dbias_wak = RTC_CNTL_DBIAS_1V10; out_config->rtc_dbias_slp = !((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBIAS_1V10 : RTC_CNTL_DBIAS_0V90; + out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_NODROP; } } @@ -207,7 +209,6 @@ void rtc_sleep_init(rtc_sleep_config_t cfg) CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BB_I2C_FORCE_PU); } else { CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN); - REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN, 0); } REG_SET_FIELD(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_XTL_FORCE_PU, cfg.xtal_fpu); @@ -226,6 +227,7 @@ void rtc_sleep_init(rtc_sleep_config_t cfg) REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_WAK, cfg.rtc_dbias_wak); REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, cfg.dig_dbias_wak); REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_SLP, cfg.dig_dbias_slp); + REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN, cfg.dbg_atten_slp); } void rtc_sleep_low_init(uint32_t slowclk_period) diff --git a/components/soc/esp32/include/soc/rtc.h b/components/soc/esp32/include/soc/rtc.h index 9819fcdcf23..3a5ad9de5e2 100644 --- a/components/soc/esp32/include/soc/rtc.h +++ b/components/soc/esp32/include/soc/rtc.h @@ -514,6 +514,7 @@ typedef struct rtc_sleep_config_s { uint32_t lslp_meminf_pd : 1; //!< remove all peripheral force power up flags uint32_t vddsdio_pd_en : 1; //!< power down VDDSDIO regulator uint32_t xtal_fpu : 1; //!< keep main XTAL powered up in sleep + uint32_t dbg_atten_slp : 2; //!< voltage parameter } rtc_sleep_config_t; #define RTC_SLEEP_PD_DIG BIT(0) //!< Deep sleep (power down digital domain) diff --git a/components/soc/esp32/include/soc/rtc_cntl_reg.h b/components/soc/esp32/include/soc/rtc_cntl_reg.h index 36945aefbb4..5afc1aef27a 100644 --- a/components/soc/esp32/include/soc/rtc_cntl_reg.h +++ b/components/soc/esp32/include/soc/rtc_cntl_reg.h @@ -1070,6 +1070,7 @@ #define RTC_CNTL_DBG_ATTEN_V 0x3 #define RTC_CNTL_DBG_ATTEN_S 24 #define RTC_CNTL_DBG_ATTEN_DEFAULT 3 +#define RTC_CNTL_DBG_ATTEN_NODROP 0 #define RTC_CNTL_REG (DR_REG_RTCCNTL_BASE + 0x7c) /* RTC_CNTL_FORCE_PU : R/W ;bitpos:[31] ;default: 1'd1 ; */ /*description: RTC_REG force power up*/