From 3dcdcc08eb54ca9cfdae17d760580e06001b2f17 Mon Sep 17 00:00:00 2001 From: KonstantinKondrashov Date: Thu, 26 May 2022 03:16:15 +0800 Subject: [PATCH 1/3] efuse: Adds major and minor versions and others --- .../subproject/main/ld/esp32/bootloader.ld | 3 +- .../subproject/main/ld/esp32c3/bootloader.ld | 3 +- .../subproject/main/ld/esp32s2/bootloader.ld | 3 +- .../subproject/main/ld/esp32s3/bootloader.ld | 3 +- components/bootloader_support/CMakeLists.txt | 2 +- .../include/bootloader_common.h | 7 - .../src/bootloader_clock_init.c | 4 +- .../src/bootloader_common_loader.c | 13 +- .../bootloader_support/src/bootloader_efuse.c | 34 ++ .../src/bootloader_efuse_esp32.c | 64 --- .../src/bootloader_efuse_esp32c3.c | 29 -- .../src/bootloader_efuse_esp32s2.c | 32 -- .../src/bootloader_efuse_esp32s3.c | 29 -- .../src/bootloader_flash_config_esp32.c | 3 +- .../bootloader_support/src/bootloader_init.c | 8 +- .../src/esp32c3/bootloader_esp32c3.c | 5 +- components/driver/i2s.c | 4 +- components/efuse/esp32/esp_efuse_table.c | 11 +- components/efuse/esp32/esp_efuse_table.csv | 1 + .../efuse/esp32/include/esp_efuse_table.h | 3 +- components/efuse/esp32c3/esp_efuse_table.c | 55 ++- components/efuse/esp32c3/esp_efuse_table.csv | 80 ++-- .../efuse/esp32c3/include/esp_efuse_table.h | 11 +- components/efuse/esp32s2/esp_efuse_table.c | 55 ++- components/efuse/esp32s2/esp_efuse_table.csv | 63 +-- .../efuse/esp32s2/include/esp_efuse_table.h | 11 +- components/efuse/esp32s3/esp_efuse_table.c | 220 +++++++++- components/efuse/esp32s3/esp_efuse_table.csv | 79 +++- .../efuse/esp32s3/include/esp_efuse_table.h | 30 +- components/efuse/include/esp_efuse.h | 7 - components/efuse/src/esp32/esp_efuse_fields.c | 32 +- .../efuse/src/esp32c3/esp_efuse_fields.c | 8 - .../efuse/src/esp32c3/esp_efuse_rtc_calib.c | 2 +- .../efuse/src/esp32s2/esp_efuse_fields.c | 9 - .../efuse/src/esp32s2/esp_efuse_rtc_table.c | 2 +- .../efuse/src/esp32s3/esp_efuse_fields.c | 9 - components/efuse/test/test_efuse.c | 6 - components/esp32/system_api_esp32.c | 12 +- components/esp32c3/ld/esp32c3.peripherals.ld | 1 + components/esp32c3/system_api_esp32c3.c | 4 +- components/esp32s2/ld/esp32s2.peripherals.ld | 1 + components/esp32s2/system_api_esp32s2.c | 5 +- components/esp32s3/ld/esp32s3.peripherals.ld | 1 + components/esp32s3/system_api_esp32s3.c | 2 + .../esp_hw_support/port/esp32/rtc_clk.c | 13 +- .../esp_hw_support/port/esp32/rtc_init.c | 3 +- .../esp_hw_support/port/esp32c3/rtc_init.c | 5 +- .../esp_hw_support/port/esp32c3/rtc_sleep.c | 4 +- .../esp_hw_support/port/esp32s2/rtc_init.c | 2 +- components/esp_system/include/esp_system.h | 1 + components/esp_wifi/src/phy_init.c | 3 +- components/hal/CMakeLists.txt | 4 +- components/hal/efuse_hal.c | 17 + components/hal/esp32/efuse_hal.c | 58 +++ components/hal/esp32/include/hal/efuse_hal.h | 26 ++ components/hal/esp32/include/hal/efuse_ll.h | 212 +++++++++ components/hal/esp32c3/efuse_hal.c | 21 + components/hal/esp32c3/include/hal/efuse_ll.h | 132 ++++++ components/hal/esp32s2/efuse_hal.c | 21 + components/hal/esp32s2/include/hal/efuse_ll.h | 152 +++++++ components/hal/esp32s3/efuse_hal.c | 21 + components/hal/esp32s3/include/hal/efuse_ll.h | 132 ++++++ components/hal/include/hal/efuse_hal.h | 36 ++ components/soc/esp32/include/soc/efuse_reg.h | 29 +- .../soc/esp32/include/soc/efuse_struct.h | 7 + .../soc/esp32c3/include/soc/efuse_reg.h | 3 + .../soc/esp32c3/include/soc/efuse_struct.h | 27 +- .../soc/esp32s2/include/soc/efuse_reg.h | 3 + .../soc/esp32s2/include/soc/efuse_struct.h | 36 +- .../soc/esp32s3/include/soc/efuse_reg.h | 3 + .../soc/esp32s3/include/soc/efuse_struct.h | 409 +++++++++++++----- components/soc/include/soc/efuse_periph.h | 1 + docs/en/api-reference/system/efuse.rst | 2 +- .../cmake/idf_as_lib/stubs/esp32/esp_system.h | 2 +- 74 files changed, 1813 insertions(+), 538 deletions(-) create mode 100644 components/bootloader_support/src/bootloader_efuse.c delete mode 100644 components/bootloader_support/src/bootloader_efuse_esp32.c delete mode 100644 components/bootloader_support/src/bootloader_efuse_esp32c3.c delete mode 100644 components/bootloader_support/src/bootloader_efuse_esp32s2.c delete mode 100644 components/bootloader_support/src/bootloader_efuse_esp32s3.c create mode 100644 components/hal/efuse_hal.c create mode 100644 components/hal/esp32/efuse_hal.c create mode 100644 components/hal/esp32/include/hal/efuse_hal.h create mode 100644 components/hal/esp32/include/hal/efuse_ll.h create mode 100644 components/hal/esp32c3/efuse_hal.c create mode 100644 components/hal/esp32c3/include/hal/efuse_ll.h create mode 100644 components/hal/esp32s2/efuse_hal.c create mode 100644 components/hal/esp32s2/include/hal/efuse_ll.h create mode 100644 components/hal/esp32s3/efuse_hal.c create mode 100644 components/hal/esp32s3/include/hal/efuse_ll.h create mode 100644 components/hal/include/hal/efuse_hal.h create mode 100644 components/soc/esp32/include/soc/efuse_struct.h diff --git a/components/bootloader/subproject/main/ld/esp32/bootloader.ld b/components/bootloader/subproject/main/ld/esp32/bootloader.ld index 5239a21041c..cf0bcb17f1b 100644 --- a/components/bootloader/subproject/main/ld/esp32/bootloader.ld +++ b/components/bootloader/subproject/main/ld/esp32/bootloader.ld @@ -43,7 +43,7 @@ SECTIONS *libbootloader_support.a:bootloader_flash.*(.literal .text .literal.* .text.*) *libbootloader_support.a:bootloader_random.*(.literal .text .literal.* .text.*) *libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable) - *libbootloader_support.a:bootloader_efuse_esp32.*(.literal .text .literal.* .text.*) + *libbootloader_support.a:bootloader_efuse.*(.literal .text .literal.* .text.*) *libbootloader_support.a:bootloader_utility.*(.literal .text .literal.* .text.*) *libbootloader_support.a:bootloader_sha.*(.literal .text .literal.* .text.*) *libbootloader_support.a:bootloader_console_loader.*(.literal .text .literal.* .text.*) @@ -57,6 +57,7 @@ SECTIONS *libmicro-ecc.a:*.*(.literal .text .literal.* .text.*) *libspi_flash.a:*.*(.literal .text .literal.* .text.*) *libhal.a:wdt_hal_iram.*(.literal .text .literal.* .text.*) + *libhal.a:efuse_hal.*(.literal .text .literal.* .text.*) *libesp_hw_support.a:rtc_clk.*(.literal .text .literal.* .text.*) *libesp_hw_support.a:rtc_time.*(.literal .text .literal.* .text.*) *libefuse.a:*.*(.literal .text .literal.* .text.*) diff --git a/components/bootloader/subproject/main/ld/esp32c3/bootloader.ld b/components/bootloader/subproject/main/ld/esp32c3/bootloader.ld index 5b2d4652dc9..6c655a03dc2 100644 --- a/components/bootloader/subproject/main/ld/esp32c3/bootloader.ld +++ b/components/bootloader/subproject/main/ld/esp32c3/bootloader.ld @@ -31,7 +31,7 @@ SECTIONS *libbootloader_support.a:bootloader_random.*(.literal .text .literal.* .text.*) *libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable) *libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_enable .text.bootloader_random_enable) - *libbootloader_support.a:bootloader_efuse_esp32c3.*(.literal .text .literal.* .text.*) + *libbootloader_support.a:bootloader_efuse.*(.literal .text .literal.* .text.*) *libbootloader_support.a:bootloader_utility.*(.literal .text .literal.* .text.*) *libbootloader_support.a:bootloader_sha.*(.literal .text .literal.* .text.*) *libbootloader_support.a:bootloader_console_loader.*(.literal .text .literal.* .text.*) @@ -45,6 +45,7 @@ SECTIONS *libmicro-ecc.a:*.*(.literal .text .literal.* .text.*) *libspi_flash.a:*.*(.literal .text .literal.* .text.*) *libhal.a:wdt_hal_iram.*(.literal .text .literal.* .text.*) + *libhal.a:efuse_hal.*(.literal .text .literal.* .text.*) *libesp_hw_support.a:rtc_clk.*(.literal .text .literal.* .text.*) *libesp_hw_support.a:rtc_time.*(.literal .text .literal.* .text.*) *libesp_hw_support.a:regi2c_ctrl.*(.literal .text .literal.* .text.*) diff --git a/components/bootloader/subproject/main/ld/esp32s2/bootloader.ld b/components/bootloader/subproject/main/ld/esp32s2/bootloader.ld index 8abe507a936..6190e3bdffa 100644 --- a/components/bootloader/subproject/main/ld/esp32s2/bootloader.ld +++ b/components/bootloader/subproject/main/ld/esp32s2/bootloader.ld @@ -30,7 +30,7 @@ SECTIONS *libbootloader_support.a:bootloader_flash.*(.literal .text .literal.* .text.*) *libbootloader_support.a:bootloader_random.*(.literal .text .literal.* .text.*) *libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable) - *libbootloader_support.a:bootloader_efuse_esp32s2.*(.literal .text .literal.* .text.*) + *libbootloader_support.a:bootloader_efuse.*(.literal .text .literal.* .text.*) *libbootloader_support.a:bootloader_utility.*(.literal .text .literal.* .text.*) *libbootloader_support.a:bootloader_sha.*(.literal .text .literal.* .text.*) *libbootloader_support.a:bootloader_console_loader.*(.literal .text .literal.* .text.*) @@ -44,6 +44,7 @@ SECTIONS *libmicro-ecc.a:*.*(.literal .text .literal.* .text.*) *libspi_flash.a:*.*(.literal .text .literal.* .text.*) *libhal.a:wdt_hal_iram.*(.literal .text .literal.* .text.*) + *libhal.a:efuse_hal.*(.literal .text .literal.* .text.*) *libesp_hw_support.a:rtc_clk.*(.literal .text .literal.* .text.*) *libesp_hw_support.a:rtc_time.*(.literal .text .literal.* .text.*) *libesp_hw_support.a:regi2c_ctrl.*(.literal .text .literal.* .text.*) diff --git a/components/bootloader/subproject/main/ld/esp32s3/bootloader.ld b/components/bootloader/subproject/main/ld/esp32s3/bootloader.ld index 61a88619068..a1467b4032b 100644 --- a/components/bootloader/subproject/main/ld/esp32s3/bootloader.ld +++ b/components/bootloader/subproject/main/ld/esp32s3/bootloader.ld @@ -31,7 +31,7 @@ SECTIONS *libbootloader_support.a:bootloader_random.*(.literal .text .literal.* .text.*) *libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable) *libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_enable .text.bootloader_random_enable) - *libbootloader_support.a:bootloader_efuse_esp32s3.*(.literal .text .literal.* .text.*) + *libbootloader_support.a:bootloader_efuse.*(.literal .text .literal.* .text.*) *libbootloader_support.a:bootloader_utility.*(.literal .text .literal.* .text.*) *libbootloader_support.a:bootloader_sha.*(.literal .text .literal.* .text.*) *libbootloader_support.a:bootloader_console_loader.*(.literal .text .literal.* .text.*) @@ -45,6 +45,7 @@ SECTIONS *libmicro-ecc.a:*.*(.literal .text .literal.* .text.*) *libspi_flash.a:*.*(.literal .text .literal.* .text.*) *libhal.a:wdt_hal_iram.*(.literal .text .literal.* .text.*) + *libhal.a:efuse_hal.*(.literal .text .literal.* .text.*) *libesp_hw_support.a:rtc_clk.*(.literal .text .literal.* .text.*) *libesp_hw_support.a:rtc_time.*(.literal .text .literal.* .text.*) *libesp_hw_support.a:regi2c_ctrl.*(.literal .text .literal.* .text.*) diff --git a/components/bootloader_support/CMakeLists.txt b/components/bootloader_support/CMakeLists.txt index 74a5b468c25..df7cdfe5476 100644 --- a/components/bootloader_support/CMakeLists.txt +++ b/components/bootloader_support/CMakeLists.txt @@ -13,7 +13,7 @@ set(srcs "src/flash_partitions.c" "src/flash_qio_mode.c" "src/bootloader_flash_config_${IDF_TARGET}.c" - "src/bootloader_efuse_${IDF_TARGET}.c" + "src/bootloader_efuse.c" ) if(BOOTLOADER_BUILD) diff --git a/components/bootloader_support/include/bootloader_common.h b/components/bootloader_support/include/bootloader_common.h index 6b04f595338..d6bf470042f 100644 --- a/components/bootloader_support/include/bootloader_common.h +++ b/components/bootloader_support/include/bootloader_common.h @@ -173,13 +173,6 @@ int bootloader_common_select_otadata(const esp_ota_select_entry_t *two_otadata, */ esp_err_t bootloader_common_get_partition_description(const esp_partition_pos_t *partition, esp_app_desc_t *app_desc); -/** - * @brief Get chip revision - * - * @return Chip revision number - */ -uint8_t bootloader_common_get_chip_revision(void); - /** * @brief Get chip package * diff --git a/components/bootloader_support/src/bootloader_clock_init.c b/components/bootloader_support/src/bootloader_clock_init.c index dee8bf201b3..56b45a220ad 100644 --- a/components/bootloader_support/src/bootloader_clock_init.c +++ b/components/bootloader_support/src/bootloader_clock_init.c @@ -31,6 +31,7 @@ #elif CONFIG_IDF_TARGET_ESP32C3 #include "esp32c3/rom/rtc.h" #endif +#include "hal/efuse_hal.h" #include "esp_rom_uart.h" __attribute__((weak)) void bootloader_clock_configure(void) @@ -51,8 +52,7 @@ __attribute__((weak)) void bootloader_clock_configure(void) * document). For rev. 0, switch to 240 instead if it has been enabled * previously. */ - uint32_t chip_ver_reg = REG_READ(EFUSE_BLK0_RDATA3_REG); - if ((chip_ver_reg & EFUSE_RD_CHIP_VER_REV1_M) == 0 && + if (efuse_hal_get_major_chip_version() == 0 && DPORT_REG_GET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL) == DPORT_CPUPERIOD_SEL_240) { cpu_freq_mhz = 240; } diff --git a/components/bootloader_support/src/bootloader_common_loader.c b/components/bootloader_support/src/bootloader_common_loader.c index b8d426840df..b0ded892118 100644 --- a/components/bootloader_support/src/bootloader_common_loader.c +++ b/components/bootloader_support/src/bootloader_common_loader.c @@ -31,6 +31,7 @@ #include "soc/rtc.h" #include "soc/efuse_reg.h" #include "soc/soc_memory_layout.h" +#include "hal/efuse_hal.h" #include "hal/gpio_ll.h" #include "esp_image_format.h" #include "bootloader_sha.h" @@ -75,7 +76,15 @@ esp_err_t bootloader_common_check_chip_validity(const esp_image_header_t* img_hd ESP_LOGE(TAG, "mismatch chip ID, expected %d, found %d", chip_id, img_hdr->chip_id); err = ESP_FAIL; } - uint8_t revision = bootloader_common_get_chip_revision(); + +#ifndef CONFIG_IDF_ENV_FPGA +#if defined(CONFIG_IDF_TARGET_ESP32) || defined(CONFIG_IDF_TARGET_ESP32S2) + uint8_t revision = efuse_hal_get_major_chip_version(); + // min_chip_rev keeps the MAJOR wafer version for these chips +#else + uint8_t revision = efuse_hal_get_minor_chip_version(); + // min_chip_rev keeps the MINOR wafer version for these chips +#endif if (revision < img_hdr->min_chip_rev) { /* To fix this error, please update mininum supported chip revision from configuration, * located in TARGET (e.g. ESP32) specific options under "Component config" menu */ @@ -86,6 +95,8 @@ esp_err_t bootloader_common_check_chip_validity(const esp_image_header_t* img_hd ESP_LOGI(TAG, "chip revision: %d, min. %s chip revision: %d", revision, type == ESP_IMAGE_BOOTLOADER ? "bootloader" : "application", img_hdr->min_chip_rev); #endif } +#endif // CONFIG_IDF_ENV_FPGA + return err; } diff --git a/components/bootloader_support/src/bootloader_efuse.c b/components/bootloader_support/src/bootloader_efuse.c new file mode 100644 index 00000000000..b34a8208d6e --- /dev/null +++ b/components/bootloader_support/src/bootloader_efuse.c @@ -0,0 +1,34 @@ +/* + * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include "sdkconfig.h" +#include "bootloader_common.h" +#include "hal/efuse_ll.h" +#include "hal/efuse_hal.h" +#include "esp_attr.h" + +IRAM_ATTR uint32_t bootloader_common_get_chip_ver_pkg(void) +{ + return efuse_ll_get_chip_ver_pkg(); +} + +int bootloader_clock_get_rated_freq_mhz(void) +{ +#ifdef CONFIG_IDF_TARGET_ESP32 + return efuse_hal_get_rated_freq_mhz(); + +#elif CONFIG_IDF_TARGET_ESP32C3 + return 160; + +#elif CONFIG_IDF_TARGET_ESP32S2 + return 240; + +#elif CONFIG_IDF_TARGET_ESP32S3 + return 240; + +#endif +} diff --git a/components/bootloader_support/src/bootloader_efuse_esp32.c b/components/bootloader_support/src/bootloader_efuse_esp32.c deleted file mode 100644 index 8fde5369150..00000000000 --- a/components/bootloader_support/src/bootloader_efuse_esp32.c +++ /dev/null @@ -1,64 +0,0 @@ -// Copyright 2019 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -#include "bootloader_common.h" -#include "bootloader_clock.h" -#include "soc/efuse_reg.h" -#include "soc/apb_ctrl_reg.h" -#include "esp_attr.h" - -IRAM_ATTR uint8_t bootloader_common_get_chip_revision(void) -{ - uint8_t eco_bit0, eco_bit1, eco_bit2; - eco_bit0 = (REG_READ(EFUSE_BLK0_RDATA3_REG) & 0xF000) >> 15; - eco_bit1 = (REG_READ(EFUSE_BLK0_RDATA5_REG) & 0x100000) >> 20; - eco_bit2 = (REG_READ(APB_CTRL_DATE_REG) & 0x80000000) >> 31; - uint32_t combine_value = (eco_bit2 << 2) | (eco_bit1 << 1) | eco_bit0; - uint8_t chip_ver = 0; - switch (combine_value) { - case 0: - chip_ver = 0; - break; - case 1: - chip_ver = 1; - break; - case 3: - chip_ver = 2; - break; - case 7: - chip_ver = 3; - break; - default: - chip_ver = 0; - break; - } - return chip_ver; -} - -IRAM_ATTR uint32_t bootloader_common_get_chip_ver_pkg(void) -{ - uint32_t pkg_version = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_PKG); - uint32_t pkg_version_4bit = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_PKG_4BIT); - return (pkg_version_4bit << 3) | pkg_version; -} - -int bootloader_clock_get_rated_freq_mhz() -{ - //Check if ESP32 is rated for a CPU frequency of 160MHz only - if (REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_CPU_FREQ_RATED) && - REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_CPU_FREQ_LOW)) { - return 160; - } - return 240; -} diff --git a/components/bootloader_support/src/bootloader_efuse_esp32c3.c b/components/bootloader_support/src/bootloader_efuse_esp32c3.c deleted file mode 100644 index 504c7e62be9..00000000000 --- a/components/bootloader_support/src/bootloader_efuse_esp32c3.c +++ /dev/null @@ -1,29 +0,0 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -#include -#include "soc/efuse_reg.h" -#include "esp_attr.h" - -IRAM_ATTR uint8_t bootloader_common_get_chip_revision(void) -{ - // should return the same value as esp_efuse_get_chip_ver() - return REG_GET_FIELD(EFUSE_RD_MAC_SPI_SYS_3_REG, EFUSE_WAFER_VERSION); -} - -IRAM_ATTR uint32_t bootloader_common_get_chip_ver_pkg(void) -{ - // should return the same value as esp_efuse_get_pkg_ver() - return REG_GET_FIELD(EFUSE_RD_MAC_SPI_SYS_3_REG, EFUSE_PKG_VERSION); -} diff --git a/components/bootloader_support/src/bootloader_efuse_esp32s2.c b/components/bootloader_support/src/bootloader_efuse_esp32s2.c deleted file mode 100644 index f0546336234..00000000000 --- a/components/bootloader_support/src/bootloader_efuse_esp32s2.c +++ /dev/null @@ -1,32 +0,0 @@ -// Copyright 2019 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -#include "sdkconfig.h" -#include "bootloader_clock.h" -#include "bootloader_common.h" -#include "soc/efuse_reg.h" -#include "esp_attr.h" - -IRAM_ATTR uint8_t bootloader_common_get_chip_revision(void) -{ - // should return the same value as esp_efuse_get_chip_ver() - return REG_GET_FIELD(EFUSE_RD_MAC_SPI_SYS_3_REG, EFUSE_WAFER_VERSION); - return 0; -} - -IRAM_ATTR uint32_t bootloader_common_get_chip_ver_pkg(void) -{ - // should return the same value as esp_efuse_get_pkg_ver() - return REG_GET_FIELD(EFUSE_RD_MAC_SPI_SYS_4_REG, EFUSE_PKG_VERSION); -} diff --git a/components/bootloader_support/src/bootloader_efuse_esp32s3.c b/components/bootloader_support/src/bootloader_efuse_esp32s3.c deleted file mode 100644 index 8a816ec7112..00000000000 --- a/components/bootloader_support/src/bootloader_efuse_esp32s3.c +++ /dev/null @@ -1,29 +0,0 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -#include -#include "esp_attr.h" - -IRAM_ATTR uint8_t bootloader_common_get_chip_revision(void) -{ - // should return the same value as esp_efuse_get_chip_ver() - /* No other revisions for ESP32-S3 */ - return 0; -} - -IRAM_ATTR uint32_t bootloader_common_get_chip_ver_pkg(void) -{ - // should return the same value as esp_efuse_get_pkg_ver() - return 0; -} diff --git a/components/bootloader_support/src/bootloader_flash_config_esp32.c b/components/bootloader_support/src/bootloader_flash_config_esp32.c index f1eef822346..f059a9525d2 100644 --- a/components/bootloader_support/src/bootloader_flash_config_esp32.c +++ b/components/bootloader_support/src/bootloader_flash_config_esp32.c @@ -25,6 +25,7 @@ #include "soc/spi_reg.h" #include "soc/soc_caps.h" #include "soc/soc_pins.h" +#include "hal/efuse_hal.h" #include "hal/gpio_hal.h" #include "flash_qio_mode.h" #include "bootloader_common.h" @@ -184,7 +185,7 @@ int bootloader_flash_get_wp_pin(void) return ESP32_D2WD_WP_GPIO; case EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4: /* Same package IDs are used for ESP32-PICO-V3 and ESP32-PICO-D4, silicon version differentiates */ - chip_ver = bootloader_common_get_chip_revision(); + chip_ver = efuse_hal_get_major_chip_version(); return (chip_ver < 3) ? ESP32_D2WD_WP_GPIO : ESP32_PICO_V3_GPIO; case EFUSE_RD_CHIP_VER_PKG_ESP32PICOV302: return ESP32_PICO_V3_GPIO; diff --git a/components/bootloader_support/src/bootloader_init.c b/components/bootloader_support/src/bootloader_init.c index d662f2d32c9..17c7d9e2a7e 100644 --- a/components/bootloader_support/src/bootloader_init.c +++ b/components/bootloader_support/src/bootloader_init.c @@ -26,6 +26,7 @@ #include "soc/cpu.h" #include "soc/rtc.h" #include "hal/wdt_hal.h" +#include "hal/efuse_hal.h" static const char *TAG = "boot"; @@ -48,9 +49,10 @@ esp_err_t bootloader_read_bootloader_header(void) esp_err_t bootloader_check_bootloader_validity(void) { - /* read chip revision from efuse */ - uint8_t revision = bootloader_common_get_chip_revision(); - ESP_LOGI(TAG, "chip revision: %d", revision); + unsigned revision = efuse_hal_chip_revision(); + unsigned major = revision / 100; + unsigned minor = revision % 100; + ESP_LOGI(TAG, "chip revision: v%d.%d", major, minor); /* compare with the one set in bootloader image header */ if (bootloader_common_check_chip_validity(&bootloader_image_hdr, ESP_IMAGE_BOOTLOADER) != ESP_OK) { return ESP_FAIL; diff --git a/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c b/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c index 3badb94945a..8819737fb84 100644 --- a/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c +++ b/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c @@ -46,6 +46,7 @@ #include "bootloader_console.h" #include "bootloader_flash_priv.h" #include "bootloader_soc.h" +#include "hal/efuse_hal.h" static const char *TAG = "boot.esp32c3"; @@ -267,7 +268,7 @@ static inline void bootloader_hardware_init(void) { // This check is always included in the bootloader so it can // print the minimum revision error message later in the boot - if (bootloader_common_get_chip_revision() < 3) { + if (efuse_hal_get_minor_chip_version() < 3) { REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_XPD_IPH, 1); REGI2C_WRITE_MASK(I2C_BIAS, I2C_BIAS_DREG_1P1_PVT, 12); } @@ -280,7 +281,7 @@ static inline void bootloader_ana_reset_config(void) For ECO2: fix brownout reset bug, support swt & brownout reset; For ECO3: fix clock glitch reset bug, support all reset, include: swt & brownout & clock glitch reset. */ - uint8_t chip_version = bootloader_common_get_chip_revision(); + uint8_t chip_version = efuse_hal_get_minor_chip_version(); switch (chip_version) { case 0: case 1: diff --git a/components/driver/i2s.c b/components/driver/i2s.c index ee219cd26f8..ee8b5d9bacf 100644 --- a/components/driver/i2s.c +++ b/components/driver/i2s.c @@ -38,7 +38,7 @@ #include "esp_attr.h" #include "esp_log.h" #include "esp_pm.h" -#include "esp_efuse.h" +#include "hal/efuse_hal.h" #include "esp_rom_gpio.h" #include "sdkconfig.h" @@ -192,7 +192,7 @@ static float i2s_apll_get_fi2s(int bits_per_sample, int sdm0, int sdm1, int sdm2 #if CONFIG_IDF_TARGET_ESP32 /* ESP32 rev0 silicon issue for APLL range/accuracy, please see ESP32 ECO document for more information on this */ - if (esp_efuse_get_chip_ver() == 0) { + if (efuse_hal_get_major_chip_version() == 0) { sdm0 = 0; sdm1 = 0; } diff --git a/components/efuse/esp32/esp_efuse_table.c b/components/efuse/esp32/esp_efuse_table.c index 2dafbb08e52..e8d692b11b2 100644 --- a/components/efuse/esp32/esp_efuse_table.c +++ b/components/efuse/esp32/esp_efuse_table.c @@ -17,7 +17,7 @@ #include #include "esp_efuse_table.h" -// md5_digest_table f552d73ac112985991efa6734a60c8d9 +// md5_digest_table 6256f9b7c6783e0b651bf52b5b162aa8 // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. @@ -168,6 +168,10 @@ static const esp_efuse_desc_t CHIP_VER_REV2[] = { {EFUSE_BLK0, 180, 1}, // EFUSE_RD_CHIP_VER_REV2, }; +static const esp_efuse_desc_t WAFER_VERSION_MINOR[] = { + {EFUSE_BLK0, 184, 2}, // WAFER_VERSION_MINOR, +}; + static const esp_efuse_desc_t XPD_SDIO_REG[] = { {EFUSE_BLK0, 142, 1}, // EFUSE_RD_XPD_SDIO_REG, }; @@ -374,6 +378,11 @@ const esp_efuse_desc_t* ESP_EFUSE_CHIP_VER_REV2[] = { NULL }; +const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[] = { + &WAFER_VERSION_MINOR[0], // WAFER_VERSION_MINOR + NULL +}; + const esp_efuse_desc_t* ESP_EFUSE_XPD_SDIO_REG[] = { &XPD_SDIO_REG[0], // EFUSE_RD_XPD_SDIO_REG NULL diff --git a/components/efuse/esp32/esp_efuse_table.csv b/components/efuse/esp32/esp_efuse_table.csv index 42cee2eb768..4395467b2cf 100644 --- a/components/efuse/esp32/esp_efuse_table.csv +++ b/components/efuse/esp32/esp_efuse_table.csv @@ -71,6 +71,7 @@ CHIP_CPU_FREQ_LOW, EFUSE_BLK0, 108, 1, EFUSE_RD_CHIP_CPU_FREQ_LOW CHIP_CPU_FREQ_RATED, EFUSE_BLK0, 109, 1, EFUSE_RD_CHIP_CPU_FREQ_RATED CHIP_VER_REV1, EFUSE_BLK0, 111, 1, EFUSE_RD_CHIP_VER_REV1 CHIP_VER_REV2, EFUSE_BLK0, 180, 1, EFUSE_RD_CHIP_VER_REV2 +WAFER_VERSION_MINOR, EFUSE_BLK0, 184, 2, WAFER_VERSION_MINOR XPD_SDIO_REG, EFUSE_BLK0, 142, 1, EFUSE_RD_XPD_SDIO_REG SDIO_TIEH, EFUSE_BLK0, 143, 1, EFUSE_RD_SDIO_TIEH SDIO_FORCE, EFUSE_BLK0, 144, 1, EFUSE_RD_SDIO_FORCE diff --git a/components/efuse/esp32/include/esp_efuse_table.h b/components/efuse/esp32/include/esp_efuse_table.h index c1023b742c6..0fda44d3863 100644 --- a/components/efuse/esp32/include/esp_efuse_table.h +++ b/components/efuse/esp32/include/esp_efuse_table.h @@ -17,7 +17,7 @@ extern "C" { #endif -// md5_digest_table f552d73ac112985991efa6734a60c8d9 +// md5_digest_table 6256f9b7c6783e0b651bf52b5b162aa8 // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. @@ -56,6 +56,7 @@ extern const esp_efuse_desc_t* ESP_EFUSE_CHIP_CPU_FREQ_LOW[]; extern const esp_efuse_desc_t* ESP_EFUSE_CHIP_CPU_FREQ_RATED[]; extern const esp_efuse_desc_t* ESP_EFUSE_CHIP_VER_REV1[]; extern const esp_efuse_desc_t* ESP_EFUSE_CHIP_VER_REV2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_XPD_SDIO_REG[]; extern const esp_efuse_desc_t* ESP_EFUSE_SDIO_TIEH[]; extern const esp_efuse_desc_t* ESP_EFUSE_SDIO_FORCE[]; diff --git a/components/efuse/esp32c3/esp_efuse_table.c b/components/efuse/esp32c3/esp_efuse_table.c index aae1f0b383b..31beb4a1c03 100644 --- a/components/efuse/esp32c3/esp_efuse_table.c +++ b/components/efuse/esp32c3/esp_efuse_table.c @@ -17,7 +17,7 @@ #include #include "esp_efuse_table.h" -// md5_digest_table 1e8e57d0ae14e863954678b88fe4c99f +// md5_digest_table 0d034bd5ee387e9b695ed2d74bb2fb34 // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. @@ -315,6 +315,14 @@ static const esp_efuse_desc_t ERR_RST_ENABLE[] = { {EFUSE_BLK0, 159, 1}, // Use BLOCK0 to check error record registers, }; +static const esp_efuse_desc_t DISABLE_WAFER_VERSION_MAJOR[] = { + {EFUSE_BLK0, 160, 1}, // Disables check of wafer version major, +}; + +static const esp_efuse_desc_t DISABLE_BLK_VERSION_MAJOR[] = { + {EFUSE_BLK0, 161, 1}, // Disables check of blk version major, +}; + static const esp_efuse_desc_t MAC_FACTORY[] = { {EFUSE_BLK1, 40, 8}, // Factory MAC addr [0], {EFUSE_BLK1, 32, 8}, // Factory MAC addr [1], @@ -368,24 +376,29 @@ static const esp_efuse_desc_t SPI_PAD_CONFIG_D7[] = { {EFUSE_BLK1, 108, 6}, // SPI_PAD_configure D7, }; -static const esp_efuse_desc_t WAFER_VERSION[] = { - {EFUSE_BLK1, 114, 3}, // WAFER version, +static const esp_efuse_desc_t WAFER_VERSION_MINOR[] = { + {EFUSE_BLK1, 114, 3}, // WAFER_VERSION_MINOR least significant bits, + {EFUSE_BLK1, 183, 1}, // WAFER_VERSION_MINOR most significant bit, }; static const esp_efuse_desc_t PKG_VERSION[] = { {EFUSE_BLK1, 117, 3}, // Package version 0:ESP32C3, }; -static const esp_efuse_desc_t BLOCK1_VERSION[] = { - {EFUSE_BLK1, 120, 3}, // BLOCK1 efuse version, +static const esp_efuse_desc_t BLK_VERSION_MINOR[] = { + {EFUSE_BLK1, 120, 3}, // BLK_VERSION_MINOR, +}; + +static const esp_efuse_desc_t WAFER_VERSION_MAJOR[] = { + {EFUSE_BLK1, 184, 2}, // WAFER_VERSION_MAJOR, }; static const esp_efuse_desc_t OPTIONAL_UNIQUE_ID[] = { {EFUSE_BLK2, 0, 128}, // Optional unique 128-bit ID, }; -static const esp_efuse_desc_t BLOCK2_VERSION[] = { - {EFUSE_BLK2, 128, 3}, // Version of BLOCK2, +static const esp_efuse_desc_t BLK_VERSION_MAJOR[] = { + {EFUSE_BLK2, 128, 2}, // BLK_VERSION_MAJOR of BLOCK2, }; static const esp_efuse_desc_t TEMP_CALIB[] = { @@ -853,6 +866,16 @@ const esp_efuse_desc_t* ESP_EFUSE_ERR_RST_ENABLE[] = { NULL }; +const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[] = { + &DISABLE_WAFER_VERSION_MAJOR[0], // Disables check of wafer version major + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[] = { + &DISABLE_BLK_VERSION_MAJOR[0], // Disables check of blk version major + NULL +}; + const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[] = { &MAC_FACTORY[0], // Factory MAC addr [0] &MAC_FACTORY[1], // Factory MAC addr [1] @@ -918,8 +941,9 @@ const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D7[] = { NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION[] = { - &WAFER_VERSION[0], // WAFER version +const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[] = { + &WAFER_VERSION_MINOR[0], // WAFER_VERSION_MINOR least significant bits + &WAFER_VERSION_MINOR[1], // WAFER_VERSION_MINOR most significant bit NULL }; @@ -928,8 +952,13 @@ const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[] = { NULL }; -const esp_efuse_desc_t* ESP_EFUSE_BLOCK1_VERSION[] = { - &BLOCK1_VERSION[0], // BLOCK1 efuse version +const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[] = { + &BLK_VERSION_MINOR[0], // BLK_VERSION_MINOR + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[] = { + &WAFER_VERSION_MAJOR[0], // WAFER_VERSION_MAJOR NULL }; @@ -938,8 +967,8 @@ const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[] = { NULL }; -const esp_efuse_desc_t* ESP_EFUSE_BLOCK2_VERSION[] = { - &BLOCK2_VERSION[0], // Version of BLOCK2 +const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[] = { + &BLK_VERSION_MAJOR[0], // BLK_VERSION_MAJOR of BLOCK2 NULL }; diff --git a/components/efuse/esp32c3/esp_efuse_table.csv b/components/efuse/esp32c3/esp_efuse_table.csv index 5851ab06495..7f42a5c84bf 100644 --- a/components/efuse/esp32c3/esp_efuse_table.csv +++ b/components/efuse/esp32c3/esp_efuse_table.csv @@ -98,45 +98,61 @@ ERR_RST_ENABLE, EFUSE_BLK0, 159, 1, Use BLOCK0 to check error record registers, 0 - without check. # EFUSE_RD_REPEAT_DATA4_REG # + DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 160, 1, Disables check of wafer version major + DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 161, 1, Disables check of blk version major # MAC_SPI_SYS BLOCK# ####################### - MAC_FACTORY, EFUSE_BLK1, 40, 8, Factory MAC addr [0] - , EFUSE_BLK1, 32, 8, Factory MAC addr [1] - , EFUSE_BLK1, 24, 8, Factory MAC addr [2] - , EFUSE_BLK1, 16, 8, Factory MAC addr [3] - , EFUSE_BLK1, 8, 8, Factory MAC addr [4] - , EFUSE_BLK1, 0, 8, Factory MAC addr [5] - SPI_PAD_CONFIG_CLK, EFUSE_BLK1, 48, 6, SPI_PAD_configure CLK - SPI_PAD_CONFIG_Q_D1, EFUSE_BLK1, 54, 6, SPI_PAD_configure Q(D1) - SPI_PAD_CONFIG_D_D0, EFUSE_BLK1, 60, 6, SPI_PAD_configure D(D0) - SPI_PAD_CONFIG_CS, EFUSE_BLK1, 66, 6, SPI_PAD_configure CS - SPI_PAD_CONFIG_HD_D3, EFUSE_BLK1, 72, 6, SPI_PAD_configure HD(D3) - SPI_PAD_CONFIG_WP_D2, EFUSE_BLK1, 78, 6, SPI_PAD_configure WP(D2) - SPI_PAD_CONFIG_DQS, EFUSE_BLK1, 84, 6, SPI_PAD_configure DQS - SPI_PAD_CONFIG_D4, EFUSE_BLK1, 90, 6, SPI_PAD_configure D4 - SPI_PAD_CONFIG_D5, EFUSE_BLK1, 96, 6, SPI_PAD_configure D5 - SPI_PAD_CONFIG_D6, EFUSE_BLK1, 102, 6, SPI_PAD_configure D6 - SPI_PAD_CONFIG_D7, EFUSE_BLK1, 108, 6, SPI_PAD_configure D7 - WAFER_VERSION, EFUSE_BLK1, 114, 3, WAFER version - PKG_VERSION, EFUSE_BLK1, 117, 3, Package version 0:ESP32C3 - BLOCK1_VERSION, EFUSE_BLK1, 120, 3, BLOCK1 efuse version + # RD_MAC_SPI_SYS_0 - RD_MAC_SPI_SYS_2 + MAC_FACTORY, EFUSE_BLK1, 40, 8, Factory MAC addr [0] + , EFUSE_BLK1, 32, 8, Factory MAC addr [1] + , EFUSE_BLK1, 24, 8, Factory MAC addr [2] + , EFUSE_BLK1, 16, 8, Factory MAC addr [3] + , EFUSE_BLK1, 8, 8, Factory MAC addr [4] + , EFUSE_BLK1, 0, 8, Factory MAC addr [5] + SPI_PAD_CONFIG_CLK, EFUSE_BLK1, 48, 6, SPI_PAD_configure CLK + SPI_PAD_CONFIG_Q_D1, EFUSE_BLK1, 54, 6, SPI_PAD_configure Q(D1) + SPI_PAD_CONFIG_D_D0, EFUSE_BLK1, 60, 6, SPI_PAD_configure D(D0) + SPI_PAD_CONFIG_CS, EFUSE_BLK1, 66, 6, SPI_PAD_configure CS + SPI_PAD_CONFIG_HD_D3, EFUSE_BLK1, 72, 6, SPI_PAD_configure HD(D3) + SPI_PAD_CONFIG_WP_D2, EFUSE_BLK1, 78, 6, SPI_PAD_configure WP(D2) + SPI_PAD_CONFIG_DQS, EFUSE_BLK1, 84, 6, SPI_PAD_configure DQS + SPI_PAD_CONFIG_D4, EFUSE_BLK1, 90, 6, SPI_PAD_configure D4 + SPI_PAD_CONFIG_D5, EFUSE_BLK1, 96, 6, SPI_PAD_configure D5 + + # RD_MAC_SPI_SYS_3 + SPI_PAD_CONFIG_D6, EFUSE_BLK1, 102, 6, SPI_PAD_configure D6 + SPI_PAD_CONFIG_D7, EFUSE_BLK1, 108, 6, SPI_PAD_configure D7 + WAFER_VERSION_MINOR, EFUSE_BLK1, 114, 3, WAFER_VERSION_MINOR least significant bits + , EFUSE_BLK1, 183, 1, WAFER_VERSION_MINOR most significant bit + # WAFER_VERSION_MINOR most significant bit is from RD_MAC_SPI_SYS_5 + PKG_VERSION, EFUSE_BLK1, 117, 3, Package version 0:ESP32C3 + BLK_VERSION_MINOR, EFUSE_BLK1, 120, 3, BLK_VERSION_MINOR + + # RD_MAC_SPI_SYS_5 + # WAFER_VERSION_MINOR most significant bit + WAFER_VERSION_MAJOR, EFUSE_BLK1, 184, 2, WAFER_VERSION_MAJOR # SYS_DATA_PART1 BLOCK# - System configuration ####################### - OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, Optional unique 128-bit ID - BLOCK2_VERSION, EFUSE_BLK2, 128, 3, Version of BLOCK2 - TEMP_CALIB, EFUSE_BLK2, 131, 9, Temperature calibration data - OCODE, EFUSE_BLK2, 140, 8, ADC OCode - ADC1_INIT_CODE_ATTEN0, EFUSE_BLK2, 148, 10, ADC1 init code at atten0 - ADC1_INIT_CODE_ATTEN1, EFUSE_BLK2, 158, 10, ADC1 init code at atten1 - ADC1_INIT_CODE_ATTEN2, EFUSE_BLK2, 168, 10, ADC1 init code at atten2 - ADC1_INIT_CODE_ATTEN3, EFUSE_BLK2, 178, 10, ADC1 init code at atten3 - ADC1_CAL_VOL_ATTEN0, EFUSE_BLK2, 188, 10, ADC1 calibration voltage at atten0 - ADC1_CAL_VOL_ATTEN1, EFUSE_BLK2, 198, 10, ADC1 calibration voltage at atten1 - ADC1_CAL_VOL_ATTEN2, EFUSE_BLK2, 208, 10, ADC1 calibration voltage at atten2 - ADC1_CAL_VOL_ATTEN3, EFUSE_BLK2, 218, 10, ADC1 calibration voltage at atten3 + # RD_SYS_PART1_DATA0 - rd_sys_part1_data3 + OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, Optional unique 128-bit ID + + # RD_SYS_PART1_DATA4 + BLK_VERSION_MAJOR, EFUSE_BLK2, 128, 2, BLK_VERSION_MAJOR of BLOCK2 + TEMP_CALIB, EFUSE_BLK2, 131, 9, Temperature calibration data + OCODE, EFUSE_BLK2, 140, 8, ADC OCode + ADC1_INIT_CODE_ATTEN0, EFUSE_BLK2, 148, 10, ADC1 init code at atten0 + ADC1_INIT_CODE_ATTEN1, EFUSE_BLK2, 158, 10, ADC1 init code at atten1 + + # RD_SYS_PART1_DATA5 + ADC1_INIT_CODE_ATTEN2, EFUSE_BLK2, 168, 10, ADC1 init code at atten2 + ADC1_INIT_CODE_ATTEN3, EFUSE_BLK2, 178, 10, ADC1 init code at atten3 + ADC1_CAL_VOL_ATTEN0, EFUSE_BLK2, 188, 10, ADC1 calibration voltage at atten0 + ADC1_CAL_VOL_ATTEN1, EFUSE_BLK2, 198, 10, ADC1 calibration voltage at atten1 + ADC1_CAL_VOL_ATTEN2, EFUSE_BLK2, 208, 10, ADC1 calibration voltage at atten2 + ADC1_CAL_VOL_ATTEN3, EFUSE_BLK2, 218, 10, ADC1 calibration voltage at atten3 ################ USER_DATA, EFUSE_BLK3, 0, 256, User data diff --git a/components/efuse/esp32c3/include/esp_efuse_table.h b/components/efuse/esp32c3/include/esp_efuse_table.h index fe6e76673e9..588e96b552a 100644 --- a/components/efuse/esp32c3/include/esp_efuse_table.h +++ b/components/efuse/esp32c3/include/esp_efuse_table.h @@ -17,7 +17,7 @@ extern "C" { #endif -// md5_digest_table 1e8e57d0ae14e863954678b88fe4c99f +// md5_digest_table 0d034bd5ee387e9b695ed2d74bb2fb34 // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. @@ -97,6 +97,8 @@ extern const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[]; extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[]; extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[]; extern const esp_efuse_desc_t* ESP_EFUSE_ERR_RST_ENABLE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[]; extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CLK[]; extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q_D1[]; @@ -109,11 +111,12 @@ extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D4[]; extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D5[]; extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D6[]; extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D7[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[]; -extern const esp_efuse_desc_t* ESP_EFUSE_BLOCK1_VERSION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[]; -extern const esp_efuse_desc_t* ESP_EFUSE_BLOCK2_VERSION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_TEMP_CALIB[]; extern const esp_efuse_desc_t* ESP_EFUSE_OCODE[]; extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0[]; diff --git a/components/efuse/esp32s2/esp_efuse_table.c b/components/efuse/esp32s2/esp_efuse_table.c index bcdca0933e7..2142dbd6ab1 100644 --- a/components/efuse/esp32s2/esp_efuse_table.c +++ b/components/efuse/esp32s2/esp_efuse_table.c @@ -17,7 +17,7 @@ #include #include "esp_efuse_table.h" -// md5_digest_table c345ec20bb033bf5d071108ae644b54c +// md5_digest_table 99c4fa31629663b69a549cd858d4e0a2 // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. @@ -331,6 +331,14 @@ static const esp_efuse_desc_t SECURE_VERSION[] = { {EFUSE_BLK0, 139, 16}, // Secure version for anti-rollback, }; +static const esp_efuse_desc_t DISABLE_WAFER_VERSION_MAJOR[] = { + {EFUSE_BLK0, 160, 1}, // Disables check of wafer version major, +}; + +static const esp_efuse_desc_t DISABLE_BLK_VERSION_MAJOR[] = { + {EFUSE_BLK0, 161, 1}, // Disables check of blk version major, +}; + static const esp_efuse_desc_t MAC_FACTORY[] = { {EFUSE_BLK1, 40, 8}, // Factory MAC addr [0], {EFUSE_BLK1, 32, 8}, // Factory MAC addr [1], @@ -384,16 +392,21 @@ static const esp_efuse_desc_t SPI_PAD_CONFIG_D7[] = { {EFUSE_BLK1, 108, 6}, // SPI_PAD_configure D7, }; -static const esp_efuse_desc_t WAFER_VERSION[] = { - {EFUSE_BLK1, 114, 3}, // WAFER version 0:A, +static const esp_efuse_desc_t WAFER_VERSION_MAJOR[] = { + {EFUSE_BLK1, 114, 2}, // WAFER_VERSION_MAJOR, +}; + +static const esp_efuse_desc_t WAFER_VERSION_MINOR[] = { + {EFUSE_BLK1, 132, 3}, // WAFER_VERSION_MINOR least significant bits, + {EFUSE_BLK1, 116, 1}, // WAFER_VERSION_MINOR most significant bit, }; static const esp_efuse_desc_t FLASH_VERSION[] = { {EFUSE_BLK1, 117, 4}, // Flash_version, }; -static const esp_efuse_desc_t BLOCK1_VERSION[] = { - {EFUSE_BLK1, 121, 3}, // BLOCK1 efuse version, +static const esp_efuse_desc_t BLK_VERSION_MAJOR[] = { + {EFUSE_BLK1, 121, 2}, // BLK_VERSION_MAJOR, }; static const esp_efuse_desc_t PSRAM_VERSION[] = { @@ -408,8 +421,8 @@ static const esp_efuse_desc_t OPTIONAL_UNIQUE_ID[] = { {EFUSE_BLK2, 0, 128}, // Optional unique 128-bit ID, }; -static const esp_efuse_desc_t BLOCK2_VERSION[] = { - {EFUSE_BLK2, 132, 3}, // Version of BLOCK2: 0-No ADC calib; 1-ADC calib V1; 2-ADC calib V2, +static const esp_efuse_desc_t BLK_VERSION_MINOR[] = { + {EFUSE_BLK2, 132, 3}, // BLK_VERSION_MINOR of BLOCK2: 0-No ADC calib; 1-ADC calib V1; 2-ADC calib V2, }; static const esp_efuse_desc_t USER_DATA[] = { @@ -833,6 +846,16 @@ const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[] = { NULL }; +const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[] = { + &DISABLE_WAFER_VERSION_MAJOR[0], // Disables check of wafer version major + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[] = { + &DISABLE_BLK_VERSION_MAJOR[0], // Disables check of blk version major + NULL +}; + const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[] = { &MAC_FACTORY[0], // Factory MAC addr [0] &MAC_FACTORY[1], // Factory MAC addr [1] @@ -898,8 +921,14 @@ const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D7[] = { NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION[] = { - &WAFER_VERSION[0], // WAFER version 0:A +const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[] = { + &WAFER_VERSION_MAJOR[0], // WAFER_VERSION_MAJOR + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[] = { + &WAFER_VERSION_MINOR[0], // WAFER_VERSION_MINOR least significant bits + &WAFER_VERSION_MINOR[1], // WAFER_VERSION_MINOR most significant bit NULL }; @@ -908,8 +937,8 @@ const esp_efuse_desc_t* ESP_EFUSE_FLASH_VERSION[] = { NULL }; -const esp_efuse_desc_t* ESP_EFUSE_BLOCK1_VERSION[] = { - &BLOCK1_VERSION[0], // BLOCK1 efuse version +const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[] = { + &BLK_VERSION_MAJOR[0], // BLK_VERSION_MAJOR NULL }; @@ -928,8 +957,8 @@ const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[] = { NULL }; -const esp_efuse_desc_t* ESP_EFUSE_BLOCK2_VERSION[] = { - &BLOCK2_VERSION[0], // Version of BLOCK2: 0-No ADC calib; 1-ADC calib V1; 2-ADC calib V2 +const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[] = { + &BLK_VERSION_MINOR[0], // BLK_VERSION_MINOR of BLOCK2: 0-No ADC calib; 1-ADC calib V1; 2-ADC calib V2 NULL }; diff --git a/components/efuse/esp32s2/esp_efuse_table.csv b/components/efuse/esp32s2/esp_efuse_table.csv index 3daed139ad7..20f03edba47 100644 --- a/components/efuse/esp32s2/esp_efuse_table.csv +++ b/components/efuse/esp32s2/esp_efuse_table.csv @@ -102,38 +102,51 @@ SECURE_VERSION, EFUSE_BLK0, 139, 16, Secure version for anti-rollback # EFUSE_RD_REPEAT_DATA4_REG # + DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 160, 1, Disables check of wafer version major + DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 161, 1, Disables check of blk version major # MAC_SPI_8M_SYS BLOCK# ####################### - MAC_FACTORY, EFUSE_BLK1, 40, 8, Factory MAC addr [0] - , EFUSE_BLK1, 32, 8, Factory MAC addr [1] - , EFUSE_BLK1, 24, 8, Factory MAC addr [2] - , EFUSE_BLK1, 16, 8, Factory MAC addr [3] - , EFUSE_BLK1, 8, 8, Factory MAC addr [4] - , EFUSE_BLK1, 0, 8, Factory MAC addr [5] - SPI_PAD_CONFIG_CLK, EFUSE_BLK1, 48, 6, SPI_PAD_configure CLK - SPI_PAD_CONFIG_Q_D1, EFUSE_BLK1, 54, 6, SPI_PAD_configure Q(D1) - SPI_PAD_CONFIG_D_D0, EFUSE_BLK1, 60, 6, SPI_PAD_configure D(D0) - SPI_PAD_CONFIG_CS, EFUSE_BLK1, 66, 6, SPI_PAD_configure CS - SPI_PAD_CONFIG_HD_D3, EFUSE_BLK1, 72, 6, SPI_PAD_configure HD(D3) - SPI_PAD_CONFIG_WP_D2, EFUSE_BLK1, 78, 6, SPI_PAD_configure WP(D2) - SPI_PAD_CONFIG_DQS, EFUSE_BLK1, 84, 6, SPI_PAD_configure DQS - SPI_PAD_CONFIG_D4, EFUSE_BLK1, 90, 6, SPI_PAD_configure D4 - SPI_PAD_CONFIG_D5, EFUSE_BLK1, 96, 6, SPI_PAD_configure D5 - SPI_PAD_CONFIG_D6, EFUSE_BLK1, 102, 6, SPI_PAD_configure D6 - SPI_PAD_CONFIG_D7, EFUSE_BLK1, 108, 6, SPI_PAD_configure D7 - WAFER_VERSION, EFUSE_BLK1, 114, 3, WAFER version 0:A - FLASH_VERSION, EFUSE_BLK1, 117, 4, Flash_version - BLOCK1_VERSION, EFUSE_BLK1, 121, 3, BLOCK1 efuse version - PSRAM_VERSION, EFUSE_BLK1, 124, 4, PSRAM version - PKG_VERSION, EFUSE_BLK1, 128, 4, Package version - # SYS_DATA_PART0, EFUSE_BLK1, 132, 60, System configuration (Reserve) + # RD_MAC_SPI_8M_0 - RD_MAC_SPI_8M_2 + MAC_FACTORY, EFUSE_BLK1, 40, 8, Factory MAC addr [0] + , EFUSE_BLK1, 32, 8, Factory MAC addr [1] + , EFUSE_BLK1, 24, 8, Factory MAC addr [2] + , EFUSE_BLK1, 16, 8, Factory MAC addr [3] + , EFUSE_BLK1, 8, 8, Factory MAC addr [4] + , EFUSE_BLK1, 0, 8, Factory MAC addr [5] + SPI_PAD_CONFIG_CLK, EFUSE_BLK1, 48, 6, SPI_PAD_configure CLK + SPI_PAD_CONFIG_Q_D1, EFUSE_BLK1, 54, 6, SPI_PAD_configure Q(D1) + SPI_PAD_CONFIG_D_D0, EFUSE_BLK1, 60, 6, SPI_PAD_configure D(D0) + SPI_PAD_CONFIG_CS, EFUSE_BLK1, 66, 6, SPI_PAD_configure CS + SPI_PAD_CONFIG_HD_D3, EFUSE_BLK1, 72, 6, SPI_PAD_configure HD(D3) + SPI_PAD_CONFIG_WP_D2, EFUSE_BLK1, 78, 6, SPI_PAD_configure WP(D2) + SPI_PAD_CONFIG_DQS, EFUSE_BLK1, 84, 6, SPI_PAD_configure DQS + SPI_PAD_CONFIG_D4, EFUSE_BLK1, 90, 6, SPI_PAD_configure D4 + + # RD_MAC_SPI_8M_3 + SPI_PAD_CONFIG_D5, EFUSE_BLK1, 96, 6, SPI_PAD_configure D5 + SPI_PAD_CONFIG_D6, EFUSE_BLK1, 102, 6, SPI_PAD_configure D6 + SPI_PAD_CONFIG_D7, EFUSE_BLK1, 108, 6, SPI_PAD_configure D7 + WAFER_VERSION_MAJOR, EFUSE_BLK1, 114, 2, WAFER_VERSION_MAJOR + WAFER_VERSION_MINOR, EFUSE_BLK1, 132, 3, WAFER_VERSION_MINOR least significant bits + , EFUSE_BLK1, 116, 1, WAFER_VERSION_MINOR most significant bit + # WAFER_VERSION_MINOR least significant bits is from RD_MAC_SPI_8M_4 + FLASH_VERSION, EFUSE_BLK1, 117, 4, Flash_version + BLK_VERSION_MAJOR, EFUSE_BLK1, 121, 2, BLK_VERSION_MAJOR + PSRAM_VERSION, EFUSE_BLK1, 124, 4, PSRAM version + + # RD_MAC_SPI_8M_4 + PKG_VERSION, EFUSE_BLK1, 128, 4, Package version + # WAFER_VERSION_MINOR least significant bits # SYS_DATA_PART1 BLOCK# - System configuration ####################### - OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, Optional unique 128-bit ID - BLOCK2_VERSION, EFUSE_BLK2, 132, 3, Version of BLOCK2: 0-No ADC calib; 1-ADC calib V1; 2-ADC calib V2 + # RD_SYS_DATA0 - RD_SYS_DATA3 + OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, Optional unique 128-bit ID + + # RD_SYS_DATA4 + BLK_VERSION_MINOR, EFUSE_BLK2, 132, 3, BLK_VERSION_MINOR of BLOCK2: 0-No ADC calib; 1-ADC calib V1; 2-ADC calib V2 ################ USER_DATA, EFUSE_BLK3, 0, 256, User data diff --git a/components/efuse/esp32s2/include/esp_efuse_table.h b/components/efuse/esp32s2/include/esp_efuse_table.h index 9078f70cca7..015ac94d004 100644 --- a/components/efuse/esp32s2/include/esp_efuse_table.h +++ b/components/efuse/esp32s2/include/esp_efuse_table.h @@ -17,7 +17,7 @@ extern "C" { #endif -// md5_digest_table c345ec20bb033bf5d071108ae644b54c +// md5_digest_table 99c4fa31629663b69a549cd858d4e0a2 // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. @@ -101,6 +101,8 @@ extern const esp_efuse_desc_t* ESP_EFUSE_PIN_POWER_SELECTION[]; extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TYPE[]; extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[]; extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[]; extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CLK[]; extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q_D1[]; @@ -113,13 +115,14 @@ extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D4[]; extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D5[]; extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D6[]; extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D7[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_VERSION[]; -extern const esp_efuse_desc_t* ESP_EFUSE_BLOCK1_VERSION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_VERSION[]; extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[]; extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[]; -extern const esp_efuse_desc_t* ESP_EFUSE_BLOCK2_VERSION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[]; extern const esp_efuse_desc_t* ESP_EFUSE_KEY0[]; extern const esp_efuse_desc_t* ESP_EFUSE_KEY1[]; diff --git a/components/efuse/esp32s3/esp_efuse_table.c b/components/efuse/esp32s3/esp_efuse_table.c index d9b5fe94163..323bad2955c 100644 --- a/components/efuse/esp32s3/esp_efuse_table.c +++ b/components/efuse/esp32s3/esp_efuse_table.c @@ -17,7 +17,7 @@ #include #include "esp_efuse_table.h" -// md5_digest_table 9295c8aa9c48d48dc42c78456bd02645 +// md5_digest_table 466199602f703d803a9f87956236882e // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. @@ -339,6 +339,14 @@ static const esp_efuse_desc_t DIS_USB_OTG_DOWNLOAD_MODE[] = { {EFUSE_BLK0, 159, 1}, // Set this bit to disable download through USB-OTG, }; +static const esp_efuse_desc_t DISABLE_WAFER_VERSION_MAJOR[] = { + {EFUSE_BLK0, 160, 1}, // Disables check of wafer version major, +}; + +static const esp_efuse_desc_t DISABLE_BLK_VERSION_MAJOR[] = { + {EFUSE_BLK0, 161, 1}, // Disables check of blk version major, +}; + static const esp_efuse_desc_t MAC_FACTORY[] = { {EFUSE_BLK1, 40, 8}, // Factory MAC addr [0], {EFUSE_BLK1, 32, 8}, // Factory MAC addr [1], @@ -392,28 +400,101 @@ static const esp_efuse_desc_t SPI_PAD_CONFIG_D7[] = { {EFUSE_BLK1, 108, 6}, // SPI_PAD_configure D7, }; -static const esp_efuse_desc_t WAFER_VERSION[] = { - {EFUSE_BLK1, 114, 3}, // WAFER version 0:A, +static const esp_efuse_desc_t WAFER_VERSION_MINOR[] = { + {EFUSE_BLK1, 114, 3}, // WAFER_VERSION_MINOR least significant bits, + {EFUSE_BLK1, 183, 1}, // WAFER_VERSION_MINOR most significant bit, }; static const esp_efuse_desc_t PKG_VERSION[] = { - {EFUSE_BLK1, 117, 4}, // Package version 0:ESP32-S2 1:ESP32-S2FH16 2:ESP32-S2FH32, + {EFUSE_BLK1, 117, 3}, // Package version, }; -static const esp_efuse_desc_t BLOCK1_VERSION[] = { - {EFUSE_BLK1, 121, 3}, // BLOCK1 efuse version 0:No calibration 1:With calibration, +static const esp_efuse_desc_t BLK_VERSION_MINOR[] = { + {EFUSE_BLK1, 120, 3}, // BLK_VERSION_MINOR, }; -static const esp_efuse_desc_t SYS_DATA_PART0[] = { - {EFUSE_BLK1, 126, 66}, // System configuration, +static const esp_efuse_desc_t WAFER_VERSION_MAJOR[] = { + {EFUSE_BLK1, 184, 2}, // WAFER_VERSION_MAJOR, +}; + +static const esp_efuse_desc_t ADC2_CAL_VOL_ATTEN3[] = { + {EFUSE_BLK1, 186, 6}, // ADC2 calibration voltage at atten3, }; static const esp_efuse_desc_t OPTIONAL_UNIQUE_ID[] = { {EFUSE_BLK2, 0, 128}, // Optional unique 128-bit ID, }; -static const esp_efuse_desc_t BLOCK2_VERSION[] = { - {EFUSE_BLK2, 132, 3}, // Version of BLOCK2, +static const esp_efuse_desc_t BLK_VERSION_MAJOR[] = { + {EFUSE_BLK2, 128, 2}, // BLK_VERSION_MAJOR of BLOCK2 change of this bit means users need to update firmware, +}; + +static const esp_efuse_desc_t TEMP_CALIB[] = { + {EFUSE_BLK2, 132, 9}, // Temperature calibration data, +}; + +static const esp_efuse_desc_t OCODE[] = { + {EFUSE_BLK2, 141, 8}, // ADC OCode, +}; + +static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN0[] = { + {EFUSE_BLK2, 149, 8}, // ADC1 init code at atten0, +}; + +static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN1[] = { + {EFUSE_BLK2, 157, 6}, // ADC1 init code at atten1, +}; + +static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN2[] = { + {EFUSE_BLK2, 163, 6}, // ADC1 init code at atten2, +}; + +static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN3[] = { + {EFUSE_BLK2, 169, 6}, // ADC1 init code at atten3, +}; + +static const esp_efuse_desc_t ADC2_INIT_CODE_ATTEN0[] = { + {EFUSE_BLK2, 175, 8}, // ADC2 init code at atten0, +}; + +static const esp_efuse_desc_t ADC2_INIT_CODE_ATTEN1[] = { + {EFUSE_BLK2, 183, 6}, // ADC2 init code at atten1, +}; + +static const esp_efuse_desc_t ADC2_INIT_CODE_ATTEN2[] = { + {EFUSE_BLK2, 189, 6}, // ADC2 init code at atten2, +}; + +static const esp_efuse_desc_t ADC2_INIT_CODE_ATTEN3[] = { + {EFUSE_BLK2, 195, 6}, // ADC2 init code at atten3, +}; + +static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN0[] = { + {EFUSE_BLK2, 201, 8}, // ADC1 calibration voltage at atten0, +}; + +static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN1[] = { + {EFUSE_BLK2, 209, 8}, // ADC1 calibration voltage at atten1, +}; + +static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN2[] = { + {EFUSE_BLK2, 217, 8}, // ADC1 calibration voltage at atten2, +}; + +static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN3[] = { + {EFUSE_BLK2, 225, 8}, // ADC1 calibration voltage at atten3, +}; + +static const esp_efuse_desc_t ADC2_CAL_VOL_ATTEN0[] = { + {EFUSE_BLK2, 233, 8}, // ADC2 calibration voltage at atten0, +}; + +static const esp_efuse_desc_t ADC2_CAL_VOL_ATTEN1[] = { + {EFUSE_BLK2, 241, 7}, // ADC2 calibration voltage at atten1, +}; + +static const esp_efuse_desc_t ADC2_CAL_VOL_ATTEN2[] = { + {EFUSE_BLK2, 248, 7}, // ADC2 calibration voltage at atten2, }; static const esp_efuse_desc_t USER_DATA[] = { @@ -847,6 +928,16 @@ const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_OTG_DOWNLOAD_MODE[] = { NULL }; +const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[] = { + &DISABLE_WAFER_VERSION_MAJOR[0], // Disables check of wafer version major + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[] = { + &DISABLE_BLK_VERSION_MAJOR[0], // Disables check of blk version major + NULL +}; + const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[] = { &MAC_FACTORY[0], // Factory MAC addr [0] &MAC_FACTORY[1], // Factory MAC addr [1] @@ -912,23 +1003,29 @@ const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D7[] = { NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION[] = { - &WAFER_VERSION[0], // WAFER version 0:A +const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[] = { + &WAFER_VERSION_MINOR[0], // WAFER_VERSION_MINOR least significant bits + &WAFER_VERSION_MINOR[1], // WAFER_VERSION_MINOR most significant bit NULL }; const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[] = { - &PKG_VERSION[0], // Package version 0:ESP32-S2 1:ESP32-S2FH16 2:ESP32-S2FH32 + &PKG_VERSION[0], // Package version + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[] = { + &BLK_VERSION_MINOR[0], // BLK_VERSION_MINOR NULL }; -const esp_efuse_desc_t* ESP_EFUSE_BLOCK1_VERSION[] = { - &BLOCK1_VERSION[0], // BLOCK1 efuse version 0:No calibration 1:With calibration +const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[] = { + &WAFER_VERSION_MAJOR[0], // WAFER_VERSION_MAJOR NULL }; -const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART0[] = { - &SYS_DATA_PART0[0], // System configuration +const esp_efuse_desc_t* ESP_EFUSE_ADC2_CAL_VOL_ATTEN3[] = { + &ADC2_CAL_VOL_ATTEN3[0], // ADC2 calibration voltage at atten3 NULL }; @@ -937,8 +1034,93 @@ const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[] = { NULL }; -const esp_efuse_desc_t* ESP_EFUSE_BLOCK2_VERSION[] = { - &BLOCK2_VERSION[0], // Version of BLOCK2 +const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[] = { + &BLK_VERSION_MAJOR[0], // BLK_VERSION_MAJOR of BLOCK2 change of this bit means users need to update firmware + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_TEMP_CALIB[] = { + &TEMP_CALIB[0], // Temperature calibration data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_OCODE[] = { + &OCODE[0], // ADC OCode + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0[] = { + &ADC1_INIT_CODE_ATTEN0[0], // ADC1 init code at atten0 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN1[] = { + &ADC1_INIT_CODE_ATTEN1[0], // ADC1 init code at atten1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN2[] = { + &ADC1_INIT_CODE_ATTEN2[0], // ADC1 init code at atten2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN3[] = { + &ADC1_INIT_CODE_ATTEN3[0], // ADC1 init code at atten3 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC2_INIT_CODE_ATTEN0[] = { + &ADC2_INIT_CODE_ATTEN0[0], // ADC2 init code at atten0 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC2_INIT_CODE_ATTEN1[] = { + &ADC2_INIT_CODE_ATTEN1[0], // ADC2 init code at atten1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC2_INIT_CODE_ATTEN2[] = { + &ADC2_INIT_CODE_ATTEN2[0], // ADC2 init code at atten2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC2_INIT_CODE_ATTEN3[] = { + &ADC2_INIT_CODE_ATTEN3[0], // ADC2 init code at atten3 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN0[] = { + &ADC1_CAL_VOL_ATTEN0[0], // ADC1 calibration voltage at atten0 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN1[] = { + &ADC1_CAL_VOL_ATTEN1[0], // ADC1 calibration voltage at atten1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN2[] = { + &ADC1_CAL_VOL_ATTEN2[0], // ADC1 calibration voltage at atten2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN3[] = { + &ADC1_CAL_VOL_ATTEN3[0], // ADC1 calibration voltage at atten3 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC2_CAL_VOL_ATTEN0[] = { + &ADC2_CAL_VOL_ATTEN0[0], // ADC2 calibration voltage at atten0 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC2_CAL_VOL_ATTEN1[] = { + &ADC2_CAL_VOL_ATTEN1[0], // ADC2 calibration voltage at atten1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC2_CAL_VOL_ATTEN2[] = { + &ADC2_CAL_VOL_ATTEN2[0], // ADC2 calibration voltage at atten2 NULL }; diff --git a/components/efuse/esp32s3/esp_efuse_table.csv b/components/efuse/esp32s3/esp_efuse_table.csv index 55559ad6ca8..72ff70819a3 100644 --- a/components/efuse/esp32s3/esp_efuse_table.csv +++ b/components/efuse/esp32s3/esp_efuse_table.csv @@ -103,36 +103,69 @@ DIS_USB_OTG_DOWNLOAD_MODE, EFUSE_BLK0, 159, 1, Set this bit to disable download through USB-OTG # EFUSE_RD_REPEAT_DATA4_REG # + DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 160, 1, Disables check of wafer version major + DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 161, 1, Disables check of blk version major # MAC_SPI_8M_SYS BLOCK# ####################### - MAC_FACTORY, EFUSE_BLK1, 40, 8, Factory MAC addr [0] - , EFUSE_BLK1, 32, 8, Factory MAC addr [1] - , EFUSE_BLK1, 24, 8, Factory MAC addr [2] - , EFUSE_BLK1, 16, 8, Factory MAC addr [3] - , EFUSE_BLK1, 8, 8, Factory MAC addr [4] - , EFUSE_BLK1, 0, 8, Factory MAC addr [5] - SPI_PAD_CONFIG_CLK, EFUSE_BLK1, 48, 6, SPI_PAD_configure CLK - SPI_PAD_CONFIG_Q_D1, EFUSE_BLK1, 54, 6, SPI_PAD_configure Q(D1) - SPI_PAD_CONFIG_D_D0, EFUSE_BLK1, 60, 6, SPI_PAD_configure D(D0) - SPI_PAD_CONFIG_CS, EFUSE_BLK1, 66, 6, SPI_PAD_configure CS - SPI_PAD_CONFIG_HD_D3, EFUSE_BLK1, 72, 6, SPI_PAD_configure HD(D3) - SPI_PAD_CONFIG_WP_D2, EFUSE_BLK1, 78, 6, SPI_PAD_configure WP(D2) - SPI_PAD_CONFIG_DQS, EFUSE_BLK1, 84, 6, SPI_PAD_configure DQS - SPI_PAD_CONFIG_D4, EFUSE_BLK1, 90, 6, SPI_PAD_configure D4 - SPI_PAD_CONFIG_D5, EFUSE_BLK1, 96, 6, SPI_PAD_configure D5 - SPI_PAD_CONFIG_D6, EFUSE_BLK1, 102, 6, SPI_PAD_configure D6 - SPI_PAD_CONFIG_D7, EFUSE_BLK1, 108, 6, SPI_PAD_configure D7 - WAFER_VERSION, EFUSE_BLK1, 114, 3, WAFER version 0:A - PKG_VERSION, EFUSE_BLK1, 117, 4, Package version 0:ESP32-S2 1:ESP32-S2FH16 2:ESP32-S2FH32 - BLOCK1_VERSION, EFUSE_BLK1, 121, 3, BLOCK1 efuse version 0:No calibration 1:With calibration - SYS_DATA_PART0, EFUSE_BLK1, 126, 66, System configuration + MAC_FACTORY, EFUSE_BLK1, 40, 8, Factory MAC addr [0] + , EFUSE_BLK1, 32, 8, Factory MAC addr [1] + , EFUSE_BLK1, 24, 8, Factory MAC addr [2] + , EFUSE_BLK1, 16, 8, Factory MAC addr [3] + , EFUSE_BLK1, 8, 8, Factory MAC addr [4] + , EFUSE_BLK1, 0, 8, Factory MAC addr [5] + SPI_PAD_CONFIG_CLK, EFUSE_BLK1, 48, 6, SPI_PAD_configure CLK + SPI_PAD_CONFIG_Q_D1, EFUSE_BLK1, 54, 6, SPI_PAD_configure Q(D1) + SPI_PAD_CONFIG_D_D0, EFUSE_BLK1, 60, 6, SPI_PAD_configure D(D0) + SPI_PAD_CONFIG_CS, EFUSE_BLK1, 66, 6, SPI_PAD_configure CS + SPI_PAD_CONFIG_HD_D3, EFUSE_BLK1, 72, 6, SPI_PAD_configure HD(D3) + SPI_PAD_CONFIG_WP_D2, EFUSE_BLK1, 78, 6, SPI_PAD_configure WP(D2) + SPI_PAD_CONFIG_DQS, EFUSE_BLK1, 84, 6, SPI_PAD_configure DQS + SPI_PAD_CONFIG_D4, EFUSE_BLK1, 90, 6, SPI_PAD_configure D4 + + # RD_MAC_SPI_SYS_3 + SPI_PAD_CONFIG_D5, EFUSE_BLK1, 96, 6, SPI_PAD_configure D5 + SPI_PAD_CONFIG_D6, EFUSE_BLK1, 102, 6, SPI_PAD_configure D6 + SPI_PAD_CONFIG_D7, EFUSE_BLK1, 108, 6, SPI_PAD_configure D7 + WAFER_VERSION_MINOR, EFUSE_BLK1, 114, 3, WAFER_VERSION_MINOR least significant bits + , EFUSE_BLK1, 183, 1, WAFER_VERSION_MINOR most significant bit + # WAFER_VERSION_MINOR most significant bit is from RD_MAC_SPI_SYS_5 + PKG_VERSION, EFUSE_BLK1, 117, 3, Package version + BLK_VERSION_MINOR, EFUSE_BLK1, 120, 3, BLK_VERSION_MINOR + + # RD_MAC_SPI_SYS_5 + # WAFER_VERSION_MINOR most significant bit + WAFER_VERSION_MAJOR, EFUSE_BLK1, 184, 2, WAFER_VERSION_MAJOR + ADC2_CAL_VOL_ATTEN3, EFUSE_BLK1, 186, 6, ADC2 calibration voltage at atten3 + # SYS_DATA_PART1 BLOCK# - System configuration ####################### - OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, Optional unique 128-bit ID - BLOCK2_VERSION, EFUSE_BLK2, 132, 3, Version of BLOCK2 + # RD_SYS_PART1_DATA0 + OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, Optional unique 128-bit ID + + # RD_SYS_PART1_DATA4 + BLK_VERSION_MAJOR, EFUSE_BLK2, 128, 2, BLK_VERSION_MAJOR of BLOCK2 change of this bit means users need to update firmware + TEMP_CALIB, EFUSE_BLK2, 132, 9, Temperature calibration data + OCODE, EFUSE_BLK2, 141, 8, ADC OCode + ADC1_INIT_CODE_ATTEN0, EFUSE_BLK2, 149, 8, ADC1 init code at atten0 + ADC1_INIT_CODE_ATTEN1, EFUSE_BLK2, 157, 6, ADC1 init code at atten1 + + # RD_SYS_PART1_DATA5 + ADC1_INIT_CODE_ATTEN2, EFUSE_BLK2, 163, 6, ADC1 init code at atten2 + ADC1_INIT_CODE_ATTEN3, EFUSE_BLK2, 169, 6, ADC1 init code at atten3 + ADC2_INIT_CODE_ATTEN0, EFUSE_BLK2, 175, 8, ADC2 init code at atten0 + ADC2_INIT_CODE_ATTEN1, EFUSE_BLK2, 183, 6, ADC2 init code at atten1 + ADC2_INIT_CODE_ATTEN2, EFUSE_BLK2, 189, 6, ADC2 init code at atten2 + ADC2_INIT_CODE_ATTEN3, EFUSE_BLK2, 195, 6, ADC2 init code at atten3 + ADC1_CAL_VOL_ATTEN0, EFUSE_BLK2, 201, 8, ADC1 calibration voltage at atten0 + ADC1_CAL_VOL_ATTEN1, EFUSE_BLK2, 209, 8, ADC1 calibration voltage at atten1 + ADC1_CAL_VOL_ATTEN2, EFUSE_BLK2, 217, 8, ADC1 calibration voltage at atten2 + ADC1_CAL_VOL_ATTEN3, EFUSE_BLK2, 225, 8, ADC1 calibration voltage at atten3 + ADC2_CAL_VOL_ATTEN0, EFUSE_BLK2, 233, 8, ADC2 calibration voltage at atten0 + ADC2_CAL_VOL_ATTEN1, EFUSE_BLK2, 241, 7, ADC2 calibration voltage at atten1 + ADC2_CAL_VOL_ATTEN2, EFUSE_BLK2, 248, 7, ADC2 calibration voltage at atten2 ################ USER_DATA, EFUSE_BLK3, 0, 256, User data diff --git a/components/efuse/esp32s3/include/esp_efuse_table.h b/components/efuse/esp32s3/include/esp_efuse_table.h index 5e470450f24..59564cdd929 100644 --- a/components/efuse/esp32s3/include/esp_efuse_table.h +++ b/components/efuse/esp32s3/include/esp_efuse_table.h @@ -17,7 +17,7 @@ extern "C" { #endif -// md5_digest_table 9295c8aa9c48d48dc42c78456bd02645 +// md5_digest_table 466199602f703d803a9f87956236882e // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. @@ -103,6 +103,8 @@ extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_ECC_EN[]; extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[]; extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_OTG_DOWNLOAD_MODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[]; extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CLK[]; extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q_D1[]; @@ -115,12 +117,30 @@ extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D4[]; extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D5[]; extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D6[]; extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D7[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[]; -extern const esp_efuse_desc_t* ESP_EFUSE_BLOCK1_VERSION[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CAL_VOL_ATTEN3[]; extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[]; -extern const esp_efuse_desc_t* ESP_EFUSE_BLOCK2_VERSION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_TEMP_CALIB[]; +extern const esp_efuse_desc_t* ESP_EFUSE_OCODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_INIT_CODE_ATTEN0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_INIT_CODE_ATTEN1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_INIT_CODE_ATTEN2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_INIT_CODE_ATTEN3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CAL_VOL_ATTEN0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CAL_VOL_ATTEN1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CAL_VOL_ATTEN2[]; extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[]; extern const esp_efuse_desc_t* ESP_EFUSE_KEY0[]; extern const esp_efuse_desc_t* ESP_EFUSE_KEY1[]; diff --git a/components/efuse/include/esp_efuse.h b/components/efuse/include/esp_efuse.h index 0413801fab8..bc236df6dcf 100644 --- a/components/efuse/include/esp_efuse.h +++ b/components/efuse/include/esp_efuse.h @@ -269,13 +269,6 @@ esp_err_t esp_efuse_read_block(esp_efuse_block_t blk, void* dst_key, size_t offs */ esp_err_t esp_efuse_write_block(esp_efuse_block_t blk, const void* src_key, size_t offset_in_bits, size_t size_bits); -/** - * @brief Returns chip version from efuse - * - * @return chip version - */ -uint8_t esp_efuse_get_chip_ver(void); - /** * @brief Returns chip package from efuse * diff --git a/components/efuse/src/esp32/esp_efuse_fields.c b/components/efuse/src/esp32/esp_efuse_fields.c index d94946e0f67..57637f4f803 100644 --- a/components/efuse/src/esp32/esp_efuse_fields.c +++ b/components/efuse/src/esp32/esp_efuse_fields.c @@ -21,6 +21,7 @@ #include "esp_err.h" #include "esp_log.h" #include "soc/efuse_periph.h" +#include "hal/efuse_hal.h" #include "bootloader_random.h" #include "sys/param.h" #include "soc/apb_ctrl_reg.h" @@ -29,35 +30,6 @@ const static char *TAG = "efuse"; // Contains functions that provide access to efuse fields which are often used in IDF. -// Returns chip version from efuse -uint8_t esp_efuse_get_chip_ver(void) -{ - uint8_t eco_bit0, eco_bit1, eco_bit2; - esp_efuse_read_field_blob(ESP_EFUSE_CHIP_VER_REV1, &eco_bit0, 1); - esp_efuse_read_field_blob(ESP_EFUSE_CHIP_VER_REV2, &eco_bit1, 1); - eco_bit2 = (REG_READ(APB_CTRL_DATE_REG) & 0x80000000) >> 31; - uint32_t combine_value = (eco_bit2 << 2) | (eco_bit1 << 1) | eco_bit0; - uint8_t chip_ver = 0; - switch (combine_value) { - case 0: - chip_ver = 0; - break; - case 1: - chip_ver = 1; - break; - case 3: - chip_ver = 2; - break; - case 7: - chip_ver = 3; - break; - default: - chip_ver = 0; - break; - } - return chip_ver; -} - // Returns chip package from efuse uint32_t esp_efuse_get_pkg_ver(void) { @@ -79,7 +51,7 @@ esp_err_t esp_efuse_disable_rom_download_mode(void) { #ifndef CONFIG_ESP32_REV_MIN_3 /* Check if we support this revision at all */ - if(esp_efuse_get_chip_ver() < 3) { + if (efuse_hal_get_major_chip_version() < 3) { return ESP_ERR_NOT_SUPPORTED; } #endif diff --git a/components/efuse/src/esp32c3/esp_efuse_fields.c b/components/efuse/src/esp32c3/esp_efuse_fields.c index 7d41bf84d67..4dd265fe537 100644 --- a/components/efuse/src/esp32c3/esp_efuse_fields.c +++ b/components/efuse/src/esp32c3/esp_efuse_fields.c @@ -29,14 +29,6 @@ const static char *TAG = "efuse"; // Contains functions that provide access to efuse fields which are often used in IDF. -// Returns chip version from efuse -uint8_t esp_efuse_get_chip_ver(void) -{ - uint32_t chip_ver = 0; - esp_efuse_read_field_blob(ESP_EFUSE_WAFER_VERSION, &chip_ver, ESP_EFUSE_WAFER_VERSION[0]->bit_count); - return chip_ver; -} - // Returns chip package from efuse uint32_t esp_efuse_get_pkg_ver(void) { diff --git a/components/efuse/src/esp32c3/esp_efuse_rtc_calib.c b/components/efuse/src/esp32c3/esp_efuse_rtc_calib.c index 844463b6f39..e937532161d 100644 --- a/components/efuse/src/esp32c3/esp_efuse_rtc_calib.c +++ b/components/efuse/src/esp32c3/esp_efuse_rtc_calib.c @@ -19,7 +19,7 @@ int esp_efuse_rtc_calib_get_ver(void) { uint32_t result = 0; - esp_efuse_read_field_blob(ESP_EFUSE_BLOCK2_VERSION, &result, 3); + esp_efuse_read_field_blob(ESP_EFUSE_BLK_VERSION_MAJOR, &result, ESP_EFUSE_BLK_VERSION_MAJOR[0]->bit_count); // IDF-5366 return result; } diff --git a/components/efuse/src/esp32s2/esp_efuse_fields.c b/components/efuse/src/esp32s2/esp_efuse_fields.c index e85eb2b1d7a..05e6247f86c 100644 --- a/components/efuse/src/esp32s2/esp_efuse_fields.c +++ b/components/efuse/src/esp32s2/esp_efuse_fields.c @@ -28,15 +28,6 @@ const static char *TAG = "efuse"; // Contains functions that provide access to efuse fields which are often used in IDF. -// Returns chip version from efuse -uint8_t esp_efuse_get_chip_ver(void) -{ - // should return the same value as bootloader_common_get_chip_revision() - uint32_t chip_ver = 0; - esp_efuse_read_field_blob(ESP_EFUSE_WAFER_VERSION, &chip_ver, ESP_EFUSE_WAFER_VERSION[0]->bit_count); - return chip_ver; -} - // Returns chip package from efuse uint32_t esp_efuse_get_pkg_ver(void) { diff --git a/components/efuse/src/esp32s2/esp_efuse_rtc_table.c b/components/efuse/src/esp32s2/esp_efuse_rtc_table.c index d9fcb6c03e8..d51581903bf 100644 --- a/components/efuse/src/esp32s2/esp_efuse_rtc_table.c +++ b/components/efuse/src/esp32s2/esp_efuse_rtc_table.c @@ -98,7 +98,7 @@ static const efuse_map_info_t adc_efuse_raw_map[] = { int esp_efuse_rtc_table_read_calib_version(void) { uint32_t result = 0; - esp_efuse_read_field_blob(ESP_EFUSE_BLOCK2_VERSION, &result, 32); + esp_efuse_read_field_blob(ESP_EFUSE_BLK_VERSION_MINOR, &result, 3); return result; } diff --git a/components/efuse/src/esp32s3/esp_efuse_fields.c b/components/efuse/src/esp32s3/esp_efuse_fields.c index 005793b4323..80210504f10 100644 --- a/components/efuse/src/esp32s3/esp_efuse_fields.c +++ b/components/efuse/src/esp32s3/esp_efuse_fields.c @@ -28,15 +28,6 @@ const static char *TAG = "efuse"; // Contains functions that provide access to efuse fields which are often used in IDF. -// Returns chip version from efuse -uint8_t esp_efuse_get_chip_ver(void) -{ - // should return the same value as bootloader_common_get_chip_revision() - uint32_t chip_ver = 0; - // TODO: ESP32S2 does not have this field - return chip_ver; -} - // Returns chip package from efuse uint32_t esp_efuse_get_pkg_ver(void) { diff --git a/components/efuse/test/test_efuse.c b/components/efuse/test/test_efuse.c index a78111818d2..e19df140634 100644 --- a/components/efuse/test/test_efuse.c +++ b/components/efuse/test/test_efuse.c @@ -853,12 +853,6 @@ TEST_CASE("Test chip_ver_pkg APIs return the same value", "[efuse]") TEST_ASSERT_EQUAL_INT(esp_efuse_get_pkg_ver(), bootloader_common_get_chip_ver_pkg()); } -TEST_CASE("Test chip_revision APIs return the same value", "[efuse]") -{ - esp_efuse_utility_update_virt_blocks(); - TEST_ASSERT_EQUAL_INT(esp_efuse_get_chip_ver(), bootloader_common_get_chip_revision()); -} - #ifndef CONFIG_IDF_TARGET_ESP32 #if CONFIG_IDF_ENV_FPGA || CONFIG_EFUSE_VIRTUAL TEST_CASE("Test writing order is BLK_MAX->BLK0", "[efuse]") diff --git a/components/esp32/system_api_esp32.c b/components/esp32/system_api_esp32.c index b66f42e417d..317243b4102 100644 --- a/components/esp32/system_api_esp32.c +++ b/components/esp32/system_api_esp32.c @@ -30,6 +30,8 @@ #include "soc/rtc.h" #include "hal/wdt_hal.h" #include "hal/cpu_hal.h" +#include "hal/efuse_hal.h" +#include "hal/efuse_ll.h" #include "freertos/xtensa_api.h" #include "soc/soc_memory_layout.h" @@ -150,19 +152,19 @@ void IRAM_ATTR esp_restart_noos(void) void esp_chip_info(esp_chip_info_t* out_info) { - uint32_t efuse_rd3 = REG_READ(EFUSE_BLK0_RDATA3_REG); memset(out_info, 0, sizeof(*out_info)); out_info->model = CHIP_ESP32; - out_info->revision = esp_efuse_get_chip_ver(); + out_info->revision = efuse_hal_get_major_chip_version(); + out_info->full_revision = efuse_hal_chip_revision(); - if ((efuse_rd3 & EFUSE_RD_CHIP_VER_DIS_APP_CPU_M) == 0) { + if (efuse_ll_get_disable_app_cpu() == 0) { out_info->cores = 2; } else { out_info->cores = 1; } out_info->features = CHIP_FEATURE_WIFI_BGN; - if ((efuse_rd3 & EFUSE_RD_CHIP_VER_DIS_BT_M) == 0) { + if (efuse_ll_get_disable_bt() == 0) { out_info->features |= CHIP_FEATURE_BT | CHIP_FEATURE_BLE; } uint32_t package = esp_efuse_get_pkg_ver(); @@ -177,6 +179,6 @@ void esp_chip_info(esp_chip_info_t* out_info) #if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX inline bool soc_has_cache_lock_bug(void) { - return (esp_efuse_get_chip_ver() == 3); + return (efuse_hal_get_major_chip_version() == 3); } #endif diff --git a/components/esp32c3/ld/esp32c3.peripherals.ld b/components/esp32c3/ld/esp32c3.peripherals.ld index 8614a111bbb..77540ca7e80 100644 --- a/components/esp32c3/ld/esp32c3.peripherals.ld +++ b/components/esp32c3/ld/esp32c3.peripherals.ld @@ -6,6 +6,7 @@ PROVIDE ( GPIO = 0x60004000 ); PROVIDE ( SIGMADELTA = 0x60004f00 ); PROVIDE ( RTCCNTL = 0x60008000 ); PROVIDE ( RTCIO = 0x60008400 ); +PROVIDE ( EFUSE = 0x60008800 ); PROVIDE ( HINF = 0x6000B000 ); PROVIDE ( I2S1 = 0x6002d000 ); PROVIDE ( I2C0 = 0x60013000 ); diff --git a/components/esp32c3/system_api_esp32c3.c b/components/esp32c3/system_api_esp32c3.c index e43bdbfab80..3fcbe850ea7 100644 --- a/components/esp32c3/system_api_esp32c3.c +++ b/components/esp32c3/system_api_esp32c3.c @@ -33,6 +33,7 @@ #include "soc/system_reg.h" #include "soc/uart_reg.h" #include "hal/wdt_hal.h" +#include "hal/efuse_hal.h" /* "inner" restart function for after RTOS, interrupts & anything else on this * core are already stopped. Stalls other core, resets hardware, @@ -146,7 +147,8 @@ void esp_chip_info(esp_chip_info_t *out_info) { memset(out_info, 0, sizeof(*out_info)); out_info->model = CHIP_ESP32C3; - out_info->revision = esp_efuse_get_chip_ver(); + out_info->revision = efuse_hal_get_minor_chip_version(); + out_info->full_revision = efuse_hal_chip_revision(); out_info->cores = 1; out_info->features = CHIP_FEATURE_WIFI_BGN | CHIP_FEATURE_BLE; } diff --git a/components/esp32s2/ld/esp32s2.peripherals.ld b/components/esp32s2/ld/esp32s2.peripherals.ld index 512d840f8e2..78453d3eed0 100644 --- a/components/esp32s2/ld/esp32s2.peripherals.ld +++ b/components/esp32s2/ld/esp32s2.peripherals.ld @@ -17,6 +17,7 @@ PROVIDE ( RMTMEM = 0x3f416400 ); PROVIDE ( PCNT = 0x3f417000 ); PROVIDE ( SLC = 0x3f418000 ); PROVIDE ( LEDC = 0x3f419000 ); +PROVIDE ( EFUSE = 0x3f41A000 ); PROVIDE ( CP_DMA = 0x3f4c3000 ); PROVIDE ( TIMERG0 = 0x3f41F000 ); PROVIDE ( TIMERG1 = 0x3f420000 ); diff --git a/components/esp32s2/system_api_esp32s2.c b/components/esp32s2/system_api_esp32s2.c index b22894ae73e..62e25397810 100644 --- a/components/esp32s2/system_api_esp32s2.c +++ b/components/esp32s2/system_api_esp32s2.c @@ -31,6 +31,8 @@ #include "hal/wdt_hal.h" #include "freertos/xtensa_api.h" #include "hal/cpu_hal.h" +#include "hal/efuse_ll.h" +#include "hal/efuse_hal.h" /* "inner" restart function for after RTOS, interrupts & anything else on this * core are already stopped. Stalls other core, resets hardware, @@ -118,11 +120,12 @@ void IRAM_ATTR esp_restart_noos(void) void esp_chip_info(esp_chip_info_t *out_info) { - uint32_t pkg_ver = esp_efuse_get_pkg_ver(); + uint32_t pkg_ver = efuse_ll_get_chip_ver_pkg(); memset(out_info, 0, sizeof(*out_info)); out_info->model = CHIP_ESP32S2; + out_info->full_revision = efuse_hal_chip_revision(); out_info->cores = 1; out_info->features = CHIP_FEATURE_WIFI_BGN; diff --git a/components/esp32s3/ld/esp32s3.peripherals.ld b/components/esp32s3/ld/esp32s3.peripherals.ld index 57939ae1c80..4cd54779996 100644 --- a/components/esp32s3/ld/esp32s3.peripherals.ld +++ b/components/esp32s3/ld/esp32s3.peripherals.ld @@ -3,6 +3,7 @@ PROVIDE ( SPIMEM1 = 0x60002000 ); PROVIDE ( SPIMEM0 = 0x60003000 ); PROVIDE ( GPIO = 0x60004000 ); PROVIDE ( SIGMADELTA = 0x60004f00 ); +PROVIDE ( EFUSE = 0x60007000 ); PROVIDE ( RTCCNTL = 0x60008000 ); PROVIDE ( RTCIO = 0x60008400 ); PROVIDE ( SENS = 0x60008800 ); diff --git a/components/esp32s3/system_api_esp32s3.c b/components/esp32s3/system_api_esp32s3.c index 33cb5778d0b..c68c73cbf63 100644 --- a/components/esp32s3/system_api_esp32s3.c +++ b/components/esp32s3/system_api_esp32s3.c @@ -28,6 +28,7 @@ #include "soc/rtc.h" #include "soc/syscon_reg.h" #include "hal/wdt_hal.h" +#include "hal/efuse_hal.h" #include "freertos/xtensa_api.h" /* "inner" restart function for after RTOS, interrupts & anything else on this @@ -152,6 +153,7 @@ void esp_chip_info(esp_chip_info_t *out_info) { memset(out_info, 0, sizeof(*out_info)); out_info->model = CHIP_ESP32S3; + out_info->full_revision = efuse_hal_chip_revision(); out_info->cores = 2; out_info->features = CHIP_FEATURE_WIFI_BGN; } diff --git a/components/esp_hw_support/port/esp32/rtc_clk.c b/components/esp_hw_support/port/esp32/rtc_clk.c index 3203ef6e36a..af81df1fbdc 100644 --- a/components/esp_hw_support/port/esp32/rtc_clk.c +++ b/components/esp_hw_support/port/esp32/rtc_clk.c @@ -24,6 +24,8 @@ #include "soc/rtc_periph.h" #include "soc/sens_periph.h" #include "soc/dport_reg.h" +#include "hal/efuse_ll.h" +#include "hal/efuse_hal.h" #include "soc/efuse_periph.h" #include "soc/apb_ctrl_reg.h" #include "soc/gpio_struct.h" @@ -129,7 +131,7 @@ static void rtc_clk_32k_enable_common(int dac, int dres, int dbias) REG_SET_FIELD(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_DBIAS_XTAL_32K, dbias); #ifdef CONFIG_ESP32_RTC_EXT_CRYST_ADDIT_CURRENT - uint8_t chip_ver = esp_efuse_get_chip_ver(); + uint8_t chip_ver = efuse_hal_get_major_chip_version(); // version0 and version1 need provide additional current to external XTAL. if(chip_ver == 0 || chip_ver == 1) { /* TOUCH sensor can provide additional current to external XTAL. @@ -145,7 +147,7 @@ static void rtc_clk_32k_enable_common(int dac, int dres, int dbias) SET_PERI_REG_MASK(RTC_IO_TOUCH_PAD9_REG, RTC_IO_TOUCH_PAD9_XPD_M); } #elif defined CONFIG_ESP32_RTC_EXT_CRYST_ADDIT_CURRENT_V2 - uint8_t chip_ver = esp_efuse_get_chip_ver(); + uint8_t chip_ver = efuse_hal_get_major_chip_version(); if(chip_ver == 0 || chip_ver == 1) { /* TOUCH sensor can provide additional current to external XTAL. In some case, X32N and X32P PAD don't have enough drive capability to start XTAL */ @@ -179,13 +181,13 @@ void rtc_clk_32k_enable(bool enable) CLEAR_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_X32N_MUX_SEL | RTC_IO_X32P_MUX_SEL); #ifdef CONFIG_ESP32_RTC_EXT_CRYST_ADDIT_CURRENT - uint8_t chip_ver = esp_efuse_get_chip_ver(); + uint8_t chip_ver = efuse_hal_get_major_chip_version(); if(chip_ver == 0 || chip_ver == 1) { /* Power down TOUCH */ CLEAR_PERI_REG_MASK(RTC_IO_TOUCH_PAD9_REG, RTC_IO_TOUCH_PAD9_XPD_M); } #elif defined CONFIG_ESP32_RTC_EXT_CRYST_ADDIT_CURRENT_V2 - uint8_t chip_ver = esp_efuse_get_chip_ver(); + uint8_t chip_ver = efuse_hal_get_major_chip_version(); if(chip_ver == 0 || chip_ver == 1) { /* Power down TOUCH */ CLEAR_PERI_REG_MASK(RTC_IO_TOUCH_CFG_REG, RTC_IO_TOUCH_XPD_BIAS_M); @@ -288,8 +290,7 @@ void rtc_clk_apll_enable(bool enable, uint32_t sdm0, uint32_t sdm1, uint32_t sdm if (enable) { uint8_t sdm_stop_val_2 = APLL_SDM_STOP_VAL_2_REV1; - uint32_t is_rev0 = (GET_PERI_REG_BITS2(EFUSE_BLK0_RDATA3_REG, 1, 15) == 0); - if (is_rev0) { + if (efuse_hal_get_major_chip_version() == 0) { sdm0 = 0; sdm1 = 0; sdm_stop_val_2 = APLL_SDM_STOP_VAL_2_REV0; diff --git a/components/esp_hw_support/port/esp32/rtc_init.c b/components/esp_hw_support/port/esp32/rtc_init.c index 67fd56bba8b..91931dc8d16 100644 --- a/components/esp_hw_support/port/esp32/rtc_init.c +++ b/components/esp_hw_support/port/esp32/rtc_init.c @@ -19,6 +19,7 @@ #include "soc/rtc_periph.h" #include "soc/dport_reg.h" #include "soc/efuse_periph.h" +#include "hal/efuse_ll.h" #include "soc/gpio_periph.h" @@ -126,7 +127,7 @@ rtc_vddsdio_config_t rtc_vddsdio_get_config(void) result.tieh = (efuse_reg & EFUSE_RD_SDIO_TIEH_M) >> EFUSE_RD_SDIO_TIEH_S; //DREFH/M/L eFuse are used for EFUSE_ADC_VREF instead. Therefore tuning //will only be available on older chips that don't have EFUSE_ADC_VREF - if(REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG ,EFUSE_RD_BLK3_PART_RESERVE) == 0){ + if(!efuse_ll_get_blk3_part_reserve()){ //BLK3_PART_RESERVE indicates the presence of EFUSE_ADC_VREF // in this case, DREFH/M/L are also set from EFUSE result.drefh = (efuse_reg & EFUSE_RD_SDIO_DREFH_M) >> EFUSE_RD_SDIO_DREFH_S; diff --git a/components/esp_hw_support/port/esp32c3/rtc_init.c b/components/esp_hw_support/port/esp32c3/rtc_init.c index 724b9bdffb4..a8b0c7e0fcc 100644 --- a/components/esp_hw_support/port/esp32c3/rtc_init.c +++ b/components/esp_hw_support/port/esp32c3/rtc_init.c @@ -22,6 +22,7 @@ #include "soc/spi_mem_reg.h" #include "soc/extmem_reg.h" #include "soc/system_reg.h" +#include "hal/efuse_hal.h" #include "regi2c_ctrl.h" #include "soc_log.h" #include "esp_efuse.h" @@ -58,7 +59,7 @@ void rtc_init(rtc_config_t cfg) if (cfg.cali_ocode) { uint32_t rtc_calib_version = 0; - esp_err_t err = esp_efuse_read_field_blob(ESP_EFUSE_BLOCK2_VERSION, &rtc_calib_version, 3); + esp_err_t err = esp_efuse_read_field_blob(ESP_EFUSE_BLK_VERSION_MAJOR, &rtc_calib_version, ESP_EFUSE_BLK_VERSION_MAJOR[0]->bit_count); // IDF-5366 if (err != ESP_OK) { rtc_calib_version = 0; SOC_LOGW(TAG, "efuse read fail, set default rtc_calib_version: %d\n", rtc_calib_version); @@ -326,7 +327,7 @@ static void set_rtc_dig_dbias() 3. a reasonable rtc_dbias can be calculated by a certion formula. */ uint32_t rtc_dbias = 28, dig_dbias = 28; - uint8_t chip_version = esp_efuse_get_chip_ver(); + uint8_t chip_version = efuse_hal_get_minor_chip_version(); if (chip_version >= 3) { dig_dbias = get_dig_dbias_by_efuse(chip_version); if (dig_dbias != 0) { diff --git a/components/esp_hw_support/port/esp32c3/rtc_sleep.c b/components/esp_hw_support/port/esp32c3/rtc_sleep.c index f1150910a1b..a37c102c055 100644 --- a/components/esp_hw_support/port/esp32c3/rtc_sleep.c +++ b/components/esp_hw_support/port/esp32c3/rtc_sleep.c @@ -29,7 +29,7 @@ #include "esp32c3/rom/ets_sys.h" #include "esp32c3/rom/rtc.h" #include "regi2c_ctrl.h" -#include "esp_efuse.h" +#include "hal/efuse_hal.h" /** * Configure whether certain peripherals are powered down in deep sleep @@ -102,7 +102,7 @@ void rtc_sleep_init(rtc_sleep_config_t cfg) CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU); unsigned atten_deep_sleep = RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT; #if CONFIG_ESP32C3_REV_MIN < 3 - if (esp_efuse_get_chip_ver() < 3) { + if (efuse_hal_get_minor_chip_version() < 3) { atten_deep_sleep = 0; /* workaround for deep sleep issue in high temp on ECO2 and below */ } #endif diff --git a/components/esp_hw_support/port/esp32s2/rtc_init.c b/components/esp_hw_support/port/esp32s2/rtc_init.c index 82909f58c36..cfcb941c0b7 100644 --- a/components/esp_hw_support/port/esp32s2/rtc_init.c +++ b/components/esp_hw_support/port/esp32s2/rtc_init.c @@ -159,7 +159,7 @@ void rtc_init(rtc_config_t cfg) if (cfg.cali_ocode) { uint32_t rtc_calib_version = 0; - esp_efuse_read_field_blob(ESP_EFUSE_BLOCK2_VERSION, &rtc_calib_version, 32); + esp_efuse_read_field_blob(ESP_EFUSE_BLK_VERSION_MINOR, &rtc_calib_version, ESP_EFUSE_BLK_VERSION_MINOR[0]->bit_count); // IDF-5366 if (rtc_calib_version == 2) { set_ocode_by_efuse(rtc_calib_version); } else { diff --git a/components/esp_system/include/esp_system.h b/components/esp_system/include/esp_system.h index bd9bb1a6c42..46e8b2a9fc6 100644 --- a/components/esp_system/include/esp_system.h +++ b/components/esp_system/include/esp_system.h @@ -281,6 +281,7 @@ typedef enum { typedef struct { esp_chip_model_t model; //!< chip model, one of esp_chip_model_t uint32_t features; //!< bit mask of CHIP_FEATURE_x feature flags + uint16_t full_revision; //!< chip revision number (in format MXX; where M - wafer major version, XX - wafer minor version) uint8_t cores; //!< number of CPU cores uint8_t revision; //!< chip revision number } esp_chip_info_t; diff --git a/components/esp_wifi/src/phy_init.c b/components/esp_wifi/src/phy_init.c index d46b8189526..72aa3f2a0ee 100644 --- a/components/esp_wifi/src/phy_init.c +++ b/components/esp_wifi/src/phy_init.c @@ -48,6 +48,7 @@ #include "esp32s3/rom/rtc.h" #include "soc/rtc_cntl_reg.h" #endif +#include "hal/efuse_hal.h" #if CONFIG_IDF_TARGET_ESP32 extern wifi_mac_time_update_cb_t s_wifi_mac_time_update_cb; @@ -674,7 +675,7 @@ void esp_phy_load_cal_and_init(void) ESP_LOGI(TAG, "phy_version %s", phy_version); #if CONFIG_IDF_TARGET_ESP32S2 - phy_eco_version_sel(esp_efuse_get_chip_ver()); + phy_eco_version_sel(efuse_hal_get_major_chip_version()); #endif esp_phy_calibration_data_t* cal_data = diff --git a/components/hal/CMakeLists.txt b/components/hal/CMakeLists.txt index 874cc23f68b..3c283e1630b 100644 --- a/components/hal/CMakeLists.txt +++ b/components/hal/CMakeLists.txt @@ -1,7 +1,9 @@ idf_build_get_property(target IDF_TARGET) set(srcs "wdt_hal_iram.c" - "mpu_hal.c") + "mpu_hal.c" + "efuse_hal.c" + "${target}/efuse_hal.c") set(includes "${target}/include" "include") if(NOT BOOTLOADER_BUILD) diff --git a/components/hal/efuse_hal.c b/components/hal/efuse_hal.c new file mode 100644 index 00000000000..00729076fe7 --- /dev/null +++ b/components/hal/efuse_hal.c @@ -0,0 +1,17 @@ +/* + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "sdkconfig.h" +#include +#include "soc/soc_caps.h" +#include "hal/efuse_ll.h" +#include "hal/efuse_hal.h" + + +uint32_t efuse_hal_chip_revision(void) +{ + return efuse_hal_get_major_chip_version() * 100 + efuse_hal_get_minor_chip_version(); +} diff --git a/components/hal/esp32/efuse_hal.c b/components/hal/esp32/efuse_hal.c new file mode 100644 index 00000000000..a37aa39b816 --- /dev/null +++ b/components/hal/esp32/efuse_hal.c @@ -0,0 +1,58 @@ +/* + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "sdkconfig.h" +#include +#include "soc/soc_caps.h" +#include "hal/efuse_ll.h" +#include "hal/efuse_hal.h" +#include "soc/syscon_reg.h" + +uint32_t efuse_hal_get_major_chip_version(void) +{ + uint8_t eco_bit0 = efuse_ll_get_chip_ver_rev1(); + uint8_t eco_bit1 = efuse_ll_get_chip_ver_rev2(); + uint8_t eco_bit2 = (REG_READ(SYSCON_DATE_REG) & 0x80000000) >> 31; + uint32_t combine_value = (eco_bit2 << 2) | (eco_bit1 << 1) | eco_bit0; + uint32_t chip_ver = 0; + switch (combine_value) { + case 0: + chip_ver = 0; + break; + case 1: + chip_ver = 1; + break; + case 3: + chip_ver = 2; + break; +#if CONFIG_IDF_ENV_FPGA + case 4: /* Empty efuses, but SYSCON_DATE_REG bit is set */ + chip_ver = 3; + break; +#endif // CONFIG_IDF_ENV_FPGA + case 7: + chip_ver = 3; + break; + default: + chip_ver = 0; + break; + } + return chip_ver; +} + +uint32_t efuse_hal_get_minor_chip_version(void) +{ + return efuse_ll_get_chip_wafer_version_minor(); +} + +uint32_t efuse_hal_get_rated_freq_mhz(void) +{ + //Check if ESP32 is rated for a CPU frequency of 160MHz only + if (efuse_ll_get_chip_cpu_freq_rated() && efuse_ll_get_chip_cpu_freq_low()) { + return 160; + } + return 240; +} diff --git a/components/hal/esp32/include/hal/efuse_hal.h b/components/hal/esp32/include/hal/efuse_hal.h new file mode 100644 index 00000000000..a0b087e8135 --- /dev/null +++ b/components/hal/esp32/include/hal/efuse_hal.h @@ -0,0 +1,26 @@ +/* + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include +#include "soc/soc_caps.h" +#include "hal/efuse_ll.h" +#include_next "hal/efuse_hal.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief get rated frequency in MHz + */ +uint32_t efuse_hal_get_rated_freq_mhz(void); + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32/include/hal/efuse_ll.h b/components/hal/esp32/include/hal/efuse_ll.h new file mode 100644 index 00000000000..d1c5e689a71 --- /dev/null +++ b/components/hal/esp32/include/hal/efuse_ll.h @@ -0,0 +1,212 @@ +/* + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include +#include "soc/efuse_periph.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// Always inline these functions even no gcc optimization is applied. + +/******************* eFuse fields *************************/ + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_flash_crypt_cnt(void) +{ + return REG_GET_FIELD(EFUSE_BLK0_RDATA0_REG, EFUSE_RD_FLASH_CRYPT_CNT); +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac0(void) +{ + return REG_READ(EFUSE_BLK0_RDATA1_REG); +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac1(void) +{ + return REG_GET_FIELD(EFUSE_BLK0_RDATA2_REG, EFUSE_RD_WIFI_MAC_CRC_HIGH) & 0x0000FFFF; +} + +__attribute__((always_inline)) static inline bool efuse_ll_get_secure_boot_v1_en(void) +{ + return REG_GET_BIT(EFUSE_BLK0_RDATA6_REG, EFUSE_RD_ABS_DONE_0); +} + +__attribute__((always_inline)) static inline bool efuse_ll_get_secure_boot_v2_en(void) +{ + return REG_GET_BIT(EFUSE_BLK0_RDATA6_REG, EFUSE_RD_ABS_DONE_1); +} + +__attribute__((always_inline)) static inline bool efuse_ll_get_sdio_force(void) +{ + return REG_GET_BIT(EFUSE_BLK0_RDATA4_REG, EFUSE_RD_SDIO_FORCE); +} + +__attribute__((always_inline)) static inline bool efuse_ll_get_xpd_sdio(void) +{ + return REG_GET_BIT(EFUSE_BLK0_RDATA4_REG, EFUSE_RD_XPD_SDIO_REG); +} + +__attribute__((always_inline)) static inline bool efuse_ll_get_sdio_tieh(void) +{ + return REG_GET_BIT(EFUSE_BLK0_RDATA4_REG, EFUSE_RD_SDIO_TIEH); +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_sdio_drefh(void) +{ + return REG_GET_FIELD(EFUSE_BLK0_RDATA0_REG, EFUSE_RD_SDIO_DREFH); +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_sdio_drefm(void) +{ + return REG_GET_FIELD(EFUSE_BLK0_RDATA0_REG, EFUSE_RD_SDIO_DREFM); +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_sdio_drefl(void) +{ + return REG_GET_FIELD(EFUSE_BLK0_RDATA0_REG, EFUSE_RD_SDIO_DREFL); +} + +__attribute__((always_inline)) static inline bool efuse_ll_get_blk3_part_reserve(void) +{ + return REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_BLK3_PART_RESERVE); +} + +__attribute__((always_inline)) static inline bool efuse_ll_get_chip_cpu_freq_rated(void) +{ + return REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_CPU_FREQ_RATED); +} + +__attribute__((always_inline)) static inline bool efuse_ll_get_chip_cpu_freq_low(void) +{ + return REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_CPU_FREQ_LOW); +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_ver_pkg(void) +{ + uint32_t pkg_version = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_PKG); + uint32_t pkg_version_4bit = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_PKG_4BIT); + return (pkg_version_4bit << 3) | pkg_version; +} + +// use efuse_hal_get_major_chip_version() to get full major chip version +__attribute__((always_inline)) static inline bool efuse_ll_get_chip_ver_rev1(void) +{ + return REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_REV1); +} + +// use efuse_hal_get_major_chip_version() to get full major chip version +__attribute__((always_inline)) static inline bool efuse_ll_get_chip_ver_rev2(void) +{ + return REG_GET_BIT(EFUSE_BLK0_RDATA5_REG, EFUSE_RD_CHIP_VER_REV2); +} + +// use efuse_hal_get_minor_chip_version() to get minor chip version +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_minor(void) +{ + return REG_GET_FIELD(EFUSE_BLK0_RDATA5_REG, EFUSE_RD_WAFER_VERSION_MINOR); +} + +__attribute__((always_inline)) static inline bool efuse_ll_get_disable_wafer_version_major(void) +{ + return false; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_coding_scheme(void) +{ + return REG_GET_FIELD(EFUSE_BLK0_RDATA6_REG, EFUSE_CODING_SCHEME); +} + +__attribute__((always_inline)) static inline bool efuse_ll_get_disable_app_cpu(void) +{ + return REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_DIS_APP_CPU); +} + +__attribute__((always_inline)) static inline bool efuse_ll_get_disable_bt(void) +{ + return REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_DIS_BT); +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_vol_level_hp_inv(void) +{ + return REG_GET_FIELD(EFUSE_BLK0_RDATA5_REG, EFUSE_RD_VOL_LEVEL_HP_INV); +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_adc_vref(void) +{ + return REG_GET_FIELD(EFUSE_BLK0_RDATA4_REG, EFUSE_RD_ADC_VREF); +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_adc1_tp_low(void) +{ + return REG_GET_FIELD(EFUSE_BLK3_RDATA3_REG, EFUSE_RD_ADC1_TP_LOW); +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_adc2_tp_low(void) +{ + return REG_GET_FIELD(EFUSE_BLK3_RDATA3_REG, EFUSE_RD_ADC2_TP_LOW); +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_adc1_tp_high(void) +{ + return REG_GET_FIELD(EFUSE_BLK3_RDATA3_REG, EFUSE_RD_ADC1_TP_HIGH); +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_adc2_tp_high(void) +{ + return REG_GET_FIELD(EFUSE_BLK3_RDATA3_REG, EFUSE_RD_ADC2_TP_HIGH); +} + +/******************* eFuse control functions *************************/ + +__attribute__((always_inline)) static inline bool efuse_ll_get_cmd(void) +{ + return REG_READ(EFUSE_CMD_REG); +} + +__attribute__((always_inline)) static inline void efuse_ll_set_read_cmd(void) +{ + REG_WRITE(EFUSE_CMD_REG, EFUSE_READ_CMD); +} + +__attribute__((always_inline)) static inline void efuse_ll_set_pgm_cmd(void) +{ + REG_WRITE(EFUSE_CMD_REG, EFUSE_PGM_CMD); +} + +__attribute__((always_inline)) static inline void efuse_ll_set_conf_read_op_code(void) +{ + REG_WRITE(EFUSE_CONF_REG, EFUSE_READ_OP_CODE); +} + +__attribute__((always_inline)) static inline void efuse_ll_set_conf_write_op_code(void) +{ + REG_WRITE(EFUSE_CONF_REG, EFUSE_WRITE_OP_CODE); +} + +__attribute__((always_inline)) static inline void efuse_ll_set_dac_clk_div(uint32_t value) +{ + REG_SET_FIELD(EFUSE_DAC_CONF_REG, EFUSE_DAC_CLK_DIV, value); +} + +__attribute__((always_inline)) static inline void efuse_ll_set_dac_clk_sel0(uint32_t value) +{ + REG_SET_FIELD(EFUSE_CLK_REG, EFUSE_CLK_SEL0, value); +} + +__attribute__((always_inline)) static inline void efuse_ll_set_dac_clk_sel1(uint32_t value) +{ + REG_SET_FIELD(EFUSE_CLK_REG, EFUSE_CLK_SEL1, value); +} + +/******************* eFuse control functions *************************/ + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c3/efuse_hal.c b/components/hal/esp32c3/efuse_hal.c new file mode 100644 index 00000000000..2529be75693 --- /dev/null +++ b/components/hal/esp32c3/efuse_hal.c @@ -0,0 +1,21 @@ +/* + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "sdkconfig.h" +#include +#include "soc/soc_caps.h" +#include "hal/efuse_hal.h" +#include "hal/efuse_ll.h" + +uint32_t efuse_hal_get_major_chip_version(void) +{ + return efuse_ll_get_chip_wafer_version_major(); +} + +uint32_t efuse_hal_get_minor_chip_version(void) +{ + return efuse_ll_get_chip_wafer_version_minor(); +} diff --git a/components/hal/esp32c3/include/hal/efuse_ll.h b/components/hal/esp32c3/include/hal/efuse_ll.h new file mode 100644 index 00000000000..77e5463bf60 --- /dev/null +++ b/components/hal/esp32c3/include/hal/efuse_ll.h @@ -0,0 +1,132 @@ +/* + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include +#include "soc/efuse_periph.h" +#include +#include "esp32c3/rom/efuse.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// Always inline these functions even no gcc optimization is applied. + +/******************* eFuse fields *************************/ + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_flash_crypt_cnt(void) +{ + return EFUSE.rd_repeat_data1.spi_boot_crypt_cnt; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_wdt_delay_sel(void) +{ + return EFUSE.rd_repeat_data1.wdt_delay_sel; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac0(void) +{ + return EFUSE.rd_mac_spi_sys_0; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac1(void) +{ + return EFUSE.rd_mac_spi_sys_1.mac_1; +} + +__attribute__((always_inline)) static inline bool efuse_ll_get_secure_boot_v2_en(void) +{ + return EFUSE.rd_repeat_data2.secure_boot_en; +} + +__attribute__((always_inline)) static inline bool efuse_ll_get_err_rst_enable(void) +{ + return EFUSE.rd_repeat_data3.err_rst_enable; +} + +// use efuse_hal_get_major_chip_version() to get major chip version +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_major(void) +{ + return EFUSE.rd_mac_spi_sys_5.wafer_version_major; +} + +// use efuse_hal_get_minor_chip_version() to get minor chip version +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_minor(void) +{ + return (EFUSE.rd_mac_spi_sys_5.wafer_version_minor_high << 3) + EFUSE.rd_mac_spi_sys_3.wafer_version_minor_low; +} + +__attribute__((always_inline)) static inline bool efuse_ll_get_disable_wafer_version_major(void) +{ + return EFUSE.rd_repeat_data4.disable_wafer_version_major; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_blk_version_major(void) +{ + return EFUSE.rd_sys_part1_data4.blk_version_major; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_blk_version_minor(void) +{ + return EFUSE.rd_mac_spi_sys_3.blk_version_minor; +} + +__attribute__((always_inline)) static inline bool efuse_ll_get_disable_blk_version_major(void) +{ + return EFUSE.rd_repeat_data4.disable_blk_version_major; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_ver_pkg(void) +{ + return EFUSE.rd_mac_spi_sys_3.pkg_version; +} + +/******************* eFuse control functions *************************/ + +__attribute__((always_inline)) static inline bool efuse_ll_get_read_cmd(void) +{ + return EFUSE.cmd.read_cmd; +} + +__attribute__((always_inline)) static inline bool efuse_ll_get_pgm_cmd(void) +{ + return EFUSE.cmd.pgm_cmd; +} + +__attribute__((always_inline)) static inline void efuse_ll_set_read_cmd(void) +{ + EFUSE.cmd.read_cmd = 1; +} + +__attribute__((always_inline)) static inline void efuse_ll_set_pgm_cmd(uint32_t block) +{ + assert(block < ETS_EFUSE_BLOCK_MAX); + EFUSE.cmd.val = ((block << EFUSE_BLK_NUM_S) & EFUSE_BLK_NUM_M) | EFUSE_PGM_CMD; +} + +__attribute__((always_inline)) static inline void efuse_ll_set_conf_read_op_code(void) +{ + EFUSE.conf.op_code = EFUSE_READ_OP_CODE; +} + +__attribute__((always_inline)) static inline void efuse_ll_set_conf_write_op_code(void) +{ + EFUSE.conf.op_code = EFUSE_WRITE_OP_CODE; +} + +__attribute__((always_inline)) static inline void efuse_ll_set_pwr_off_num(uint16_t value) +{ + EFUSE.wr_tim_conf2.pwr_off_num = value; +} + +/******************* eFuse control functions *************************/ + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32s2/efuse_hal.c b/components/hal/esp32s2/efuse_hal.c new file mode 100644 index 00000000000..2529be75693 --- /dev/null +++ b/components/hal/esp32s2/efuse_hal.c @@ -0,0 +1,21 @@ +/* + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "sdkconfig.h" +#include +#include "soc/soc_caps.h" +#include "hal/efuse_hal.h" +#include "hal/efuse_ll.h" + +uint32_t efuse_hal_get_major_chip_version(void) +{ + return efuse_ll_get_chip_wafer_version_major(); +} + +uint32_t efuse_hal_get_minor_chip_version(void) +{ + return efuse_ll_get_chip_wafer_version_minor(); +} diff --git a/components/hal/esp32s2/include/hal/efuse_ll.h b/components/hal/esp32s2/include/hal/efuse_ll.h new file mode 100644 index 00000000000..6358444f3b6 --- /dev/null +++ b/components/hal/esp32s2/include/hal/efuse_ll.h @@ -0,0 +1,152 @@ +/* + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include +#include "soc/efuse_periph.h" +#include +#include "esp32s2/rom/efuse.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// Always inline these functions even no gcc optimization is applied. + +/******************* eFuse fields *************************/ + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_flash_crypt_cnt(void) +{ + return EFUSE.rd_repeat_data1.spi_boot_crypt_cnt; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_wdt_delay_sel(void) +{ + return EFUSE.rd_repeat_data1.wdt_delay_sel; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac0(void) +{ + return EFUSE.rd_mac_spi_8m_0; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac1(void) +{ + return EFUSE.rd_mac_spi_8m_1.mac_1; +} + +__attribute__((always_inline)) static inline bool efuse_ll_get_secure_boot_v2_en(void) +{ + return EFUSE.rd_repeat_data2.secure_boot_en; +} + +// use efuse_hal_get_major_chip_version() to get major chip version +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_major(void) +{ + return EFUSE.rd_mac_spi_8m_3.wafer_version_major; +} + +// use efuse_hal_get_minor_chip_version() to get minor chip version +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_minor(void) +{ + return (EFUSE.rd_mac_spi_8m_3.wafer_version_minor_high << 3) + EFUSE.rd_mac_spi_8m_4.wafer_version_minor_low; +} + +__attribute__((always_inline)) static inline bool efuse_ll_get_disable_wafer_version_major(void) +{ + return EFUSE.rd_repeat_data4.disable_wafer_version_major; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_blk_version_major(void) +{ + return EFUSE.rd_mac_spi_8m_3.blk_version_major; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_blk_version_minor(void) +{ + return EFUSE.rd_sys_data4.blk_version_minor; +} + +__attribute__((always_inline)) static inline bool efuse_ll_get_disable_blk_version_major(void) +{ + return EFUSE.rd_repeat_data4.disable_blk_version_major; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_ver_pkg(void) +{ + return EFUSE.rd_mac_spi_8m_4.pkg_version; +} + +__attribute__((always_inline)) static inline bool efuse_ll_get_sdio_force(void) +{ + return EFUSE.rd_repeat_data1.sdio_force; +} + +__attribute__((always_inline)) static inline bool efuse_ll_get_sdio_tieh(void) +{ + return EFUSE.rd_repeat_data1.sdio_tieh; +} + +__attribute__((always_inline)) static inline bool efuse_ll_get_sdio_xpd(void) +{ + return EFUSE.rd_repeat_data1.sdio_xpd; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_sdio_drefl(void) +{ + return EFUSE.rd_repeat_data1.sdio_drefl; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_sdio_drefm(void) +{ + return EFUSE.rd_repeat_data1.sdio_drefm; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_sdio_drefh(void) +{ + return EFUSE.rd_repeat_data0.sdio_drefh; +} + +/******************* eFuse control functions *************************/ + +__attribute__((always_inline)) static inline bool efuse_ll_get_read_cmd(void) +{ + return EFUSE.cmd.read_cmd; +} + +__attribute__((always_inline)) static inline bool efuse_ll_get_pgm_cmd(void) +{ + return EFUSE.cmd.pgm_cmd; +} + +__attribute__((always_inline)) static inline void efuse_ll_set_read_cmd(void) +{ + EFUSE.cmd.read_cmd = 1; +} + +__attribute__((always_inline)) static inline void efuse_ll_set_pgm_cmd(uint32_t block) +{ + assert(block < ETS_EFUSE_BLOCK_MAX); + EFUSE.cmd.val = ((block << EFUSE_BLK_NUM_S) & EFUSE_BLK_NUM_M) | EFUSE_PGM_CMD; +} + +__attribute__((always_inline)) static inline void efuse_ll_set_conf_read_op_code(void) +{ + EFUSE.conf.op_code = EFUSE_READ_OP_CODE; +} + +__attribute__((always_inline)) static inline void efuse_ll_set_conf_write_op_code(void) +{ + EFUSE.conf.op_code = EFUSE_WRITE_OP_CODE; +} + +/******************* eFuse control functions *************************/ + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32s3/efuse_hal.c b/components/hal/esp32s3/efuse_hal.c new file mode 100644 index 00000000000..2529be75693 --- /dev/null +++ b/components/hal/esp32s3/efuse_hal.c @@ -0,0 +1,21 @@ +/* + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "sdkconfig.h" +#include +#include "soc/soc_caps.h" +#include "hal/efuse_hal.h" +#include "hal/efuse_ll.h" + +uint32_t efuse_hal_get_major_chip_version(void) +{ + return efuse_ll_get_chip_wafer_version_major(); +} + +uint32_t efuse_hal_get_minor_chip_version(void) +{ + return efuse_ll_get_chip_wafer_version_minor(); +} diff --git a/components/hal/esp32s3/include/hal/efuse_ll.h b/components/hal/esp32s3/include/hal/efuse_ll.h new file mode 100644 index 00000000000..6a9b5d7e23b --- /dev/null +++ b/components/hal/esp32s3/include/hal/efuse_ll.h @@ -0,0 +1,132 @@ +/* + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include +#include "soc/efuse_periph.h" +#include +#include "esp32s3/rom/efuse.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// Always inline these functions even no gcc optimization is applied. + +/******************* eFuse fields *************************/ + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_flash_crypt_cnt(void) +{ + return EFUSE.rd_repeat_data1.reg_spi_boot_crypt_cnt; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_wdt_delay_sel(void) +{ + return EFUSE.rd_repeat_data1.reg_wdt_delay_sel; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_flash_type(void) +{ + return EFUSE.rd_repeat_data3.reg_flash_type; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac0(void) +{ + return EFUSE.rd_mac_spi_sys_0; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac1(void) +{ + return EFUSE.rd_mac_spi_sys_1.reg_mac_1; +} + +__attribute__((always_inline)) static inline bool efuse_ll_get_secure_boot_v2_en(void) +{ + return EFUSE.rd_repeat_data2.reg_secure_boot_en; +} + +// use efuse_hal_get_major_chip_version() to get major chip version +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_major(void) +{ + return EFUSE.rd_mac_spi_sys_5.wafer_version_major; +} + +// use efuse_hal_get_minor_chip_version() to get minor chip version +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_minor(void) +{ + return (EFUSE.rd_mac_spi_sys_5.wafer_version_minor_high << 3) + EFUSE.rd_mac_spi_sys_3.wafer_version_minor_low; +} + +__attribute__((always_inline)) static inline bool efuse_ll_get_disable_wafer_version_major(void) +{ + return EFUSE.rd_repeat_data4.disable_wafer_version_major; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_blk_version_major(void) +{ + return EFUSE.rd_sys_part1_data4.blk_version_major; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_blk_version_minor(void) +{ + return EFUSE.rd_mac_spi_sys_3.blk_version_minor; +} + +__attribute__((always_inline)) static inline bool efuse_ll_get_disable_blk_version_major(void) +{ + return EFUSE.rd_repeat_data4.disable_blk_version_major; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_ver_pkg(void) +{ + return 0; +} + +/******************* eFuse control functions *************************/ + +__attribute__((always_inline)) static inline bool efuse_ll_get_read_cmd(void) +{ + return EFUSE.cmd.read_cmd; +} + +__attribute__((always_inline)) static inline bool efuse_ll_get_pgm_cmd(void) +{ + return EFUSE.cmd.pgm_cmd; +} + +__attribute__((always_inline)) static inline void efuse_ll_set_read_cmd(void) +{ + EFUSE.cmd.read_cmd = 1; +} + +__attribute__((always_inline)) static inline void efuse_ll_set_pgm_cmd(uint32_t block) +{ + assert(block < ETS_EFUSE_BLOCK_MAX); + EFUSE.cmd.val = ((block << EFUSE_BLK_NUM_S) & EFUSE_BLK_NUM_M) | EFUSE_PGM_CMD; +} + +__attribute__((always_inline)) static inline void efuse_ll_set_conf_read_op_code(void) +{ + EFUSE.conf.op_code = EFUSE_READ_OP_CODE; +} + +__attribute__((always_inline)) static inline void efuse_ll_set_conf_write_op_code(void) +{ + EFUSE.conf.op_code = EFUSE_WRITE_OP_CODE; +} + +__attribute__((always_inline)) static inline void efuse_ll_set_pwr_off_num(uint16_t value) +{ + EFUSE.wr_tim_conf2.pwr_off_num = value; +} + +/******************* eFuse control functions *************************/ + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/include/hal/efuse_hal.h b/components/hal/include/hal/efuse_hal.h new file mode 100644 index 00000000000..ca7fcd2003e --- /dev/null +++ b/components/hal/include/hal/efuse_hal.h @@ -0,0 +1,36 @@ +/* + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + + +/** + * @brief Returns chip version + * + * @return Chip version in format: Major * 100 + Minor + */ +uint32_t efuse_hal_chip_revision(void); + +/** + * @brief Returns major chip version + */ +uint32_t efuse_hal_get_major_chip_version(void); + +/** + * @brief Returns minor chip version + */ +uint32_t efuse_hal_get_minor_chip_version(void); + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32/include/soc/efuse_reg.h b/components/soc/esp32/include/soc/efuse_reg.h index 0c7d3d50325..38c255670b0 100644 --- a/components/soc/esp32/include/soc/efuse_reg.h +++ b/components/soc/esp32/include/soc/efuse_reg.h @@ -208,15 +208,12 @@ #define EFUSE_RD_FLASH_CRYPT_CONFIG_M ((EFUSE_RD_FLASH_CRYPT_CONFIG_V)<<(EFUSE_RD_FLASH_CRYPT_CONFIG_S)) #define EFUSE_RD_FLASH_CRYPT_CONFIG_V 0xF #define EFUSE_RD_FLASH_CRYPT_CONFIG_S 28 -/* EFUSE_RD_DIG_VOL_L6: RO; bitpos:[27:24]; */ -/*descritpion: This field stores the difference between the digital regulator voltage at level6 and 1.2 V. (RO) - BIT[27] is the sign bit, 0: + , 1: - - BIT[26:24] is the difference value, unit: 0.017V - volt_lv6 = BIT[27] ? 1.2 - BIT[26:24] * 0.017 : 1.2 + BIT[26:24] * 0.017 */ -#define EFUSE_RD_DIG_VOL_L6 0x0F -#define EFUSE_RD_DIG_VOL_L6_M ((EFUSE_RD_DIG_VOL_L6_V)<<(EFUSE_RD_DIG_VOL_L6_S)) -#define EFUSE_RD_DIG_VOL_L6_V 0x0F -#define EFUSE_RD_DIG_VOL_L6_S 24 +/* EFUSE_RD_WAFER_VERSION_MINOR: RO; bitpos:[25:24]; */ +/*descritpion: Wafer version minor*/ +#define EFUSE_RD_WAFER_VERSION_MINOR 0x00000003 +#define EFUSE_RD_WAFER_VERSION_MINOR_M ((EFUSE_RD_WAFER_VERSION_MINOR_V)<<(EFUSE_RD_WAFER_VERSION_MINOR_S)) +#define EFUSE_RD_WAFER_VERSION_MINOR_V 0x03 +#define EFUSE_RD_WAFER_VERSION_MINOR_S 24 /* EFUSE_RD_VOL_LEVEL_HP_INV: RO; bitpos:[23:22] */ /*description: This field stores the voltage level for CPU to run at 240 MHz, or for flash/PSRAM to run at 80 MHz. 0x0: level 7; 0x1: level 6; 0x2: level 5; 0x3: level 4. (RO)*/ @@ -224,12 +221,11 @@ #define EFUSE_RD_VOL_LEVEL_HP_INV_M ((EFUSE_RD_VOL_LEVEL_HP_INV_V)<<(EFUSE_RD_VOL_LEVEL_HP_INV_S)) #define EFUSE_RD_VOL_LEVEL_HP_INV_V 0x03 #define EFUSE_RD_VOL_LEVEL_HP_INV_S 22 -/* EFUSE_RD_INST_CONFIG : RO ;bitpos:[27:20] ;default: 8'b0 ; */ -/* Deprecated */ -#define EFUSE_RD_INST_CONFIG 0x000000FF /** Deprecated **/ -#define EFUSE_RD_INST_CONFIG_M ((EFUSE_RD_INST_CONFIG_V)<<(EFUSE_RD_INST_CONFIG_S)) /** Deprecated **/ -#define EFUSE_RD_INST_CONFIG_V 0xFF /** Deprecated **/ -#define EFUSE_RD_INST_CONFIG_S 20 /** Deprecated **/ +/* EFUSE_RD_CHIP_VER_REV2 : RO ;bitpos:[20] ;default: 8'b0 ; */ +#define EFUSE_RD_CHIP_VER_REV2 (BIT(20)) +#define EFUSE_RD_CHIP_VER_REV2_M ((EFUSE_RD_CHIP_VER_REV2_V)<<(EFUSE_RD_CHIP_VER_REV2_S)) +#define EFUSE_RD_CHIP_VER_REV2_V 0x1 +#define EFUSE_RD_CHIP_VER_REV2_S 20 /* EFUSE_RD_SPI_PAD_CONFIG_CS0 : RO ;bitpos:[19:15] ;default: 5'b0 ; */ /*description: read for SPI_pad_config_cs0*/ #define EFUSE_RD_SPI_PAD_CONFIG_CS0 0x0000001F @@ -1062,6 +1058,9 @@ #define EFUSE_CLK_SEL0_V 0xFF #define EFUSE_CLK_SEL0_S 0 +#define EFUSE_WRITE_OP_CODE 0x5a5a +#define EFUSE_READ_OP_CODE 0x5aa5 + #define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x0fc) /* EFUSE_FORCE_NO_WR_RD_DIS : R/W ;bitpos:[16] ;default: 1'h1 ; */ /*description: */ diff --git a/components/soc/esp32/include/soc/efuse_struct.h b/components/soc/esp32/include/soc/efuse_struct.h new file mode 100644 index 00000000000..d9b52d49416 --- /dev/null +++ b/components/soc/esp32/include/soc/efuse_struct.h @@ -0,0 +1,7 @@ +/* + * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once diff --git a/components/soc/esp32c3/include/soc/efuse_reg.h b/components/soc/esp32c3/include/soc/efuse_reg.h index 2522821041e..0b612fd64fb 100644 --- a/components/soc/esp32c3/include/soc/efuse_reg.h +++ b/components/soc/esp32c3/include/soc/efuse_reg.h @@ -1807,6 +1807,9 @@ extern "C" { #define EFUSE_MEM_FORCE_PD_V 0x1 #define EFUSE_MEM_FORCE_PD_S 0 +#define EFUSE_WRITE_OP_CODE 0x5a5a +#define EFUSE_READ_OP_CODE 0x5aa5 + #define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1CC) /* EFUSE_OP_CODE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ /*description: 0x5A5A: Operate programming command 0x5AA5: Operate read command.*/ diff --git a/components/soc/esp32c3/include/soc/efuse_struct.h b/components/soc/esp32c3/include/soc/efuse_struct.h index 9cb4b01e449..d0a804aca6c 100644 --- a/components/soc/esp32c3/include/soc/efuse_struct.h +++ b/components/soc/esp32c3/include/soc/efuse_struct.h @@ -172,7 +172,9 @@ typedef volatile struct efuse_dev_s { } rd_repeat_data3; union { struct { - uint32_t rpt4_reserved4:24; /*Reserved.*/ + uint32_t disable_wafer_version_major: 1; + uint32_t disable_blk_version_major: 1; + uint32_t rpt4_reserved4:22; /*Reserved.*/ uint32_t reserved24: 8; /*Reserved.*/ }; uint32_t val; @@ -189,17 +191,34 @@ typedef volatile struct efuse_dev_s { union { struct { uint32_t spi_pad_conf_2: 18; /*Stores the second part of SPI_PAD_CONF.*/ - uint32_t sys_data_part0_0:14; /*Stores the fist 14 bits of the zeroth part of system data.*/ + uint32_t wafer_version_minor_low: 3; + uint32_t pkg_version: 3; + uint32_t blk_version_minor:3; + uint32_t sys_data_part0_0: 5; }; uint32_t val; } rd_mac_spi_sys_3; uint32_t rd_mac_spi_sys_4; /*BLOCK1 data register $n.*/ - uint32_t rd_mac_spi_sys_5; /*BLOCK1 data register $n.*/ + union { + struct { + uint32_t reserved1: 23; + uint32_t wafer_version_minor_high: 1; + uint32_t wafer_version_major: 2; + uint32_t reserved2: 6; + }; + uint32_t val; + } rd_mac_spi_sys_5; /*BLOCK1 data register $n.*/ uint32_t rd_sys_part1_data0; /*Register $n of BLOCK2 (system).*/ uint32_t rd_sys_part1_data1; /*Register $n of BLOCK2 (system).*/ uint32_t rd_sys_part1_data2; /*Register $n of BLOCK2 (system).*/ uint32_t rd_sys_part1_data3; /*Register $n of BLOCK2 (system).*/ - uint32_t rd_sys_part1_data4; /*Register $n of BLOCK2 (system).*/ + union { + struct { + uint32_t blk_version_major : 2; + uint32_t reserved1: 30; + }; + uint32_t val; + } rd_sys_part1_data4; /*Register $n of BLOCK2 (system).*/ uint32_t rd_sys_part1_data5; /*Register $n of BLOCK2 (system).*/ uint32_t rd_sys_part1_data6; /*Register $n of BLOCK2 (system).*/ uint32_t rd_sys_part1_data7; /*Register $n of BLOCK2 (system).*/ diff --git a/components/soc/esp32s2/include/soc/efuse_reg.h b/components/soc/esp32s2/include/soc/efuse_reg.h index f7be21c6edd..1bf6e48b58e 100644 --- a/components/soc/esp32s2/include/soc/efuse_reg.h +++ b/components/soc/esp32s2/include/soc/efuse_reg.h @@ -2072,6 +2072,9 @@ extern "C" { #define EFUSE_MEM_FORCE_PD_V 0x1 #define EFUSE_MEM_FORCE_PD_S 0 +#define EFUSE_WRITE_OP_CODE 0x5a5a +#define EFUSE_READ_OP_CODE 0x5aa5 + #define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1cc) /* EFUSE_OP_CODE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ /*description: 0x5A5A: Operate programming command*/ diff --git a/components/soc/esp32s2/include/soc/efuse_struct.h b/components/soc/esp32s2/include/soc/efuse_struct.h index d2ef6454948..d6b21a5c46a 100644 --- a/components/soc/esp32s2/include/soc/efuse_struct.h +++ b/components/soc/esp32s2/include/soc/efuse_struct.h @@ -186,8 +186,10 @@ typedef volatile struct efuse_dev_s { } rd_repeat_data3; union { struct { - uint32_t chip_version:24; - uint32_t reserved24: 8; + uint32_t disable_wafer_version_major: 1; + uint32_t disable_blk_version_major: 1; + uint32_t rpt4_reserved4:22; + uint32_t reserved24: 8; }; uint32_t val; } rd_repeat_data4; @@ -206,14 +208,38 @@ typedef volatile struct efuse_dev_s { }; uint32_t val; } rd_mac_spi_8m_2; - uint32_t rd_mac_spi_8m_3; /**/ - uint32_t rd_mac_spi_8m_4; /**/ + union { + struct { + uint32_t spi_pad_conf_2: 18; + uint32_t wafer_version_major: 2; + uint32_t wafer_version_minor_high: 1; // most significant bit + uint32_t reserve1: 4; + uint32_t blk_version_major: 2; + uint32_t reserve2: 5; + }; + uint32_t val; + } rd_mac_spi_8m_3; + union { + struct { + uint32_t pkg_version: 4; + uint32_t wafer_version_minor_low: 3; // least significant bits + uint32_t reserve: 25; + }; + uint32_t val; + } rd_mac_spi_8m_4; uint32_t rd_mac_spi_8m_5; /**/ uint32_t rd_sys_data0; /**/ uint32_t rd_sys_data1; /**/ uint32_t rd_sys_data2; /**/ uint32_t rd_sys_data3; /**/ - uint32_t rd_sys_data4; /**/ + union { + struct { + uint32_t reserved1: 4; + uint32_t blk_version_minor : 3; + uint32_t reserved2: 25; + }; + uint32_t val; + } rd_sys_data4; /**/ uint32_t rd_sys_data5; /**/ uint32_t rd_sys_data6; /**/ uint32_t rd_sys_data7; /**/ diff --git a/components/soc/esp32s3/include/soc/efuse_reg.h b/components/soc/esp32s3/include/soc/efuse_reg.h index bd2112fa96e..988755de46f 100644 --- a/components/soc/esp32s3/include/soc/efuse_reg.h +++ b/components/soc/esp32s3/include/soc/efuse_reg.h @@ -2023,6 +2023,9 @@ extern "C" { #define EFUSE_MEM_FORCE_PD_V 0x1 #define EFUSE_MEM_FORCE_PD_S 0 +#define EFUSE_WRITE_OP_CODE 0x5a5a +#define EFUSE_READ_OP_CODE 0x5aa5 + #define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1CC) /* EFUSE_OP_CODE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ /*description: 0x5A5A: Operate programming command 0x5AA5: Operate read command.*/ diff --git a/components/soc/esp32s3/include/soc/efuse_struct.h b/components/soc/esp32s3/include/soc/efuse_struct.h index e4fd4a65fc3..16c683294c6 100644 --- a/components/soc/esp32s3/include/soc/efuse_struct.h +++ b/components/soc/esp32s3/include/soc/efuse_struct.h @@ -17,109 +17,312 @@ extern "C" { #endif -#include - -typedef volatile struct { - uint32_t reserved_0; - uint32_t reserved_4; - uint32_t reserved_8; - uint32_t reserved_c; - uint32_t reserved_10; - uint32_t reserved_14; - uint32_t reserved_18; - uint32_t reserved_1c; - uint32_t reserved_20; - uint32_t reserved_24; - uint32_t reserved_28; - uint32_t reserved_2c; - uint32_t reserved_30; - uint32_t reserved_34; - uint32_t reserved_38; - uint32_t reserved_3c; - uint32_t reserved_40; - uint32_t reserved_44; - uint32_t reserved_48; - uint32_t reserved_4c; - uint32_t reserved_50; - uint32_t reserved_54; - uint32_t reserved_58; - uint32_t reserved_5c; - uint32_t reserved_60; - uint32_t reserved_64; - uint32_t reserved_68; - uint32_t reserved_6c; - uint32_t reserved_70; - uint32_t reserved_74; - uint32_t reserved_78; - uint32_t reserved_7c; - uint32_t reserved_80; - uint32_t reserved_84; - uint32_t reserved_88; - uint32_t reserved_8c; - uint32_t reserved_90; - uint32_t reserved_94; - uint32_t reserved_98; - uint32_t reserved_9c; - uint32_t reserved_a0; - uint32_t reserved_a4; - uint32_t reserved_a8; - uint32_t reserved_ac; - uint32_t reserved_b0; - uint32_t reserved_b4; - uint32_t reserved_b8; - uint32_t reserved_bc; - uint32_t reserved_c0; - uint32_t reserved_c4; - uint32_t reserved_c8; - uint32_t reserved_cc; - uint32_t reserved_d0; - uint32_t reserved_d4; - uint32_t reserved_d8; - uint32_t reserved_dc; - uint32_t reserved_e0; - uint32_t reserved_e4; - uint32_t reserved_e8; - uint32_t reserved_ec; - uint32_t reserved_f0; - uint32_t reserved_f4; - uint32_t reserved_f8; - uint32_t reserved_fc; - uint32_t reserved_100; - uint32_t reserved_104; - uint32_t reserved_108; - uint32_t reserved_10c; - uint32_t reserved_110; - uint32_t reserved_114; - uint32_t reserved_118; - uint32_t reserved_11c; - uint32_t reserved_120; - uint32_t reserved_124; - uint32_t reserved_128; - uint32_t reserved_12c; - uint32_t reserved_130; - uint32_t reserved_134; - uint32_t reserved_138; - uint32_t reserved_13c; - uint32_t reserved_140; - uint32_t reserved_144; - uint32_t reserved_148; - uint32_t reserved_14c; - uint32_t reserved_150; - uint32_t reserved_154; - uint32_t reserved_158; - uint32_t reserved_15c; - uint32_t reserved_160; - uint32_t reserved_164; - uint32_t reserved_168; - uint32_t reserved_16c; - uint32_t reserved_170; - uint32_t reserved_174; - uint32_t reserved_178; - uint32_t reserved_17c; - uint32_t reserved_180; - uint32_t reserved_184; - uint32_t reserved_188; - uint32_t reserved_18c; +typedef volatile struct efuse_dev_s { + uint32_t pgm_data0; + uint32_t pgm_data1; + uint32_t pgm_data2; + uint32_t pgm_data3; + uint32_t pgm_data4; + uint32_t pgm_data5; + uint32_t pgm_data6; + uint32_t pgm_data7; + uint32_t pgm_check_value0; + uint32_t pgm_check_value1; + uint32_t pgm_check_value2; + uint32_t rd_wr_dis; + union { + struct { + uint32_t reg_rd_dis : 7; /*Set this bit to disable reading from BlOCK4-10.*/ + uint32_t reg_rpt4_reserved5 : 1; /*Reserved*/ + uint32_t reg_dis_icache : 1; /*Set this bit to disable Icache.*/ + uint32_t reg_dis_dcache : 1; /*Set this bit to disable Dcache.*/ + uint32_t reg_dis_download_icache : 1; /*Set this bit to disable Icache in download mode (boot_mode[3:0] is 0, 1, 2, 3, 6, 7).*/ + uint32_t reg_dis_download_dcache : 1; /*Set this bit to disable Dcache in download mode ( boot_mode[3:0] is 0, 1, 2, 3, 6, 7).*/ + uint32_t reg_dis_force_download : 1; /*Set this bit to disable the function that forces chip into download mode.*/ + uint32_t reg_dis_usb : 1; /*Set this bit to disable USB function.*/ + uint32_t reg_dis_can : 1; /*Set this bit to disable CAN function.*/ + uint32_t reg_dis_app_cpu : 1; /*Disable app cpu.*/ + uint32_t reg_soft_dis_jtag : 3; /*Set these bits to disable JTAG in the soft way (odd number 1 means disable ). JTAG can be enabled in HMAC module.*/ + uint32_t reg_dis_pad_jtag : 1; /*Set this bit to disable JTAG in the hard way. JTAG is disabled permanently.*/ + uint32_t reg_dis_download_manual_encrypt: 1; /*Set this bit to disable flash encryption when in download boot modes.*/ + uint32_t reg_usb_drefh : 2; /*Controls single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV, stored in eFuse.*/ + uint32_t reg_usb_drefl : 2; /*Controls single-end input threshold vrefl, 0.8 V to 1.04 V with step of 80 mV, stored in eFuse.*/ + uint32_t reg_usb_exchg_pins : 1; /*Set this bit to exchange USB D+ and D- pins.*/ + uint32_t reg_ext_phy_enable : 1; /*Set this bit to enable external PHY.*/ + uint32_t reg_btlc_gpio_enable : 2; /*Enable btlc gpio.*/ + uint32_t reg_vdd_spi_modecurlim : 1; /*SPI regulator switches current limit mode.*/ + uint32_t reg_vdd_spi_drefh : 2; /*SPI regulator high voltage reference.*/ + }; + uint32_t val; + } rd_repeat_data0; + union { + struct { + uint32_t reg_vdd_spi_drefm : 2; /*SPI regulator medium voltage reference.*/ + uint32_t reg_vdd_spi_drefl : 2; /*SPI regulator low voltage reference.*/ + uint32_t reg_vdd_spi_xpd : 1; /*SPI regulator power up signal.*/ + uint32_t reg_vdd_spi_tieh : 1; /*SPI regulator output is short connected to VDD3P3_RTC_IO.*/ + uint32_t reg_vdd_spi_force : 1; /*Set this bit and force to use the configuration of eFuse to configure VDD_SPI.*/ + uint32_t reg_vdd_spi_en_init : 1; /*Set SPI regulator to 0 to configure init[1:0]=0.*/ + uint32_t reg_vdd_spi_encurlim : 1; /*Set SPI regulator to 1 to enable output current limit.*/ + uint32_t reg_vdd_spi_dcurlim : 3; /*Tunes the current limit threshold of SPI regulator when tieh=0, about 800 mA/(8+d).*/ + uint32_t reg_vdd_spi_init : 2; /*Adds resistor from LDO output to ground. 0: no resistance 1: 6 K 2: 4 K 3: 2 K.*/ + uint32_t reg_vdd_spi_dcap : 2; /*Prevents SPI regulator from overshoot.*/ + uint32_t reg_wdt_delay_sel : 2; /*Selects RTC watchdog timeout threshold, in unit of slow clock cycle. 0: 40000. 1: 80000. 2: 160000. 3:320000.*/ + uint32_t reg_spi_boot_crypt_cnt : 3; /*Set this bit to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even number of 1: disable.*/ + uint32_t reg_secure_boot_key_revoke0 : 1; /*Set this bit to enable revoking first secure boot key.*/ + uint32_t reg_secure_boot_key_revoke1 : 1; /*Set this bit to enable revoking second secure boot key.*/ + uint32_t reg_secure_boot_key_revoke2 : 1; /*Set this bit to enable revoking third secure boot key.*/ + uint32_t reg_key_purpose_0 : 4; /*Purpose of Key0.*/ + uint32_t reg_key_purpose_1 : 4; /*Purpose of Key1.*/ + }; + uint32_t val; + } rd_repeat_data1; + union { + struct { + uint32_t reg_key_purpose_2 : 4; /*Purpose of Key2.*/ + uint32_t reg_key_purpose_3 : 4; /*Purpose of Key3.*/ + uint32_t reg_key_purpose_4 : 4; /*Purpose of Key4.*/ + uint32_t reg_key_purpose_5 : 4; /*Purpose of Key5.*/ + uint32_t reg_rpt4_reserved0 : 4; /*Reserved (used for four backups method).*/ + uint32_t reg_secure_boot_en : 1; /*Set this bit to enable secure boot.*/ + uint32_t reg_secure_boot_aggressive_revoke: 1; /*Set this bit to enable revoking aggressive secure boot.*/ + uint32_t reg_dis_usb_jtag : 1; /*Set this bit to disable function of usb switch to jtag in module of usb device.*/ + uint32_t reg_dis_usb_device : 1; /*Set this bit to disable usb device.*/ + uint32_t reg_strap_jtag_sel : 1; /*Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0.*/ + uint32_t reg_usb_phy_sel : 1; /*This bit is used to switch internal PHY and external PHY for USB OTG and USB Device. 0: internal PHY is assigned to USB Device while external PHY is assigned to USB OTG. 1: internal PHY is assigned to USB OTG while external PHY is assigned to USB Device.*/ + uint32_t reg_power_glitch_dsense : 2; /*Sample delay configuration of power glitch.*/ + uint32_t reg_flash_tpuw : 4; /*Configures flash waiting time after power-up, in unit of ms. If the value is less than 15, the waiting time is the configurable value; Otherwise, the waiting time is twice the configurable value.*/ + }; + uint32_t val; + } rd_repeat_data2; + union { + struct { + uint32_t reg_dis_download_mode : 1; /*Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 3, 6, 7).*/ + uint32_t reg_dis_direct_boot : 1; /*Set this bit to disable direct boot..*/ + uint32_t dis_usb_serial_jtag_rom_print : 1; /*Set this bit to disable USB-Serial-JTAG print during rom boot*/ + uint32_t reg_flash_ecc_mode : 1; /*Set ECC mode in ROM, 0: ROM would Enable Flash ECC 16to18 byte mode. 1:ROM would use 16to17 byte mode.*/ + uint32_t reg_dis_usb_serial_jtag_download_mode: 1; /*Set this bit to disable download through USB-Serial-JTAG.*/ + uint32_t reg_enable_security_download : 1; /*Set this bit to enable secure UART download mode.*/ + uint32_t reg_uart_print_control : 2; /*Set the default UARTboot message output mode. 00: Enabled. 01: Enabled when GPIO8 is low at reset. 10: Enabled when GPIO8 is high at reset. 11:disabled.*/ + uint32_t reg_pin_power_selection : 1; /*GPIO33-GPIO37 power supply selection in ROM code. 0: VDD3P3_CPU. 1: VDD_SPI.*/ + uint32_t reg_flash_type : 1; /*Set the maximum lines of SPI flash. 0: four lines. 1: eight lines.*/ + uint32_t reg_flash_page_size : 2; /*Set Flash page size.*/ + uint32_t reg_flash_ecc_en : 1; /*Set 1 to enable ECC for flash boot.*/ + uint32_t reg_force_send_resume : 1; /*Set this bit to force ROM code to send a resume command during SPI boot.*/ + uint32_t reg_secure_version : 16; /*Secure version (used by ESP-IDF anti-rollback feature).*/ + uint32_t reg_rpt4_reserved1 : 1; /*Reserved (used for four backups method).*/ + uint32_t reg_dis_usb_otg_download_mode : 1; /*Set this bit to disable download through USB-OTG*/ + }; + uint32_t val; + } rd_repeat_data3; + union { + struct { + uint32_t disable_wafer_version_major : 1; + uint32_t disable_blk_version_major : 1; + uint32_t reg_rpt4_reserved2 : 22; /*Reserved.*/ + uint32_t reserved24 : 8; /*Reserved.*/ + }; + uint32_t val; + } rd_repeat_data4; + uint32_t rd_mac_spi_sys_0; + union { + struct { + uint32_t reg_mac_1 : 16; /*Stores the high 16 bits of MAC address.*/ + uint32_t reg_spi_pad_conf_0 : 16; /*Stores the zeroth part of SPI_PAD_CONF.*/ + }; + uint32_t val; + } rd_mac_spi_sys_1; + uint32_t rd_mac_spi_sys_2; + union { + struct { + uint32_t spi_pad_conf_2: 18; /*Stores the second part of SPI_PAD_CONF.*/ + uint32_t wafer_version_minor_low: 3; + uint32_t pkg_version: 3; + uint32_t blk_version_minor:3; + uint32_t reg_sys_data_part0_0: 5; + }; + uint32_t val; + } rd_mac_spi_sys_3; + uint32_t rd_mac_spi_sys_4; + union { + struct { + uint32_t reserved1: 23; + uint32_t wafer_version_minor_high: 1; + uint32_t wafer_version_major: 2; + uint32_t reserved2: 6; + }; + uint32_t val; + } rd_mac_spi_sys_5; + uint32_t rd_sys_part1_data0; + uint32_t rd_sys_part1_data1; + uint32_t rd_sys_part1_data2; + uint32_t rd_sys_part1_data3; + union { + struct { + uint32_t blk_version_major : 2; + uint32_t reserved1: 30; + }; + uint32_t val; + } rd_sys_part1_data4; + uint32_t rd_sys_part1_data5; + uint32_t rd_sys_part1_data6; + uint32_t rd_sys_part1_data7; + uint32_t rd_usr_data0; + uint32_t rd_usr_data1; + uint32_t rd_usr_data2; + uint32_t rd_usr_data3; + uint32_t rd_usr_data4; + uint32_t rd_usr_data5; + uint32_t rd_usr_data6; + uint32_t rd_usr_data7; + uint32_t rd_key0_data0; + uint32_t rd_key0_data1; + uint32_t rd_key0_data2; + uint32_t rd_key0_data3; + uint32_t rd_key0_data4; + uint32_t rd_key0_data5; + uint32_t rd_key0_data6; + uint32_t rd_key0_data7; + uint32_t rd_key1_data0; + uint32_t rd_key1_data1; + uint32_t rd_key1_data2; + uint32_t rd_key1_data3; + uint32_t rd_key1_data4; + uint32_t rd_key1_data5; + uint32_t rd_key1_data6; + uint32_t rd_key1_data7; + uint32_t rd_key2_data0; + uint32_t rd_key2_data1; + uint32_t rd_key2_data2; + uint32_t rd_key2_data3; + uint32_t rd_key2_data4; + uint32_t rd_key2_data5; + uint32_t rd_key2_data6; + uint32_t rd_key2_data7; + uint32_t rd_key3_data0; + uint32_t rd_key3_data1; + uint32_t rd_key3_data2; + uint32_t rd_key3_data3; + uint32_t rd_key3_data4; + uint32_t rd_key3_data5; + uint32_t rd_key3_data6; + uint32_t rd_key3_data7; + uint32_t rd_key4_data0; + uint32_t rd_key4_data1; + uint32_t rd_key4_data2; + uint32_t rd_key4_data3; + uint32_t rd_key4_data4; + uint32_t rd_key4_data5; + uint32_t rd_key4_data6; + uint32_t rd_key4_data7; + uint32_t rd_key5_data0; + uint32_t rd_key5_data1; + uint32_t rd_key5_data2; + uint32_t rd_key5_data3; + uint32_t rd_key5_data4; + uint32_t rd_key5_data5; + uint32_t rd_key5_data6; + uint32_t rd_key5_data7; + uint32_t rd_sys_part2_data0; + uint32_t rd_sys_part2_data1; + uint32_t rd_sys_part2_data2; + uint32_t rd_sys_part2_data3; + uint32_t rd_sys_part2_data4; + uint32_t rd_sys_part2_data5; + uint32_t rd_sys_part2_data6; + uint32_t rd_sys_part2_data7; + union { + struct { + uint32_t reg_rd_dis_err : 7; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_rpt4_reserved5_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_dis_icache_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_dis_dcache_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_dis_download_icache_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_dis_download_dcache_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_dis_force_download_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_dis_usb_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_dis_can_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_dis_app_cpu_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_soft_dis_jtag_err : 3; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_dis_pad_jtag_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_dis_download_manual_encrypt_err: 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_usb_drefh_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_usb_drefl_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_usb_exchg_pins_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_ext_phy_enable_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_btlc_gpio_enable_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_vdd_spi_modecurlim_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_vdd_spi_drefh_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/ + }; + uint32_t val; + } rd_repeat_err0; + union { + struct { + uint32_t reg_vdd_spi_drefm_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_vdd_spi_drefl_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_vdd_spi_xpd_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_vdd_spi_tieh_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_vdd_spi_force_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_vdd_spi_en_init_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_vdd_spi_encurlim_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_vdd_spi_dcurlim_err : 3; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_vdd_spi_init_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_vdd_spi_dcap_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_wdt_delay_sel_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_spi_boot_crypt_cnt_err : 3; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_secure_boot_key_revoke0_err: 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_secure_boot_key_revoke1_err: 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_secure_boot_key_revoke2_err: 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_key_purpose_0_err : 4; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_key_purpose_1_err : 4; /*If any bits in this filed are 1, then it indicates a programming error.*/ + }; + uint32_t val; + } rd_repeat_err1; + union { + struct { + uint32_t reg_key_purpose_2_err : 4; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_key_purpose_3_err : 4; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_key_purpose_4_err : 4; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_key_purpose_5_err : 4; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_rpt4_reserved0_err : 4; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_secure_boot_en_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_secure_boot_aggressive_revoke_err: 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_dis_usb_jtag_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_dis_usb_device_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_strap_jtag_sel_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_usb_phy_sel_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_power_glitch_dsense_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_flash_tpuw_err : 4; /*If any bits in this filed are 1, then it indicates a programming error.*/ + }; + uint32_t val; + } rd_repeat_err2; + union { + struct { + uint32_t reg_dis_download_mode_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_dis_direct_boot_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_dis_usb_serial_jtag_rom_print_err:1;/*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_flash_ecc_mode_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_dis_usb_serial_jtag_download_mode_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_enable_security_download_err: 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_uart_print_control_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_pin_power_selection_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_flash_type_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_flash_page_size_err : 2; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_flash_ecc_en_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_force_send_resume_err : 1; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_secure_version_err : 16; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reg_rpt4_reserved1_err : 1; /*Reserved.*/ + uint32_t reg_dis_usb_otg_download_mode_err: 1; /*Set this bit to disable download through USB-OTG*/ + }; + uint32_t val; + } rd_repeat_err3; + union { + struct { + uint32_t reg_rpt4_reserved2_err : 24; /*If any bits in this filed are 1, then it indicates a programming error.*/ + uint32_t reserved24 : 8; /*Reserved.*/ + }; + uint32_t val; + } rd_repeat_err4; uint32_t reserved_190; uint32_t reserved_194; uint32_t reserved_198; diff --git a/components/soc/include/soc/efuse_periph.h b/components/soc/include/soc/efuse_periph.h index 76a118e3b68..a7fc65042c6 100644 --- a/components/soc/include/soc/efuse_periph.h +++ b/components/soc/include/soc/efuse_periph.h @@ -14,3 +14,4 @@ #pragma once #include "soc/efuse_reg.h" +#include "soc/efuse_struct.h" diff --git a/docs/en/api-reference/system/efuse.rst b/docs/en/api-reference/system/efuse.rst index fab51f203e7..8c16527a838 100644 --- a/docs/en/api-reference/system/efuse.rst +++ b/docs/en/api-reference/system/efuse.rst @@ -211,7 +211,7 @@ Access to the fields is via a pointer to the description structure. API function * :cpp:func:`esp_efuse_batch_write_commit` - writes all prepared data for batch writing mode and reset the batch writing mode. * :cpp:func:`esp_efuse_batch_write_cancel` - reset the batch writing mode and prepared data. -For frequently used fields, special functions are made, like this :cpp:func:`esp_efuse_get_chip_ver`, :cpp:func:`esp_efuse_get_pkg_ver`. +For frequently used fields, special functions are made, like this :cpp:func:`esp_efuse_get_pkg_ver`. .. only:: not esp32 diff --git a/examples/build_system/cmake/idf_as_lib/stubs/esp32/esp_system.h b/examples/build_system/cmake/idf_as_lib/stubs/esp32/esp_system.h index 3cd073adf16..81bcfcffb8e 100644 --- a/examples/build_system/cmake/idf_as_lib/stubs/esp32/esp_system.h +++ b/examples/build_system/cmake/idf_as_lib/stubs/esp32/esp_system.h @@ -7,8 +7,8 @@ typedef struct { uint32_t features; //!< bit mask of CHIP_FEATURE_x feature flags + uint16_t revision; //!< chip revision number (in format MXX; where M - wafer major version, XX - wafer minor version) uint8_t cores; //!< number of CPU cores - uint8_t revision; //!< chip revision number } esp_chip_info_t; void esp_restart(void); From 611339564d0f8cce79c9744a871e7adc82437701 Mon Sep 17 00:00:00 2001 From: "Michael (XIAO Xufeng)" Date: Sun, 6 Nov 2022 02:37:10 +0800 Subject: [PATCH 2/3] esp32s3: fixed bug chip v0.0 detected as vX.0 A typical value is 2.0. --- components/hal/esp32s3/efuse_hal.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/components/hal/esp32s3/efuse_hal.c b/components/hal/esp32s3/efuse_hal.c index 2529be75693..e9f3e3d0d92 100644 --- a/components/hal/esp32s3/efuse_hal.c +++ b/components/hal/esp32s3/efuse_hal.c @@ -12,7 +12,15 @@ uint32_t efuse_hal_get_major_chip_version(void) { - return efuse_ll_get_chip_wafer_version_major(); + uint32_t ret = efuse_ll_get_chip_wafer_version_major(); + //Workaround: The major version field was allocated to other purposes when block version is v1.1. + //Luckily only chip v0.0 have this kind of block version and efuse usage. + if (efuse_ll_get_chip_wafer_version_minor() == 0 && + efuse_ll_get_blk_version_major() == 1 && + efuse_ll_get_blk_version_minor() == 1) { + ret = 0; + } + return ret; } uint32_t efuse_hal_get_minor_chip_version(void) From 3e269ffc0dd53c98c85fb97e0649960622e03050 Mon Sep 17 00:00:00 2001 From: "Michael (XIAO Xufeng)" Date: Thu, 1 Dec 2022 01:05:09 +0800 Subject: [PATCH 3/3] esp32s3: fixed bug chip v0.0 detected as vX.Y A typical value is 2.8. Previous commit 32ef2b321aac317bdf6d088ec87c809ab8471042 doesn't fix the issue cleanly. The MSB of wafer_minor also has this problem. --- components/hal/esp32s3/efuse_hal.c | 32 +++++++++++++++++++++--------- 1 file changed, 23 insertions(+), 9 deletions(-) diff --git a/components/hal/esp32s3/efuse_hal.c b/components/hal/esp32s3/efuse_hal.c index e9f3e3d0d92..14564a92de5 100644 --- a/components/hal/esp32s3/efuse_hal.c +++ b/components/hal/esp32s3/efuse_hal.c @@ -10,20 +10,34 @@ #include "hal/efuse_hal.h" #include "hal/efuse_ll.h" +#define ESP_EFUSE_BLOCK_ERROR_BITS(error_reg, block) ((error_reg) & (0x0F << (4 * (block)))) + + +//The wafer_major and MSB of wafer_minor fields was allocated to other purposes when block version is v1.1. +//Luckily only chip v0.0 have this kind of block version and efuse usage. +//This workaround fixes the issue. +static inline bool is_eco0(uint32_t minor_raw) +{ + return ((minor_raw & 0x7) == 0 && + efuse_ll_get_blk_version_major() == 1 && efuse_ll_get_blk_version_minor() == 1); +} + uint32_t efuse_hal_get_major_chip_version(void) { - uint32_t ret = efuse_ll_get_chip_wafer_version_major(); - //Workaround: The major version field was allocated to other purposes when block version is v1.1. - //Luckily only chip v0.0 have this kind of block version and efuse usage. - if (efuse_ll_get_chip_wafer_version_minor() == 0 && - efuse_ll_get_blk_version_major() == 1 && - efuse_ll_get_blk_version_minor() == 1) { - ret = 0; + uint32_t minor_raw = efuse_ll_get_chip_wafer_version_minor(); + + if (is_eco0(minor_raw)) { + return 0; } - return ret; + return efuse_ll_get_chip_wafer_version_major(); } uint32_t efuse_hal_get_minor_chip_version(void) { - return efuse_ll_get_chip_wafer_version_minor(); + uint32_t minor_raw = efuse_ll_get_chip_wafer_version_minor(); + + if (is_eco0(minor_raw)) { + return 0; + } + return minor_raw; }