From 1059ec7faff24ea1647c80963ef65abc515ef0fd Mon Sep 17 00:00:00 2001 From: "C.S.M" Date: Fri, 7 Jun 2024 15:15:42 +0800 Subject: [PATCH] fix(esp32-c5): Use a longer reset delay with usb-serial/jtag to stabilize boot-up --- esptool/reset.py | 6 +++--- esptool/targets/esp32c5.py | 7 +++++++ 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/esptool/reset.py b/esptool/reset.py index edf3b13b0..ef91e4bdc 100644 --- a/esptool/reset.py +++ b/esptool/reset.py @@ -148,13 +148,13 @@ class HardReset(ResetStrategy): Can be used to reset out of the bootloader or to restart a running app. """ - def __init__(self, port, uses_usb_otg=False): + def __init__(self, port, uses_usb=False): super().__init__(port) - self.uses_usb_otg = uses_usb_otg + self.uses_usb = uses_usb def reset(self): self._setRTS(True) # EN->LOW - if self.uses_usb_otg: + if self.uses_usb: # Give the chip some time to come out of reset, # to be able to handle further DTR/RTS transitions time.sleep(0.2) diff --git a/esptool/targets/esp32c5.py b/esptool/targets/esp32c5.py index fc2db6c0d..51d52effd 100644 --- a/esptool/targets/esp32c5.py +++ b/esptool/targets/esp32c5.py @@ -7,6 +7,7 @@ from .esp32c6 import ESP32C6ROM from ..loader import ESPLoader +from ..reset import HardReset class ESP32C5ROM(ESP32C6ROM): @@ -24,6 +25,8 @@ class ESP32C5ROM(ESP32C6ROM): PCR_SYSCLK_XTAL_FREQ_V = 0x7F << 24 PCR_SYSCLK_XTAL_FREQ_S = 24 + UARTDEV_BUF_NO = 0x4085F51C # Variable in ROM .bss which indicates the port in use + # Magic value for ESP32C5 CHIP_DETECT_MAGIC_VALUE = [0x8082C5DC] @@ -67,6 +70,10 @@ def get_crystal_freq_rom_expect(self): self.read_reg(self.PCR_SYSCLK_CONF_REG) & self.PCR_SYSCLK_XTAL_FREQ_V ) >> self.PCR_SYSCLK_XTAL_FREQ_S + def hard_reset(self): + print("Hard resetting via RTS pin...") + HardReset(self._port, self.uses_usb_jtag_serial())() + def change_baud(self, baud): if not self.IS_STUB: crystal_freq_rom_expect = self.get_crystal_freq_rom_expect()