C:\Espressif\frameworks\esp-idf-v4.4.1>openocd -d3 -s ${openocd_path}/share/openocd/scripts -f board/esp32c3-builtin.cfg -c "set ESP_FLASH_SIZE 0"
Open On-Chip Debugger  v0.11.0-esp32-20220706 (2022-07-06-15:48)
Licensed under GNU GPL v2
For bug reports, read
        http://openocd.org/doc/doxygen/bugs.html
User : 3 3 options.c:63 configuration_output_handler(): debug_level: 3
User : 4 7 options.c:63 configuration_output_handler():
Debug: 5 9 configuration.c:44 add_script_search_dir(): adding ${openocd_path}/share/openocd/scripts
Debug: 6 13 options.c:244 add_default_dirs(): bindir=/builds/idf/openocd-esp32/_build/../openocd-esp32/bin
Debug: 7 17 options.c:245 add_default_dirs(): pkgdatadir=/builds/idf/openocd-esp32/_build/../openocd-esp32/share/openocd
Debug: 8 21 options.c:246 add_default_dirs(): exepath=C:/Espressif/tools/openocd-esp32/v0.11.0-esp32-20220706/openocd-esp32/bin
Debug: 9 27 options.c:247 add_default_dirs(): bin2data=../share/openocd
Debug: 10 29 configuration.c:44 add_script_search_dir(): adding C:\Espressif\tools\openocd-esp32\v0.11.0-esp32-20220706\openocd-esp32\share\openocd\scripts
Debug: 11 35 configuration.c:44 add_script_search_dir(): adding C:/Users/gdvecchia/AppData/Roaming/OpenOCD
Debug: 12 39 configuration.c:44 add_script_search_dir(): adding C:/Espressif/tools/openocd-esp32/v0.11.0-esp32-20220706/openocd-esp32/bin/../share/openocd/site
Debug: 13 45 configuration.c:44 add_script_search_dir(): adding C:/Espressif/tools/openocd-esp32/v0.11.0-esp32-20220706/openocd-esp32/bin/../share/openocd/scripts
Debug: 14 51 command.c:166 script_debug(): command - ocd_find board/esp32c3-builtin.cfg
Debug: 15 55 configuration.c:99 find_file(): found C:\Espressif\tools\openocd-esp32\v0.11.0-esp32-20220706\openocd-esp32\share\openocd\scripts/board/esp32c3-builtin.cfg
Debug: 16 64 command.c:166 script_debug(): command - ocd_find interface/esp_usb_jtag.cfg
Debug: 17 68 configuration.c:99 find_file(): found C:\Espressif\tools\openocd-esp32\v0.11.0-esp32-20220706\openocd-esp32\share\openocd\scripts/interface/esp_usb_jtag.cfg
Debug: 18 75 command.c:166 script_debug(): command - adapter driver esp_usb_jtag
Info : 19 78 transport.c:118 allow_transports(): only one transport option; autoselect 'jtag'
Debug: 20 82 command.c:166 script_debug(): command - espusbjtag vid_pid 0x303a 0x1001
Info : 21 85 esp_usb_jtag.c:899 esp_usb_jtag_vid_pid(): esp_usb_jtag: VID set to 0x303a and PID to 0x1001
Debug: 22 91 command.c:166 script_debug(): command - espusbjtag caps_descriptor 0x2000
Info : 23 94 esp_usb_jtag.c:910 esp_usb_jtag_caps_descriptor(): esp_usb_jtag: capabilities descriptor set to 0x2000
Debug: 24 98 command.c:166 script_debug(): command - adapter speed 40000
Debug: 25 101 adapter.c:180 adapter_config_khz(): handle adapter khz
Debug: 26 105 adapter.c:144 adapter_khz_to_speed(): convert khz to adapter specific speed value
Debug: 27 108 adapter.c:144 adapter_khz_to_speed(): convert khz to adapter specific speed value
Debug: 28 112 command.c:166 script_debug(): command - ocd_find target/esp32c3.cfg
Debug: 29 116 configuration.c:99 find_file(): found C:\Espressif\tools\openocd-esp32\v0.11.0-esp32-20220706\openocd-esp32\share\openocd\scripts/target/esp32c3.cfg
Debug: 30 123 command.c:166 script_debug(): command - transport select jtag
Warn : 31 126 transport.c:287 jim_transport_select(): Transport "jtag" was already selected
Debug: 32 129 command.c:166 script_debug(): command - ocd_find bitsbytes.tcl
Debug: 33 133 configuration.c:99 find_file(): found C:\Espressif\tools\openocd-esp32\v0.11.0-esp32-20220706\openocd-esp32\share\openocd\scripts/bitsbytes.tcl
Debug: 34 140 command.c:166 script_debug(): command - expr 1 << $x
Debug: 35 143 command.c:166 script_debug(): command - expr $x + 1
Debug: 36 146 command.c:166 script_debug(): command - expr 1 << $x
Debug: 37 149 command.c:166 script_debug(): command - expr $x + 1
Debug: 38 151 command.c:166 script_debug(): command - expr 1 << $x
Debug: 39 155 command.c:166 script_debug(): command - expr $x + 1
Debug: 40 157 command.c:166 script_debug(): command - expr 1 << $x
Debug: 41 160 command.c:166 script_debug(): command - expr $x + 1
Debug: 42 163 command.c:166 script_debug(): command - expr 1 << $x
Debug: 43 165 command.c:166 script_debug(): command - expr $x + 1
Debug: 44 168 command.c:166 script_debug(): command - expr 1 << $x
Debug: 45 171 command.c:166 script_debug(): command - expr $x + 1
Debug: 46 174 command.c:166 script_debug(): command - expr 1 << $x
Debug: 47 176 command.c:166 script_debug(): command - expr $x + 1
Debug: 48 179 command.c:166 script_debug(): command - expr 1 << $x
Debug: 49 182 command.c:166 script_debug(): command - expr $x + 1
Debug: 50 185 command.c:166 script_debug(): command - expr 1 << $x
Debug: 51 188 command.c:166 script_debug(): command - expr $x + 1
Debug: 52 190 command.c:166 script_debug(): command - expr 1 << $x
Debug: 53 193 command.c:166 script_debug(): command - expr $x + 1
Debug: 54 195 command.c:166 script_debug(): command - expr 1 << $x
Debug: 55 198 command.c:166 script_debug(): command - expr $x + 1
Debug: 56 201 command.c:166 script_debug(): command - expr 1 << $x
Debug: 57 204 command.c:166 script_debug(): command - expr $x + 1
Debug: 58 207 command.c:166 script_debug(): command - expr 1 << $x
Debug: 59 209 command.c:166 script_debug(): command - expr $x + 1
Debug: 60 212 command.c:166 script_debug(): command - expr 1 << $x
Debug: 61 215 command.c:166 script_debug(): command - expr $x + 1
Debug: 62 218 command.c:166 script_debug(): command - expr 1 << $x
Debug: 63 220 command.c:166 script_debug(): command - expr $x + 1
Debug: 64 223 command.c:166 script_debug(): command - expr 1 << $x
Debug: 65 226 command.c:166 script_debug(): command - expr $x + 1
Debug: 66 228 command.c:166 script_debug(): command - expr 1 << $x
Debug: 67 231 command.c:166 script_debug(): command - expr $x + 1
Debug: 68 234 command.c:166 script_debug(): command - expr 1 << $x
Debug: 69 237 command.c:166 script_debug(): command - expr $x + 1
Debug: 70 240 command.c:166 script_debug(): command - expr 1 << $x
Debug: 71 242 command.c:166 script_debug(): command - expr $x + 1
Debug: 72 245 command.c:166 script_debug(): command - expr 1 << $x
Debug: 73 247 command.c:166 script_debug(): command - expr $x + 1
Debug: 74 251 command.c:166 script_debug(): command - expr 1 << $x
Debug: 75 253 command.c:166 script_debug(): command - expr $x + 1
Debug: 76 256 command.c:166 script_debug(): command - expr 1 << $x
Debug: 77 259 command.c:166 script_debug(): command - expr $x + 1
Debug: 78 261 command.c:166 script_debug(): command - expr 1 << $x
Debug: 79 264 command.c:166 script_debug(): command - expr $x + 1
Debug: 80 267 command.c:166 script_debug(): command - expr 1 << $x
Debug: 81 270 command.c:166 script_debug(): command - expr $x + 1
Debug: 82 271 command.c:166 script_debug(): command - expr 1 << $x
Debug: 83 274 command.c:166 script_debug(): command - expr $x + 1
Debug: 84 277 command.c:166 script_debug(): command - expr 1 << $x
Debug: 85 280 command.c:166 script_debug(): command - expr $x + 1
Debug: 86 283 command.c:166 script_debug(): command - expr 1 << $x
Debug: 87 285 command.c:166 script_debug(): command - expr $x + 1
Debug: 88 288 command.c:166 script_debug(): command - expr 1 << $x
Debug: 89 291 command.c:166 script_debug(): command - expr $x + 1
Debug: 90 293 command.c:166 script_debug(): command - expr 1 << $x
Debug: 91 297 command.c:166 script_debug(): command - expr $x + 1
Debug: 92 299 command.c:166 script_debug(): command - expr 1 << $x
Debug: 93 302 command.c:166 script_debug(): command - expr $x + 1
Debug: 94 305 command.c:166 script_debug(): command - expr 1 << $x
Debug: 95 307 command.c:166 script_debug(): command - expr $x + 1
Debug: 96 310 command.c:166 script_debug(): command - expr 1 << $x
Debug: 97 313 command.c:166 script_debug(): command - expr $x + 1
Debug: 98 316 command.c:166 script_debug(): command - expr 1024 * $x
Debug: 99 318 command.c:166 script_debug(): command - expr $x * 2
Debug: 100 321 command.c:166 script_debug(): command - expr 1024 * $x
Debug: 101 325 command.c:166 script_debug(): command - expr $x * 2
Debug: 102 327 command.c:166 script_debug(): command - expr 1024 * $x
Debug: 103 330 command.c:166 script_debug(): command - expr $x * 2
Debug: 104 333 command.c:166 script_debug(): command - expr 1024 * $x
Debug: 105 336 command.c:166 script_debug(): command - expr $x * 2
Debug: 106 338 command.c:166 script_debug(): command - expr 1024 * $x
Debug: 107 342 command.c:166 script_debug(): command - expr $x * 2
Debug: 108 344 command.c:166 script_debug(): command - expr 1024 * $x
Debug: 109 347 command.c:166 script_debug(): command - expr $x * 2
Debug: 110 350 command.c:166 script_debug(): command - expr 1024 * $x
Debug: 111 352 command.c:166 script_debug(): command - expr $x * 2
Debug: 112 356 command.c:166 script_debug(): command - expr 1024 * $x
Debug: 113 359 command.c:166 script_debug(): command - expr $x * 2
Debug: 114 362 command.c:166 script_debug(): command - expr 1024 * $x
Debug: 115 364 command.c:166 script_debug(): command - expr $x * 2
Debug: 116 367 command.c:166 script_debug(): command - expr 1024 * $x
Debug: 117 370 command.c:166 script_debug(): command - expr $x * 2
Debug: 118 373 command.c:166 script_debug(): command - expr 1024 * $x
Debug: 119 376 command.c:166 script_debug(): command - expr $x * 2
Debug: 120 378 command.c:166 script_debug(): command - expr 1024 * 1024 * $x
Debug: 121 381 command.c:166 script_debug(): command - expr $x * 2
Debug: 122 384 command.c:166 script_debug(): command - expr 1024 * 1024 * $x
Debug: 123 388 command.c:166 script_debug(): command - expr $x * 2
Debug: 124 390 command.c:166 script_debug(): command - expr 1024 * 1024 * $x
Debug: 125 393 command.c:166 script_debug(): command - expr $x * 2
Debug: 126 396 command.c:166 script_debug(): command - expr 1024 * 1024 * $x
Debug: 127 399 command.c:166 script_debug(): command - expr $x * 2
Debug: 128 402 command.c:166 script_debug(): command - expr 1024 * 1024 * $x
Debug: 129 406 command.c:166 script_debug(): command - expr $x * 2
Debug: 130 408 command.c:166 script_debug(): command - expr 1024 * 1024 * $x
Debug: 131 411 command.c:166 script_debug(): command - expr $x * 2
Debug: 132 414 command.c:166 script_debug(): command - expr 1024 * 1024 * $x
Debug: 133 417 command.c:166 script_debug(): command - expr $x * 2
Debug: 134 420 command.c:166 script_debug(): command - expr 1024 * 1024 * $x
Debug: 135 423 command.c:166 script_debug(): command - expr $x * 2
Debug: 136 426 command.c:166 script_debug(): command - expr 1024 * 1024 * $x
Debug: 137 429 command.c:166 script_debug(): command - expr $x * 2
Debug: 138 431 command.c:166 script_debug(): command - expr 1024 * 1024 * $x
Debug: 139 434 command.c:166 script_debug(): command - expr $x * 2
Debug: 140 438 command.c:166 script_debug(): command - expr 1024 * 1024 * $x
Debug: 141 441 command.c:166 script_debug(): command - expr $x * 2
Debug: 142 443 command.c:166 script_debug(): command - ocd_find memory.tcl
Debug: 143 447 configuration.c:99 find_file(): found C:\Espressif\tools\openocd-esp32\v0.11.0-esp32-20220706\openocd-esp32\share\openocd\scripts/memory.tcl
Debug: 144 453 command.c:166 script_debug(): command - expr $RWX_R_ONLY + $RWX_W_ONLY
Debug: 145 457 command.c:166 script_debug(): command - expr $RWX_R_ONLY + $RWX_X_ONLY
Debug: 146 460 command.c:166 script_debug(): command - expr $RWX_R_ONLY + $RWX_W_ONLY + $RWX_X_ONLY
Debug: 147 464 command.c:166 script_debug(): command - expr $ACCESS_WIDTH_8 + $ACCESS_WIDTH_16 + $ACCESS_WIDTH_32
Debug: 148 469 command.c:166 script_debug(): command - ocd_find mmr_helpers.tcl
Debug: 149 472 configuration.c:99 find_file(): found C:\Espressif\tools\openocd-esp32\v0.11.0-esp32-20220706\openocd-esp32\share\openocd\scripts/mmr_helpers.tcl
Debug: 150 478 command.c:166 script_debug(): command - ocd_find target/esp_common.cfg
Debug: 151 482 configuration.c:99 find_file(): found C:\Espressif\tools\openocd-esp32\v0.11.0-esp32-20220706\openocd-esp32\share\openocd\scripts/target/esp_common.cfg
Debug: 152 489 command.c:166 script_debug(): command - add_help_text program_esp write an image to flash, address is only required for binary images. verify, reset, exit, compress, restore_clock are optional
Debug: 153 497 command.c:166 script_debug(): command - add_usage_text program_esp <filename> [address] [verify] [reset] [exit] [compress] [no_clock_boost] [restore_clock]
Debug: 154 504 command.c:166 script_debug(): command - add_help_text program_esp_bins write all the images at address specified in flasher_args.json generated while building idf project
Debug: 155 511 command.c:166 script_debug(): command - add_usage_text program_esp_bins <build_dir> flasher_args.json [verify] [reset] [exit] [compress] [no_clock_boost] [restore_clock]
Debug: 156 518 command.c:166 script_debug(): command - add_help_text esp_get_mac Print MAC address of the chip. Use a `format` argument to return formatted MAC value
Debug: 157 525 command.c:166 script_debug(): command - add_usage_text esp_get_mac [format]
Debug: 158 529 command.c:166 script_debug(): command - jtag newtap esp32c3 cpu -irlen 5 -expected-id 0x00005c25
Debug: 159 534 tcl.c:569 jim_newtap_cmd(): Creating New Tap, Chip: esp32c3, Tap: cpu, Dotted: esp32c3.cpu, 4 params
Debug: 160 538 tcl.c:593 jim_newtap_cmd(): Processing option: -irlen
Debug: 161 541 tcl.c:593 jim_newtap_cmd(): Processing option: -expected-id
Debug: 162 544 core.c:1472 jtag_tap_init(): Created Tap: esp32c3.cpu @ abs position 0, irlen 5, capture: 0x1 mask: 0x3
Debug: 163 548 command.c:166 script_debug(): command - target create esp32c3 esp32c3 -chain-position esp32c3.cpu -rtos FreeRTOS
Debug: 164 554 target.c:2239 target_free_all_working_areas_restore(): freeing all working areas
Debug: 165 558 target.c:2239 target_free_all_working_areas_restore(): freeing all working areas
Debug: 166 561 FreeRTOS.c:1387 freertos_create(): freertos_create
Debug: 167 564 command.c:300 register_command(): command 'esp' is already registered
Debug: 168 568 command.c:300 register_command(): command 'esp32c3 esp' is already registered
Debug: 169 572 command.c:166 script_debug(): command - esp32c3 configure -event reset-assert-post  esp32c3_soc_reset
Debug: 170 576 command.c:166 script_debug(): command - esp32c3 configure -event halted
    esp32c3_wdt_disable

Debug: 171 581 command.c:166 script_debug(): command - esp32c3 configure -event examine-end
    # Need this to handle 'apptrace init' syscall correctly because semihosting is not enabled by default
    arm semihosting enable
    arm semihosting_resexit enable
    if { [info exists _SEMIHOST_BASEDIR] } {
        if { $_SEMIHOST_BASEDIR != "" } {
            arm semihosting_basedir $_SEMIHOST_BASEDIR
        }
    }

Debug: 172 599 command.c:166 script_debug(): command - esp32c3 configure -event gdb-attach
    # 'halt' is necessary to auto-probe flash bank when GDB is connected and generate proper memory map
    halt 1000
    if { [esp32c3_memprot_is_enabled] } {
        # 'reset halt' to disable memory protection and allow flasher to work correctly
        echo "Memory protection is enabled. Reset target to disable it..."
        reset halt
    }
    # by default mask interrupts while stepping
    riscv set_maskisr steponly

Debug: 173 622 command.c:166 script_debug(): command - esp32c3 configure -work-area-phys 0x40380000 -work-area-virt 0x40380000 -work-area-size 0x4000 -work-area-backup 1
Debug: 174 629 target.c:2239 target_free_all_working_areas_restore(): freeing all working areas
Debug: 175 633 target.c:2239 target_free_all_working_areas_restore(): freeing all working areas
Debug: 176 636 target.c:2239 target_free_all_working_areas_restore(): freeing all working areas
Debug: 177 640 target.c:2239 target_free_all_working_areas_restore(): freeing all working areas
Debug: 178 644 command.c:166 script_debug(): command - esp32c3 configure -alt-work-area-phys 0x3FC84000 -alt-work-area-virt 0x3FC84000 -alt-work-area-size 0x20000 -alt-work-area-backup 1
Debug: 179 651 target.c:2239 target_free_all_working_areas_restore(): freeing all working areas
Debug: 180 655 target.c:2239 target_free_all_working_areas_restore(): freeing all working areas
Debug: 181 660 target.c:2239 target_free_all_working_areas_restore(): freeing all working areas
Debug: 182 663 target.c:2239 target_free_all_working_areas_restore(): freeing all working areas
Debug: 183 667 command.c:166 script_debug(): command - flash bank esp32c3.flash esp32c3 0x0 0 0 0 esp32c3
Debug: 184 671 command.c:300 register_command(): command 'esp' is already registered
Debug: 185 675 tcl.c:1316 handle_flash_bank_command(): 'esp32c3' driver usage field missing
Debug: 186 679 command.c:166 script_debug(): command - flash bank esp32c3.irom esp32c3 0x0 0 0 0 esp32c3
Debug: 187 683 command.c:300 register_command(): command 'esp' is already registered
Debug: 188 685 command.c:300 register_command(): command 'esp appimage_offset' is already registered
Debug: 189 689 command.c:300 register_command(): command 'esp compression' is already registered
Debug: 190 693 command.c:300 register_command(): command 'esp verify_bank_hash' is already registered
Debug: 191 697 command.c:300 register_command(): command 'esp flash_stub_clock_boost' is already registered
Debug: 192 701 tcl.c:1316 handle_flash_bank_command(): 'esp32c3' driver usage field missing
Debug: 193 705 command.c:166 script_debug(): command - flash bank esp32c3.drom esp32c3 0x0 0 0 0 esp32c3
Debug: 194 709 command.c:300 register_command(): command 'esp' is already registered
Debug: 195 713 command.c:300 register_command(): command 'esp appimage_offset' is already registered
Debug: 196 716 command.c:300 register_command(): command 'esp compression' is already registered
Debug: 197 721 command.c:300 register_command(): command 'esp verify_bank_hash' is already registered
Debug: 198 725 command.c:300 register_command(): command 'esp flash_stub_clock_boost' is already registered
Debug: 199 729 tcl.c:1316 handle_flash_bank_command(): 'esp32c3' driver usage field missing
Debug: 200 732 command.c:166 script_debug(): command - riscv set_reset_timeout_sec 2
Debug: 201 735 command.c:166 script_debug(): command - riscv set_command_timeout_sec 5
Debug: 202 739 command.c:166 script_debug(): command - riscv set_mem_access sysbus progbuf abstract
Debug: 203 743 command.c:166 script_debug(): command - riscv set_ebreakm on
Debug: 204 746 command.c:166 script_debug(): command - riscv set_ebreaks on
Debug: 205 749 command.c:166 script_debug(): command - riscv set_ebreaku on
User : 206 753 options.c:63 configuration_output_handler(): 0User : 207 755 options.c:63 configuration_output_handler():
Info : 208 759 server.c:303 add_service(): Listening on port 6666 for tcl connections
Info : 209 762 server.c:303 add_service(): Listening on port 4444 for telnet connections
Debug: 210 766 command.c:166 script_debug(): command - init
Debug: 211 769 command.c:166 script_debug(): command - target init
Debug: 212 774 command.c:166 script_debug(): command - target names
Debug: 213 777 command.c:166 script_debug(): command - esp32c3 cget -event gdb-flash-erase-start
Debug: 214 780 command.c:166 script_debug(): command - esp32c3 configure -event gdb-flash-erase-start reset init
Debug: 215 785 command.c:166 script_debug(): command - esp32c3 cget -event gdb-flash-write-end
Debug: 216 789 command.c:166 script_debug(): command - esp32c3 configure -event gdb-flash-write-end reset halt
Debug: 217 793 command.c:166 script_debug(): command - esp32c3 cget -event gdb-attach
Debug: 218 797 target.c:1672 handle_target_init_command(): Initializing targets...
Debug: 219 800 riscv.c:441 riscv_init_target(): riscv_init_target()
Debug: 220 803 semihosting_common.c:118 semihosting_common_init():
Info : 221 830 esp_usb_jtag.c:666 esp_usb_jtag_init(): esp_usb_jtag: serial (34:B4:72:43:CD:08)
Debug: 222 834 libusb_helper.c:337 jtag_libusb_choose_interface(): usb ep out 02
Debug: 223 837 libusb_helper.c:337 jtag_libusb_choose_interface(): usb ep in 83
Debug: 224 840 libusb_helper.c:345 jtag_libusb_choose_interface(): Claiming interface 2
Info : 225 844 esp_usb_jtag.c:741 esp_usb_jtag_init(): esp_usb_jtag: Device found. Base speed 40000KHz, div range 1 to 255
Debug: 226 850 adapter.c:144 adapter_khz_to_speed(): convert khz to adapter specific speed value
Debug: 227 853 adapter.c:148 adapter_khz_to_speed(): have adapter set up
Debug: 228 856 esp_usb_jtag.c:800 esp_usb_jtag_khz(): Divisor for 40000 KHz with base clock of 40000 khz is 1
Debug: 229 861 esp_usb_jtag.c:816 esp_usb_jtag_speed(): esp_usb_jtag: setting divisor 1
Debug: 230 865 adapter.c:144 adapter_khz_to_speed(): convert khz to adapter specific speed value
Debug: 231 869 adapter.c:148 adapter_khz_to_speed(): have adapter set up
Debug: 232 872 esp_usb_jtag.c:800 esp_usb_jtag_khz(): Divisor for 40000 KHz with base clock of 40000 khz is 1
Info : 233 876 adapter.c:108 adapter_init(): clock speed 40000 kHz
Debug: 234 879 openocd.c:143 handle_init_command(): Debug Adapter init complete
Debug: 235 882 command.c:166 script_debug(): command - transport init
Debug: 236 885 transport.c:230 handle_transport_init(): handle_transport_init
Debug: 237 889 core.c:712 legacy_jtag_add_reset(): SRST line released
Debug: 238 891 core.c:736 legacy_jtag_add_reset(): TRST line released
Debug: 239 894 core.c:322 jtag_call_event_callbacks(): jtag event: TAP reset
Debug: 240 899 command.c:166 script_debug(): command - jtag arp_init
Debug: 241 902 core.c:1503 jtag_init_inner(): Init JTAG chain
Debug: 242 904 core.c:322 jtag_call_event_callbacks(): jtag event: TAP reset
Debug: 243 907 core.c:1228 jtag_examine_chain(): DR scan interrogation for IDCODE/BYPASS
Debug: 244 911 core.c:322 jtag_call_event_callbacks(): jtag event: TAP reset
Info : 245 916 core.c:1127 jtag_examine_chain_display(): JTAG tap: esp32c3.cpu tap/device found: 0x00005c25 (mfg: 0x612 (Espressif Systems), part: 0x0005, ver: 0x0)
Debug: 246 922 core.c:1358 jtag_validate_ircapture(): IR capture validation scan
Debug: 247 926 core.c:1416 jtag_validate_ircapture(): esp32c3.cpu: IR capture 0x05
Debug: 248 929 command.c:166 script_debug(): command - dap init
Debug: 249 932 arm_dap.c:109 dap_init_all(): Initializing all DAPs ...
Debug: 250 934 openocd.c:160 handle_init_command(): Examining targets...
Debug: 251 937 target.c:1860 target_call_event_callbacks(): target event 19 (examine-start) for core esp32c3
Debug: 252 942 esp32c3.c:188 esp32c3_handle_target_event(): 19
Debug: 253 945 esp_riscv.c:281 esp_riscv_handle_target_event(): 19
Debug: 254 947 riscv.c:1118 riscv_examine(): riscv_examine()
Debug: 255 950 riscv.c:401 dtmcontrol_scan(): DTMCONTROL: 0x0 -> 0x1071
Debug: 256 953 riscv.c:1128 riscv_examine(): dtmcontrol=0x1071
Debug: 257 956 riscv.c:1130 riscv_examine():   version=0x1
Debug: 258 959 riscv-013.c:2289 init_target(): init
Debug: 259 961 riscv-013.c:451 dtmcontrol_scan(): DTMCS: 0x0 -> 0x1071
Debug: 260 964 riscv-013.c:1579 examine(): dtmcontrol=0x1071
Debug: 261 966 riscv-013.c:1580 examine():   dmireset=0
Debug: 262 968 riscv-013.c:1581 examine():   idle=1
Debug: 263 971 riscv-013.c:1582 examine():   dmistat=0
Debug: 264 973 riscv-013.c:1583 examine():   abits=7
Debug: 265 976 riscv-013.c:1584 examine():   version=1
Debug: 266 978 riscv-013.c:257 get_dm(): [0] Allocating new DM
Debug: 267 983 riscv-013.c:462 increase_dmi_busy_delay(): dtmcs_idle=1, dmi_busy_delay=1, ac_busy_delay=0
Debug: 268 987 riscv-013.c:451 dtmcontrol_scan(): DTMCS: 0x10000 -> 0x1c71
Debug: 269 991 riscv-013.c:462 increase_dmi_busy_delay(): dtmcs_idle=1, dmi_busy_delay=2, ac_busy_delay=0
Debug: 270 995 riscv-013.c:451 dtmcontrol_scan(): DTMCS: 0x10000 -> 0x1071
Debug: 271 999 riscv-013.c:1629 examine(): dmstatus:  0x0003c3a2
Debug: 272 1001 riscv-013.c:1645 examine(): hartsellen=20
Debug: 273 1005 riscv-013.c:462 increase_dmi_busy_delay(): dtmcs_idle=1, dmi_busy_delay=3, ac_busy_delay=0
Debug: 274 1009 riscv-013.c:451 dtmcontrol_scan(): DTMCS: 0x10000 -> 0x1071
Info : 275 1013 riscv-013.c:1676 examine(): datacount=2 progbufsize=16
Debug: 276 1019 riscv-013.c:1714 examine(): Detected 1 harts.
Debug: 277 1023 riscv-013.c:800 execute_abstract_command(): command=0x321008; access register, size=64, postexec=0, transfer=1, write=0, regno=0x1008
Debug: 278 1030 riscv-013.c:816 execute_abstract_command(): command 0x321008 failed; abstractcs=0x10000202
Debug: 279 1035 riscv-013.c:800 execute_abstract_command(): command=0x220301; access register, size=32, postexec=0, transfer=1, write=0, regno=0x301
Debug: 280 1042 riscv-013.c:1504 register_read_direct(): {0} misa = 0x40101104
Debug: 281 1045 riscv.c:3975 riscv_init_registers(): create register cache for 4194 registers
Debug: 282 1049 riscv-013.c:1765 examine():  hart 0: XLEN=32, misa=0x40101104
Info : 283 1053 riscv-013.c:1788 examine(): Examined RISC-V core; found 1 harts
Info : 284 1056 riscv-013.c:1790 examine():  hart 0: XLEN=32, misa=0x40101104
Debug: 285 1060 target.c:1860 target_call_event_callbacks(): target event 21 (examine-end) for core esp32c3
Debug: 286 1063 target.c:5153 target_handle_event(): target(0): esp32c3 (esp32c3) event: 21 (examine-end) action:
    # Need this to handle 'apptrace init' syscall correctly because semihosting is not enabled by default
    arm semihosting enable
    arm semihosting_resexit enable
    if { [info exists _SEMIHOST_BASEDIR] } {
        if { $_SEMIHOST_BASEDIR != "" } {
            arm semihosting_basedir $_SEMIHOST_BASEDIR
        }
    }

Debug: 287 1083 command.c:166 script_debug(): command - arm semihosting enable
Debug: 288 1087 riscv.c:2078 riscv_poll_hart():   triggered a halt
Debug: 289 1089 riscv.c:2258 riscv_openocd_poll():   hart 0 halted
Debug: 290 1093 riscv-013.c:800 execute_abstract_command(): command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0
Debug: 291 1100 riscv-013.c:1504 register_read_direct(): {0} dcsr = 0x400000c3
Debug: 292 1103 riscv-013.c:4345 riscv013_halt_reason(): dcsr.cause: 0x3
Debug: 293 1106 riscv.c:2113 set_debug_reason(): [esp32c3] debug_reason=0
Debug: 294 1109 target.c:1860 target_call_event_callbacks(): target event 0 (gdb-halt) for core esp32c3
Debug: 295 1113 esp32c3.c:188 esp32c3_handle_target_event(): 0
Debug: 296 1116 esp_riscv.c:281 esp_riscv_handle_target_event(): 0
Debug: 297 1119 target.c:1860 target_call_event_callbacks(): target event 1 (halted) for core esp32c3
Debug: 298 1123 target.c:5153 target_handle_event(): target(0): esp32c3 (esp32c3) event: 1 (halted) action:
    esp32c3_wdt_disable

Debug: 299 1128 command.c:166 script_debug(): command - command mode
Debug: 300 1131 command.c:166 script_debug(): command - mww 0x6001f064 0x50D83AA1
Debug: 301 1136 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x6001f064
Debug: 302 1141 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 303 1144 command.c:166 script_debug(): command - mww 0x6001F048 0
Debug: 304 1149 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x6001f048
Debug: 305 1154 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 306 1158 command.c:166 script_debug(): command - mww 0x60020064 0x50D83AA1
Debug: 307 1163 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x60020064
Debug: 308 1168 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 309 1171 command.c:166 script_debug(): command - mww 0x60020048 0
Debug: 310 1176 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x60020048
Debug: 311 1181 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 312 1185 command.c:166 script_debug(): command - mww 0x600080a8 0x50D83AA1
Debug: 313 1190 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x600080a8
Debug: 314 1195 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 315 1199 command.c:166 script_debug(): command - mww 0x60008090 0
Debug: 316 1203 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x60008090
Debug: 317 1208 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 318 1212 command.c:166 script_debug(): command - mww 0x600080b0 0x8F1D312A
Debug: 319 1216 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x600080b0
Debug: 320 1221 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 321 1226 command.c:166 script_debug(): command - mww 0x600080ac 0x84B00000
Debug: 322 1230 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x600080ac
Debug: 323 1236 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 324 1240 esp32c3.c:188 esp32c3_handle_target_event(): 1
Debug: 325 1242 esp_riscv.c:281 esp_riscv_handle_target_event(): 1
Debug: 326 1245 riscv_semihosting.c:192 riscv_semihosting_setup(): [esp32c3] enable=1
Debug: 327 1248 command.c:166 script_debug(): command - arm semihosting_resexit enable
Debug: 328 1253 command.c:166 script_debug(): command - arm semihosting_basedir .
Debug: 329 1257 esp32c3.c:188 esp32c3_handle_target_event(): 21
Debug: 330 1259 esp_riscv.c:281 esp_riscv_handle_target_event(): 21
Debug: 331 1262 command.c:166 script_debug(): command - flash init
Debug: 332 1265 tcl.c:1386 handle_flash_init_command(): Initializing flash devices...
Debug: 333 1269 command.c:166 script_debug(): command - nand init
Debug: 334 1272 tcl.c:498 handle_nand_init_command(): Initializing NAND devices...
Debug: 335 1275 command.c:166 script_debug(): command - pld init
Debug: 336 1279 pld.c:205 handle_pld_init_command(): Initializing PLDs...
Debug: 337 1281 command.c:166 script_debug(): command - tpiu init
Info : 338 1285 gdb_server.c:3796 gdb_target_start(): starting gdb server for esp32c3 on 3333
Info : 339 1289 server.c:303 add_service(): Listening on port 3333 for gdb connections
Info : 340 8628 server.c:95 add_connection(): accepting 'gdb' connection on tcp/3333
Debug: 341 8632 breakpoints.c:374 breakpoint_clear_target_internal(): Delete all breakpoints for target: esp32c3
Debug: 342 8636 breakpoints.c:562 watchpoint_clear_target(): Delete all watchpoints for target: esp32c3
Debug: 343 8644 target.c:1860 target_call_event_callbacks(): target event 22 (gdb-attach) for core esp32c3
Debug: 344 8649 target.c:5153 target_handle_event(): target(0): esp32c3 (esp32c3) event: 22 (gdb-attach) action:
    # 'halt' is necessary to auto-probe flash bank when GDB is connected and generate proper memory map
    halt 1000
    if { [esp32c3_memprot_is_enabled] } {
        # 'reset halt' to disable memory protection and allow flasher to work correctly
        echo "Memory protection is enabled. Reset target to disable it..."
        reset halt
    }
    # by default mask interrupts while stepping
    riscv set_maskisr steponly

Debug: 345 8672 command.c:166 script_debug(): command - halt 1000
Debug: 346 8675 target.c:3365 handle_halt_command(): -
Debug: 347 8678 riscv.c:1232 riscv_halt(): [0] halting all harts
Debug: 348 8680 riscv.c:1168 halt_prep(): [esp32c3] prep hart, debug_reason=0
Debug: 349 8684 riscv.c:1173 halt_prep(): [esp32c3] Hart is already halted (reason=0).
Debug: 350 8688 riscv.c:1190 riscv_halt_go_all_harts(): [esp32c3] Hart is already halted.
Debug: 351 8691 riscv.c:3397 riscv_invalidate_register_cache(): [0]
Debug: 352 8694 target.c:1860 target_call_event_callbacks(): target event 0 (gdb-halt) for core esp32c3
Debug: 353 8698 esp32c3.c:188 esp32c3_handle_target_event(): 0
Debug: 354 8700 esp_riscv.c:281 esp_riscv_handle_target_event(): 0
Debug: 355 8703 target.c:1860 target_call_event_callbacks(): target event 1 (halted) for core esp32c3
Debug: 356 8707 target.c:5153 target_handle_event(): target(0): esp32c3 (esp32c3) event: 1 (halted) action:
    esp32c3_wdt_disable

Debug: 357 8713 command.c:166 script_debug(): command - command mode
Debug: 358 8716 command.c:166 script_debug(): command - mww 0x6001f064 0x50D83AA1
Debug: 359 8721 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x6001f064
Debug: 360 8726 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 361 8730 command.c:166 script_debug(): command - mww 0x6001F048 0
Debug: 362 8734 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x6001f048
Debug: 363 8740 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 364 8743 command.c:166 script_debug(): command - mww 0x60020064 0x50D83AA1
Debug: 365 8749 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x60020064
Debug: 366 8754 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 367 8758 command.c:166 script_debug(): command - mww 0x60020048 0
Debug: 368 8763 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x60020048
Debug: 369 8768 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 370 8772 command.c:166 script_debug(): command - mww 0x600080a8 0x50D83AA1
Debug: 371 8777 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x600080a8
Debug: 372 8782 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 373 8786 command.c:166 script_debug(): command - mww 0x60008090 0
Debug: 374 8790 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x60008090
Debug: 375 8795 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 376 8799 command.c:166 script_debug(): command - mww 0x600080b0 0x8F1D312A
Debug: 377 8804 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x600080b0
Debug: 378 8809 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 379 8813 command.c:166 script_debug(): command - mww 0x600080ac 0x84B00000
Debug: 380 8818 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x600080ac
Debug: 381 8822 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 382 8827 esp32c3.c:188 esp32c3_handle_target_event(): 1
Debug: 383 8829 esp_riscv.c:281 esp_riscv_handle_target_event(): 1
Debug: 384 8832 command.c:166 script_debug(): command - read_memory 0x600C10A8 32 1
Debug: 385 8838 riscv-013.c:2858 log_mem_access_result(): Succeeded to read memory via system bus.
Debug: 386 8843 command.c:166 script_debug(): command - expr $val & [expr {1 << $BIT}]
Debug: 387 8847 command.c:166 script_debug(): command - expr 1 << $BIT
Debug: 388 8851 command.c:166 script_debug(): command - read_memory 0x600C10C0 32 1
Debug: 389 8857 riscv-013.c:2858 log_mem_access_result(): Succeeded to read memory via system bus.
Debug: 390 8860 command.c:166 script_debug(): command - expr $val & [expr {1 << $BIT}]
Debug: 391 8865 command.c:166 script_debug(): command - expr 1 << $BIT
Debug: 392 8868 command.c:166 script_debug(): command - riscv set_maskisr steponly
Debug: 393 8871 esp32c3.c:188 esp32c3_handle_target_event(): 22
Debug: 394 8874 esp_riscv.c:281 esp_riscv_handle_target_event(): 22
Debug: 395 8876 FreeRTOS.c:1360 freertos_clean(): freertos_clean
Debug: 396 8879 FreeRTOS.c:875 freertos_update_threads(): freertos_update_threads
Warn : 397 8883 FreeRTOS.c:883 freertos_update_threads(): No symbols for FreeRTOS!
Debug: 398 8886 esp_flash.c:948 esp_flash_probe(): Flash size = 0 KB @ 0x00000000 'esp32c3' - 'halted'
Debug: 399 8890 esp_flash.c:239 esp_flasher_algorithm_init(): base=00000000 set=0
Debug: 400 8893 esp_algorithm.c:312 algorithm_load_func_image(): stub: base 0x0, start 0x403810d2, 2 sections
Debug: 401 8899 esp_algorithm.c:319 algorithm_load_func_image(): addr 0x00000000, sz 7396, flags 1
Debug: 402 8903 target.c:2065 alloc_working_area_try_do(): MMU disabled, using physical address for working memory 0x40380000
Debug: 403 8908 target.c:2119 alloc_working_area_try_do(): allocated new working area of 7396 bytes at address 0x40380000
Debug: 404 9355 riscv-013.c:2858 log_mem_access_result(): Succeeded to read memory via system bus.
Debug: 405 9359 target.c:1986 print_wa_layout(): b* 0x40380000-0x40381ce3 (7396 bytes)
Debug: 406 9363 target.c:1986 print_wa_layout():    0x40381ce4-0x40383fff (8988 bytes)
Debug: 407 9368 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40380000
Debug: 408 9374 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380000
Debug: 409 9385 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 410 9390 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40380200
Debug: 411 9396 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380200
Debug: 412 9406 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 413 9411 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40380400
Debug: 414 9417 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380400
Debug: 415 9428 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 416 9433 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40380600
Debug: 417 9440 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380600
Debug: 418 9450 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 419 9454 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40380800
Debug: 420 9460 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380800
Debug: 421 9471 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 422 9476 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40380a00
Debug: 423 9482 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380a00
Debug: 424 9494 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 425 9498 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40380c00
Debug: 426 9504 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380c00
Debug: 427 9513 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 428 9518 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40380e00
Debug: 429 9524 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380e00
Debug: 430 9535 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 431 9540 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40381000
Debug: 432 9546 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381000
Debug: 433 9556 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 434 9560 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40381200
Debug: 435 9566 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381200
Debug: 436 9576 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 437 9580 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40381400
Debug: 438 9587 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381400
Debug: 439 9596 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 440 9602 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40381600
Debug: 441 9608 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381600
Debug: 442 9618 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 443 9622 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40381800
Debug: 444 9628 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381800
Debug: 445 9640 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 446 9644 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40381a00
Debug: 447 9651 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381a00
Debug: 448 9662 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 449 9667 target.c:2471 target_write_buffer(): writing buffer of 228 byte at 0x40381c00
Debug: 450 9672 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381c00
Debug: 451 9681 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 452 9685 esp_algorithm.c:319 algorithm_load_func_image(): addr 0x00000000, sz 769, flags 0
Debug: 453 9689 esp_algorithm.c:351 algorithm_load_func_image(): DATA sec size 769 -> 772
Debug: 454 9694 esp_algorithm.c:356 algorithm_load_func_image(): BSS sec size 289 -> 292
Debug: 455 9698 target.c:2065 alloc_working_area_try_do(): MMU disabled, using physical address for working memory 0x3fc84000
Debug: 456 9705 target.c:2119 alloc_working_area_try_do(): allocated new working area of 1064 bytes at address 0x3fc84000
Debug: 457 9779 riscv-013.c:2858 log_mem_access_result(): Succeeded to read memory via system bus.
Debug: 458 9783 target.c:1986 print_wa_layout(): b* 0x3fc84000-0x3fc84427 (1064 bytes)
Debug: 459 9788 target.c:1986 print_wa_layout():    0x3fc84428-0x3fca3fff (130008 bytes)
Debug: 460 9792 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x3fc84000
Debug: 461 9796 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x3fc84000
Debug: 462 9807 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 463 9811 target.c:2471 target_write_buffer(): writing buffer of 257 byte at 0x3fc84200
Debug: 464 9817 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x3fc84200
Debug: 465 9824 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 466 9828 esp_riscv.c:556 esp_riscv_write_memory(): Use 32-bit access: size: 1    count:1 start address: 0x3fc84300
Debug: 467 9837 riscv-013.c:2858 log_mem_access_result(): Succeeded to read memory via system bus.
Debug: 468 9843 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x3fc84300
Debug: 469 9847 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 470 9850 target.c:2119 alloc_working_area_try_do(): allocated new working area of 1300 bytes at address 0x3fc84428
Debug: 471 9934 riscv-013.c:2858 log_mem_access_result(): Succeeded to read memory via system bus.
Debug: 472 9939 target.c:1986 print_wa_layout(): b* 0x3fc84000-0x3fc84427 (1064 bytes)
Debug: 473 9943 target.c:1986 print_wa_layout(): b* 0x3fc84428-0x3fc8493b (1300 bytes)
Debug: 474 9947 target.c:1986 print_wa_layout():    0x3fc8493c-0x3fca3fff (128708 bytes)
Debug: 475 9952 target.c:2119 alloc_working_area_try_do(): allocated new working area of 4 bytes at address 0x40381ce4
Debug: 476 9961 riscv-013.c:2858 log_mem_access_result(): Succeeded to read memory via system bus.
Debug: 477 9964 target.c:1986 print_wa_layout(): b* 0x40380000-0x40381ce3 (7396 bytes)
Debug: 478 9968 target.c:1986 print_wa_layout(): b* 0x40381ce4-0x40381ce7 (4 bytes)
Debug: 479 9971 target.c:1986 print_wa_layout():    0x40381ce8-0x40383fff (8984 bytes)
Debug: 480 9974 target.c:2471 target_write_buffer(): writing buffer of 4 byte at 0x40381ce4
Debug: 481 9980 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381ce4
Debug: 482 9985 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 483 9989 esp_algorithm.c:442 algorithm_load_func_image(): Stub loaded in 1095.37 ms
Debug: 484 9992 esp_riscv_algorithm.c:55 esp_riscv_algo_regs_init_start(): Check stack addr 0x3fc8493c
Debug: 485 9997 esp_riscv_algorithm.c:58 esp_riscv_algo_regs_init_start(): Adjust stack addr to 0x3fc84930
Debug: 486 10000 esp_riscv_algorithm.c:98 esp_riscv_algo_init(): Set arg[0] = 5 (a0)
Debug: 487 10003 esp_riscv_algorithm.c:109 esp_riscv_algo_init(): Set arg[1] = -1 (a1)
Debug: 488 10007 esp_riscv_algorithm.c:109 esp_riscv_algo_init(): Set arg[2] = 0 (a2)
Debug: 489 10010 target.c:2119 alloc_working_area_try_do(): allocated new working area of 28 bytes at address 0x3fc8493c
Debug: 490 10020 riscv-013.c:2858 log_mem_access_result(): Succeeded to read memory via system bus.
Debug: 491 10025 target.c:1986 print_wa_layout(): b* 0x3fc84000-0x3fc84427 (1064 bytes)
Debug: 492 10029 target.c:1986 print_wa_layout(): b* 0x3fc84428-0x3fc8493b (1300 bytes)
Debug: 493 10033 target.c:1986 print_wa_layout(): b* 0x3fc8493c-0x3fc84957 (28 bytes)
Debug: 494 10037 target.c:1986 print_wa_layout():    0x3fc84958-0x3fca3fff (128680 bytes)
Debug: 495 10042 esp_algorithm.c:196 algorithm_run(): Algorithm start @ 0x40381ce4, stack 1300 bytes @ 0x3fc8493c
Debug: 496 10047 esp_riscv.c:321 esp_riscv_start_algorithm(): save ra
Debug: 497 10051 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register ra
Debug: 498 10056 riscv-013.c:800 execute_abstract_command(): command=0x221001; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1001
Debug: 499 10064 riscv-013.c:1504 register_read_direct(): {0} ra = 0x4038aa78
Debug: 500 10067 riscv.c:3534 riscv_get_register(): [esp32c3] ra: 4038aa78
Debug: 501 10069 riscv.c:3888 register_get(): [esp32c3] read 0x4038aa78 from ra (valid=1)
Debug: 502 10073 esp_riscv.c:321 esp_riscv_start_algorithm(): save sp
Debug: 503 10076 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register sp
Debug: 504 10079 riscv-013.c:800 execute_abstract_command(): command=0x221002; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1002
Debug: 505 10087 riscv-013.c:1504 register_read_direct(): {0} sp = 0x3fca8080
Debug: 506 10090 riscv.c:3534 riscv_get_register(): [esp32c3] sp: 3fca8080
Debug: 507 10093 riscv.c:3888 register_get(): [esp32c3] read 0x3fca8080 from sp (valid=1)
Debug: 508 10096 esp_riscv.c:321 esp_riscv_start_algorithm(): save gp
Debug: 509 10099 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register gp
Debug: 510 10103 riscv-013.c:800 execute_abstract_command(): command=0x221003; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1003
Debug: 511 10110 riscv-013.c:1504 register_read_direct(): {0} gp = 0x3fc8fc00
Debug: 512 10113 riscv.c:3534 riscv_get_register(): [esp32c3] gp: 3fc8fc00
Debug: 513 10116 riscv.c:3888 register_get(): [esp32c3] read 0x3fc8fc00 from gp (valid=1)
Debug: 514 10120 esp_riscv.c:321 esp_riscv_start_algorithm(): save tp
Debug: 515 10122 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register tp
Debug: 516 10126 riscv-013.c:800 execute_abstract_command(): command=0x221004; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1004
Debug: 517 10133 riscv-013.c:1504 register_read_direct(): {0} tp = 0x3fc97820
Debug: 518 10136 riscv.c:3534 riscv_get_register(): [esp32c3] tp: 3fc97820
Debug: 519 10139 riscv.c:3888 register_get(): [esp32c3] read 0x3fc97820 from tp (valid=1)
Debug: 520 10142 esp_riscv.c:321 esp_riscv_start_algorithm(): save t0
Debug: 521 10145 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register t0
Debug: 522 10148 riscv-013.c:800 execute_abstract_command(): command=0x221005; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1005
Debug: 523 10156 riscv-013.c:1504 register_read_direct(): {0} t0 = 0x0
Debug: 524 10159 riscv.c:3534 riscv_get_register(): [esp32c3] t0: 0
Debug: 525 10161 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from t0 (valid=1)
Debug: 526 10165 esp_riscv.c:321 esp_riscv_start_algorithm(): save t1
Debug: 527 10168 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register t1
Debug: 528 10171 riscv-013.c:800 execute_abstract_command(): command=0x221006; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1006
Debug: 529 10178 riscv-013.c:1504 register_read_direct(): {0} t1 = 0x0
Debug: 530 10180 riscv.c:3534 riscv_get_register(): [esp32c3] t1: 0
Debug: 531 10184 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from t1 (valid=1)
Debug: 532 10187 esp_riscv.c:321 esp_riscv_start_algorithm(): save t2
Debug: 533 10189 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register t2
Debug: 534 10192 riscv-013.c:800 execute_abstract_command(): command=0x221007; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1007
Debug: 535 10202 riscv-013.c:1504 register_read_direct(): {0} t2 = 0x0
Debug: 536 10204 riscv.c:3534 riscv_get_register(): [esp32c3] t2: 0
Debug: 537 10207 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from t2 (valid=1)
Debug: 538 10210 esp_riscv.c:321 esp_riscv_start_algorithm(): save fp
Debug: 539 10213 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register s0
Debug: 540 10216 riscv-013.c:800 execute_abstract_command(): command=0x221008; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1008
Debug: 541 10224 riscv-013.c:1504 register_read_direct(): {0} s0 = 0x0
Debug: 542 10226 riscv.c:3534 riscv_get_register(): [esp32c3] s0: 0
Debug: 543 10230 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from fp (valid=1)
Debug: 544 10233 esp_riscv.c:321 esp_riscv_start_algorithm(): save s1
Debug: 545 10235 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register s1
Debug: 546 10239 riscv-013.c:800 execute_abstract_command(): command=0x221009; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1009
Debug: 547 10247 riscv-013.c:1504 register_read_direct(): {0} s1 = 0x1
Debug: 548 10249 riscv.c:3534 riscv_get_register(): [esp32c3] s1: 1
Debug: 549 10252 riscv.c:3888 register_get(): [esp32c3] read 0x00000001 from s1 (valid=1)
Debug: 550 10255 esp_riscv.c:321 esp_riscv_start_algorithm(): save a0
Debug: 551 10258 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register a0
Debug: 552 10261 riscv-013.c:800 execute_abstract_command(): command=0x22100a; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100a
Debug: 553 10269 riscv-013.c:1504 register_read_direct(): {0} a0 = 0x1
Debug: 554 10272 riscv.c:3534 riscv_get_register(): [esp32c3] a0: 1
Debug: 555 10274 riscv.c:3888 register_get(): [esp32c3] read 0x00000001 from a0 (valid=1)
Debug: 556 10278 esp_riscv.c:321 esp_riscv_start_algorithm(): save a1
Debug: 557 10280 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register a1
Debug: 558 10284 riscv-013.c:800 execute_abstract_command(): command=0x22100b; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100b
Debug: 559 10291 riscv-013.c:1504 register_read_direct(): {0} a1 = 0x3fca809f
Debug: 560 10294 riscv.c:3534 riscv_get_register(): [esp32c3] a1: 3fca809f
Debug: 561 10297 riscv.c:3888 register_get(): [esp32c3] read 0x3fca809f from a1 (valid=1)
Debug: 562 10299 esp_riscv.c:321 esp_riscv_start_algorithm(): save a2
Debug: 563 10302 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register a2
Debug: 564 10306 riscv-013.c:800 execute_abstract_command(): command=0x22100c; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100c
Debug: 565 10313 riscv-013.c:1504 register_read_direct(): {0} a2 = 0x0
Debug: 566 10316 riscv.c:3534 riscv_get_register(): [esp32c3] a2: 0
Debug: 567 10319 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from a2 (valid=1)
Debug: 568 10322 esp_riscv.c:321 esp_riscv_start_algorithm(): save a3
Debug: 569 10325 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register a3
Debug: 570 10328 riscv-013.c:800 execute_abstract_command(): command=0x22100d; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100d
Debug: 571 10336 riscv-013.c:1504 register_read_direct(): {0} a3 = 0x4
Debug: 572 10338 riscv.c:3534 riscv_get_register(): [esp32c3] a3: 4
Debug: 573 10341 riscv.c:3888 register_get(): [esp32c3] read 0x00000004 from a3 (valid=1)
Debug: 574 10344 esp_riscv.c:321 esp_riscv_start_algorithm(): save a4
Debug: 575 10347 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register a4
Debug: 576 10350 riscv-013.c:800 execute_abstract_command(): command=0x22100e; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100e
Debug: 577 10358 riscv-013.c:1504 register_read_direct(): {0} a4 = 0x600c2000
Debug: 578 10361 riscv.c:3534 riscv_get_register(): [esp32c3] a4: 600c2000
Debug: 579 10363 riscv.c:3888 register_get(): [esp32c3] read 0x600c2000 from a4 (valid=1)
Debug: 580 10367 esp_riscv.c:321 esp_riscv_start_algorithm(): save a5
Debug: 581 10370 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register a5
Debug: 582 10373 riscv-013.c:800 execute_abstract_command(): command=0x22100f; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100f
Debug: 583 10381 riscv-013.c:1504 register_read_direct(): {0} a5 = 0x89
Debug: 584 10383 riscv.c:3534 riscv_get_register(): [esp32c3] a5: 89
Debug: 585 10386 riscv.c:3888 register_get(): [esp32c3] read 0x00000089 from a5 (valid=1)
Debug: 586 10389 esp_riscv.c:321 esp_riscv_start_algorithm(): save a6
Debug: 587 10392 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register a6
Debug: 588 10395 riscv-013.c:800 execute_abstract_command(): command=0x221010; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1010
Debug: 589 10402 riscv-013.c:1504 register_read_direct(): {0} a6 = 0x0
Debug: 590 10405 riscv.c:3534 riscv_get_register(): [esp32c3] a6: 0
Debug: 591 10407 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from a6 (valid=1)
Debug: 592 10411 esp_riscv.c:321 esp_riscv_start_algorithm(): save a7
Debug: 593 10414 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register a7
Debug: 594 10417 riscv-013.c:800 execute_abstract_command(): command=0x221011; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1011
Debug: 595 10425 riscv-013.c:1504 register_read_direct(): {0} a7 = 0x0
Debug: 596 10427 riscv.c:3534 riscv_get_register(): [esp32c3] a7: 0
Debug: 597 10430 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from a7 (valid=1)
Debug: 598 10434 esp_riscv.c:321 esp_riscv_start_algorithm(): save s2
Debug: 599 10435 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register s2
Debug: 600 10440 riscv-013.c:800 execute_abstract_command(): command=0x221012; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1012
Debug: 601 10447 riscv-013.c:1504 register_read_direct(): {0} s2 = 0x0
Debug: 602 10449 riscv.c:3534 riscv_get_register(): [esp32c3] s2: 0
Debug: 603 10452 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from s2 (valid=1)
Debug: 604 10455 esp_riscv.c:321 esp_riscv_start_algorithm(): save s3
Debug: 605 10458 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register s3
Debug: 606 10461 riscv-013.c:800 execute_abstract_command(): command=0x221013; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1013
Debug: 607 10469 riscv-013.c:1504 register_read_direct(): {0} s3 = 0x0
Debug: 608 10471 riscv.c:3534 riscv_get_register(): [esp32c3] s3: 0
Debug: 609 10474 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from s3 (valid=1)
Debug: 610 10477 esp_riscv.c:321 esp_riscv_start_algorithm(): save s4
Debug: 611 10480 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register s4
Debug: 612 10483 riscv-013.c:800 execute_abstract_command(): command=0x221014; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1014
Debug: 613 10490 riscv-013.c:1504 register_read_direct(): {0} s4 = 0x0
Debug: 614 10493 riscv.c:3534 riscv_get_register(): [esp32c3] s4: 0
Debug: 615 10496 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from s4 (valid=1)
Debug: 616 10499 esp_riscv.c:321 esp_riscv_start_algorithm(): save s5
Debug: 617 10502 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register s5
Debug: 618 10505 riscv-013.c:800 execute_abstract_command(): command=0x221015; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1015
Debug: 619 10513 riscv-013.c:1504 register_read_direct(): {0} s5 = 0x0
Debug: 620 10515 riscv.c:3534 riscv_get_register(): [esp32c3] s5: 0
Debug: 621 10518 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from s5 (valid=1)
Debug: 622 10521 esp_riscv.c:321 esp_riscv_start_algorithm(): save s6
Debug: 623 10524 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register s6
Debug: 624 10527 riscv-013.c:800 execute_abstract_command(): command=0x221016; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1016
Debug: 625 10535 riscv-013.c:1504 register_read_direct(): {0} s6 = 0x0
Debug: 626 10537 riscv.c:3534 riscv_get_register(): [esp32c3] s6: 0
Debug: 627 10540 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from s6 (valid=1)
Debug: 628 10544 esp_riscv.c:321 esp_riscv_start_algorithm(): save s7
Debug: 629 10546 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register s7
Debug: 630 10549 riscv-013.c:800 execute_abstract_command(): command=0x221017; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1017
Debug: 631 10557 riscv-013.c:1504 register_read_direct(): {0} s7 = 0x0
Debug: 632 10559 riscv.c:3534 riscv_get_register(): [esp32c3] s7: 0
Debug: 633 10562 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from s7 (valid=1)
Debug: 634 10565 esp_riscv.c:321 esp_riscv_start_algorithm(): save s8
Debug: 635 10568 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register s8
Debug: 636 10571 riscv-013.c:800 execute_abstract_command(): command=0x221018; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1018
Debug: 637 10579 riscv-013.c:1504 register_read_direct(): {0} s8 = 0x0
Debug: 638 10581 riscv.c:3534 riscv_get_register(): [esp32c3] s8: 0
Debug: 639 10584 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from s8 (valid=1)
Debug: 640 10587 esp_riscv.c:321 esp_riscv_start_algorithm(): save s9
Debug: 641 10590 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register s9
Debug: 642 10593 riscv-013.c:800 execute_abstract_command(): command=0x221019; access register, size=32, postexec=0, transfer=1, write=0, regno=0x1019
Debug: 643 10600 riscv-013.c:1504 register_read_direct(): {0} s9 = 0x0
Debug: 644 10603 riscv.c:3534 riscv_get_register(): [esp32c3] s9: 0
Debug: 645 10606 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from s9 (valid=1)
Debug: 646 10609 esp_riscv.c:321 esp_riscv_start_algorithm(): save s10
Debug: 647 10612 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register s10
Debug: 648 10615 riscv-013.c:800 execute_abstract_command(): command=0x22101a; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101a
Debug: 649 10623 riscv-013.c:1504 register_read_direct(): {0} s10 = 0x0
Debug: 650 10625 riscv.c:3534 riscv_get_register(): [esp32c3] s10: 0
Debug: 651 10628 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from s10 (valid=1)
Debug: 652 10631 esp_riscv.c:321 esp_riscv_start_algorithm(): save s11
Debug: 653 10634 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register s11
Debug: 654 10637 riscv-013.c:800 execute_abstract_command(): command=0x22101b; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101b
Debug: 655 10645 riscv-013.c:1504 register_read_direct(): {0} s11 = 0x0
Debug: 656 10647 riscv.c:3534 riscv_get_register(): [esp32c3] s11: 0
Debug: 657 10651 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from s11 (valid=1)
Debug: 658 10654 esp_riscv.c:321 esp_riscv_start_algorithm(): save t3
Debug: 659 10657 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register t3
Debug: 660 10660 riscv-013.c:800 execute_abstract_command(): command=0x22101c; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101c
Debug: 661 10668 riscv-013.c:1504 register_read_direct(): {0} t3 = 0x0
Debug: 662 10670 riscv.c:3534 riscv_get_register(): [esp32c3] t3: 0
Debug: 663 10673 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from t3 (valid=1)
Debug: 664 10677 esp_riscv.c:321 esp_riscv_start_algorithm(): save t4
Debug: 665 10680 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register t4
Debug: 666 10684 riscv-013.c:800 execute_abstract_command(): command=0x22101d; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101d
Debug: 667 10692 riscv-013.c:1504 register_read_direct(): {0} t4 = 0x0
Debug: 668 10694 riscv.c:3534 riscv_get_register(): [esp32c3] t4: 0
Debug: 669 10696 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from t4 (valid=1)
Debug: 670 10700 esp_riscv.c:321 esp_riscv_start_algorithm(): save t5
Debug: 671 10703 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register t5
Debug: 672 10706 riscv-013.c:800 execute_abstract_command(): command=0x22101e; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101e
Debug: 673 10714 riscv-013.c:1504 register_read_direct(): {0} t5 = 0x0
Debug: 674 10716 riscv.c:3534 riscv_get_register(): [esp32c3] t5: 0
Debug: 675 10719 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from t5 (valid=1)
Debug: 676 10722 esp_riscv.c:321 esp_riscv_start_algorithm(): save t6
Debug: 677 10725 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register t6
Debug: 678 10728 riscv-013.c:800 execute_abstract_command(): command=0x22101f; access register, size=32, postexec=0, transfer=1, write=0, regno=0x101f
Debug: 679 10736 riscv-013.c:1504 register_read_direct(): {0} t6 = 0x0
Debug: 680 10738 riscv.c:3534 riscv_get_register(): [esp32c3] t6: 0
Debug: 681 10741 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from t6 (valid=1)
Debug: 682 10744 esp_riscv.c:321 esp_riscv_start_algorithm(): save pc
Debug: 683 10747 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register pc
Debug: 684 10751 riscv-013.c:800 execute_abstract_command(): command=0x2207b1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b1
Debug: 685 10758 riscv-013.c:1504 register_read_direct(): {0} dpc = 0x4038aa24
Debug: 686 10761 riscv-013.c:4095 riscv013_get_register(): [0] read PC from DPC: 0x4038aa24
Debug: 687 10765 riscv.c:3534 riscv_get_register(): [esp32c3] pc: 4038aa24
Debug: 688 10768 riscv.c:3888 register_get(): [esp32c3] read 0x4038aa24 from pc (valid=0)
Debug: 689 10770 esp_riscv.c:321 esp_riscv_start_algorithm(): save mstatus
Debug: 690 10773 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register mstatus
Debug: 691 10777 riscv-013.c:800 execute_abstract_command(): command=0x220300; access register, size=32, postexec=0, transfer=1, write=0, regno=0x300
Debug: 692 10784 riscv-013.c:1504 register_read_direct(): {0} mstatus = 0x81
Debug: 693 10787 riscv.c:3534 riscv_get_register(): [esp32c3] mstatus: 81
Debug: 694 10790 riscv.c:3888 register_get(): [esp32c3] read 0x00000081 from mstatus (valid=1)
Debug: 695 10793 esp_riscv.c:321 esp_riscv_start_algorithm(): save misa
Debug: 696 10797 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register misa
Debug: 697 10800 riscv-013.c:800 execute_abstract_command(): command=0x220301; access register, size=32, postexec=0, transfer=1, write=0, regno=0x301
Debug: 698 10807 riscv-013.c:1504 register_read_direct(): {0} misa = 0x40101104
Debug: 699 10810 riscv.c:3534 riscv_get_register(): [esp32c3] misa: 40101104
Debug: 700 10813 riscv.c:3888 register_get(): [esp32c3] read 0x40101104 from misa (valid=1)
Debug: 701 10816 esp_riscv.c:321 esp_riscv_start_algorithm(): save mtvec
Debug: 702 10819 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr773
Debug: 703 10823 riscv-013.c:800 execute_abstract_command(): command=0x220305; access register, size=32, postexec=0, transfer=1, write=0, regno=0x305
Debug: 704 10830 riscv-013.c:1504 register_read_direct(): {0} csr773 = 0x40380001
Debug: 705 10834 riscv.c:3534 riscv_get_register(): [esp32c3] csr773: 40380001
Debug: 706 10836 riscv.c:3888 register_get(): [esp32c3] read 0x40380001 from mtvec (valid=0)
Debug: 707 10840 esp_riscv.c:321 esp_riscv_start_algorithm(): save mscratch
Debug: 708 10842 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr832
Debug: 709 10846 riscv-013.c:800 execute_abstract_command(): command=0x220340; access register, size=32, postexec=0, transfer=1, write=0, regno=0x340
Debug: 710 10854 riscv-013.c:1504 register_read_direct(): {0} csr832 = 0x0
Debug: 711 10857 riscv.c:3534 riscv_get_register(): [esp32c3] csr832: 0
Debug: 712 10860 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from mscratch (valid=0)
Debug: 713 10863 esp_riscv.c:321 esp_riscv_start_algorithm(): save mepc
Debug: 714 10866 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register mepc
Debug: 715 10870 riscv-013.c:800 execute_abstract_command(): command=0x220341; access register, size=32, postexec=0, transfer=1, write=0, regno=0x341
Debug: 716 10877 riscv-013.c:1504 register_read_direct(): {0} mepc = 0x4038aaaa
Debug: 717 10880 riscv.c:3534 riscv_get_register(): [esp32c3] mepc: 4038aaaa
Debug: 718 10882 riscv.c:3888 register_get(): [esp32c3] read 0x4038aaaa from mepc (valid=1)
Debug: 719 10886 esp_riscv.c:321 esp_riscv_start_algorithm(): save mcause
Debug: 720 10889 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register mcause
Debug: 721 10893 riscv-013.c:800 execute_abstract_command(): command=0x220342; access register, size=32, postexec=0, transfer=1, write=0, regno=0x342
Debug: 722 10900 riscv-013.c:1504 register_read_direct(): {0} mcause = 0x80000009
Debug: 723 10903 riscv.c:3534 riscv_get_register(): [esp32c3] mcause: 80000009
Debug: 724 10906 riscv.c:3888 register_get(): [esp32c3] read 0x80000009 from mcause (valid=1)
Debug: 725 10909 esp_riscv.c:321 esp_riscv_start_algorithm(): save mtval
Debug: 726 10912 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr835
Debug: 727 10915 riscv-013.c:800 execute_abstract_command(): command=0x220343; access register, size=32, postexec=0, transfer=1, write=0, regno=0x343
Debug: 728 10923 riscv-013.c:1504 register_read_direct(): {0} csr835 = 0x8082
Debug: 729 10926 riscv.c:3534 riscv_get_register(): [esp32c3] csr835: 8082
Debug: 730 10928 riscv.c:3888 register_get(): [esp32c3] read 0x00008082 from mtval (valid=0)
Debug: 731 10932 esp_riscv.c:321 esp_riscv_start_algorithm(): save pmpcfg0
Debug: 732 10935 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr928
Debug: 733 10939 riscv-013.c:800 execute_abstract_command(): command=0x2203a0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3a0
Debug: 734 10946 riscv-013.c:1504 register_read_direct(): {0} csr928 = 0x89888f88
Debug: 735 10948 riscv.c:3534 riscv_get_register(): [esp32c3] csr928: 89888f88
Debug: 736 10951 riscv.c:3888 register_get(): [esp32c3] read 0x89888f88 from pmpcfg0 (valid=0)
Debug: 737 10955 esp_riscv.c:321 esp_riscv_start_algorithm(): save pmpcfg1
Debug: 738 10958 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr929
Debug: 739 10961 riscv-013.c:800 execute_abstract_command(): command=0x2203a1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3a1
Debug: 740 10969 riscv-013.c:1504 register_read_direct(): {0} csr929 = 0x888d898b
Debug: 741 10972 riscv.c:3534 riscv_get_register(): [esp32c3] csr929: 888d898b
Debug: 742 10975 riscv.c:3888 register_get(): [esp32c3] read 0x888d898b from pmpcfg1 (valid=0)
Debug: 743 10978 esp_riscv.c:321 esp_riscv_start_algorithm(): save pmpcfg2
Debug: 744 10982 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr930
Debug: 745 10985 riscv-013.c:800 execute_abstract_command(): command=0x2203a2; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3a2
Debug: 746 10992 riscv-013.c:1504 register_read_direct(): {0} csr930 = 0x8f888d8f
Debug: 747 10996 riscv.c:3534 riscv_get_register(): [esp32c3] csr930: 8f888d8f
Debug: 748 10998 riscv.c:3888 register_get(): [esp32c3] read 0x8f888d8f from pmpcfg2 (valid=0)
Debug: 749 11002 esp_riscv.c:321 esp_riscv_start_algorithm(): save pmpcfg3
Debug: 750 11005 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr931
Debug: 751 11008 riscv-013.c:800 execute_abstract_command(): command=0x2203a3; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3a3
Debug: 752 11016 riscv-013.c:1504 register_read_direct(): {0} csr931 = 0x90888b88
Debug: 753 11019 riscv.c:3534 riscv_get_register(): [esp32c3] csr931: 90888b88
Debug: 754 11022 riscv.c:3888 register_get(): [esp32c3] read 0x90888b88 from pmpcfg3 (valid=0)
Debug: 755 11026 esp_riscv.c:321 esp_riscv_start_algorithm(): save pmpaddr0
Debug: 756 11028 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr944
Debug: 757 11032 riscv-013.c:800 execute_abstract_command(): command=0x2203b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b0
Debug: 758 11039 riscv-013.c:1504 register_read_direct(): {0} csr944 = 0x8000000
Debug: 759 11042 riscv.c:3534 riscv_get_register(): [esp32c3] csr944: 8000000
Debug: 760 11045 riscv.c:3888 register_get(): [esp32c3] read 0x08000000 from pmpaddr0 (valid=0)
Debug: 761 11049 esp_riscv.c:321 esp_riscv_start_algorithm(): save pmpaddr1
Debug: 762 11051 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr945
Debug: 763 11055 riscv-013.c:800 execute_abstract_command(): command=0x2203b1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b1
Debug: 764 11062 riscv-013.c:1504 register_read_direct(): {0} csr945 = 0xa000000
Debug: 765 11065 riscv.c:3534 riscv_get_register(): [esp32c3] csr945: a000000
Debug: 766 11068 riscv.c:3888 register_get(): [esp32c3] read 0x0a000000 from pmpaddr1 (valid=0)
Debug: 767 11072 esp_riscv.c:321 esp_riscv_start_algorithm(): save pmpaddr2
Debug: 768 11075 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr946
Debug: 769 11079 riscv-013.c:800 execute_abstract_command(): command=0x2203b2; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b2
Debug: 770 11086 riscv-013.c:1504 register_read_direct(): {0} csr946 = 0xf000000
Debug: 771 11089 riscv.c:3534 riscv_get_register(): [esp32c3] csr946: f000000
Debug: 772 11093 riscv.c:3888 register_get(): [esp32c3] read 0x0f000000 from pmpaddr2 (valid=0)
Debug: 773 11096 esp_riscv.c:321 esp_riscv_start_algorithm(): save pmpaddr3
Debug: 774 11099 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr947
Debug: 775 11102 riscv-013.c:800 execute_abstract_command(): command=0x2203b3; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b3
Debug: 776 11110 riscv-013.c:1504 register_read_direct(): {0} csr947 = 0xff20000
Debug: 777 11113 riscv.c:3534 riscv_get_register(): [esp32c3] csr947: ff20000
Debug: 778 11116 riscv.c:3888 register_get(): [esp32c3] read 0x0ff20000 from pmpaddr3 (valid=0)
Debug: 779 11120 esp_riscv.c:321 esp_riscv_start_algorithm(): save pmpaddr4
Debug: 780 11123 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr948
Debug: 781 11126 riscv-013.c:800 execute_abstract_command(): command=0x2203b4; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b4
Debug: 782 11133 riscv-013.c:1504 register_read_direct(): {0} csr948 = 0xff38000
Debug: 783 11137 riscv.c:3534 riscv_get_register(): [esp32c3] csr948: ff38000
Debug: 784 11140 riscv.c:3888 register_get(): [esp32c3] read 0x0ff38000 from pmpaddr4 (valid=0)
Debug: 785 11143 esp_riscv.c:321 esp_riscv_start_algorithm(): save pmpaddr5
Debug: 786 11146 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr949
Debug: 787 11149 riscv-013.c:800 execute_abstract_command(): command=0x2203b5; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b5
Debug: 788 11158 riscv-013.c:1504 register_read_direct(): {0} csr949 = 0xffc8000
Debug: 789 11160 riscv.c:3534 riscv_get_register(): [esp32c3] csr949: ffc8000
Debug: 790 11163 riscv.c:3888 register_get(): [esp32c3] read 0x0ffc8000 from pmpaddr5 (valid=0)
Debug: 791 11167 esp_riscv.c:321 esp_riscv_start_algorithm(): save pmpaddr6
Debug: 792 11170 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr950
Debug: 793 11174 riscv-013.c:800 execute_abstract_command(): command=0x2203b6; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b6
Debug: 794 11181 riscv-013.c:1504 register_read_direct(): {0} csr950 = 0x10018000
Debug: 795 11184 riscv.c:3534 riscv_get_register(): [esp32c3] csr950: 10018000
Debug: 796 11187 riscv.c:3888 register_get(): [esp32c3] read 0x10018000 from pmpaddr6 (valid=0)
Debug: 797 11190 esp_riscv.c:321 esp_riscv_start_algorithm(): save pmpaddr7
Debug: 798 11193 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr951
Debug: 799 11196 riscv-013.c:800 execute_abstract_command(): command=0x2203b7; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b7
Debug: 800 11204 riscv-013.c:1504 register_read_direct(): {0} csr951 = 0x100df000
Debug: 801 11207 riscv.c:3534 riscv_get_register(): [esp32c3] csr951: 100df000
Debug: 802 11210 riscv.c:3888 register_get(): [esp32c3] read 0x100df000 from pmpaddr7 (valid=0)
Debug: 803 11214 esp_riscv.c:321 esp_riscv_start_algorithm(): save pmpaddr8
Debug: 804 11217 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr952
Debug: 805 11220 riscv-013.c:800 execute_abstract_command(): command=0x2203b8; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b8
Debug: 806 11228 riscv-013.c:1504 register_read_direct(): {0} csr952 = 0x100f8000
Debug: 807 11231 riscv.c:3534 riscv_get_register(): [esp32c3] csr952: 100f8000
Debug: 808 11234 riscv.c:3888 register_get(): [esp32c3] read 0x100f8000 from pmpaddr8 (valid=0)
Debug: 809 11238 esp_riscv.c:321 esp_riscv_start_algorithm(): save pmpaddr9
Debug: 810 11240 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr953
Debug: 811 11244 riscv-013.c:800 execute_abstract_command(): command=0x2203b9; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b9
Debug: 812 11251 riscv-013.c:1504 register_read_direct(): {0} csr953 = 0x10a00000
Debug: 813 11254 riscv.c:3534 riscv_get_register(): [esp32c3] csr953: 10a00000
Debug: 814 11257 riscv.c:3888 register_get(): [esp32c3] read 0x10a00000 from pmpaddr9 (valid=0)
Debug: 815 11260 esp_riscv.c:321 esp_riscv_start_algorithm(): save pmpaddr10
Debug: 816 11263 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr954
Debug: 817 11267 riscv-013.c:800 execute_abstract_command(): command=0x2203ba; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3ba
Debug: 818 11274 riscv-013.c:1504 register_read_direct(): {0} csr954 = 0x14000000
Debug: 819 11277 riscv.c:3534 riscv_get_register(): [esp32c3] csr954: 14000000
Debug: 820 11280 riscv.c:3888 register_get(): [esp32c3] read 0x14000000 from pmpaddr10 (valid=0)
Debug: 821 11284 esp_riscv.c:321 esp_riscv_start_algorithm(): save pmpaddr11
Debug: 822 11286 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr955
Debug: 823 11291 riscv-013.c:800 execute_abstract_command(): command=0x2203bb; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3bb
Debug: 824 11298 riscv-013.c:1504 register_read_direct(): {0} csr955 = 0x14000800
Debug: 825 11300 riscv.c:3534 riscv_get_register(): [esp32c3] csr955: 14000800
Debug: 826 11303 riscv.c:3888 register_get(): [esp32c3] read 0x14000800 from pmpaddr11 (valid=0)
Debug: 827 11307 esp_riscv.c:321 esp_riscv_start_algorithm(): save pmpaddr12
Debug: 828 11310 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr956
Debug: 829 11314 riscv-013.c:800 execute_abstract_command(): command=0x2203bc; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3bc
Debug: 830 11321 riscv-013.c:1504 register_read_direct(): {0} csr956 = 0x18000000
Debug: 831 11324 riscv.c:3534 riscv_get_register(): [esp32c3] csr956: 18000000
Debug: 832 11327 riscv.c:3888 register_get(): [esp32c3] read 0x18000000 from pmpaddr12 (valid=0)
Debug: 833 11330 esp_riscv.c:321 esp_riscv_start_algorithm(): save pmpaddr13
Debug: 834 11333 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr957
Debug: 835 11336 riscv-013.c:800 execute_abstract_command(): command=0x2203bd; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3bd
Debug: 836 11345 riscv-013.c:1504 register_read_direct(): {0} csr957 = 0x18040000
Debug: 837 11347 riscv.c:3534 riscv_get_register(): [esp32c3] csr957: 18040000
Debug: 838 11350 riscv.c:3888 register_get(): [esp32c3] read 0x18040000 from pmpaddr13 (valid=0)
Debug: 839 11354 esp_riscv.c:321 esp_riscv_start_algorithm(): save pmpaddr14
Debug: 840 11357 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr958
Debug: 841 11361 riscv-013.c:800 execute_abstract_command(): command=0x2203be; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3be
Debug: 842 11368 riscv-013.c:1504 register_read_direct(): {0} csr958 = 0x3fffffff
Debug: 843 11371 riscv.c:3534 riscv_get_register(): [esp32c3] csr958: 3fffffff
Debug: 844 11374 riscv.c:3888 register_get(): [esp32c3] read 0x3fffffff from pmpaddr14 (valid=0)
Debug: 845 11378 esp_riscv.c:321 esp_riscv_start_algorithm(): save pmpaddr15
Debug: 846 11381 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr959
Debug: 847 11384 riscv-013.c:800 execute_abstract_command(): command=0x2203bf; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3bf
Debug: 848 11392 riscv-013.c:1504 register_read_direct(): {0} csr959 = 0x3fffffff
Debug: 849 11394 riscv.c:3534 riscv_get_register(): [esp32c3] csr959: 3fffffff
Debug: 850 11397 riscv.c:3888 register_get(): [esp32c3] read 0x3fffffff from pmpaddr15 (valid=0)
Debug: 851 11401 esp_riscv.c:321 esp_riscv_start_algorithm(): save tselect
Debug: 852 11404 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register tselect
Debug: 853 11408 riscv-013.c:800 execute_abstract_command(): command=0x2207a0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a0
Debug: 854 11415 riscv-013.c:1504 register_read_direct(): {0} tselect = 0x0
Debug: 855 11418 riscv.c:3534 riscv_get_register(): [esp32c3] tselect: 0
Debug: 856 11421 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from tselect (valid=0)
Debug: 857 11424 esp_riscv.c:321 esp_riscv_start_algorithm(): save tdata1
Debug: 858 11427 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register tdata1
Debug: 859 11430 riscv-013.c:800 execute_abstract_command(): command=0x2207a1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a1
Debug: 860 11438 riscv-013.c:1504 register_read_direct(): {0} tdata1 = 0x23e00000
Debug: 861 11441 riscv.c:3534 riscv_get_register(): [esp32c3] tdata1: 23e00000
Debug: 862 11444 riscv.c:3888 register_get(): [esp32c3] read 0x23e00000 from tdata1 (valid=0)
Debug: 863 11448 esp_riscv.c:321 esp_riscv_start_algorithm(): save tdata2
Debug: 864 11450 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register tdata2
Debug: 865 11454 riscv-013.c:800 execute_abstract_command(): command=0x2207a2; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a2
Debug: 866 11460 riscv-013.c:1504 register_read_direct(): {0} tdata2 = 0x0
Debug: 867 11464 riscv.c:3534 riscv_get_register(): [esp32c3] tdata2: 0
Debug: 868 11466 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from tdata2 (valid=0)
Debug: 869 11469 esp_riscv.c:321 esp_riscv_start_algorithm(): save tcontrol
Debug: 870 11472 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr1957
Debug: 871 11476 riscv-013.c:800 execute_abstract_command(): command=0x2207a5; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a5
Debug: 872 11483 riscv-013.c:1504 register_read_direct(): {0} csr1957 = 0x88
Debug: 873 11486 riscv.c:3534 riscv_get_register(): [esp32c3] csr1957: 88
Debug: 874 11489 riscv.c:3888 register_get(): [esp32c3] read 0x00000088 from tcontrol (valid=0)
Debug: 875 11492 esp_riscv.c:321 esp_riscv_start_algorithm(): save dcsr
Debug: 876 11496 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register dcsr
Debug: 877 11499 riscv-013.c:800 execute_abstract_command(): command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0
Debug: 878 11506 riscv-013.c:1504 register_read_direct(): {0} dcsr = 0x400000c3
Debug: 879 11509 riscv.c:3534 riscv_get_register(): [esp32c3] dcsr: 400000c3
Debug: 880 11513 riscv.c:3888 register_get(): [esp32c3] read 0x400000c3 from dcsr (valid=1)
Debug: 881 11517 esp_riscv.c:321 esp_riscv_start_algorithm(): save dpc
Debug: 882 11519 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register dpc
Debug: 883 11523 riscv-013.c:800 execute_abstract_command(): command=0x2207b1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b1
Debug: 884 11530 riscv-013.c:1504 register_read_direct(): {0} dpc = 0x4038aa24
Debug: 885 11533 riscv.c:3534 riscv_get_register(): [esp32c3] dpc: 4038aa24
Debug: 886 11536 riscv.c:3888 register_get(): [esp32c3] read 0x4038aa24 from dpc (valid=1)
Debug: 887 11539 esp_riscv.c:321 esp_riscv_start_algorithm(): save dscratch0
Debug: 888 11543 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register dscratch0
Debug: 889 11547 riscv-013.c:800 execute_abstract_command(): command=0x2207b2; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b2
Debug: 890 11553 riscv-013.c:1504 register_read_direct(): {0} dscratch0 = 0x0
Debug: 891 11557 riscv.c:3534 riscv_get_register(): [esp32c3] dscratch0: 0
Debug: 892 11559 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from dscratch0 (valid=1)
Debug: 893 11562 esp_riscv.c:321 esp_riscv_start_algorithm(): save dscratch1
Debug: 894 11565 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr1971
Debug: 895 11569 riscv-013.c:800 execute_abstract_command(): command=0x2207b3; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b3
Debug: 896 11577 riscv-013.c:1504 register_read_direct(): {0} csr1971 = 0x1
Debug: 897 11580 riscv.c:3534 riscv_get_register(): [esp32c3] csr1971: 1
Debug: 898 11583 riscv.c:3888 register_get(): [esp32c3] read 0x00000001 from dscratch1 (valid=0)
Debug: 899 11586 esp_riscv.c:321 esp_riscv_start_algorithm(): save hpmcounter16
Debug: 900 11590 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr3088
Debug: 901 11593 riscv-013.c:800 execute_abstract_command(): command=0x220c10; access register, size=32, postexec=0, transfer=1, write=0, regno=0xc10
Debug: 902 11600 riscv-013.c:1504 register_read_direct(): {0} csr3088 = 0x3
Debug: 903 11603 riscv.c:3534 riscv_get_register(): [esp32c3] csr3088: 3
Debug: 904 11606 riscv.c:3888 register_get(): [esp32c3] read 0x00000003 from hpmcounter16 (valid=0)
Debug: 905 11610 esp_riscv.c:321 esp_riscv_start_algorithm(): save priv
Debug: 906 11612 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register priv
Debug: 907 11616 riscv-013.c:800 execute_abstract_command(): command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0
Debug: 908 11624 riscv-013.c:1504 register_read_direct(): {0} dcsr = 0x400000c3
Debug: 909 11626 riscv.c:3534 riscv_get_register(): [esp32c3] priv: 3
Debug: 910 11629 riscv.c:3888 register_get(): [esp32c3] read 0x03 from priv (valid=0)
Debug: 911 11632 esp_riscv.c:350 esp_riscv_start_algorithm(): set sp
Debug: 912 11635 riscv.c:3901 register_set(): [esp32c3] write 0x3fc84920 to sp (valid=1)
Debug: 913 11639 riscv.c:3477 riscv_set_register(): [esp32c3] sp <- 3fc84920
Debug: 914 11641 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x3fc84920 to register sp
Debug: 915 11645 riscv-013.c:1315 register_write_direct(): {0} sp <- 0x3fc84920
Debug: 916 11648 riscv-013.c:800 execute_abstract_command(): command=0x231002; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1002
Debug: 917 11655 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x3fc84920 to sp valid=1
Debug: 918 11658 esp_riscv.c:350 esp_riscv_start_algorithm(): set a7
Debug: 919 11661 riscv.c:3901 register_set(): [esp32c3] write 0x403810d2 to a7 (valid=1)
Debug: 920 11664 riscv.c:3477 riscv_set_register(): [esp32c3] a7 <- 403810d2
Debug: 921 11667 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x403810d2 to register a7
Debug: 922 11671 riscv-013.c:1315 register_write_direct(): {0} a7 <- 0x403810d2
Debug: 923 11674 riscv-013.c:800 execute_abstract_command(): command=0x231011; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1011
Debug: 924 11681 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x403810d2 to a7 valid=1
Debug: 925 11685 esp_riscv.c:350 esp_riscv_start_algorithm(): set a0
Debug: 926 11688 riscv.c:3901 register_set(): [esp32c3] write 0x00000005 to a0 (valid=1)
Debug: 927 11691 riscv.c:3477 riscv_set_register(): [esp32c3] a0 <- 5
Debug: 928 11694 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x5 to register a0
Debug: 929 11697 riscv-013.c:1315 register_write_direct(): {0} a0 <- 0x5
Debug: 930 11701 riscv-013.c:800 execute_abstract_command(): command=0x23100a; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100a
Debug: 931 11708 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x5 to a0 valid=1
Debug: 932 11711 esp_riscv.c:350 esp_riscv_start_algorithm(): set a1
Debug: 933 11714 riscv.c:3901 register_set(): [esp32c3] write 0xffffffff to a1 (valid=1)
Debug: 934 11717 riscv.c:3477 riscv_set_register(): [esp32c3] a1 <- ffffffff
Debug: 935 11720 riscv-013.c:4115 riscv013_set_register(): [0] writing 0xffffffff to register a1
Debug: 936 11724 riscv-013.c:1315 register_write_direct(): {0} a1 <- 0xffffffff
Debug: 937 11728 riscv-013.c:800 execute_abstract_command(): command=0x23100b; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100b
Debug: 938 11735 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0xffffffff to a1 valid=1
Debug: 939 11738 esp_riscv.c:350 esp_riscv_start_algorithm(): set a2
Debug: 940 11741 riscv.c:3901 register_set(): [esp32c3] write 0x3fc8493c to a2 (valid=1)
Debug: 941 11744 riscv.c:3477 riscv_set_register(): [esp32c3] a2 <- 3fc8493c
Debug: 942 11747 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x3fc8493c to register a2
Debug: 943 11751 riscv-013.c:1315 register_write_direct(): {0} a2 <- 0x3fc8493c
Debug: 944 11755 riscv-013.c:800 execute_abstract_command(): command=0x23100c; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100c
Debug: 945 11761 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x3fc8493c to a2 valid=1
Debug: 946 11765 riscv.c:3293 riscv_interrupts_disable(): Disabling Interrupts
Debug: 947 11768 riscv.c:3517 riscv_get_register(): [esp32c3] mstatus: 81 (cached)
Debug: 948 11771 riscv.c:3888 register_get(): [esp32c3] read 0x00000081 from mstatus (valid=1)
Debug: 949 11774 riscv.c:3901 register_set(): [esp32c3] write 0x00000080 to mstatus (valid=1)
Debug: 950 11778 riscv.c:3477 riscv_set_register(): [esp32c3] mstatus <- 80
Debug: 951 11781 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x80 to register mstatus
Debug: 952 11785 riscv-013.c:1315 register_write_direct(): {0} mstatus <- 0x80
Debug: 953 11788 riscv-013.c:800 execute_abstract_command(): command=0x230300; access register, size=32, postexec=0, transfer=1, write=1, regno=0x300
Debug: 954 11794 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x80 to mstatus valid=0
Debug: 955 11798 esp_riscv.c:387 esp_riscv_start_algorithm(): resume at 0x40381ce4
Debug: 956 11801 riscv.c:1472 riscv_resume(): handle_breakpoints=0
Debug: 957 11803 riscv.c:1399 resume_prep(): [0]
Debug: 958 11805 riscv.c:3477 riscv_set_register(): [esp32c3] pc <- 40381ce4
Debug: 959 11808 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x40381ce4 to register pc
Debug: 960 11812 riscv-013.c:4120 riscv013_set_register(): [0] writing PC to DPC: 0x40381ce4
Debug: 961 11815 riscv-013.c:1315 register_write_direct(): {0} dpc <- 0x40381ce4
Debug: 962 11819 riscv-013.c:800 execute_abstract_command(): command=0x2307b1; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b1
Debug: 963 11826 riscv-013.c:800 execute_abstract_command(): command=0x2207b1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b1
Debug: 964 11833 riscv-013.c:1504 register_read_direct(): {0} dpc = 0x40381ce4
Debug: 965 11837 riscv-013.c:4124 riscv013_set_register(): [0]   actual DPC written: 0x0000000040381ce4
Debug: 966 11840 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x40381ce4 to pc valid=0
Debug: 967 11845 riscv.c:1289 riscv_resume_prep_all_harts(): [esp32c3] prep hart
Debug: 968 11849 program.c:35 riscv_program_write(): debug_buffer[00] = DASM(0x0000100f)
Debug: 969 11852 program.c:35 riscv_program_write(): debug_buffer[01] = DASM(0x0000000f)
Debug: 970 11856 program.c:35 riscv_program_write(): debug_buffer[02] = DASM(0x00100073)
Debug: 971 11860 riscv-013.c:800 execute_abstract_command(): command=0x241000; access register, size=32, postexec=1, transfer=0, write=0, regno=0x1000
Debug: 972 11865 riscv-013.c:800 execute_abstract_command(): command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0
Debug: 973 11874 riscv-013.c:1504 register_read_direct(): {0} dcsr = 0x400000c3
Debug: 974 11876 riscv.c:3477 riscv_set_register(): [esp32c3] dcsr <- 4000b0c3
Debug: 975 11879 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x4000b0c3 to register dcsr
Debug: 976 11883 riscv-013.c:1315 register_write_direct(): {0} dcsr <- 0x4000b0c3
Debug: 977 11886 riscv-013.c:800 execute_abstract_command(): command=0x2307b0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b0
Debug: 978 11894 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x4000b0c3 to dcsr valid=0
Debug: 979 11897 riscv.c:1300 riscv_resume_prep_all_harts(): [esp32c3] mark as prepped
Debug: 980 11900 riscv.c:1424 resume_prep(): [0] mark as prepped
Debug: 981 11902 riscv.c:3276 riscv_resume_go_all_harts(): [esp32c3] resuming hart
Debug: 982 11907 riscv-013.c:4190 select_prepped_harts(): index=0, coreid=0, prepped=1
Debug: 983 11910 riscv-013.c:4815 riscv013_step_or_resume_current_hart(): resuming hart 0 (for step?=0)
Debug: 984 11916 riscv.c:3397 riscv_invalidate_register_cache(): [0]
Debug: 985 11919 target.c:1860 target_call_event_callbacks(): target event 18 (debug-resumed) for core esp32c3
Debug: 986 11923 esp32c3.c:188 esp32c3_handle_target_event(): 18
Debug: 987 11925 esp_riscv.c:281 esp_riscv_handle_target_event(): 18
Debug: 988 11928 esp_algorithm.c:218 algorithm_run(): Wait algorithm completion
Debug: 989 11931 riscv.c:2078 riscv_poll_hart():   triggered a halt
Debug: 990 11933 riscv.c:2258 riscv_openocd_poll():   hart 0 halted
Debug: 991 11937 riscv-013.c:800 execute_abstract_command(): command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0
Debug: 992 11944 riscv-013.c:1504 register_read_direct(): {0} dcsr = 0x4000b043
Debug: 993 11947 riscv-013.c:4345 riscv013_halt_reason(): dcsr.cause: 0x1
Debug: 994 11951 riscv.c:2113 set_debug_reason(): [esp32c3] debug_reason=1
Debug: 995 11954 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register pc
Debug: 996 11958 riscv-013.c:800 execute_abstract_command(): command=0x2207b1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b1
Debug: 997 11965 riscv-013.c:1504 register_read_direct(): {0} dpc = 0x40381ce6
Debug: 998 11968 riscv-013.c:4095 riscv013_get_register(): [0] read PC from DPC: 0x40381ce6
Debug: 999 11972 riscv.c:3534 riscv_get_register(): [esp32c3] pc: 40381ce6
Debug: 1000 11975 esp_riscv.c:529 esp_riscv_read_memory(): Use 32-bit access: size: 2   count:2 start address: 0x40381ce2
Debug: 1001 11983 riscv-013.c:2858 log_mem_access_result(): Succeeded to read memory via system bus.
Debug: 1002 11987 esp_riscv.c:529 esp_riscv_read_memory(): Use 32-bit access: size: 2   count:2 start address: 0x40381ce6
Debug: 1003 11995 riscv-013.c:2858 log_mem_access_result(): Succeeded to read memory via system bus.
Debug: 1004 11999 esp_riscv.c:529 esp_riscv_read_memory(): Use 32-bit access: size: 2   count:2 start address: 0x40381cea
Debug: 1005 12008 riscv-013.c:2858 log_mem_access_result(): Succeeded to read memory via system bus.
Debug: 1006 12011 riscv_semihosting.c:108 riscv_semihosting(): check 9882bd19 85269002 446240f2 from 0x40381ce6-4
Debug: 1007 12016 riscv_semihosting.c:112 riscv_semihosting():    -> NONE (no magic)
Debug: 1008 12019 target.c:1860 target_call_event_callbacks(): target event 0 (gdb-halt) for core esp32c3
Debug: 1009 12023 esp32c3.c:188 esp32c3_handle_target_event(): 0
Debug: 1010 12025 esp_riscv.c:281 esp_riscv_handle_target_event(): 0
Debug: 1011 12029 target.c:1860 target_call_event_callbacks(): target event 1 (halted) for core esp32c3
Debug: 1012 12032 target.c:5153 target_handle_event(): target(0): esp32c3 (esp32c3) event: 1 (halted) action:
    esp32c3_wdt_disable

Debug: 1013 12038 command.c:166 script_debug(): command - command mode
Debug: 1014 12041 command.c:166 script_debug(): command - mww 0x6001f064 0x50D83AA1
Debug: 1015 12047 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x6001f064
Debug: 1016 12052 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 1017 12055 command.c:166 script_debug(): command - mww 0x6001F048 0
Debug: 1018 12061 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x6001f048
Debug: 1019 12065 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 1020 12069 command.c:166 script_debug(): command - mww 0x60020064 0x50D83AA1
Debug: 1021 12075 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x60020064
Debug: 1022 12079 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 1023 12083 command.c:166 script_debug(): command - mww 0x60020048 0
Debug: 1024 12087 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x60020048
Debug: 1025 12093 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 1026 12096 command.c:166 script_debug(): command - mww 0x600080a8 0x50D83AA1
Debug: 1027 12100 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x600080a8
Debug: 1028 12106 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 1029 12109 command.c:166 script_debug(): command - mww 0x60008090 0
Debug: 1030 12114 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x60008090
Debug: 1031 12118 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 1032 12122 command.c:166 script_debug(): command - mww 0x600080b0 0x8F1D312A
Debug: 1033 12128 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x600080b0
Debug: 1034 12132 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 1035 12136 command.c:166 script_debug(): command - mww 0x600080ac 0x84B00000
Debug: 1036 12142 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x600080ac
Debug: 1037 12147 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 1038 12150 esp32c3.c:188 esp32c3_handle_target_event(): 1
Debug: 1039 12153 esp_riscv.c:281 esp_riscv_handle_target_event(): 1
Debug: 1040 12156 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register pc
Debug: 1041 12159 riscv-013.c:800 execute_abstract_command(): command=0x2207b1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b1
Debug: 1042 12166 riscv-013.c:1504 register_read_direct(): {0} dpc = 0x40381ce6
Debug: 1043 12170 riscv-013.c:4095 riscv013_get_register(): [0] read PC from DPC: 0x40381ce6
Debug: 1044 12173 riscv.c:3534 riscv_get_register(): [esp32c3] pc: 40381ce6
Debug: 1045 12176 riscv.c:3888 register_get(): [esp32c3] read 0x40381ce6 from pc (valid=0)
Debug: 1046 12179 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register a0
Debug: 1047 12183 riscv-013.c:800 execute_abstract_command(): command=0x22100a; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100a
Debug: 1048 12190 riscv-013.c:1504 register_read_direct(): {0} a0 = 0xffffffff
Debug: 1049 12193 riscv.c:3534 riscv_get_register(): [esp32c3] a0: ffffffff
Debug: 1050 12196 riscv.c:3888 register_get(): [esp32c3] read 0xffffffff from a0 (valid=1)
Debug: 1051 12200 esp_riscv.c:465 esp_riscv_wait_algorithm(): Read mem params
Debug: 1052 12203 esp_riscv.c:467 esp_riscv_wait_algorithm(): Check mem param @ 0x3fc8493c
Debug: 1053 12206 esp_riscv.c:469 esp_riscv_wait_algorithm(): Read mem param @ 0x3fc8493c
Debug: 1054 12209 target.c:2536 target_read_buffer(): reading buffer of 28 byte at 0x3fc8493c
Debug: 1055 12218 riscv-013.c:2858 log_mem_access_result(): Succeeded to read memory via system bus.
Debug: 1056 12221 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore ra
Debug: 1057 12224 riscv.c:3901 register_set(): [esp32c3] write 0x4038aa78 to ra (valid=0)
Debug: 1058 12227 riscv.c:3477 riscv_set_register(): [esp32c3] ra <- 4038aa78
Debug: 1059 12230 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x4038aa78 to register ra
Debug: 1060 12234 riscv-013.c:1315 register_write_direct(): {0} ra <- 0x4038aa78
Debug: 1061 12238 riscv-013.c:800 execute_abstract_command(): command=0x231001; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1001
Debug: 1062 12244 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x4038aa78 to ra valid=1
Debug: 1063 12248 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore sp
Debug: 1064 12251 riscv.c:3901 register_set(): [esp32c3] write 0x3fca8080 to sp (valid=0)
Debug: 1065 12254 riscv.c:3477 riscv_set_register(): [esp32c3] sp <- 3fca8080
Debug: 1066 12257 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x3fca8080 to register sp
Debug: 1067 12261 riscv-013.c:1315 register_write_direct(): {0} sp <- 0x3fca8080
Debug: 1068 12265 riscv-013.c:800 execute_abstract_command(): command=0x231002; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1002
Debug: 1069 12272 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x3fca8080 to sp valid=1
Debug: 1070 12275 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore gp
Debug: 1071 12277 riscv.c:3901 register_set(): [esp32c3] write 0x3fc8fc00 to gp (valid=0)
Debug: 1072 12282 riscv.c:3477 riscv_set_register(): [esp32c3] gp <- 3fc8fc00
Debug: 1073 12285 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x3fc8fc00 to register gp
Debug: 1074 12289 riscv-013.c:1315 register_write_direct(): {0} gp <- 0x3fc8fc00
Debug: 1075 12292 riscv-013.c:800 execute_abstract_command(): command=0x231003; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1003
Debug: 1076 12299 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x3fc8fc00 to gp valid=1
Debug: 1077 12303 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore tp
Debug: 1078 12305 riscv.c:3901 register_set(): [esp32c3] write 0x3fc97820 to tp (valid=0)
Debug: 1079 12309 riscv.c:3477 riscv_set_register(): [esp32c3] tp <- 3fc97820
Debug: 1080 12312 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x3fc97820 to register tp
Debug: 1081 12316 riscv-013.c:1315 register_write_direct(): {0} tp <- 0x3fc97820
Debug: 1082 12319 riscv-013.c:800 execute_abstract_command(): command=0x231004; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1004
Debug: 1083 12326 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x3fc97820 to tp valid=1
Debug: 1084 12329 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore t0
Debug: 1085 12332 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to t0 (valid=0)
Debug: 1086 12336 riscv.c:3477 riscv_set_register(): [esp32c3] t0 <- 0
Debug: 1087 12338 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register t0
Debug: 1088 12342 riscv-013.c:1315 register_write_direct(): {0} t0 <- 0x0
Debug: 1089 12346 riscv-013.c:800 execute_abstract_command(): command=0x231005; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1005
Debug: 1090 12352 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to t0 valid=1
Debug: 1091 12355 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore t1
Debug: 1092 12358 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to t1 (valid=0)
Debug: 1093 12362 riscv.c:3477 riscv_set_register(): [esp32c3] t1 <- 0
Debug: 1094 12364 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register t1
Debug: 1095 12368 riscv-013.c:1315 register_write_direct(): {0} t1 <- 0x0
Debug: 1096 12371 riscv-013.c:800 execute_abstract_command(): command=0x231006; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1006
Debug: 1097 12378 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to t1 valid=1
Debug: 1098 12381 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore t2
Debug: 1099 12384 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to t2 (valid=0)
Debug: 1100 12388 riscv.c:3477 riscv_set_register(): [esp32c3] t2 <- 0
Debug: 1101 12391 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register t2
Debug: 1102 12394 riscv-013.c:1315 register_write_direct(): {0} t2 <- 0x0
Debug: 1103 12397 riscv-013.c:800 execute_abstract_command(): command=0x231007; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1007
Debug: 1104 12404 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to t2 valid=1
Debug: 1105 12408 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore fp
Debug: 1106 12410 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to fp (valid=0)
Debug: 1107 12413 riscv.c:3477 riscv_set_register(): [esp32c3] s0 <- 0
Debug: 1108 12416 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register s0
Debug: 1109 12420 riscv-013.c:1315 register_write_direct(): {0} s0 <- 0x0
Debug: 1110 12423 riscv-013.c:800 execute_abstract_command(): command=0x231008; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1008
Debug: 1111 12429 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to fp valid=1
Debug: 1112 12432 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore s1
Debug: 1113 12435 riscv.c:3901 register_set(): [esp32c3] write 0x00000001 to s1 (valid=0)
Debug: 1114 12438 riscv.c:3477 riscv_set_register(): [esp32c3] s1 <- 1
Debug: 1115 12441 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x1 to register s1
Debug: 1116 12444 riscv-013.c:1315 register_write_direct(): {0} s1 <- 0x1
Debug: 1117 12448 riscv-013.c:800 execute_abstract_command(): command=0x231009; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1009
Debug: 1118 12455 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x1 to s1 valid=1
Debug: 1119 12458 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore a0
Debug: 1120 12461 riscv.c:3901 register_set(): [esp32c3] write 0x00000001 to a0 (valid=1)
Debug: 1121 12464 riscv.c:3477 riscv_set_register(): [esp32c3] a0 <- 1
Debug: 1122 12467 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x1 to register a0
Debug: 1123 12470 riscv-013.c:1315 register_write_direct(): {0} a0 <- 0x1
Debug: 1124 12474 riscv-013.c:800 execute_abstract_command(): command=0x23100a; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100a
Debug: 1125 12481 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x1 to a0 valid=1
Debug: 1126 12484 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore a1
Debug: 1127 12487 riscv.c:3901 register_set(): [esp32c3] write 0x3fca809f to a1 (valid=0)
Debug: 1128 12490 riscv.c:3477 riscv_set_register(): [esp32c3] a1 <- 3fca809f
Debug: 1129 12493 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x3fca809f to register a1
Debug: 1130 12498 riscv-013.c:1315 register_write_direct(): {0} a1 <- 0x3fca809f
Debug: 1131 12502 riscv-013.c:800 execute_abstract_command(): command=0x23100b; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100b
Debug: 1132 12509 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x3fca809f to a1 valid=1
Debug: 1133 12512 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore a2
Debug: 1134 12515 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to a2 (valid=0)
Debug: 1135 12517 riscv.c:3477 riscv_set_register(): [esp32c3] a2 <- 0
Debug: 1136 12521 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register a2
Debug: 1137 12524 riscv-013.c:1315 register_write_direct(): {0} a2 <- 0x0
Debug: 1138 12527 riscv-013.c:800 execute_abstract_command(): command=0x23100c; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100c
Debug: 1139 12534 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to a2 valid=1
Debug: 1140 12537 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore a3
Debug: 1141 12540 riscv.c:3901 register_set(): [esp32c3] write 0x00000004 to a3 (valid=0)
Debug: 1142 12543 riscv.c:3477 riscv_set_register(): [esp32c3] a3 <- 4
Debug: 1143 12546 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x4 to register a3
Debug: 1144 12550 riscv-013.c:1315 register_write_direct(): {0} a3 <- 0x4
Debug: 1145 12554 riscv-013.c:800 execute_abstract_command(): command=0x23100d; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100d
Debug: 1146 12561 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x4 to a3 valid=1
Debug: 1147 12564 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore a4
Debug: 1148 12566 riscv.c:3901 register_set(): [esp32c3] write 0x600c2000 to a4 (valid=0)
Debug: 1149 12570 riscv.c:3477 riscv_set_register(): [esp32c3] a4 <- 600c2000
Debug: 1150 12573 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x600c2000 to register a4
Debug: 1151 12577 riscv-013.c:1315 register_write_direct(): {0} a4 <- 0x600c2000
Debug: 1152 12580 riscv-013.c:800 execute_abstract_command(): command=0x23100e; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100e
Debug: 1153 12587 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x600c2000 to a4 valid=1
Debug: 1154 12590 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore a5
Debug: 1155 12593 riscv.c:3901 register_set(): [esp32c3] write 0x00000089 to a5 (valid=0)
Debug: 1156 12596 riscv.c:3477 riscv_set_register(): [esp32c3] a5 <- 89
Debug: 1157 12599 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x89 to register a5
Debug: 1158 12602 riscv-013.c:1315 register_write_direct(): {0} a5 <- 0x89
Debug: 1159 12606 riscv-013.c:800 execute_abstract_command(): command=0x23100f; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100f
Debug: 1160 12613 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x89 to a5 valid=1
Debug: 1161 12616 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore a6
Debug: 1162 12619 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to a6 (valid=0)
Debug: 1163 12623 riscv.c:3477 riscv_set_register(): [esp32c3] a6 <- 0
Debug: 1164 12626 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register a6
Debug: 1165 12629 riscv-013.c:1315 register_write_direct(): {0} a6 <- 0x0
Debug: 1166 12633 riscv-013.c:800 execute_abstract_command(): command=0x231010; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1010
Debug: 1167 12639 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to a6 valid=1
Debug: 1168 12643 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore a7
Debug: 1169 12645 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to a7 (valid=0)
Debug: 1170 12647 riscv.c:3477 riscv_set_register(): [esp32c3] a7 <- 0
Debug: 1171 12650 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register a7
Debug: 1172 12653 riscv-013.c:1315 register_write_direct(): {0} a7 <- 0x0
Debug: 1173 12658 riscv-013.c:800 execute_abstract_command(): command=0x231011; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1011
Debug: 1174 12664 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to a7 valid=1
Debug: 1175 12667 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore s2
Debug: 1176 12671 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to s2 (valid=0)
Debug: 1177 12674 riscv.c:3477 riscv_set_register(): [esp32c3] s2 <- 0
Debug: 1178 12677 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register s2
Debug: 1179 12680 riscv-013.c:1315 register_write_direct(): {0} s2 <- 0x0
Debug: 1180 12684 riscv-013.c:800 execute_abstract_command(): command=0x231012; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1012
Debug: 1181 12692 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to s2 valid=1
Debug: 1182 12694 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore s3
Debug: 1183 12697 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to s3 (valid=0)
Debug: 1184 12700 riscv.c:3477 riscv_set_register(): [esp32c3] s3 <- 0
Debug: 1185 12704 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register s3
Debug: 1186 12707 riscv-013.c:1315 register_write_direct(): {0} s3 <- 0x0
Debug: 1187 12710 riscv-013.c:800 execute_abstract_command(): command=0x231013; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1013
Debug: 1188 12717 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to s3 valid=1
Debug: 1189 12720 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore s4
Debug: 1190 12723 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to s4 (valid=0)
Debug: 1191 12727 riscv.c:3477 riscv_set_register(): [esp32c3] s4 <- 0
Debug: 1192 12729 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register s4
Debug: 1193 12733 riscv-013.c:1315 register_write_direct(): {0} s4 <- 0x0
Debug: 1194 12737 riscv-013.c:800 execute_abstract_command(): command=0x231014; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1014
Debug: 1195 12743 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to s4 valid=1
Debug: 1196 12746 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore s5
Debug: 1197 12749 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to s5 (valid=0)
Debug: 1198 12753 riscv.c:3477 riscv_set_register(): [esp32c3] s5 <- 0
Debug: 1199 12755 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register s5
Debug: 1200 12759 riscv-013.c:1315 register_write_direct(): {0} s5 <- 0x0
Debug: 1201 12762 riscv-013.c:800 execute_abstract_command(): command=0x231015; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1015
Debug: 1202 12769 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to s5 valid=1
Debug: 1203 12772 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore s6
Debug: 1204 12775 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to s6 (valid=0)
Debug: 1205 12778 riscv.c:3477 riscv_set_register(): [esp32c3] s6 <- 0
Debug: 1206 12781 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register s6
Debug: 1207 12785 riscv-013.c:1315 register_write_direct(): {0} s6 <- 0x0
Debug: 1208 12788 riscv-013.c:800 execute_abstract_command(): command=0x231016; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1016
Debug: 1209 12795 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to s6 valid=1
Debug: 1210 12798 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore s7
Debug: 1211 12801 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to s7 (valid=0)
Debug: 1212 12804 riscv.c:3477 riscv_set_register(): [esp32c3] s7 <- 0
Debug: 1213 12807 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register s7
Debug: 1214 12810 riscv-013.c:1315 register_write_direct(): {0} s7 <- 0x0
Debug: 1215 12814 riscv-013.c:800 execute_abstract_command(): command=0x231017; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1017
Debug: 1216 12821 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to s7 valid=1
Debug: 1217 12824 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore s8
Debug: 1218 12827 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to s8 (valid=0)
Debug: 1219 12830 riscv.c:3477 riscv_set_register(): [esp32c3] s8 <- 0
Debug: 1220 12833 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register s8
Debug: 1221 12836 riscv-013.c:1315 register_write_direct(): {0} s8 <- 0x0
Debug: 1222 12840 riscv-013.c:800 execute_abstract_command(): command=0x231018; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1018
Debug: 1223 12847 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to s8 valid=1
Debug: 1224 12850 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore s9
Debug: 1225 12852 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to s9 (valid=0)
Debug: 1226 12856 riscv.c:3477 riscv_set_register(): [esp32c3] s9 <- 0
Debug: 1227 12858 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register s9
Debug: 1228 12863 riscv-013.c:1315 register_write_direct(): {0} s9 <- 0x0
Debug: 1229 12867 riscv-013.c:800 execute_abstract_command(): command=0x231019; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1019
Debug: 1230 12874 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to s9 valid=1
Debug: 1231 12877 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore s10
Debug: 1232 12880 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to s10 (valid=0)
Debug: 1233 12883 riscv.c:3477 riscv_set_register(): [esp32c3] s10 <- 0
Debug: 1234 12886 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register s10
Debug: 1235 12890 riscv-013.c:1315 register_write_direct(): {0} s10 <- 0x0
Debug: 1236 12893 riscv-013.c:800 execute_abstract_command(): command=0x23101a; access register, size=32, postexec=0, transfer=1, write=1, regno=0x101a
Debug: 1237 12900 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to s10 valid=1
Debug: 1238 12903 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore s11
Debug: 1239 12906 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to s11 (valid=0)
Debug: 1240 12909 riscv.c:3477 riscv_set_register(): [esp32c3] s11 <- 0
Debug: 1241 12912 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register s11
Debug: 1242 12915 riscv-013.c:1315 register_write_direct(): {0} s11 <- 0x0
Debug: 1243 12920 riscv-013.c:800 execute_abstract_command(): command=0x23101b; access register, size=32, postexec=0, transfer=1, write=1, regno=0x101b
Debug: 1244 12927 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to s11 valid=1
Debug: 1245 12930 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore t3
Debug: 1246 12933 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to t3 (valid=0)
Debug: 1247 12936 riscv.c:3477 riscv_set_register(): [esp32c3] t3 <- 0
Debug: 1248 12939 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register t3
Debug: 1249 12942 riscv-013.c:1315 register_write_direct(): {0} t3 <- 0x0
Debug: 1250 12946 riscv-013.c:800 execute_abstract_command(): command=0x23101c; access register, size=32, postexec=0, transfer=1, write=1, regno=0x101c
Debug: 1251 12953 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to t3 valid=1
Debug: 1252 12956 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore t4
Debug: 1253 12958 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to t4 (valid=0)
Debug: 1254 12962 riscv.c:3477 riscv_set_register(): [esp32c3] t4 <- 0
Debug: 1255 12964 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register t4
Debug: 1256 12968 riscv-013.c:1315 register_write_direct(): {0} t4 <- 0x0
Debug: 1257 12972 riscv-013.c:800 execute_abstract_command(): command=0x23101d; access register, size=32, postexec=0, transfer=1, write=1, regno=0x101d
Debug: 1258 12978 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to t4 valid=1
Debug: 1259 12981 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore t5
Debug: 1260 12985 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to t5 (valid=0)
Debug: 1261 12988 riscv.c:3477 riscv_set_register(): [esp32c3] t5 <- 0
Debug: 1262 12991 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register t5
Debug: 1263 12994 riscv-013.c:1315 register_write_direct(): {0} t5 <- 0x0
Debug: 1264 12998 riscv-013.c:800 execute_abstract_command(): command=0x23101e; access register, size=32, postexec=0, transfer=1, write=1, regno=0x101e
Debug: 1265 13006 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to t5 valid=1
Debug: 1266 13008 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore t6
Debug: 1267 13011 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to t6 (valid=0)
Debug: 1268 13014 riscv.c:3477 riscv_set_register(): [esp32c3] t6 <- 0
Debug: 1269 13018 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register t6
Debug: 1270 13021 riscv-013.c:1315 register_write_direct(): {0} t6 <- 0x0
Debug: 1271 13024 riscv-013.c:800 execute_abstract_command(): command=0x23101f; access register, size=32, postexec=0, transfer=1, write=1, regno=0x101f
Debug: 1272 13030 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to t6 valid=1
Debug: 1273 13033 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pc
Debug: 1274 13036 riscv.c:3901 register_set(): [esp32c3] write 0x4038aa24 to pc (valid=0)
Debug: 1275 13040 riscv.c:3477 riscv_set_register(): [esp32c3] pc <- 4038aa24
Debug: 1276 13043 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x4038aa24 to register pc
Debug: 1277 13046 riscv-013.c:4120 riscv013_set_register(): [0] writing PC to DPC: 0x4038aa24
Debug: 1278 13051 riscv-013.c:1315 register_write_direct(): {0} dpc <- 0x4038aa24
Debug: 1279 13055 riscv-013.c:800 execute_abstract_command(): command=0x2307b1; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b1
Debug: 1280 13061 riscv-013.c:800 execute_abstract_command(): command=0x2207b1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b1
Debug: 1281 13068 riscv-013.c:1504 register_read_direct(): {0} dpc = 0x4038aa24
Debug: 1282 13072 riscv-013.c:4124 riscv013_set_register(): [0]   actual DPC written: 0x000000004038aa24
Debug: 1283 13076 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x4038aa24 to pc valid=0
Debug: 1284 13080 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore mstatus
Debug: 1285 13082 riscv.c:3901 register_set(): [esp32c3] write 0x00000081 to mstatus (valid=0)
Debug: 1286 13086 riscv.c:3477 riscv_set_register(): [esp32c3] mstatus <- 81
Debug: 1287 13089 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x81 to register mstatus
Debug: 1288 13093 riscv-013.c:1315 register_write_direct(): {0} mstatus <- 0x81
Debug: 1289 13097 riscv-013.c:800 execute_abstract_command(): command=0x230300; access register, size=32, postexec=0, transfer=1, write=1, regno=0x300
Debug: 1290 13103 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x81 to mstatus valid=0
Debug: 1291 13106 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore misa
Debug: 1292 13109 riscv.c:3901 register_set(): [esp32c3] write 0x40101104 to misa (valid=0)
Debug: 1293 13113 riscv.c:3477 riscv_set_register(): [esp32c3] misa <- 40101104
Debug: 1294 13116 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x40101104 to register misa
Debug: 1295 13120 riscv-013.c:1315 register_write_direct(): {0} misa <- 0x40101104
Debug: 1296 13124 riscv-013.c:800 execute_abstract_command(): command=0x230301; access register, size=32, postexec=0, transfer=1, write=1, regno=0x301
Debug: 1297 13131 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x40101104 to misa valid=0
Debug: 1298 13134 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore mtvec
Debug: 1299 13137 riscv.c:3901 register_set(): [esp32c3] write 0x40380001 to mtvec (valid=0)
Debug: 1300 13140 riscv.c:3477 riscv_set_register(): [esp32c3] csr773 <- 40380001
Debug: 1301 13144 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x40380001 to register csr773
Debug: 1302 13147 riscv-013.c:1315 register_write_direct(): {0} csr773 <- 0x40380001
Debug: 1303 13151 riscv-013.c:800 execute_abstract_command(): command=0x230305; access register, size=32, postexec=0, transfer=1, write=1, regno=0x305
Debug: 1304 13159 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x40380001 to mtvec valid=0
Debug: 1305 13162 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore mscratch
Debug: 1306 13165 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to mscratch (valid=0)
Debug: 1307 13168 riscv.c:3477 riscv_set_register(): [esp32c3] csr832 <- 0
Debug: 1308 13170 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register csr832
Debug: 1309 13174 riscv-013.c:1315 register_write_direct(): {0} csr832 <- 0x0
Debug: 1310 13178 riscv-013.c:800 execute_abstract_command(): command=0x230340; access register, size=32, postexec=0, transfer=1, write=1, regno=0x340
Debug: 1311 13184 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to mscratch valid=0
Debug: 1312 13188 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore mepc
Debug: 1313 13191 riscv.c:3901 register_set(): [esp32c3] write 0x4038aaaa to mepc (valid=0)
Debug: 1314 13194 riscv.c:3477 riscv_set_register(): [esp32c3] mepc <- 4038aaaa
Debug: 1315 13197 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x4038aaaa to register mepc
Debug: 1316 13201 riscv-013.c:1315 register_write_direct(): {0} mepc <- 0x4038aaaa
Debug: 1317 13205 riscv-013.c:800 execute_abstract_command(): command=0x230341; access register, size=32, postexec=0, transfer=1, write=1, regno=0x341
Debug: 1318 13212 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x4038aaaa to mepc valid=0
Debug: 1319 13215 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore mcause
Debug: 1320 13218 riscv.c:3901 register_set(): [esp32c3] write 0x80000009 to mcause (valid=0)
Debug: 1321 13222 riscv.c:3477 riscv_set_register(): [esp32c3] mcause <- 80000009
Debug: 1322 13225 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x80000009 to register mcause
Debug: 1323 13229 riscv-013.c:1315 register_write_direct(): {0} mcause <- 0x80000009
Debug: 1324 13233 riscv-013.c:800 execute_abstract_command(): command=0x230342; access register, size=32, postexec=0, transfer=1, write=1, regno=0x342
Debug: 1325 13240 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x80000009 to mcause valid=0
Debug: 1326 13243 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore mtval
Debug: 1327 13246 riscv.c:3901 register_set(): [esp32c3] write 0x00008082 to mtval (valid=0)
Debug: 1328 13249 riscv.c:3477 riscv_set_register(): [esp32c3] csr835 <- 8082
Debug: 1329 13253 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x8082 to register csr835
Debug: 1330 13257 riscv-013.c:1315 register_write_direct(): {0} csr835 <- 0x8082
Debug: 1331 13260 riscv-013.c:800 execute_abstract_command(): command=0x230343; access register, size=32, postexec=0, transfer=1, write=1, regno=0x343
Debug: 1332 13267 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x8082 to mtval valid=0
Debug: 1333 13271 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pmpcfg0
Debug: 1334 13273 riscv.c:3901 register_set(): [esp32c3] write 0x89888f88 to pmpcfg0 (valid=0)
Debug: 1335 13278 riscv.c:3477 riscv_set_register(): [esp32c3] csr928 <- 89888f88
Debug: 1336 13281 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x89888f88 to register csr928
Debug: 1337 13285 riscv-013.c:1315 register_write_direct(): {0} csr928 <- 0x89888f88
Debug: 1338 13288 riscv-013.c:800 execute_abstract_command(): command=0x2303a0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3a0
Debug: 1339 13294 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x89888f88 to pmpcfg0 valid=0
Debug: 1340 13298 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pmpcfg1
Debug: 1341 13302 riscv.c:3901 register_set(): [esp32c3] write 0x888d898b to pmpcfg1 (valid=0)
Debug: 1342 13305 riscv.c:3477 riscv_set_register(): [esp32c3] csr929 <- 888d898b
Debug: 1343 13309 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x888d898b to register csr929
Debug: 1344 13312 riscv-013.c:1315 register_write_direct(): {0} csr929 <- 0x888d898b
Debug: 1345 13317 riscv-013.c:800 execute_abstract_command(): command=0x2303a1; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3a1
Debug: 1346 13323 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x888d898b to pmpcfg1 valid=0
Debug: 1347 13327 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pmpcfg2
Debug: 1348 13329 riscv.c:3901 register_set(): [esp32c3] write 0x8f888d8f to pmpcfg2 (valid=0)
Debug: 1349 13334 riscv.c:3477 riscv_set_register(): [esp32c3] csr930 <- 8f888d8f
Debug: 1350 13337 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x8f888d8f to register csr930
Debug: 1351 13341 riscv-013.c:1315 register_write_direct(): {0} csr930 <- 0x8f888d8f
Debug: 1352 13344 riscv-013.c:800 execute_abstract_command(): command=0x2303a2; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3a2
Debug: 1353 13352 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x8f888d8f to pmpcfg2 valid=0
Debug: 1354 13356 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pmpcfg3
Debug: 1355 13359 riscv.c:3901 register_set(): [esp32c3] write 0x90888b88 to pmpcfg3 (valid=0)
Debug: 1356 13362 riscv.c:3477 riscv_set_register(): [esp32c3] csr931 <- 90888b88
Debug: 1357 13365 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x90888b88 to register csr931
Debug: 1358 13368 riscv-013.c:1315 register_write_direct(): {0} csr931 <- 0x90888b88
Debug: 1359 13372 riscv-013.c:800 execute_abstract_command(): command=0x2303a3; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3a3
Debug: 1360 13381 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x90888b88 to pmpcfg3 valid=0
Debug: 1361 13384 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pmpaddr0
Debug: 1362 13387 riscv.c:3901 register_set(): [esp32c3] write 0x08000000 to pmpaddr0 (valid=0)
Debug: 1363 13391 riscv.c:3477 riscv_set_register(): [esp32c3] csr944 <- 8000000
Debug: 1364 13394 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x8000000 to register csr944
Debug: 1365 13398 riscv-013.c:1315 register_write_direct(): {0} csr944 <- 0x8000000
Debug: 1366 13402 riscv-013.c:800 execute_abstract_command(): command=0x2303b0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b0
Debug: 1367 13408 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x8000000 to pmpaddr0 valid=0
Debug: 1368 13412 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pmpaddr1
Debug: 1369 13415 riscv.c:3901 register_set(): [esp32c3] write 0x0a000000 to pmpaddr1 (valid=0)
Debug: 1370 13418 riscv.c:3477 riscv_set_register(): [esp32c3] csr945 <- a000000
Debug: 1371 13421 riscv-013.c:4115 riscv013_set_register(): [0] writing 0xa000000 to register csr945
Debug: 1372 13425 riscv-013.c:1315 register_write_direct(): {0} csr945 <- 0xa000000
Debug: 1373 13429 riscv-013.c:800 execute_abstract_command(): command=0x2303b1; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b1
Debug: 1374 13436 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0xa000000 to pmpaddr1 valid=0
Debug: 1375 13439 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pmpaddr2
Debug: 1376 13443 riscv.c:3901 register_set(): [esp32c3] write 0x0f000000 to pmpaddr2 (valid=0)
Debug: 1377 13446 riscv.c:3477 riscv_set_register(): [esp32c3] csr946 <- f000000
Debug: 1378 13449 riscv-013.c:4115 riscv013_set_register(): [0] writing 0xf000000 to register csr946
Debug: 1379 13453 riscv-013.c:1315 register_write_direct(): {0} csr946 <- 0xf000000
Debug: 1380 13457 riscv-013.c:800 execute_abstract_command(): command=0x2303b2; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b2
Debug: 1381 13462 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0xf000000 to pmpaddr2 valid=0
Debug: 1382 13466 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pmpaddr3
Debug: 1383 13469 riscv.c:3901 register_set(): [esp32c3] write 0x0ff20000 to pmpaddr3 (valid=0)
Debug: 1384 13473 riscv.c:3477 riscv_set_register(): [esp32c3] csr947 <- ff20000
Debug: 1385 13476 riscv-013.c:4115 riscv013_set_register(): [0] writing 0xff20000 to register csr947
Debug: 1386 13479 riscv-013.c:1315 register_write_direct(): {0} csr947 <- 0xff20000
Debug: 1387 13483 riscv-013.c:800 execute_abstract_command(): command=0x2303b3; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b3
Debug: 1388 13490 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0xff20000 to pmpaddr3 valid=0
Debug: 1389 13494 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pmpaddr4
Debug: 1390 13496 riscv.c:3901 register_set(): [esp32c3] write 0x0ff38000 to pmpaddr4 (valid=0)
Debug: 1391 13500 riscv.c:3477 riscv_set_register(): [esp32c3] csr948 <- ff38000
Debug: 1392 13503 riscv-013.c:4115 riscv013_set_register(): [0] writing 0xff38000 to register csr948
Debug: 1393 13507 riscv-013.c:1315 register_write_direct(): {0} csr948 <- 0xff38000
Debug: 1394 13511 riscv-013.c:800 execute_abstract_command(): command=0x2303b4; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b4
Debug: 1395 13517 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0xff38000 to pmpaddr4 valid=0
Debug: 1396 13521 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pmpaddr5
Debug: 1397 13524 riscv.c:3901 register_set(): [esp32c3] write 0x0ffc8000 to pmpaddr5 (valid=0)
Debug: 1398 13528 riscv.c:3477 riscv_set_register(): [esp32c3] csr949 <- ffc8000
Debug: 1399 13531 riscv-013.c:4115 riscv013_set_register(): [0] writing 0xffc8000 to register csr949
Debug: 1400 13535 riscv-013.c:1315 register_write_direct(): {0} csr949 <- 0xffc8000
Debug: 1401 13539 riscv-013.c:800 execute_abstract_command(): command=0x2303b5; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b5
Debug: 1402 13545 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0xffc8000 to pmpaddr5 valid=0
Debug: 1403 13548 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pmpaddr6
Debug: 1404 13552 riscv.c:3901 register_set(): [esp32c3] write 0x10018000 to pmpaddr6 (valid=0)
Debug: 1405 13555 riscv.c:3477 riscv_set_register(): [esp32c3] csr950 <- 10018000
Debug: 1406 13559 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x10018000 to register csr950
Debug: 1407 13562 riscv-013.c:1315 register_write_direct(): {0} csr950 <- 0x10018000
Debug: 1408 13566 riscv-013.c:800 execute_abstract_command(): command=0x2303b6; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b6
Debug: 1409 13573 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x10018000 to pmpaddr6 valid=0
Debug: 1410 13576 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pmpaddr7
Debug: 1411 13579 riscv.c:3901 register_set(): [esp32c3] write 0x100df000 to pmpaddr7 (valid=0)
Debug: 1412 13583 riscv.c:3477 riscv_set_register(): [esp32c3] csr951 <- 100df000
Debug: 1413 13586 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x100df000 to register csr951
Debug: 1414 13590 riscv-013.c:1315 register_write_direct(): {0} csr951 <- 0x100df000
Debug: 1415 13594 riscv-013.c:800 execute_abstract_command(): command=0x2303b7; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b7
Debug: 1416 13601 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x100df000 to pmpaddr7 valid=0
Debug: 1417 13605 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pmpaddr8
Debug: 1418 13608 riscv.c:3901 register_set(): [esp32c3] write 0x100f8000 to pmpaddr8 (valid=0)
Debug: 1419 13611 riscv.c:3477 riscv_set_register(): [esp32c3] csr952 <- 100f8000
Debug: 1420 13615 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x100f8000 to register csr952
Debug: 1421 13618 riscv-013.c:1315 register_write_direct(): {0} csr952 <- 0x100f8000
Debug: 1422 13622 riscv-013.c:800 execute_abstract_command(): command=0x2303b8; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b8
Debug: 1423 13629 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x100f8000 to pmpaddr8 valid=0
Debug: 1424 13633 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pmpaddr9
Debug: 1425 13636 riscv.c:3901 register_set(): [esp32c3] write 0x10a00000 to pmpaddr9 (valid=0)
Debug: 1426 13639 riscv.c:3477 riscv_set_register(): [esp32c3] csr953 <- 10a00000
Debug: 1427 13642 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x10a00000 to register csr953
Debug: 1428 13646 riscv-013.c:1315 register_write_direct(): {0} csr953 <- 0x10a00000
Debug: 1429 13650 riscv-013.c:800 execute_abstract_command(): command=0x2303b9; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b9
Debug: 1430 13657 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x10a00000 to pmpaddr9 valid=0
Debug: 1431 13660 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pmpaddr10
Debug: 1432 13663 riscv.c:3901 register_set(): [esp32c3] write 0x14000000 to pmpaddr10 (valid=0)
Debug: 1433 13667 riscv.c:3477 riscv_set_register(): [esp32c3] csr954 <- 14000000
Debug: 1434 13670 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x14000000 to register csr954
Debug: 1435 13674 riscv-013.c:1315 register_write_direct(): {0} csr954 <- 0x14000000
Debug: 1436 13678 riscv-013.c:800 execute_abstract_command(): command=0x2303ba; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3ba
Debug: 1437 13684 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x14000000 to pmpaddr10 valid=0
Debug: 1438 13688 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pmpaddr11
Debug: 1439 13690 riscv.c:3901 register_set(): [esp32c3] write 0x14000800 to pmpaddr11 (valid=0)
Debug: 1440 13694 riscv.c:3477 riscv_set_register(): [esp32c3] csr955 <- 14000800
Debug: 1441 13697 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x14000800 to register csr955
Debug: 1442 13701 riscv-013.c:1315 register_write_direct(): {0} csr955 <- 0x14000800
Debug: 1443 13705 riscv-013.c:800 execute_abstract_command(): command=0x2303bb; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3bb
Debug: 1444 13712 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x14000800 to pmpaddr11 valid=0
Debug: 1445 13715 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pmpaddr12
Debug: 1446 13719 riscv.c:3901 register_set(): [esp32c3] write 0x18000000 to pmpaddr12 (valid=0)
Debug: 1447 13722 riscv.c:3477 riscv_set_register(): [esp32c3] csr956 <- 18000000
Debug: 1448 13726 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x18000000 to register csr956
Debug: 1449 13729 riscv-013.c:1315 register_write_direct(): {0} csr956 <- 0x18000000
Debug: 1450 13733 riscv-013.c:800 execute_abstract_command(): command=0x2303bc; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3bc
Debug: 1451 13740 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x18000000 to pmpaddr12 valid=0
Debug: 1452 13744 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pmpaddr13
Debug: 1453 13747 riscv.c:3901 register_set(): [esp32c3] write 0x18040000 to pmpaddr13 (valid=0)
Debug: 1454 13750 riscv.c:3477 riscv_set_register(): [esp32c3] csr957 <- 18040000
Debug: 1455 13753 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x18040000 to register csr957
Debug: 1456 13758 riscv-013.c:1315 register_write_direct(): {0} csr957 <- 0x18040000
Debug: 1457 13762 riscv-013.c:800 execute_abstract_command(): command=0x2303bd; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3bd
Debug: 1458 13768 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x18040000 to pmpaddr13 valid=0
Debug: 1459 13772 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pmpaddr14
Debug: 1460 13775 riscv.c:3901 register_set(): [esp32c3] write 0x3fffffff to pmpaddr14 (valid=0)
Debug: 1461 13779 riscv.c:3477 riscv_set_register(): [esp32c3] csr958 <- 3fffffff
Debug: 1462 13782 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x3fffffff to register csr958
Debug: 1463 13785 riscv-013.c:1315 register_write_direct(): {0} csr958 <- 0x3fffffff
Debug: 1464 13790 riscv-013.c:800 execute_abstract_command(): command=0x2303be; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3be
Debug: 1465 13796 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x3fffffff to pmpaddr14 valid=0
Debug: 1466 13800 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pmpaddr15
Debug: 1467 13803 riscv.c:3901 register_set(): [esp32c3] write 0x3fffffff to pmpaddr15 (valid=0)
Debug: 1468 13807 riscv.c:3477 riscv_set_register(): [esp32c3] csr959 <- 3fffffff
Debug: 1469 13810 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x3fffffff to register csr959
Debug: 1470 13814 riscv-013.c:1315 register_write_direct(): {0} csr959 <- 0x3fffffff
Debug: 1471 13817 riscv-013.c:800 execute_abstract_command(): command=0x2303bf; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3bf
Debug: 1472 13825 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x3fffffff to pmpaddr15 valid=0
Debug: 1473 13829 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore tselect
Debug: 1474 13832 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to tselect (valid=0)
Debug: 1475 13836 riscv.c:3477 riscv_set_register(): [esp32c3] tselect <- 0
Debug: 1476 13839 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register tselect
Debug: 1477 13842 riscv-013.c:1315 register_write_direct(): {0} tselect <- 0x0
Debug: 1478 13846 riscv-013.c:800 execute_abstract_command(): command=0x2307a0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a0
Debug: 1479 13853 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to tselect valid=0
Debug: 1480 13856 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore tdata1
Debug: 1481 13859 riscv.c:3901 register_set(): [esp32c3] write 0x23e00000 to tdata1 (valid=0)
Debug: 1482 13862 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register tselect
Debug: 1483 13866 riscv-013.c:800 execute_abstract_command(): command=0x2207a0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a0
Debug: 1484 13874 riscv-013.c:1504 register_read_direct(): {0} tselect = 0x0
Debug: 1485 13876 riscv.c:3534 riscv_get_register(): [esp32c3] tselect: 0
Debug: 1486 13879 riscv.c:3477 riscv_set_register(): [esp32c3] tselect <- 0
Debug: 1487 13882 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register tselect
Debug: 1488 13886 riscv-013.c:1315 register_write_direct(): {0} tselect <- 0x0
Debug: 1489 13890 riscv-013.c:800 execute_abstract_command(): command=0x2307a0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a0
Debug: 1490 13896 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to tselect valid=0
Debug: 1491 13900 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register tselect
Debug: 1492 13903 riscv-013.c:800 execute_abstract_command(): command=0x2207a0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a0
Debug: 1493 13911 riscv-013.c:1504 register_read_direct(): {0} tselect = 0x0
Debug: 1494 13913 riscv.c:3534 riscv_get_register(): [esp32c3] tselect: 0
Debug: 1495 13916 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register tdata1
Debug: 1496 13920 riscv-013.c:800 execute_abstract_command(): command=0x2207a1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a1
Debug: 1497 13927 riscv-013.c:1504 register_read_direct(): {0} tdata1 = 0x23e00000
Debug: 1498 13931 riscv.c:3534 riscv_get_register(): [esp32c3] tdata1: 23e00000
Debug: 1499 13934 riscv.c:3477 riscv_set_register(): [esp32c3] tselect <- 1
Debug: 1500 13936 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x1 to register tselect
Debug: 1501 13940 riscv-013.c:1315 register_write_direct(): {0} tselect <- 0x1
Debug: 1502 13944 riscv-013.c:800 execute_abstract_command(): command=0x2307a0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a0
Debug: 1503 13951 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x1 to tselect valid=0
Debug: 1504 13954 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register tselect
Debug: 1505 13958 riscv-013.c:800 execute_abstract_command(): command=0x2207a0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a0
Debug: 1506 13965 riscv-013.c:1504 register_read_direct(): {0} tselect = 0x1
Debug: 1507 13968 riscv.c:3534 riscv_get_register(): [esp32c3] tselect: 1
Debug: 1508 13971 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register tdata1
Debug: 1509 13974 riscv-013.c:800 execute_abstract_command(): command=0x2207a1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a1
Debug: 1510 13982 riscv-013.c:1504 register_read_direct(): {0} tdata1 = 0x23e00000
Debug: 1511 13985 riscv.c:3534 riscv_get_register(): [esp32c3] tdata1: 23e00000
Debug: 1512 13988 riscv.c:3477 riscv_set_register(): [esp32c3] tselect <- 2
Debug: 1513 13991 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x2 to register tselect
Debug: 1514 13995 riscv-013.c:1315 register_write_direct(): {0} tselect <- 0x2
Debug: 1515 13999 riscv-013.c:800 execute_abstract_command(): command=0x2307a0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a0
Debug: 1516 14005 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x2 to tselect valid=0
Debug: 1517 14009 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register tselect
Debug: 1518 14013 riscv-013.c:800 execute_abstract_command(): command=0x2207a0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a0
Debug: 1519 14020 riscv-013.c:1504 register_read_direct(): {0} tselect = 0x2
Debug: 1520 14022 riscv.c:3534 riscv_get_register(): [esp32c3] tselect: 2
Debug: 1521 14025 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register tdata1
Debug: 1522 14028 riscv-013.c:800 execute_abstract_command(): command=0x2207a1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a1
Debug: 1523 14036 riscv-013.c:1504 register_read_direct(): {0} tdata1 = 0x23e00000
Debug: 1524 14038 riscv.c:3534 riscv_get_register(): [esp32c3] tdata1: 23e00000
Debug: 1525 14043 riscv.c:3477 riscv_set_register(): [esp32c3] tselect <- 3
Debug: 1526 14046 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x3 to register tselect
Debug: 1527 14049 riscv-013.c:1315 register_write_direct(): {0} tselect <- 0x3
Debug: 1528 14053 riscv-013.c:800 execute_abstract_command(): command=0x2307a0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a0
Debug: 1529 14060 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x3 to tselect valid=0
Debug: 1530 14063 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register tselect
Debug: 1531 14066 riscv-013.c:800 execute_abstract_command(): command=0x2207a0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a0
Debug: 1532 14074 riscv-013.c:1504 register_read_direct(): {0} tselect = 0x3
Debug: 1533 14076 riscv.c:3534 riscv_get_register(): [esp32c3] tselect: 3
Debug: 1534 14079 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register tdata1
Debug: 1535 14083 riscv-013.c:800 execute_abstract_command(): command=0x2207a1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a1
Debug: 1536 14090 riscv-013.c:1504 register_read_direct(): {0} tdata1 = 0x23e00000
Debug: 1537 14093 riscv.c:3534 riscv_get_register(): [esp32c3] tdata1: 23e00000
Debug: 1538 14096 riscv.c:3477 riscv_set_register(): [esp32c3] tselect <- 4
Debug: 1539 14099 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x4 to register tselect
Debug: 1540 14103 riscv-013.c:1315 register_write_direct(): {0} tselect <- 0x4
Debug: 1541 14107 riscv-013.c:800 execute_abstract_command(): command=0x2307a0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a0
Debug: 1542 14114 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x4 to tselect valid=0
Debug: 1543 14117 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register tselect
Debug: 1544 14121 riscv-013.c:800 execute_abstract_command(): command=0x2207a0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a0
Debug: 1545 14128 riscv-013.c:1504 register_read_direct(): {0} tselect = 0x4
Debug: 1546 14131 riscv.c:3534 riscv_get_register(): [esp32c3] tselect: 4
Debug: 1547 14134 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register tdata1
Debug: 1548 14138 riscv-013.c:800 execute_abstract_command(): command=0x2207a1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a1
Debug: 1549 14145 riscv-013.c:1504 register_read_direct(): {0} tdata1 = 0x23e00000
Debug: 1550 14148 riscv.c:3534 riscv_get_register(): [esp32c3] tdata1: 23e00000
Debug: 1551 14151 riscv.c:3477 riscv_set_register(): [esp32c3] tselect <- 5
Debug: 1552 14154 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x5 to register tselect
Debug: 1553 14158 riscv-013.c:1315 register_write_direct(): {0} tselect <- 0x5
Debug: 1554 14161 riscv-013.c:800 execute_abstract_command(): command=0x2307a0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a0
Debug: 1555 14168 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x5 to tselect valid=0
Debug: 1556 14172 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register tselect
Debug: 1557 14175 riscv-013.c:800 execute_abstract_command(): command=0x2207a0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a0
Debug: 1558 14183 riscv-013.c:1504 register_read_direct(): {0} tselect = 0x5
Debug: 1559 14185 riscv.c:3534 riscv_get_register(): [esp32c3] tselect: 5
Debug: 1560 14188 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register tdata1
Debug: 1561 14191 riscv-013.c:800 execute_abstract_command(): command=0x2207a1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a1
Debug: 1562 14199 riscv-013.c:1504 register_read_direct(): {0} tdata1 = 0x23e00000
Debug: 1563 14202 riscv.c:3534 riscv_get_register(): [esp32c3] tdata1: 23e00000
Debug: 1564 14205 riscv.c:3477 riscv_set_register(): [esp32c3] tselect <- 6
Debug: 1565 14208 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x6 to register tselect
Debug: 1566 14212 riscv-013.c:1315 register_write_direct(): {0} tselect <- 0x6
Debug: 1567 14216 riscv-013.c:800 execute_abstract_command(): command=0x2307a0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a0
Debug: 1568 14222 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x6 to tselect valid=0
Debug: 1569 14226 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register tselect
Debug: 1570 14229 riscv-013.c:800 execute_abstract_command(): command=0x2207a0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a0
Debug: 1571 14237 riscv-013.c:1504 register_read_direct(): {0} tselect = 0x6
Debug: 1572 14239 riscv.c:3534 riscv_get_register(): [esp32c3] tselect: 6
Debug: 1573 14242 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register tdata1
Debug: 1574 14246 riscv-013.c:800 execute_abstract_command(): command=0x2207a1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a1
Debug: 1575 14253 riscv-013.c:1504 register_read_direct(): {0} tdata1 = 0x23e00000
Debug: 1576 14256 riscv.c:3534 riscv_get_register(): [esp32c3] tdata1: 23e00000
Debug: 1577 14259 riscv.c:3477 riscv_set_register(): [esp32c3] tselect <- 7
Debug: 1578 14263 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x7 to register tselect
Debug: 1579 14266 riscv-013.c:1315 register_write_direct(): {0} tselect <- 0x7
Debug: 1580 14270 riscv-013.c:800 execute_abstract_command(): command=0x2307a0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a0
Debug: 1581 14277 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x7 to tselect valid=0
Debug: 1582 14280 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register tselect
Debug: 1583 14284 riscv-013.c:800 execute_abstract_command(): command=0x2207a0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a0
Debug: 1584 14291 riscv-013.c:1504 register_read_direct(): {0} tselect = 0x7
Debug: 1585 14295 riscv.c:3534 riscv_get_register(): [esp32c3] tselect: 7
Debug: 1586 14297 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register tdata1
Debug: 1587 14301 riscv-013.c:800 execute_abstract_command(): command=0x2207a1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a1
Debug: 1588 14308 riscv-013.c:1504 register_read_direct(): {0} tdata1 = 0x23e00000
Debug: 1589 14312 riscv.c:3534 riscv_get_register(): [esp32c3] tdata1: 23e00000
Debug: 1590 14314 riscv.c:3477 riscv_set_register(): [esp32c3] tselect <- 8
Debug: 1591 14317 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x8 to register tselect
Debug: 1592 14321 riscv-013.c:1315 register_write_direct(): {0} tselect <- 0x8
Debug: 1593 14325 riscv-013.c:800 execute_abstract_command(): command=0x2307a0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a0
Debug: 1594 14332 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x8 to tselect valid=0
Debug: 1595 14335 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register tselect
Debug: 1596 14339 riscv-013.c:800 execute_abstract_command(): command=0x2207a0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a0
Debug: 1597 14346 riscv-013.c:1504 register_read_direct(): {0} tselect = 0x7
Debug: 1598 14350 riscv.c:3534 riscv_get_register(): [esp32c3] tselect: 7
Debug: 1599 14353 riscv.c:3477 riscv_set_register(): [esp32c3] tselect <- 0
Debug: 1600 14355 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register tselect
Debug: 1601 14359 riscv-013.c:1315 register_write_direct(): {0} tselect <- 0x0
Debug: 1602 14363 riscv-013.c:800 execute_abstract_command(): command=0x2307a0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a0
Debug: 1603 14370 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to tselect valid=0
Info : 1604 14374 riscv.c:3676 riscv_enumerate_triggers(): [esp32c3] Found 8 triggers
Debug: 1605 14377 riscv.c:3477 riscv_set_register(): [esp32c3] tdata1 <- 23e00000
Debug: 1606 14380 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x23e00000 to register tdata1
Debug: 1607 14384 riscv-013.c:1315 register_write_direct(): {0} tdata1 <- 0x23e00000
Debug: 1608 14388 riscv-013.c:800 execute_abstract_command(): command=0x2307a1; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a1
Debug: 1609 14395 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x23e00000 to tdata1 valid=0
Debug: 1610 14398 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore tdata2
Debug: 1611 14401 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to tdata2 (valid=0)
Debug: 1612 14405 riscv.c:3477 riscv_set_register(): [esp32c3] tdata2 <- 0
Debug: 1613 14408 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register tdata2
Debug: 1614 14411 riscv-013.c:1315 register_write_direct(): {0} tdata2 <- 0x0
Debug: 1615 14415 riscv-013.c:800 execute_abstract_command(): command=0x2307a2; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a2
Debug: 1616 14422 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to tdata2 valid=0
Debug: 1617 14425 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore tcontrol
Debug: 1618 14428 riscv.c:3901 register_set(): [esp32c3] write 0x00000088 to tcontrol (valid=0)
Debug: 1619 14432 riscv.c:3477 riscv_set_register(): [esp32c3] csr1957 <- 88
Debug: 1620 14435 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x88 to register csr1957
Debug: 1621 14439 riscv-013.c:1315 register_write_direct(): {0} csr1957 <- 0x88
Debug: 1622 14443 riscv-013.c:800 execute_abstract_command(): command=0x2307a5; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a5
Debug: 1623 14449 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x88 to tcontrol valid=0
Debug: 1624 14453 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore dcsr
Debug: 1625 14456 riscv.c:3901 register_set(): [esp32c3] write 0x400000c3 to dcsr (valid=0)
Debug: 1626 14459 riscv.c:3477 riscv_set_register(): [esp32c3] dcsr <- 400000c3
Debug: 1627 14462 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x400000c3 to register dcsr
Debug: 1628 14466 riscv-013.c:1315 register_write_direct(): {0} dcsr <- 0x400000c3
Debug: 1629 14470 riscv-013.c:800 execute_abstract_command(): command=0x2307b0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b0
Debug: 1630 14477 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x400000c3 to dcsr valid=0
Debug: 1631 14480 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore dpc
Debug: 1632 14483 riscv.c:3901 register_set(): [esp32c3] write 0x4038aa24 to dpc (valid=0)
Debug: 1633 14487 riscv.c:3477 riscv_set_register(): [esp32c3] dpc <- 4038aa24
Debug: 1634 14490 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x4038aa24 to register dpc
Debug: 1635 14492 riscv-013.c:1315 register_write_direct(): {0} dpc <- 0x4038aa24
Debug: 1636 14496 riscv-013.c:800 execute_abstract_command(): command=0x2307b1; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b1
Debug: 1637 14505 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x4038aa24 to dpc valid=1
Debug: 1638 14509 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore dscratch0
Debug: 1639 14513 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to dscratch0 (valid=0)
Debug: 1640 14517 riscv.c:3477 riscv_set_register(): [esp32c3] dscratch0 <- 0
Debug: 1641 14520 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register dscratch0
Debug: 1642 14524 riscv-013.c:1315 register_write_direct(): {0} dscratch0 <- 0x0
Debug: 1643 14527 riscv-013.c:800 execute_abstract_command(): command=0x2307b2; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b2
Debug: 1644 14535 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to dscratch0 valid=0
Debug: 1645 14538 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore dscratch1
Debug: 1646 14541 riscv.c:3901 register_set(): [esp32c3] write 0x00000001 to dscratch1 (valid=0)
Debug: 1647 14545 riscv.c:3477 riscv_set_register(): [esp32c3] csr1971 <- 1
Debug: 1648 14548 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x1 to register csr1971
Debug: 1649 14551 riscv-013.c:1315 register_write_direct(): {0} csr1971 <- 0x1
Debug: 1650 14555 riscv-013.c:800 execute_abstract_command(): command=0x2307b3; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b3
Debug: 1651 14562 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x1 to dscratch1 valid=0
Debug: 1652 14565 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore hpmcounter16
Debug: 1653 14569 riscv.c:3901 register_set(): [esp32c3] write 0x00000003 to hpmcounter16 (valid=0)
Debug: 1654 14573 riscv.c:3477 riscv_set_register(): [esp32c3] csr3088 <- 3
Debug: 1655 14575 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x3 to register csr3088
Debug: 1656 14579 riscv-013.c:1315 register_write_direct(): {0} csr3088 <- 0x3
Debug: 1657 14583 riscv-013.c:800 execute_abstract_command(): command=0x230c10; access register, size=32, postexec=0, transfer=1, write=1, regno=0xc10
Debug: 1658 14590 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x3 to hpmcounter16 valid=0
Debug: 1659 14593 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore priv
Debug: 1660 14596 riscv.c:3901 register_set(): [esp32c3] write 0x03 to priv (valid=0)
Debug: 1661 14599 riscv.c:3477 riscv_set_register(): [esp32c3] priv <- 3
Debug: 1662 14602 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x3 to register priv
Debug: 1663 14606 riscv-013.c:800 execute_abstract_command(): command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0
Debug: 1664 14613 riscv-013.c:1504 register_read_direct(): {0} dcsr = 0x400000c3
Debug: 1665 14616 riscv-013.c:1315 register_write_direct(): {0} dcsr <- 0x400000c3
Debug: 1666 14620 riscv-013.c:800 execute_abstract_command(): command=0x2307b0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b0
Debug: 1667 14627 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x3 to priv valid=0
Debug: 1668 14630 esp_algorithm.c:246 algorithm_run(): Got algorithm RC 0xffffffff
Debug: 1669 14634 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x3fc8493c
Debug: 1670 14638 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 1671 14643 target.c:2206 target_free_working_area_restore(): freed 28 bytes of working area at address 0x3fc8493c
Debug: 1672 14647 target.c:1986 print_wa_layout(): b* 0x3fc84000-0x3fc84427 (1064 bytes)
Debug: 1673 14651 target.c:1986 print_wa_layout(): b* 0x3fc84428-0x3fc8493b (1300 bytes)
Debug: 1674 14654 target.c:1986 print_wa_layout():    0x3fc8493c-0x3fca3fff (128708 bytes)
Debug: 1675 14661 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381ce4
Debug: 1676 14666 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 1677 14669 target.c:2206 target_free_working_area_restore(): freed 4 bytes of working area at address 0x40381ce4
Debug: 1678 14674 target.c:1986 print_wa_layout(): b* 0x40380000-0x40381ce3 (7396 bytes)
Debug: 1679 14677 target.c:1986 print_wa_layout():    0x40381ce4-0x40383fff (8988 bytes)
Debug: 1680 14682 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x3fc84428
Debug: 1681 14692 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x3fc84628
Debug: 1682 14703 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x3fc84828
Debug: 1683 14711 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 1684 14714 target.c:2206 target_free_working_area_restore(): freed 1300 bytes of working area at address 0x3fc84428
Debug: 1685 14719 target.c:1986 print_wa_layout(): b* 0x3fc84000-0x3fc84427 (1064 bytes)
Debug: 1686 14723 target.c:1986 print_wa_layout():    0x3fc84428-0x3fca3fff (130008 bytes)
Debug: 1687 14727 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380000
Debug: 1688 14737 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380200
Debug: 1689 14747 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380400
Debug: 1690 14757 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380600
Debug: 1691 14768 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380800
Debug: 1692 14778 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380a00
Debug: 1693 14788 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380c00
Debug: 1694 14798 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380e00
Debug: 1695 14809 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381000
Debug: 1696 14821 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381200
Debug: 1697 14831 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381400
Debug: 1698 14843 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381600
Debug: 1699 14855 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381800
Debug: 1700 14867 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381a00
Debug: 1701 14878 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381c00
Debug: 1702 14886 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 1703 14890 target.c:2206 target_free_working_area_restore(): freed 7396 bytes of working area at address 0x40380000
Debug: 1704 14897 target.c:1986 print_wa_layout():    0x40380000-0x40383fff (16384 bytes)
Debug: 1705 14902 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x3fc84000
Debug: 1706 14914 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x3fc84200
Debug: 1707 14924 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x3fc84400
Debug: 1708 14931 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 1709 14936 target.c:2206 target_free_working_area_restore(): freed 1064 bytes of working area at address 0x3fc84000
Debug: 1710 14942 target.c:1986 print_wa_layout():    0x3fc84000-0x3fca3fff (131072 bytes)
Error: 1711 14945 esp_flash.c:382 esp_flash_get_mappings(): Failed to get flash maps (4294967295)!
Warn : 1712 14949 esp_flash.c:960 esp_flash_probe(): Failed to get flash mappings (-4)!
Debug: 1713 14953 esp_flash.c:239 esp_flasher_algorithm_init(): base=00000000 set=0
Debug: 1714 14956 esp_algorithm.c:312 algorithm_load_func_image(): stub: base 0x0, start 0x403810d2, 2 sections
Debug: 1715 14960 esp_algorithm.c:319 algorithm_load_func_image(): addr 0x00000000, sz 7396, flags 1
Debug: 1716 14964 target.c:2119 alloc_working_area_try_do(): allocated new working area of 7396 bytes at address 0x40380000
Debug: 1717 15406 riscv-013.c:2858 log_mem_access_result(): Succeeded to read memory via system bus.
Debug: 1718 15410 target.c:1986 print_wa_layout(): b* 0x40380000-0x40381ce3 (7396 bytes)
Debug: 1719 15414 target.c:1986 print_wa_layout():    0x40381ce4-0x40383fff (8988 bytes)
Debug: 1720 15419 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40380000
Debug: 1721 15426 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380000
Debug: 1722 15436 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 1723 15441 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40380200
Debug: 1724 15446 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380200
Debug: 1725 15457 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 1726 15461 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40380400
Debug: 1727 15468 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380400
Debug: 1728 15479 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 1729 15484 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40380600
Debug: 1730 15490 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380600
Debug: 1731 15500 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 1732 15505 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40380800
Debug: 1733 15511 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380800
Debug: 1734 15523 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 1735 15528 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40380a00
Debug: 1736 15534 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380a00
Debug: 1737 15545 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 1738 15550 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40380c00
Debug: 1739 15556 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380c00
Debug: 1740 15566 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 1741 15571 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40380e00
Debug: 1742 15576 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380e00
Debug: 1743 15587 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 1744 15592 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40381000
Debug: 1745 15599 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381000
Debug: 1746 15610 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 1747 15615 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40381200
Debug: 1748 15620 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381200
Debug: 1749 15633 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 1750 15638 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40381400
Debug: 1751 15644 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381400
Debug: 1752 15654 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 1753 15659 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40381600
Debug: 1754 15665 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381600
Debug: 1755 15677 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 1756 15682 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40381800
Debug: 1757 15688 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381800
Debug: 1758 15699 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 1759 15705 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40381a00
Debug: 1760 15711 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381a00
Debug: 1761 15721 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 1762 15725 target.c:2471 target_write_buffer(): writing buffer of 228 byte at 0x40381c00
Debug: 1763 15731 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381c00
Debug: 1764 15740 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 1765 15744 esp_algorithm.c:319 algorithm_load_func_image(): addr 0x00000000, sz 769, flags 0
Debug: 1766 15749 esp_algorithm.c:351 algorithm_load_func_image(): DATA sec size 769 -> 772
Debug: 1767 15754 esp_algorithm.c:356 algorithm_load_func_image(): BSS sec size 289 -> 292
Debug: 1768 15758 target.c:2119 alloc_working_area_try_do(): allocated new working area of 1064 bytes at address 0x3fc84000
Debug: 1769 15831 riscv-013.c:2858 log_mem_access_result(): Succeeded to read memory via system bus.
Debug: 1770 15835 target.c:1986 print_wa_layout(): b* 0x3fc84000-0x3fc84427 (1064 bytes)
Debug: 1771 15840 target.c:1986 print_wa_layout():    0x3fc84428-0x3fca3fff (130008 bytes)
Debug: 1772 15844 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x3fc84000
Debug: 1773 15850 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x3fc84000
Debug: 1774 15860 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 1775 15864 target.c:2471 target_write_buffer(): writing buffer of 257 byte at 0x3fc84200
Debug: 1776 15871 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x3fc84200
Debug: 1777 15879 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 1778 15884 esp_riscv.c:556 esp_riscv_write_memory(): Use 32-bit access: size: 1  count:1 start address: 0x3fc84300
Debug: 1779 15892 riscv-013.c:2858 log_mem_access_result(): Succeeded to read memory via system bus.
Debug: 1780 15897 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x3fc84300
Debug: 1781 15902 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 1782 15906 target.c:2119 alloc_working_area_try_do(): allocated new working area of 1024 bytes at address 0x3fc84428
Debug: 1783 15975 riscv-013.c:2858 log_mem_access_result(): Succeeded to read memory via system bus.
Debug: 1784 15979 target.c:1986 print_wa_layout(): b* 0x3fc84000-0x3fc84427 (1064 bytes)
Debug: 1785 15984 target.c:1986 print_wa_layout(): b* 0x3fc84428-0x3fc84827 (1024 bytes)
Debug: 1786 15988 target.c:1986 print_wa_layout():    0x3fc84828-0x3fca3fff (128984 bytes)
Debug: 1787 15993 target.c:2119 alloc_working_area_try_do(): allocated new working area of 4 bytes at address 0x40381ce4
Debug: 1788 16001 riscv-013.c:2858 log_mem_access_result(): Succeeded to read memory via system bus.
Debug: 1789 16006 target.c:1986 print_wa_layout(): b* 0x40380000-0x40381ce3 (7396 bytes)
Debug: 1790 16010 target.c:1986 print_wa_layout(): b* 0x40381ce4-0x40381ce7 (4 bytes)
Debug: 1791 16015 target.c:1986 print_wa_layout():    0x40381ce8-0x40383fff (8984 bytes)
Debug: 1792 16020 target.c:2471 target_write_buffer(): writing buffer of 4 byte at 0x40381ce4
Debug: 1793 16025 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381ce4
Debug: 1794 16030 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 1795 16034 esp_algorithm.c:442 algorithm_load_func_image(): Stub loaded in 1078.46 ms
Debug: 1796 16038 esp_riscv_algorithm.c:55 esp_riscv_algo_regs_init_start(): Check stack addr 0x3fc84828
Debug: 1797 16041 esp_riscv_algorithm.c:58 esp_riscv_algo_regs_init_start(): Adjust stack addr to 0x3fc84820
Debug: 1798 16046 esp_riscv_algorithm.c:98 esp_riscv_algo_init(): Set arg[0] = 4 (a0)
Debug: 1799 16049 esp_algorithm.c:196 algorithm_run(): Algorithm start @ 0x40381ce4, stack 1024 bytes @ 0x3fc84828
Debug: 1800 16053 esp_riscv.c:321 esp_riscv_start_algorithm(): save ra
Debug: 1801 16056 riscv.c:3517 riscv_get_register(): [esp32c3] ra: 4038aa78 (cached)
Debug: 1802 16059 riscv.c:3888 register_get(): [esp32c3] read 0x4038aa78 from ra (valid=1)
Debug: 1803 16063 esp_riscv.c:321 esp_riscv_start_algorithm(): save sp
Debug: 1804 16066 riscv.c:3517 riscv_get_register(): [esp32c3] sp: 3fca8080 (cached)
Debug: 1805 16069 riscv.c:3888 register_get(): [esp32c3] read 0x3fca8080 from sp (valid=1)
Debug: 1806 16072 esp_riscv.c:321 esp_riscv_start_algorithm(): save gp
Debug: 1807 16075 riscv.c:3517 riscv_get_register(): [esp32c3] gp: 3fc8fc00 (cached)
Debug: 1808 16079 riscv.c:3888 register_get(): [esp32c3] read 0x3fc8fc00 from gp (valid=1)
Debug: 1809 16082 esp_riscv.c:321 esp_riscv_start_algorithm(): save tp
Debug: 1810 16085 riscv.c:3517 riscv_get_register(): [esp32c3] tp: 3fc97820 (cached)
Debug: 1811 16089 riscv.c:3888 register_get(): [esp32c3] read 0x3fc97820 from tp (valid=1)
Debug: 1812 16092 esp_riscv.c:321 esp_riscv_start_algorithm(): save t0
Debug: 1813 16095 riscv.c:3517 riscv_get_register(): [esp32c3] t0: 0 (cached)
Debug: 1814 16098 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from t0 (valid=1)
Debug: 1815 16102 esp_riscv.c:321 esp_riscv_start_algorithm(): save t1
Debug: 1816 16104 riscv.c:3517 riscv_get_register(): [esp32c3] t1: 0 (cached)
Debug: 1817 16107 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from t1 (valid=1)
Debug: 1818 16111 esp_riscv.c:321 esp_riscv_start_algorithm(): save t2
Debug: 1819 16114 riscv.c:3517 riscv_get_register(): [esp32c3] t2: 0 (cached)
Debug: 1820 16117 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from t2 (valid=1)
Debug: 1821 16120 esp_riscv.c:321 esp_riscv_start_algorithm(): save fp
Debug: 1822 16123 riscv.c:3517 riscv_get_register(): [esp32c3] s0: 0 (cached)
Debug: 1823 16127 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from fp (valid=1)
Debug: 1824 16130 esp_riscv.c:321 esp_riscv_start_algorithm(): save s1
Debug: 1825 16133 riscv.c:3517 riscv_get_register(): [esp32c3] s1: 1 (cached)
Debug: 1826 16135 riscv.c:3888 register_get(): [esp32c3] read 0x00000001 from s1 (valid=1)
Debug: 1827 16139 esp_riscv.c:321 esp_riscv_start_algorithm(): save a0
Debug: 1828 16142 riscv.c:3517 riscv_get_register(): [esp32c3] a0: 1 (cached)
Debug: 1829 16145 riscv.c:3888 register_get(): [esp32c3] read 0x00000001 from a0 (valid=1)
Debug: 1830 16148 esp_riscv.c:321 esp_riscv_start_algorithm(): save a1
Debug: 1831 16151 riscv.c:3517 riscv_get_register(): [esp32c3] a1: 3fca809f (cached)
Debug: 1832 16154 riscv.c:3888 register_get(): [esp32c3] read 0x3fca809f from a1 (valid=1)
Debug: 1833 16158 esp_riscv.c:321 esp_riscv_start_algorithm(): save a2
Debug: 1834 16161 riscv.c:3517 riscv_get_register(): [esp32c3] a2: 0 (cached)
Debug: 1835 16163 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from a2 (valid=1)
Debug: 1836 16167 esp_riscv.c:321 esp_riscv_start_algorithm(): save a3
Debug: 1837 16169 riscv.c:3517 riscv_get_register(): [esp32c3] a3: 4 (cached)
Debug: 1838 16173 riscv.c:3888 register_get(): [esp32c3] read 0x00000004 from a3 (valid=1)
Debug: 1839 16176 esp_riscv.c:321 esp_riscv_start_algorithm(): save a4
Debug: 1840 16179 riscv.c:3517 riscv_get_register(): [esp32c3] a4: 600c2000 (cached)
Debug: 1841 16182 riscv.c:3888 register_get(): [esp32c3] read 0x600c2000 from a4 (valid=1)
Debug: 1842 16186 esp_riscv.c:321 esp_riscv_start_algorithm(): save a5
Debug: 1843 16189 riscv.c:3517 riscv_get_register(): [esp32c3] a5: 89 (cached)
Debug: 1844 16192 riscv.c:3888 register_get(): [esp32c3] read 0x00000089 from a5 (valid=1)
Debug: 1845 16195 esp_riscv.c:321 esp_riscv_start_algorithm(): save a6
Debug: 1846 16198 riscv.c:3517 riscv_get_register(): [esp32c3] a6: 0 (cached)
Debug: 1847 16201 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from a6 (valid=1)
Debug: 1848 16204 esp_riscv.c:321 esp_riscv_start_algorithm(): save a7
Debug: 1849 16207 riscv.c:3517 riscv_get_register(): [esp32c3] a7: 0 (cached)
Debug: 1850 16210 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from a7 (valid=1)
Debug: 1851 16213 esp_riscv.c:321 esp_riscv_start_algorithm(): save s2
Debug: 1852 16216 riscv.c:3517 riscv_get_register(): [esp32c3] s2: 0 (cached)
Debug: 1853 16219 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from s2 (valid=1)
Debug: 1854 16222 esp_riscv.c:321 esp_riscv_start_algorithm(): save s3
Debug: 1855 16225 riscv.c:3517 riscv_get_register(): [esp32c3] s3: 0 (cached)
Debug: 1856 16228 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from s3 (valid=1)
Debug: 1857 16231 esp_riscv.c:321 esp_riscv_start_algorithm(): save s4
Debug: 1858 16234 riscv.c:3517 riscv_get_register(): [esp32c3] s4: 0 (cached)
Debug: 1859 16237 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from s4 (valid=1)
Debug: 1860 16240 esp_riscv.c:321 esp_riscv_start_algorithm(): save s5
Debug: 1861 16243 riscv.c:3517 riscv_get_register(): [esp32c3] s5: 0 (cached)
Debug: 1862 16246 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from s5 (valid=1)
Debug: 1863 16250 esp_riscv.c:321 esp_riscv_start_algorithm(): save s6
Debug: 1864 16253 riscv.c:3517 riscv_get_register(): [esp32c3] s6: 0 (cached)
Debug: 1865 16256 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from s6 (valid=1)
Debug: 1866 16259 esp_riscv.c:321 esp_riscv_start_algorithm(): save s7
Debug: 1867 16262 riscv.c:3517 riscv_get_register(): [esp32c3] s7: 0 (cached)
Debug: 1868 16265 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from s7 (valid=1)
Debug: 1869 16268 esp_riscv.c:321 esp_riscv_start_algorithm(): save s8
Debug: 1870 16271 riscv.c:3517 riscv_get_register(): [esp32c3] s8: 0 (cached)
Debug: 1871 16274 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from s8 (valid=1)
Debug: 1872 16277 esp_riscv.c:321 esp_riscv_start_algorithm(): save s9
Debug: 1873 16281 riscv.c:3517 riscv_get_register(): [esp32c3] s9: 0 (cached)
Debug: 1874 16283 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from s9 (valid=1)
Debug: 1875 16287 esp_riscv.c:321 esp_riscv_start_algorithm(): save s10
Debug: 1876 16290 riscv.c:3517 riscv_get_register(): [esp32c3] s10: 0 (cached)
Debug: 1877 16293 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from s10 (valid=1)
Debug: 1878 16296 esp_riscv.c:321 esp_riscv_start_algorithm(): save s11
Debug: 1879 16299 riscv.c:3517 riscv_get_register(): [esp32c3] s11: 0 (cached)
Debug: 1880 16302 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from s11 (valid=1)
Debug: 1881 16306 esp_riscv.c:321 esp_riscv_start_algorithm(): save t3
Debug: 1882 16308 riscv.c:3517 riscv_get_register(): [esp32c3] t3: 0 (cached)
Debug: 1883 16312 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from t3 (valid=1)
Debug: 1884 16315 esp_riscv.c:321 esp_riscv_start_algorithm(): save t4
Debug: 1885 16318 riscv.c:3517 riscv_get_register(): [esp32c3] t4: 0 (cached)
Debug: 1886 16321 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from t4 (valid=1)
Debug: 1887 16324 esp_riscv.c:321 esp_riscv_start_algorithm(): save t5
Debug: 1888 16327 riscv.c:3517 riscv_get_register(): [esp32c3] t5: 0 (cached)
Debug: 1889 16330 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from t5 (valid=1)
Debug: 1890 16334 esp_riscv.c:321 esp_riscv_start_algorithm(): save t6
Debug: 1891 16336 riscv.c:3517 riscv_get_register(): [esp32c3] t6: 0 (cached)
Debug: 1892 16339 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from t6 (valid=1)
Debug: 1893 16343 esp_riscv.c:321 esp_riscv_start_algorithm(): save pc
Debug: 1894 16345 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register pc
Debug: 1895 16349 riscv-013.c:800 execute_abstract_command(): command=0x2207b1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b1
Debug: 1896 16356 riscv-013.c:1504 register_read_direct(): {0} dpc = 0x4038aa24
Debug: 1897 16359 riscv-013.c:4095 riscv013_get_register(): [0] read PC from DPC: 0x4038aa24
Debug: 1898 16362 riscv.c:3534 riscv_get_register(): [esp32c3] pc: 4038aa24
Debug: 1899 16365 riscv.c:3888 register_get(): [esp32c3] read 0x4038aa24 from pc (valid=0)
Debug: 1900 16368 esp_riscv.c:321 esp_riscv_start_algorithm(): save mstatus
Debug: 1901 16372 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register mstatus
Debug: 1902 16375 riscv-013.c:800 execute_abstract_command(): command=0x220300; access register, size=32, postexec=0, transfer=1, write=0, regno=0x300
Debug: 1903 16382 riscv-013.c:1504 register_read_direct(): {0} mstatus = 0x81
Debug: 1904 16385 riscv.c:3534 riscv_get_register(): [esp32c3] mstatus: 81
Debug: 1905 16388 riscv.c:3888 register_get(): [esp32c3] read 0x00000081 from mstatus (valid=1)
Debug: 1906 16392 esp_riscv.c:321 esp_riscv_start_algorithm(): save misa
Debug: 1907 16394 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register misa
Debug: 1908 16398 riscv-013.c:800 execute_abstract_command(): command=0x220301; access register, size=32, postexec=0, transfer=1, write=0, regno=0x301
Debug: 1909 16406 riscv-013.c:1504 register_read_direct(): {0} misa = 0x40101104
Debug: 1910 16408 riscv.c:3534 riscv_get_register(): [esp32c3] misa: 40101104
Debug: 1911 16411 riscv.c:3888 register_get(): [esp32c3] read 0x40101104 from misa (valid=1)
Debug: 1912 16415 esp_riscv.c:321 esp_riscv_start_algorithm(): save mtvec
Debug: 1913 16419 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr773
Debug: 1914 16424 riscv-013.c:800 execute_abstract_command(): command=0x220305; access register, size=32, postexec=0, transfer=1, write=0, regno=0x305
Debug: 1915 16431 riscv-013.c:1504 register_read_direct(): {0} csr773 = 0x40380001
Debug: 1916 16433 riscv.c:3534 riscv_get_register(): [esp32c3] csr773: 40380001
Debug: 1917 16437 riscv.c:3888 register_get(): [esp32c3] read 0x40380001 from mtvec (valid=0)
Debug: 1918 16440 esp_riscv.c:321 esp_riscv_start_algorithm(): save mscratch
Debug: 1919 16443 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr832
Debug: 1920 16447 riscv-013.c:800 execute_abstract_command(): command=0x220340; access register, size=32, postexec=0, transfer=1, write=0, regno=0x340
Debug: 1921 16463 riscv-013.c:1504 register_read_direct(): {0} csr832 = 0x0
Debug: 1922 16465 riscv.c:3534 riscv_get_register(): [esp32c3] csr832: 0
Debug: 1923 16468 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from mscratch (valid=0)
Debug: 1924 16472 esp_riscv.c:321 esp_riscv_start_algorithm(): save mepc
Debug: 1925 16475 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register mepc
Debug: 1926 16478 riscv-013.c:800 execute_abstract_command(): command=0x220341; access register, size=32, postexec=0, transfer=1, write=0, regno=0x341
Debug: 1927 16486 riscv-013.c:1504 register_read_direct(): {0} mepc = 0x4038aaaa
Debug: 1928 16489 riscv.c:3534 riscv_get_register(): [esp32c3] mepc: 4038aaaa
Debug: 1929 16491 riscv.c:3888 register_get(): [esp32c3] read 0x4038aaaa from mepc (valid=1)
Debug: 1930 16495 esp_riscv.c:321 esp_riscv_start_algorithm(): save mcause
Debug: 1931 16498 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register mcause
Debug: 1932 16502 riscv-013.c:800 execute_abstract_command(): command=0x220342; access register, size=32, postexec=0, transfer=1, write=0, regno=0x342
Debug: 1933 16509 riscv-013.c:1504 register_read_direct(): {0} mcause = 0x80000009
Debug: 1934 16512 riscv.c:3534 riscv_get_register(): [esp32c3] mcause: 80000009
Debug: 1935 16515 riscv.c:3888 register_get(): [esp32c3] read 0x80000009 from mcause (valid=1)
Debug: 1936 16519 esp_riscv.c:321 esp_riscv_start_algorithm(): save mtval
Debug: 1937 16522 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr835
Debug: 1938 16525 riscv-013.c:800 execute_abstract_command(): command=0x220343; access register, size=32, postexec=0, transfer=1, write=0, regno=0x343
Debug: 1939 16533 riscv-013.c:1504 register_read_direct(): {0} csr835 = 0x8082
Debug: 1940 16536 riscv.c:3534 riscv_get_register(): [esp32c3] csr835: 8082
Debug: 1941 16539 riscv.c:3888 register_get(): [esp32c3] read 0x00008082 from mtval (valid=0)
Debug: 1942 16542 esp_riscv.c:321 esp_riscv_start_algorithm(): save pmpcfg0
Debug: 1943 16545 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr928
Debug: 1944 16549 riscv-013.c:800 execute_abstract_command(): command=0x2203a0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3a0
Debug: 1945 16556 riscv-013.c:1504 register_read_direct(): {0} csr928 = 0x89888f88
Debug: 1946 16559 riscv.c:3534 riscv_get_register(): [esp32c3] csr928: 89888f88
Debug: 1947 16563 riscv.c:3888 register_get(): [esp32c3] read 0x89888f88 from pmpcfg0 (valid=0)
Debug: 1948 16566 esp_riscv.c:321 esp_riscv_start_algorithm(): save pmpcfg1
Debug: 1949 16569 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr929
Debug: 1950 16573 riscv-013.c:800 execute_abstract_command(): command=0x2203a1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3a1
Debug: 1951 16580 riscv-013.c:1504 register_read_direct(): {0} csr929 = 0x888d898b
Debug: 1952 16583 riscv.c:3534 riscv_get_register(): [esp32c3] csr929: 888d898b
Debug: 1953 16586 riscv.c:3888 register_get(): [esp32c3] read 0x888d898b from pmpcfg1 (valid=0)
Debug: 1954 16589 esp_riscv.c:321 esp_riscv_start_algorithm(): save pmpcfg2
Debug: 1955 16593 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr930
Debug: 1956 16596 riscv-013.c:800 execute_abstract_command(): command=0x2203a2; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3a2
Debug: 1957 16602 riscv-013.c:1504 register_read_direct(): {0} csr930 = 0x8f888d8f
Debug: 1958 16605 riscv.c:3534 riscv_get_register(): [esp32c3] csr930: 8f888d8f
Debug: 1959 16609 riscv.c:3888 register_get(): [esp32c3] read 0x8f888d8f from pmpcfg2 (valid=0)
Debug: 1960 16612 esp_riscv.c:321 esp_riscv_start_algorithm(): save pmpcfg3
Debug: 1961 16615 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr931
Debug: 1962 16618 riscv-013.c:800 execute_abstract_command(): command=0x2203a3; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3a3
Debug: 1963 16626 riscv-013.c:1504 register_read_direct(): {0} csr931 = 0x90888b88
Debug: 1964 16629 riscv.c:3534 riscv_get_register(): [esp32c3] csr931: 90888b88
Debug: 1965 16632 riscv.c:3888 register_get(): [esp32c3] read 0x90888b88 from pmpcfg3 (valid=0)
Debug: 1966 16635 esp_riscv.c:321 esp_riscv_start_algorithm(): save pmpaddr0
Debug: 1967 16639 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr944
Debug: 1968 16642 riscv-013.c:800 execute_abstract_command(): command=0x2203b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b0
Debug: 1969 16649 riscv-013.c:1504 register_read_direct(): {0} csr944 = 0x8000000
Debug: 1970 16652 riscv.c:3534 riscv_get_register(): [esp32c3] csr944: 8000000
Debug: 1971 16655 riscv.c:3888 register_get(): [esp32c3] read 0x08000000 from pmpaddr0 (valid=0)
Debug: 1972 16659 esp_riscv.c:321 esp_riscv_start_algorithm(): save pmpaddr1
Debug: 1973 16662 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr945
Debug: 1974 16665 riscv-013.c:800 execute_abstract_command(): command=0x2203b1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b1
Debug: 1975 16674 riscv-013.c:1504 register_read_direct(): {0} csr945 = 0xa000000
Debug: 1976 16676 riscv.c:3534 riscv_get_register(): [esp32c3] csr945: a000000
Debug: 1977 16679 riscv.c:3888 register_get(): [esp32c3] read 0x0a000000 from pmpaddr1 (valid=0)
Debug: 1978 16683 esp_riscv.c:321 esp_riscv_start_algorithm(): save pmpaddr2
Debug: 1979 16686 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr946
Debug: 1980 16690 riscv-013.c:800 execute_abstract_command(): command=0x2203b2; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b2
Debug: 1981 16697 riscv-013.c:1504 register_read_direct(): {0} csr946 = 0xf000000
Debug: 1982 16699 riscv.c:3534 riscv_get_register(): [esp32c3] csr946: f000000
Debug: 1983 16703 riscv.c:3888 register_get(): [esp32c3] read 0x0f000000 from pmpaddr2 (valid=0)
Debug: 1984 16706 esp_riscv.c:321 esp_riscv_start_algorithm(): save pmpaddr3
Debug: 1985 16709 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr947
Debug: 1986 16713 riscv-013.c:800 execute_abstract_command(): command=0x2203b3; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b3
Debug: 1987 16720 riscv-013.c:1504 register_read_direct(): {0} csr947 = 0xff20000
Debug: 1988 16722 riscv.c:3534 riscv_get_register(): [esp32c3] csr947: ff20000
Debug: 1989 16725 riscv.c:3888 register_get(): [esp32c3] read 0x0ff20000 from pmpaddr3 (valid=0)
Debug: 1990 16729 esp_riscv.c:321 esp_riscv_start_algorithm(): save pmpaddr4
Debug: 1991 16732 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr948
Debug: 1992 16735 riscv-013.c:800 execute_abstract_command(): command=0x2203b4; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b4
Debug: 1993 16743 riscv-013.c:1504 register_read_direct(): {0} csr948 = 0xff38000
Debug: 1994 16746 riscv.c:3534 riscv_get_register(): [esp32c3] csr948: ff38000
Debug: 1995 16749 riscv.c:3888 register_get(): [esp32c3] read 0x0ff38000 from pmpaddr4 (valid=0)
Debug: 1996 16753 esp_riscv.c:321 esp_riscv_start_algorithm(): save pmpaddr5
Debug: 1997 16756 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr949
Debug: 1998 16759 riscv-013.c:800 execute_abstract_command(): command=0x2203b5; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b5
Debug: 1999 16768 riscv-013.c:1504 register_read_direct(): {0} csr949 = 0xffc8000
Debug: 2000 16770 riscv.c:3534 riscv_get_register(): [esp32c3] csr949: ffc8000
Debug: 2001 16773 riscv.c:3888 register_get(): [esp32c3] read 0x0ffc8000 from pmpaddr5 (valid=0)
Debug: 2002 16777 esp_riscv.c:321 esp_riscv_start_algorithm(): save pmpaddr6
Debug: 2003 16780 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr950
Debug: 2004 16783 riscv-013.c:800 execute_abstract_command(): command=0x2203b6; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b6
Debug: 2005 16791 riscv-013.c:1504 register_read_direct(): {0} csr950 = 0x10018000
Debug: 2006 16794 riscv.c:3534 riscv_get_register(): [esp32c3] csr950: 10018000
Debug: 2007 16797 riscv.c:3888 register_get(): [esp32c3] read 0x10018000 from pmpaddr6 (valid=0)
Debug: 2008 16801 esp_riscv.c:321 esp_riscv_start_algorithm(): save pmpaddr7
Debug: 2009 16804 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr951
Debug: 2010 16807 riscv-013.c:800 execute_abstract_command(): command=0x2203b7; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b7
Debug: 2011 16815 riscv-013.c:1504 register_read_direct(): {0} csr951 = 0x100df000
Debug: 2012 16818 riscv.c:3534 riscv_get_register(): [esp32c3] csr951: 100df000
Debug: 2013 16821 riscv.c:3888 register_get(): [esp32c3] read 0x100df000 from pmpaddr7 (valid=0)
Debug: 2014 16824 esp_riscv.c:321 esp_riscv_start_algorithm(): save pmpaddr8
Debug: 2015 16827 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr952
Debug: 2016 16831 riscv-013.c:800 execute_abstract_command(): command=0x2203b8; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b8
Debug: 2017 16838 riscv-013.c:1504 register_read_direct(): {0} csr952 = 0x100f8000
Debug: 2018 16841 riscv.c:3534 riscv_get_register(): [esp32c3] csr952: 100f8000
Debug: 2019 16844 riscv.c:3888 register_get(): [esp32c3] read 0x100f8000 from pmpaddr8 (valid=0)
Debug: 2020 16848 esp_riscv.c:321 esp_riscv_start_algorithm(): save pmpaddr9
Debug: 2021 16851 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr953
Debug: 2022 16854 riscv-013.c:800 execute_abstract_command(): command=0x2203b9; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b9
Debug: 2023 16862 riscv-013.c:1504 register_read_direct(): {0} csr953 = 0x10a00000
Debug: 2024 16864 riscv.c:3534 riscv_get_register(): [esp32c3] csr953: 10a00000
Debug: 2025 16867 riscv.c:3888 register_get(): [esp32c3] read 0x10a00000 from pmpaddr9 (valid=0)
Debug: 2026 16871 esp_riscv.c:321 esp_riscv_start_algorithm(): save pmpaddr10
Debug: 2027 16874 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr954
Debug: 2028 16878 riscv-013.c:800 execute_abstract_command(): command=0x2203ba; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3ba
Debug: 2029 16886 riscv-013.c:1504 register_read_direct(): {0} csr954 = 0x14000000
Debug: 2030 16889 riscv.c:3534 riscv_get_register(): [esp32c3] csr954: 14000000
Debug: 2031 16892 riscv.c:3888 register_get(): [esp32c3] read 0x14000000 from pmpaddr10 (valid=0)
Debug: 2032 16897 esp_riscv.c:321 esp_riscv_start_algorithm(): save pmpaddr11
Debug: 2033 16900 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr955
Debug: 2034 16903 riscv-013.c:800 execute_abstract_command(): command=0x2203bb; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3bb
Debug: 2035 16911 riscv-013.c:1504 register_read_direct(): {0} csr955 = 0x14000800
Debug: 2036 16914 riscv.c:3534 riscv_get_register(): [esp32c3] csr955: 14000800
Debug: 2037 16917 riscv.c:3888 register_get(): [esp32c3] read 0x14000800 from pmpaddr11 (valid=0)
Debug: 2038 16920 esp_riscv.c:321 esp_riscv_start_algorithm(): save pmpaddr12
Debug: 2039 16923 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr956
Debug: 2040 16927 riscv-013.c:800 execute_abstract_command(): command=0x2203bc; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3bc
Debug: 2041 16934 riscv-013.c:1504 register_read_direct(): {0} csr956 = 0x18000000
Debug: 2042 16938 riscv.c:3534 riscv_get_register(): [esp32c3] csr956: 18000000
Debug: 2043 16941 riscv.c:3888 register_get(): [esp32c3] read 0x18000000 from pmpaddr12 (valid=0)
Debug: 2044 16944 esp_riscv.c:321 esp_riscv_start_algorithm(): save pmpaddr13
Debug: 2045 16947 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr957
Debug: 2046 16950 riscv-013.c:800 execute_abstract_command(): command=0x2203bd; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3bd
Debug: 2047 16959 riscv-013.c:1504 register_read_direct(): {0} csr957 = 0x18040000
Debug: 2048 16961 riscv.c:3534 riscv_get_register(): [esp32c3] csr957: 18040000
Debug: 2049 16964 riscv.c:3888 register_get(): [esp32c3] read 0x18040000 from pmpaddr13 (valid=0)
Debug: 2050 16968 esp_riscv.c:321 esp_riscv_start_algorithm(): save pmpaddr14
Debug: 2051 16972 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr958
Debug: 2052 16975 riscv-013.c:800 execute_abstract_command(): command=0x2203be; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3be
Debug: 2053 16982 riscv-013.c:1504 register_read_direct(): {0} csr958 = 0x3fffffff
Debug: 2054 16985 riscv.c:3534 riscv_get_register(): [esp32c3] csr958: 3fffffff
Debug: 2055 16989 riscv.c:3888 register_get(): [esp32c3] read 0x3fffffff from pmpaddr14 (valid=0)
Debug: 2056 16992 esp_riscv.c:321 esp_riscv_start_algorithm(): save pmpaddr15
Debug: 2057 16995 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr959
Debug: 2058 16999 riscv-013.c:800 execute_abstract_command(): command=0x2203bf; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3bf
Debug: 2059 17007 riscv-013.c:1504 register_read_direct(): {0} csr959 = 0x3fffffff
Debug: 2060 17009 riscv.c:3534 riscv_get_register(): [esp32c3] csr959: 3fffffff
Debug: 2061 17012 riscv.c:3888 register_get(): [esp32c3] read 0x3fffffff from pmpaddr15 (valid=0)
Debug: 2062 17016 esp_riscv.c:321 esp_riscv_start_algorithm(): save tselect
Debug: 2063 17019 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register tselect
Debug: 2064 17023 riscv-013.c:800 execute_abstract_command(): command=0x2207a0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a0
Debug: 2065 17030 riscv-013.c:1504 register_read_direct(): {0} tselect = 0x0
Debug: 2066 17033 riscv.c:3534 riscv_get_register(): [esp32c3] tselect: 0
Debug: 2067 17036 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from tselect (valid=0)
Debug: 2068 17040 esp_riscv.c:321 esp_riscv_start_algorithm(): save tdata1
Debug: 2069 17043 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register tdata1
Debug: 2070 17046 riscv-013.c:800 execute_abstract_command(): command=0x2207a1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a1
Debug: 2071 17054 riscv-013.c:1504 register_read_direct(): {0} tdata1 = 0x23e00000
Debug: 2072 17057 riscv.c:3534 riscv_get_register(): [esp32c3] tdata1: 23e00000
Debug: 2073 17060 riscv.c:3888 register_get(): [esp32c3] read 0x23e00000 from tdata1 (valid=0)
Debug: 2074 17063 esp_riscv.c:321 esp_riscv_start_algorithm(): save tdata2
Debug: 2075 17066 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register tdata2
Debug: 2076 17070 riscv-013.c:800 execute_abstract_command(): command=0x2207a2; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a2
Debug: 2077 17078 riscv-013.c:1504 register_read_direct(): {0} tdata2 = 0x0
Debug: 2078 17080 riscv.c:3534 riscv_get_register(): [esp32c3] tdata2: 0
Debug: 2079 17084 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from tdata2 (valid=0)
Debug: 2080 17088 esp_riscv.c:321 esp_riscv_start_algorithm(): save tcontrol
Debug: 2081 17091 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr1957
Debug: 2082 17095 riscv-013.c:800 execute_abstract_command(): command=0x2207a5; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a5
Debug: 2083 17102 riscv-013.c:1504 register_read_direct(): {0} csr1957 = 0x88
Debug: 2084 17105 riscv.c:3534 riscv_get_register(): [esp32c3] csr1957: 88
Debug: 2085 17108 riscv.c:3888 register_get(): [esp32c3] read 0x00000088 from tcontrol (valid=0)
Debug: 2086 17111 esp_riscv.c:321 esp_riscv_start_algorithm(): save dcsr
Debug: 2087 17114 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register dcsr
Debug: 2088 17118 riscv-013.c:800 execute_abstract_command(): command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0
Debug: 2089 17126 riscv-013.c:1504 register_read_direct(): {0} dcsr = 0x400000c3
Debug: 2090 17128 riscv.c:3534 riscv_get_register(): [esp32c3] dcsr: 400000c3
Debug: 2091 17132 riscv.c:3888 register_get(): [esp32c3] read 0x400000c3 from dcsr (valid=1)
Debug: 2092 17135 esp_riscv.c:321 esp_riscv_start_algorithm(): save dpc
Debug: 2093 17138 riscv.c:3517 riscv_get_register(): [esp32c3] dpc: 4038aa24 (cached)
Debug: 2094 17141 riscv.c:3888 register_get(): [esp32c3] read 0x4038aa24 from dpc (valid=1)
Debug: 2095 17145 esp_riscv.c:321 esp_riscv_start_algorithm(): save dscratch0
Debug: 2096 17148 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register dscratch0
Debug: 2097 17151 riscv-013.c:800 execute_abstract_command(): command=0x2207b2; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b2
Debug: 2098 17159 riscv-013.c:1504 register_read_direct(): {0} dscratch0 = 0x0
Debug: 2099 17162 riscv.c:3534 riscv_get_register(): [esp32c3] dscratch0: 0
Debug: 2100 17165 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from dscratch0 (valid=1)
Debug: 2101 17169 esp_riscv.c:321 esp_riscv_start_algorithm(): save dscratch1
Debug: 2102 17172 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr1971
Debug: 2103 17175 riscv-013.c:800 execute_abstract_command(): command=0x2207b3; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b3
Debug: 2104 17183 riscv-013.c:1504 register_read_direct(): {0} csr1971 = 0x1
Debug: 2105 17186 riscv.c:3534 riscv_get_register(): [esp32c3] csr1971: 1
Debug: 2106 17188 riscv.c:3888 register_get(): [esp32c3] read 0x00000001 from dscratch1 (valid=0)
Debug: 2107 17192 esp_riscv.c:321 esp_riscv_start_algorithm(): save hpmcounter16
Debug: 2108 17195 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr3088
Debug: 2109 17199 riscv-013.c:800 execute_abstract_command(): command=0x220c10; access register, size=32, postexec=0, transfer=1, write=0, regno=0xc10
Debug: 2110 17206 riscv-013.c:1504 register_read_direct(): {0} csr3088 = 0x3
Debug: 2111 17209 riscv.c:3534 riscv_get_register(): [esp32c3] csr3088: 3
Debug: 2112 17212 riscv.c:3888 register_get(): [esp32c3] read 0x00000003 from hpmcounter16 (valid=0)
Debug: 2113 17216 esp_riscv.c:321 esp_riscv_start_algorithm(): save priv
Debug: 2114 17218 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register priv
Debug: 2115 17222 riscv-013.c:800 execute_abstract_command(): command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0
Debug: 2116 17230 riscv-013.c:1504 register_read_direct(): {0} dcsr = 0x400000c3
Debug: 2117 17232 riscv.c:3534 riscv_get_register(): [esp32c3] priv: 3
Debug: 2118 17235 riscv.c:3888 register_get(): [esp32c3] read 0x03 from priv (valid=0)
Debug: 2119 17239 esp_riscv.c:350 esp_riscv_start_algorithm(): set sp
Debug: 2120 17242 riscv.c:3901 register_set(): [esp32c3] write 0x3fc84810 to sp (valid=1)
Debug: 2121 17245 riscv.c:3477 riscv_set_register(): [esp32c3] sp <- 3fc84810
Debug: 2122 17248 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x3fc84810 to register sp
Debug: 2123 17252 riscv-013.c:1315 register_write_direct(): {0} sp <- 0x3fc84810
Debug: 2124 17256 riscv-013.c:800 execute_abstract_command(): command=0x231002; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1002
Debug: 2125 17262 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x3fc84810 to sp valid=1
Debug: 2126 17266 esp_riscv.c:350 esp_riscv_start_algorithm(): set a7
Debug: 2127 17268 riscv.c:3901 register_set(): [esp32c3] write 0x403810d2 to a7 (valid=1)
Debug: 2128 17273 riscv.c:3477 riscv_set_register(): [esp32c3] a7 <- 403810d2
Debug: 2129 17275 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x403810d2 to register a7
Debug: 2130 17279 riscv-013.c:1315 register_write_direct(): {0} a7 <- 0x403810d2
Debug: 2131 17283 riscv-013.c:800 execute_abstract_command(): command=0x231011; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1011
Debug: 2132 17290 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x403810d2 to a7 valid=1
Debug: 2133 17293 esp_riscv.c:350 esp_riscv_start_algorithm(): set a0
Debug: 2134 17296 riscv.c:3901 register_set(): [esp32c3] write 0x00000004 to a0 (valid=1)
Debug: 2135 17301 riscv.c:3477 riscv_set_register(): [esp32c3] a0 <- 4
Debug: 2136 17303 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x4 to register a0
Debug: 2137 17308 riscv-013.c:1315 register_write_direct(): {0} a0 <- 0x4
Debug: 2138 17312 riscv-013.c:800 execute_abstract_command(): command=0x23100a; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100a
Debug: 2139 17318 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x4 to a0 valid=1
Debug: 2140 17322 riscv.c:3293 riscv_interrupts_disable(): Disabling Interrupts
Debug: 2141 17325 riscv.c:3517 riscv_get_register(): [esp32c3] mstatus: 81 (cached)
Debug: 2142 17328 riscv.c:3888 register_get(): [esp32c3] read 0x00000081 from mstatus (valid=1)
Debug: 2143 17332 riscv.c:3901 register_set(): [esp32c3] write 0x00000080 to mstatus (valid=1)
Debug: 2144 17336 riscv.c:3477 riscv_set_register(): [esp32c3] mstatus <- 80
Debug: 2145 17339 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x80 to register mstatus
Debug: 2146 17343 riscv-013.c:1315 register_write_direct(): {0} mstatus <- 0x80
Debug: 2147 17347 riscv-013.c:800 execute_abstract_command(): command=0x230300; access register, size=32, postexec=0, transfer=1, write=1, regno=0x300
Debug: 2148 17355 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x80 to mstatus valid=0
Debug: 2149 17358 esp_riscv.c:387 esp_riscv_start_algorithm(): resume at 0x40381ce4
Debug: 2150 17362 riscv.c:1472 riscv_resume(): handle_breakpoints=0
Debug: 2151 17365 riscv.c:1399 resume_prep(): [0]
Debug: 2152 17368 riscv.c:3477 riscv_set_register(): [esp32c3] pc <- 40381ce4
Debug: 2153 17371 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x40381ce4 to register pc
Debug: 2154 17374 riscv-013.c:4120 riscv013_set_register(): [0] writing PC to DPC: 0x40381ce4
Debug: 2155 17378 riscv-013.c:1315 register_write_direct(): {0} dpc <- 0x40381ce4
Debug: 2156 17382 riscv-013.c:800 execute_abstract_command(): command=0x2307b1; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b1
Debug: 2157 17389 riscv-013.c:800 execute_abstract_command(): command=0x2207b1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b1
Debug: 2158 17396 riscv-013.c:1504 register_read_direct(): {0} dpc = 0x40381ce4
Debug: 2159 17399 riscv-013.c:4124 riscv013_set_register(): [0]   actual DPC written: 0x0000000040381ce4
Debug: 2160 17403 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x40381ce4 to pc valid=0
Debug: 2161 17407 riscv.c:1289 riscv_resume_prep_all_harts(): [esp32c3] prep hart
Debug: 2162 17410 program.c:35 riscv_program_write(): debug_buffer[00] = DASM(0x0000100f)
Debug: 2163 17414 riscv-013.c:4381 riscv013_write_debug_buffer(): cache hit for 0x100f @0
Debug: 2164 17417 program.c:35 riscv_program_write(): debug_buffer[01] = DASM(0x0000000f)
Debug: 2165 17421 riscv-013.c:4381 riscv013_write_debug_buffer(): cache hit for 0xf @1
Debug: 2166 17424 program.c:35 riscv_program_write(): debug_buffer[02] = DASM(0x00100073)
Debug: 2167 17427 riscv-013.c:4381 riscv013_write_debug_buffer(): cache hit for 0x100073 @2
Debug: 2168 17431 riscv-013.c:800 execute_abstract_command(): command=0x241000; access register, size=32, postexec=1, transfer=0, write=0, regno=0x1000
Debug: 2169 17438 riscv-013.c:800 execute_abstract_command(): command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0
Debug: 2170 17446 riscv-013.c:1504 register_read_direct(): {0} dcsr = 0x400000c3
Debug: 2171 17448 riscv.c:3477 riscv_set_register(): [esp32c3] dcsr <- 4000b0c3
Debug: 2172 17451 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x4000b0c3 to register dcsr
Debug: 2173 17455 riscv-013.c:1315 register_write_direct(): {0} dcsr <- 0x4000b0c3
Debug: 2174 17459 riscv-013.c:800 execute_abstract_command(): command=0x2307b0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b0
Debug: 2175 17466 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x4000b0c3 to dcsr valid=0
Debug: 2176 17469 riscv.c:1300 riscv_resume_prep_all_harts(): [esp32c3] mark as prepped
Debug: 2177 17473 riscv.c:1424 resume_prep(): [0] mark as prepped
Debug: 2178 17475 riscv.c:3276 riscv_resume_go_all_harts(): [esp32c3] resuming hart
Debug: 2179 17480 riscv-013.c:4190 select_prepped_harts(): index=0, coreid=0, prepped=1
Debug: 2180 17483 riscv-013.c:4815 riscv013_step_or_resume_current_hart(): resuming hart 0 (for step?=0)
Debug: 2181 17489 riscv.c:3397 riscv_invalidate_register_cache(): [0]
Debug: 2182 17492 target.c:1860 target_call_event_callbacks(): target event 18 (debug-resumed) for core esp32c3
Debug: 2183 17496 esp32c3.c:188 esp32c3_handle_target_event(): 18
Debug: 2184 17499 esp_riscv.c:281 esp_riscv_handle_target_event(): 18
Debug: 2185 17501 esp_algorithm.c:218 algorithm_run(): Wait algorithm completion
Debug: 2186 17505 riscv.c:2078 riscv_poll_hart():   triggered a halt
Debug: 2187 17508 riscv.c:2258 riscv_openocd_poll():   hart 0 halted
Debug: 2188 17512 riscv-013.c:800 execute_abstract_command(): command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0
Debug: 2189 17519 riscv-013.c:1504 register_read_direct(): {0} dcsr = 0x4000b043
Debug: 2190 17522 riscv-013.c:4345 riscv013_halt_reason(): dcsr.cause: 0x1
Debug: 2191 17525 riscv.c:2113 set_debug_reason(): [esp32c3] debug_reason=1
Debug: 2192 17528 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register pc
Debug: 2193 17532 riscv-013.c:800 execute_abstract_command(): command=0x2207b1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b1
Debug: 2194 17539 riscv-013.c:1504 register_read_direct(): {0} dpc = 0x40381ce6
Debug: 2195 17542 riscv-013.c:4095 riscv013_get_register(): [0] read PC from DPC: 0x40381ce6
Debug: 2196 17546 riscv.c:3534 riscv_get_register(): [esp32c3] pc: 40381ce6
Debug: 2197 17549 esp_riscv.c:529 esp_riscv_read_memory(): Use 32-bit access: size: 2   count:2 start address: 0x40381ce2
Debug: 2198 17558 riscv-013.c:2858 log_mem_access_result(): Succeeded to read memory via system bus.
Debug: 2199 17561 esp_riscv.c:529 esp_riscv_read_memory(): Use 32-bit access: size: 2   count:2 start address: 0x40381ce6
Debug: 2200 17570 riscv-013.c:2858 log_mem_access_result(): Succeeded to read memory via system bus.
Debug: 2201 17573 esp_riscv.c:529 esp_riscv_read_memory(): Use 32-bit access: size: 2   count:2 start address: 0x40381cea
Debug: 2202 17582 riscv-013.c:2858 log_mem_access_result(): Succeeded to read memory via system bus.
Debug: 2203 17585 riscv_semihosting.c:108 riscv_semihosting(): check 9882bd19 85269002 446240f2 from 0x40381ce6-4
Debug: 2204 17590 riscv_semihosting.c:112 riscv_semihosting():    -> NONE (no magic)
Debug: 2205 17593 target.c:1860 target_call_event_callbacks(): target event 0 (gdb-halt) for core esp32c3
Debug: 2206 17597 esp32c3.c:188 esp32c3_handle_target_event(): 0
Debug: 2207 17599 esp_riscv.c:281 esp_riscv_handle_target_event(): 0
Debug: 2208 17602 target.c:1860 target_call_event_callbacks(): target event 1 (halted) for core esp32c3
Debug: 2209 17607 target.c:5153 target_handle_event(): target(0): esp32c3 (esp32c3) event: 1 (halted) action:
    esp32c3_wdt_disable

Debug: 2210 17612 command.c:166 script_debug(): command - command mode
Debug: 2211 17615 command.c:166 script_debug(): command - mww 0x6001f064 0x50D83AA1
Debug: 2212 17620 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x6001f064
Debug: 2213 17625 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 2214 17629 command.c:166 script_debug(): command - mww 0x6001F048 0
Debug: 2215 17634 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x6001f048
Debug: 2216 17639 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 2217 17642 command.c:166 script_debug(): command - mww 0x60020064 0x50D83AA1
Debug: 2218 17647 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x60020064
Debug: 2219 17653 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 2220 17656 command.c:166 script_debug(): command - mww 0x60020048 0
Debug: 2221 17661 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x60020048
Debug: 2222 17666 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 2223 17670 command.c:166 script_debug(): command - mww 0x600080a8 0x50D83AA1
Debug: 2224 17676 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x600080a8
Debug: 2225 17681 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 2226 17686 command.c:166 script_debug(): command - mww 0x60008090 0
Debug: 2227 17690 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x60008090
Debug: 2228 17695 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 2229 17699 command.c:166 script_debug(): command - mww 0x600080b0 0x8F1D312A
Debug: 2230 17704 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x600080b0
Debug: 2231 17708 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 2232 17712 command.c:166 script_debug(): command - mww 0x600080ac 0x84B00000
Debug: 2233 17718 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x600080ac
Debug: 2234 17723 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 2235 17726 esp32c3.c:188 esp32c3_handle_target_event(): 1
Debug: 2236 17729 esp_riscv.c:281 esp_riscv_handle_target_event(): 1
Debug: 2237 17731 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register pc
Debug: 2238 17735 riscv-013.c:800 execute_abstract_command(): command=0x2207b1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b1
Debug: 2239 17742 riscv-013.c:1504 register_read_direct(): {0} dpc = 0x40381ce6
Debug: 2240 17745 riscv-013.c:4095 riscv013_get_register(): [0] read PC from DPC: 0x40381ce6
Debug: 2241 17749 riscv.c:3534 riscv_get_register(): [esp32c3] pc: 40381ce6
Debug: 2242 17752 riscv.c:3888 register_get(): [esp32c3] read 0x40381ce6 from pc (valid=0)
Debug: 2243 17755 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register a0
Debug: 2244 17759 riscv-013.c:800 execute_abstract_command(): command=0x22100a; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100a
Debug: 2245 17767 riscv-013.c:1504 register_read_direct(): {0} a0 = 0x0
Debug: 2246 17769 riscv.c:3534 riscv_get_register(): [esp32c3] a0: 0
Debug: 2247 17772 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from a0 (valid=1)
Debug: 2248 17776 esp_riscv.c:465 esp_riscv_wait_algorithm(): Read mem params
Debug: 2249 17779 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore ra
Debug: 2250 17781 riscv.c:3901 register_set(): [esp32c3] write 0x4038aa78 to ra (valid=0)
Debug: 2251 17785 riscv.c:3477 riscv_set_register(): [esp32c3] ra <- 4038aa78
Debug: 2252 17788 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x4038aa78 to register ra
Debug: 2253 17792 riscv-013.c:1315 register_write_direct(): {0} ra <- 0x4038aa78
Debug: 2254 17795 riscv-013.c:800 execute_abstract_command(): command=0x231001; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1001
Debug: 2255 17802 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x4038aa78 to ra valid=1
Debug: 2256 17806 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore sp
Debug: 2257 17808 riscv.c:3901 register_set(): [esp32c3] write 0x3fca8080 to sp (valid=0)
Debug: 2258 17812 riscv.c:3477 riscv_set_register(): [esp32c3] sp <- 3fca8080
Debug: 2259 17815 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x3fca8080 to register sp
Debug: 2260 17818 riscv-013.c:1315 register_write_direct(): {0} sp <- 0x3fca8080
Debug: 2261 17822 riscv-013.c:800 execute_abstract_command(): command=0x231002; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1002
Debug: 2262 17829 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x3fca8080 to sp valid=1
Debug: 2263 17832 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore gp
Debug: 2264 17835 riscv.c:3901 register_set(): [esp32c3] write 0x3fc8fc00 to gp (valid=0)
Debug: 2265 17838 riscv.c:3477 riscv_set_register(): [esp32c3] gp <- 3fc8fc00
Debug: 2266 17841 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x3fc8fc00 to register gp
Debug: 2267 17845 riscv-013.c:1315 register_write_direct(): {0} gp <- 0x3fc8fc00
Debug: 2268 17849 riscv-013.c:800 execute_abstract_command(): command=0x231003; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1003
Debug: 2269 17856 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x3fc8fc00 to gp valid=1
Debug: 2270 17859 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore tp
Debug: 2271 17861 riscv.c:3901 register_set(): [esp32c3] write 0x3fc97820 to tp (valid=0)
Debug: 2272 17865 riscv.c:3477 riscv_set_register(): [esp32c3] tp <- 3fc97820
Debug: 2273 17868 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x3fc97820 to register tp
Debug: 2274 17872 riscv-013.c:1315 register_write_direct(): {0} tp <- 0x3fc97820
Debug: 2275 17876 riscv-013.c:800 execute_abstract_command(): command=0x231004; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1004
Debug: 2276 17882 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x3fc97820 to tp valid=1
Debug: 2277 17885 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore t0
Debug: 2278 17888 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to t0 (valid=0)
Debug: 2279 17892 riscv.c:3477 riscv_set_register(): [esp32c3] t0 <- 0
Debug: 2280 17894 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register t0
Debug: 2281 17898 riscv-013.c:1315 register_write_direct(): {0} t0 <- 0x0
Debug: 2282 17902 riscv-013.c:800 execute_abstract_command(): command=0x231005; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1005
Debug: 2283 17909 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to t0 valid=1
Debug: 2284 17912 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore t1
Debug: 2285 17915 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to t1 (valid=0)
Debug: 2286 17918 riscv.c:3477 riscv_set_register(): [esp32c3] t1 <- 0
Debug: 2287 17921 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register t1
Debug: 2288 17924 riscv-013.c:1315 register_write_direct(): {0} t1 <- 0x0
Debug: 2289 17928 riscv-013.c:800 execute_abstract_command(): command=0x231006; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1006
Debug: 2290 17935 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to t1 valid=1
Debug: 2291 17938 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore t2
Debug: 2292 17941 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to t2 (valid=0)
Debug: 2293 17945 riscv.c:3477 riscv_set_register(): [esp32c3] t2 <- 0
Debug: 2294 17947 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register t2
Debug: 2295 17951 riscv-013.c:1315 register_write_direct(): {0} t2 <- 0x0
Debug: 2296 17954 riscv-013.c:800 execute_abstract_command(): command=0x231007; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1007
Debug: 2297 17962 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to t2 valid=1
Debug: 2298 17965 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore fp
Debug: 2299 17968 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to fp (valid=0)
Debug: 2300 17971 riscv.c:3477 riscv_set_register(): [esp32c3] s0 <- 0
Debug: 2301 17973 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register s0
Debug: 2302 17977 riscv-013.c:1315 register_write_direct(): {0} s0 <- 0x0
Debug: 2303 17981 riscv-013.c:800 execute_abstract_command(): command=0x231008; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1008
Debug: 2304 17988 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to fp valid=1
Debug: 2305 17991 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore s1
Debug: 2306 17994 riscv.c:3901 register_set(): [esp32c3] write 0x00000001 to s1 (valid=0)
Debug: 2307 17997 riscv.c:3477 riscv_set_register(): [esp32c3] s1 <- 1
Debug: 2308 18000 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x1 to register s1
Debug: 2309 18003 riscv-013.c:1315 register_write_direct(): {0} s1 <- 0x1
Debug: 2310 18008 riscv-013.c:800 execute_abstract_command(): command=0x231009; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1009
Debug: 2311 18014 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x1 to s1 valid=1
Debug: 2312 18017 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore a0
Debug: 2313 18020 riscv.c:3901 register_set(): [esp32c3] write 0x00000001 to a0 (valid=1)
Debug: 2314 18024 riscv.c:3477 riscv_set_register(): [esp32c3] a0 <- 1
Debug: 2315 18027 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x1 to register a0
Debug: 2316 18030 riscv-013.c:1315 register_write_direct(): {0} a0 <- 0x1
Debug: 2317 18034 riscv-013.c:800 execute_abstract_command(): command=0x23100a; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100a
Debug: 2318 18041 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x1 to a0 valid=1
Debug: 2319 18044 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore a1
Debug: 2320 18047 riscv.c:3901 register_set(): [esp32c3] write 0x3fca809f to a1 (valid=0)
Debug: 2321 18050 riscv.c:3477 riscv_set_register(): [esp32c3] a1 <- 3fca809f
Debug: 2322 18053 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x3fca809f to register a1
Debug: 2323 18058 riscv-013.c:1315 register_write_direct(): {0} a1 <- 0x3fca809f
Debug: 2324 18062 riscv-013.c:800 execute_abstract_command(): command=0x23100b; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100b
Debug: 2325 18068 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x3fca809f to a1 valid=1
Debug: 2326 18072 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore a2
Debug: 2327 18075 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to a2 (valid=0)
Debug: 2328 18078 riscv.c:3477 riscv_set_register(): [esp32c3] a2 <- 0
Debug: 2329 18081 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register a2
Debug: 2330 18084 riscv-013.c:1315 register_write_direct(): {0} a2 <- 0x0
Debug: 2331 18088 riscv-013.c:800 execute_abstract_command(): command=0x23100c; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100c
Debug: 2332 18095 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to a2 valid=1
Debug: 2333 18098 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore a3
Debug: 2334 18101 riscv.c:3901 register_set(): [esp32c3] write 0x00000004 to a3 (valid=0)
Debug: 2335 18105 riscv.c:3477 riscv_set_register(): [esp32c3] a3 <- 4
Debug: 2336 18108 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x4 to register a3
Debug: 2337 18111 riscv-013.c:1315 register_write_direct(): {0} a3 <- 0x4
Debug: 2338 18114 riscv-013.c:800 execute_abstract_command(): command=0x23100d; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100d
Debug: 2339 18121 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x4 to a3 valid=1
Debug: 2340 18124 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore a4
Debug: 2341 18127 riscv.c:3901 register_set(): [esp32c3] write 0x600c2000 to a4 (valid=0)
Debug: 2342 18130 riscv.c:3477 riscv_set_register(): [esp32c3] a4 <- 600c2000
Debug: 2343 18133 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x600c2000 to register a4
Debug: 2344 18137 riscv-013.c:1315 register_write_direct(): {0} a4 <- 0x600c2000
Debug: 2345 18141 riscv-013.c:800 execute_abstract_command(): command=0x23100e; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100e
Debug: 2346 18147 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x600c2000 to a4 valid=1
Debug: 2347 18151 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore a5
Debug: 2348 18154 riscv.c:3901 register_set(): [esp32c3] write 0x00000089 to a5 (valid=0)
Debug: 2349 18157 riscv.c:3477 riscv_set_register(): [esp32c3] a5 <- 89
Debug: 2350 18160 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x89 to register a5
Debug: 2351 18164 riscv-013.c:1315 register_write_direct(): {0} a5 <- 0x89
Debug: 2352 18168 riscv-013.c:800 execute_abstract_command(): command=0x23100f; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100f
Debug: 2353 18174 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x89 to a5 valid=1
Debug: 2354 18177 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore a6
Debug: 2355 18180 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to a6 (valid=0)
Debug: 2356 18184 riscv.c:3477 riscv_set_register(): [esp32c3] a6 <- 0
Debug: 2357 18187 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register a6
Debug: 2358 18190 riscv-013.c:1315 register_write_direct(): {0} a6 <- 0x0
Debug: 2359 18194 riscv-013.c:800 execute_abstract_command(): command=0x231010; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1010
Debug: 2360 18201 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to a6 valid=1
Debug: 2361 18205 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore a7
Debug: 2362 18207 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to a7 (valid=0)
Debug: 2363 18211 riscv.c:3477 riscv_set_register(): [esp32c3] a7 <- 0
Debug: 2364 18214 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register a7
Debug: 2365 18218 riscv-013.c:1315 register_write_direct(): {0} a7 <- 0x0
Debug: 2366 18221 riscv-013.c:800 execute_abstract_command(): command=0x231011; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1011
Debug: 2367 18228 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to a7 valid=1
Debug: 2368 18231 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore s2
Debug: 2369 18234 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to s2 (valid=0)
Debug: 2370 18237 riscv.c:3477 riscv_set_register(): [esp32c3] s2 <- 0
Debug: 2371 18240 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register s2
Debug: 2372 18244 riscv-013.c:1315 register_write_direct(): {0} s2 <- 0x0
Debug: 2373 18247 riscv-013.c:800 execute_abstract_command(): command=0x231012; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1012
Debug: 2374 18254 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to s2 valid=1
Debug: 2375 18257 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore s3
Debug: 2376 18260 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to s3 (valid=0)
Debug: 2377 18264 riscv.c:3477 riscv_set_register(): [esp32c3] s3 <- 0
Debug: 2378 18266 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register s3
Debug: 2379 18270 riscv-013.c:1315 register_write_direct(): {0} s3 <- 0x0
Debug: 2380 18273 riscv-013.c:800 execute_abstract_command(): command=0x231013; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1013
Debug: 2381 18280 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to s3 valid=1
Debug: 2382 18283 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore s4
Debug: 2383 18286 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to s4 (valid=0)
Debug: 2384 18290 riscv.c:3477 riscv_set_register(): [esp32c3] s4 <- 0
Debug: 2385 18293 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register s4
Debug: 2386 18296 riscv-013.c:1315 register_write_direct(): {0} s4 <- 0x0
Debug: 2387 18299 riscv-013.c:800 execute_abstract_command(): command=0x231014; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1014
Debug: 2388 18306 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to s4 valid=1
Debug: 2389 18309 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore s5
Debug: 2390 18312 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to s5 (valid=0)
Debug: 2391 18315 riscv.c:3477 riscv_set_register(): [esp32c3] s5 <- 0
Debug: 2392 18318 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register s5
Debug: 2393 18322 riscv-013.c:1315 register_write_direct(): {0} s5 <- 0x0
Debug: 2394 18326 riscv-013.c:800 execute_abstract_command(): command=0x231015; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1015
Debug: 2395 18332 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to s5 valid=1
Debug: 2396 18335 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore s6
Debug: 2397 18338 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to s6 (valid=0)
Debug: 2398 18341 riscv.c:3477 riscv_set_register(): [esp32c3] s6 <- 0
Debug: 2399 18344 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register s6
Debug: 2400 18347 riscv-013.c:1315 register_write_direct(): {0} s6 <- 0x0
Debug: 2401 18351 riscv-013.c:800 execute_abstract_command(): command=0x231016; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1016
Debug: 2402 18358 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to s6 valid=1
Debug: 2403 18361 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore s7
Debug: 2404 18363 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to s7 (valid=0)
Debug: 2405 18367 riscv.c:3477 riscv_set_register(): [esp32c3] s7 <- 0
Debug: 2406 18370 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register s7
Debug: 2407 18373 riscv-013.c:1315 register_write_direct(): {0} s7 <- 0x0
Debug: 2408 18377 riscv-013.c:800 execute_abstract_command(): command=0x231017; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1017
Debug: 2409 18383 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to s7 valid=1
Debug: 2410 18387 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore s8
Debug: 2411 18390 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to s8 (valid=0)
Debug: 2412 18393 riscv.c:3477 riscv_set_register(): [esp32c3] s8 <- 0
Debug: 2413 18395 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register s8
Debug: 2414 18399 riscv-013.c:1315 register_write_direct(): {0} s8 <- 0x0
Debug: 2415 18403 riscv-013.c:800 execute_abstract_command(): command=0x231018; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1018
Debug: 2416 18409 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to s8 valid=1
Debug: 2417 18412 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore s9
Debug: 2418 18415 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to s9 (valid=0)
Debug: 2419 18419 riscv.c:3477 riscv_set_register(): [esp32c3] s9 <- 0
Debug: 2420 18422 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register s9
Debug: 2421 18425 riscv-013.c:1315 register_write_direct(): {0} s9 <- 0x0
Debug: 2422 18428 riscv-013.c:800 execute_abstract_command(): command=0x231019; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1019
Debug: 2423 18436 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to s9 valid=1
Debug: 2424 18439 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore s10
Debug: 2425 18442 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to s10 (valid=0)
Debug: 2426 18445 riscv.c:3477 riscv_set_register(): [esp32c3] s10 <- 0
Debug: 2427 18449 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register s10
Debug: 2428 18452 riscv-013.c:1315 register_write_direct(): {0} s10 <- 0x0
Debug: 2429 18456 riscv-013.c:800 execute_abstract_command(): command=0x23101a; access register, size=32, postexec=0, transfer=1, write=1, regno=0x101a
Debug: 2430 18461 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to s10 valid=1
Debug: 2431 18466 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore s11
Debug: 2432 18468 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to s11 (valid=0)
Debug: 2433 18471 riscv.c:3477 riscv_set_register(): [esp32c3] s11 <- 0
Debug: 2434 18474 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register s11
Debug: 2435 18477 riscv-013.c:1315 register_write_direct(): {0} s11 <- 0x0
Debug: 2436 18481 riscv-013.c:800 execute_abstract_command(): command=0x23101b; access register, size=32, postexec=0, transfer=1, write=1, regno=0x101b
Debug: 2437 18488 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to s11 valid=1
Debug: 2438 18491 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore t3
Debug: 2439 18493 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to t3 (valid=0)
Debug: 2440 18497 riscv.c:3477 riscv_set_register(): [esp32c3] t3 <- 0
Debug: 2441 18500 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register t3
Debug: 2442 18503 riscv-013.c:1315 register_write_direct(): {0} t3 <- 0x0
Debug: 2443 18507 riscv-013.c:800 execute_abstract_command(): command=0x23101c; access register, size=32, postexec=0, transfer=1, write=1, regno=0x101c
Debug: 2444 18514 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to t3 valid=1
Debug: 2445 18517 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore t4
Debug: 2446 18519 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to t4 (valid=0)
Debug: 2447 18523 riscv.c:3477 riscv_set_register(): [esp32c3] t4 <- 0
Debug: 2448 18526 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register t4
Debug: 2449 18529 riscv-013.c:1315 register_write_direct(): {0} t4 <- 0x0
Debug: 2450 18533 riscv-013.c:800 execute_abstract_command(): command=0x23101d; access register, size=32, postexec=0, transfer=1, write=1, regno=0x101d
Debug: 2451 18539 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to t4 valid=1
Debug: 2452 18543 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore t5
Debug: 2453 18546 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to t5 (valid=0)
Debug: 2454 18549 riscv.c:3477 riscv_set_register(): [esp32c3] t5 <- 0
Debug: 2455 18552 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register t5
Debug: 2456 18555 riscv-013.c:1315 register_write_direct(): {0} t5 <- 0x0
Debug: 2457 18560 riscv-013.c:800 execute_abstract_command(): command=0x23101e; access register, size=32, postexec=0, transfer=1, write=1, regno=0x101e
Debug: 2458 18567 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to t5 valid=1
Debug: 2459 18570 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore t6
Debug: 2460 18573 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to t6 (valid=0)
Debug: 2461 18576 riscv.c:3477 riscv_set_register(): [esp32c3] t6 <- 0
Debug: 2462 18579 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register t6
Debug: 2463 18582 riscv-013.c:1315 register_write_direct(): {0} t6 <- 0x0
Debug: 2464 18586 riscv-013.c:800 execute_abstract_command(): command=0x23101f; access register, size=32, postexec=0, transfer=1, write=1, regno=0x101f
Debug: 2465 18592 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to t6 valid=1
Debug: 2466 18595 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pc
Debug: 2467 18598 riscv.c:3901 register_set(): [esp32c3] write 0x4038aa24 to pc (valid=0)
Debug: 2468 18601 riscv.c:3477 riscv_set_register(): [esp32c3] pc <- 4038aa24
Debug: 2469 18604 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x4038aa24 to register pc
Debug: 2470 18608 riscv-013.c:4120 riscv013_set_register(): [0] writing PC to DPC: 0x4038aa24
Debug: 2471 18611 riscv-013.c:1315 register_write_direct(): {0} dpc <- 0x4038aa24
Debug: 2472 18615 riscv-013.c:800 execute_abstract_command(): command=0x2307b1; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b1
Debug: 2473 18622 riscv-013.c:800 execute_abstract_command(): command=0x2207b1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b1
Debug: 2474 18629 riscv-013.c:1504 register_read_direct(): {0} dpc = 0x4038aa24
Debug: 2475 18631 riscv-013.c:4124 riscv013_set_register(): [0]   actual DPC written: 0x000000004038aa24
Debug: 2476 18636 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x4038aa24 to pc valid=0
Debug: 2477 18639 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore mstatus
Debug: 2478 18642 riscv.c:3901 register_set(): [esp32c3] write 0x00000081 to mstatus (valid=0)
Debug: 2479 18646 riscv.c:3477 riscv_set_register(): [esp32c3] mstatus <- 81
Debug: 2480 18648 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x81 to register mstatus
Debug: 2481 18652 riscv-013.c:1315 register_write_direct(): {0} mstatus <- 0x81
Debug: 2482 18656 riscv-013.c:800 execute_abstract_command(): command=0x230300; access register, size=32, postexec=0, transfer=1, write=1, regno=0x300
Debug: 2483 18662 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x81 to mstatus valid=0
Debug: 2484 18666 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore misa
Debug: 2485 18670 riscv.c:3901 register_set(): [esp32c3] write 0x40101104 to misa (valid=0)
Debug: 2486 18674 riscv.c:3477 riscv_set_register(): [esp32c3] misa <- 40101104
Debug: 2487 18677 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x40101104 to register misa
Debug: 2488 18681 riscv-013.c:1315 register_write_direct(): {0} misa <- 0x40101104
Debug: 2489 18685 riscv-013.c:800 execute_abstract_command(): command=0x230301; access register, size=32, postexec=0, transfer=1, write=1, regno=0x301
Debug: 2490 18692 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x40101104 to misa valid=0
Debug: 2491 18695 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore mtvec
Debug: 2492 18698 riscv.c:3901 register_set(): [esp32c3] write 0x40380001 to mtvec (valid=0)
Debug: 2493 18702 riscv.c:3477 riscv_set_register(): [esp32c3] csr773 <- 40380001
Debug: 2494 18705 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x40380001 to register csr773
Debug: 2495 18709 riscv-013.c:1315 register_write_direct(): {0} csr773 <- 0x40380001
Debug: 2496 18712 riscv-013.c:800 execute_abstract_command(): command=0x230305; access register, size=32, postexec=0, transfer=1, write=1, regno=0x305
Debug: 2497 18719 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x40380001 to mtvec valid=0
Debug: 2498 18723 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore mscratch
Debug: 2499 18726 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to mscratch (valid=0)
Debug: 2500 18730 riscv.c:3477 riscv_set_register(): [esp32c3] csr832 <- 0
Debug: 2501 18732 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register csr832
Debug: 2502 18736 riscv-013.c:1315 register_write_direct(): {0} csr832 <- 0x0
Debug: 2503 18740 riscv-013.c:800 execute_abstract_command(): command=0x230340; access register, size=32, postexec=0, transfer=1, write=1, regno=0x340
Debug: 2504 18746 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to mscratch valid=0
Debug: 2505 18750 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore mepc
Debug: 2506 18752 riscv.c:3901 register_set(): [esp32c3] write 0x4038aaaa to mepc (valid=0)
Debug: 2507 18756 riscv.c:3477 riscv_set_register(): [esp32c3] mepc <- 4038aaaa
Debug: 2508 18759 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x4038aaaa to register mepc
Debug: 2509 18763 riscv-013.c:1315 register_write_direct(): {0} mepc <- 0x4038aaaa
Debug: 2510 18767 riscv-013.c:800 execute_abstract_command(): command=0x230341; access register, size=32, postexec=0, transfer=1, write=1, regno=0x341
Debug: 2511 18774 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x4038aaaa to mepc valid=0
Debug: 2512 18778 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore mcause
Debug: 2513 18781 riscv.c:3901 register_set(): [esp32c3] write 0x80000009 to mcause (valid=0)
Debug: 2514 18784 riscv.c:3477 riscv_set_register(): [esp32c3] mcause <- 80000009
Debug: 2515 18787 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x80000009 to register mcause
Debug: 2516 18790 riscv-013.c:1315 register_write_direct(): {0} mcause <- 0x80000009
Debug: 2517 18794 riscv-013.c:800 execute_abstract_command(): command=0x230342; access register, size=32, postexec=0, transfer=1, write=1, regno=0x342
Debug: 2518 18801 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x80000009 to mcause valid=0
Debug: 2519 18804 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore mtval
Debug: 2520 18807 riscv.c:3901 register_set(): [esp32c3] write 0x00008082 to mtval (valid=0)
Debug: 2521 18811 riscv.c:3477 riscv_set_register(): [esp32c3] csr835 <- 8082
Debug: 2522 18814 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x8082 to register csr835
Debug: 2523 18817 riscv-013.c:1315 register_write_direct(): {0} csr835 <- 0x8082
Debug: 2524 18821 riscv-013.c:800 execute_abstract_command(): command=0x230343; access register, size=32, postexec=0, transfer=1, write=1, regno=0x343
Debug: 2525 18828 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x8082 to mtval valid=0
Debug: 2526 18831 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pmpcfg0
Debug: 2527 18834 riscv.c:3901 register_set(): [esp32c3] write 0x89888f88 to pmpcfg0 (valid=0)
Debug: 2528 18838 riscv.c:3477 riscv_set_register(): [esp32c3] csr928 <- 89888f88
Debug: 2529 18841 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x89888f88 to register csr928
Debug: 2530 18844 riscv-013.c:1315 register_write_direct(): {0} csr928 <- 0x89888f88
Debug: 2531 18848 riscv-013.c:800 execute_abstract_command(): command=0x2303a0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3a0
Debug: 2532 18855 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x89888f88 to pmpcfg0 valid=0
Debug: 2533 18858 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pmpcfg1
Debug: 2534 18861 riscv.c:3901 register_set(): [esp32c3] write 0x888d898b to pmpcfg1 (valid=0)
Debug: 2535 18865 riscv.c:3477 riscv_set_register(): [esp32c3] csr929 <- 888d898b
Debug: 2536 18869 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x888d898b to register csr929
Debug: 2537 18873 riscv-013.c:1315 register_write_direct(): {0} csr929 <- 0x888d898b
Debug: 2538 18876 riscv-013.c:800 execute_abstract_command(): command=0x2303a1; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3a1
Debug: 2539 18882 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x888d898b to pmpcfg1 valid=0
Debug: 2540 18886 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pmpcfg2
Debug: 2541 18889 riscv.c:3901 register_set(): [esp32c3] write 0x8f888d8f to pmpcfg2 (valid=0)
Debug: 2542 18893 riscv.c:3477 riscv_set_register(): [esp32c3] csr930 <- 8f888d8f
Debug: 2543 18896 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x8f888d8f to register csr930
Debug: 2544 18900 riscv-013.c:1315 register_write_direct(): {0} csr930 <- 0x8f888d8f
Debug: 2545 18905 riscv-013.c:800 execute_abstract_command(): command=0x2303a2; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3a2
Debug: 2546 18911 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x8f888d8f to pmpcfg2 valid=0
Debug: 2547 18914 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pmpcfg3
Debug: 2548 18917 riscv.c:3901 register_set(): [esp32c3] write 0x90888b88 to pmpcfg3 (valid=0)
Debug: 2549 18921 riscv.c:3477 riscv_set_register(): [esp32c3] csr931 <- 90888b88
Debug: 2550 18924 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x90888b88 to register csr931
Debug: 2551 18928 riscv-013.c:1315 register_write_direct(): {0} csr931 <- 0x90888b88
Debug: 2552 18932 riscv-013.c:800 execute_abstract_command(): command=0x2303a3; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3a3
Debug: 2553 18939 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x90888b88 to pmpcfg3 valid=0
Debug: 2554 18942 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pmpaddr0
Debug: 2555 18945 riscv.c:3901 register_set(): [esp32c3] write 0x08000000 to pmpaddr0 (valid=0)
Debug: 2556 18949 riscv.c:3477 riscv_set_register(): [esp32c3] csr944 <- 8000000
Debug: 2557 18952 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x8000000 to register csr944
Debug: 2558 18956 riscv-013.c:1315 register_write_direct(): {0} csr944 <- 0x8000000
Debug: 2559 18959 riscv-013.c:800 execute_abstract_command(): command=0x2303b0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b0
Debug: 2560 18966 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x8000000 to pmpaddr0 valid=0
Debug: 2561 18970 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pmpaddr1
Debug: 2562 18973 riscv.c:3901 register_set(): [esp32c3] write 0x0a000000 to pmpaddr1 (valid=0)
Debug: 2563 18976 riscv.c:3477 riscv_set_register(): [esp32c3] csr945 <- a000000
Debug: 2564 18980 riscv-013.c:4115 riscv013_set_register(): [0] writing 0xa000000 to register csr945
Debug: 2565 18984 riscv-013.c:1315 register_write_direct(): {0} csr945 <- 0xa000000
Debug: 2566 18988 riscv-013.c:800 execute_abstract_command(): command=0x2303b1; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b1
Debug: 2567 18994 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0xa000000 to pmpaddr1 valid=0
Debug: 2568 18998 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pmpaddr2
Debug: 2569 19001 riscv.c:3901 register_set(): [esp32c3] write 0x0f000000 to pmpaddr2 (valid=0)
Debug: 2570 19005 riscv.c:3477 riscv_set_register(): [esp32c3] csr946 <- f000000
Debug: 2571 19008 riscv-013.c:4115 riscv013_set_register(): [0] writing 0xf000000 to register csr946
Debug: 2572 19012 riscv-013.c:1315 register_write_direct(): {0} csr946 <- 0xf000000
Debug: 2573 19016 riscv-013.c:800 execute_abstract_command(): command=0x2303b2; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b2
Debug: 2574 19023 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0xf000000 to pmpaddr2 valid=0
Debug: 2575 19026 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pmpaddr3
Debug: 2576 19030 riscv.c:3901 register_set(): [esp32c3] write 0x0ff20000 to pmpaddr3 (valid=0)
Debug: 2577 19033 riscv.c:3477 riscv_set_register(): [esp32c3] csr947 <- ff20000
Debug: 2578 19036 riscv-013.c:4115 riscv013_set_register(): [0] writing 0xff20000 to register csr947
Debug: 2579 19040 riscv-013.c:1315 register_write_direct(): {0} csr947 <- 0xff20000
Debug: 2580 19044 riscv-013.c:800 execute_abstract_command(): command=0x2303b3; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b3
Debug: 2581 19051 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0xff20000 to pmpaddr3 valid=0
Debug: 2582 19054 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pmpaddr4
Debug: 2583 19057 riscv.c:3901 register_set(): [esp32c3] write 0x0ff38000 to pmpaddr4 (valid=0)
Debug: 2584 19061 riscv.c:3477 riscv_set_register(): [esp32c3] csr948 <- ff38000
Debug: 2585 19064 riscv-013.c:4115 riscv013_set_register(): [0] writing 0xff38000 to register csr948
Debug: 2586 19068 riscv-013.c:1315 register_write_direct(): {0} csr948 <- 0xff38000
Debug: 2587 19072 riscv-013.c:800 execute_abstract_command(): command=0x2303b4; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b4
Debug: 2588 19079 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0xff38000 to pmpaddr4 valid=0
Debug: 2589 19082 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pmpaddr5
Debug: 2590 19085 riscv.c:3901 register_set(): [esp32c3] write 0x0ffc8000 to pmpaddr5 (valid=0)
Debug: 2591 19089 riscv.c:3477 riscv_set_register(): [esp32c3] csr949 <- ffc8000
Debug: 2592 19092 riscv-013.c:4115 riscv013_set_register(): [0] writing 0xffc8000 to register csr949
Debug: 2593 19096 riscv-013.c:1315 register_write_direct(): {0} csr949 <- 0xffc8000
Debug: 2594 19100 riscv-013.c:800 execute_abstract_command(): command=0x2303b5; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b5
Debug: 2595 19107 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0xffc8000 to pmpaddr5 valid=0
Debug: 2596 19110 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pmpaddr6
Debug: 2597 19113 riscv.c:3901 register_set(): [esp32c3] write 0x10018000 to pmpaddr6 (valid=0)
Debug: 2598 19117 riscv.c:3477 riscv_set_register(): [esp32c3] csr950 <- 10018000
Debug: 2599 19120 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x10018000 to register csr950
Debug: 2600 19124 riscv-013.c:1315 register_write_direct(): {0} csr950 <- 0x10018000
Debug: 2601 19129 riscv-013.c:800 execute_abstract_command(): command=0x2303b6; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b6
Debug: 2602 19135 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x10018000 to pmpaddr6 valid=0
Debug: 2603 19139 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pmpaddr7
Debug: 2604 19142 riscv.c:3901 register_set(): [esp32c3] write 0x100df000 to pmpaddr7 (valid=0)
Debug: 2605 19146 riscv.c:3477 riscv_set_register(): [esp32c3] csr951 <- 100df000
Debug: 2606 19150 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x100df000 to register csr951
Debug: 2607 19154 riscv-013.c:1315 register_write_direct(): {0} csr951 <- 0x100df000
Debug: 2608 19158 riscv-013.c:800 execute_abstract_command(): command=0x2303b7; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b7
Debug: 2609 19164 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x100df000 to pmpaddr7 valid=0
Debug: 2610 19168 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pmpaddr8
Debug: 2611 19171 riscv.c:3901 register_set(): [esp32c3] write 0x100f8000 to pmpaddr8 (valid=0)
Debug: 2612 19175 riscv.c:3477 riscv_set_register(): [esp32c3] csr952 <- 100f8000
Debug: 2613 19178 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x100f8000 to register csr952
Debug: 2614 19181 riscv-013.c:1315 register_write_direct(): {0} csr952 <- 0x100f8000
Debug: 2615 19186 riscv-013.c:800 execute_abstract_command(): command=0x2303b8; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b8
Debug: 2616 19192 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x100f8000 to pmpaddr8 valid=0
Debug: 2617 19195 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pmpaddr9
Debug: 2618 19198 riscv.c:3901 register_set(): [esp32c3] write 0x10a00000 to pmpaddr9 (valid=0)
Debug: 2619 19203 riscv.c:3477 riscv_set_register(): [esp32c3] csr953 <- 10a00000
Debug: 2620 19206 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x10a00000 to register csr953
Debug: 2621 19210 riscv-013.c:1315 register_write_direct(): {0} csr953 <- 0x10a00000
Debug: 2622 19213 riscv-013.c:800 execute_abstract_command(): command=0x2303b9; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b9
Debug: 2623 19220 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x10a00000 to pmpaddr9 valid=0
Debug: 2624 19224 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pmpaddr10
Debug: 2625 19227 riscv.c:3901 register_set(): [esp32c3] write 0x14000000 to pmpaddr10 (valid=0)
Debug: 2626 19230 riscv.c:3477 riscv_set_register(): [esp32c3] csr954 <- 14000000
Debug: 2627 19233 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x14000000 to register csr954
Debug: 2628 19237 riscv-013.c:1315 register_write_direct(): {0} csr954 <- 0x14000000
Debug: 2629 19241 riscv-013.c:800 execute_abstract_command(): command=0x2303ba; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3ba
Debug: 2630 19248 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x14000000 to pmpaddr10 valid=0
Debug: 2631 19252 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pmpaddr11
Debug: 2632 19255 riscv.c:3901 register_set(): [esp32c3] write 0x14000800 to pmpaddr11 (valid=0)
Debug: 2633 19258 riscv.c:3477 riscv_set_register(): [esp32c3] csr955 <- 14000800
Debug: 2634 19262 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x14000800 to register csr955
Debug: 2635 19266 riscv-013.c:1315 register_write_direct(): {0} csr955 <- 0x14000800
Debug: 2636 19269 riscv-013.c:800 execute_abstract_command(): command=0x2303bb; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3bb
Debug: 2637 19276 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x14000800 to pmpaddr11 valid=0
Debug: 2638 19280 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pmpaddr12
Debug: 2639 19282 riscv.c:3901 register_set(): [esp32c3] write 0x18000000 to pmpaddr12 (valid=0)
Debug: 2640 19286 riscv.c:3477 riscv_set_register(): [esp32c3] csr956 <- 18000000
Debug: 2641 19289 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x18000000 to register csr956
Debug: 2642 19293 riscv-013.c:1315 register_write_direct(): {0} csr956 <- 0x18000000
Debug: 2643 19297 riscv-013.c:800 execute_abstract_command(): command=0x2303bc; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3bc
Debug: 2644 19304 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x18000000 to pmpaddr12 valid=0
Debug: 2645 19308 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pmpaddr13
Debug: 2646 19311 riscv.c:3901 register_set(): [esp32c3] write 0x18040000 to pmpaddr13 (valid=0)
Debug: 2647 19314 riscv.c:3477 riscv_set_register(): [esp32c3] csr957 <- 18040000
Debug: 2648 19317 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x18040000 to register csr957
Debug: 2649 19321 riscv-013.c:1315 register_write_direct(): {0} csr957 <- 0x18040000
Debug: 2650 19325 riscv-013.c:800 execute_abstract_command(): command=0x2303bd; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3bd
Debug: 2651 19333 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x18040000 to pmpaddr13 valid=0
Debug: 2652 19336 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pmpaddr14
Debug: 2653 19340 riscv.c:3901 register_set(): [esp32c3] write 0x3fffffff to pmpaddr14 (valid=0)
Debug: 2654 19343 riscv.c:3477 riscv_set_register(): [esp32c3] csr958 <- 3fffffff
Debug: 2655 19346 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x3fffffff to register csr958
Debug: 2656 19349 riscv-013.c:1315 register_write_direct(): {0} csr958 <- 0x3fffffff
Debug: 2657 19353 riscv-013.c:800 execute_abstract_command(): command=0x2303be; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3be
Debug: 2658 19360 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x3fffffff to pmpaddr14 valid=0
Debug: 2659 19364 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pmpaddr15
Debug: 2660 19366 riscv.c:3901 register_set(): [esp32c3] write 0x3fffffff to pmpaddr15 (valid=0)
Debug: 2661 19370 riscv.c:3477 riscv_set_register(): [esp32c3] csr959 <- 3fffffff
Debug: 2662 19374 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x3fffffff to register csr959
Debug: 2663 19377 riscv-013.c:1315 register_write_direct(): {0} csr959 <- 0x3fffffff
Debug: 2664 19381 riscv-013.c:800 execute_abstract_command(): command=0x2303bf; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3bf
Debug: 2665 19388 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x3fffffff to pmpaddr15 valid=0
Debug: 2666 19391 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore tselect
Debug: 2667 19394 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to tselect (valid=0)
Debug: 2668 19397 riscv.c:3477 riscv_set_register(): [esp32c3] tselect <- 0
Debug: 2669 19400 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register tselect
Debug: 2670 19404 riscv-013.c:1315 register_write_direct(): {0} tselect <- 0x0
Debug: 2671 19408 riscv-013.c:800 execute_abstract_command(): command=0x2307a0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a0
Debug: 2672 19414 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to tselect valid=0
Debug: 2673 19418 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore tdata1
Debug: 2674 19421 riscv.c:3901 register_set(): [esp32c3] write 0x23e00000 to tdata1 (valid=0)
Debug: 2675 19424 riscv.c:3477 riscv_set_register(): [esp32c3] tdata1 <- 23e00000
Debug: 2676 19427 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x23e00000 to register tdata1
Debug: 2677 19431 riscv-013.c:1315 register_write_direct(): {0} tdata1 <- 0x23e00000
Debug: 2678 19435 riscv-013.c:800 execute_abstract_command(): command=0x2307a1; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a1
Debug: 2679 19442 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x23e00000 to tdata1 valid=0
Debug: 2680 19445 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore tdata2
Debug: 2681 19448 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to tdata2 (valid=0)
Debug: 2682 19452 riscv.c:3477 riscv_set_register(): [esp32c3] tdata2 <- 0
Debug: 2683 19455 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register tdata2
Debug: 2684 19458 riscv-013.c:1315 register_write_direct(): {0} tdata2 <- 0x0
Debug: 2685 19462 riscv-013.c:800 execute_abstract_command(): command=0x2307a2; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a2
Debug: 2686 19469 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to tdata2 valid=0
Debug: 2687 19472 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore tcontrol
Debug: 2688 19475 riscv.c:3901 register_set(): [esp32c3] write 0x00000088 to tcontrol (valid=0)
Debug: 2689 19479 riscv.c:3477 riscv_set_register(): [esp32c3] csr1957 <- 88
Debug: 2690 19482 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x88 to register csr1957
Debug: 2691 19485 riscv-013.c:1315 register_write_direct(): {0} csr1957 <- 0x88
Debug: 2692 19489 riscv-013.c:800 execute_abstract_command(): command=0x2307a5; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a5
Debug: 2693 19496 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x88 to tcontrol valid=0
Debug: 2694 19499 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore dcsr
Debug: 2695 19502 riscv.c:3901 register_set(): [esp32c3] write 0x400000c3 to dcsr (valid=0)
Debug: 2696 19506 riscv.c:3477 riscv_set_register(): [esp32c3] dcsr <- 400000c3
Debug: 2697 19509 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x400000c3 to register dcsr
Debug: 2698 19512 riscv-013.c:1315 register_write_direct(): {0} dcsr <- 0x400000c3
Debug: 2699 19517 riscv-013.c:800 execute_abstract_command(): command=0x2307b0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b0
Debug: 2700 19523 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x400000c3 to dcsr valid=0
Debug: 2701 19526 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore dpc
Debug: 2702 19530 riscv.c:3901 register_set(): [esp32c3] write 0x4038aa24 to dpc (valid=0)
Debug: 2703 19533 riscv.c:3477 riscv_set_register(): [esp32c3] dpc <- 4038aa24
Debug: 2704 19536 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x4038aa24 to register dpc
Debug: 2705 19540 riscv-013.c:1315 register_write_direct(): {0} dpc <- 0x4038aa24
Debug: 2706 19544 riscv-013.c:800 execute_abstract_command(): command=0x2307b1; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b1
Debug: 2707 19551 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x4038aa24 to dpc valid=1
Debug: 2708 19554 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore dscratch0
Debug: 2709 19557 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to dscratch0 (valid=0)
Debug: 2710 19561 riscv.c:3477 riscv_set_register(): [esp32c3] dscratch0 <- 0
Debug: 2711 19564 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register dscratch0
Debug: 2712 19568 riscv-013.c:1315 register_write_direct(): {0} dscratch0 <- 0x0
Debug: 2713 19572 riscv-013.c:800 execute_abstract_command(): command=0x2307b2; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b2
Debug: 2714 19580 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to dscratch0 valid=0
Debug: 2715 19583 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore dscratch1
Debug: 2716 19586 riscv.c:3901 register_set(): [esp32c3] write 0x00000001 to dscratch1 (valid=0)
Debug: 2717 19590 riscv.c:3477 riscv_set_register(): [esp32c3] csr1971 <- 1
Debug: 2718 19593 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x1 to register csr1971
Debug: 2719 19597 riscv-013.c:1315 register_write_direct(): {0} csr1971 <- 0x1
Debug: 2720 19600 riscv-013.c:800 execute_abstract_command(): command=0x2307b3; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b3
Debug: 2721 19606 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x1 to dscratch1 valid=0
Debug: 2722 19610 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore hpmcounter16
Debug: 2723 19613 riscv.c:3901 register_set(): [esp32c3] write 0x00000003 to hpmcounter16 (valid=0)
Debug: 2724 19617 riscv.c:3477 riscv_set_register(): [esp32c3] csr3088 <- 3
Debug: 2725 19619 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x3 to register csr3088
Debug: 2726 19623 riscv-013.c:1315 register_write_direct(): {0} csr3088 <- 0x3
Debug: 2727 19627 riscv-013.c:800 execute_abstract_command(): command=0x230c10; access register, size=32, postexec=0, transfer=1, write=1, regno=0xc10
Debug: 2728 19634 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x3 to hpmcounter16 valid=0
Debug: 2729 19637 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore priv
Debug: 2730 19641 riscv.c:3901 register_set(): [esp32c3] write 0x03 to priv (valid=0)
Debug: 2731 19644 riscv.c:3477 riscv_set_register(): [esp32c3] priv <- 3
Debug: 2732 19646 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x3 to register priv
Debug: 2733 19650 riscv-013.c:800 execute_abstract_command(): command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0
Debug: 2734 19658 riscv-013.c:1504 register_read_direct(): {0} dcsr = 0x400000c3
Debug: 2735 19661 riscv-013.c:1315 register_write_direct(): {0} dcsr <- 0x400000c3
Debug: 2736 19665 riscv-013.c:800 execute_abstract_command(): command=0x2307b0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b0
Debug: 2737 19672 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x3 to priv valid=0
Debug: 2738 19675 esp_algorithm.c:246 algorithm_run(): Got algorithm RC 0x0
Debug: 2739 19679 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381ce4
Debug: 2740 19683 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 2741 19687 target.c:2206 target_free_working_area_restore(): freed 4 bytes of working area at address 0x40381ce4
Debug: 2742 19691 target.c:1986 print_wa_layout(): b* 0x40380000-0x40381ce3 (7396 bytes)
Debug: 2743 19695 target.c:1986 print_wa_layout():    0x40381ce4-0x40383fff (8988 bytes)
Debug: 2744 19699 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x3fc84428
Debug: 2745 19710 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x3fc84628
Debug: 2746 19721 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 2747 19724 target.c:2206 target_free_working_area_restore(): freed 1024 bytes of working area at address 0x3fc84428
Debug: 2748 19729 target.c:1986 print_wa_layout(): b* 0x3fc84000-0x3fc84427 (1064 bytes)
Debug: 2749 19732 target.c:1986 print_wa_layout():    0x3fc84428-0x3fca3fff (130008 bytes)
Debug: 2750 19737 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380000
Debug: 2751 19748 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380200
Debug: 2752 19758 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380400
Debug: 2753 19768 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380600
Debug: 2754 19778 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380800
Debug: 2755 19788 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380a00
Debug: 2756 19800 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380c00
Debug: 2757 19810 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380e00
Debug: 2758 19822 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381000
Debug: 2759 19834 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381200
Debug: 2760 19846 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381400
Debug: 2761 19858 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381600
Debug: 2762 19870 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381800
Debug: 2763 19881 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381a00
Debug: 2764 19892 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381c00
Debug: 2765 19899 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 2766 19904 target.c:2206 target_free_working_area_restore(): freed 7396 bytes of working area at address 0x40380000
Debug: 2767 19909 target.c:1986 print_wa_layout():    0x40380000-0x40383fff (16384 bytes)
Debug: 2768 19914 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x3fc84000
Debug: 2769 19924 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x3fc84200
Debug: 2770 19935 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x3fc84400
Debug: 2771 19941 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 2772 19945 target.c:2206 target_free_working_area_restore(): freed 1064 bytes of working area at address 0x3fc84000
Debug: 2773 19950 target.c:1986 print_wa_layout():    0x3fc84000-0x3fca3fff (131072 bytes)
Error: 2774 19954 esp_flash.c:343 esp_flash_get_size(): Failed to get flash size!
Debug: 2775 19957 esp_flash.c:344 esp_flash_get_size(): esp_flash_get_size size 0x0
Debug: 2776 19960 esp_flash.c:239 esp_flasher_algorithm_init(): base=00000000 set=0
Debug: 2777 19963 esp_algorithm.c:312 algorithm_load_func_image(): stub: base 0x0, start 0x403810d2, 2 sections
Debug: 2778 19968 esp_algorithm.c:319 algorithm_load_func_image(): addr 0x00000000, sz 7396, flags 1
Debug: 2779 19972 target.c:2119 alloc_working_area_try_do(): allocated new working area of 7396 bytes at address 0x40380000
Debug: 2780 20414 riscv-013.c:2858 log_mem_access_result(): Succeeded to read memory via system bus.
Debug: 2781 20418 target.c:1986 print_wa_layout(): b* 0x40380000-0x40381ce3 (7396 bytes)
Debug: 2782 20423 target.c:1986 print_wa_layout():    0x40381ce4-0x40383fff (8988 bytes)
Debug: 2783 20427 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40380000
Debug: 2784 20432 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380000
Debug: 2785 20442 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 2786 20446 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40380200
Debug: 2787 20453 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380200
Debug: 2788 20463 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 2789 20467 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40380400
Debug: 2790 20474 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380400
Debug: 2791 20485 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 2792 20489 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40380600
Debug: 2793 20496 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380600
Debug: 2794 20507 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 2795 20512 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40380800
Debug: 2796 20519 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380800
Debug: 2797 20529 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 2798 20534 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40380a00
Debug: 2799 20541 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380a00
Debug: 2800 20551 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 2801 20555 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40380c00
Debug: 2802 20561 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380c00
Debug: 2803 20571 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 2804 20576 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40380e00
Debug: 2805 20582 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380e00
Debug: 2806 20592 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 2807 20598 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40381000
Debug: 2808 20603 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381000
Debug: 2809 20615 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 2810 20620 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40381200
Debug: 2811 20626 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381200
Debug: 2812 20636 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 2813 20641 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40381400
Debug: 2814 20647 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381400
Debug: 2815 20657 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 2816 20661 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40381600
Debug: 2817 20667 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381600
Debug: 2818 20678 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 2819 20682 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40381800
Debug: 2820 20688 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381800
Debug: 2821 20700 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 2822 20705 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x40381a00
Debug: 2823 20712 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381a00
Debug: 2824 20723 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 2825 20728 target.c:2471 target_write_buffer(): writing buffer of 228 byte at 0x40381c00
Debug: 2826 20735 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381c00
Debug: 2827 20741 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 2828 20745 esp_algorithm.c:319 algorithm_load_func_image(): addr 0x00000000, sz 769, flags 0
Debug: 2829 20750 esp_algorithm.c:351 algorithm_load_func_image(): DATA sec size 769 -> 772
Debug: 2830 20755 esp_algorithm.c:356 algorithm_load_func_image(): BSS sec size 289 -> 292
Debug: 2831 20759 target.c:2119 alloc_working_area_try_do(): allocated new working area of 1064 bytes at address 0x3fc84000
Debug: 2832 20832 riscv-013.c:2858 log_mem_access_result(): Succeeded to read memory via system bus.
Debug: 2833 20836 target.c:1986 print_wa_layout(): b* 0x3fc84000-0x3fc84427 (1064 bytes)
Debug: 2834 20840 target.c:1986 print_wa_layout():    0x3fc84428-0x3fca3fff (130008 bytes)
Debug: 2835 20844 target.c:2471 target_write_buffer(): writing buffer of 512 byte at 0x3fc84000
Debug: 2836 20850 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x3fc84000
Debug: 2837 20860 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 2838 20864 target.c:2471 target_write_buffer(): writing buffer of 257 byte at 0x3fc84200
Debug: 2839 20870 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x3fc84200
Debug: 2840 20880 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 2841 20884 esp_riscv.c:556 esp_riscv_write_memory(): Use 32-bit access: size: 1  count:1 start address: 0x3fc84300
Debug: 2842 20894 riscv-013.c:2858 log_mem_access_result(): Succeeded to read memory via system bus.
Debug: 2843 20899 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x3fc84300
Debug: 2844 20904 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 2845 20908 target.c:2119 alloc_working_area_try_do(): allocated new working area of 1024 bytes at address 0x3fc84428
Debug: 2846 20975 riscv-013.c:2858 log_mem_access_result(): Succeeded to read memory via system bus.
Debug: 2847 20981 target.c:1986 print_wa_layout(): b* 0x3fc84000-0x3fc84427 (1064 bytes)
Debug: 2848 20984 target.c:1986 print_wa_layout(): b* 0x3fc84428-0x3fc84827 (1024 bytes)
Debug: 2849 20989 target.c:1986 print_wa_layout():    0x3fc84828-0x3fca3fff (128984 bytes)
Debug: 2850 20993 target.c:2119 alloc_working_area_try_do(): allocated new working area of 4 bytes at address 0x40381ce4
Debug: 2851 21002 riscv-013.c:2858 log_mem_access_result(): Succeeded to read memory via system bus.
Debug: 2852 21006 target.c:1986 print_wa_layout(): b* 0x40380000-0x40381ce3 (7396 bytes)
Debug: 2853 21010 target.c:1986 print_wa_layout(): b* 0x40381ce4-0x40381ce7 (4 bytes)
Debug: 2854 21016 target.c:1986 print_wa_layout():    0x40381ce8-0x40383fff (8984 bytes)
Debug: 2855 21020 target.c:2471 target_write_buffer(): writing buffer of 4 byte at 0x40381ce4
Debug: 2856 21026 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381ce4
Debug: 2857 21032 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 2858 21035 esp_algorithm.c:442 algorithm_load_func_image(): Stub loaded in 1072.06 ms
Debug: 2859 21039 esp_riscv_algorithm.c:55 esp_riscv_algo_regs_init_start(): Check stack addr 0x3fc84828
Debug: 2860 21042 esp_riscv_algorithm.c:58 esp_riscv_algo_regs_init_start(): Adjust stack addr to 0x3fc84820
Debug: 2861 21047 esp_riscv_algorithm.c:98 esp_riscv_algo_init(): Set arg[0] = 4 (a0)
Debug: 2862 21050 esp_algorithm.c:196 algorithm_run(): Algorithm start @ 0x40381ce4, stack 1024 bytes @ 0x3fc84828
Debug: 2863 21054 esp_riscv.c:321 esp_riscv_start_algorithm(): save ra
Debug: 2864 21057 riscv.c:3517 riscv_get_register(): [esp32c3] ra: 4038aa78 (cached)
Debug: 2865 21061 riscv.c:3888 register_get(): [esp32c3] read 0x4038aa78 from ra (valid=1)
Debug: 2866 21064 esp_riscv.c:321 esp_riscv_start_algorithm(): save sp
Debug: 2867 21067 riscv.c:3517 riscv_get_register(): [esp32c3] sp: 3fca8080 (cached)
Debug: 2868 21070 riscv.c:3888 register_get(): [esp32c3] read 0x3fca8080 from sp (valid=1)
Debug: 2869 21074 esp_riscv.c:321 esp_riscv_start_algorithm(): save gp
Debug: 2870 21077 riscv.c:3517 riscv_get_register(): [esp32c3] gp: 3fc8fc00 (cached)
Debug: 2871 21080 riscv.c:3888 register_get(): [esp32c3] read 0x3fc8fc00 from gp (valid=1)
Debug: 2872 21083 esp_riscv.c:321 esp_riscv_start_algorithm(): save tp
Debug: 2873 21086 riscv.c:3517 riscv_get_register(): [esp32c3] tp: 3fc97820 (cached)
Debug: 2874 21089 riscv.c:3888 register_get(): [esp32c3] read 0x3fc97820 from tp (valid=1)
Debug: 2875 21093 esp_riscv.c:321 esp_riscv_start_algorithm(): save t0
Debug: 2876 21096 riscv.c:3517 riscv_get_register(): [esp32c3] t0: 0 (cached)
Debug: 2877 21099 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from t0 (valid=1)
Debug: 2878 21102 esp_riscv.c:321 esp_riscv_start_algorithm(): save t1
Debug: 2879 21105 riscv.c:3517 riscv_get_register(): [esp32c3] t1: 0 (cached)
Debug: 2880 21108 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from t1 (valid=1)
Debug: 2881 21112 esp_riscv.c:321 esp_riscv_start_algorithm(): save t2
Debug: 2882 21114 riscv.c:3517 riscv_get_register(): [esp32c3] t2: 0 (cached)
Debug: 2883 21117 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from t2 (valid=1)
Debug: 2884 21120 esp_riscv.c:321 esp_riscv_start_algorithm(): save fp
Debug: 2885 21123 riscv.c:3517 riscv_get_register(): [esp32c3] s0: 0 (cached)
Debug: 2886 21126 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from fp (valid=1)
Debug: 2887 21129 esp_riscv.c:321 esp_riscv_start_algorithm(): save s1
Debug: 2888 21132 riscv.c:3517 riscv_get_register(): [esp32c3] s1: 1 (cached)
Debug: 2889 21135 riscv.c:3888 register_get(): [esp32c3] read 0x00000001 from s1 (valid=1)
Debug: 2890 21139 esp_riscv.c:321 esp_riscv_start_algorithm(): save a0
Debug: 2891 21141 riscv.c:3517 riscv_get_register(): [esp32c3] a0: 1 (cached)
Debug: 2892 21144 riscv.c:3888 register_get(): [esp32c3] read 0x00000001 from a0 (valid=1)
Debug: 2893 21147 esp_riscv.c:321 esp_riscv_start_algorithm(): save a1
Debug: 2894 21150 riscv.c:3517 riscv_get_register(): [esp32c3] a1: 3fca809f (cached)
Debug: 2895 21153 riscv.c:3888 register_get(): [esp32c3] read 0x3fca809f from a1 (valid=1)
Debug: 2896 21157 esp_riscv.c:321 esp_riscv_start_algorithm(): save a2
Debug: 2897 21160 riscv.c:3517 riscv_get_register(): [esp32c3] a2: 0 (cached)
Debug: 2898 21162 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from a2 (valid=1)
Debug: 2899 21166 esp_riscv.c:321 esp_riscv_start_algorithm(): save a3
Debug: 2900 21169 riscv.c:3517 riscv_get_register(): [esp32c3] a3: 4 (cached)
Debug: 2901 21172 riscv.c:3888 register_get(): [esp32c3] read 0x00000004 from a3 (valid=1)
Debug: 2902 21175 esp_riscv.c:321 esp_riscv_start_algorithm(): save a4
Debug: 2903 21178 riscv.c:3517 riscv_get_register(): [esp32c3] a4: 600c2000 (cached)
Debug: 2904 21181 riscv.c:3888 register_get(): [esp32c3] read 0x600c2000 from a4 (valid=1)
Debug: 2905 21185 esp_riscv.c:321 esp_riscv_start_algorithm(): save a5
Debug: 2906 21188 riscv.c:3517 riscv_get_register(): [esp32c3] a5: 89 (cached)
Debug: 2907 21191 riscv.c:3888 register_get(): [esp32c3] read 0x00000089 from a5 (valid=1)
Debug: 2908 21194 esp_riscv.c:321 esp_riscv_start_algorithm(): save a6
Debug: 2909 21197 riscv.c:3517 riscv_get_register(): [esp32c3] a6: 0 (cached)
Debug: 2910 21200 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from a6 (valid=1)
Debug: 2911 21203 esp_riscv.c:321 esp_riscv_start_algorithm(): save a7
Debug: 2912 21206 riscv.c:3517 riscv_get_register(): [esp32c3] a7: 0 (cached)
Debug: 2913 21209 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from a7 (valid=1)
Debug: 2914 21212 esp_riscv.c:321 esp_riscv_start_algorithm(): save s2
Debug: 2915 21215 riscv.c:3517 riscv_get_register(): [esp32c3] s2: 0 (cached)
Debug: 2916 21218 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from s2 (valid=1)
Debug: 2917 21222 esp_riscv.c:321 esp_riscv_start_algorithm(): save s3
Debug: 2918 21224 riscv.c:3517 riscv_get_register(): [esp32c3] s3: 0 (cached)
Debug: 2919 21227 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from s3 (valid=1)
Debug: 2920 21231 esp_riscv.c:321 esp_riscv_start_algorithm(): save s4
Debug: 2921 21233 riscv.c:3517 riscv_get_register(): [esp32c3] s4: 0 (cached)
Debug: 2922 21236 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from s4 (valid=1)
Debug: 2923 21240 esp_riscv.c:321 esp_riscv_start_algorithm(): save s5
Debug: 2924 21242 riscv.c:3517 riscv_get_register(): [esp32c3] s5: 0 (cached)
Debug: 2925 21245 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from s5 (valid=1)
Debug: 2926 21249 esp_riscv.c:321 esp_riscv_start_algorithm(): save s6
Debug: 2927 21252 riscv.c:3517 riscv_get_register(): [esp32c3] s6: 0 (cached)
Debug: 2928 21255 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from s6 (valid=1)
Debug: 2929 21258 esp_riscv.c:321 esp_riscv_start_algorithm(): save s7
Debug: 2930 21261 riscv.c:3517 riscv_get_register(): [esp32c3] s7: 0 (cached)
Debug: 2931 21264 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from s7 (valid=1)
Debug: 2932 21267 esp_riscv.c:321 esp_riscv_start_algorithm(): save s8
Debug: 2933 21270 riscv.c:3517 riscv_get_register(): [esp32c3] s8: 0 (cached)
Debug: 2934 21273 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from s8 (valid=1)
Debug: 2935 21276 esp_riscv.c:321 esp_riscv_start_algorithm(): save s9
Debug: 2936 21280 riscv.c:3517 riscv_get_register(): [esp32c3] s9: 0 (cached)
Debug: 2937 21283 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from s9 (valid=1)
Debug: 2938 21286 esp_riscv.c:321 esp_riscv_start_algorithm(): save s10
Debug: 2939 21289 riscv.c:3517 riscv_get_register(): [esp32c3] s10: 0 (cached)
Debug: 2940 21292 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from s10 (valid=1)
Debug: 2941 21296 esp_riscv.c:321 esp_riscv_start_algorithm(): save s11
Debug: 2942 21298 riscv.c:3517 riscv_get_register(): [esp32c3] s11: 0 (cached)
Debug: 2943 21301 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from s11 (valid=1)
Debug: 2944 21305 esp_riscv.c:321 esp_riscv_start_algorithm(): save t3
Debug: 2945 21308 riscv.c:3517 riscv_get_register(): [esp32c3] t3: 0 (cached)
Debug: 2946 21311 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from t3 (valid=1)
Debug: 2947 21314 esp_riscv.c:321 esp_riscv_start_algorithm(): save t4
Debug: 2948 21317 riscv.c:3517 riscv_get_register(): [esp32c3] t4: 0 (cached)
Debug: 2949 21320 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from t4 (valid=1)
Debug: 2950 21323 esp_riscv.c:321 esp_riscv_start_algorithm(): save t5
Debug: 2951 21327 riscv.c:3517 riscv_get_register(): [esp32c3] t5: 0 (cached)
Debug: 2952 21329 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from t5 (valid=1)
Debug: 2953 21333 esp_riscv.c:321 esp_riscv_start_algorithm(): save t6
Debug: 2954 21335 riscv.c:3517 riscv_get_register(): [esp32c3] t6: 0 (cached)
Debug: 2955 21338 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from t6 (valid=1)
Debug: 2956 21342 esp_riscv.c:321 esp_riscv_start_algorithm(): save pc
Debug: 2957 21345 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register pc
Debug: 2958 21348 riscv-013.c:800 execute_abstract_command(): command=0x2207b1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b1
Debug: 2959 21356 riscv-013.c:1504 register_read_direct(): {0} dpc = 0x4038aa24
Debug: 2960 21358 riscv-013.c:4095 riscv013_get_register(): [0] read PC from DPC: 0x4038aa24
Debug: 2961 21362 riscv.c:3534 riscv_get_register(): [esp32c3] pc: 4038aa24
Debug: 2962 21365 riscv.c:3888 register_get(): [esp32c3] read 0x4038aa24 from pc (valid=0)
Debug: 2963 21368 esp_riscv.c:321 esp_riscv_start_algorithm(): save mstatus
Debug: 2964 21372 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register mstatus
Debug: 2965 21375 riscv-013.c:800 execute_abstract_command(): command=0x220300; access register, size=32, postexec=0, transfer=1, write=0, regno=0x300
Debug: 2966 21382 riscv-013.c:1504 register_read_direct(): {0} mstatus = 0x81
Debug: 2967 21385 riscv.c:3534 riscv_get_register(): [esp32c3] mstatus: 81
Debug: 2968 21389 riscv.c:3888 register_get(): [esp32c3] read 0x00000081 from mstatus (valid=1)
Debug: 2969 21392 esp_riscv.c:321 esp_riscv_start_algorithm(): save misa
Debug: 2970 21395 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register misa
Debug: 2971 21398 riscv-013.c:800 execute_abstract_command(): command=0x220301; access register, size=32, postexec=0, transfer=1, write=0, regno=0x301
Debug: 2972 21406 riscv-013.c:1504 register_read_direct(): {0} misa = 0x40101104
Debug: 2973 21408 riscv.c:3534 riscv_get_register(): [esp32c3] misa: 40101104
Debug: 2974 21411 riscv.c:3888 register_get(): [esp32c3] read 0x40101104 from misa (valid=1)
Debug: 2975 21415 esp_riscv.c:321 esp_riscv_start_algorithm(): save mtvec
Debug: 2976 21418 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr773
Debug: 2977 21422 riscv-013.c:800 execute_abstract_command(): command=0x220305; access register, size=32, postexec=0, transfer=1, write=0, regno=0x305
Debug: 2978 21429 riscv-013.c:1504 register_read_direct(): {0} csr773 = 0x40380001
Debug: 2979 21432 riscv.c:3534 riscv_get_register(): [esp32c3] csr773: 40380001
Debug: 2980 21435 riscv.c:3888 register_get(): [esp32c3] read 0x40380001 from mtvec (valid=0)
Debug: 2981 21439 esp_riscv.c:321 esp_riscv_start_algorithm(): save mscratch
Debug: 2982 21441 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr832
Debug: 2983 21445 riscv-013.c:800 execute_abstract_command(): command=0x220340; access register, size=32, postexec=0, transfer=1, write=0, regno=0x340
Debug: 2984 21452 riscv-013.c:1504 register_read_direct(): {0} csr832 = 0x0
Debug: 2985 21455 riscv.c:3534 riscv_get_register(): [esp32c3] csr832: 0
Debug: 2986 21459 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from mscratch (valid=0)
Debug: 2987 21463 esp_riscv.c:321 esp_riscv_start_algorithm(): save mepc
Debug: 2988 21466 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register mepc
Debug: 2989 21469 riscv-013.c:800 execute_abstract_command(): command=0x220341; access register, size=32, postexec=0, transfer=1, write=0, regno=0x341
Debug: 2990 21477 riscv-013.c:1504 register_read_direct(): {0} mepc = 0x4038aaaa
Debug: 2991 21480 riscv.c:3534 riscv_get_register(): [esp32c3] mepc: 4038aaaa
Debug: 2992 21483 riscv.c:3888 register_get(): [esp32c3] read 0x4038aaaa from mepc (valid=1)
Debug: 2993 21486 esp_riscv.c:321 esp_riscv_start_algorithm(): save mcause
Debug: 2994 21489 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register mcause
Debug: 2995 21492 riscv-013.c:800 execute_abstract_command(): command=0x220342; access register, size=32, postexec=0, transfer=1, write=0, regno=0x342
Debug: 2996 21500 riscv-013.c:1504 register_read_direct(): {0} mcause = 0x80000009
Debug: 2997 21503 riscv.c:3534 riscv_get_register(): [esp32c3] mcause: 80000009
Debug: 2998 21506 riscv.c:3888 register_get(): [esp32c3] read 0x80000009 from mcause (valid=1)
Debug: 2999 21509 esp_riscv.c:321 esp_riscv_start_algorithm(): save mtval
Debug: 3000 21512 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr835
Debug: 3001 21516 riscv-013.c:800 execute_abstract_command(): command=0x220343; access register, size=32, postexec=0, transfer=1, write=0, regno=0x343
Debug: 3002 21523 riscv-013.c:1504 register_read_direct(): {0} csr835 = 0x8082
Debug: 3003 21525 riscv.c:3534 riscv_get_register(): [esp32c3] csr835: 8082
Debug: 3004 21529 riscv.c:3888 register_get(): [esp32c3] read 0x00008082 from mtval (valid=0)
Debug: 3005 21532 esp_riscv.c:321 esp_riscv_start_algorithm(): save pmpcfg0
Debug: 3006 21535 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr928
Debug: 3007 21538 riscv-013.c:800 execute_abstract_command(): command=0x2203a0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3a0
Debug: 3008 21546 riscv-013.c:1504 register_read_direct(): {0} csr928 = 0x89888f88
Debug: 3009 21549 riscv.c:3534 riscv_get_register(): [esp32c3] csr928: 89888f88
Debug: 3010 21552 riscv.c:3888 register_get(): [esp32c3] read 0x89888f88 from pmpcfg0 (valid=0)
Debug: 3011 21555 esp_riscv.c:321 esp_riscv_start_algorithm(): save pmpcfg1
Debug: 3012 21559 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr929
Debug: 3013 21562 riscv-013.c:800 execute_abstract_command(): command=0x2203a1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3a1
Debug: 3014 21569 riscv-013.c:1504 register_read_direct(): {0} csr929 = 0x888d898b
Debug: 3015 21572 riscv.c:3534 riscv_get_register(): [esp32c3] csr929: 888d898b
Debug: 3016 21575 riscv.c:3888 register_get(): [esp32c3] read 0x888d898b from pmpcfg1 (valid=0)
Debug: 3017 21579 esp_riscv.c:321 esp_riscv_start_algorithm(): save pmpcfg2
Debug: 3018 21582 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr930
Debug: 3019 21585 riscv-013.c:800 execute_abstract_command(): command=0x2203a2; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3a2
Debug: 3020 21593 riscv-013.c:1504 register_read_direct(): {0} csr930 = 0x8f888d8f
Debug: 3021 21596 riscv.c:3534 riscv_get_register(): [esp32c3] csr930: 8f888d8f
Debug: 3022 21599 riscv.c:3888 register_get(): [esp32c3] read 0x8f888d8f from pmpcfg2 (valid=0)
Debug: 3023 21602 esp_riscv.c:321 esp_riscv_start_algorithm(): save pmpcfg3
Debug: 3024 21606 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr931
Debug: 3025 21609 riscv-013.c:800 execute_abstract_command(): command=0x2203a3; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3a3
Debug: 3026 21617 riscv-013.c:1504 register_read_direct(): {0} csr931 = 0x90888b88
Debug: 3027 21620 riscv.c:3534 riscv_get_register(): [esp32c3] csr931: 90888b88
Debug: 3028 21623 riscv.c:3888 register_get(): [esp32c3] read 0x90888b88 from pmpcfg3 (valid=0)
Debug: 3029 21627 esp_riscv.c:321 esp_riscv_start_algorithm(): save pmpaddr0
Debug: 3030 21630 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr944
Debug: 3031 21633 riscv-013.c:800 execute_abstract_command(): command=0x2203b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b0
Debug: 3032 21641 riscv-013.c:1504 register_read_direct(): {0} csr944 = 0x8000000
Debug: 3033 21644 riscv.c:3534 riscv_get_register(): [esp32c3] csr944: 8000000
Debug: 3034 21647 riscv.c:3888 register_get(): [esp32c3] read 0x08000000 from pmpaddr0 (valid=0)
Debug: 3035 21650 esp_riscv.c:321 esp_riscv_start_algorithm(): save pmpaddr1
Debug: 3036 21653 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr945
Debug: 3037 21657 riscv-013.c:800 execute_abstract_command(): command=0x2203b1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b1
Debug: 3038 21664 riscv-013.c:1504 register_read_direct(): {0} csr945 = 0xa000000
Debug: 3039 21668 riscv.c:3534 riscv_get_register(): [esp32c3] csr945: a000000
Debug: 3040 21670 riscv.c:3888 register_get(): [esp32c3] read 0x0a000000 from pmpaddr1 (valid=0)
Debug: 3041 21674 esp_riscv.c:321 esp_riscv_start_algorithm(): save pmpaddr2
Debug: 3042 21677 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr946
Debug: 3043 21681 riscv-013.c:800 execute_abstract_command(): command=0x2203b2; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b2
Debug: 3044 21688 riscv-013.c:1504 register_read_direct(): {0} csr946 = 0xf000000
Debug: 3045 21690 riscv.c:3534 riscv_get_register(): [esp32c3] csr946: f000000
Debug: 3046 21693 riscv.c:3888 register_get(): [esp32c3] read 0x0f000000 from pmpaddr2 (valid=0)
Debug: 3047 21697 esp_riscv.c:321 esp_riscv_start_algorithm(): save pmpaddr3
Debug: 3048 21700 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr947
Debug: 3049 21704 riscv-013.c:800 execute_abstract_command(): command=0x2203b3; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b3
Debug: 3050 21711 riscv-013.c:1504 register_read_direct(): {0} csr947 = 0xff20000
Debug: 3051 21714 riscv.c:3534 riscv_get_register(): [esp32c3] csr947: ff20000
Debug: 3052 21717 riscv.c:3888 register_get(): [esp32c3] read 0x0ff20000 from pmpaddr3 (valid=0)
Debug: 3053 21722 esp_riscv.c:321 esp_riscv_start_algorithm(): save pmpaddr4
Debug: 3054 21725 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr948
Debug: 3055 21728 riscv-013.c:800 execute_abstract_command(): command=0x2203b4; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b4
Debug: 3056 21736 riscv-013.c:1504 register_read_direct(): {0} csr948 = 0xff38000
Debug: 3057 21739 riscv.c:3534 riscv_get_register(): [esp32c3] csr948: ff38000
Debug: 3058 21742 riscv.c:3888 register_get(): [esp32c3] read 0x0ff38000 from pmpaddr4 (valid=0)
Debug: 3059 21745 esp_riscv.c:321 esp_riscv_start_algorithm(): save pmpaddr5
Debug: 3060 21748 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr949
Debug: 3061 21752 riscv-013.c:800 execute_abstract_command(): command=0x2203b5; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b5
Debug: 3062 21759 riscv-013.c:1504 register_read_direct(): {0} csr949 = 0xffc8000
Debug: 3063 21762 riscv.c:3534 riscv_get_register(): [esp32c3] csr949: ffc8000
Debug: 3064 21765 riscv.c:3888 register_get(): [esp32c3] read 0x0ffc8000 from pmpaddr5 (valid=0)
Debug: 3065 21769 esp_riscv.c:321 esp_riscv_start_algorithm(): save pmpaddr6
Debug: 3066 21772 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr950
Debug: 3067 21775 riscv-013.c:800 execute_abstract_command(): command=0x2203b6; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b6
Debug: 3068 21783 riscv-013.c:1504 register_read_direct(): {0} csr950 = 0x10018000
Debug: 3069 21786 riscv.c:3534 riscv_get_register(): [esp32c3] csr950: 10018000
Debug: 3070 21789 riscv.c:3888 register_get(): [esp32c3] read 0x10018000 from pmpaddr6 (valid=0)
Debug: 3071 21793 esp_riscv.c:321 esp_riscv_start_algorithm(): save pmpaddr7
Debug: 3072 21796 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr951
Debug: 3073 21799 riscv-013.c:800 execute_abstract_command(): command=0x2203b7; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b7
Debug: 3074 21806 riscv-013.c:1504 register_read_direct(): {0} csr951 = 0x100df000
Debug: 3075 21810 riscv.c:3534 riscv_get_register(): [esp32c3] csr951: 100df000
Debug: 3076 21813 riscv.c:3888 register_get(): [esp32c3] read 0x100df000 from pmpaddr7 (valid=0)
Debug: 3077 21816 esp_riscv.c:321 esp_riscv_start_algorithm(): save pmpaddr8
Debug: 3078 21819 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr952
Debug: 3079 21823 riscv-013.c:800 execute_abstract_command(): command=0x2203b8; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b8
Debug: 3080 21831 riscv-013.c:1504 register_read_direct(): {0} csr952 = 0x100f8000
Debug: 3081 21833 riscv.c:3534 riscv_get_register(): [esp32c3] csr952: 100f8000
Debug: 3082 21836 riscv.c:3888 register_get(): [esp32c3] read 0x100f8000 from pmpaddr8 (valid=0)
Debug: 3083 21840 esp_riscv.c:321 esp_riscv_start_algorithm(): save pmpaddr9
Debug: 3084 21843 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr953
Debug: 3085 21847 riscv-013.c:800 execute_abstract_command(): command=0x2203b9; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3b9
Debug: 3086 21854 riscv-013.c:1504 register_read_direct(): {0} csr953 = 0x10a00000
Debug: 3087 21857 riscv.c:3534 riscv_get_register(): [esp32c3] csr953: 10a00000
Debug: 3088 21860 riscv.c:3888 register_get(): [esp32c3] read 0x10a00000 from pmpaddr9 (valid=0)
Debug: 3089 21864 esp_riscv.c:321 esp_riscv_start_algorithm(): save pmpaddr10
Debug: 3090 21867 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr954
Debug: 3091 21870 riscv-013.c:800 execute_abstract_command(): command=0x2203ba; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3ba
Debug: 3092 21878 riscv-013.c:1504 register_read_direct(): {0} csr954 = 0x14000000
Debug: 3093 21881 riscv.c:3534 riscv_get_register(): [esp32c3] csr954: 14000000
Debug: 3094 21884 riscv.c:3888 register_get(): [esp32c3] read 0x14000000 from pmpaddr10 (valid=0)
Debug: 3095 21888 esp_riscv.c:321 esp_riscv_start_algorithm(): save pmpaddr11
Debug: 3096 21891 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr955
Debug: 3097 21894 riscv-013.c:800 execute_abstract_command(): command=0x2203bb; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3bb
Debug: 3098 21902 riscv-013.c:1504 register_read_direct(): {0} csr955 = 0x14000800
Debug: 3099 21905 riscv.c:3534 riscv_get_register(): [esp32c3] csr955: 14000800
Debug: 3100 21908 riscv.c:3888 register_get(): [esp32c3] read 0x14000800 from pmpaddr11 (valid=0)
Debug: 3101 21912 esp_riscv.c:321 esp_riscv_start_algorithm(): save pmpaddr12
Debug: 3102 21915 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr956
Debug: 3103 21918 riscv-013.c:800 execute_abstract_command(): command=0x2203bc; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3bc
Debug: 3104 21926 riscv-013.c:1504 register_read_direct(): {0} csr956 = 0x18000000
Debug: 3105 21929 riscv.c:3534 riscv_get_register(): [esp32c3] csr956: 18000000
Debug: 3106 21932 riscv.c:3888 register_get(): [esp32c3] read 0x18000000 from pmpaddr12 (valid=0)
Debug: 3107 21936 esp_riscv.c:321 esp_riscv_start_algorithm(): save pmpaddr13
Debug: 3108 21939 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr957
Debug: 3109 21943 riscv-013.c:800 execute_abstract_command(): command=0x2203bd; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3bd
Debug: 3110 21950 riscv-013.c:1504 register_read_direct(): {0} csr957 = 0x18040000
Debug: 3111 21953 riscv.c:3534 riscv_get_register(): [esp32c3] csr957: 18040000
Debug: 3112 21957 riscv.c:3888 register_get(): [esp32c3] read 0x18040000 from pmpaddr13 (valid=0)
Debug: 3113 21960 esp_riscv.c:321 esp_riscv_start_algorithm(): save pmpaddr14
Debug: 3114 21963 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr958
Debug: 3115 21967 riscv-013.c:800 execute_abstract_command(): command=0x2203be; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3be
Debug: 3116 21975 riscv-013.c:1504 register_read_direct(): {0} csr958 = 0x3fffffff
Debug: 3117 21978 riscv.c:3534 riscv_get_register(): [esp32c3] csr958: 3fffffff
Debug: 3118 21981 riscv.c:3888 register_get(): [esp32c3] read 0x3fffffff from pmpaddr14 (valid=0)
Debug: 3119 21985 esp_riscv.c:321 esp_riscv_start_algorithm(): save pmpaddr15
Debug: 3120 21989 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr959
Debug: 3121 21992 riscv-013.c:800 execute_abstract_command(): command=0x2203bf; access register, size=32, postexec=0, transfer=1, write=0, regno=0x3bf
Debug: 3122 21999 riscv-013.c:1504 register_read_direct(): {0} csr959 = 0x3fffffff
Debug: 3123 22002 riscv.c:3534 riscv_get_register(): [esp32c3] csr959: 3fffffff
Debug: 3124 22005 riscv.c:3888 register_get(): [esp32c3] read 0x3fffffff from pmpaddr15 (valid=0)
Debug: 3125 22009 esp_riscv.c:321 esp_riscv_start_algorithm(): save tselect
Debug: 3126 22012 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register tselect
Debug: 3127 22016 riscv-013.c:800 execute_abstract_command(): command=0x2207a0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a0
Debug: 3128 22025 riscv-013.c:1504 register_read_direct(): {0} tselect = 0x0
Debug: 3129 22029 riscv.c:3534 riscv_get_register(): [esp32c3] tselect: 0
Debug: 3130 22033 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from tselect (valid=0)
Debug: 3131 22037 esp_riscv.c:321 esp_riscv_start_algorithm(): save tdata1
Debug: 3132 22039 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register tdata1
Debug: 3133 22043 riscv-013.c:800 execute_abstract_command(): command=0x2207a1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a1
Debug: 3134 22051 riscv-013.c:1504 register_read_direct(): {0} tdata1 = 0x23e00000
Debug: 3135 22053 riscv.c:3534 riscv_get_register(): [esp32c3] tdata1: 23e00000
Debug: 3136 22056 riscv.c:3888 register_get(): [esp32c3] read 0x23e00000 from tdata1 (valid=0)
Debug: 3137 22060 esp_riscv.c:321 esp_riscv_start_algorithm(): save tdata2
Debug: 3138 22063 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register tdata2
Debug: 3139 22067 riscv-013.c:800 execute_abstract_command(): command=0x2207a2; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a2
Debug: 3140 22074 riscv-013.c:1504 register_read_direct(): {0} tdata2 = 0x0
Debug: 3141 22077 riscv.c:3534 riscv_get_register(): [esp32c3] tdata2: 0
Debug: 3142 22080 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from tdata2 (valid=0)
Debug: 3143 22083 esp_riscv.c:321 esp_riscv_start_algorithm(): save tcontrol
Debug: 3144 22086 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr1957
Debug: 3145 22089 riscv-013.c:800 execute_abstract_command(): command=0x2207a5; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7a5
Debug: 3146 22097 riscv-013.c:1504 register_read_direct(): {0} csr1957 = 0x88
Debug: 3147 22100 riscv.c:3534 riscv_get_register(): [esp32c3] csr1957: 88
Debug: 3148 22102 riscv.c:3888 register_get(): [esp32c3] read 0x00000088 from tcontrol (valid=0)
Debug: 3149 22106 esp_riscv.c:321 esp_riscv_start_algorithm(): save dcsr
Debug: 3150 22109 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register dcsr
Debug: 3151 22113 riscv-013.c:800 execute_abstract_command(): command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0
Debug: 3152 22120 riscv-013.c:1504 register_read_direct(): {0} dcsr = 0x400000c3
Debug: 3153 22123 riscv.c:3534 riscv_get_register(): [esp32c3] dcsr: 400000c3
Debug: 3154 22126 riscv.c:3888 register_get(): [esp32c3] read 0x400000c3 from dcsr (valid=1)
Debug: 3155 22129 esp_riscv.c:321 esp_riscv_start_algorithm(): save dpc
Debug: 3156 22132 riscv.c:3517 riscv_get_register(): [esp32c3] dpc: 4038aa24 (cached)
Debug: 3157 22135 riscv.c:3888 register_get(): [esp32c3] read 0x4038aa24 from dpc (valid=1)
Debug: 3158 22139 esp_riscv.c:321 esp_riscv_start_algorithm(): save dscratch0
Debug: 3159 22142 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register dscratch0
Debug: 3160 22146 riscv-013.c:800 execute_abstract_command(): command=0x2207b2; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b2
Debug: 3161 22153 riscv-013.c:1504 register_read_direct(): {0} dscratch0 = 0x0
Debug: 3162 22156 riscv.c:3534 riscv_get_register(): [esp32c3] dscratch0: 0
Debug: 3163 22159 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from dscratch0 (valid=1)
Debug: 3164 22162 esp_riscv.c:321 esp_riscv_start_algorithm(): save dscratch1
Debug: 3165 22165 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr1971
Debug: 3166 22169 riscv-013.c:800 execute_abstract_command(): command=0x2207b3; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b3
Debug: 3167 22176 riscv-013.c:1504 register_read_direct(): {0} csr1971 = 0x1
Debug: 3168 22179 riscv.c:3534 riscv_get_register(): [esp32c3] csr1971: 1
Debug: 3169 22182 riscv.c:3888 register_get(): [esp32c3] read 0x00000001 from dscratch1 (valid=0)
Debug: 3170 22185 esp_riscv.c:321 esp_riscv_start_algorithm(): save hpmcounter16
Debug: 3171 22189 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register csr3088
Debug: 3172 22192 riscv-013.c:800 execute_abstract_command(): command=0x220c10; access register, size=32, postexec=0, transfer=1, write=0, regno=0xc10
Debug: 3173 22200 riscv-013.c:1504 register_read_direct(): {0} csr3088 = 0x3
Debug: 3174 22203 riscv.c:3534 riscv_get_register(): [esp32c3] csr3088: 3
Debug: 3175 22206 riscv.c:3888 register_get(): [esp32c3] read 0x00000003 from hpmcounter16 (valid=0)
Debug: 3176 22210 esp_riscv.c:321 esp_riscv_start_algorithm(): save priv
Debug: 3177 22212 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register priv
Debug: 3178 22216 riscv-013.c:800 execute_abstract_command(): command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0
Debug: 3179 22224 riscv-013.c:1504 register_read_direct(): {0} dcsr = 0x400000c3
Debug: 3180 22226 riscv.c:3534 riscv_get_register(): [esp32c3] priv: 3
Debug: 3181 22229 riscv.c:3888 register_get(): [esp32c3] read 0x03 from priv (valid=0)
Debug: 3182 22232 esp_riscv.c:350 esp_riscv_start_algorithm(): set sp
Debug: 3183 22236 riscv.c:3901 register_set(): [esp32c3] write 0x3fc84810 to sp (valid=1)
Debug: 3184 22240 riscv.c:3477 riscv_set_register(): [esp32c3] sp <- 3fc84810
Debug: 3185 22244 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x3fc84810 to register sp
Debug: 3186 22248 riscv-013.c:1315 register_write_direct(): {0} sp <- 0x3fc84810
Debug: 3187 22253 riscv-013.c:800 execute_abstract_command(): command=0x231002; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1002
Debug: 3188 22259 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x3fc84810 to sp valid=1
Debug: 3189 22263 esp_riscv.c:350 esp_riscv_start_algorithm(): set a7
Debug: 3190 22266 riscv.c:3901 register_set(): [esp32c3] write 0x403810d2 to a7 (valid=1)
Debug: 3191 22269 riscv.c:3477 riscv_set_register(): [esp32c3] a7 <- 403810d2
Debug: 3192 22272 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x403810d2 to register a7
Debug: 3193 22276 riscv-013.c:1315 register_write_direct(): {0} a7 <- 0x403810d2
Debug: 3194 22279 riscv-013.c:800 execute_abstract_command(): command=0x231011; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1011
Debug: 3195 22287 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x403810d2 to a7 valid=1
Debug: 3196 22290 esp_riscv.c:350 esp_riscv_start_algorithm(): set a0
Debug: 3197 22293 riscv.c:3901 register_set(): [esp32c3] write 0x00000004 to a0 (valid=1)
Debug: 3198 22296 riscv.c:3477 riscv_set_register(): [esp32c3] a0 <- 4
Debug: 3199 22299 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x4 to register a0
Debug: 3200 22303 riscv-013.c:1315 register_write_direct(): {0} a0 <- 0x4
Debug: 3201 22306 riscv-013.c:800 execute_abstract_command(): command=0x23100a; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100a
Debug: 3202 22313 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x4 to a0 valid=1
Debug: 3203 22316 riscv.c:3293 riscv_interrupts_disable(): Disabling Interrupts
Debug: 3204 22319 riscv.c:3517 riscv_get_register(): [esp32c3] mstatus: 81 (cached)
Debug: 3205 22322 riscv.c:3888 register_get(): [esp32c3] read 0x00000081 from mstatus (valid=1)
Debug: 3206 22326 riscv.c:3901 register_set(): [esp32c3] write 0x00000080 to mstatus (valid=1)
Debug: 3207 22330 riscv.c:3477 riscv_set_register(): [esp32c3] mstatus <- 80
Debug: 3208 22333 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x80 to register mstatus
Debug: 3209 22336 riscv-013.c:1315 register_write_direct(): {0} mstatus <- 0x80
Debug: 3210 22339 riscv-013.c:800 execute_abstract_command(): command=0x230300; access register, size=32, postexec=0, transfer=1, write=1, regno=0x300
Debug: 3211 22347 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x80 to mstatus valid=0
Debug: 3212 22350 esp_riscv.c:387 esp_riscv_start_algorithm(): resume at 0x40381ce4
Debug: 3213 22353 riscv.c:1472 riscv_resume(): handle_breakpoints=0
Debug: 3214 22356 riscv.c:1399 resume_prep(): [0]
Debug: 3215 22358 riscv.c:3477 riscv_set_register(): [esp32c3] pc <- 40381ce4
Debug: 3216 22361 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x40381ce4 to register pc
Debug: 3217 22365 riscv-013.c:4120 riscv013_set_register(): [0] writing PC to DPC: 0x40381ce4
Debug: 3218 22368 riscv-013.c:1315 register_write_direct(): {0} dpc <- 0x40381ce4
Debug: 3219 22371 riscv-013.c:800 execute_abstract_command(): command=0x2307b1; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b1
Debug: 3220 22378 riscv-013.c:800 execute_abstract_command(): command=0x2207b1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b1
Debug: 3221 22385 riscv-013.c:1504 register_read_direct(): {0} dpc = 0x40381ce4
Debug: 3222 22389 riscv-013.c:4124 riscv013_set_register(): [0]   actual DPC written: 0x0000000040381ce4
Debug: 3223 22393 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x40381ce4 to pc valid=0
Debug: 3224 22396 riscv.c:1289 riscv_resume_prep_all_harts(): [esp32c3] prep hart
Debug: 3225 22400 program.c:35 riscv_program_write(): debug_buffer[00] = DASM(0x0000100f)
Debug: 3226 22403 riscv-013.c:4381 riscv013_write_debug_buffer(): cache hit for 0x100f @0
Debug: 3227 22407 program.c:35 riscv_program_write(): debug_buffer[01] = DASM(0x0000000f)
Debug: 3228 22410 riscv-013.c:4381 riscv013_write_debug_buffer(): cache hit for 0xf @1
Debug: 3229 22413 program.c:35 riscv_program_write(): debug_buffer[02] = DASM(0x00100073)
Debug: 3230 22416 riscv-013.c:4381 riscv013_write_debug_buffer(): cache hit for 0x100073 @2
Debug: 3231 22419 riscv-013.c:800 execute_abstract_command(): command=0x241000; access register, size=32, postexec=1, transfer=0, write=0, regno=0x1000
Debug: 3232 22428 riscv-013.c:800 execute_abstract_command(): command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0
Debug: 3233 22434 riscv-013.c:1504 register_read_direct(): {0} dcsr = 0x400000c3
Debug: 3234 22437 riscv.c:3477 riscv_set_register(): [esp32c3] dcsr <- 4000b0c3
Debug: 3235 22441 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x4000b0c3 to register dcsr
Debug: 3236 22444 riscv-013.c:1315 register_write_direct(): {0} dcsr <- 0x4000b0c3
Debug: 3237 22448 riscv-013.c:800 execute_abstract_command(): command=0x2307b0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b0
Debug: 3238 22454 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x4000b0c3 to dcsr valid=0
Debug: 3239 22459 riscv.c:1300 riscv_resume_prep_all_harts(): [esp32c3] mark as prepped
Debug: 3240 22462 riscv.c:1424 resume_prep(): [0] mark as prepped
Debug: 3241 22465 riscv.c:3276 riscv_resume_go_all_harts(): [esp32c3] resuming hart
Debug: 3242 22468 riscv-013.c:4190 select_prepped_harts(): index=0, coreid=0, prepped=1
Debug: 3243 22472 riscv-013.c:4815 riscv013_step_or_resume_current_hart(): resuming hart 0 (for step?=0)
Debug: 3244 22478 riscv.c:3397 riscv_invalidate_register_cache(): [0]
Debug: 3245 22480 target.c:1860 target_call_event_callbacks(): target event 18 (debug-resumed) for core esp32c3
Debug: 3246 22484 esp32c3.c:188 esp32c3_handle_target_event(): 18
Debug: 3247 22488 esp_riscv.c:281 esp_riscv_handle_target_event(): 18
Debug: 3248 22490 esp_algorithm.c:218 algorithm_run(): Wait algorithm completion
Debug: 3249 22493 riscv.c:2078 riscv_poll_hart():   triggered a halt
Debug: 3250 22496 riscv.c:2258 riscv_openocd_poll():   hart 0 halted
Debug: 3251 22499 riscv-013.c:800 execute_abstract_command(): command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0
Debug: 3252 22507 riscv-013.c:1504 register_read_direct(): {0} dcsr = 0x4000b043
Debug: 3253 22510 riscv-013.c:4345 riscv013_halt_reason(): dcsr.cause: 0x1
Debug: 3254 22512 riscv.c:2113 set_debug_reason(): [esp32c3] debug_reason=1
Debug: 3255 22515 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register pc
Debug: 3256 22519 riscv-013.c:800 execute_abstract_command(): command=0x2207b1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b1
Debug: 3257 22526 riscv-013.c:1504 register_read_direct(): {0} dpc = 0x40381ce6
Debug: 3258 22529 riscv-013.c:4095 riscv013_get_register(): [0] read PC from DPC: 0x40381ce6
Debug: 3259 22532 riscv.c:3534 riscv_get_register(): [esp32c3] pc: 40381ce6
Debug: 3260 22535 esp_riscv.c:529 esp_riscv_read_memory(): Use 32-bit access: size: 2   count:2 start address: 0x40381ce2
Debug: 3261 22544 riscv-013.c:2858 log_mem_access_result(): Succeeded to read memory via system bus.
Debug: 3262 22547 esp_riscv.c:529 esp_riscv_read_memory(): Use 32-bit access: size: 2   count:2 start address: 0x40381ce6
Debug: 3263 22556 riscv-013.c:2858 log_mem_access_result(): Succeeded to read memory via system bus.
Debug: 3264 22559 esp_riscv.c:529 esp_riscv_read_memory(): Use 32-bit access: size: 2   count:2 start address: 0x40381cea
Debug: 3265 22567 riscv-013.c:2858 log_mem_access_result(): Succeeded to read memory via system bus.
Debug: 3266 22570 riscv_semihosting.c:108 riscv_semihosting(): check 9882bd19 85269002 446240f2 from 0x40381ce6-4
Debug: 3267 22575 riscv_semihosting.c:112 riscv_semihosting():    -> NONE (no magic)
Debug: 3268 22578 target.c:1860 target_call_event_callbacks(): target event 0 (gdb-halt) for core esp32c3
Debug: 3269 22582 esp32c3.c:188 esp32c3_handle_target_event(): 0
Debug: 3270 22584 esp_riscv.c:281 esp_riscv_handle_target_event(): 0
Debug: 3271 22587 target.c:1860 target_call_event_callbacks(): target event 1 (halted) for core esp32c3
Debug: 3272 22591 target.c:5153 target_handle_event(): target(0): esp32c3 (esp32c3) event: 1 (halted) action:
    esp32c3_wdt_disable

Debug: 3273 22596 command.c:166 script_debug(): command - command mode
Debug: 3274 22600 command.c:166 script_debug(): command - mww 0x6001f064 0x50D83AA1
Debug: 3275 22605 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x6001f064
Debug: 3276 22609 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 3277 22613 command.c:166 script_debug(): command - mww 0x6001F048 0
Debug: 3278 22618 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x6001f048
Debug: 3279 22622 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 3280 22626 command.c:166 script_debug(): command - mww 0x60020064 0x50D83AA1
Debug: 3281 22632 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x60020064
Debug: 3282 22637 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 3283 22640 command.c:166 script_debug(): command - mww 0x60020048 0
Debug: 3284 22645 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x60020048
Debug: 3285 22650 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 3286 22653 command.c:166 script_debug(): command - mww 0x600080a8 0x50D83AA1
Debug: 3287 22658 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x600080a8
Debug: 3288 22663 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 3289 22666 command.c:166 script_debug(): command - mww 0x60008090 0
Debug: 3290 22671 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x60008090
Debug: 3291 22676 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 3292 22679 command.c:166 script_debug(): command - mww 0x600080b0 0x8F1D312A
Debug: 3293 22685 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x600080b0
Debug: 3294 22690 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 3295 22694 command.c:166 script_debug(): command - mww 0x600080ac 0x84B00000
Debug: 3296 22699 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x600080ac
Debug: 3297 22704 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 3298 22708 esp32c3.c:188 esp32c3_handle_target_event(): 1
Debug: 3299 22710 esp_riscv.c:281 esp_riscv_handle_target_event(): 1
Debug: 3300 22713 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register pc
Debug: 3301 22716 riscv-013.c:800 execute_abstract_command(): command=0x2207b1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b1
Debug: 3302 22724 riscv-013.c:1504 register_read_direct(): {0} dpc = 0x40381ce6
Debug: 3303 22727 riscv-013.c:4095 riscv013_get_register(): [0] read PC from DPC: 0x40381ce6
Debug: 3304 22730 riscv.c:3534 riscv_get_register(): [esp32c3] pc: 40381ce6
Debug: 3305 22733 riscv.c:3888 register_get(): [esp32c3] read 0x40381ce6 from pc (valid=0)
Debug: 3306 22736 riscv-013.c:4086 riscv013_get_register(): [esp32c3] reading register a0
Debug: 3307 22740 riscv-013.c:800 execute_abstract_command(): command=0x22100a; access register, size=32, postexec=0, transfer=1, write=0, regno=0x100a
Debug: 3308 22748 riscv-013.c:1504 register_read_direct(): {0} a0 = 0x0
Debug: 3309 22750 riscv.c:3534 riscv_get_register(): [esp32c3] a0: 0
Debug: 3310 22754 riscv.c:3888 register_get(): [esp32c3] read 0x00000000 from a0 (valid=1)
Debug: 3311 22757 esp_riscv.c:465 esp_riscv_wait_algorithm(): Read mem params
Debug: 3312 22760 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore ra
Debug: 3313 22763 riscv.c:3901 register_set(): [esp32c3] write 0x4038aa78 to ra (valid=0)
Debug: 3314 22766 riscv.c:3477 riscv_set_register(): [esp32c3] ra <- 4038aa78
Debug: 3315 22769 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x4038aa78 to register ra
Debug: 3316 22773 riscv-013.c:1315 register_write_direct(): {0} ra <- 0x4038aa78
Debug: 3317 22777 riscv-013.c:800 execute_abstract_command(): command=0x231001; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1001
Debug: 3318 22784 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x4038aa78 to ra valid=1
Debug: 3319 22788 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore sp
Debug: 3320 22790 riscv.c:3901 register_set(): [esp32c3] write 0x3fca8080 to sp (valid=0)
Debug: 3321 22794 riscv.c:3477 riscv_set_register(): [esp32c3] sp <- 3fca8080
Debug: 3322 22798 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x3fca8080 to register sp
Debug: 3323 22802 riscv-013.c:1315 register_write_direct(): {0} sp <- 0x3fca8080
Debug: 3324 22807 riscv-013.c:800 execute_abstract_command(): command=0x231002; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1002
Debug: 3325 22814 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x3fca8080 to sp valid=1
Debug: 3326 22818 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore gp
Debug: 3327 22821 riscv.c:3901 register_set(): [esp32c3] write 0x3fc8fc00 to gp (valid=0)
Debug: 3328 22824 riscv.c:3477 riscv_set_register(): [esp32c3] gp <- 3fc8fc00
Debug: 3329 22827 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x3fc8fc00 to register gp
Debug: 3330 22831 riscv-013.c:1315 register_write_direct(): {0} gp <- 0x3fc8fc00
Debug: 3331 22836 riscv-013.c:800 execute_abstract_command(): command=0x231003; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1003
Debug: 3332 22843 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x3fc8fc00 to gp valid=1
Debug: 3333 22847 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore tp
Debug: 3334 22850 riscv.c:3901 register_set(): [esp32c3] write 0x3fc97820 to tp (valid=0)
Debug: 3335 22853 riscv.c:3477 riscv_set_register(): [esp32c3] tp <- 3fc97820
Debug: 3336 22857 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x3fc97820 to register tp
Debug: 3337 22860 riscv-013.c:1315 register_write_direct(): {0} tp <- 0x3fc97820
Debug: 3338 22865 riscv-013.c:800 execute_abstract_command(): command=0x231004; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1004
Debug: 3339 22872 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x3fc97820 to tp valid=1
Debug: 3340 22875 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore t0
Debug: 3341 22878 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to t0 (valid=0)
Debug: 3342 22882 riscv.c:3477 riscv_set_register(): [esp32c3] t0 <- 0
Debug: 3343 22885 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register t0
Debug: 3344 22889 riscv-013.c:1315 register_write_direct(): {0} t0 <- 0x0
Debug: 3345 22892 riscv-013.c:800 execute_abstract_command(): command=0x231005; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1005
Debug: 3346 22900 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to t0 valid=1
Debug: 3347 22903 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore t1
Debug: 3348 22906 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to t1 (valid=0)
Debug: 3349 22910 riscv.c:3477 riscv_set_register(): [esp32c3] t1 <- 0
Debug: 3350 22913 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register t1
Debug: 3351 22916 riscv-013.c:1315 register_write_direct(): {0} t1 <- 0x0
Debug: 3352 22920 riscv-013.c:800 execute_abstract_command(): command=0x231006; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1006
Debug: 3353 22928 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to t1 valid=1
Debug: 3354 22931 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore t2
Debug: 3355 22934 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to t2 (valid=0)
Debug: 3356 22937 riscv.c:3477 riscv_set_register(): [esp32c3] t2 <- 0
Debug: 3357 22941 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register t2
Debug: 3358 22944 riscv-013.c:1315 register_write_direct(): {0} t2 <- 0x0
Debug: 3359 22948 riscv-013.c:800 execute_abstract_command(): command=0x231007; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1007
Debug: 3360 22955 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to t2 valid=1
Debug: 3361 22958 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore fp
Debug: 3362 22961 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to fp (valid=0)
Debug: 3363 22965 riscv.c:3477 riscv_set_register(): [esp32c3] s0 <- 0
Debug: 3364 22968 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register s0
Debug: 3365 22971 riscv-013.c:1315 register_write_direct(): {0} s0 <- 0x0
Debug: 3366 22975 riscv-013.c:800 execute_abstract_command(): command=0x231008; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1008
Debug: 3367 22982 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to fp valid=1
Debug: 3368 22985 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore s1
Debug: 3369 22988 riscv.c:3901 register_set(): [esp32c3] write 0x00000001 to s1 (valid=0)
Debug: 3370 22991 riscv.c:3477 riscv_set_register(): [esp32c3] s1 <- 1
Debug: 3371 22994 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x1 to register s1
Debug: 3372 22998 riscv-013.c:1315 register_write_direct(): {0} s1 <- 0x1
Debug: 3373 23001 riscv-013.c:800 execute_abstract_command(): command=0x231009; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1009
Debug: 3374 23009 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x1 to s1 valid=1
Debug: 3375 23012 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore a0
Debug: 3376 23015 riscv.c:3901 register_set(): [esp32c3] write 0x00000001 to a0 (valid=1)
Debug: 3377 23019 riscv.c:3477 riscv_set_register(): [esp32c3] a0 <- 1
Debug: 3378 23022 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x1 to register a0
Debug: 3379 23026 riscv-013.c:1315 register_write_direct(): {0} a0 <- 0x1
Debug: 3380 23030 riscv-013.c:800 execute_abstract_command(): command=0x23100a; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100a
Debug: 3381 23037 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x1 to a0 valid=1
Debug: 3382 23041 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore a1
Debug: 3383 23044 riscv.c:3901 register_set(): [esp32c3] write 0x3fca809f to a1 (valid=0)
Debug: 3384 23047 riscv.c:3477 riscv_set_register(): [esp32c3] a1 <- 3fca809f
Debug: 3385 23050 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x3fca809f to register a1
Debug: 3386 23054 riscv-013.c:1315 register_write_direct(): {0} a1 <- 0x3fca809f
Debug: 3387 23058 riscv-013.c:800 execute_abstract_command(): command=0x23100b; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100b
Debug: 3388 23065 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x3fca809f to a1 valid=1
Debug: 3389 23069 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore a2
Debug: 3390 23072 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to a2 (valid=0)
Debug: 3391 23076 riscv.c:3477 riscv_set_register(): [esp32c3] a2 <- 0
Debug: 3392 23078 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register a2
Debug: 3393 23082 riscv-013.c:1315 register_write_direct(): {0} a2 <- 0x0
Debug: 3394 23086 riscv-013.c:800 execute_abstract_command(): command=0x23100c; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100c
Debug: 3395 23093 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to a2 valid=1
Debug: 3396 23096 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore a3
Debug: 3397 23099 riscv.c:3901 register_set(): [esp32c3] write 0x00000004 to a3 (valid=0)
Debug: 3398 23103 riscv.c:3477 riscv_set_register(): [esp32c3] a3 <- 4
Debug: 3399 23106 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x4 to register a3
Debug: 3400 23109 riscv-013.c:1315 register_write_direct(): {0} a3 <- 0x4
Debug: 3401 23113 riscv-013.c:800 execute_abstract_command(): command=0x23100d; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100d
Debug: 3402 23120 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x4 to a3 valid=1
Debug: 3403 23123 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore a4
Debug: 3404 23126 riscv.c:3901 register_set(): [esp32c3] write 0x600c2000 to a4 (valid=0)
Debug: 3405 23130 riscv.c:3477 riscv_set_register(): [esp32c3] a4 <- 600c2000
Debug: 3406 23133 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x600c2000 to register a4
Debug: 3407 23137 riscv-013.c:1315 register_write_direct(): {0} a4 <- 0x600c2000
Debug: 3408 23141 riscv-013.c:800 execute_abstract_command(): command=0x23100e; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100e
Debug: 3409 23149 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x600c2000 to a4 valid=1
Debug: 3410 23152 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore a5
Debug: 3411 23155 riscv.c:3901 register_set(): [esp32c3] write 0x00000089 to a5 (valid=0)
Debug: 3412 23159 riscv.c:3477 riscv_set_register(): [esp32c3] a5 <- 89
Debug: 3413 23161 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x89 to register a5
Debug: 3414 23165 riscv-013.c:1315 register_write_direct(): {0} a5 <- 0x89
Debug: 3415 23169 riscv-013.c:800 execute_abstract_command(): command=0x23100f; access register, size=32, postexec=0, transfer=1, write=1, regno=0x100f
Debug: 3416 23176 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x89 to a5 valid=1
Debug: 3417 23179 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore a6
Debug: 3418 23182 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to a6 (valid=0)
Debug: 3419 23186 riscv.c:3477 riscv_set_register(): [esp32c3] a6 <- 0
Debug: 3420 23187 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register a6
Debug: 3421 23191 riscv-013.c:1315 register_write_direct(): {0} a6 <- 0x0
Debug: 3422 23195 riscv-013.c:800 execute_abstract_command(): command=0x231010; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1010
Debug: 3423 23202 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to a6 valid=1
Debug: 3424 23205 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore a7
Debug: 3425 23208 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to a7 (valid=0)
Debug: 3426 23212 riscv.c:3477 riscv_set_register(): [esp32c3] a7 <- 0
Debug: 3427 23214 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register a7
Debug: 3428 23218 riscv-013.c:1315 register_write_direct(): {0} a7 <- 0x0
Debug: 3429 23221 riscv-013.c:800 execute_abstract_command(): command=0x231011; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1011
Debug: 3430 23228 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to a7 valid=1
Debug: 3431 23231 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore s2
Debug: 3432 23234 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to s2 (valid=0)
Debug: 3433 23238 riscv.c:3477 riscv_set_register(): [esp32c3] s2 <- 0
Debug: 3434 23240 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register s2
Debug: 3435 23244 riscv-013.c:1315 register_write_direct(): {0} s2 <- 0x0
Debug: 3436 23248 riscv-013.c:800 execute_abstract_command(): command=0x231012; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1012
Debug: 3437 23254 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to s2 valid=1
Debug: 3438 23258 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore s3
Debug: 3439 23261 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to s3 (valid=0)
Debug: 3440 23265 riscv.c:3477 riscv_set_register(): [esp32c3] s3 <- 0
Debug: 3441 23268 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register s3
Debug: 3442 23271 riscv-013.c:1315 register_write_direct(): {0} s3 <- 0x0
Debug: 3443 23275 riscv-013.c:800 execute_abstract_command(): command=0x231013; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1013
Debug: 3444 23282 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to s3 valid=1
Debug: 3445 23285 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore s4
Debug: 3446 23288 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to s4 (valid=0)
Debug: 3447 23292 riscv.c:3477 riscv_set_register(): [esp32c3] s4 <- 0
Debug: 3448 23295 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register s4
Debug: 3449 23298 riscv-013.c:1315 register_write_direct(): {0} s4 <- 0x0
Debug: 3450 23302 riscv-013.c:800 execute_abstract_command(): command=0x231014; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1014
Debug: 3451 23309 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to s4 valid=1
Debug: 3452 23312 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore s5
Debug: 3453 23315 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to s5 (valid=0)
Debug: 3454 23318 riscv.c:3477 riscv_set_register(): [esp32c3] s5 <- 0
Debug: 3455 23321 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register s5
Debug: 3456 23325 riscv-013.c:1315 register_write_direct(): {0} s5 <- 0x0
Debug: 3457 23328 riscv-013.c:800 execute_abstract_command(): command=0x231015; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1015
Debug: 3458 23335 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to s5 valid=1
Debug: 3459 23338 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore s6
Debug: 3460 23341 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to s6 (valid=0)
Debug: 3461 23344 riscv.c:3477 riscv_set_register(): [esp32c3] s6 <- 0
Debug: 3462 23347 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register s6
Debug: 3463 23350 riscv-013.c:1315 register_write_direct(): {0} s6 <- 0x0
Debug: 3464 23355 riscv-013.c:800 execute_abstract_command(): command=0x231016; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1016
Debug: 3465 23361 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to s6 valid=1
Debug: 3466 23364 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore s7
Debug: 3467 23367 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to s7 (valid=0)
Debug: 3468 23370 riscv.c:3477 riscv_set_register(): [esp32c3] s7 <- 0
Debug: 3469 23374 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register s7
Debug: 3470 23377 riscv-013.c:1315 register_write_direct(): {0} s7 <- 0x0
Debug: 3471 23379 riscv-013.c:800 execute_abstract_command(): command=0x231017; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1017
Debug: 3472 23386 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to s7 valid=1
Debug: 3473 23389 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore s8
Debug: 3474 23392 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to s8 (valid=0)
Debug: 3475 23395 riscv.c:3477 riscv_set_register(): [esp32c3] s8 <- 0
Debug: 3476 23398 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register s8
Debug: 3477 23402 riscv-013.c:1315 register_write_direct(): {0} s8 <- 0x0
Debug: 3478 23405 riscv-013.c:800 execute_abstract_command(): command=0x231018; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1018
Debug: 3479 23412 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to s8 valid=1
Debug: 3480 23415 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore s9
Debug: 3481 23418 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to s9 (valid=0)
Debug: 3482 23421 riscv.c:3477 riscv_set_register(): [esp32c3] s9 <- 0
Debug: 3483 23424 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register s9
Debug: 3484 23427 riscv-013.c:1315 register_write_direct(): {0} s9 <- 0x0
Debug: 3485 23432 riscv-013.c:800 execute_abstract_command(): command=0x231019; access register, size=32, postexec=0, transfer=1, write=1, regno=0x1019
Debug: 3486 23439 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to s9 valid=1
Debug: 3487 23442 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore s10
Debug: 3488 23444 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to s10 (valid=0)
Debug: 3489 23448 riscv.c:3477 riscv_set_register(): [esp32c3] s10 <- 0
Debug: 3490 23451 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register s10
Debug: 3491 23455 riscv-013.c:1315 register_write_direct(): {0} s10 <- 0x0
Debug: 3492 23458 riscv-013.c:800 execute_abstract_command(): command=0x23101a; access register, size=32, postexec=0, transfer=1, write=1, regno=0x101a
Debug: 3493 23465 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to s10 valid=1
Debug: 3494 23468 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore s11
Debug: 3495 23471 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to s11 (valid=0)
Debug: 3496 23475 riscv.c:3477 riscv_set_register(): [esp32c3] s11 <- 0
Debug: 3497 23479 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register s11
Debug: 3498 23482 riscv-013.c:1315 register_write_direct(): {0} s11 <- 0x0
Debug: 3499 23485 riscv-013.c:800 execute_abstract_command(): command=0x23101b; access register, size=32, postexec=0, transfer=1, write=1, regno=0x101b
Debug: 3500 23492 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to s11 valid=1
Debug: 3501 23495 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore t3
Debug: 3502 23498 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to t3 (valid=0)
Debug: 3503 23501 riscv.c:3477 riscv_set_register(): [esp32c3] t3 <- 0
Debug: 3504 23504 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register t3
Debug: 3505 23508 riscv-013.c:1315 register_write_direct(): {0} t3 <- 0x0
Debug: 3506 23512 riscv-013.c:800 execute_abstract_command(): command=0x23101c; access register, size=32, postexec=0, transfer=1, write=1, regno=0x101c
Debug: 3507 23518 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to t3 valid=1
Debug: 3508 23521 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore t4
Debug: 3509 23524 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to t4 (valid=0)
Debug: 3510 23528 riscv.c:3477 riscv_set_register(): [esp32c3] t4 <- 0
Debug: 3511 23531 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register t4
Debug: 3512 23534 riscv-013.c:1315 register_write_direct(): {0} t4 <- 0x0
Debug: 3513 23538 riscv-013.c:800 execute_abstract_command(): command=0x23101d; access register, size=32, postexec=0, transfer=1, write=1, regno=0x101d
Debug: 3514 23545 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to t4 valid=1
Debug: 3515 23548 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore t5
Debug: 3516 23550 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to t5 (valid=0)
Debug: 3517 23554 riscv.c:3477 riscv_set_register(): [esp32c3] t5 <- 0
Debug: 3518 23557 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register t5
Debug: 3519 23560 riscv-013.c:1315 register_write_direct(): {0} t5 <- 0x0
Debug: 3520 23564 riscv-013.c:800 execute_abstract_command(): command=0x23101e; access register, size=32, postexec=0, transfer=1, write=1, regno=0x101e
Debug: 3521 23571 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to t5 valid=1
Debug: 3522 23574 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore t6
Debug: 3523 23577 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to t6 (valid=0)
Debug: 3524 23580 riscv.c:3477 riscv_set_register(): [esp32c3] t6 <- 0
Debug: 3525 23583 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register t6
Debug: 3526 23586 riscv-013.c:1315 register_write_direct(): {0} t6 <- 0x0
Debug: 3527 23591 riscv-013.c:800 execute_abstract_command(): command=0x23101f; access register, size=32, postexec=0, transfer=1, write=1, regno=0x101f
Debug: 3528 23597 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to t6 valid=1
Debug: 3529 23600 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pc
Debug: 3530 23603 riscv.c:3901 register_set(): [esp32c3] write 0x4038aa24 to pc (valid=0)
Debug: 3531 23607 riscv.c:3477 riscv_set_register(): [esp32c3] pc <- 4038aa24
Debug: 3532 23609 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x4038aa24 to register pc
Debug: 3533 23613 riscv-013.c:4120 riscv013_set_register(): [0] writing PC to DPC: 0x4038aa24
Debug: 3534 23617 riscv-013.c:1315 register_write_direct(): {0} dpc <- 0x4038aa24
Debug: 3535 23621 riscv-013.c:800 execute_abstract_command(): command=0x2307b1; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b1
Debug: 3536 23627 riscv-013.c:800 execute_abstract_command(): command=0x2207b1; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b1
Debug: 3537 23634 riscv-013.c:1504 register_read_direct(): {0} dpc = 0x4038aa24
Debug: 3538 23637 riscv-013.c:4124 riscv013_set_register(): [0]   actual DPC written: 0x000000004038aa24
Debug: 3539 23641 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x4038aa24 to pc valid=0
Debug: 3540 23645 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore mstatus
Debug: 3541 23648 riscv.c:3901 register_set(): [esp32c3] write 0x00000081 to mstatus (valid=0)
Debug: 3542 23652 riscv.c:3477 riscv_set_register(): [esp32c3] mstatus <- 81
Debug: 3543 23655 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x81 to register mstatus
Debug: 3544 23658 riscv-013.c:1315 register_write_direct(): {0} mstatus <- 0x81
Debug: 3545 23662 riscv-013.c:800 execute_abstract_command(): command=0x230300; access register, size=32, postexec=0, transfer=1, write=1, regno=0x300
Debug: 3546 23669 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x81 to mstatus valid=0
Debug: 3547 23672 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore misa
Debug: 3548 23675 riscv.c:3901 register_set(): [esp32c3] write 0x40101104 to misa (valid=0)
Debug: 3549 23678 riscv.c:3477 riscv_set_register(): [esp32c3] misa <- 40101104
Debug: 3550 23681 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x40101104 to register misa
Debug: 3551 23685 riscv-013.c:1315 register_write_direct(): {0} misa <- 0x40101104
Debug: 3552 23689 riscv-013.c:800 execute_abstract_command(): command=0x230301; access register, size=32, postexec=0, transfer=1, write=1, regno=0x301
Debug: 3553 23696 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x40101104 to misa valid=0
Debug: 3554 23699 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore mtvec
Debug: 3555 23702 riscv.c:3901 register_set(): [esp32c3] write 0x40380001 to mtvec (valid=0)
Debug: 3556 23706 riscv.c:3477 riscv_set_register(): [esp32c3] csr773 <- 40380001
Debug: 3557 23709 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x40380001 to register csr773
Debug: 3558 23713 riscv-013.c:1315 register_write_direct(): {0} csr773 <- 0x40380001
Debug: 3559 23717 riscv-013.c:800 execute_abstract_command(): command=0x230305; access register, size=32, postexec=0, transfer=1, write=1, regno=0x305
Debug: 3560 23723 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x40380001 to mtvec valid=0
Debug: 3561 23727 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore mscratch
Debug: 3562 23730 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to mscratch (valid=0)
Debug: 3563 23733 riscv.c:3477 riscv_set_register(): [esp32c3] csr832 <- 0
Debug: 3564 23736 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register csr832
Debug: 3565 23740 riscv-013.c:1315 register_write_direct(): {0} csr832 <- 0x0
Debug: 3566 23743 riscv-013.c:800 execute_abstract_command(): command=0x230340; access register, size=32, postexec=0, transfer=1, write=1, regno=0x340
Debug: 3567 23750 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to mscratch valid=0
Debug: 3568 23754 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore mepc
Debug: 3569 23756 riscv.c:3901 register_set(): [esp32c3] write 0x4038aaaa to mepc (valid=0)
Debug: 3570 23760 riscv.c:3477 riscv_set_register(): [esp32c3] mepc <- 4038aaaa
Debug: 3571 23764 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x4038aaaa to register mepc
Debug: 3572 23768 riscv-013.c:1315 register_write_direct(): {0} mepc <- 0x4038aaaa
Debug: 3573 23772 riscv-013.c:800 execute_abstract_command(): command=0x230341; access register, size=32, postexec=0, transfer=1, write=1, regno=0x341
Debug: 3574 23779 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x4038aaaa to mepc valid=0
Debug: 3575 23782 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore mcause
Debug: 3576 23785 riscv.c:3901 register_set(): [esp32c3] write 0x80000009 to mcause (valid=0)
Debug: 3577 23788 riscv.c:3477 riscv_set_register(): [esp32c3] mcause <- 80000009
Debug: 3578 23791 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x80000009 to register mcause
Debug: 3579 23795 riscv-013.c:1315 register_write_direct(): {0} mcause <- 0x80000009
Debug: 3580 23799 riscv-013.c:800 execute_abstract_command(): command=0x230342; access register, size=32, postexec=0, transfer=1, write=1, regno=0x342
Debug: 3581 23806 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x80000009 to mcause valid=0
Debug: 3582 23809 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore mtval
Debug: 3583 23812 riscv.c:3901 register_set(): [esp32c3] write 0x00008082 to mtval (valid=0)
Debug: 3584 23816 riscv.c:3477 riscv_set_register(): [esp32c3] csr835 <- 8082
Debug: 3585 23819 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x8082 to register csr835
Debug: 3586 23822 riscv-013.c:1315 register_write_direct(): {0} csr835 <- 0x8082
Debug: 3587 23827 riscv-013.c:800 execute_abstract_command(): command=0x230343; access register, size=32, postexec=0, transfer=1, write=1, regno=0x343
Debug: 3588 23833 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x8082 to mtval valid=0
Debug: 3589 23836 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pmpcfg0
Debug: 3590 23839 riscv.c:3901 register_set(): [esp32c3] write 0x89888f88 to pmpcfg0 (valid=0)
Debug: 3591 23843 riscv.c:3477 riscv_set_register(): [esp32c3] csr928 <- 89888f88
Debug: 3592 23846 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x89888f88 to register csr928
Debug: 3593 23850 riscv-013.c:1315 register_write_direct(): {0} csr928 <- 0x89888f88
Debug: 3594 23854 riscv-013.c:800 execute_abstract_command(): command=0x2303a0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3a0
Debug: 3595 23861 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x89888f88 to pmpcfg0 valid=0
Debug: 3596 23864 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pmpcfg1
Debug: 3597 23867 riscv.c:3901 register_set(): [esp32c3] write 0x888d898b to pmpcfg1 (valid=0)
Debug: 3598 23872 riscv.c:3477 riscv_set_register(): [esp32c3] csr929 <- 888d898b
Debug: 3599 23875 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x888d898b to register csr929
Debug: 3600 23878 riscv-013.c:1315 register_write_direct(): {0} csr929 <- 0x888d898b
Debug: 3601 23882 riscv-013.c:800 execute_abstract_command(): command=0x2303a1; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3a1
Debug: 3602 23889 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x888d898b to pmpcfg1 valid=0
Debug: 3603 23893 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pmpcfg2
Debug: 3604 23896 riscv.c:3901 register_set(): [esp32c3] write 0x8f888d8f to pmpcfg2 (valid=0)
Debug: 3605 23899 riscv.c:3477 riscv_set_register(): [esp32c3] csr930 <- 8f888d8f
Debug: 3606 23902 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x8f888d8f to register csr930
Debug: 3607 23906 riscv-013.c:1315 register_write_direct(): {0} csr930 <- 0x8f888d8f
Debug: 3608 23910 riscv-013.c:800 execute_abstract_command(): command=0x2303a2; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3a2
Debug: 3609 23917 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x8f888d8f to pmpcfg2 valid=0
Debug: 3610 23920 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pmpcfg3
Debug: 3611 23923 riscv.c:3901 register_set(): [esp32c3] write 0x90888b88 to pmpcfg3 (valid=0)
Debug: 3612 23927 riscv.c:3477 riscv_set_register(): [esp32c3] csr931 <- 90888b88
Debug: 3613 23930 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x90888b88 to register csr931
Debug: 3614 23934 riscv-013.c:1315 register_write_direct(): {0} csr931 <- 0x90888b88
Debug: 3615 23938 riscv-013.c:800 execute_abstract_command(): command=0x2303a3; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3a3
Debug: 3616 23945 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x90888b88 to pmpcfg3 valid=0
Debug: 3617 23948 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pmpaddr0
Debug: 3618 23952 riscv.c:3901 register_set(): [esp32c3] write 0x08000000 to pmpaddr0 (valid=0)
Debug: 3619 23955 riscv.c:3477 riscv_set_register(): [esp32c3] csr944 <- 8000000
Debug: 3620 23958 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x8000000 to register csr944
Debug: 3621 23962 riscv-013.c:1315 register_write_direct(): {0} csr944 <- 0x8000000
Debug: 3622 23966 riscv-013.c:800 execute_abstract_command(): command=0x2303b0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b0
Debug: 3623 23973 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x8000000 to pmpaddr0 valid=0
Debug: 3624 23976 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pmpaddr1
Debug: 3625 23979 riscv.c:3901 register_set(): [esp32c3] write 0x0a000000 to pmpaddr1 (valid=0)
Debug: 3626 23983 riscv.c:3477 riscv_set_register(): [esp32c3] csr945 <- a000000
Debug: 3627 23986 riscv-013.c:4115 riscv013_set_register(): [0] writing 0xa000000 to register csr945
Debug: 3628 23990 riscv-013.c:1315 register_write_direct(): {0} csr945 <- 0xa000000
Debug: 3629 23993 riscv-013.c:800 execute_abstract_command(): command=0x2303b1; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b1
Debug: 3630 24000 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0xa000000 to pmpaddr1 valid=0
Debug: 3631 24004 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pmpaddr2
Debug: 3632 24007 riscv.c:3901 register_set(): [esp32c3] write 0x0f000000 to pmpaddr2 (valid=0)
Debug: 3633 24010 riscv.c:3477 riscv_set_register(): [esp32c3] csr946 <- f000000
Debug: 3634 24014 riscv-013.c:4115 riscv013_set_register(): [0] writing 0xf000000 to register csr946
Debug: 3635 24018 riscv-013.c:1315 register_write_direct(): {0} csr946 <- 0xf000000
Debug: 3636 24021 riscv-013.c:800 execute_abstract_command(): command=0x2303b2; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b2
Debug: 3637 24028 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0xf000000 to pmpaddr2 valid=0
Debug: 3638 24031 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pmpaddr3
Debug: 3639 24034 riscv.c:3901 register_set(): [esp32c3] write 0x0ff20000 to pmpaddr3 (valid=0)
Debug: 3640 24038 riscv.c:3477 riscv_set_register(): [esp32c3] csr947 <- ff20000
Debug: 3641 24041 riscv-013.c:4115 riscv013_set_register(): [0] writing 0xff20000 to register csr947
Debug: 3642 24046 riscv-013.c:1315 register_write_direct(): {0} csr947 <- 0xff20000
Debug: 3643 24050 riscv-013.c:800 execute_abstract_command(): command=0x2303b3; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b3
Debug: 3644 24057 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0xff20000 to pmpaddr3 valid=0
Debug: 3645 24061 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pmpaddr4
Debug: 3646 24064 riscv.c:3901 register_set(): [esp32c3] write 0x0ff38000 to pmpaddr4 (valid=0)
Debug: 3647 24067 riscv.c:3477 riscv_set_register(): [esp32c3] csr948 <- ff38000
Debug: 3648 24070 riscv-013.c:4115 riscv013_set_register(): [0] writing 0xff38000 to register csr948
Debug: 3649 24074 riscv-013.c:1315 register_write_direct(): {0} csr948 <- 0xff38000
Debug: 3650 24079 riscv-013.c:800 execute_abstract_command(): command=0x2303b4; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b4
Debug: 3651 24085 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0xff38000 to pmpaddr4 valid=0
Debug: 3652 24089 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pmpaddr5
Debug: 3653 24092 riscv.c:3901 register_set(): [esp32c3] write 0x0ffc8000 to pmpaddr5 (valid=0)
Debug: 3654 24096 riscv.c:3477 riscv_set_register(): [esp32c3] csr949 <- ffc8000
Debug: 3655 24099 riscv-013.c:4115 riscv013_set_register(): [0] writing 0xffc8000 to register csr949
Debug: 3656 24102 riscv-013.c:1315 register_write_direct(): {0} csr949 <- 0xffc8000
Debug: 3657 24106 riscv-013.c:800 execute_abstract_command(): command=0x2303b5; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b5
Debug: 3658 24113 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0xffc8000 to pmpaddr5 valid=0
Debug: 3659 24116 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pmpaddr6
Debug: 3660 24119 riscv.c:3901 register_set(): [esp32c3] write 0x10018000 to pmpaddr6 (valid=0)
Debug: 3661 24123 riscv.c:3477 riscv_set_register(): [esp32c3] csr950 <- 10018000
Debug: 3662 24126 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x10018000 to register csr950
Debug: 3663 24130 riscv-013.c:1315 register_write_direct(): {0} csr950 <- 0x10018000
Debug: 3664 24134 riscv-013.c:800 execute_abstract_command(): command=0x2303b6; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b6
Debug: 3665 24142 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x10018000 to pmpaddr6 valid=0
Debug: 3666 24145 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pmpaddr7
Debug: 3667 24148 riscv.c:3901 register_set(): [esp32c3] write 0x100df000 to pmpaddr7 (valid=0)
Debug: 3668 24152 riscv.c:3477 riscv_set_register(): [esp32c3] csr951 <- 100df000
Debug: 3669 24155 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x100df000 to register csr951
Debug: 3670 24159 riscv-013.c:1315 register_write_direct(): {0} csr951 <- 0x100df000
Debug: 3671 24163 riscv-013.c:800 execute_abstract_command(): command=0x2303b7; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b7
Debug: 3672 24169 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x100df000 to pmpaddr7 valid=0
Debug: 3673 24174 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pmpaddr8
Debug: 3674 24177 riscv.c:3901 register_set(): [esp32c3] write 0x100f8000 to pmpaddr8 (valid=0)
Debug: 3675 24180 riscv.c:3477 riscv_set_register(): [esp32c3] csr952 <- 100f8000
Debug: 3676 24182 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x100f8000 to register csr952
Debug: 3677 24187 riscv-013.c:1315 register_write_direct(): {0} csr952 <- 0x100f8000
Debug: 3678 24191 riscv-013.c:800 execute_abstract_command(): command=0x2303b8; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b8
Debug: 3679 24197 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x100f8000 to pmpaddr8 valid=0
Debug: 3680 24200 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pmpaddr9
Debug: 3681 24204 riscv.c:3901 register_set(): [esp32c3] write 0x10a00000 to pmpaddr9 (valid=0)
Debug: 3682 24208 riscv.c:3477 riscv_set_register(): [esp32c3] csr953 <- 10a00000
Debug: 3683 24211 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x10a00000 to register csr953
Debug: 3684 24215 riscv-013.c:1315 register_write_direct(): {0} csr953 <- 0x10a00000
Debug: 3685 24219 riscv-013.c:800 execute_abstract_command(): command=0x2303b9; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3b9
Debug: 3686 24226 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x10a00000 to pmpaddr9 valid=0
Debug: 3687 24229 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pmpaddr10
Debug: 3688 24233 riscv.c:3901 register_set(): [esp32c3] write 0x14000000 to pmpaddr10 (valid=0)
Debug: 3689 24236 riscv.c:3477 riscv_set_register(): [esp32c3] csr954 <- 14000000
Debug: 3690 24239 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x14000000 to register csr954
Debug: 3691 24243 riscv-013.c:1315 register_write_direct(): {0} csr954 <- 0x14000000
Debug: 3692 24247 riscv-013.c:800 execute_abstract_command(): command=0x2303ba; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3ba
Debug: 3693 24254 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x14000000 to pmpaddr10 valid=0
Debug: 3694 24257 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pmpaddr11
Debug: 3695 24260 riscv.c:3901 register_set(): [esp32c3] write 0x14000800 to pmpaddr11 (valid=0)
Debug: 3696 24264 riscv.c:3477 riscv_set_register(): [esp32c3] csr955 <- 14000800
Debug: 3697 24267 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x14000800 to register csr955
Debug: 3698 24271 riscv-013.c:1315 register_write_direct(): {0} csr955 <- 0x14000800
Debug: 3699 24275 riscv-013.c:800 execute_abstract_command(): command=0x2303bb; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3bb
Debug: 3700 24282 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x14000800 to pmpaddr11 valid=0
Debug: 3701 24285 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pmpaddr12
Debug: 3702 24289 riscv.c:3901 register_set(): [esp32c3] write 0x18000000 to pmpaddr12 (valid=0)
Debug: 3703 24292 riscv.c:3477 riscv_set_register(): [esp32c3] csr956 <- 18000000
Debug: 3704 24295 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x18000000 to register csr956
Debug: 3705 24299 riscv-013.c:1315 register_write_direct(): {0} csr956 <- 0x18000000
Debug: 3706 24303 riscv-013.c:800 execute_abstract_command(): command=0x2303bc; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3bc
Debug: 3707 24309 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x18000000 to pmpaddr12 valid=0
Debug: 3708 24313 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pmpaddr13
Debug: 3709 24316 riscv.c:3901 register_set(): [esp32c3] write 0x18040000 to pmpaddr13 (valid=0)
Debug: 3710 24320 riscv.c:3477 riscv_set_register(): [esp32c3] csr957 <- 18040000
Debug: 3711 24323 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x18040000 to register csr957
Debug: 3712 24326 riscv-013.c:1315 register_write_direct(): {0} csr957 <- 0x18040000
Debug: 3713 24331 riscv-013.c:800 execute_abstract_command(): command=0x2303bd; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3bd
Debug: 3714 24337 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x18040000 to pmpaddr13 valid=0
Debug: 3715 24340 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pmpaddr14
Debug: 3716 24343 riscv.c:3901 register_set(): [esp32c3] write 0x3fffffff to pmpaddr14 (valid=0)
Debug: 3717 24347 riscv.c:3477 riscv_set_register(): [esp32c3] csr958 <- 3fffffff
Debug: 3718 24350 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x3fffffff to register csr958
Debug: 3719 24354 riscv-013.c:1315 register_write_direct(): {0} csr958 <- 0x3fffffff
Debug: 3720 24358 riscv-013.c:800 execute_abstract_command(): command=0x2303be; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3be
Debug: 3721 24366 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x3fffffff to pmpaddr14 valid=0
Debug: 3722 24370 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore pmpaddr15
Debug: 3723 24373 riscv.c:3901 register_set(): [esp32c3] write 0x3fffffff to pmpaddr15 (valid=0)
Debug: 3724 24378 riscv.c:3477 riscv_set_register(): [esp32c3] csr959 <- 3fffffff
Debug: 3725 24381 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x3fffffff to register csr959
Debug: 3726 24386 riscv-013.c:1315 register_write_direct(): {0} csr959 <- 0x3fffffff
Debug: 3727 24390 riscv-013.c:800 execute_abstract_command(): command=0x2303bf; access register, size=32, postexec=0, transfer=1, write=1, regno=0x3bf
Debug: 3728 24398 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x3fffffff to pmpaddr15 valid=0
Debug: 3729 24401 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore tselect
Debug: 3730 24404 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to tselect (valid=0)
Debug: 3731 24409 riscv.c:3477 riscv_set_register(): [esp32c3] tselect <- 0
Debug: 3732 24411 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register tselect
Debug: 3733 24415 riscv-013.c:1315 register_write_direct(): {0} tselect <- 0x0
Debug: 3734 24419 riscv-013.c:800 execute_abstract_command(): command=0x2307a0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a0
Debug: 3735 24427 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to tselect valid=0
Debug: 3736 24430 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore tdata1
Debug: 3737 24434 riscv.c:3901 register_set(): [esp32c3] write 0x23e00000 to tdata1 (valid=0)
Debug: 3738 24438 riscv.c:3477 riscv_set_register(): [esp32c3] tdata1 <- 23e00000
Debug: 3739 24442 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x23e00000 to register tdata1
Debug: 3740 24447 riscv-013.c:1315 register_write_direct(): {0} tdata1 <- 0x23e00000
Debug: 3741 24452 riscv-013.c:800 execute_abstract_command(): command=0x2307a1; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a1
Debug: 3742 24459 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x23e00000 to tdata1 valid=0
Debug: 3743 24463 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore tdata2
Debug: 3744 24467 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to tdata2 (valid=0)
Debug: 3745 24471 riscv.c:3477 riscv_set_register(): [esp32c3] tdata2 <- 0
Debug: 3746 24474 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register tdata2
Debug: 3747 24479 riscv-013.c:1315 register_write_direct(): {0} tdata2 <- 0x0
Debug: 3748 24482 riscv-013.c:800 execute_abstract_command(): command=0x2307a2; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a2
Debug: 3749 24490 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to tdata2 valid=0
Debug: 3750 24493 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore tcontrol
Debug: 3751 24497 riscv.c:3901 register_set(): [esp32c3] write 0x00000088 to tcontrol (valid=0)
Debug: 3752 24500 riscv.c:3477 riscv_set_register(): [esp32c3] csr1957 <- 88
Debug: 3753 24504 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x88 to register csr1957
Debug: 3754 24508 riscv-013.c:1315 register_write_direct(): {0} csr1957 <- 0x88
Debug: 3755 24512 riscv-013.c:800 execute_abstract_command(): command=0x2307a5; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7a5
Debug: 3756 24519 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x88 to tcontrol valid=0
Debug: 3757 24522 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore dcsr
Debug: 3758 24525 riscv.c:3901 register_set(): [esp32c3] write 0x400000c3 to dcsr (valid=0)
Debug: 3759 24529 riscv.c:3477 riscv_set_register(): [esp32c3] dcsr <- 400000c3
Debug: 3760 24532 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x400000c3 to register dcsr
Debug: 3761 24536 riscv-013.c:1315 register_write_direct(): {0} dcsr <- 0x400000c3
Debug: 3762 24540 riscv-013.c:800 execute_abstract_command(): command=0x2307b0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b0
Debug: 3763 24547 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x400000c3 to dcsr valid=0
Debug: 3764 24550 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore dpc
Debug: 3765 24553 riscv.c:3901 register_set(): [esp32c3] write 0x4038aa24 to dpc (valid=0)
Debug: 3766 24556 riscv.c:3477 riscv_set_register(): [esp32c3] dpc <- 4038aa24
Debug: 3767 24560 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x4038aa24 to register dpc
Debug: 3768 24564 riscv-013.c:1315 register_write_direct(): {0} dpc <- 0x4038aa24
Debug: 3769 24568 riscv-013.c:800 execute_abstract_command(): command=0x2307b1; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b1
Debug: 3770 24576 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x4038aa24 to dpc valid=1
Debug: 3771 24579 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore dscratch0
Debug: 3772 24582 riscv.c:3901 register_set(): [esp32c3] write 0x00000000 to dscratch0 (valid=0)
Debug: 3773 24586 riscv.c:3477 riscv_set_register(): [esp32c3] dscratch0 <- 0
Debug: 3774 24589 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x0 to register dscratch0
Debug: 3775 24593 riscv-013.c:1315 register_write_direct(): {0} dscratch0 <- 0x0
Debug: 3776 24596 riscv-013.c:800 execute_abstract_command(): command=0x2307b2; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b2
Debug: 3777 24603 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x0 to dscratch0 valid=0
Debug: 3778 24607 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore dscratch1
Debug: 3779 24610 riscv.c:3901 register_set(): [esp32c3] write 0x00000001 to dscratch1 (valid=0)
Debug: 3780 24614 riscv.c:3477 riscv_set_register(): [esp32c3] csr1971 <- 1
Debug: 3781 24617 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x1 to register csr1971
Debug: 3782 24620 riscv-013.c:1315 register_write_direct(): {0} csr1971 <- 0x1
Debug: 3783 24624 riscv-013.c:800 execute_abstract_command(): command=0x2307b3; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b3
Debug: 3784 24631 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x1 to dscratch1 valid=0
Debug: 3785 24635 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore hpmcounter16
Debug: 3786 24638 riscv.c:3901 register_set(): [esp32c3] write 0x00000003 to hpmcounter16 (valid=0)
Debug: 3787 24641 riscv.c:3477 riscv_set_register(): [esp32c3] csr3088 <- 3
Debug: 3788 24645 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x3 to register csr3088
Debug: 3789 24648 riscv-013.c:1315 register_write_direct(): {0} csr3088 <- 0x3
Debug: 3790 24652 riscv-013.c:800 execute_abstract_command(): command=0x230c10; access register, size=32, postexec=0, transfer=1, write=1, regno=0xc10
Debug: 3791 24658 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x3 to hpmcounter16 valid=0
Debug: 3792 24662 esp_riscv.c:486 esp_riscv_wait_algorithm(): restore priv
Debug: 3793 24665 riscv.c:3901 register_set(): [esp32c3] write 0x03 to priv (valid=0)
Debug: 3794 24668 riscv.c:3477 riscv_set_register(): [esp32c3] priv <- 3
Debug: 3795 24671 riscv-013.c:4115 riscv013_set_register(): [0] writing 0x3 to register priv
Debug: 3796 24675 riscv-013.c:800 execute_abstract_command(): command=0x2207b0; access register, size=32, postexec=0, transfer=1, write=0, regno=0x7b0
Debug: 3797 24682 riscv-013.c:1504 register_read_direct(): {0} dcsr = 0x400000c3
Debug: 3798 24685 riscv-013.c:1315 register_write_direct(): {0} dcsr <- 0x400000c3
Debug: 3799 24689 riscv-013.c:800 execute_abstract_command(): command=0x2307b0; access register, size=32, postexec=0, transfer=1, write=1, regno=0x7b0
Debug: 3800 24696 riscv.c:3496 riscv_set_register(): [esp32c3] wrote 0x3 to priv valid=0
Debug: 3801 24699 esp_algorithm.c:246 algorithm_run(): Got algorithm RC 0x0
Debug: 3802 24703 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381ce4
Debug: 3803 24708 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 3804 24712 target.c:2206 target_free_working_area_restore(): freed 4 bytes of working area at address 0x40381ce4
Debug: 3805 24716 target.c:1986 print_wa_layout(): b* 0x40380000-0x40381ce3 (7396 bytes)
Debug: 3806 24719 target.c:1986 print_wa_layout():    0x40381ce4-0x40383fff (8988 bytes)
Debug: 3807 24725 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x3fc84428
Debug: 3808 24735 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x3fc84628
Debug: 3809 24746 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 3810 24749 target.c:2206 target_free_working_area_restore(): freed 1024 bytes of working area at address 0x3fc84428
Debug: 3811 24755 target.c:1986 print_wa_layout(): b* 0x3fc84000-0x3fc84427 (1064 bytes)
Debug: 3812 24758 target.c:1986 print_wa_layout():    0x3fc84428-0x3fca3fff (130008 bytes)
Debug: 3813 24762 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380000
Debug: 3814 24774 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380200
Debug: 3815 24784 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380400
Debug: 3816 24794 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380600
Debug: 3817 24805 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380800
Debug: 3818 24815 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380a00
Debug: 3819 24826 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380c00
Debug: 3820 24837 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40380e00
Debug: 3821 24849 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381000
Debug: 3822 24861 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381200
Debug: 3823 24872 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381400
Debug: 3824 24884 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381600
Debug: 3825 24896 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381800
Debug: 3826 24908 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381a00
Debug: 3827 24918 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x40381c00
Debug: 3828 24928 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 3829 24932 target.c:2206 target_free_working_area_restore(): freed 7396 bytes of working area at address 0x40380000
Debug: 3830 24937 target.c:1986 print_wa_layout():    0x40380000-0x40383fff (16384 bytes)
Debug: 3831 24942 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x3fc84000
Debug: 3832 24951 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x3fc84200
Debug: 3833 24964 riscv-013.c:3680 write_memory_bus_v1(): transferring burst starting at address 0x3fc84400
Debug: 3834 24970 riscv-013.c:2858 log_mem_access_result(): Succeeded to write memory via system bus.
Debug: 3835 24974 target.c:2206 target_free_working_area_restore(): freed 1064 bytes of working area at address 0x3fc84000
Debug: 3836 24979 target.c:1986 print_wa_layout():    0x3fc84000-0x3fca3fff (131072 bytes)
Error: 3837 24982 esp_flash.c:343 esp_flash_get_size(): Failed to get flash size!
Debug: 3838 24985 esp_flash.c:344 esp_flash_get_size(): esp_flash_get_size size 0x0
Error: 3839 24989 esp_flash.c:1000 esp_flash_probe(): Failed to probe flash, size 0 KB
Error: 3840 24992 core.c:302 get_flash_bank_by_num(): auto_probe failed
Error: 3841 24995 gdb_server.c:1073 gdb_new_connection(): Connect failed. Consider setting up a gdb-attach event for the target to prepare target for GDB connect, or use 'gdb_memory_map disable'.
Error: 3842 25003 server.c:99 add_connection(): attempted 'gdb' connection rejected