EVEREST aims at proposing a high-performance, distributed and heterogeneous hardware architecture and a companion design environment. The multi-node hardware architecture seamlessly combines CPUs and coherent FPGA accelerators for cloud computing, and disaggregated FPGA devices for edge computing. The design environment uses state-of-the-art programming models, emerging communication standards, and novel domain-specific extensions in combination to provide characteristics of algorithms and data, to better exploit data parallelism, to improve the dynamic control of the distributed execution, and to enforce security. The EVEREST approach will be validated on three industry-relevant applications.
For more information, refer to https://everest-h2020.eu/.
If you use any part of this work in your reasearch, please cite our DATE 2024 paper:
@INPROCEEDINGS{everest24date,
author={Pilato, Christian and Banik, Subhadeep and Ber\'anek, Jakub and Brocheton, Fabien and Castrillon, Jeronimo and Cevasco, Riccardo and Cmar, Radim and Curzel, Serena and Ferrandi, Fabrizio and Friebel, Karl F. A. and Galizia, Antonella and Grasso, Matteo and Silva, Paulo and Martinovic, Jan and Palermo, Gianluca and Paolino, Michele and Parodi, Andrea and Parodi, Antonio and Pintus, Fabio and Polig, Raphael and Poulet, David and Regazzoni, Francesco and Ringlein, Burkhard and Rocco, Roberto and Slaninova, Katerina and Slooff, Tom and Soldavini, Stephanie and Suchert, Felix and Tibaldi, Mattia and Weiss, Beat and Hagleitner, Christoph},
booktitle={2024 Design, Automation \& Test in Europe Conference \& Exhibition (DATE)},
title={A System Development Kit for Big Data Applications on FPGA-based Clusters: The EVEREST Approach},
year={2024},
pages={1-6}
}
The EVEREST System Development Kit (SDK) combines commercial and open-source tools into a unified and interoperable framework to ease the development of complex FPGA system architectures and optimize the runtime execution of the applications. The tools are organised into three phases, compilation, deployment and runtime. All tools within the SDK are wrapped under the basecamp command, which provides a single point of access to the users of the SDK.
During compilation, computational kernels marked for FPGA offloading are translated into the corresponding hardware descriptions and passed to downstream tools to generate final bitstreams. EVEREST aims to unify the different input languages into a single hardware generation flow based on MLIR and high-level synthesis (HLS). Based on MLIR, the SDK allows for interoperability with other frontends that produce MLIR descriptions. This is demonstrated with the Messner frontend and MLIR-based compiler for general tensor kernels. A dataflow dialect in MLIR allows connecting kernels, like those generated from a Messner specification, with logical channels to enable transparent offloading and system-level architecture exploration. Ohua, an implicit dataflow coordination language, is provided as an example of a high-level language for application specification. As a third entry to the flows, the SDK supports DNN-to-FPGA mapping via DOSA from ONNX specifications. DOSA builds on the operation set architecture concept and intelligently combines accelerators generated by existing frameworks to produce an overall solution partitioned across FPGAs. In terms of HLS, the SDK aims to add value to existing HLS tools while being tool-agnostic. High-level system architecture exploration is enabled by Olympus, which generates a custom infrastructure for data movement and organization for the kernels. In the case of network-attached FPGAs, hardware-agnostic synchronous communication routines are automatically generated and inserted. The SDK supports the commercial Vitis HLS tool and the academic Bambu HLS tool. The compiler backend supports different target platforms (e.g., AMD Alveo and IBM cloudFPGA), also varying the configuration of the memory architectures around the accelerators.
At deployment, application workflows leverage the LEXIS platform, which has been extended to offload the execution of selected kernels to FPGA. Once a task (or one of its parts) is marked for FPGA acceleration, its execution is set to be offloaded to FPGA-based clusters. During execution, the FPGA cluster may reserve a variable number of nodes for the given application. If the accelerated task requires more resources, the EVEREST runtime can adapt the computation accordingly. Variants are managed by mARGOt, which adds auto-tuning capabilities to the SDK. mARGOt, an application-level library, monitors the application performance during execution and selects the best configuration according to the execution environment (i.e., available hardware resources, resource usage, and data to be processed).
The SDK repository is structured as follows:
examples: this folder contains application examples that showcase how to use different tools on real-world use cases;tests: this folder contains small tests that verify if a tool has been installed correctly;tools: this folder contains the SDK tools, further divided intocompilation,runtime,services, andbasecamp.
Make sure to include all submodules through git clone --recursive or git submodule init and git submodule update.
Run the command . set_env.sh before proceeding.
Each tool provides dedicated installation instructions, and many of them also available as Docker containers.
The EVEREST SDK relies on a specific revision of the MLIR and CIRCT projects.
The easiest way to obtain and build these is by executing the script build_mlir.sh, which will fetch and build both projects.
Be advised that up to 150GB of space is temporarily required for build artifacts during the compilation process.
One way to get started is to use the basecamp tool, which is the entry point for most of the EVEREST SDK's tools. Setup instructions can be found under tools/basecamp.
