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SCons (make-like) scripts for building FPGA code with Xilinx tools
Python Tcl
Branch: master
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scons cleanup. XST results look == in SCons version and Project Navigator
.gitignore ignore compiled python modules
LICENSE Initial revision. Includes SConstruct file and FreeBSD-style license
README Make it more of a Python package
SConstruct Refactor: Move everything into a separate loadable file Make it more of a Python package
xprop_extract.tcl Handle XST command-line options (all the options and values I've enco…


This is a very rudimentary SCons build script for Verilog code using
the Xilinx ISE tools.

This software and accompanying documentation are Copyright 2011,
Carnegie Mellon University.  Redistribution rights are granted
according to the "FreeBSD license" as described in the accompanying
file "LICENSE".

Currently, the ISE installlation paths and a large number of the tool
command-line parameters are hard-coded.  Unless your project exactly matches
mine, it's pretty likely that you'll need to update these.

The easiest way to use this package is to place all of these files in
a subdirectory of your site_dir (let's call it "fpga" because
xilinx-build-scripts is not a valid python module name), and then call
"import fpga.xilinx" in your SConsctruct file.  Right now, this is
very dirty, and lots of code will be executed at the import point, not
just made available to call later.  Caveat emptor
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