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Commits on Aug 10, 2012
  1. Merge of the acer A501 Code Drop

    authored
    (Mostly a clean merge from the a500 to a501 diff, however sim_detect
     remains a module for this codebase as in v1.0.0)
    
    Note the a101 may also now work with sim-detect.. needs testing
  2. Change spinlock to limited spin lock

    authored
    This code sometimes deadlocks; to prevent this spinlock for a while
    (10240 loops) but then just assume we can try again the next time
    the timer is triggered
    
    This prevents our kernel process from being killed by a watchdog; thus causing
    lulzactive to discontinue updating the CPU speed. either causing the system
    to be stuck at a low speed (sluggish) or enter a rare SoD state.
Commits on Jun 13, 2012
  1. Fix some minor A100 merge errors

    authored
    Merge of A100 code reverted a change in the A500 touchscreen, in addition
    to adding a simular fix to the A100 touchscreen.
    
    This fixes the code for the A500 w/o impacting the A100
  2. ARM: tegra: la: use lower LA for display clients

    Jon Mayo authored committed
    In order to prevent display underflow until latency allowance scaling is
    enabled, use the LA value corresponding to low threshold, instead of max
    LA for full FIFO.
    
    Bug 840688
    
    Original-Change-Id: If405e5931b817cdadec0294d487af1a4b921894a
    Reviewed-on: http://git-master/r/46342
    Reviewed-by: Jonathan Mayo <jmayo@nvidia.com>
    Tested-by: Jonathan Mayo <jmayo@nvidia.com>
    Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
    Reviewed-by: Kevin Huang <kevinh@nvidia.com>
    
    Rebase-Id: Rca14600452178655a8864b0b7bc7bf66576b8ca1
  3. video: tegra: dc: acquire window locks in an order to avoid a deadlock

    Nitin Kumbhar authored committed
    All window locks are grabbed while performing dc window updates. Currently, no
    particular locking order is followed for these locks. If user provided windows
    are not in order, this leads to deadlock due to race between flip ioctl and
    dc underflow reset worker.
    
    Now on all window locks are acquired in an order as below
    1. window A i.e. index 0
    2. window B i.e. index 1
    3. window C i.e. index 2
    
    And unlocked in the reverse order
    1. window C i.e. index 2
    2. window B i.e. index 1
    3. window A i.e. index 0
    
    Bug 936545
    
    Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
    Reviewed-on: http://git-master/r/83107
    (cherry picked from commit 68815fa87e879d0c783e8fd38f473f414806c0be)
    
    Change-Id: I3b3e00eaf91384c39ff74047f06af8199848ad92
    Reviewed-on: http://git-master/r/83405
    Tested-by: Nitin Kumbhar <nkumbhar@nvidia.com>
    Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
    Reviewed-by: Jon Mayo <jmayo@nvidia.com>
    Reviewed-by: Robert Morell <rmorell@nvidia.com>
  4. arm: tegra: cardhu: increase mc outstanding reqs for lower ram freqs

    Nitin Kumbhar authored committed
    The number of outstanding memory transactions is limited by a setting
    in MC. This leads to dc underflows which cause flickers on lcd panel.
    Increase the limits to optimal values which don't show dc underflows.
    
    Currently, the cap on outstanding requests for a frequency is calculated
    by linearly scaling up values for frequencies keeping minimum value at
    0x08. An exception has to be made to resolve dc underflows and
    lcd flickers.
    
    For cardhu, the lower ram frequencies are 25.5MHz, 51MHz and 102MHz.
    So increase minimum value to 0x10 and set 0x18 for 102MHz as an optimal
    value with which there are no dc underflows.
    
    Memory tables of Hynix-1GB, Hynix-2GB and Samsung-2GB memory types are
    updated with this change.
    
    Bug 932113
    Bug 946316
    
    Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
    Reviewed-on:http://git-master/r/87230
    (cherry picked from commit 39642475dc4401e666d4ade338c5b9e0741ce017)
    
    Change-Id: I19e8c04f4acc93f07121ee7da98588d2441147e8
    Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
    Reviewed-on: http://git-master/r/87236
    Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
    Reviewed-by: Edward Ahn <eahn@nvidia.com>
Commits on Jun 8, 2012
  1. remove pm_idle from lulzactive gov

    authored
    remove pm_idle implementation in favor of idle_notify
  2. remove pm_idle from interactive gov

    authored
    remove pm_idle implementation in favor of idle_notify
  3. TEGRA2 Link CPU governors

    authored
    When configure option TEGRA2_LINK_CPU_GOVERNORS is enabled
    updating the scaling_governor on CPU0 or CPU1 will cause both
    CPUs to change to the new governor.
    
    This is a workaround for many cpu apps that will not cleanly update
    both CPUs
  4. adjust bfq settings

    authored
  5. Clean up lulzactive logic

    authored
    previously steped up to lowest speed, and down to highest caused
    it to behave like performace
  6. video: tegra: dc: Fix support for YUV422R

    Francis Hart authored committed
    The tegra display controller supports the YUV422R planar surface format, but
    this was not handled by the dc driver.
    
    This change also fixes the YUV422RA planar format variation.
    
    Bug 914375
    
    Change-Id: I73ffd2f7434c71d8353c7e16ada5ac6b13fee86b
    Reviewed-on: http://git-master/r/69446
    Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
    Tested-by: Varun Colbert <vcolbert@nvidia.com>
    (cherry picked from commit a085ef1eeb332116f102d82af25f7a6451eb6329)
    Reviewed-on: http://git-master/r/73950
    Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
    Tested-by: Varun Wadekar <vwadekar@nvidia.com>
  7. Revert "video: tegra: dc: fix DSI pclk calculation"

    Jon Mayo authored committed
    This reverts commit 20f43df.
    
    Conflicts:
    
    	drivers/video/tegra/dc/dc.c
    
    This fix is no longer needed to boot.
    
    Change-Id: Ie8d877207b6a1d70c63834f234d7a7cc68a372bf
    Signed-off-by: Jon Mayo <jmayo@nvidia.com>
    Reviewed-on: http://git-master/r/74884
    Reviewed-by: Automatic_Commit_Validation_User
    Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com>
    Reviewed-on: http://git-master/r/75151
    Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
    Tested-by: Varun Wadekar <vwadekar@nvidia.com>
  8. video: tegra: dc: 1-shot bandwidth calculation

    Jon Mayo authored committed
    In one-shot mode(DSI) report emc rate as disabled to reduce bandwidth in
    this idle state. Use this same tegra_dc_clear_bandwidth() function to handle
    display disable for all types of displays.
    
    Bug 914917
    
    Change-Id: I84ca1341d71999b3558f9dadb103b258a1a6ab6f
    Signed-off-by: Jon Mayo <jmayo@nvidia.com>
    Reviewed-on: http://git-master/r/74652
    Reviewed-by: Automatic_Commit_Validation_User
    Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com>
    Tested-by: Xin Xie <xxie@nvidia.com>
    Reviewed-on: http://git-master/r/75536
    Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
    Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
  9. video: tegra: dc: enable emc clock on probe

    Nitin Kumbhar authored committed
    When dc->emc_clk_rate goes from 0 to non-zero the dispX.emc clock is
    enabled. This works with the sequence for probe and hotplug to have emc
    clock in the correct enable/disable state.
    
    Bug 927785
    Bug 917769
    
    Reviewed-on: http://git-master/r/76208
    
    Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
    Signed-off-by: Jon Mayo <jmayo@nvidia.com>
    
    Change-Id: I53cc8c5091967ce021dd3ec1e2bc75405dc8c45c
    Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
    Reviewed-on: http://git-master/r/76813
    Reviewed-by: Automatic_Commit_Validation_User
  10. video: tegra: dc: Add dc backup clock source support

    Alex Frid authored committed
    Add backup clock source option in dc platform configuration. Use
    backup source if fixed frequency pllp is specified as main source,
    but its rate can not be divided into pixel clock within required
    tolerance.
    
    928260
    
    Change-Id: I19bd9173276c6ea087f86361956809787875e979
    Reviewed-on: http://git-master/r/76033
    Signed-off-by: Alex Frid <afrid@nvidia.com>
    Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
    Reviewed-on: http://git-master/r/76818
    Reviewed-by: Automatic_Commit_Validation_User
  11. video: tegra: dsi: Refine the DSI clock calculation.

    Kevin Huang authored committed
    Reviewed-on: http://git-master/r/76406
    
    Change-Id: I6e5b37a88d6be4ba2cc81417fe3eadfd129bc899
    Signed-off-by: Kevin Huang <kevinh@nvidia.com>
    Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
    Reviewed-on: http://git-master/r/77306
    Reviewed-by: Automatic_Commit_Validation_User
  12. video: tegra: dc: enable dc ext from underflow reset worker

    Nitin Kumbhar authored committed
    DC ext is enabled only from _tegra_dc_controller_enable() which is not used
    from reset worker. Enable dc ext from _tegra_dc_controller_reset_enable()
    as well.
    
    Bug 933391
    
    Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
    Reviewed-on: http://git-master/r/78753
    (cherry picked from commit a099c612f91cc12a99325e39609b1f9001525be0)
    
    Change-Id: Ia95df85ea602174c2fd66888b21f7a6d264c176e
    Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
    Reviewed-on: http://git-master/r/82714
    Reviewed-by: Automatic_Commit_Validation_User
    Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com>
    Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
    Tested-by: Varun Wadekar <vwadekar@nvidia.com>
  13. video: tegra: dc: Activate dc registers properly for one-shot mode.

    Kevin Huang authored committed
    Enable GENERAL_ACT_REQ and HOST_TRIG_ENABLE at the same time.
    
    Bug 930840
    
    Signed-off-by: Kevin Huang <kevinh@nvidia.com>
    Reviewed-on: http://git-master/r/78638
    (cherry picked from commit 2f78c8e3c243b4c866ad54a550167abd94c200c1)
    
    Change-Id: If0ef97c4a2b1a0621152c02728edbbed064a5e34
    Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
    Reviewed-on: http://git-master/r/82715
    Reviewed-by: Automatic_Commit_Validation_User
    Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
    Tested-by: Varun Wadekar <vwadekar@nvidia.com>
  14. video: tegra: dc: protect dc extension disabling with a lock

    Nitin Kumbhar authored committed
    When dc gets many underflows, instances of reset worker can race
    to perform reset. dc ext was getting disabled outside critical region
    affecting display path. disable dc ext after getting the lock.
    
    Bug 936545
    
    Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
    Reviewed-on: http://git-master/r/83108
    (cherry picked from commit f9dcf7eee8ca8db28cee6fa9550044d1f746e843)
    
    Change-Id: Ie29dc66eb52c9be472c2d0db8c0014bfe1837ad4
    Reviewed-on: http://git-master/r/83406
    Reviewed-by: Simone Willett <swillett@nvidia.com>
    Tested-by: Simone Willett <swillett@nvidia.com>
  15. video: tegra: dc: use side-by-side stereo HDMI mode

    Andrija Bosnjakovic authored committed
    Add a config option to limit HDMI stereo 3D output to 74.25MHz pixel clock.
    
    When this option is set,
    substitute the frame pack stereo modes
    for side-by-side (half) left-right stereo modes
    to meet this pixel clock restriction.
    
    By default, do not use it (use frame packed HDMI mode as usual).
    
    Bug 938807
    
    Change-Id: I2ce2ca72cbb15ac1939af0f3386dd23650262435
    Reviewed-on: http://git-master/r/84252
    Reviewed-by: Andrija Bosnjakovic <abosnjakovic@nvidia.com>
    Tested-by: Andrija Bosnjakovic <abosnjakovic@nvidia.com>
    Reviewed-by: Jon Mayo <jmayo@nvidia.com>
  16. video: tegra: dc: in continuous mode mask VBLANK after first frame

    Nitin Kumbhar authored committed
    A V_BLANK interrupt for each frame does not allow long lp2 idle intervals.
    If all windows are clean, mask V_BLANK interrupt after processing it
    for updating smart dimmer. It's unmasked again when a new window update
    is performed. This will schedule a work for updating smart dimmer for
    the new frame.
    
    Bug 920110
    
    Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
    Reviewed-on: http://git-master/r/85137
    (cherry picked from commit 68398090aee22cf02069e5767c3e9a062b0fc2f6)
    
    Change-Id: I588328bfd0d6036febed236dc07f441878aa81d1
    Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
    Reviewed-on: http://git-master/r/85166
    Reviewed-by: Lokesh Pathak <lpathak@nvidia.com>
    Tested-by: Lokesh Pathak <lpathak@nvidia.com>
  17. video: tegra: dc: consolidate underflow code

    Jon Mayo authored committed
    Move underflow handling out of the irq handler and into a workqueue.
    
    Change-Id: I289d0a4c4e632a229e46d8e7f82e637409813807
    Signed-off-by: Jon Mayo <jmayo@nvidia.com>
    Reviewed-on: http://git-master/r/74427
    Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
    Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
    Reviewed-on: http://git-master/r/75143
    Reviewed-by: Automatic_Commit_Validation_User
    Tested-by: Varun Wadekar <vwadekar@nvidia.com>
    Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
  18. Add Lulzactive Governor v2

    authored
    Lulzactive Governor v2
    Author: Tegrak
    
    Based on "interactive" governor
    Inspired by erasmux's "smartass" governor (included in Flykernel)
    
    I've adjusted some of the tunables to default to better tegra2 values
    
    additional information at:
    
    http://tegrak2x.blogspot.com/2011/11/lulzactive-governor-v2.html
    
    (Note at this time I'm having problems with the dedicated settings app
     SetCPU seems able to adjust the tunables, however is not providing
     clean metadata)
  19. @paolo-github

    block: introduce the BFQ-v3r4 I/O sched for 2.6.39

    paolo-github authored committed
    Add the BFQ-v3r4 I/O scheduler to 2.6.39.
    The general structure is borrowed from CFQ, as much of the code. A (bfq_)queue
    is associated to each task doing I/O on a device, and each time a scheduling
    decision has to be taken a queue is selected and it is served until it expires.
    
    The main differences are:
        - Slices are given in the service domain: tasks are assigned budgets,
          measured in number of sectors. Once got the disk, a task must
          however consume its assigned budget within a configurable maximum time
          (by default, the maximum possible value of the budgets is automaticall
          computed to comply with this timeout). This allows the desired latency
          vs "throughput boosting" tradeoff to be set.
    
        - Budgets are scheduled according to a variant of WF2Q+, implemented
          using an augmented rb-tree to take eligibility into account while
          preserving an O(log N) overall complexity.
    
        - A low-latency tunable is provided; if enabled, both interactive and soft
          real-time applications are guaranteed very low latency.
    
        - Latency guarantees are preserved also in presence of NCQ.
    
        - Useful features borrowed from CFQ: cooperating-queues merging (with
          some additional optimizations with respect to the original CFQ version),
          static fallback queue for OOM.
    
        - BFQ supports full hierarchical scheduling, exporting a cgroups
          interface.  Each node has a full scheduler, so each group can
          be assigned its own ioprio and an ioprio_class.
    
        - If the cgroups interface is used, weights can be explictly assigned,
          otherwise ioprio values are mapped to weights using the relation
          weight = IOPRIO_BE_NR - ioprio.
    
        - ioprio classes are served in strict priority order, i.e., lower
          priority queues are not served as long as there are higher priority
          queues.  Among queues in the same class the bandwidth is distributed
          in proportion to the weights of each queue. A very thin extra bandwidth
          is however guaranteed to the Idle class, to prevent it from starving.
    
    Regarding what has not changed it is worth noting:
        - the handling of cfq_io_contexts to associate queues to tasks.
          Much of the code has been reused just renaming it.  (There is room for
          code sharing with CFQ but we wanted to minimize the impact of this
          patch.)
    
        - The handling of async queues.
    
        - The handling of idle windows.
    
        - The handling of merging.
    
        - The heuristics to assert that a task is worth an idle window (with
          minor modifications to hw_tag/CIC_SEEKY detection).
    
    Signed-off-by: Paolo Valente <paolo.valente@unimore.it>
    Signed-off-by: Arianna Avanzini <avanzini.arianna@gmail.com>
  20. @paolo-github

    block: cgroups, kconfig, build bits for BFQ-v3r4-2.6.39

    paolo-github authored committed
    Add a Kconfig option and do the related Makefile changes to compile
    the BFQ I/O scheduler.  Also let the cgroups subsystem know about the
    BFQ I/O controller.
    
    Signed-off-by: Fabio Checconi <fabio@gandalf.sssup.it>
    Signed-off-by: Paolo Valente <paolo.valente@unimore.it>
    Signed-off-by: Arianna Avanzini <avanzini.arianna@gmail.com>
  21. @paolo-github

    block: prepare I/O context code for BFQ-v3r4 for 2.6.39

    paolo-github authored committed
    BFQ uses struct cfq_io_context to store its per-process per-device data,
    reusing the same code for cic handling of CFQ.  The code is not shared
    ATM to minimize the impact of these patches.
    
    This patch introduces a new hlist to each io_context to store all the
    cic's allocated by BFQ to allow calling the right destructor on module
    unload; the radix tree used for cic lookup needs to be duplicated
    because it can contain dead keys inserted by a scheduler and later
    retrieved by the other one.
    
    Update the io_context exit and free paths to take care also of
    the BFQ cic's.
    
    Change the type of cfqq inside struct cfq_io_context to void *
    to use it also for BFQ per-queue data.
    
    A new bfq-specific ioprio_changed field is necessary, too, to avoid
    clobbering cfq's one, so switch ioprio_changed to a bitmap, with one
    element per scheduler.
    
    Signed-off-by: Fabio Checconi <fabio@gandalf.sssup.it>
    Signed-off-by: Paolo Valente <paolo.valente@unimore.it>
    Signed-off-by: Arianna Avanzini <avanzini.arianna@gmail.com>
Commits on Jun 5, 2012
  1. Fix calls to 'stat' on OSX

    authored
    When we are being built on Darwin, ensure we use the BSD
    format (and not GNU format) for stat.
    
    This simply changes the arguments to obtain the same data
  2. Optimize CFLAGS for tegra

    authored
  3. Ensure moduels in new 4.6.3 toolchain build without pic

    authored
    We must ensure modules build without pic or they will fail to load into
    the running kernel
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