diff --git a/xc7/fasm2bels/bram_models.py b/xc7/fasm2bels/bram_models.py
index 3db8d7ea44..99344f23cb 100644
--- a/xc7/fasm2bels/bram_models.py
+++ b/xc7/fasm2bels/bram_models.py
@@ -783,7 +783,7 @@ def make_target_feature(feature):
         elif 'RAMB18_Y0.READ_WIDTH_A_2' in set_features:
             READ_WIDTH_A = 4
         elif 'RAMB18_Y0.READ_WIDTH_A_4' in set_features:
-            READ_WIDTH_A = 8
+            READ_WIDTH_A = 9
         elif 'RAMB18_Y0.READ_WIDTH_A_9' in set_features:
             READ_WIDTH_A = 18
         elif 'RAMB18_Y0.READ_WIDTH_A_18' in set_features:
@@ -796,7 +796,7 @@ def make_target_feature(feature):
         elif 'RAMB18_Y0.READ_WIDTH_B_2' in set_features:
             READ_WIDTH_B = 4
         elif 'RAMB18_Y0.READ_WIDTH_B_4' in set_features:
-            READ_WIDTH_B = 8
+            READ_WIDTH_B = 9
         elif 'RAMB18_Y0.READ_WIDTH_B_9' in set_features:
             READ_WIDTH_B = 18
         elif 'RAMB18_Y0.READ_WIDTH_B_18' in set_features:
@@ -829,7 +829,7 @@ def make_target_feature(feature):
         elif 'RAMB18_Y0.WRITE_WIDTH_A_2' in set_features:
             WRITE_WIDTH_A = 4
         elif 'RAMB18_Y0.WRITE_WIDTH_A_4' in set_features:
-            WRITE_WIDTH_A = 8
+            WRITE_WIDTH_A = 9
         elif 'RAMB18_Y0.WRITE_WIDTH_A_9' in set_features:
             WRITE_WIDTH_A = 18
         elif 'RAMB18_Y0.WRITE_WIDTH_A_18' in set_features:
@@ -842,7 +842,7 @@ def make_target_feature(feature):
         elif 'RAMB18_Y0.WRITE_WIDTH_B_2' in set_features:
             WRITE_WIDTH_B = 4
         elif 'RAMB18_Y0.WRITE_WIDTH_B_4' in set_features:
-            WRITE_WIDTH_B = 8
+            WRITE_WIDTH_B = 9
         elif 'RAMB18_Y0.WRITE_WIDTH_B_9' in set_features:
             WRITE_WIDTH_B = 18
         elif 'RAMB18_Y0.WRITE_WIDTH_B_18' in set_features:
diff --git a/xc7/fasm2bels/fasm2bels.py b/xc7/fasm2bels/fasm2bels.py
index c37833a019..ff117aa195 100644
--- a/xc7/fasm2bels/fasm2bels.py
+++ b/xc7/fasm2bels/fasm2bels.py
@@ -265,6 +265,11 @@ def main():
         net_map = load_net_list(conn, args.rr_graph, args.route_file)
         top.set_net_map(net_map)
 
+    if args.part:
+        with open(os.path.join(args.db_root, args.part + '.json')) as f:
+            part_data = json.load(f)
+            top.set_io_banks(part_data['iobanks'])
+
     if args.eblif:
         with open(args.eblif) as f:
             parsed_eblif = eblif.parse_blif(f)
@@ -313,6 +318,9 @@ def main():
         for l in top.output_disabled_drcs():
             print(l, file=f)
 
+        for l in top.output_extra_tcl():
+            print(l, file=f)
+
 
 if __name__ == "__main__":
     main()
diff --git a/xc7/fasm2bels/hclk_ioi3_models.py b/xc7/fasm2bels/hclk_ioi3_models.py
index da3fad7429..89792d57ed 100644
--- a/xc7/fasm2bels/hclk_ioi3_models.py
+++ b/xc7/fasm2bels/hclk_ioi3_models.py
@@ -9,6 +9,21 @@ def process_hclk_ioi3(conn, top, tile, features):
             have_idelayctrl = True
             break
 
+        if 'VREF' in f.feature:
+            # HCLK_IOI3_X113Y26.VREF.V_675_MV
+            tile, vref_str, vref_value = f.feature.split('.')
+            assert vref_str == 'VREF', f
+            v_str, value, mv_str = vref_value.split('_')
+            assert v_str == 'V', f
+            assert mv_str == 'MV', f
+
+            iobank = top.find_iobank(tile.split('_')[-1])
+
+            top.add_extra_tcl_line(
+                'set_property INTERNAL_VREF 0.{VREF} [get_iobanks {iobank}]'.
+                format(VREF=value, iobank=iobank)
+            )
+
     if not have_idelayctrl:
         return
 
diff --git a/xc7/fasm2bels/verilog_modeling.py b/xc7/fasm2bels/verilog_modeling.py
index 73e811d150..f074428b27 100644
--- a/xc7/fasm2bels/verilog_modeling.py
+++ b/xc7/fasm2bels/verilog_modeling.py
@@ -1239,6 +1239,15 @@ def __init__(self, db, grid, conn, name="top"):
         # .cname value.
         self.cname_map = {}
 
+        # Extra TCL lines (e.g. VREF)
+        self.extra_tcl = []
+
+        # IO bank lookup (if part was provided).
+        self.iobank_lookup = {}
+
+    def add_extra_tcl_line(self, tcl_line):
+        self.extra_tcl.append(tcl_line)
+
     def set_iostandard_defs(self, defs):
         self.iostandard_defs = defs
 
@@ -1703,3 +1712,12 @@ def add_to_cname_map(self, parsed_eblif):
 
     def lookup_cname(self, pin, idx, net):
         return self.cname_map.get((pin, idx, net))
+
+    def output_extra_tcl(self):
+        return self.extra_tcl
+
+    def set_io_banks(self, iobanks):
+        self.iobank_lookup = dict((v, int(k)) for k, v in iobanks.items())
+
+    def find_iobank(self, hclk_ioi3_tile):
+        return self.iobank_lookup[hclk_ioi3_tile]
diff --git a/xc7/tests/soc/litex/mini/minilitex.xdc b/xc7/tests/soc/litex/mini/minilitex.xdc
index e24769c726..e69de29bb2 100644
--- a/xc7/tests/soc/litex/mini/minilitex.xdc
+++ b/xc7/tests/soc/litex/mini/minilitex.xdc
@@ -1 +0,0 @@
-set_property INTERNAL_VREF 0.675 [get_iobanks 34]
diff --git a/xc7/tests/soc/litex/mini/minilitex_arty.v b/xc7/tests/soc/litex/mini/minilitex_arty.v
index 9b0078b39e..2536ec939a 100644
--- a/xc7/tests/soc/litex/mini/minilitex_arty.v
+++ b/xc7/tests/soc/litex/mini/minilitex_arty.v
@@ -1420,6 +1420,7 @@ VexRiscv VexRiscv(
 	.iBusWishbone_WE(vexriscv_ibus_we)
 );
 
+(* LOC="PLLE2_ADV_X1Y1" *)
 PLLE2_ADV #(
 	.CLKFBOUT_MULT(4'd8),
 	.CLKIN1_PERIOD(10.0),