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Print debug when source is reading EDID from hdmi_in ports

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fallen committed Nov 24, 2015
1 parent 481b837 commit 5d771720b6553665b87058ae7fbe1d077dd0a5f6
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@@ -33,6 +33,33 @@ static int hdmi_in0_hres, hdmi_in0_vres;
extern void processor_update(void);
static int hdmi_in0_edid_started = 0;
static int hdmi_in0_edid_finished = 0;
void hdmi_in0_edid_isr(void)
{
static int edid_read_start_time;
static int edid_read_finished_time;
if(hdmi_in0_edid_ev_status_read()) {
elapsed(&edid_read_start_time, -1);
edid_read_finished_time = edid_read_start_time;
if(hdmi_in0_debug)
printf("hdmi_in0: reading EDID\n");
hdmi_in0_edid_started = 1;
} else {
elapsed(&edid_read_finished_time, 0);
if(edid_read_finished_time - edid_read_start_time < 0)
edid_read_finished_time += timer0_reload_read();
if(hdmi_in0_debug) {
int dt = edid_read_finished_time - edid_read_start_time;
printf("hdmi_in0: finished reading EDID after %d ns\n", dt*1.0e9/(identifier_frequency_read()));
}
hdmi_in0_edid_finished = 1;
}
hdmi_in0_edid_ev_pending_write(1); // clearing IRQ pending flag
}
void hdmi_in0_isr(void)
{
int fb_index = -1;
View
@@ -6,6 +6,7 @@ extern int hdmi_in0_fb_index;
unsigned int hdmi_in0_framebuffer_base(char n);
void hdmi_in0_edid_isr(void);
void hdmi_in0_isr(void);
void hdmi_in0_init_video(int hres, int vres);
void hdmi_in0_disable(void);
View
@@ -33,6 +33,33 @@ static int hdmi_in1_hres, hdmi_in1_vres;
extern void processor_update(void);
static int hdmi_in1_edid_started = 0;
static int hdmi_in1_edid_finished = 0;
void hdmi_in1_edid_isr(void)
{
static int edid_read_start_time;
static int edid_read_finished_time;
if(hdmi_in1_edid_ev_status_read()) {
elapsed(&edid_read_start_time, -1);
edid_read_finished_time = edid_read_start_time;
if(hdmi_in1_debug)
printf("hdmi_in1: reading EDID\n");
hdmi_in1_edid_started = 1;
} else {
elapsed(&edid_read_finished_time, 0);
if(edid_read_finished_time - edid_read_start_time < 0)
edid_read_finished_time += timer0_reload_read();
if(hdmi_in1_debug) {
int dt = edid_read_finished_time - edid_read_start_time;
printf("hdmi_in1: finished reading EDID after %d ns\n", dt*1.0e9/(identifier_frequency_read()));
}
hdmi_in1_edid_finished = 1;
}
hdmi_in1_edid_ev_pending_write(1); // clearing IRQ pending flag
}
void hdmi_in1_isr(void)
{
int fb_index = -1;
View
@@ -6,6 +6,7 @@ extern int hdmi_in1_fb_index;
unsigned int hdmi_in1_framebuffer_base(char n);
void hdmi_in1_edid_isr(void);
void hdmi_in1_isr(void);
void hdmi_in1_init_video(int hres, int vres);
void hdmi_in1_disable(void);
View
@@ -15,10 +15,14 @@ void isr(void)
if(irqs & (1 << UART_INTERRUPT))
uart_isr();
#ifdef CSR_HDMI_IN0_BASE
if(irqs & (1 << HDMI_IN0_EDID_INTERRUPT))
hdmi_in0_edid_isr();
if(irqs & (1 << HDMI_IN0_INTERRUPT))
hdmi_in0_isr();
#endif
#ifdef CSR_HDMI_IN1_BASE
if(irqs & (1 << HDMI_IN1_EDID_INTERRUPT))
hdmi_in1_edid_isr();
if(irqs & (1 << HDMI_IN1_INTERRUPT))
hdmi_in1_isr();
#endif
View
@@ -4,6 +4,7 @@
from migen.genlib.fsm import FSM, NextState
from migen.genlib.misc import chooser
from migen.bank.description import CSRStorage, CSRStatus, AutoCSR
from migen.bank.eventmanager import EventManager, EventSourceProcess, _EventSource
_default_edid = [
0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x3D, 0x17, 0x32, 0x12, 0x2A, 0x6A, 0xBF, 0x00,
@@ -17,11 +18,45 @@
]
# EventSource which raises an IRQ on both rising and falling edge
# of the trigger
class EventSourceEdge(Module, _EventSource):
def __init__(self, trigger_reset_value=0):
_EventSource.__init__(self)
self.captured_trigger = Signal()
self.trigger_r = Signal(reset=trigger_reset_value)
self.comb += [
self.status.eq(self.captured_trigger),
]
self.sync += [
If(~self.pending & (self.trigger_r ^ self.trigger),
self.pending.eq(1),
self.captured_trigger.eq(self.trigger),
),
If(self.clear,
self.pending.eq(0),
),
self.trigger_r.eq(self.trigger),
]
class EDIDIrq(Module, AutoCSR):
def __init__(self):
self.submodules.ev = EventManager()
def finalize(self, *args, **kwargs):
self.ev.finalize()
Module.finalize(self, *args, **kwargs)
class EDID(Module, AutoCSR):
def __init__(self, pads, default=_default_edid):
self._hpd_notif = CSRStatus()
self._hpd_en = CSRStorage()
self.specials.mem = Memory(8, 128, init=default)
self.edid_read_started = EventSourceEdge(trigger_reset_value=1)
###
@@ -130,6 +165,10 @@ def __init__(self, pads, default=_default_edid):
self.submodules.fsm = fsm = FSM()
# Will trig an IRQ on the falling edge of edid_read_started signal
# i.e. when leaving the WAIT_START state meaning EDID is being read
self.comb += self.edid_read_started.trigger.eq(fsm.ongoing("WAIT_START"))
fsm.act("WAIT_START")
fsm.act("RCV_ADDRESS",
If(counter == 8,
View
@@ -5,6 +5,8 @@
from gateware.hdmi_out import HDMIOut
from gateware.encoder import EncoderReader, Encoder
from gateware.streamer import USBStreamer
from gateware.hdmi_in.edid import EDIDIrq
class VideomixerSoC(BaseSoC):
csr_map = {
@@ -14,12 +16,16 @@ class VideomixerSoC(BaseSoC):
"hdmi_in0_edid_mem": 23,
"hdmi_in1": 24,
"hdmi_in1_edid_mem": 25,
"hdmi_in0_edid": 26,
"hdmi_in1_edid": 27,
}
csr_map.update(BaseSoC.csr_map)
interrupt_map = {
"hdmi_in0": 3,
"hdmi_in1": 4,
"hdmi_in0_edid": 5,
"hdmi_in1_edid": 6,
}
interrupt_map.update(BaseSoC.interrupt_map)
@@ -38,6 +44,12 @@ def __init__(self, platform, **kwargs):
self.hdmi_out0.driver.clocking) # share clocking with hdmi_out0
# since no PLL_ADV left.
self.submodules.hdmi_in0_edid = EDIDIrq()
self.hdmi_in0_edid.ev.edid_read = self.hdmi_in0.edid.edid_read_started
self.submodules.hdmi_in1_edid = EDIDIrq()
self.hdmi_in1_edid.ev.edid_read = self.hdmi_in1.edid.edid_read_started
platform.add_platform_command("""INST PLL_ADV LOC=PLL_ADV_X0Y0;""") # all PLL_ADV are used: router needs help...
platform.add_platform_command("""PIN "hdmi_out_pix_bufg.O" CLOCK_DEDICATED_ROUTE = FALSE;""")
platform.add_platform_command("""PIN "hdmi_out_pix_bufg_1.O" CLOCK_DEDICATED_ROUTE = FALSE;""")
@@ -56,8 +68,8 @@ def __init__(self, platform, **kwargs):
class HDMI2USBSoC(VideomixerSoC):
csr_map = {
"encoder_reader": 26,
"encoder": 27
"encoder_reader": 28,
"encoder": 29
}
csr_map.update(VideomixerSoC.csr_map)
mem_map = {

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