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base fork: fallen/NetBSD
base: 1dabf3fa0441
...
head fork: fallen/NetBSD
compare: ed27bd4878a6
  • 2 commits
  • 4 files changed
  • 0 commit comments
  • 1 contributor
4 TODO
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@@ -20,3 +20,7 @@ LM32 port TODO:
- sparc64: sys/arch/sparc64/sparc64/copy.S:ENTRY(copyout)
- usermod: sys/arch/usermode/usermode/copy.c
- vax: sys/arch/vax/boot/boot/if_le.c: copyout(void *f, int dest, int len)
+
+- Decide what to do with SH_HAS_VIRTUAL_ALIAS stuff
+ - It seems that as long as total_cache_size <= page size (with total_cache_size = line size * number of sets * cache associativity)
+ there is no cache aliasing issue
1  sys/arch/lm32/conf/files.lm32
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@@ -3,4 +3,3 @@ include "arch/lm32/conf/majors.lm32"
file arch/lm32/lm32/pmap.c
file arch/lm32/lm32/copy.c
file arch/lm32/lm32/lock_stubs.S
-file arch/lm32/lm32/mmu.c
46 sys/arch/lm32/include/cpu.h
View
@@ -63,7 +63,7 @@ struct pmap;
#define lm32_dcache_invalidate() do { \
asm volatile("wcsr DCC, r0"); \
- } while(0);
+ } while(0)
#define lm32_icache_invalidate() do { \
asm volatile("wcsr ICC, r0\n" \
@@ -71,12 +71,48 @@ struct pmap;
"nop\n" \
"nop\n" \
"nop\n"); \
- } while(0);
+ } while(0)
+
+#define lm32_itlb_invalidate_line(vaddr) do { \
+ vaddr_t ___va = vaddr | 0x20; \
+ asm volatile ("wcsr tlbvaddr, %0" :: "r"(___va) : ); \
+ } while(0)
+
+#define lm32_dtlb_invalidate_line(vaddr) do { \
+ vaddr_t ___va = vaddr | 0x21; \
+ asm volatile ("wcsr tlbvaddr, %0" :: "r"(___va) : ); \
+ } while(0)
+
+#define lm32_tlb_invalidate_line(vaddr) do { \
+ lm32_itlb_invalidate_line(vaddr); \
+ lm32_dtlb_invalidate_line(vaddr); \
+ } while(0)
+
+#define lm32_itlb_update(va, pa) do { \
+ asm volatile ("wcsr tlbvaddr, %0" :: "r"(va) : ); \
+ asm volatile ("wcsr tlbpaddr, %0" :: "r"(pa) : ); \
+ } while (0)
+
+#define lm32_dtlb_update(va, pa) do { \
+ asm volatile ("ori %0, %0, 1\n\t" \
+ "wcsr tlbvaddr, %0" :: "r"(va) : ); \
+ asm volatile ("ori %0, %0, 1\n\t" \
+ "wcsr tlbpaddr, %0" :: "r"(pa) : ); \
+ } while (0)
+
+static inline void lm32_mmu_start(void)
+{
+ unsigned int old_psw;
+ asm volatile("rcsr %0, PSW\n\t"
+ "ori %0, %0, 72\n\t"
+ "wcsr PSW, %0" : "=&r"(old_psw) :: );
+}
+
+#define __ways 1
+#define __cache_size 256
+#define __cache_line_size 16
-void lm32_dtlb_invalidate_line(vaddr_t vaddr);
-void lm32_itlb_invalidate_line(vaddr_t vaddr);
-
/*
* a bunch of this belongs in cpuvar.h; move it later..
*/
18 sys/arch/lm32/lm32/mmu.c
View
@@ -1,18 +0,0 @@
-
-/*
- * COPYRIGHT (C) 2013 Yann Sionneau <yann.sionneau@gmail.com>
- */
-
-#include <lm32/cpu.h>
-
-void lm32_dtlb_invalidate_line(vaddr_t vaddr)
-{
- vaddr |= 0x21;
- asm volatile ("wcsr tlbvaddr, %0" :: "r"(vaddr) : );
-}
-
-void lm32_itlb_invalidate_line(vaddr_t vaddr)
-{
- vaddr |= 0x20;
- asm volatile ("wcsr tlbvaddr, %0" :: "r"(vaddr) : );
-}

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