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4  TODO
@@ -20,3 +20,7 @@ LM32 port TODO:
20 20
   - sparc64: sys/arch/sparc64/sparc64/copy.S:ENTRY(copyout)
21 21
   - usermod: sys/arch/usermode/usermode/copy.c
22 22
   - vax: sys/arch/vax/boot/boot/if_le.c: copyout(void *f, int dest, int len)
  23
+
  24
+- Decide what to do with SH_HAS_VIRTUAL_ALIAS stuff
  25
+  - It seems that as long as total_cache_size <= page size (with total_cache_size = line size * number of sets * cache associativity)
  26
+    there is no cache aliasing issue
1  sys/arch/lm32/conf/files.lm32
@@ -3,4 +3,3 @@ include "arch/lm32/conf/majors.lm32"
3 3
 file 	arch/lm32/lm32/pmap.c
4 4
 file 	arch/lm32/lm32/copy.c
5 5
 file    arch/lm32/lm32/lock_stubs.S
6  
-file    arch/lm32/lm32/mmu.c
46  sys/arch/lm32/include/cpu.h
@@ -63,7 +63,7 @@ struct pmap;
63 63
 
64 64
 #define lm32_dcache_invalidate() do { \
65 65
 					asm volatile("wcsr DCC, r0"); \
66  
-				} while(0);
  66
+				} while(0)
67 67
 
68 68
 #define lm32_icache_invalidate() do { \
69 69
 					asm volatile("wcsr ICC, r0\n" \
@@ -71,12 +71,48 @@ struct pmap;
71 71
 						     "nop\n" \
72 72
 						     "nop\n" \
73 73
 						     "nop\n"); \
74  
-				} while(0);
  74
+				} while(0)
  75
+
  76
+#define lm32_itlb_invalidate_line(vaddr) do { \
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+						vaddr_t ___va = vaddr | 0x20; \
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+						asm volatile ("wcsr tlbvaddr, %0" :: "r"(___va) : ); \
  79
+				} while(0)
  80
+
  81
+#define lm32_dtlb_invalidate_line(vaddr) do { \
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+						vaddr_t ___va = vaddr | 0x21; \
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+						asm volatile ("wcsr tlbvaddr, %0" :: "r"(___va) : ); \
  84
+				} while(0)
  85
+
  86
+#define lm32_tlb_invalidate_line(vaddr) do { \
  87
+						lm32_itlb_invalidate_line(vaddr); \
  88
+						lm32_dtlb_invalidate_line(vaddr); \
  89
+					} while(0)
  90
+
  91
+#define lm32_itlb_update(va, pa) do { \
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+					asm volatile	("wcsr tlbvaddr, %0" :: "r"(va) : ); \
  93
+					asm volatile	("wcsr tlbpaddr, %0" :: "r"(pa) : ); \
  94
+				} while (0)
  95
+
  96
+#define lm32_dtlb_update(va, pa) do { \
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+					asm volatile	("ori %0, %0, 1\n\t" \
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+							 "wcsr tlbvaddr, %0" :: "r"(va) : ); \
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+					asm volatile	("ori %0, %0, 1\n\t" \
  100
+							 "wcsr tlbpaddr, %0" :: "r"(pa) : ); \
  101
+				} while (0)
  102
+
  103
+static inline void lm32_mmu_start(void)
  104
+{
  105
+	unsigned int old_psw;
  106
+	asm volatile("rcsr %0, PSW\n\t"
  107
+		     "ori %0, %0, 72\n\t"
  108
+		     "wcsr PSW, %0" : "=&r"(old_psw) :: );
  109
+}
  110
+
  111
+#define __ways 1
  112
+#define __cache_size 256
  113
+#define __cache_line_size 16
75 114
 
76 115
 
77  
-void lm32_dtlb_invalidate_line(vaddr_t vaddr);
78  
-void lm32_itlb_invalidate_line(vaddr_t vaddr);
79  
-
80 116
 /*
81 117
  * a bunch of this belongs in cpuvar.h; move it later..
82 118
  */
18  sys/arch/lm32/lm32/mmu.c
... ...
@@ -1,18 +0,0 @@
1  
-
2  
-/*
3  
- * COPYRIGHT (C) 2013 Yann Sionneau <yann.sionneau@gmail.com>
4  
- */
5  
-
6  
-#include <lm32/cpu.h>
7  
-
8  
-void lm32_dtlb_invalidate_line(vaddr_t vaddr)
9  
-{
10  
-	vaddr |= 0x21;
11  
-	asm volatile ("wcsr tlbvaddr, %0" :: "r"(vaddr) : );
12  
-}
13  
-
14  
-void lm32_itlb_invalidate_line(vaddr_t vaddr)
15  
-{
16  
-	vaddr |= 0x20;
17  
-	asm volatile ("wcsr tlbvaddr, %0" :: "r"(vaddr) : );
18  
-}

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