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14  sys/arch/lm32/include/intr.h
@@ -5,6 +5,20 @@
5 5
 
6 6
 #include <lm32/psl.h>
7 7
 
  8
+/* Define the various Interrupt Priority Levels */
  9
+
  10
+/* Hardware Interrupt Priority Levels are not mutually exclusive. */
  11
+
  12
+#define		IPL_NONE	0
  13
+#define		IPL_SOFTCLOCK	1
  14
+#define		IPL_SOFTBIO	1
  15
+#define		IPL_SOFTNET	1
  16
+#define		IPL_SOFTSERIAL	1
  17
+#define		IPL_VM		1
  18
+#define		IPL_SCHED	1
  19
+#define		IPL_HIGH	1
  20
+#define		NIPL		2
  21
+
8 22
 static __inline int _get_irq_mask(void)
9 23
 {
10 24
 	int mask;
15  sys/arch/lm32/include/pmap.h
@@ -2,6 +2,8 @@
2 2
 
3 3
 #ifndef _LM32_PMAP_H_
4 4
 #define _LM32_PMAP_H_
  5
+#include <sys/resource.h>
  6
+#include <uvm/uvm_page.h>
5 7
 
6 8
 #if !defined(_LOCORE) && (defined(MODULAR) || defined(_MODULE))
7 9
 
@@ -9,6 +11,18 @@ __CTASSERT(sizeof(struct vm_page_md) == sizeof(uintptr_t)*5);
9 11
 
10 12
 #endif /* !LOCORE && (MODULAR || _MODULE) */
11 13
 
  14
+
  15
+/*
  16
+ * Pmap stuff
  17
+ */
  18
+struct pmap {
  19
+	pt_entry_t		*pm_ptab;	/* KVA of page table */
  20
+	u_int			pm_count;	/* pmap reference count */
  21
+	struct pmap_statistics	pm_stats;	/* pmap statistics */
  22
+	int pm_refcnt;
  23
+	int			pm_ptpages;	/* more stats: PT pages */
  24
+};
  25
+
12 26
 #define L2_SLOT_PTE	(KERNBASE/NBPD_L2-1) /* 767: for recursive PDP map */
13 27
 #define L2_SLOT_KERN	(KERNBASE/NBPD_L2)   /* 768: start of kernel space */
14 28
 
@@ -19,5 +33,6 @@ __CTASSERT(sizeof(struct vm_page_md) == sizeof(uintptr_t)*5);
19 33
 
20 34
 void tlbflush(void);
21 35
 void pmap_load(void);
  36
+void pmap_reference(pmap_t pmap);
22 37
 
23 38
 #endif /* !_LM32_PMAP_H_ */
36  sys/arch/lm32/lm32/pmap.c
@@ -2,6 +2,12 @@
2 2
  * COPYRIGHT (C) 2013 Yann Sionneau <yann.sionneau@gmail.com>
3 3
  */
4 4
 
  5
+#include <lm32/pmap.h>
  6
+#include <sys/types.h>
  7
+#include <lm32/cpu.h>
  8
+#include <sys/systm.h>
  9
+#include <uvm/uvm_map.h>
  10
+#include <uvm/uvm_extern.h>
5 11
 void tlbflush(void)
6 12
 {
7 13
 	/* flush DTLB */
@@ -15,6 +21,13 @@ void tlbflush(void)
15 21
 		     "wcsr tlbvaddr, r11" ::: "r11");	
16 22
 }
17 23
 
  24
+void
  25
+pmap_reference(pmap_t pmap)
  26
+{
  27
+
  28
+	pmap->pm_refcnt++;
  29
+}
  30
+
18 31
 /*
19 32
  * pmap_load: perform the actual pmap switch
20 33
  *
@@ -32,7 +45,6 @@ pmap_load(void)
32 45
 	struct pmap *pmap, *oldpmap;
33 46
 	struct lwp *l;
34 47
 	struct pcb *pcb;
35  
-	cpuid_t cid;
36 48
 	uint64_t ncsw;
37 49
 
38 50
 	kpreempt_disable();
@@ -55,18 +67,6 @@ pmap_load(void)
55 67
 	pcb = lwp_getpcb(l);
56 68
 
57 69
 	if (pmap == oldpmap) {
58  
-		if (!pmap_reactivate(pmap)) {
59  
-			u_int gen = uvm_emap_gen_return();
60  
-
61  
-			/*
62  
-			 * pmap has been changed during deactivated.
63  
-			 * our tlb may be stale.
64  
-			 */
65  
-
66  
-			tlbflush();
67  
-			uvm_emap_update(gen);
68  
-		}
69  
-
70 70
 		ci->ci_want_pmapload = 0;
71 71
 		kpreempt_enable();
72 72
 		return;
@@ -78,21 +78,11 @@ pmap_load(void)
78 78
 
79 79
 	pmap_reference(pmap);
80 80
 
81  
-	cid = cpu_index(ci);
82  
-	kcpuset_atomic_clear(oldpmap->pm_cpus, cid);
83  
-	kcpuset_atomic_clear(oldpmap->pm_kernel_cpus, cid);
84  
-
85  
-	KASSERT(!kcpuset_isset(pmap->pm_cpus, cid));
86  
-	KASSERT(!kcpuset_isset(pmap->pm_kernel_cpus, cid));
87  
-
88 81
 	/*
89 82
 	 * Mark the pmap in use by this CPU.  Again, we must synchronize
90 83
 	 * with TLB shootdown interrupts, so set the state VALID first,
91 84
 	 * then register us for shootdown events on this pmap.
92 85
 	 */
93  
-	ci->ci_tlbstate = TLBSTATE_VALID;
94  
-	kcpuset_atomic_set(pmap->pm_cpus, cid);
95  
-	kcpuset_atomic_set(pmap->pm_kernel_cpus, cid);
96 86
 	ci->ci_pmap = pmap;
97 87
 
98 88
 
4  sys/arch/milkymist/include/cpu.h
... ...
@@ -1,6 +1,10 @@
1 1
 /*	$NetBSD: cpu.h,v 1.3 2002/03/04 14:36:13 uch Exp $	*/
2 2
 
  3
+#ifndef _MACHINE_CPU_H_
  4
+#define _MACHINE_CPU_H_
3 5
 #define curcpu() (&cpu_info_store)
4 6
 extern struct cpu_info cpu_info_store;
5 7
 
6 8
 #include <lm32/cpu.h>
  9
+
  10
+#endif
13  sys/arch/milkymist/include/intr.h
@@ -40,19 +40,6 @@
40 40
 #include <machine/cpu.h>
41 41
 #include <lib/libkern/libkern.h>
42 42
 
43  
-/* Define the various Interrupt Priority Levels */
44  
-
45  
-/* Hardware Interrupt Priority Levels are not mutually exclusive. */
46  
-
47  
-#define	IPL_NONE	0
48  
-#define	IPL_SOFTCLOCK	1
49  
-#define	IPL_SOFTBIO	1
50  
-#define	IPL_SOFTNET	1
51  
-#define	IPL_SOFTSERIAL	1
52  
-#define	IPL_VM		1
53  
-#define	IPL_SCHED	1
54  
-#define IPL_HIGH	1
55  
-#define NIPL		2
56 43
 
57 44
 #define USB_IRQ 		(0x00008000)
58 45
 #define IR_IRQ 			(0x00004000)
4  sys/arch/milkymist/include/mutex.h
... ...
@@ -1,3 +1,7 @@
1 1
 /*	$NetBSD: mutex.h,v 1.2 2007/02/09 21:55:05 ad Exp $	*/
2 2
 
  3
+#ifndef _MACHINE_MUTEX_H_
  4
+#define _MACHINE_MUTEX_H_
3 5
 #include <lm32/mutex.h>
  6
+
  7
+#endif
5  sys/arch/milkymist/include/pmap.h
... ...
@@ -1,3 +1,8 @@
1 1
 /*	$NetBSD: pmap.h,v 1.45 2007/10/17 19:53:26 garbled Exp $	*/
2 2
 
  3
+#ifndef _MACHINE_PMAP_H_
  4
+#define _MACHINE_PMAP_H_
  5
+
3 6
 #include <lm32/pmap.h>
  7
+
  8
+#endif

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