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Add support for new CSR registers in GDB

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commit 60faaaf832e3a4e1e230d95c0716e64da39d6252 1 parent 15e95e6
@fallen authored
Showing with 12 additions and 3 deletions.
  1. +4 −3 gdb/lm32-tdep.c
  2. +4 −0 include/gdb/sim-lm32.h
  3. +4 −0 sim/lm32/lm32-sim.h
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7 gdb/lm32-tdep.c
@@ -83,7 +83,7 @@ lm32_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
|| (regnum == SIM_LM32_PC_REGNUM);
else if (group == system_reggroup)
return ((regnum >= SIM_LM32_EA_REGNUM) && (regnum <= SIM_LM32_BA_REGNUM))
- || ((regnum >= SIM_LM32_EID_REGNUM) && (regnum <= SIM_LM32_IP_REGNUM));
+ || ((regnum >= SIM_LM32_EID_REGNUM) && (regnum <= SIM_LM32_TLBBADVADDR_REGNUM));
return default_register_reggroup_p (gdbarch, regnum, group);
}
@@ -97,7 +97,8 @@ lm32_register_name (struct gdbarch *gdbarch, int reg_nr)
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
"r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
"r24", "r25", "gp", "fp", "sp", "ra", "ea", "ba",
- "PC", "EID", "EBA", "DEBA", "IE", "IM", "IP"
+ "PC", "EID", "EBA", "DEBA", "IE", "IM", "IP", "PSW",
+ "TLBVADDR", "TLBPADDR", "TLBBADVADDR"
};
if ((reg_nr < 0) || (reg_nr >= ARRAY_SIZE (register_names)))
@@ -119,7 +120,7 @@ lm32_register_type (struct gdbarch *gdbarch, int reg_nr)
static int
lm32_cannot_store_register (struct gdbarch *gdbarch, int regno)
{
- return (regno == SIM_LM32_R0_REGNUM) || (regno == SIM_LM32_EID_REGNUM);
+ return (regno == SIM_LM32_R0_REGNUM) || (regno == SIM_LM32_EID_REGNUM) || (regno == SIM_LM32_TLBBADVADDR_REGNUM);
}
/* Analyze a function's prologue. */
View
4 include/gdb/sim-lm32.h
@@ -66,6 +66,10 @@ enum sim_lm32_regs
SIM_LM32_IE_REGNUM,
SIM_LM32_IM_REGNUM,
SIM_LM32_IP_REGNUM,
+ SIM_LM32_PSW_REGNUM,
+ SIM_LM32_TLBVADDR_REGNUM,
+ SIM_LM32_TLBPADDR_REGNUM,
+ SIM_LM32_TLBBADVADDR_REGNUM,
SIM_LM32_NUM_REGS
};
View
4 sim/lm32/lm32-sim.h
@@ -43,6 +43,10 @@
#define LM32_CSR_WP1 0x19
#define LM32_CSR_WP2 0x1a
#define LM32_CSR_WP3 0x1b
+#define LM32_CSR_PSW 0x1d
+#define LM32_CSR_TLBVADDR 0x1e
+#define LM32_CSR_TLBPADDR 0x1f
+#define LM32_CSR_TLBBADVADDR 0x1f
/* Exception IDs. */
#define LM32_EID_RESET 0
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