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Remove TLBCTRL from LM32-MMU toolchain and add PSW instead

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commit ad74f21f61699aca37b6c94023c972d38c96954a 1 parent 48745c5
Yann Sionneau authored
3  cpu/lm32.cpu
@@ -101,10 +101,11 @@
101 101
                (EBA 7)
102 102
                (DC 8)
103 103
                (DEBA 9)
  104
+	       (PSW 11)
104 105
                (JTX 14) (JRX 15)          
105 106
                (BP0 16) (BP1 17) (BP2 18) (BP3 19)
106 107
                (WP0 24) (WP1 25) (WP2 26) (WP3 27)     
107  
-               (TLBCTRL 28) (TLBVADDR 29) (TLBPADDR 30)
  108
+               (TLBVADDR 29) (TLBPADDR 30)
108 109
 	       (DTLBMA 29) (ITLBMA 30)
109 110
               )
110 111
   )
2  opcodes/lm32-desc.c
@@ -185,6 +185,7 @@ static CGEN_KEYWORD_ENTRY lm32_cgen_opval_h_csr_entries[] =
185 185
   { "EBA", 7, {0, {{{0, 0}}}}, 0, 0 },
186 186
   { "DC", 8, {0, {{{0, 0}}}}, 0, 0 },
187 187
   { "DEBA", 9, {0, {{{0, 0}}}}, 0, 0 },
  188
+  { "PSW", 11, {0, {{{0, 0}}}}, 0, 0 },
188 189
   { "JTX", 14, {0, {{{0, 0}}}}, 0, 0 },
189 190
   { "JRX", 15, {0, {{{0, 0}}}}, 0, 0 },
190 191
   { "BP0", 16, {0, {{{0, 0}}}}, 0, 0 },
@@ -195,7 +196,6 @@ static CGEN_KEYWORD_ENTRY lm32_cgen_opval_h_csr_entries[] =
195 196
   { "WP1", 25, {0, {{{0, 0}}}}, 0, 0 },
196 197
   { "WP2", 26, {0, {{{0, 0}}}}, 0, 0 },
197 198
   { "WP3", 27, {0, {{{0, 0}}}}, 0, 0 },
198  
-  { "TLBCTRL", 28, {0, {{{0, 0}}}}, 0, 0 },
199 199
   { "TLBVADDR", 29, {0, {{{0, 0}}}}, 0, 0 },
200 200
   { "DTLBMA", 29, {0, {{{0, 0}}}}, 0, 0 },
201 201
   { "TLBPADDR", 30, {0, {{{0, 0}}}}, 0, 0 },

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