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Remove TLBCTRL from LM32-MMU toolchain and add PSW instead

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commit ad74f21f61699aca37b6c94023c972d38c96954a 1 parent 48745c5
@fallen authored
Showing with 3 additions and 2 deletions.
  1. +2 −1  cpu/lm32.cpu
  2. +1 −1  opcodes/lm32-desc.c
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3  cpu/lm32.cpu
@@ -101,10 +101,11 @@
(EBA 7)
(DC 8)
(DEBA 9)
+ (PSW 11)
(JTX 14) (JRX 15)
(BP0 16) (BP1 17) (BP2 18) (BP3 19)
(WP0 24) (WP1 25) (WP2 26) (WP3 27)
- (TLBCTRL 28) (TLBVADDR 29) (TLBPADDR 30)
+ (TLBVADDR 29) (TLBPADDR 30)
(DTLBMA 29) (ITLBMA 30)
)
)
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2  opcodes/lm32-desc.c
@@ -185,6 +185,7 @@ static CGEN_KEYWORD_ENTRY lm32_cgen_opval_h_csr_entries[] =
{ "EBA", 7, {0, {{{0, 0}}}}, 0, 0 },
{ "DC", 8, {0, {{{0, 0}}}}, 0, 0 },
{ "DEBA", 9, {0, {{{0, 0}}}}, 0, 0 },
+ { "PSW", 11, {0, {{{0, 0}}}}, 0, 0 },
{ "JTX", 14, {0, {{{0, 0}}}}, 0, 0 },
{ "JRX", 15, {0, {{{0, 0}}}}, 0, 0 },
{ "BP0", 16, {0, {{{0, 0}}}}, 0, 0 },
@@ -195,7 +196,6 @@ static CGEN_KEYWORD_ENTRY lm32_cgen_opval_h_csr_entries[] =
{ "WP1", 25, {0, {{{0, 0}}}}, 0, 0 },
{ "WP2", 26, {0, {{{0, 0}}}}, 0, 0 },
{ "WP3", 27, {0, {{{0, 0}}}}, 0, 0 },
- { "TLBCTRL", 28, {0, {{{0, 0}}}}, 0, 0 },
{ "TLBVADDR", 29, {0, {{{0, 0}}}}, 0, 0 },
{ "DTLBMA", 29, {0, {{{0, 0}}}}, 0, 0 },
{ "TLBPADDR", 30, {0, {{{0, 0}}}}, 0, 0 },
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