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Fix typo

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commit 7e7685402c253450dbda220304ced2c16dbbc3ec 1 parent e472898
Yann Sionneau authored
Showing with 3 additions and 3 deletions.
  1. +1 −1  lm32_cpu.v
  2. +1 −1  lm32_dcache.v
  3. +1 −1  lm32_interrupt.v
2  lm32_cpu.v
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@@ -2196,7 +2196,7 @@ begin
`LM32_CSR_JRX: csr_read_data_x = jrx_csr_read_data;
`endif
`LM32_CSR_CFG2: csr_read_data_x = cfg2;
-`ifdef `LM32_MMU_ENABLED
+`ifdef CFG_MMU_ENABLED
`LM32_CSR_TLB_VADDRESS: csr_read_data_x = load_store_csr_read_data_x;
`LM32_CSR_TLB_PADDRESS: csr_read_data_x = instruction_csr_read_data_x;
`LM32_CSR_PSW: csr_read_data_x = lm32_csr_psw_reg;
2  lm32_dcache.v
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@@ -284,7 +284,7 @@ reg [`LM32_DC_ADDR_OFFSET_RNG] refill_offset; // Which word in cache l
wire last_refill; // Indicates when on last cycle of cache refill
reg [`LM32_DC_TMEM_ADDR_RNG] flush_set; // Which set is currently being flushed
-`ifdef LM32_MMU_ENABLED
+`ifdef CFG_MMU_ENABLED
wire [addr_dtlb_index_width-1:0] dtlb_data_read_address;
wire [addr_dtlb_index_width-1:0] dtlb_data_write_address;
wire dtlb_data_read_port_enable;
2  lm32_interrupt.v
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@@ -267,7 +267,7 @@ begin
begin
// Handle wcsr write
if ((csr == `LM32_CSR_IE)
-`ifdef `LM32_MMU_ENABLED
+`ifdef CFG_MMU_ENABLED
|| (csr == `LM32_CSR_PSW)
`endif
)
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