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Add support for ITLB miss generating page fault

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commit aad21edf52a6fef9106080de0b6b79fbc618309b 1 parent fdfe002
Yann Sionneau authored June 12, 2012
11  lm32_cpu.v
@@ -780,6 +780,7 @@ reg ext_break_r;
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 `ifdef CFG_MMU_ENABLED
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 wire dtlb_miss_exception;
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+wire itlb_miss_exception;
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 `endif
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 /////////////////////////////////////////////////////
@@ -1791,7 +1792,7 @@ assign non_debug_exception_x = (system_call_exception == `TRUE)
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                                )
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 `endif
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 `ifdef CFG_MMU_ENABLED
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-			|| (dtlb_miss_exception == `TRUE)
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+			|| (dtlb_miss_exception == `TRUE || itlb_miss_exception == `TRUE)
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 `endif
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                             ;
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@@ -1817,7 +1818,7 @@ assign exception_x =           (system_call_exception == `TRUE)
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                                )
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 `endif
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 `ifdef CFG_MMU_ENABLED
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-			|| (dtlb_miss_exception == `TRUE)
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+			|| (dtlb_miss_exception == `TRUE || itlb_miss_exception == `TRUE)
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 `endif
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                             ;
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 `endif
@@ -1868,8 +1869,10 @@ begin
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     else
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 `endif
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 `ifdef CFG_MMU_ENABLED
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-	if (dtlb_miss_exception == `TRUE )
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+	if (dtlb_miss_exception == `TRUE)
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 		eid_x = `LM32_EID_DTLB_MISS;
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+	else if (itlb_miss_exception == `TRUE)
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+		eid_x = `LM32_EID_ITLB_MISS;
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 	else
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 `endif
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 		eid_x = `LM32_EID_SCALL;
@@ -2166,7 +2169,7 @@ begin
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 `endif
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     `LM32_CSR_CFG2: csr_read_data_x = cfg2;
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     `LM32_CSR_TLB_VADDRESS: csr_read_data_x = load_store_csr_read_data_x;
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-      
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+    `LM32_CSR_TLB_PADDRESS: csr_read_data_x = instruction_csr_read_data_x;
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     default:        csr_read_data_x = {`LM32_WORD_WIDTH{1'bx}};
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     endcase
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 end
8  lm32_icache.v
@@ -316,7 +316,7 @@ reg itlb_flushing;
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 reg [addr_itlb_index_width-1:0] itlb_flush_set;
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 wire itlb_miss;
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 reg itlb_miss_q = `FALSE;
319  
-reg [`LM32_WORD_RNG] itlb_miss_addr;
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+reg [`LM32_PC_RNG] itlb_miss_addr;
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 wire itlb_data_valid;
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 wire [`LM32_ITLB_LOOKUP_RANGE] itlb_lookup;
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 reg go_to_user_mode;
@@ -673,7 +673,7 @@ assign kernel_mode = kernel_mode_reg;
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 assign switch_to_kernel_mode = (/*(kernel_mode_reg == `LM32_KERNEL_MODE) && */csr_write_enable && (csr == `LM32_CSR_TLB_CTRL) && csr_write_data[5:0] == {`LM32_TLB_CTRL_SWITCH_TO_KERNEL_MODE, 1'b0});
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 assign switch_to_user_mode = (/*(kernel_mode_reg == `LM32_KERNEL_MODE) && */csr_write_enable && (csr == `LM32_CSR_TLB_CTRL) && csr_write_data[5:0] == {`LM32_TLB_CTRL_SWITCH_TO_USER_MODE, 1'b0});
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-assign csr_read_data = itlb_miss_addr;
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+assign csr_read_data = {itlb_miss_addr, 2'b0};
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 assign itlb_miss = (kernel_mode_reg == `LM32_USER_MODE) && (read_enable_f) && ~(itlb_data_valid);
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 assign itlb_miss_int = (itlb_miss || itlb_miss_q);
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 assign itlb_read_tag = itlb_read_data[`LM32_ITLB_TAG_RANGE];
@@ -765,7 +765,7 @@ begin
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 		itlb_flush_set <= {addr_itlb_index_width{1'b1}};
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 		itlb_state <= `LM32_TLB_STATE_FLUSH;
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 		itlb_updating <= 0;
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-		itlb_miss_addr <= `LM32_WORD_WIDTH'd0;
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+		itlb_miss_addr <= {`LM32_PC_WIDTH{1'b0}};
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 	end
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 	else
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 	begin
@@ -778,7 +778,7 @@ begin
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 			if (itlb_miss == `TRUE)
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 			begin
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 				itlb_miss_addr <= address_f;
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-				$display("WARNING : ITLB MISS on addr 0x%08X at time %t", address_f, $time);
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+				$display("WARNING : ITLB MISS on addr 0x%08X at time %t", address_f * 4, $time);
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 			end
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 			if (csr_write_enable && ~csr_write_data[0])
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 			begin
1  lm32_include.v
@@ -318,6 +318,7 @@
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 `define LM32_EID_INTERRUPT              `LM32_EID_WIDTH'h6
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 `define LM32_EID_SCALL                  `LM32_EID_WIDTH'h7
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 `define LM32_EID_DTLB_MISS              `LM32_EID_WIDTH'h8
  321
+`define LM32_EID_ITLB_MISS              `LM32_EID_WIDTH'h9
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 // Pipeline result selection mux controls
323 324
 

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