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Fix compilation with MMU disabled

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commit e47289845eaf5e86ba92c6c98d40600ae5844de6 1 parent 975b9ff
Yann Sionneau authored October 24, 2012
2  lm32_cpu.v
@@ -2196,9 +2196,11 @@ begin
2196 2196
     `LM32_CSR_JRX:  csr_read_data_x = jrx_csr_read_data;
2197 2197
 `endif
2198 2198
     `LM32_CSR_CFG2: csr_read_data_x = cfg2;
  2199
+`ifdef `LM32_MMU_ENABLED
2199 2200
     `LM32_CSR_TLB_VADDRESS: csr_read_data_x = load_store_csr_read_data_x;
2200 2201
     `LM32_CSR_TLB_PADDRESS: csr_read_data_x = instruction_csr_read_data_x;
2201 2202
     `LM32_CSR_PSW:	csr_read_data_x = lm32_csr_psw_reg;
  2203
+`endif
2202 2204
     default:        csr_read_data_x = {`LM32_WORD_WIDTH{1'bx}};
2203 2205
     endcase
2204 2206
 end
22  lm32_dcache.v
@@ -284,6 +284,7 @@ reg [`LM32_DC_ADDR_OFFSET_RNG] refill_offset;           // Which word in cache l
284 284
 wire last_refill;                                       // Indicates when on last cycle of cache refill
285 285
 reg [`LM32_DC_TMEM_ADDR_RNG] flush_set;                 // Which set is currently being flushed
286 286
 
  287
+`ifdef LM32_MMU_ENABLED
287 288
 wire [addr_dtlb_index_width-1:0] dtlb_data_read_address;
288 289
 wire [addr_dtlb_index_width-1:0] dtlb_data_write_address;
289 290
 wire dtlb_data_read_port_enable;
@@ -310,10 +311,11 @@ reg dtlb_miss_q = `FALSE;
310 311
 reg [`LM32_WORD_RNG] dtlb_miss_addr;
311 312
 wire dtlb_data_valid;
312 313
 wire [`LM32_DTLB_LOOKUP_RANGE] dtlb_lookup;
  314
+assign kernel_mode = kernel_mode_reg;
  315
+`endif
313 316
 
314 317
 genvar i, j;
315 318
 
316  
-assign kernel_mode = kernel_mode_reg;
317 319
 
318 320
 /////////////////////////////////////////////////////
319 321
 // Functions
@@ -553,12 +555,17 @@ assign flushing = state[0];
553 555
 assign check = state[1];
554 556
 assign refill = state[2];
555 557
 
556  
-assign miss = (~(|way_match)) && (load_q_m == `TRUE) && (stall_m == `FALSE) && (~dtlb_miss);
557  
-assign stall_request = (check == `FALSE) || (dtlb_state == `LM32_TLB_STATE_FLUSH 
  558
+assign miss = (~(|way_match)) && (load_q_m == `TRUE) && (stall_m == `FALSE)
  559
+`ifdef CFG_MMU_ENABLED
  560
+ 		&& (~dtlb_miss)
  561
+`endif
  562
+		;
  563
+assign stall_request = (check == `FALSE) 
558 564
 `ifdef CFG_MMU_ENABLED
559  
-			&& (dtlb_enabled == `TRUE)
  565
+			|| (dtlb_state == `LM32_TLB_STATE_FLUSH 
  566
+			&& (dtlb_enabled == `TRUE))
560 567
 `endif
561  
-			);
  568
+			;
562 569
 
563 570
 /////////////////////////////////////////////////////
564 571
 // Sequential logic
@@ -807,7 +814,10 @@ begin
807 814
 						dtlb_updating <= 0;
808 815
 						dtlb_state <= `LM32_TLB_STATE_CHECK;
809 816
 					end
810  
-
  817
+					default:
  818
+					begin
  819
+						$display("[ %t ] DTLB TLBVADDRESS stored 0x%08X", $time, csr_write_data);
  820
+					end
811 821
 					endcase
812 822
 				end
813 823
 				else
2  lm32_icache.v
@@ -885,7 +885,7 @@ begin
885 885
 					`LM32_TLB_CTRL_INVALIDATE_ENTRY:
886 886
 					begin
887 887
 //`ifdef CFG_VERBOSE_DISPLAY_ENABLED
888  
-						$display("it's an INVALIDATE ENTRY at %t", $time);
  888
+						$display("[ %t ] ITLB TLBVADDRESS INVALIDATE ENTRY 0x%08X command [vaddr_reg == 0x%08X]", $time, csr_write_data, itlb_update_vaddr_csr_reg);
889 889
 //`endif
890 890
 						itlb_flushing <= 1;
891 891
 //						itlb_flush_set <= itlb_update_vaddr_csr_reg[`LM32_ITLB_IDX_RNG];
6  lm32_interrupt.v
@@ -266,7 +266,11 @@ begin
266 266
             else if (csr_write_enable == `TRUE)
267 267
             begin
268 268
                 // Handle wcsr write
269  
-                if ((csr == `LM32_CSR_IE) || (csr == `LM32_CSR_PSW))
  269
+                if ((csr == `LM32_CSR_IE)
  270
+`ifdef `LM32_MMU_ENABLED
  271
+		 || (csr == `LM32_CSR_PSW)
  272
+`endif
  273
+		)
270 274
                 begin
271 275
                     ie <= csr_write_data[0];
272 276
                     eie <= csr_write_data[1];
2  lm32_load_store_unit.v
@@ -172,9 +172,9 @@ input kill_x;                                           // Kill instruction in X
172 172
 input kill_m;                                           // Kill instruction in M stage
173 173
 input exception_m;                                      // An exception occured in the M stage
174 174
 input exception_x;                                      // An exception occured in the X stage
175  
-input eret_q_x;
176 175
 
177 176
 `ifdef CFG_MMU_ENABLED
  177
+input eret_q_x;
178 178
 input [`LM32_CSR_RNG] csr;				// CSR read/write index
179 179
 input [`LM32_WORD_RNG] csr_write_data;			// Data to write to specified CSR
180 180
 input csr_write_enable;					// CSR write enable

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