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base fork: fallen/milkymist-mmu-simulation
base: 3f0985978557
...
head fork: fallen/milkymist-mmu-simulation
compare: fdfe002f1ece
  • 2 commits
  • 5 files changed
  • 0 commit comments
  • 1 contributor
View
18 lm32_cpu.v
@@ -778,6 +778,10 @@ reg data_bus_error_seen; // Indicates if a data bus error
reg ext_break_r;
`endif
+`ifdef CFG_MMU_ENABLED
+wire dtlb_miss_exception;
+`endif
+
/////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////
@@ -820,7 +824,9 @@ lm32_instruction_unit #(
.branch_target_x (branch_target_x),
`endif
.exception_m (exception_m),
+`ifdef CFG_MMU_ENABLED
.exception_x (exception_x),
+`endif
.branch_taken_m (branch_taken_m),
.branch_mispredict_taken_m (branch_mispredict_taken_m),
.branch_target_m (branch_target_m),
@@ -837,10 +843,12 @@ lm32_instruction_unit #(
.dcache_refill_request (dcache_refill_request),
.dcache_refilling (dcache_refilling),
`endif
+`ifdef CFG_MMU_ENABLED
.csr (csr_x),
.csr_write_data (operand_1_x),
.csr_write_enable (csr_write_enable_q_x),
.eret_q_x (eret_q_x),
+`endif
`ifdef CFG_IWB_ENABLED
// From Wishbone
.i_dat_i (I_DAT_I),
@@ -869,8 +877,10 @@ lm32_instruction_unit #(
`ifdef CFG_IROM_ENABLED
.irom_data_m (irom_data_m),
`endif
+`ifdef CFG_MMU_ENABLED
.itlb_miss (itlb_miss_exception),
.csr_read_data (instruction_csr_read_data_x),
+`endif
`ifdef CFG_IWB_ENABLED
// To Wishbone
.i_dat_o (I_DAT_O),
@@ -975,8 +985,6 @@ lm32_decoder decoder (
.csr_write_enable (csr_write_enable_d)
);
-wire dtlb_miss_exception;
-
// Load/store unit
lm32_load_store_unit #(
.associativity (dcache_associativity),
@@ -1014,10 +1022,12 @@ lm32_load_store_unit #(
`ifdef CFG_IROM_ENABLED
.irom_data_m (irom_data_m),
`endif
+`ifdef CFG_MMU_ENABLED
.csr (csr_x),
.csr_write_data (operand_1_x),
.csr_write_enable (csr_write_enable_q_x),
.eret_q_x (eret_q_x),
+`endif
// From Wishbone
.d_dat_i (D_DAT_I),
.d_ack_i (D_ACK_I),
@@ -1039,8 +1049,10 @@ lm32_load_store_unit #(
`endif
.load_data_w (load_data_w),
.stall_wb_load (stall_wb_load),
+`ifdef CFG_MMU_ENABLED
.dtlb_miss (dtlb_miss_exception),
.csr_read_data (load_store_csr_read_data_x),
+`endif
// To Wishbone
.d_dat_o (D_DAT_O),
.d_adr_o (D_ADR_O),
@@ -1855,9 +1867,11 @@ begin
eid_x = `LM32_EID_INTERRUPT;
else
`endif
+`ifdef CFG_MMU_ENABLED
if (dtlb_miss_exception == `TRUE )
eid_x = `LM32_EID_DTLB_MISS;
else
+`endif
eid_x = `LM32_EID_SCALL;
end
View
351 lm32_dcache.v
@@ -2,7 +2,7 @@
// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// ------------------------------------------------------------------
// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
-// ALL RIGHTS RESERVED
+// ALL RIGHTS RESERVED
// ------------------------------------------------------------------
//
// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
@@ -11,7 +11,7 @@
//
// Lattice Semiconductor grants permission to use this code
// pursuant to the terms of the Lattice Semiconductor Corporation
-// Open Source License Agreement.
+// Open Source License Agreement.
//
// Disclaimer:
//
@@ -48,14 +48,11 @@
// : cache memory. Additional parameters must be defined when
// : invoking lm32_ram.v
// =============================================================================
-
+
`include "lm32_include.v"
`ifdef CFG_DCACHE_ENABLED
-`define LM32_KERNEL_MODE 1
-`define LM32_USER_MODE 0
-
`define LM32_DC_ADDR_OFFSET_RNG addr_offset_msb:addr_offset_lsb
`define LM32_DC_ADDR_SET_RNG addr_set_msb:addr_set_lsb
`define LM32_DC_ADDR_TAG_RNG addr_tag_msb:addr_tag_lsb
@@ -76,6 +73,7 @@
`define LM32_DC_STATE_CHECK 3'b010
`define LM32_DC_STATE_REFILL 3'b100
+`ifdef CFG_MMU_ENABLED
`define LM32_DTLB_CTRL_FLUSH 5'h1
`define LM32_DTLB_CTRL_UPDATE 5'h2
`define LM32_TLB_CTRL_SWITCH_TO_KERNEL_MODE 5'h4
@@ -85,14 +83,18 @@
`define LM32_TLB_STATE_CHECK 2'b01
`define LM32_TLB_STATE_FLUSH 2'b10
+`define LM32_KERNEL_MODE 1
+`define LM32_USER_MODE 0
+`endif
+
/////////////////////////////////////////////////////
// Module interface
/////////////////////////////////////////////////////
-module lm32_dcache (
+module lm32_dcache (
// ----- Inputs -----
clk_i,
- rst_i,
+ rst_i,
stall_a,
stall_x,
stall_m,
@@ -105,24 +107,27 @@ module lm32_dcache (
refill_ready,
refill_data,
dflush,
+`ifdef CFG_MMU_ENABLED
csr,
csr_write_data,
csr_write_enable,
exception_x,
eret_q_x,
exception_m,
+`endif
// ----- Outputs -----
stall_request,
restart_request,
refill_request,
refill_address,
refilling,
- load_data,
- // To pipeline
+`ifdef CFG_MMU_ENABLED
dtlb_miss_int,
kernel_mode,
pa,
- csr_read_data
+ csr_read_data,
+`endif
+ load_data
);
/////////////////////////////////////////////////////
@@ -135,6 +140,8 @@ parameter bytes_per_line = 16; // Number of bytes per c
parameter base_address = 0; // Base address of cachable memory
parameter limit = 0; // Limit (highest address) of cachable memory
+`ifdef CFG_MMU_ENABLED
+
parameter dtlb_sets = 1024; // Number of lines of DTLB
parameter page_size = 4096; // System page size
@@ -167,6 +174,7 @@ localparam addr_dtlb_tag_msb = addr_dtlb_tag_lsb + addr_dtlb_tag_width - 1;
`define LM32_DTLB_ADDR_TAG_RNG addr_dtlb_tag_msb:addr_dtlb_tag_lsb
`define LM32_DTLB_VALID_BIT vpfn_width+addr_dtlb_tag_width
+`endif
localparam addr_offset_width = clogb2(bytes_per_line)-1-2;
localparam addr_set_width = clogb2(sets)-1;
@@ -201,6 +209,7 @@ input [`LM32_WORD_RNG] refill_data; // Refill data
input dflush; // Indicates cache should be flushed
+`ifdef CFG_MMU_ENABLED
input [`LM32_CSR_RNG] csr; // CSR read/write index
input [`LM32_WORD_RNG] csr_write_data; // Data to write to specified CSR
@@ -209,18 +218,17 @@ input exception_x; // An exception occured in the X stage
input exception_m;
input eret_q_x;
+`endif
+
/////////////////////////////////////////////////////
// Outputs
/////////////////////////////////////////////////////
-output csr_read_data;
-wire [`LM32_WORD_RNG] csr_read_data;
-
output stall_request; // Request pipeline be stalled because cache is busy
wire stall_request;
output restart_request; // Request to restart instruction that caused the cache miss
reg restart_request;
-output refill_request; // Request a refill
+output refill_request; // Request a refill
reg refill_request;
output [`LM32_WORD_RNG] refill_address; // Address to refill from
reg [`LM32_WORD_RNG] refill_address;
@@ -229,13 +237,21 @@ reg refilling;
output [`LM32_WORD_RNG] load_data; // Data read from cache
wire [`LM32_WORD_RNG] load_data;
+`ifdef CFG_MMU_ENABLED
+
output kernel_mode;
wire kernel_mode;
-
+output csr_read_data;
+wire [`LM32_WORD_RNG] csr_read_data;
output dtlb_miss_int;
+wire dtlb_miss_int;
+output [`LM32_WORD_RNG] pa;
+wire [`LM32_WORD_RNG] pa;
+
+`endif
/////////////////////////////////////////////////////
-// Internal nets and registers
+// Internal nets and registers
/////////////////////////////////////////////////////
wire read_port_enable; // Cache memory read port clock enable
@@ -252,7 +268,7 @@ wire [`LM32_DC_TMEM_ADDR_RNG] tmem_read_address; // Tag memory read addre
wire [`LM32_DC_TMEM_ADDR_RNG] tmem_write_address; // Tag memory write address
wire [`LM32_DC_DMEM_ADDR_RNG] dmem_read_address; // Data memory read address
wire [`LM32_DC_DMEM_ADDR_RNG] dmem_write_address; // Data memory write address
-wire [`LM32_DC_TAGS_RNG] tmem_write_data; // Tag memory write data
+wire [`LM32_DC_TAGS_RNG] tmem_write_data; // Tag memory write data
reg [`LM32_WORD_RNG] dmem_write_data; // Data memory write data
reg [`LM32_DC_STATE_RNG] state; // Current state of FSM
@@ -272,13 +288,8 @@ wire dtlb_data_read_port_enable;
wire dtlb_write_port_enable;
wire [vpfn_width + addr_dtlb_tag_width + 1 - 1:0] dtlb_write_data; // +1 is for valid_bit
wire [vpfn_width + addr_dtlb_tag_width + 1 - 1:0] dtlb_read_data; // +1 is for valid_bit
-
wire [`LM32_WORD_RNG] physical_address;
-wire [`LM32_WORD_RNG] pa;
-output [`LM32_WORD_RNG] pa;
-reg [`LM32_WORD_RNG] latest_store_tlb_lookup;
-
assign pa = physical_address;
reg kernel_mode_reg = `LM32_KERNEL_MODE;
@@ -294,7 +305,6 @@ reg dtlb_flushing;
reg [addr_dtlb_index_width-1:0] dtlb_flush_set;
wire dtlb_miss;
reg dtlb_miss_q = `FALSE;
-wire dtlb_miss_int;
reg [`LM32_WORD_RNG] dtlb_miss_addr;
wire dtlb_data_valid;
wire [`LM32_DTLB_LOOKUP_RANGE] dtlb_lookup;
@@ -313,15 +323,15 @@ assign kernel_mode = kernel_mode_reg;
// Instantiations
/////////////////////////////////////////////////////
-
+`ifdef CFG_MMU_ENABLED
// DTLB instantiation
-lm32_ram
+lm32_ram
#(
// ----- Parameters -------
.data_width (vpfn_width + addr_dtlb_tag_width + 1),
.address_width (addr_dtlb_index_width)
// Modified for Milkymist: removed non-portable RAM parameters
- ) dtlb_data_ram
+ ) dtlb_data_ram
(
// ----- Inputs -------
.read_clk (clk_i),
@@ -332,34 +342,25 @@ lm32_ram
.write_address (dtlb_data_write_address),
.enable_write (`TRUE),
.write_enable (dtlb_write_port_enable),
- .write_data (dtlb_write_data),
+ .write_data (dtlb_write_data),
// ----- Outputs -------
.read_data (dtlb_read_data)
);
-
-`ifdef CFG_VERBOSE_DISPLAY_ENABLED
-always @(posedge clk_i)
-begin
- if (dtlb_write_port_enable)
- begin
- $display("[DTLB data : %d] Writing 0x%08X to 0x%08X", $time, dtlb_write_data, dtlb_data_write_address);
- end
-end
`endif
generate
- for (i = 0; i < associativity; i = i + 1)
+ for (i = 0; i < associativity; i = i + 1)
begin : memories
// Way data
if (`LM32_DC_DMEM_ADDR_WIDTH < 11)
begin : data_memories
- lm32_ram
+ lm32_ram
#(
// ----- Parameters -------
.data_width (32),
.address_width (`LM32_DC_DMEM_ADDR_WIDTH)
// Modified for Milkymist: removed non-portable RAM parameters
- ) way_0_data_ram
+ ) way_0_data_ram
(
// ----- Inputs -------
.read_clk (clk_i),
@@ -370,22 +371,22 @@ end
.write_address (dmem_write_address),
.enable_write (write_port_enable),
.write_enable (way_dmem_we[i]),
- .write_data (dmem_write_data),
+ .write_data (dmem_write_data),
// ----- Outputs -------
.read_data (way_data[i])
- );
+ );
end
else
begin
- for (j = 0; j < 4; j = j + 1)
+ for (j = 0; j < 4; j = j + 1)
begin : byte_memories
- lm32_ram
+ lm32_ram
#(
// ----- Parameters -------
.data_width (8),
.address_width (`LM32_DC_DMEM_ADDR_WIDTH)
// Modified for Milkymist: removed non-portable RAM parameters
- ) way_0_data_ram
+ ) way_0_data_ram
(
// ----- Inputs -------
.read_clk (clk_i),
@@ -396,21 +397,21 @@ end
.write_address (dmem_write_address),
.enable_write (write_port_enable),
.write_enable (way_dmem_we[i] & (store_byte_select[j] | refill)),
- .write_data (dmem_write_data[(j+1)*8-1:j*8]),
+ .write_data (dmem_write_data[(j+1)*8-1:j*8]),
// ----- Outputs -------
.read_data (way_data[i][(j+1)*8-1:j*8])
);
end
end
-
+
// Way tags
- lm32_ram
+ lm32_ram
#(
// ----- Parameters -------
.data_width (`LM32_DC_TAGS_WIDTH),
.address_width (`LM32_DC_TMEM_ADDR_WIDTH)
// Modified for Milkymist: removed non-portable RAM parameters
- ) way_0_tag_ram
+ ) way_0_tag_ram
(
// ----- Inputs -------
.read_clk (clk_i),
@@ -426,37 +427,13 @@ end
.read_data ({way_tag[i], way_valid[i]})
);
end
-
+
endgenerate
/////////////////////////////////////////////////////
// Combinational logic
/////////////////////////////////////////////////////
-// CSR Write
-always @(posedge clk_i `CFG_RESET_SENSITIVITY)
-begin
- if (rst_i == `TRUE)
- begin
- dtlb_ctrl_csr_reg <= `LM32_WORD_WIDTH'd0;
- dtlb_update_vaddr_csr_reg <= `LM32_WORD_WIDTH'd0;
- dtlb_update_paddr_csr_reg <= `LM32_WORD_WIDTH'd0;
- end
- else
- begin
- if (csr_write_enable)
- begin
- case (csr)
- `LM32_CSR_TLB_CTRL: if (csr_write_data[0]) dtlb_ctrl_csr_reg[31:1] <= csr_write_data[31:1];
- `LM32_CSR_TLB_VADDRESS: if (csr_write_data[0]) dtlb_update_vaddr_csr_reg[31:1] <= csr_write_data[31:1];
- `LM32_CSR_TLB_PADDRESS: if (csr_write_data[0]) dtlb_update_paddr_csr_reg[31:1] <= csr_write_data[31:1];
- endcase
- end
- dtlb_ctrl_csr_reg[0] <= 0;
- dtlb_update_vaddr_csr_reg[0] <= 0;
- dtlb_update_paddr_csr_reg[0] <= 0;
- end
-end
@@ -465,25 +442,24 @@ generate
for (i = 0; i < associativity; i = i + 1)
begin : match
-assign dtlb_read_tag = dtlb_read_data[`LM32_DTLB_TAG_RANGE];
-assign dtlb_data_valid = dtlb_read_data[`LM32_DTLB_VALID_BIT];
-assign dtlb_lookup = dtlb_read_data[`LM32_DTLB_LOOKUP_RANGE];
-
-assign way_match[i] = (kernel_mode_reg == `LM32_KERNEL_MODE) ?
- ({way_tag[i], way_valid[i]} == {address_m[`LM32_DC_ADDR_TAG_RNG], `TRUE})
- : ({way_tag[i], way_valid[i]} == {dtlb_lookup, `TRUE});
+assign way_match[i] =
+`ifdef CFG_MMU_ENABLED
+ (kernel_mode_reg == `LM32_USER_MODE) ?
+ ({way_tag[i], way_valid[i]} == {dtlb_lookup, `TRUE}) :
+`endif
+ ({way_tag[i], way_valid[i]} == {address_m[`LM32_DC_ADDR_TAG_RNG], `TRUE});
end
endgenerate
-// Select data from way that matched the address being read
+// Select data from way that matched the address being read
generate
- if (associativity == 1)
+ if (associativity == 1)
begin : data_1
assign load_data = way_data[0];
end
else if (associativity == 2)
begin : data_2
-assign load_data = way_match[0] ? way_data[0] : way_data[1];
+assign load_data = way_match[0] ? way_data[0] : way_data[1];
end
endgenerate
@@ -518,45 +494,26 @@ end
endgenerate
// Compute address to use to index into the data memories
-generate
+generate
if (bytes_per_line > 4)
-assign dmem_write_address = (refill == `TRUE)
+assign dmem_write_address = (refill == `TRUE)
? {refill_address[`LM32_DC_ADDR_SET_RNG], refill_offset}
: address_m[`LM32_DC_ADDR_IDX_RNG];
else
-assign dmem_write_address = (refill == `TRUE)
+assign dmem_write_address = (refill == `TRUE)
? refill_address[`LM32_DC_ADDR_SET_RNG]
: address_m[`LM32_DC_ADDR_IDX_RNG];
endgenerate
assign dmem_read_address = address_x[`LM32_DC_ADDR_IDX_RNG];
-// Compute address to use to index into the tag memories
+// Compute address to use to index into the tag memories
assign tmem_write_address = (flushing == `TRUE)
? flush_set
: refill_address[`LM32_DC_ADDR_SET_RNG];
assign tmem_read_address = address_x[`LM32_DC_ADDR_SET_RNG];
-// Compute address to use to index into the DTLB data memory
-
-assign dtlb_data_read_address = address_x[`LM32_DTLB_IDX_RNG];
-assign dtlb_tag_read_address = address_x[`LM32_DTLB_IDX_RNG];
-
-// tlb_update_address will receive data from a CSR register
-assign dtlb_data_write_address = dtlb_update_vaddr_csr_reg[`LM32_DTLB_IDX_RNG];
-
-assign dtlb_data_read_port_enable = (stall_x == `FALSE) || !stall_m;
-assign dtlb_write_port_enable = dtlb_updating || dtlb_flushing;
-
-assign physical_address = (kernel_mode_reg == `LM32_KERNEL_MODE)
- ? address_m
- : {dtlb_lookup, address_m[`LM32_PAGE_OFFSET_RNG]};
-
-assign dtlb_write_data = (dtlb_flushing == `TRUE)
- ? {`FALSE, {addr_dtlb_tag_width{1'b0}}, {vpfn_width{1'b0}}}
- : {`TRUE, {dtlb_update_vaddr_csr_reg[`LM32_DTLB_ADDR_TAG_RNG]}, dtlb_update_paddr_csr_reg[`LM32_DTLB_ADDRESS_PFN_RNG]};
-
// Compute signal to indicate when we are on the last refill accesses
-generate
- if (bytes_per_line > 4)
+generate
+ if (bytes_per_line > 4)
assign last_refill = refill_offset == {addr_offset_width{1'b1}};
else
assign last_refill = `TRUE;
@@ -571,12 +528,12 @@ assign valid_store = (store_q_m == `TRUE) && (check == `TRUE);
// Compute data and tag memory write enables
generate
- if (associativity == 1)
- begin : we_1
+ if (associativity == 1)
+ begin : we_1
assign way_dmem_we[0] = (refill_ready == `TRUE) || ((valid_store == `TRUE) && (way_match[0] == `TRUE));
assign way_tmem_we[0] = (refill_ready == `TRUE) || (flushing == `TRUE);
- end
- else
+ end
+ else
begin : we_2
assign way_dmem_we[0] = ((refill_ready == `TRUE) && (refill_way_select[0] == `TRUE)) || ((valid_store == `TRUE) && (way_match[0] == `TRUE));
assign way_dmem_we[1] = ((refill_ready == `TRUE) && (refill_way_select[1] == `TRUE)) || ((valid_store == `TRUE) && (way_match[1] == `TRUE));
@@ -595,35 +552,39 @@ assign check = state[1];
assign refill = state[2];
assign miss = (~(|way_match)) && (load_q_m == `TRUE) && (stall_m == `FALSE) && (~dtlb_miss);
-assign stall_request = (check == `FALSE) || (dtlb_state == `LM32_TLB_STATE_FLUSH && kernel_mode_reg != `LM32_KERNEL_MODE);
-
+assign stall_request = (check == `FALSE) || (dtlb_state == `LM32_TLB_STATE_FLUSH
+`ifdef CFG_MMU_ENABLED
+ && kernel_mode_reg != `LM32_KERNEL_MODE
+`endif
+ );
+
/////////////////////////////////////////////////////
// Sequential logic
/////////////////////////////////////////////////////
// Record way selected for replacement on a cache miss
generate
- if (associativity >= 2)
- begin : way_select
+ if (associativity >= 2)
+ begin : way_select
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
refill_way_select <= {{associativity-1{1'b0}}, 1'b1};
else
- begin
+ begin
if (refill_request == `TRUE)
refill_way_select <= {refill_way_select[0], refill_way_select[1]};
end
end
- end
-endgenerate
+ end
+endgenerate
// Record whether we are currently refilling
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
refilling <= `FALSE;
- else
+ else
refilling <= refill;
end
@@ -638,18 +599,18 @@ begin
refill_address <= {`LM32_WORD_WIDTH{1'b0}};
restart_request <= `FALSE;
end
- else
+ else
begin
case (state)
- // Flush the cache
+ // Flush the cache
`LM32_DC_STATE_FLUSH:
begin
if (flush_set == {`LM32_DC_TMEM_ADDR_WIDTH{1'b0}})
state <= `LM32_DC_STATE_CHECK;
flush_set <= flush_set - 1'b1;
end
-
+
// Check for cache misses
`LM32_DC_STATE_CHECK:
begin
@@ -658,7 +619,11 @@ begin
if (miss == `TRUE)
begin
refill_request <= `TRUE;
+`ifdef CFG_MMU_ENABLED
refill_address <= physical_address;
+`else
+ refill_address <= address_m;
+`endif
state <= `LM32_DC_STATE_REFILL;
end
else if (dflush == `TRUE)
@@ -678,28 +643,103 @@ begin
end
end
end
-
- endcase
+
+ endcase
+ end
+end
+
+
+generate
+ if (bytes_per_line > 4)
+ begin
+// Refill offset
+always @(posedge clk_i `CFG_RESET_SENSITIVITY)
+begin
+ if (rst_i == `TRUE)
+ refill_offset <= {addr_offset_width{1'b0}};
+ else
+ begin
+ case (state)
+
+ // Check for cache misses
+ `LM32_DC_STATE_CHECK:
+ begin
+ if (miss == `TRUE)
+ refill_offset <= {addr_offset_width{1'b0}};
+ end
+
+ // Refill a cache line
+ `LM32_DC_STATE_REFILL:
+ begin
+ if (refill_ready == `TRUE)
+ refill_offset <= refill_offset + 1'b1;
+ end
+
+ endcase
end
end
+ end
+endgenerate
+
+`endif
+
+`ifdef CFG_MMU_ENABLED
+// Beginning of MMU specific code
+
+// Compute address to use to index into the DTLB data memory
+
+assign dtlb_data_read_address = address_x[`LM32_DTLB_IDX_RNG];
+assign dtlb_tag_read_address = address_x[`LM32_DTLB_IDX_RNG];
+
+// tlb_update_address will receive data from a CSR register
+assign dtlb_data_write_address = dtlb_update_vaddr_csr_reg[`LM32_DTLB_IDX_RNG];
+
+assign dtlb_data_read_port_enable = (stall_x == `FALSE) || !stall_m;
+assign dtlb_write_port_enable = dtlb_updating || dtlb_flushing;
+assign physical_address = (kernel_mode_reg == `LM32_KERNEL_MODE)
+ ? address_m
+ : {dtlb_lookup, address_m[`LM32_PAGE_OFFSET_RNG]};
+
+assign dtlb_write_data = (dtlb_flushing == `TRUE)
+ ? {`FALSE, {addr_dtlb_tag_width{1'b0}}, {vpfn_width{1'b0}}}
+ : {`TRUE, {dtlb_update_vaddr_csr_reg[`LM32_DTLB_ADDR_TAG_RNG]}, dtlb_update_paddr_csr_reg[`LM32_DTLB_ADDRESS_PFN_RNG]};
+
+assign dtlb_read_tag = dtlb_read_data[`LM32_DTLB_TAG_RANGE];
+assign dtlb_data_valid = dtlb_read_data[`LM32_DTLB_VALID_BIT];
+assign dtlb_lookup = dtlb_read_data[`LM32_DTLB_LOOKUP_RANGE];
+assign csr_read_data = dtlb_miss_addr;
+assign dtlb_miss = (kernel_mode_reg == `LM32_USER_MODE) && (load_q_m || store_q_m) && ~(dtlb_data_valid);
+assign dtlb_miss_int = (dtlb_miss || dtlb_miss_q);
+
+assign switch_to_kernel_mode = (/*(kernel_mode_reg == `LM32_KERNEL_MODE) && */csr_write_enable && (csr == `LM32_CSR_TLB_CTRL) && csr_write_data[5:0] == {`LM32_TLB_CTRL_SWITCH_TO_KERNEL_MODE, 1'b1});
+assign switch_to_user_mode = (/*(kernel_mode_reg == `LM32_KERNEL_MODE) && */csr_write_enable && (csr == `LM32_CSR_TLB_CTRL) && csr_write_data[5:0] == {`LM32_TLB_CTRL_SWITCH_TO_USER_MODE, 1'b1});
+
+// CSR Write
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
- latest_store_tlb_lookup <= `LM32_WORD_WIDTH'd0;
+ begin
+ dtlb_ctrl_csr_reg <= `LM32_WORD_WIDTH'd0;
+ dtlb_update_vaddr_csr_reg <= `LM32_WORD_WIDTH'd0;
+ dtlb_update_paddr_csr_reg <= `LM32_WORD_WIDTH'd0;
+ end
else
begin
- if (write_port_enable && (|way_dmem_we))
+ if (csr_write_enable)
begin
- latest_store_tlb_lookup <= {dtlb_lookup, address_m[`LM32_PAGE_OFFSET_RNG]};
+ case (csr)
+ `LM32_CSR_TLB_CTRL: if (csr_write_data[0]) dtlb_ctrl_csr_reg[31:1] <= csr_write_data[31:1];
+ `LM32_CSR_TLB_VADDRESS: if (csr_write_data[0]) dtlb_update_vaddr_csr_reg[31:1] <= csr_write_data[31:1];
+ `LM32_CSR_TLB_PADDRESS: if (csr_write_data[0]) dtlb_update_paddr_csr_reg[31:1] <= csr_write_data[31:1];
+ endcase
end
+ dtlb_ctrl_csr_reg[0] <= 0;
+ dtlb_update_vaddr_csr_reg[0] <= 0;
+ dtlb_update_paddr_csr_reg[0] <= 0;
end
end
-assign csr_read_data = dtlb_miss_addr;
-
-assign dtlb_miss = (kernel_mode_reg == `LM32_USER_MODE) && (load_q_m || store_q_m) && ~(dtlb_data_valid);
-
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
@@ -713,8 +753,6 @@ begin
end
end
-assign dtlb_miss_int = (dtlb_miss || dtlb_miss_q);
-
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
@@ -782,10 +820,6 @@ begin
end
end
-assign switch_to_kernel_mode = (/*(kernel_mode_reg == `LM32_KERNEL_MODE) && */csr_write_enable && (csr == `LM32_CSR_TLB_CTRL) && csr_write_data[5:0] == {`LM32_TLB_CTRL_SWITCH_TO_KERNEL_MODE, 1'b1});
-assign switch_to_user_mode = (/*(kernel_mode_reg == `LM32_KERNEL_MODE) && */csr_write_enable && (csr == `LM32_CSR_TLB_CTRL) && csr_write_data[5:0] == {`LM32_TLB_CTRL_SWITCH_TO_USER_MODE, 1'b1});
-
-
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
@@ -799,39 +833,16 @@ begin
end
end
-generate
- if (bytes_per_line > 4)
- begin
-// Refill offset
-always @(posedge clk_i `CFG_RESET_SENSITIVITY)
+`ifdef CFG_VERBOSE_DISPLAY_ENABLED
+always @(posedge clk_i)
begin
- if (rst_i == `TRUE)
- refill_offset <= {addr_offset_width{1'b0}};
- else
- begin
- case (state)
-
- // Check for cache misses
- `LM32_DC_STATE_CHECK:
- begin
- if (miss == `TRUE)
- refill_offset <= {addr_offset_width{1'b0}};
- end
-
- // Refill a cache line
- `LM32_DC_STATE_REFILL:
- begin
- if (refill_ready == `TRUE)
- refill_offset <= refill_offset + 1'b1;
- end
-
- endcase
- end
+ if (dtlb_write_port_enable)
+ begin
+ $display("[DTLB data : %d] Writing 0x%08X to 0x%08X", $time, dtlb_write_data, dtlb_data_write_address);
+ end
end
- end
-endgenerate
-
-endmodule
+`endif
`endif
+endmodule
View
328 lm32_icache.v
@@ -57,9 +57,6 @@
`include "lm32_include.v"
`ifdef CFG_ICACHE_ENABLED
-`define LM32_KERNEL_MODE 1
-`define LM32_USER_MODE 0
-
`define LM32_IC_ADDR_OFFSET_RNG addr_offset_msb:addr_offset_lsb
`define LM32_IC_ADDR_SET_RNG addr_set_msb:addr_set_lsb
`define LM32_IC_ADDR_TAG_RNG addr_tag_msb:addr_tag_lsb
@@ -81,6 +78,8 @@
`define LM32_IC_STATE_CHECK 4'b0100
`define LM32_IC_STATE_REFILL 4'b1000
+`ifdef CFG_MMU_ENABLED
+
`define LM32_ITLB_CTRL_FLUSH 5'h1
`define LM32_ITLB_CTRL_UPDATE 5'h2
`define LM32_TLB_CTRL_SWITCH_TO_KERNEL_MODE 5'h4
@@ -90,6 +89,11 @@
`define LM32_TLB_STATE_CHECK 2'b01
`define LM32_TLB_STATE_FLUSH 2'b10
+`define LM32_KERNEL_MODE 1
+`define LM32_USER_MODE 0
+
+`endif
+
/////////////////////////////////////////////////////
// Module interface
/////////////////////////////////////////////////////
@@ -111,24 +115,30 @@ module lm32_icache (
`endif
valid_d,
branch_predict_taken_d,
+`ifdef CFG_MMU_ENABLED
csr,
csr_write_data,
csr_write_enable,
exception_x,
eret_q_x,
exception_m,
+`endif
// ----- Outputs -----
stall_request,
restart_request,
refill_request,
refill_address,
+`ifdef CFG_MMU_ENABLED
physical_refill_address,
+`endif
refilling,
- inst,
+`ifdef CFG_MMU_ENABLED
itlb_miss_int,
kernel_mode,
pa,
- csr_read_data
+ csr_read_data,
+`endif
+ inst
);
/////////////////////////////////////////////////////
@@ -141,6 +151,8 @@ parameter bytes_per_line = 16; // Number of bytes per c
parameter base_address = 0; // Base address of cachable memory
parameter limit = 0; // Limit (highest address) of cachable memory
+`ifdef CFG_MMU_ENABLED
+
parameter itlb_sets = 1024; // Number of lines of ITLB
parameter page_size = 4096; // System page size
@@ -173,6 +185,7 @@ localparam addr_itlb_tag_msb = addr_itlb_tag_lsb + addr_itlb_tag_width - 1;
`define LM32_ITLB_ADDR_TAG_RNG addr_itlb_tag_msb:addr_itlb_tag_lsb
`define LM32_ITLB_VALID_BIT vpfn_width+addr_itlb_tag_width
+`endif
localparam addr_offset_width = clogb2(bytes_per_line)-1-2;
localparam addr_set_width = clogb2(sets)-1;
@@ -208,20 +221,24 @@ input iflush; // Flush the cache
`ifdef CFG_IROM_ENABLED
input select_f; // Instruction in F stage is mapped through instruction cache
`endif
-
+
+`ifdef CFG_MMU_ENABLED
input [`LM32_CSR_RNG] csr; // CSR read/write index
input [`LM32_WORD_RNG] csr_write_data; // Data to write to specified CSR
input csr_write_enable; // CSR write enable
input exception_x; // An exception occured in the X stage
input exception_m;
input eret_q_x;
+`endif
/////////////////////////////////////////////////////
// Outputs
/////////////////////////////////////////////////////
+`ifdef CFG_MMU_ENABLED
output csr_read_data;
wire [`LM32_WORD_RNG] csr_read_data;
+`endif
output stall_request; // Request to stall the pipeline
wire stall_request;
@@ -231,17 +248,23 @@ output refill_request; // Request to refill a cache
wire refill_request;
output [`LM32_PC_RNG] refill_address; // Base address of cache refill
reg [`LM32_PC_RNG] refill_address;
+`ifdef CFG_MMU_ENABLED
output [`LM32_PC_RNG] physical_refill_address;
reg [`LM32_PC_RNG] physical_refill_address;
+`endif
output refilling; // Indicates the instruction cache is currently refilling
reg refilling;
output [`LM32_INSTRUCTION_RNG] inst; // Instruction read from cache
wire [`LM32_INSTRUCTION_RNG] inst;
+`ifdef CFG_MMU_ENABLED
output kernel_mode;
wire kernel_mode;
-
output itlb_miss_int;
+wire itlb_miss_int;
+output [`LM32_WORD_RNG] pa;
+wire [`LM32_WORD_RNG] pa;
+`endif
/////////////////////////////////////////////////////
// Internal nets and registers
@@ -271,20 +294,15 @@ reg [`LM32_IC_ADDR_OFFSET_RNG] refill_offset;
wire last_refill;
reg [`LM32_IC_TMEM_ADDR_RNG] flush_set;
+`ifdef CFG_MMU_ENABLED
+
wire [addr_itlb_index_width-1:0] itlb_data_read_address;
wire [addr_itlb_index_width-1:0] itlb_data_write_address;
wire itlb_data_read_port_enable;
wire itlb_write_port_enable;
wire [vpfn_width + addr_itlb_tag_width + 1 - 1:0] itlb_write_data; // +1 is for valid_bit
wire [vpfn_width + addr_itlb_tag_width + 1 - 1:0] itlb_read_data; // +1 is for valid_bit
-
wire [`LM32_WORD_RNG] physical_address;
-
-wire [`LM32_WORD_RNG] pa;
-output [`LM32_WORD_RNG] pa;
-
-assign pa = physical_address;
-
reg kernel_mode_reg = `LM32_KERNEL_MODE;
wire switch_to_kernel_mode;
wire switch_to_user_mode;
@@ -298,14 +316,16 @@ reg itlb_flushing;
reg [addr_itlb_index_width-1:0] itlb_flush_set;
wire itlb_miss;
reg itlb_miss_q = `FALSE;
-wire itlb_miss_int;
reg [`LM32_WORD_RNG] itlb_miss_addr;
wire itlb_data_valid;
wire [`LM32_ITLB_LOOKUP_RANGE] itlb_lookup;
+reg go_to_user_mode;
+reg go_to_user_mode_2;
+
+`endif
genvar i, j;
-assign kernel_mode = kernel_mode_reg;
/////////////////////////////////////////////////////
// Functions
@@ -317,6 +337,7 @@ assign kernel_mode = kernel_mode_reg;
// Instantiations
/////////////////////////////////////////////////////
+`ifdef CFG_MMU_ENABLED
// ITLB instantiation
lm32_ram
#(
@@ -339,17 +360,9 @@ lm32_ram
// ----- Outputs -------
.read_data (itlb_read_data)
);
-
-`ifdef CFG_VERBOSE_DISPLAY_ENABLED
-always @(posedge clk_i)
-begin
- if (itlb_write_port_enable)
- begin
- $display("[ITLB data : %d] Writing 0x%08X to 0x%08X", $time, itlb_write_data, itlb_data_write_address);
- end
-end
`endif
+
generate
for (i = 0; i < associativity; i = i + 1)
begin : memories
@@ -407,45 +420,18 @@ endgenerate
// Combinational logic
/////////////////////////////////////////////////////
-// CSR Write
-always @(posedge clk_i `CFG_RESET_SENSITIVITY)
-begin
- if (rst_i == `TRUE)
- begin
- itlb_ctrl_csr_reg <= `LM32_WORD_WIDTH'd0;
- itlb_update_vaddr_csr_reg <= `LM32_WORD_WIDTH'd0;
- itlb_update_paddr_csr_reg <= `LM32_WORD_WIDTH'd0;
- end
- else
- begin
- if (csr_write_enable)
- begin
- case (csr)
- `LM32_CSR_TLB_CTRL: if (~csr_write_data[0]) itlb_ctrl_csr_reg[31:1] <= csr_write_data[31:1];
- `LM32_CSR_TLB_VADDRESS: if (~csr_write_data[0]) itlb_update_vaddr_csr_reg[31:1] <= csr_write_data[31:1];
- `LM32_CSR_TLB_PADDRESS: if (~csr_write_data[0]) itlb_update_paddr_csr_reg[31:1] <= csr_write_data[31:1];
- endcase
- end
- itlb_ctrl_csr_reg[0] <= 0;
- itlb_update_vaddr_csr_reg[0] <= 0;
- itlb_update_paddr_csr_reg[0] <= 0;
- end
-end
-
// Compute which ways in the cache match the address address being read
generate
for (i = 0; i < associativity; i = i + 1)
begin : match
-assign itlb_read_tag = itlb_read_data[`LM32_ITLB_TAG_RANGE];
-assign itlb_data_valid = itlb_read_data[`LM32_ITLB_VALID_BIT];
-assign itlb_lookup = itlb_read_data[`LM32_ITLB_LOOKUP_RANGE];
-
-//assign way_match[i] = ({way_tag[i], way_valid[i]} == {address_f[`LM32_IC_ADDR_TAG_RNG], `TRUE});
-assign way_match[i] = (kernel_mode_reg == `LM32_KERNEL_MODE) ?
- ({way_tag[i], way_valid[i]} == {address_f[`LM32_IC_ADDR_TAG_RNG], `TRUE}) :
+assign way_match[i] =
+`ifdef CFG_MMU_ENABLED
+ (kernel_mode_reg == `LM32_USER_MODE) ?
+ ({way_tag[i], way_valid[i]} == {itlb_lookup, `TRUE }) :
+`endif
+ ({way_tag[i], way_valid[i]} == {address_f[`LM32_IC_ADDR_TAG_RNG], `TRUE});
- ({way_tag[i], way_valid[i]} == {itlb_lookup, `TRUE });
end
endgenerate
@@ -477,24 +463,6 @@ assign tmem_write_address = flushing
? flush_set
: refill_address[`LM32_IC_ADDR_SET_RNG];
-// Compute address to use to index into the ITLB data memory
-
-assign itlb_data_read_address = address_a[`LM32_ITLB_IDX_RNG];
-
-// tlb_update_address will receive data from a CSR register
-assign itlb_data_write_address = itlb_update_vaddr_csr_reg[`LM32_ITLB_IDX_RNG];
-
-assign itlb_data_read_port_enable = (stall_a == `FALSE) || !stall_f;
-assign itlb_write_port_enable = itlb_updating || itlb_flushing;
-
-assign physical_address = (kernel_mode_reg == `LM32_KERNEL_MODE)
- ? {address_f, 2'b0}
- : {itlb_lookup, address_f[`LM32_PAGE_OFFSET_RNG+2], 2'b0};
-
-assign itlb_write_data = (itlb_flushing == `TRUE)
- ? {`FALSE, {addr_itlb_tag_width{1'b0}}, {vpfn_width{1'b0}}}
- : {`TRUE, {itlb_update_vaddr_csr_reg[`LM32_ITLB_ADDR_TAG_RNG]}, itlb_update_paddr_csr_reg[`LM32_ITLB_ADDRESS_PFN_RNG]};
-
// Compute signal to indicate when we are on the last refill accesses
generate
@@ -522,7 +490,11 @@ endgenerate
// On the last refill cycle set the valid bit, for all other writes it should be cleared
assign tmem_write_data[`LM32_IC_TAGS_VALID_RNG] = last_refill & !flushing;
+`ifdef CFG_MMU_ENABLED
assign tmem_write_data[`LM32_IC_TAGS_TAG_RNG] = physical_refill_address[`LM32_IC_ADDR_TAG_RNG];
+`else
+assign tmem_write_data[`LM32_IC_TAGS_TAG_RNG] = refill_address[`LM32_IC_ADDR_TAG_RNG];
+`endif
// Signals that indicate which state we are in
assign flushing = |state[1:0];
@@ -571,6 +543,9 @@ begin
state <= `LM32_IC_STATE_FLUSH_INIT;
flush_set <= {`LM32_IC_TMEM_ADDR_WIDTH{1'b1}};
refill_address <= {`LM32_PC_WIDTH{1'bx}};
+`ifdef CFG_MMU_ENABLED
+ physical_refill_address <= {`LM32_PC_WIDTH{1'bx}};
+`endif
restart_request <= `FALSE;
end
else
@@ -606,13 +581,17 @@ begin
restart_request <= `FALSE;
if (iflush == `TRUE)
begin
+`ifdef CFG_MMU_ENABLED
physical_refill_address <= physical_address[`LM32_PC_RNG];
+`endif
refill_address <= address_f;
state <= `LM32_IC_STATE_FLUSH;
end
else if (miss == `TRUE)
begin
+`ifdef CFG_MMU_ENABLED
physical_refill_address <= physical_address[`LM32_PC_RNG];
+`endif
refill_address <= address_f;
state <= `LM32_IC_STATE_REFILL;
end
@@ -635,9 +614,110 @@ begin
end
end
-assign csr_read_data = itlb_miss_addr;
+generate
+ if (bytes_per_line > 4)
+ begin
+// Refill offset
+always @(posedge clk_i `CFG_RESET_SENSITIVITY)
+begin
+ if (rst_i == `TRUE)
+ refill_offset <= {addr_offset_width{1'b0}};
+ else
+ begin
+ case (state)
+
+ // Check for cache misses
+ `LM32_IC_STATE_CHECK:
+ begin
+ if (iflush == `TRUE)
+ refill_offset <= {addr_offset_width{1'b0}};
+ else if (miss == `TRUE)
+ refill_offset <= {addr_offset_width{1'b0}};
+ end
+
+ // Refill a cache line
+ `LM32_IC_STATE_REFILL:
+ begin
+ if (refill_ready == `TRUE)
+ refill_offset <= refill_offset + 1'b1;
+ end
+
+ endcase
+ end
+end
+ end
+endgenerate
+
+`ifdef CFG_MMU_ENABLED
+
+// Compute address to use to index into the ITLB data memory
+assign itlb_data_read_address = address_a[`LM32_ITLB_IDX_RNG];
+
+// tlb_update_address will receive data from a CSR register
+assign itlb_data_write_address = itlb_update_vaddr_csr_reg[`LM32_ITLB_IDX_RNG];
+
+assign itlb_data_read_port_enable = (stall_a == `FALSE) || !stall_f;
+assign itlb_write_port_enable = itlb_updating || itlb_flushing;
+
+assign physical_address = (kernel_mode_reg == `LM32_KERNEL_MODE)
+ ? {address_f, 2'b0}
+ : {itlb_lookup, address_f[`LM32_PAGE_OFFSET_RNG+2], 2'b0};
+assign itlb_write_data = (itlb_flushing == `TRUE)
+ ? {`FALSE, {addr_itlb_tag_width{1'b0}}, {vpfn_width{1'b0}}}
+ : {`TRUE, {itlb_update_vaddr_csr_reg[`LM32_ITLB_ADDR_TAG_RNG]}, itlb_update_paddr_csr_reg[`LM32_ITLB_ADDRESS_PFN_RNG]};
+
+assign pa = physical_address;
+assign kernel_mode = kernel_mode_reg;
+
+assign switch_to_kernel_mode = (/*(kernel_mode_reg == `LM32_KERNEL_MODE) && */csr_write_enable && (csr == `LM32_CSR_TLB_CTRL) && csr_write_data[5:0] == {`LM32_TLB_CTRL_SWITCH_TO_KERNEL_MODE, 1'b0});
+assign switch_to_user_mode = (/*(kernel_mode_reg == `LM32_KERNEL_MODE) && */csr_write_enable && (csr == `LM32_CSR_TLB_CTRL) && csr_write_data[5:0] == {`LM32_TLB_CTRL_SWITCH_TO_USER_MODE, 1'b0});
+
+assign csr_read_data = itlb_miss_addr;
assign itlb_miss = (kernel_mode_reg == `LM32_USER_MODE) && (read_enable_f) && ~(itlb_data_valid);
+assign itlb_miss_int = (itlb_miss || itlb_miss_q);
+assign itlb_read_tag = itlb_read_data[`LM32_ITLB_TAG_RANGE];
+assign itlb_data_valid = itlb_read_data[`LM32_ITLB_VALID_BIT];
+assign itlb_lookup = itlb_read_data[`LM32_ITLB_LOOKUP_RANGE];
+
+`ifdef CFG_VERBOSE_DISPLAY_ENABLED
+always @(posedge clk_i)
+begin
+ if (itlb_write_port_enable)
+ begin
+ $display("[ITLB data : %d] Writing 0x%08X to 0x%08X", $time, itlb_write_data, itlb_data_write_address);
+ end
+end
+`endif
+
+always @(posedge clk_i `CFG_RESET_SENSITIVITY)
+begin
+ if (rst_i == `TRUE)
+ go_to_user_mode <= `FALSE;
+ else
+ go_to_user_mode <= (eret_q_x || switch_to_user_mode);
+end
+
+always @(posedge clk_i `CFG_RESET_SENSITIVITY)
+begin
+ if (rst_i == `TRUE)
+ go_to_user_mode_2 <= `FALSE;
+ else
+ go_to_user_mode_2 <= go_to_user_mode;
+end
+
+always @(posedge clk_i `CFG_RESET_SENSITIVITY)
+begin
+ if (rst_i == `TRUE)
+ kernel_mode_reg <= `LM32_KERNEL_MODE;
+ else
+ begin
+ if (exception_x || switch_to_kernel_mode)
+ kernel_mode_reg <= `LM32_KERNEL_MODE;
+ else if (go_to_user_mode_2)
+ kernel_mode_reg <= `LM32_USER_MODE;
+ end
+end
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
@@ -652,7 +732,30 @@ begin
end
end
-assign itlb_miss_int = (itlb_miss || itlb_miss_q);
+// CSR Write
+always @(posedge clk_i `CFG_RESET_SENSITIVITY)
+begin
+ if (rst_i == `TRUE)
+ begin
+ itlb_ctrl_csr_reg <= `LM32_WORD_WIDTH'd0;
+ itlb_update_vaddr_csr_reg <= `LM32_WORD_WIDTH'd0;
+ itlb_update_paddr_csr_reg <= `LM32_WORD_WIDTH'd0;
+ end
+ else
+ begin
+ if (csr_write_enable)
+ begin
+ case (csr)
+ `LM32_CSR_TLB_CTRL: if (~csr_write_data[0]) itlb_ctrl_csr_reg[31:1] <= csr_write_data[31:1];
+ `LM32_CSR_TLB_VADDRESS: if (~csr_write_data[0]) itlb_update_vaddr_csr_reg[31:1] <= csr_write_data[31:1];
+ `LM32_CSR_TLB_PADDRESS: if (~csr_write_data[0]) itlb_update_paddr_csr_reg[31:1] <= csr_write_data[31:1];
+ endcase
+ end
+ itlb_ctrl_csr_reg[0] <= 0;
+ itlb_update_vaddr_csr_reg[0] <= 0;
+ itlb_update_paddr_csr_reg[0] <= 0;
+ end
+end
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
@@ -733,75 +836,8 @@ begin
end
end
-assign switch_to_kernel_mode = (/*(kernel_mode_reg == `LM32_KERNEL_MODE) && */csr_write_enable && (csr == `LM32_CSR_TLB_CTRL) && csr_write_data[5:0] == {`LM32_TLB_CTRL_SWITCH_TO_KERNEL_MODE, 1'b0});
-assign switch_to_user_mode = (/*(kernel_mode_reg == `LM32_KERNEL_MODE) && */csr_write_enable && (csr == `LM32_CSR_TLB_CTRL) && csr_write_data[5:0] == {`LM32_TLB_CTRL_SWITCH_TO_USER_MODE, 1'b0});
-
-reg go_to_user_mode;
-reg go_to_user_mode_2;
-
-always @(posedge clk_i `CFG_RESET_SENSITIVITY)
-begin
- if (rst_i == `TRUE)
- go_to_user_mode <= `FALSE;
- else
- go_to_user_mode <= (eret_q_x || switch_to_user_mode);
-end
-
-always @(posedge clk_i `CFG_RESET_SENSITIVITY)
-begin
- if (rst_i == `TRUE)
- go_to_user_mode_2 <= `FALSE;
- else
- go_to_user_mode_2 <= go_to_user_mode;
-end
-
-always @(posedge clk_i `CFG_RESET_SENSITIVITY)
-begin
- if (rst_i == `TRUE)
- kernel_mode_reg <= `LM32_KERNEL_MODE;
- else
- begin
- if (exception_x || switch_to_kernel_mode)
- kernel_mode_reg <= `LM32_KERNEL_MODE;
- else if (go_to_user_mode_2)
- kernel_mode_reg <= `LM32_USER_MODE;
- end
-end
-
-generate
- if (bytes_per_line > 4)
- begin
-// Refill offset
-always @(posedge clk_i `CFG_RESET_SENSITIVITY)
-begin
- if (rst_i == `TRUE)
- refill_offset <= {addr_offset_width{1'b0}};
- else
- begin
- case (state)
-
- // Check for cache misses
- `LM32_IC_STATE_CHECK:
- begin
- if (iflush == `TRUE)
- refill_offset <= {addr_offset_width{1'b0}};
- else if (miss == `TRUE)
- refill_offset <= {addr_offset_width{1'b0}};
- end
-
- // Refill a cache line
- `LM32_IC_STATE_REFILL:
- begin
- if (refill_ready == `TRUE)
- refill_offset <= refill_offset + 1'b1;
- end
+`endif
- endcase
- end
-end
- end
-endgenerate
-
endmodule
`endif
View
38 lm32_instruction_unit.v
@@ -99,7 +99,9 @@ module lm32_instruction_unit (
branch_target_x,
`endif
exception_m,
+`ifdef CFG_MMU_ENABLED
exception_x,
+`endif
branch_taken_m,
branch_mispredict_taken_m,
branch_target_m,
@@ -116,10 +118,12 @@ module lm32_instruction_unit (
irom_address_xm,
irom_we_xm,
`endif
+`ifdef CFG_MMU_ENABLED
csr,
csr_write_data,
csr_write_enable,
eret_q_x,
+`endif
`ifdef CFG_IWB_ENABLED
// From Wishbone
i_dat_i,
@@ -148,8 +152,10 @@ module lm32_instruction_unit (
`ifdef CFG_IROM_ENABLED
irom_data_m,
`endif
+`ifdef CFG_MMU_ENABLED
itlb_miss,
csr_read_data,
+`endif
`ifdef CFG_IWB_ENABLED
// To Wishbone
i_dat_o,
@@ -252,12 +258,13 @@ input [`LM32_BYTE_RNG] jtag_write_data; // JTAG wrirte data
input [`LM32_WORD_RNG] jtag_address; // JTAG read/write address
`endif
+`ifdef CFG_MMU_ENABLED
input exception_x; // An exception occured in the X stage
input eret_q_x;
-
input [`LM32_CSR_RNG] csr; // CSR read/write index
input [`LM32_WORD_RNG] csr_write_data; // Data to write to specified CSR
input csr_write_enable; // CSR write enable
+`endif
/////////////////////////////////////////////////////
// Outputs
@@ -341,11 +348,12 @@ wire [`LM32_INSTRUCTION_RNG] instruction_f;
output [`LM32_INSTRUCTION_RNG] instruction_d; // D stage instruction to be decoded
reg [`LM32_INSTRUCTION_RNG] instruction_d;
+`ifdef CFG_MMU_ENABLED
output csr_read_data;
wire [`LM32_WORD_RNG] csr_read_data;
-
output itlb_miss;
wire itlb_miss;
+`endif
/////////////////////////////////////////////////////
// Internal nets and registers
@@ -360,7 +368,9 @@ reg [`LM32_PC_RNG] restart_address; // Address to restart fr
`ifdef CFG_ICACHE_ENABLED
wire icache_read_enable_f; // Indicates if instruction cache miss is valid
wire [`LM32_PC_RNG] icache_refill_address; // Address that caused cache miss
+`ifdef CFG_MMU_ENABLED
wire [`LM32_PC_RNG] icache_physical_refill_address; // Physical address that caused cache miss
+`endif
reg icache_refill_ready; // Indicates when next word of refill data is ready to be written to cache
reg [`LM32_INSTRUCTION_RNG] icache_refill_data; // Next word of refill data, fetched from Wishbone
wire [`LM32_INSTRUCTION_RNG] icache_data_f; // Instruction fetched from instruction cache
@@ -394,8 +404,10 @@ reg jtag_access; // Indicates if a JTAG W
reg alternate_eba_taken;
`endif
+`ifdef CFG_MMU_ENABLED
wire [`LM32_WORD_RNG] physical_address;
wire kernel_mode;
+`endif
/////////////////////////////////////////////////////
// Functions
@@ -478,24 +490,30 @@ lm32_icache #(
.refill_ready (icache_refill_ready),
.refill_data (icache_refill_data),
.iflush (iflush),
+`ifdef CFG_MMU_ENABLED
.csr (csr),
.csr_write_data (csr_write_data),
.csr_write_enable (csr_write_enable),
.exception_x (exception_x),
.eret_q_x (eret_q_x),
.exception_m (exception_m),
+`endif
// ----- Outputs -----
.stall_request (icache_stall_request),
.restart_request (icache_restart_request),
.refill_request (icache_refill_request),
.refill_address (icache_refill_address),
+`ifdef CFG_MMU_ENABLED
.physical_refill_address (icache_physical_refill_address),
+`endif
.refilling (icache_refilling),
- .inst (icache_data_f),
+`ifdef CFG_MMU_ENABLED
.itlb_miss_int (itlb_miss),
.kernel_mode (kernel_mode),
.pa (physical_address),
- .csr_read_data (csr_read_data)
+ .csr_read_data (csr_read_data),
+`endif
+ .inst (icache_data_f)
);
`endif
@@ -590,21 +608,33 @@ generate
assign first_cycle_type = `LM32_CTYPE_END;
assign next_cycle_type = `LM32_CTYPE_END;
assign last_word = `TRUE;
+`ifdef CFG_MMU_ENABLED
assign first_address = icache_physical_refill_address;
+`else
+assign first_address = icache_refill_address;
+`endif
end
8:
begin
assign first_cycle_type = `LM32_CTYPE_INCREMENTING;
assign next_cycle_type = `LM32_CTYPE_END;
assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 1'b1;
+`ifdef CFG_MMU_ENABLED
assign first_address = {icache_physical_refill_address[`LM32_PC_WIDTH+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
+`else
+assign first_address = {icache_refill_address[`LM32_PC_WIDTH+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
+`endif
end
16:
begin
assign first_cycle_type = `LM32_CTYPE_INCREMENTING;
assign next_cycle_type = i_adr_o[addr_offset_msb] == 1'b1 ? `LM32_CTYPE_END : `LM32_CTYPE_INCREMENTING;
assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 2'b11;
+`ifdef CFG_MMU_ENABLED
assign first_address = {icache_physical_refill_address[`LM32_PC_WIDTH+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
+`else
+assign first_address = {icache_refill_address[`LM32_PC_WIDTH+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
+`endif
end
endcase
endgenerate
View
47 lm32_load_store_unit.v
@@ -99,10 +99,12 @@ module lm32_load_store_unit (
`ifdef CFG_IROM_ENABLED
irom_data_m,
`endif
+`ifdef CFG_MMU_ENABLED
csr,
csr_write_data,
csr_write_enable,
eret_q_x,
+`endif
// From Wishbone
d_dat_i,
d_ack_i,
@@ -124,8 +126,10 @@ module lm32_load_store_unit (
`endif
load_data_w,
stall_wb_load,
+`ifdef CFG_MMU_ENABLED
dtlb_miss,
csr_read_data,
+`endif
// To Wishbone
d_dat_o,
d_adr_o,
@@ -169,11 +173,11 @@ input exception_m; // An exception occured
input exception_x; // An exception occured in the X stage
input eret_q_x;
-
+`ifdef CFG_MMU_ENABLED
input [`LM32_CSR_RNG] csr; // CSR read/write index
input [`LM32_WORD_RNG] csr_write_data; // Data to write to specified CSR
input csr_write_enable; // CSR write enable
-
+`endif
input [`LM32_WORD_RNG] store_operand_x; // Data read from register to store
input [`LM32_WORD_RNG] load_store_address_x; // X stage load/store address
@@ -196,8 +200,10 @@ input dflush; // Flush the data cache
input [`LM32_WORD_RNG] irom_data_m; // Data from Instruction-ROM
`endif
+`ifdef CFG_MMU_ENABLED
wire dtlb_miss;
output dtlb_miss;
+`endif
input [`LM32_WORD_RNG] d_dat_i; // Data Wishbone interface read data
input d_ack_i; // Data Wishbone interface acknowledgement
@@ -219,8 +225,10 @@ output dcache_refilling;
wire dcache_refilling;
`endif
+`ifdef CFG_MMU_ENABLED
output csr_read_data;
wire [`LM32_WORD_RNG] csr_read_data;
+`endif
`ifdef CFG_IROM_ENABLED
output irom_store_data_m; // Store data to Instruction ROM
@@ -279,7 +287,6 @@ reg dcache_select_m;
wire [`LM32_WORD_RNG] dcache_data_m; // Data read from cache
wire [`LM32_WORD_RNG] dcache_refill_address; // Address to refill data cache from
reg dcache_refill_ready; // Indicates the next word of refill data is ready
-reg d_adr_o_sampling;
wire [`LM32_CTYPE_RNG] first_cycle_type; // First Wishbone cycle type
wire [`LM32_CTYPE_RNG] next_cycle_type; // Next Wishbone cycle type
wire last_word; // Indicates if this is the last word in the cache line
@@ -303,8 +310,10 @@ reg wb_select_m;
reg [`LM32_WORD_RNG] wb_data_m; // Data read from Wishbone
reg wb_load_complete; // Indicates when a Wishbone load is complete
+`ifdef CFG_MMU_ENABLED
wire [`LM32_WORD_RNG] physical_address;
wire kernel_mode;
+`endif
/////////////////////////////////////////////////////
// Functions
@@ -424,23 +433,27 @@ lm32_dcache #(
.refill_ready (dcache_refill_ready),
.refill_data (wb_data_m),
.dflush (dflush),
+`ifdef CFG_MMU_ENABLED
.csr (csr),
.csr_write_data (csr_write_data),
.csr_write_enable (csr_write_enable),
.exception_x (exception_x),
.eret_q_x (eret_q_x),
.exception_m (exception_m),
+`endif
// ----- Outputs -----
.stall_request (dcache_stall_request),
.restart_request (dcache_restart_request),
.refill_request (dcache_refill_request),
.refill_address (dcache_refill_address),
.refilling (dcache_refilling),
- .load_data (dcache_data_m),
+`ifdef CFG_MMU_ENABLED
.dtlb_miss_int (dtlb_miss),
.kernel_mode (kernel_mode),
.pa (physical_address),
- .csr_read_data (csr_read_data)
+ .csr_read_data (csr_read_data),
+`endif
+ .load_data (dcache_data_m)
);
`endif
@@ -664,7 +677,6 @@ always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
begin
- d_adr_o_sampling <= `FALSE;
d_cyc_o <= `FALSE;
d_stb_o <= `FALSE;
d_dat_o <= {`LM32_WORD_WIDTH{1'b0}};
@@ -701,7 +713,6 @@ begin
else
`endif
begin
- d_adr_o_sampling <= 0;
// Refill/access complete
d_cyc_o <= `FALSE;
d_stb_o <= `FALSE;
@@ -728,10 +739,11 @@ begin
if (dcache_refill_request == `TRUE)
begin
// Start cache refill
+`ifdef CFG_MMU_ENABLED
`ifdef CFG_VERBOSE_DISPLAY_ENABLED
$display("Sampling address to refill 0x%08X\n", first_address);
`endif
- d_adr_o_sampling <= 1;
+`endif
d_adr_o <= first_address;
d_cyc_o <= `TRUE;
d_sel_o <= {`LM32_WORD_WIDTH/8{`TRUE}};
@@ -756,12 +768,17 @@ begin
)
begin
// Data cache is write through, so all stores go to memory
+`ifdef CFG_MMU_ENABLED
`ifdef CFG_VERBOSE_DISPLAY_ENABLED
$display("Sampling address to write through 0x%08X\n", store_data_m);
`endif
- d_adr_o_sampling <= 1;
+`endif
d_dat_o <= store_data_m;
- d_adr_o <= (kernel_mode == `LM32_KERNEL_MODE) ? load_store_address_m : physical_address;
+ d_adr_o <=
+`ifdef CFG_MMU_ENABLED
+ (kernel_mode == `LM32_USER_MODE) ? physical_address :
+`endif
+ load_store_address_m;
d_cyc_o <= `TRUE;
d_sel_o <= byte_enable_m;
d_stb_o <= `TRUE;
@@ -775,12 +792,18 @@ begin
)
begin
// Read requested address
+`ifdef CFG_MMU_ENABLED
`ifdef CFG_VERBOSE_DISPLAY_ENABLED
$display("Sampling address to read 0x%08X\n", (kernel_mode == `LM32_KERNEL_MODE) ? load_store_address_m : physical_address);
`endif
- d_adr_o_sampling <= 1;
+`endif
stall_wb_load <= `FALSE;
- d_adr_o <= (kernel_mode == `LM32_KERNEL_MODE) ? load_store_address_m : physical_address;
+ d_adr_o <=
+`ifdef CFG_MMU_ENABLED
+ (kernel_mode == `LM32_USER_MODE) ? physical_address :
+`endif
+ load_store_address_m;
+
d_cyc_o <= `TRUE;
d_sel_o <= byte_enable_m;
d_stb_o <= `TRUE;

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