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18  lm32_cpu.v
@@ -778,6 +778,10 @@ reg data_bus_error_seen;                        // Indicates if a data bus error
778 778
 reg ext_break_r;
779 779
 `endif
780 780
 
  781
+`ifdef CFG_MMU_ENABLED
  782
+wire dtlb_miss_exception;
  783
+`endif
  784
+
781 785
 /////////////////////////////////////////////////////
782 786
 // Functions
783 787
 /////////////////////////////////////////////////////
@@ -820,7 +824,9 @@ lm32_instruction_unit #(
820 824
     .branch_target_x        (branch_target_x),
821 825
 `endif
822 826
     .exception_m            (exception_m),
  827
+`ifdef CFG_MMU_ENABLED
823 828
     .exception_x            (exception_x),
  829
+`endif
824 830
     .branch_taken_m         (branch_taken_m),
825 831
     .branch_mispredict_taken_m (branch_mispredict_taken_m),
826 832
     .branch_target_m        (branch_target_m),
@@ -837,10 +843,12 @@ lm32_instruction_unit #(
837 843
     .dcache_refill_request  (dcache_refill_request),
838 844
     .dcache_refilling       (dcache_refilling),
839 845
 `endif
  846
+`ifdef CFG_MMU_ENABLED
840 847
     .csr		    (csr_x),
841 848
     .csr_write_data	    (operand_1_x),
842 849
     .csr_write_enable	    (csr_write_enable_q_x),
843 850
     .eret_q_x		    (eret_q_x),
  851
+`endif
844 852
 `ifdef CFG_IWB_ENABLED
845 853
     // From Wishbone
846 854
     .i_dat_i                (I_DAT_I),
@@ -869,8 +877,10 @@ lm32_instruction_unit #(
869 877
 `ifdef CFG_IROM_ENABLED
870 878
     .irom_data_m            (irom_data_m),
871 879
 `endif
  880
+`ifdef CFG_MMU_ENABLED
872 881
     .itlb_miss		    (itlb_miss_exception),
873 882
     .csr_read_data	    (instruction_csr_read_data_x),
  883
+`endif
874 884
 `ifdef CFG_IWB_ENABLED
875 885
     // To Wishbone
876 886
     .i_dat_o                (I_DAT_O),
@@ -975,8 +985,6 @@ lm32_decoder decoder (
975 985
     .csr_write_enable       (csr_write_enable_d)
976 986
     ); 
977 987
 
978  
-wire dtlb_miss_exception;
979  
-
980 988
 // Load/store unit       
981 989
 lm32_load_store_unit #(
982 990
     .associativity          (dcache_associativity),
@@ -1014,10 +1022,12 @@ lm32_load_store_unit #(
1014 1022
 `ifdef CFG_IROM_ENABLED
1015 1023
     .irom_data_m            (irom_data_m),
1016 1024
 `endif
  1025
+`ifdef CFG_MMU_ENABLED
1017 1026
     .csr		    (csr_x),
1018 1027
     .csr_write_data         (operand_1_x),
1019 1028
     .csr_write_enable       (csr_write_enable_q_x),
1020 1029
     .eret_q_x		    (eret_q_x),
  1030
+`endif
1021 1031
     // From Wishbone
1022 1032
     .d_dat_i                (D_DAT_I),
1023 1033
     .d_ack_i                (D_ACK_I),
@@ -1039,8 +1049,10 @@ lm32_load_store_unit #(
1039 1049
 `endif
1040 1050
     .load_data_w            (load_data_w),
1041 1051
     .stall_wb_load          (stall_wb_load),
  1052
+`ifdef CFG_MMU_ENABLED
1042 1053
     .dtlb_miss		    (dtlb_miss_exception),
1043 1054
     .csr_read_data          (load_store_csr_read_data_x),
  1055
+`endif
1044 1056
     // To Wishbone
1045 1057
     .d_dat_o                (D_DAT_O),
1046 1058
     .d_adr_o                (D_ADR_O),
@@ -1855,9 +1867,11 @@ begin
1855 1867
         eid_x = `LM32_EID_INTERRUPT;
1856 1868
     else
1857 1869
 `endif
  1870
+`ifdef CFG_MMU_ENABLED
1858 1871
 	if (dtlb_miss_exception == `TRUE )
1859 1872
 		eid_x = `LM32_EID_DTLB_MISS;
1860 1873
 	else
  1874
+`endif
1861 1875
 		eid_x = `LM32_EID_SCALL;
1862 1876
 end
1863 1877
 
351  lm32_dcache.v
@@ -2,7 +2,7 @@
2 2
 //   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
3 3
 //   ------------------------------------------------------------------
4 4
 //   Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
5  
-//   ALL RIGHTS RESERVED 
  5
+//   ALL RIGHTS RESERVED
6 6
 //   ------------------------------------------------------------------
7 7
 //
8 8
 //   IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
@@ -11,7 +11,7 @@
11 11
 //
12 12
 //      Lattice Semiconductor grants permission to use this code
13 13
 //      pursuant to the terms of the Lattice Semiconductor Corporation
14  
-//      Open Source License Agreement.  
  14
+//      Open Source License Agreement.
15 15
 //
16 16
 //   Disclaimer:
17 17
 //
@@ -48,14 +48,11 @@
48 48
 //                  : cache memory. Additional parameters must be defined when
49 49
 //                  : invoking lm32_ram.v
50 50
 // =============================================================================
51  
-								 
  51
+
52 52
 `include "lm32_include.v"
53 53
 
54 54
 `ifdef CFG_DCACHE_ENABLED
55 55
 
56  
-`define LM32_KERNEL_MODE		 1
57  
-`define LM32_USER_MODE			 0
58  
-
59 56
 `define LM32_DC_ADDR_OFFSET_RNG          addr_offset_msb:addr_offset_lsb
60 57
 `define LM32_DC_ADDR_SET_RNG             addr_set_msb:addr_set_lsb
61 58
 `define LM32_DC_ADDR_TAG_RNG             addr_tag_msb:addr_tag_lsb
@@ -76,6 +73,7 @@
76 73
 `define LM32_DC_STATE_CHECK              3'b010
77 74
 `define LM32_DC_STATE_REFILL             3'b100
78 75
 
  76
+`ifdef CFG_MMU_ENABLED
79 77
 `define LM32_DTLB_CTRL_FLUSH		 	5'h1
80 78
 `define LM32_DTLB_CTRL_UPDATE		 	5'h2
81 79
 `define LM32_TLB_CTRL_SWITCH_TO_KERNEL_MODE	5'h4
@@ -85,14 +83,18 @@
85 83
 `define LM32_TLB_STATE_CHECK		 2'b01
86 84
 `define LM32_TLB_STATE_FLUSH		 2'b10
87 85
 
  86
+`define LM32_KERNEL_MODE		 1
  87
+`define LM32_USER_MODE			 0
  88
+`endif
  89
+
88 90
 /////////////////////////////////////////////////////
89 91
 // Module interface
90 92
 /////////////////////////////////////////////////////
91 93
 
92  
-module lm32_dcache ( 
  94
+module lm32_dcache (
93 95
     // ----- Inputs -----
94 96
     clk_i,
95  
-    rst_i,    
  97
+    rst_i,
96 98
     stall_a,
97 99
     stall_x,
98 100
     stall_m,
@@ -105,24 +107,27 @@ module lm32_dcache (
105 107
     refill_ready,
106 108
     refill_data,
107 109
     dflush,
  110
+`ifdef CFG_MMU_ENABLED
108 111
     csr,
109 112
     csr_write_data,
110 113
     csr_write_enable,
111 114
     exception_x,
112 115
     eret_q_x,
113 116
     exception_m,
  117
+`endif
114 118
     // ----- Outputs -----
115 119
     stall_request,
116 120
     restart_request,
117 121
     refill_request,
118 122
     refill_address,
119 123
     refilling,
120  
-    load_data,
121  
-   // To pipeline
  124
+`ifdef CFG_MMU_ENABLED
122 125
     dtlb_miss_int,
123 126
     kernel_mode,
124 127
     pa,
125  
-    csr_read_data
  128
+    csr_read_data,
  129
+`endif
  130
+    load_data
126 131
     );
127 132
 
128 133
 /////////////////////////////////////////////////////
@@ -135,6 +140,8 @@ parameter bytes_per_line = 16;                          // Number of bytes per c
135 140
 parameter base_address = 0;                             // Base address of cachable memory
136 141
 parameter limit = 0;                                    // Limit (highest address) of cachable memory
137 142
 
  143
+`ifdef CFG_MMU_ENABLED
  144
+
138 145
 parameter dtlb_sets = 1024;				// Number of lines of DTLB
139 146
 parameter page_size = 4096;				// System page size
140 147
 
@@ -167,6 +174,7 @@ localparam addr_dtlb_tag_msb = addr_dtlb_tag_lsb + addr_dtlb_tag_width - 1;
167 174
 `define LM32_DTLB_ADDR_TAG_RNG		addr_dtlb_tag_msb:addr_dtlb_tag_lsb
168 175
 `define LM32_DTLB_VALID_BIT		vpfn_width+addr_dtlb_tag_width
169 176
 
  177
+`endif
170 178
 
171 179
 localparam addr_offset_width = clogb2(bytes_per_line)-1-2;
172 180
 localparam addr_set_width = clogb2(sets)-1;
@@ -201,6 +209,7 @@ input [`LM32_WORD_RNG] refill_data;                     // Refill data
201 209
 
202 210
 input dflush;                                           // Indicates cache should be flushed
203 211
 
  212
+`ifdef CFG_MMU_ENABLED
204 213
 
205 214
 input [`LM32_CSR_RNG] csr;				// CSR read/write index
206 215
 input [`LM32_WORD_RNG] csr_write_data;			// Data to write to specified CSR
@@ -209,18 +218,17 @@ input exception_x;					// An exception occured in the X stage
209 218
 input exception_m;
210 219
 input eret_q_x;
211 220
 
  221
+`endif
  222
+
212 223
 /////////////////////////////////////////////////////
213 224
 // Outputs
214 225
 /////////////////////////////////////////////////////
215 226
 
216  
-output csr_read_data;
217  
-wire [`LM32_WORD_RNG] csr_read_data;
218  
-
219 227
 output stall_request;                                   // Request pipeline be stalled because cache is busy
220 228
 wire   stall_request;
221 229
 output restart_request;                                 // Request to restart instruction that caused the cache miss
222 230
 reg    restart_request;
223  
-output refill_request;                                  // Request a refill 
  231
+output refill_request;                                  // Request a refill
224 232
 reg    refill_request;
225 233
 output [`LM32_WORD_RNG] refill_address;                 // Address to refill from
226 234
 reg    [`LM32_WORD_RNG] refill_address;
@@ -229,13 +237,21 @@ reg    refilling;
229 237
 output [`LM32_WORD_RNG] load_data;                      // Data read from cache
230 238
 wire   [`LM32_WORD_RNG] load_data;
231 239
 
  240
+`ifdef CFG_MMU_ENABLED
  241
+
232 242
 output kernel_mode;
233 243
 wire kernel_mode;
234  
-
  244
+output csr_read_data;
  245
+wire [`LM32_WORD_RNG] csr_read_data;
235 246
 output dtlb_miss_int;
  247
+wire dtlb_miss_int;
  248
+output [`LM32_WORD_RNG] pa;
  249
+wire [`LM32_WORD_RNG] pa;
  250
+
  251
+`endif
236 252
 
237 253
 /////////////////////////////////////////////////////
238  
-// Internal nets and registers 
  254
+// Internal nets and registers
239 255
 /////////////////////////////////////////////////////
240 256
 
241 257
 wire read_port_enable;                                  // Cache memory read port clock enable
@@ -252,7 +268,7 @@ wire [`LM32_DC_TMEM_ADDR_RNG] tmem_read_address;        // Tag memory read addre
252 268
 wire [`LM32_DC_TMEM_ADDR_RNG] tmem_write_address;       // Tag memory write address
253 269
 wire [`LM32_DC_DMEM_ADDR_RNG] dmem_read_address;        // Data memory read address
254 270
 wire [`LM32_DC_DMEM_ADDR_RNG] dmem_write_address;       // Data memory write address
255  
-wire [`LM32_DC_TAGS_RNG] tmem_write_data;               // Tag memory write data        
  271
+wire [`LM32_DC_TAGS_RNG] tmem_write_data;               // Tag memory write data
256 272
 reg [`LM32_WORD_RNG] dmem_write_data;                   // Data memory write data
257 273
 
258 274
 reg [`LM32_DC_STATE_RNG] state;                         // Current state of FSM
@@ -272,13 +288,8 @@ wire dtlb_data_read_port_enable;
272 288
 wire dtlb_write_port_enable;
273 289
 wire [vpfn_width + addr_dtlb_tag_width + 1 - 1:0] dtlb_write_data; // +1 is for valid_bit
274 290
 wire [vpfn_width + addr_dtlb_tag_width + 1 - 1:0] dtlb_read_data; // +1 is for valid_bit
275  
-
276 291
 wire [`LM32_WORD_RNG] physical_address;
277 292
 
278  
-wire [`LM32_WORD_RNG] pa;
279  
-output [`LM32_WORD_RNG] pa;
280  
-reg [`LM32_WORD_RNG] latest_store_tlb_lookup; 
281  
-
282 293
 assign pa = physical_address;
283 294
 
284 295
 reg kernel_mode_reg = `LM32_KERNEL_MODE;
@@ -294,7 +305,6 @@ reg dtlb_flushing;
294 305
 reg [addr_dtlb_index_width-1:0] dtlb_flush_set;
295 306
 wire dtlb_miss;
296 307
 reg dtlb_miss_q = `FALSE;
297  
-wire dtlb_miss_int;
298 308
 reg [`LM32_WORD_RNG] dtlb_miss_addr;
299 309
 wire dtlb_data_valid;
300 310
 wire [`LM32_DTLB_LOOKUP_RANGE] dtlb_lookup;
@@ -313,15 +323,15 @@ assign kernel_mode = kernel_mode_reg;
313 323
 // Instantiations
314 324
 /////////////////////////////////////////////////////
315 325
 
316  
-
  326
+`ifdef CFG_MMU_ENABLED
317 327
 // DTLB instantiation
318  
-lm32_ram 
  328
+lm32_ram
319 329
   #(
320 330
     // ----- Parameters -------
321 331
     .data_width (vpfn_width + addr_dtlb_tag_width + 1),
322 332
     .address_width (addr_dtlb_index_width)
323 333
 // Modified for Milkymist: removed non-portable RAM parameters
324  
-    ) dtlb_data_ram 
  334
+    ) dtlb_data_ram
325 335
     (
326 336
      // ----- Inputs -------
327 337
      .read_clk (clk_i),
@@ -332,34 +342,25 @@ lm32_ram
332 342
      .write_address (dtlb_data_write_address),
333 343
      .enable_write (`TRUE),
334 344
      .write_enable (dtlb_write_port_enable),
335  
-     .write_data (dtlb_write_data),    
  345
+     .write_data (dtlb_write_data),
336 346
      // ----- Outputs -------
337 347
      .read_data (dtlb_read_data)
338 348
      );
339  
-
340  
-`ifdef CFG_VERBOSE_DISPLAY_ENABLED
341  
-always @(posedge clk_i)
342  
-begin
343  
-	if (dtlb_write_port_enable)
344  
-	begin
345  
-		$display("[DTLB data : %d] Writing 0x%08X to 0x%08X", $time, dtlb_write_data, dtlb_data_write_address);
346  
-	end
347  
-end
348 349
 `endif
349 350
 
350 351
    generate
351  
-      for (i = 0; i < associativity; i = i + 1)    
  352
+      for (i = 0; i < associativity; i = i + 1)
352 353
 	begin : memories
353 354
 	   // Way data
354 355
            if (`LM32_DC_DMEM_ADDR_WIDTH < 11)
355 356
              begin : data_memories
356  
-		lm32_ram 
  357
+		lm32_ram
357 358
 		  #(
358 359
 		    // ----- Parameters -------
359 360
 		    .data_width (32),
360 361
 		    .address_width (`LM32_DC_DMEM_ADDR_WIDTH)
361 362
 // Modified for Milkymist: removed non-portable RAM parameters
362  
-		    ) way_0_data_ram 
  363
+		    ) way_0_data_ram
363 364
 		    (
364 365
 		     // ----- Inputs -------
365 366
 		     .read_clk (clk_i),
@@ -370,22 +371,22 @@ end
370 371
 		     .write_address (dmem_write_address),
371 372
 		     .enable_write (write_port_enable),
372 373
 		     .write_enable (way_dmem_we[i]),
373  
-		     .write_data (dmem_write_data),    
  374
+		     .write_data (dmem_write_data),
374 375
 		     // ----- Outputs -------
375 376
 		     .read_data (way_data[i])
376  
-		     );    
  377
+		     );
377 378
              end
378 379
            else
379 380
              begin
380  
-		for (j = 0; j < 4; j = j + 1)    
  381
+		for (j = 0; j < 4; j = j + 1)
381 382
 		  begin : byte_memories
382  
-		     lm32_ram 
  383
+		     lm32_ram
383 384
 		       #(
384 385
 			 // ----- Parameters -------
385 386
 			 .data_width (8),
386 387
 			 .address_width (`LM32_DC_DMEM_ADDR_WIDTH)
387 388
 // Modified for Milkymist: removed non-portable RAM parameters
388  
-			 ) way_0_data_ram 
  389
+			 ) way_0_data_ram
389 390
 			 (
390 391
 			  // ----- Inputs -------
391 392
 			  .read_clk (clk_i),
@@ -396,21 +397,21 @@ end
396 397
 			  .write_address (dmem_write_address),
397 398
 			  .enable_write (write_port_enable),
398 399
 			  .write_enable (way_dmem_we[i] & (store_byte_select[j] | refill)),
399  
-			  .write_data (dmem_write_data[(j+1)*8-1:j*8]),    
  400
+			  .write_data (dmem_write_data[(j+1)*8-1:j*8]),
400 401
 			  // ----- Outputs -------
401 402
 			  .read_data (way_data[i][(j+1)*8-1:j*8])
402 403
 			  );
403 404
 		  end
404 405
              end
405  
-	   
  406
+
406 407
 	   // Way tags
407  
-	   lm32_ram 
  408
+	   lm32_ram
408 409
 	     #(
409 410
 	       // ----- Parameters -------
410 411
 	       .data_width (`LM32_DC_TAGS_WIDTH),
411 412
 	       .address_width (`LM32_DC_TMEM_ADDR_WIDTH)
412 413
 // Modified for Milkymist: removed non-portable RAM parameters
413  
-	       ) way_0_tag_ram 
  414
+	       ) way_0_tag_ram
414 415
 	       (
415 416
 		// ----- Inputs -------
416 417
 		.read_clk (clk_i),
@@ -426,37 +427,13 @@ end
426 427
 		.read_data ({way_tag[i], way_valid[i]})
427 428
 		);
428 429
 	end
429  
-      
  430
+
430 431
    endgenerate
431 432
 
432 433
 /////////////////////////////////////////////////////
433 434
 // Combinational logic
434 435
 /////////////////////////////////////////////////////
435 436
 
436  
-// CSR Write
437  
-always @(posedge clk_i `CFG_RESET_SENSITIVITY)
438  
-begin
439  
-	if (rst_i == `TRUE)
440  
-	begin
441  
-		dtlb_ctrl_csr_reg <= `LM32_WORD_WIDTH'd0;
442  
-		dtlb_update_vaddr_csr_reg <= `LM32_WORD_WIDTH'd0;
443  
-		dtlb_update_paddr_csr_reg <= `LM32_WORD_WIDTH'd0;
444  
-	end
445  
-	else
446  
-	begin
447  
-		if (csr_write_enable)
448  
-		begin
449  
-			case (csr)
450  
-			`LM32_CSR_TLB_CTRL:	if (csr_write_data[0]) dtlb_ctrl_csr_reg[31:1] <= csr_write_data[31:1];
451  
-			`LM32_CSR_TLB_VADDRESS: if (csr_write_data[0]) dtlb_update_vaddr_csr_reg[31:1] <= csr_write_data[31:1];
452  
-			`LM32_CSR_TLB_PADDRESS: if (csr_write_data[0]) dtlb_update_paddr_csr_reg[31:1] <= csr_write_data[31:1];
453  
-			endcase
454  
-		end
455  
-		dtlb_ctrl_csr_reg[0] <= 0;
456  
-		dtlb_update_vaddr_csr_reg[0] <= 0;
457  
-		dtlb_update_paddr_csr_reg[0] <= 0;
458  
-	end
459  
-end
460 437
 
461 438
 
462 439
 
@@ -465,25 +442,24 @@ generate
465 442
     for (i = 0; i < associativity; i = i + 1)
466 443
     begin : match
467 444
 
468  
-assign dtlb_read_tag = dtlb_read_data[`LM32_DTLB_TAG_RANGE];
469  
-assign dtlb_data_valid = dtlb_read_data[`LM32_DTLB_VALID_BIT];
470  
-assign dtlb_lookup = dtlb_read_data[`LM32_DTLB_LOOKUP_RANGE];
471  
-
472  
-assign way_match[i] = (kernel_mode_reg == `LM32_KERNEL_MODE) ?
473  
-		      ({way_tag[i], way_valid[i]} == {address_m[`LM32_DC_ADDR_TAG_RNG], `TRUE})
474  
-		      : ({way_tag[i], way_valid[i]} == {dtlb_lookup, `TRUE});
  445
+assign way_match[i] = 
  446
+`ifdef CFG_MMU_ENABLED
  447
+			(kernel_mode_reg == `LM32_USER_MODE) ?
  448
+			({way_tag[i], way_valid[i]} == {dtlb_lookup, `TRUE}) : 
  449
+`endif
  450
+		      ({way_tag[i], way_valid[i]} == {address_m[`LM32_DC_ADDR_TAG_RNG], `TRUE});
475 451
     end
476 452
 endgenerate
477 453
 
478  
-// Select data from way that matched the address being read     
  454
+// Select data from way that matched the address being read
479 455
 generate
480  
-    if (associativity == 1)    
  456
+    if (associativity == 1)
481 457
 	 begin : data_1
482 458
 assign load_data = way_data[0];
483 459
     end
484 460
     else if (associativity == 2)
485 461
 	 begin : data_2
486  
-assign load_data = way_match[0] ? way_data[0] : way_data[1]; 
  462
+assign load_data = way_match[0] ? way_data[0] : way_data[1];
487 463
     end
488 464
 endgenerate
489 465
 
@@ -518,45 +494,26 @@ end
518 494
 endgenerate
519 495
 
520 496
 // Compute address to use to index into the data memories
521  
-generate 
  497
+generate
522 498
      if (bytes_per_line > 4)
523  
-assign dmem_write_address = (refill == `TRUE) 
  499
+assign dmem_write_address = (refill == `TRUE)
524 500
                             ? {refill_address[`LM32_DC_ADDR_SET_RNG], refill_offset}
525 501
                             : address_m[`LM32_DC_ADDR_IDX_RNG];
526 502
     else
527  
-assign dmem_write_address = (refill == `TRUE) 
  503
+assign dmem_write_address = (refill == `TRUE)
528 504
                             ? refill_address[`LM32_DC_ADDR_SET_RNG]
529 505
                             : address_m[`LM32_DC_ADDR_IDX_RNG];
530 506
 endgenerate
531 507
 assign dmem_read_address = address_x[`LM32_DC_ADDR_IDX_RNG];
532  
-// Compute address to use to index into the tag memories   
  508
+// Compute address to use to index into the tag memories
533 509
 assign tmem_write_address = (flushing == `TRUE)
534 510
                             ? flush_set
535 511
                             : refill_address[`LM32_DC_ADDR_SET_RNG];
536 512
 assign tmem_read_address = address_x[`LM32_DC_ADDR_SET_RNG];
537 513
 
538  
-// Compute address to use to index into the DTLB data memory
539  
-
540  
-assign dtlb_data_read_address = address_x[`LM32_DTLB_IDX_RNG];
541  
-assign dtlb_tag_read_address = address_x[`LM32_DTLB_IDX_RNG];
542  
-
543  
-// tlb_update_address will receive data from a CSR register
544  
-assign dtlb_data_write_address = dtlb_update_vaddr_csr_reg[`LM32_DTLB_IDX_RNG];
545  
-
546  
-assign dtlb_data_read_port_enable = (stall_x == `FALSE) || !stall_m;
547  
-assign dtlb_write_port_enable = dtlb_updating || dtlb_flushing;
548  
-
549  
-assign physical_address = (kernel_mode_reg == `LM32_KERNEL_MODE)
550  
-			    ? address_m
551  
-			    : {dtlb_lookup, address_m[`LM32_PAGE_OFFSET_RNG]};
552  
-
553  
-assign dtlb_write_data = (dtlb_flushing == `TRUE)
554  
-			 ? {`FALSE, {addr_dtlb_tag_width{1'b0}}, {vpfn_width{1'b0}}}
555  
-			 : {`TRUE, {dtlb_update_vaddr_csr_reg[`LM32_DTLB_ADDR_TAG_RNG]}, dtlb_update_paddr_csr_reg[`LM32_DTLB_ADDRESS_PFN_RNG]};
556  
-
557 514
 // Compute signal to indicate when we are on the last refill accesses
558  
-generate 
559  
-    if (bytes_per_line > 4)                            
  515
+generate
  516
+    if (bytes_per_line > 4)
560 517
 assign last_refill = refill_offset == {addr_offset_width{1'b1}};
561 518
     else
562 519
 assign last_refill = `TRUE;
@@ -571,12 +528,12 @@ assign valid_store = (store_q_m == `TRUE) && (check == `TRUE);
571 528
 
572 529
 // Compute data and tag memory write enables
573 530
 generate
574  
-    if (associativity == 1) 
575  
-    begin : we_1     
  531
+    if (associativity == 1)
  532
+    begin : we_1
576 533
 assign way_dmem_we[0] = (refill_ready == `TRUE) || ((valid_store == `TRUE) && (way_match[0] == `TRUE));
577 534
 assign way_tmem_we[0] = (refill_ready == `TRUE) || (flushing == `TRUE);
578  
-    end 
579  
-    else 
  535
+    end
  536
+    else
580 537
     begin : we_2
581 538
 assign way_dmem_we[0] = ((refill_ready == `TRUE) && (refill_way_select[0] == `TRUE)) || ((valid_store == `TRUE) && (way_match[0] == `TRUE));
582 539
 assign way_dmem_we[1] = ((refill_ready == `TRUE) && (refill_way_select[1] == `TRUE)) || ((valid_store == `TRUE) && (way_match[1] == `TRUE));
@@ -595,35 +552,39 @@ assign check = state[1];
595 552
 assign refill = state[2];
596 553
 
597 554
 assign miss = (~(|way_match)) && (load_q_m == `TRUE) && (stall_m == `FALSE) && (~dtlb_miss);
598  
-assign stall_request = (check == `FALSE) || (dtlb_state == `LM32_TLB_STATE_FLUSH && kernel_mode_reg != `LM32_KERNEL_MODE);
599  
-                      
  555
+assign stall_request = (check == `FALSE) || (dtlb_state == `LM32_TLB_STATE_FLUSH 
  556
+`ifdef CFG_MMU_ENABLED
  557
+			&& kernel_mode_reg != `LM32_KERNEL_MODE
  558
+`endif
  559
+			);
  560
+
600 561
 /////////////////////////////////////////////////////
601 562
 // Sequential logic
602 563
 /////////////////////////////////////////////////////
603 564
 
604 565
 // Record way selected for replacement on a cache miss
605 566
 generate
606  
-    if (associativity >= 2) 
607  
-    begin : way_select      
  567
+    if (associativity >= 2)
  568
+    begin : way_select
608 569
 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
609 570
 begin
610 571
     if (rst_i == `TRUE)
611 572
         refill_way_select <= {{associativity-1{1'b0}}, 1'b1};
612 573
     else
613  
-    begin        
  574
+    begin
614 575
         if (refill_request == `TRUE)
615 576
             refill_way_select <= {refill_way_select[0], refill_way_select[1]};
616 577
     end
617 578
 end
618  
-    end 
619  
-endgenerate   
  579
+    end
  580
+endgenerate
620 581
 
621 582
 // Record whether we are currently refilling
622 583
 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
623 584
 begin
624 585
     if (rst_i == `TRUE)
625 586
         refilling <= `FALSE;
626  
-    else 
  587
+    else
627 588
         refilling <= refill;
628 589
 end
629 590
 
@@ -638,18 +599,18 @@ begin
638 599
         refill_address <= {`LM32_WORD_WIDTH{1'b0}};
639 600
         restart_request <= `FALSE;
640 601
     end
641  
-    else 
  602
+    else
642 603
     begin
643 604
         case (state)
644 605
 
645  
-        // Flush the cache 
  606
+        // Flush the cache
646 607
         `LM32_DC_STATE_FLUSH:
647 608
         begin
648 609
             if (flush_set == {`LM32_DC_TMEM_ADDR_WIDTH{1'b0}})
649 610
                 state <= `LM32_DC_STATE_CHECK;
650 611
             flush_set <= flush_set - 1'b1;
651 612
         end
652  
-        
  613
+
653 614
         // Check for cache misses
654 615
         `LM32_DC_STATE_CHECK:
655 616
         begin
@@ -658,7 +619,11 @@ begin
658 619
             if (miss == `TRUE)
659 620
             begin
660 621
                 refill_request <= `TRUE;
  622
+`ifdef CFG_MMU_ENABLED
661 623
                 refill_address <= physical_address;
  624
+`else
  625
+		refill_address <= address_m;		
  626
+`endif
662 627
                 state <= `LM32_DC_STATE_REFILL;
663 628
             end
664 629
             else if (dflush == `TRUE)
@@ -678,28 +643,103 @@ begin
678 643
                 end
679 644
             end
680 645
         end
681  
-        
682  
-        endcase        
  646
+
  647
+        endcase
  648
+    end
  649
+end
  650
+
  651
+
  652
+generate
  653
+    if (bytes_per_line > 4)
  654
+    begin
  655
+// Refill offset
  656
+always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  657
+begin
  658
+    if (rst_i == `TRUE)
  659
+        refill_offset <= {addr_offset_width{1'b0}};
  660
+    else
  661
+    begin
  662
+        case (state)
  663
+
  664
+        // Check for cache misses
  665
+        `LM32_DC_STATE_CHECK:
  666
+        begin
  667
+            if (miss == `TRUE)
  668
+                refill_offset <= {addr_offset_width{1'b0}};
  669
+        end
  670
+
  671
+        // Refill a cache line
  672
+        `LM32_DC_STATE_REFILL:
  673
+        begin
  674
+            if (refill_ready == `TRUE)
  675
+                refill_offset <= refill_offset + 1'b1;
  676
+        end
  677
+
  678
+        endcase
683 679
     end
684 680
 end
  681
+    end
  682
+endgenerate
  683
+
  684
+`endif
  685
+
  686
+`ifdef CFG_MMU_ENABLED
  687
+// Beginning of MMU specific code
  688
+
  689
+// Compute address to use to index into the DTLB data memory
  690
+
  691
+assign dtlb_data_read_address = address_x[`LM32_DTLB_IDX_RNG];
  692
+assign dtlb_tag_read_address = address_x[`LM32_DTLB_IDX_RNG];
  693
+
  694
+// tlb_update_address will receive data from a CSR register
  695
+assign dtlb_data_write_address = dtlb_update_vaddr_csr_reg[`LM32_DTLB_IDX_RNG];
  696
+
  697
+assign dtlb_data_read_port_enable = (stall_x == `FALSE) || !stall_m;
  698
+assign dtlb_write_port_enable = dtlb_updating || dtlb_flushing;
685 699
 
  700
+assign physical_address = (kernel_mode_reg == `LM32_KERNEL_MODE)
  701
+			    ? address_m
  702
+			    : {dtlb_lookup, address_m[`LM32_PAGE_OFFSET_RNG]};
  703
+
  704
+assign dtlb_write_data = (dtlb_flushing == `TRUE)
  705
+			 ? {`FALSE, {addr_dtlb_tag_width{1'b0}}, {vpfn_width{1'b0}}}
  706
+			 : {`TRUE, {dtlb_update_vaddr_csr_reg[`LM32_DTLB_ADDR_TAG_RNG]}, dtlb_update_paddr_csr_reg[`LM32_DTLB_ADDRESS_PFN_RNG]};
  707
+
  708
+assign dtlb_read_tag = dtlb_read_data[`LM32_DTLB_TAG_RANGE];
  709
+assign dtlb_data_valid = dtlb_read_data[`LM32_DTLB_VALID_BIT];
  710
+assign dtlb_lookup = dtlb_read_data[`LM32_DTLB_LOOKUP_RANGE];
  711
+assign csr_read_data = dtlb_miss_addr;
  712
+assign dtlb_miss = (kernel_mode_reg == `LM32_USER_MODE) && (load_q_m || store_q_m) && ~(dtlb_data_valid);
  713
+assign dtlb_miss_int = (dtlb_miss || dtlb_miss_q);
  714
+
  715
+assign switch_to_kernel_mode = (/*(kernel_mode_reg == `LM32_KERNEL_MODE) && */csr_write_enable && (csr == `LM32_CSR_TLB_CTRL) && csr_write_data[5:0] == {`LM32_TLB_CTRL_SWITCH_TO_KERNEL_MODE, 1'b1});
  716
+assign switch_to_user_mode = (/*(kernel_mode_reg == `LM32_KERNEL_MODE) && */csr_write_enable && (csr == `LM32_CSR_TLB_CTRL) && csr_write_data[5:0] == {`LM32_TLB_CTRL_SWITCH_TO_USER_MODE, 1'b1});
  717
+
  718
+// CSR Write
686 719
 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
687 720
 begin
688 721
 	if (rst_i == `TRUE)
689  
-		latest_store_tlb_lookup <= `LM32_WORD_WIDTH'd0;
  722
+	begin
  723
+		dtlb_ctrl_csr_reg <= `LM32_WORD_WIDTH'd0;
  724
+		dtlb_update_vaddr_csr_reg <= `LM32_WORD_WIDTH'd0;
  725
+		dtlb_update_paddr_csr_reg <= `LM32_WORD_WIDTH'd0;
  726
+	end
690 727
 	else
691 728
 	begin
692  
-		if (write_port_enable && (|way_dmem_we))
  729
+		if (csr_write_enable)
693 730
 		begin
694  
-			latest_store_tlb_lookup <= {dtlb_lookup, address_m[`LM32_PAGE_OFFSET_RNG]};
  731
+			case (csr)
  732
+			`LM32_CSR_TLB_CTRL:	if (csr_write_data[0]) dtlb_ctrl_csr_reg[31:1] <= csr_write_data[31:1];
  733
+			`LM32_CSR_TLB_VADDRESS: if (csr_write_data[0]) dtlb_update_vaddr_csr_reg[31:1] <= csr_write_data[31:1];
  734
+			`LM32_CSR_TLB_PADDRESS: if (csr_write_data[0]) dtlb_update_paddr_csr_reg[31:1] <= csr_write_data[31:1];
  735
+			endcase
695 736
 		end
  737
+		dtlb_ctrl_csr_reg[0] <= 0;
  738
+		dtlb_update_vaddr_csr_reg[0] <= 0;
  739
+		dtlb_update_paddr_csr_reg[0] <= 0;
696 740
 	end
697 741
 end
698 742
 
699  
-assign csr_read_data = dtlb_miss_addr;
700  
-
701  
-assign dtlb_miss = (kernel_mode_reg == `LM32_USER_MODE) && (load_q_m || store_q_m) && ~(dtlb_data_valid);
702  
-
703 743
 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
704 744
 begin
705 745
 	if (rst_i == `TRUE)
@@ -713,8 +753,6 @@ begin
713 753
 	end
714 754
 end
715 755
 
716  
-assign dtlb_miss_int = (dtlb_miss || dtlb_miss_q);
717  
-
718 756
 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
719 757
 begin
720 758
 	if (rst_i == `TRUE)
@@ -782,10 +820,6 @@ begin
782 820
 	end
783 821
 end
784 822
 
785  
-assign switch_to_kernel_mode = (/*(kernel_mode_reg == `LM32_KERNEL_MODE) && */csr_write_enable && (csr == `LM32_CSR_TLB_CTRL) && csr_write_data[5:0] == {`LM32_TLB_CTRL_SWITCH_TO_KERNEL_MODE, 1'b1});
786  
-assign switch_to_user_mode = (/*(kernel_mode_reg == `LM32_KERNEL_MODE) && */csr_write_enable && (csr == `LM32_CSR_TLB_CTRL) && csr_write_data[5:0] == {`LM32_TLB_CTRL_SWITCH_TO_USER_MODE, 1'b1});
787  
-
788  
-
789 823
 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
790 824
 begin
791 825
 	if (rst_i == `TRUE)
@@ -799,39 +833,16 @@ begin
799 833
 	end
800 834
 end
801 835
 
802  
-generate
803  
-    if (bytes_per_line > 4)
804  
-    begin
805  
-// Refill offset
806  
-always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  836
+`ifdef CFG_VERBOSE_DISPLAY_ENABLED
  837
+always @(posedge clk_i)
807 838
 begin
808  
-    if (rst_i == `TRUE)
809  
-        refill_offset <= {addr_offset_width{1'b0}};
810  
-    else 
811  
-    begin
812  
-        case (state)
813  
-        
814  
-        // Check for cache misses
815  
-        `LM32_DC_STATE_CHECK:
816  
-        begin
817  
-            if (miss == `TRUE)
818  
-                refill_offset <= {addr_offset_width{1'b0}};
819  
-        end
820  
-
821  
-        // Refill a cache line
822  
-        `LM32_DC_STATE_REFILL:
823  
-        begin
824  
-            if (refill_ready == `TRUE)
825  
-                refill_offset <= refill_offset + 1'b1;
826  
-        end
827  
-        
828  
-        endcase        
829  
-    end
  839
+	if (dtlb_write_port_enable)
  840
+	begin
  841
+		$display("[DTLB data : %d] Writing 0x%08X to 0x%08X", $time, dtlb_write_data, dtlb_data_write_address);
  842
+	end
830 843
 end
831  
-    end
832  
-endgenerate
833  
-
834  
-endmodule
  844
+`endif
835 845
 
836 846
 `endif
837 847
 
  848
+endmodule
328  lm32_icache.v
@@ -57,9 +57,6 @@
57 57
 `include "lm32_include.v"
58 58
 
59 59
 `ifdef CFG_ICACHE_ENABLED
60  
-`define LM32_KERNEL_MODE		 1
61  
-`define LM32_USER_MODE			 0
62  
-
63 60
 `define LM32_IC_ADDR_OFFSET_RNG          addr_offset_msb:addr_offset_lsb
64 61
 `define LM32_IC_ADDR_SET_RNG             addr_set_msb:addr_set_lsb
65 62
 `define LM32_IC_ADDR_TAG_RNG             addr_tag_msb:addr_tag_lsb
@@ -81,6 +78,8 @@
81 78
 `define LM32_IC_STATE_CHECK              4'b0100
82 79
 `define LM32_IC_STATE_REFILL             4'b1000
83 80
 
  81
+`ifdef CFG_MMU_ENABLED
  82
+
84 83
 `define LM32_ITLB_CTRL_FLUSH		 	5'h1
85 84
 `define LM32_ITLB_CTRL_UPDATE		 	5'h2
86 85
 `define LM32_TLB_CTRL_SWITCH_TO_KERNEL_MODE	5'h4
@@ -90,6 +89,11 @@
90 89
 `define LM32_TLB_STATE_CHECK		 2'b01
91 90
 `define LM32_TLB_STATE_FLUSH		 2'b10
92 91
 
  92
+`define LM32_KERNEL_MODE		 1
  93
+`define LM32_USER_MODE			 0
  94
+
  95
+`endif
  96
+
93 97
 /////////////////////////////////////////////////////
94 98
 // Module interface
95 99
 /////////////////////////////////////////////////////
@@ -111,24 +115,30 @@ module lm32_icache (
111 115
 `endif
112 116
     valid_d,
113 117
     branch_predict_taken_d,
  118
+`ifdef CFG_MMU_ENABLED
114 119
     csr,
115 120
     csr_write_data,
116 121
     csr_write_enable,
117 122
     exception_x,
118 123
     eret_q_x,
119 124
     exception_m,
  125
+`endif
120 126
     // ----- Outputs -----
121 127
     stall_request,
122 128
     restart_request,
123 129
     refill_request,
124 130
     refill_address,
  131
+`ifdef CFG_MMU_ENABLED
125 132
     physical_refill_address,
  133
+`endif
126 134
     refilling,
127  
-    inst,
  135
+`ifdef CFG_MMU_ENABLED
128 136
     itlb_miss_int,
129 137
     kernel_mode,
130 138
     pa,
131  
-    csr_read_data
  139
+    csr_read_data,
  140
+`endif
  141
+    inst
132 142
     );
133 143
 
134 144
 /////////////////////////////////////////////////////
@@ -141,6 +151,8 @@ parameter bytes_per_line = 16;                          // Number of bytes per c
141 151
 parameter base_address = 0;                             // Base address of cachable memory
142 152
 parameter limit = 0;                                    // Limit (highest address) of cachable memory
143 153
 
  154
+`ifdef CFG_MMU_ENABLED
  155
+
144 156
 parameter itlb_sets = 1024;				// Number of lines of ITLB
145 157
 parameter page_size = 4096;				// System page size
146 158
 
@@ -173,6 +185,7 @@ localparam addr_itlb_tag_msb = addr_itlb_tag_lsb + addr_itlb_tag_width - 1;
173 185
 `define LM32_ITLB_ADDR_TAG_RNG		addr_itlb_tag_msb:addr_itlb_tag_lsb
174 186
 `define LM32_ITLB_VALID_BIT		vpfn_width+addr_itlb_tag_width
175 187
 
  188
+`endif
176 189
 
177 190
 localparam addr_offset_width = clogb2(bytes_per_line)-1-2;
178 191
 localparam addr_set_width = clogb2(sets)-1;
@@ -208,20 +221,24 @@ input iflush;                                       // Flush the cache
208 221
 `ifdef CFG_IROM_ENABLED
209 222
 input select_f;                                     // Instruction in F stage is mapped through instruction cache
210 223
 `endif
211  
-   
  224
+
  225
+`ifdef CFG_MMU_ENABLED   
212 226
 input [`LM32_CSR_RNG] csr;				// CSR read/write index
213 227
 input [`LM32_WORD_RNG] csr_write_data;			// Data to write to specified CSR
214 228
 input csr_write_enable;					// CSR write enable
215 229
 input exception_x;					// An exception occured in the X stage
216 230
 input exception_m;
217 231
 input eret_q_x;
  232
+`endif
218 233
 
219 234
 /////////////////////////////////////////////////////
220 235
 // Outputs
221 236
 /////////////////////////////////////////////////////
222 237
 
  238
+`ifdef CFG_MMU_ENABLED
223 239
 output csr_read_data;
224 240
 wire [`LM32_WORD_RNG] csr_read_data;
  241
+`endif
225 242
 
226 243
 output stall_request;                               // Request to stall the pipeline
227 244
 wire   stall_request;
@@ -231,17 +248,23 @@ output refill_request;                              // Request to refill a cache
231 248
 wire   refill_request;
232 249
 output [`LM32_PC_RNG] refill_address;               // Base address of cache refill
233 250
 reg    [`LM32_PC_RNG] refill_address;               
  251
+`ifdef CFG_MMU_ENABLED
234 252
 output [`LM32_PC_RNG] physical_refill_address;
235 253
 reg    [`LM32_PC_RNG] physical_refill_address;
  254
+`endif
236 255
 output refilling;                                   // Indicates the instruction cache is currently refilling
237 256
 reg    refilling;
238 257
 output [`LM32_INSTRUCTION_RNG] inst;                // Instruction read from cache
239 258
 wire   [`LM32_INSTRUCTION_RNG] inst;
240 259
 
  260
+`ifdef CFG_MMU_ENABLED
241 261
 output kernel_mode;
242 262
 wire kernel_mode;
243  
-
244 263
 output itlb_miss_int;
  264
+wire itlb_miss_int;
  265
+output [`LM32_WORD_RNG] pa;
  266
+wire [`LM32_WORD_RNG] pa;
  267
+`endif
245 268
 
246 269
 /////////////////////////////////////////////////////
247 270
 // Internal nets and registers 
@@ -271,20 +294,15 @@ reg [`LM32_IC_ADDR_OFFSET_RNG] refill_offset;
271 294
 wire last_refill;
272 295
 reg [`LM32_IC_TMEM_ADDR_RNG] flush_set;
273 296
 
  297
+`ifdef CFG_MMU_ENABLED
  298
+
274 299
 wire [addr_itlb_index_width-1:0] itlb_data_read_address;
275 300
 wire [addr_itlb_index_width-1:0] itlb_data_write_address;
276 301
 wire itlb_data_read_port_enable;
277 302
 wire itlb_write_port_enable;
278 303
 wire [vpfn_width + addr_itlb_tag_width + 1 - 1:0] itlb_write_data; // +1 is for valid_bit
279 304
 wire [vpfn_width + addr_itlb_tag_width + 1 - 1:0] itlb_read_data; // +1 is for valid_bit
280  
-
281 305
 wire [`LM32_WORD_RNG] physical_address;
282  
-
283  
-wire [`LM32_WORD_RNG] pa;
284  
-output [`LM32_WORD_RNG] pa;
285  
-
286  
-assign pa = physical_address;
287  
-
288 306
 reg kernel_mode_reg = `LM32_KERNEL_MODE;
289 307
 wire switch_to_kernel_mode;
290 308
 wire switch_to_user_mode;
@@ -298,14 +316,16 @@ reg itlb_flushing;
298 316
 reg [addr_itlb_index_width-1:0] itlb_flush_set;
299 317
 wire itlb_miss;
300 318
 reg itlb_miss_q = `FALSE;
301  
-wire itlb_miss_int;
302 319
 reg [`LM32_WORD_RNG] itlb_miss_addr;
303 320
 wire itlb_data_valid;
304 321
 wire [`LM32_ITLB_LOOKUP_RANGE] itlb_lookup;
  322
+reg go_to_user_mode;
  323
+reg go_to_user_mode_2;
  324
+
  325
+`endif
305 326
 
306 327
 genvar i, j;
307 328
 
308  
-assign kernel_mode = kernel_mode_reg;
309 329
 
310 330
 /////////////////////////////////////////////////////
311 331
 // Functions
@@ -317,6 +337,7 @@ assign kernel_mode = kernel_mode_reg;
317 337
 // Instantiations
318 338
 /////////////////////////////////////////////////////
319 339
 
  340
+`ifdef CFG_MMU_ENABLED
320 341
 // ITLB instantiation
321 342
 lm32_ram
322 343
   #(
@@ -339,17 +360,9 @@ lm32_ram
339 360
      // ----- Outputs -------
340 361
      .read_data (itlb_read_data)
341 362
      );
342  
-
343  
-`ifdef CFG_VERBOSE_DISPLAY_ENABLED
344  
-always @(posedge clk_i)
345  
-begin
346  
-	if (itlb_write_port_enable)
347  
-	begin
348  
-		$display("[ITLB data : %d] Writing 0x%08X to 0x%08X", $time, itlb_write_data, itlb_data_write_address);
349  
-	end
350  
-end
351 363
 `endif
352 364
 
  365
+
353 366
    generate
354 367
       for (i = 0; i < associativity; i = i + 1)
355 368
 	begin : memories
@@ -407,45 +420,18 @@ endgenerate
407 420
 // Combinational logic
408 421
 /////////////////////////////////////////////////////
409 422
 
410  
-// CSR Write
411  
-always @(posedge clk_i `CFG_RESET_SENSITIVITY)
412  
-begin
413  
-	if (rst_i == `TRUE)
414  
-	begin
415  
-		itlb_ctrl_csr_reg <= `LM32_WORD_WIDTH'd0;
416  
-		itlb_update_vaddr_csr_reg <= `LM32_WORD_WIDTH'd0;
417  
-		itlb_update_paddr_csr_reg <= `LM32_WORD_WIDTH'd0;
418  
-	end
419  
-	else
420  
-	begin
421  
-		if (csr_write_enable)
422  
-		begin
423  
-			case (csr)
424  
-			`LM32_CSR_TLB_CTRL:	if (~csr_write_data[0]) itlb_ctrl_csr_reg[31:1] <= csr_write_data[31:1];
425  
-			`LM32_CSR_TLB_VADDRESS: if (~csr_write_data[0]) itlb_update_vaddr_csr_reg[31:1] <= csr_write_data[31:1];
426  
-			`LM32_CSR_TLB_PADDRESS: if (~csr_write_data[0]) itlb_update_paddr_csr_reg[31:1] <= csr_write_data[31:1];
427  
-			endcase
428  
-		end
429  
-		itlb_ctrl_csr_reg[0] <= 0;
430  
-		itlb_update_vaddr_csr_reg[0] <= 0;
431  
-		itlb_update_paddr_csr_reg[0] <= 0;
432  
-	end
433  
-end
434  
-
435 423
 // Compute which ways in the cache match the address address being read
436 424
 generate
437 425
     for (i = 0; i < associativity; i = i + 1)
438 426
     begin : match
439 427
 
440  
-assign itlb_read_tag = itlb_read_data[`LM32_ITLB_TAG_RANGE];
441  
-assign itlb_data_valid = itlb_read_data[`LM32_ITLB_VALID_BIT];
442  
-assign itlb_lookup = itlb_read_data[`LM32_ITLB_LOOKUP_RANGE];
443  
-
444  
-//assign way_match[i] = ({way_tag[i], way_valid[i]} == {address_f[`LM32_IC_ADDR_TAG_RNG], `TRUE});
445  
-assign way_match[i] = (kernel_mode_reg == `LM32_KERNEL_MODE) ?
446  
-		      ({way_tag[i], way_valid[i]} == {address_f[`LM32_IC_ADDR_TAG_RNG], `TRUE}) : 
  428
+assign way_match[i] =
  429
+`ifdef CFG_MMU_ENABLED
  430
+			(kernel_mode_reg == `LM32_USER_MODE) ?
  431
+			({way_tag[i], way_valid[i]} == {itlb_lookup, `TRUE }) : 
  432
+`endif
  433
+			({way_tag[i], way_valid[i]} == {address_f[`LM32_IC_ADDR_TAG_RNG], `TRUE});
447 434
 
448  
-		      ({way_tag[i], way_valid[i]} == {itlb_lookup, `TRUE });
449 435
     end
450 436
 endgenerate
451 437
 
@@ -477,24 +463,6 @@ assign tmem_write_address = flushing
477 463
                                 ? flush_set
478 464
                                 : refill_address[`LM32_IC_ADDR_SET_RNG];
479 465
 
480  
-// Compute address to use to index into the ITLB data memory
481  
-
482  
-assign itlb_data_read_address = address_a[`LM32_ITLB_IDX_RNG];
483  
-
484  
-// tlb_update_address will receive data from a CSR register
485  
-assign itlb_data_write_address = itlb_update_vaddr_csr_reg[`LM32_ITLB_IDX_RNG];
486  
-
487  
-assign itlb_data_read_port_enable = (stall_a == `FALSE) || !stall_f;
488  
-assign itlb_write_port_enable = itlb_updating || itlb_flushing;
489  
-
490  
-assign physical_address = (kernel_mode_reg == `LM32_KERNEL_MODE)
491  
-			    ? {address_f, 2'b0}
492  
-			    : {itlb_lookup, address_f[`LM32_PAGE_OFFSET_RNG+2], 2'b0};
493  
-
494  
-assign itlb_write_data = (itlb_flushing == `TRUE)
495  
-			 ? {`FALSE, {addr_itlb_tag_width{1'b0}}, {vpfn_width{1'b0}}}
496  
-			 : {`TRUE, {itlb_update_vaddr_csr_reg[`LM32_ITLB_ADDR_TAG_RNG]}, itlb_update_paddr_csr_reg[`LM32_ITLB_ADDRESS_PFN_RNG]};
497  
-
498 466
 
499 467
 // Compute signal to indicate when we are on the last refill accesses
500 468
 generate 
@@ -522,7 +490,11 @@ endgenerate
522 490
 
523 491
 // On the last refill cycle set the valid bit, for all other writes it should be cleared
524 492
 assign tmem_write_data[`LM32_IC_TAGS_VALID_RNG] = last_refill & !flushing;
  493
+`ifdef CFG_MMU_ENABLED
525 494
 assign tmem_write_data[`LM32_IC_TAGS_TAG_RNG] = physical_refill_address[`LM32_IC_ADDR_TAG_RNG];
  495
+`else
  496
+assign tmem_write_data[`LM32_IC_TAGS_TAG_RNG] = refill_address[`LM32_IC_ADDR_TAG_RNG];
  497
+`endif
526 498
 
527 499
 // Signals that indicate which state we are in
528 500
 assign flushing = |state[1:0];
@@ -571,6 +543,9 @@ begin
571 543
         state <= `LM32_IC_STATE_FLUSH_INIT;
572 544
         flush_set <= {`LM32_IC_TMEM_ADDR_WIDTH{1'b1}};
573 545
         refill_address <= {`LM32_PC_WIDTH{1'bx}};
  546
+`ifdef CFG_MMU_ENABLED
  547
+        physical_refill_address <= {`LM32_PC_WIDTH{1'bx}};
  548
+`endif
574 549
         restart_request <= `FALSE;
575 550
     end
576 551
     else 
@@ -606,13 +581,17 @@ begin
606 581
                 restart_request <= `FALSE;
607 582
             if (iflush == `TRUE)
608 583
             begin
  584
+`ifdef CFG_MMU_ENABLED
609 585
                 physical_refill_address <= physical_address[`LM32_PC_RNG];
  586
+`endif
610 587
                 refill_address <= address_f;
611 588
                 state <= `LM32_IC_STATE_FLUSH;
612 589
             end
613 590
             else if (miss == `TRUE)
614 591
             begin
  592
+`ifdef CFG_MMU_ENABLED
615 593
                 physical_refill_address <= physical_address[`LM32_PC_RNG];
  594
+`endif
616 595
                 refill_address <= address_f;
617 596
                 state <= `LM32_IC_STATE_REFILL;
618 597
             end
@@ -635,9 +614,110 @@ begin
635 614
     end
636 615
 end
637 616
 
638  
-assign csr_read_data = itlb_miss_addr;
  617
+generate 
  618
+    if (bytes_per_line > 4)
  619
+    begin
  620
+// Refill offset
  621
+always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  622
+begin
  623
+    if (rst_i == `TRUE)
  624
+        refill_offset <= {addr_offset_width{1'b0}};
  625
+    else 
  626
+    begin
  627
+        case (state)
  628
+        
  629
+        // Check for cache misses
  630
+        `LM32_IC_STATE_CHECK:
  631
+        begin            
  632
+            if (iflush == `TRUE)
  633
+                refill_offset <= {addr_offset_width{1'b0}};
  634
+            else if (miss == `TRUE)
  635
+                refill_offset <= {addr_offset_width{1'b0}};
  636
+        end
  637
+
  638
+        // Refill a cache line
  639
+        `LM32_IC_STATE_REFILL:
  640
+        begin            
  641
+            if (refill_ready == `TRUE)
  642
+                refill_offset <= refill_offset + 1'b1;
  643
+        end
  644
+
  645
+        endcase        
  646
+    end
  647
+end
  648
+    end
  649
+endgenerate
  650
+
  651
+`ifdef CFG_MMU_ENABLED
  652
+   
  653
+// Compute address to use to index into the ITLB data memory
  654
+assign itlb_data_read_address = address_a[`LM32_ITLB_IDX_RNG];
  655
+
  656
+// tlb_update_address will receive data from a CSR register
  657
+assign itlb_data_write_address = itlb_update_vaddr_csr_reg[`LM32_ITLB_IDX_RNG];
  658
+
  659
+assign itlb_data_read_port_enable = (stall_a == `FALSE) || !stall_f;
  660
+assign itlb_write_port_enable = itlb_updating || itlb_flushing;
  661
+
  662
+assign physical_address = (kernel_mode_reg == `LM32_KERNEL_MODE)
  663
+			    ? {address_f, 2'b0}
  664
+			    : {itlb_lookup, address_f[`LM32_PAGE_OFFSET_RNG+2], 2'b0};
639 665
 
  666
+assign itlb_write_data = (itlb_flushing == `TRUE)
  667
+			 ? {`FALSE, {addr_itlb_tag_width{1'b0}}, {vpfn_width{1'b0}}}
  668
+			 : {`TRUE, {itlb_update_vaddr_csr_reg[`LM32_ITLB_ADDR_TAG_RNG]}, itlb_update_paddr_csr_reg[`LM32_ITLB_ADDRESS_PFN_RNG]};
  669
+
  670
+assign pa = physical_address;
  671
+assign kernel_mode = kernel_mode_reg;
  672
+
  673
+assign switch_to_kernel_mode = (/*(kernel_mode_reg == `LM32_KERNEL_MODE) && */csr_write_enable && (csr == `LM32_CSR_TLB_CTRL) && csr_write_data[5:0] == {`LM32_TLB_CTRL_SWITCH_TO_KERNEL_MODE, 1'b0});
  674
+assign switch_to_user_mode = (/*(kernel_mode_reg == `LM32_KERNEL_MODE) && */csr_write_enable && (csr == `LM32_CSR_TLB_CTRL) && csr_write_data[5:0] == {`LM32_TLB_CTRL_SWITCH_TO_USER_MODE, 1'b0});
  675
+
  676
+assign csr_read_data = itlb_miss_addr;
640 677
 assign itlb_miss = (kernel_mode_reg == `LM32_USER_MODE) && (read_enable_f) && ~(itlb_data_valid);
  678
+assign itlb_miss_int = (itlb_miss || itlb_miss_q);
  679
+assign itlb_read_tag = itlb_read_data[`LM32_ITLB_TAG_RANGE];
  680
+assign itlb_data_valid = itlb_read_data[`LM32_ITLB_VALID_BIT];
  681
+assign itlb_lookup = itlb_read_data[`LM32_ITLB_LOOKUP_RANGE];
  682
+
  683
+`ifdef CFG_VERBOSE_DISPLAY_ENABLED
  684
+always @(posedge clk_i)
  685
+begin
  686
+	if (itlb_write_port_enable)
  687
+	begin
  688
+		$display("[ITLB data : %d] Writing 0x%08X to 0x%08X", $time, itlb_write_data, itlb_data_write_address);
  689
+	end
  690
+end
  691
+`endif
  692
+
  693
+always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  694
+begin
  695
+	if (rst_i == `TRUE)
  696
+		go_to_user_mode <= `FALSE;
  697
+	else
  698
+		go_to_user_mode <= (eret_q_x || switch_to_user_mode);
  699
+end
  700
+
  701
+always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  702
+begin
  703
+	if (rst_i == `TRUE)
  704
+		go_to_user_mode_2 <= `FALSE;
  705
+	else
  706
+		go_to_user_mode_2 <= go_to_user_mode;
  707
+end
  708
+
  709
+always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  710
+begin
  711
+	if (rst_i == `TRUE)
  712
+		kernel_mode_reg <= `LM32_KERNEL_MODE;
  713
+	else
  714
+	begin
  715
+		if (exception_x || switch_to_kernel_mode)
  716
+			kernel_mode_reg <= `LM32_KERNEL_MODE;
  717
+		else if (go_to_user_mode_2)
  718
+			kernel_mode_reg <= `LM32_USER_MODE;
  719
+	end
  720
+end
641 721
 
642 722
 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
643 723
 begin
@@ -652,7 +732,30 @@ begin
652 732
 	end
653 733
 end
654 734
 
655  
-assign itlb_miss_int = (itlb_miss || itlb_miss_q);
  735
+// CSR Write
  736
+always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  737
+begin
  738
+	if (rst_i == `TRUE)
  739
+	begin
  740
+		itlb_ctrl_csr_reg <= `LM32_WORD_WIDTH'd0;
  741
+		itlb_update_vaddr_csr_reg <= `LM32_WORD_WIDTH'd0;
  742
+		itlb_update_paddr_csr_reg <= `LM32_WORD_WIDTH'd0;
  743
+	end
  744
+	else
  745
+	begin
  746
+		if (csr_write_enable)
  747
+		begin
  748
+			case (csr)
  749
+			`LM32_CSR_TLB_CTRL:	if (~csr_write_data[0]) itlb_ctrl_csr_reg[31:1] <= csr_write_data[31:1];
  750
+			`LM32_CSR_TLB_VADDRESS: if (~csr_write_data[0]) itlb_update_vaddr_csr_reg[31:1] <= csr_write_data[31:1];
  751
+			`LM32_CSR_TLB_PADDRESS: if (~csr_write_data[0]) itlb_update_paddr_csr_reg[31:1] <= csr_write_data[31:1];
  752
+			endcase
  753
+		end
  754
+		itlb_ctrl_csr_reg[0] <= 0;
  755
+		itlb_update_vaddr_csr_reg[0] <= 0;
  756
+		itlb_update_paddr_csr_reg[0] <= 0;
  757
+	end
  758
+end
656 759
 
657 760
 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
658 761
 begin
@@ -733,75 +836,8 @@ begin
733 836
 	end
734 837
 end
735 838
 
736  
-assign switch_to_kernel_mode = (/*(kernel_mode_reg == `LM32_KERNEL_MODE) && */csr_write_enable && (csr == `LM32_CSR_TLB_CTRL) && csr_write_data[5:0] == {`LM32_TLB_CTRL_SWITCH_TO_KERNEL_MODE, 1'b0});
737  
-assign switch_to_user_mode = (/*(kernel_mode_reg == `LM32_KERNEL_MODE) && */csr_write_enable && (csr == `LM32_CSR_TLB_CTRL) && csr_write_data[5:0] == {`LM32_TLB_CTRL_SWITCH_TO_USER_MODE, 1'b0});
738  
-
739  
-reg go_to_user_mode;
740  
-reg go_to_user_mode_2;
741  
-
742  
-always @(posedge clk_i `CFG_RESET_SENSITIVITY)
743  
-begin
744  
-	if (rst_i == `TRUE)
745  
-		go_to_user_mode <= `FALSE;
746  
-	else
747  
-		go_to_user_mode <= (eret_q_x || switch_to_user_mode);
748  
-end
749  
-
750  
-always @(posedge clk_i `CFG_RESET_SENSITIVITY)
751  
-begin
752  
-	if (rst_i == `TRUE)
753  
-		go_to_user_mode_2 <= `FALSE;
754  
-	else
755  
-		go_to_user_mode_2 <= go_to_user_mode;
756  
-end
757  
-
758  
-always @(posedge clk_i `CFG_RESET_SENSITIVITY)
759  
-begin
760  
-	if (rst_i == `TRUE)
761  
-		kernel_mode_reg <= `LM32_KERNEL_MODE;
762  
-	else
763  
-	begin
764  
-		if (exception_x || switch_to_kernel_mode)
765  
-			kernel_mode_reg <= `LM32_KERNEL_MODE;
766  
-		else if (go_to_user_mode_2)
767  
-			kernel_mode_reg <= `LM32_USER_MODE;
768  
-	end
769  
-end
770  
-
771  
-generate 
772  
-    if (bytes_per_line > 4)
773  
-    begin
774  
-// Refill offset
775  
-always @(posedge clk_i `CFG_RESET_SENSITIVITY)
776  
-begin
777  
-    if (rst_i == `TRUE)
778  
-        refill_offset <= {addr_offset_width{1'b0}};
779  
-    else 
780  
-    begin
781  
-        case (state)
782  
-        
783  
-        // Check for cache misses
784  
-        `LM32_IC_STATE_CHECK:
785  
-        begin            
786  
-            if (iflush == `TRUE)
787  
-                refill_offset <= {addr_offset_width{1'b0}};
788  
-            else if (miss == `TRUE)
789  
-                refill_offset <= {addr_offset_width{1'b0}};
790  
-        end
791  
-
792  
-        // Refill a cache line
793  
-        `LM32_IC_STATE_REFILL:
794  
-        begin            
795  
-            if (refill_ready == `TRUE)
796  
-                refill_offset <= refill_offset + 1'b1;
797  
-        end
  839
+`endif
798 840
 
799  
-        endcase        
800  
-    end
801  
-end
802  
-    end
803  
-endgenerate
804  
-   
805 841
 endmodule
806 842
 
807 843
 `endif
38  lm32_instruction_unit.v
@@ -99,7 +99,9 @@ module lm32_instruction_unit (
99 99
     branch_target_x,
100 100
 `endif
101 101
     exception_m,
  102
+`ifdef CFG_MMU_ENABLED
102 103
     exception_x,
  104
+`endif
103 105
     branch_taken_m,
104 106
     branch_mispredict_taken_m,
105 107
     branch_target_m,
@@ -116,10 +118,12 @@ module lm32_instruction_unit (
116 118
     irom_address_xm,
117 119
     irom_we_xm,
118 120
 `endif
  121
+`ifdef CFG_MMU_ENABLED
119 122
     csr,
120 123
     csr_write_data,
121 124
     csr_write_enable,
122 125
     eret_q_x,
  126
+`endif
123 127
 `ifdef CFG_IWB_ENABLED
124 128
     // From Wishbone
125 129
     i_dat_i,
@@ -148,8 +152,10 @@ module lm32_instruction_unit (
148 152
 `ifdef CFG_IROM_ENABLED
149 153
     irom_data_m,
150 154
 `endif
  155
+`ifdef CFG_MMU_ENABLED
151 156
     itlb_miss,
152 157
     csr_read_data,
  158
+`endif
153 159
 `ifdef CFG_IWB_ENABLED
154 160
     // To Wishbone
155 161
     i_dat_o,
@@ -252,12 +258,13 @@ input [`LM32_BYTE_RNG] jtag_write_data;                 // JTAG wrirte data
252 258
 input [`LM32_WORD_RNG] jtag_address;                    // JTAG read/write address
253 259
 `endif
254 260
 
  261
+`ifdef CFG_MMU_ENABLED
255 262
 input exception_x;                                      // An exception occured in the X stage
256 263
 input eret_q_x;
257  
-
258 264
 input [`LM32_CSR_RNG] csr;				// CSR read/write index
259 265
 input [`LM32_WORD_RNG] csr_write_data;			// Data to write to specified CSR
260 266
 input csr_write_enable;					// CSR write enable
  267
+`endif
261 268
 
262 269
 /////////////////////////////////////////////////////
263 270
 // Outputs
@@ -341,11 +348,12 @@ wire   [`LM32_INSTRUCTION_RNG] instruction_f;
341 348
 output [`LM32_INSTRUCTION_RNG] instruction_d;           // D stage instruction to be decoded
342 349
 reg    [`LM32_INSTRUCTION_RNG] instruction_d;
343 350
 
  351
+`ifdef CFG_MMU_ENABLED
344 352
 output csr_read_data;
345 353
 wire [`LM32_WORD_RNG] csr_read_data;
346  
-
347 354
 output itlb_miss;
348 355
 wire itlb_miss;
  356
+`endif
349 357
 
350 358
 /////////////////////////////////////////////////////
351 359
 // Internal nets and registers 
@@ -360,7 +368,9 @@ reg [`LM32_PC_RNG] restart_address;                     // Address to restart fr
360 368
 `ifdef CFG_ICACHE_ENABLED
361 369
 wire icache_read_enable_f;                              // Indicates if instruction cache miss is valid
362 370
 wire [`LM32_PC_RNG] icache_refill_address;              // Address that caused cache miss
  371
+`ifdef CFG_MMU_ENABLED
363 372
 wire [`LM32_PC_RNG] icache_physical_refill_address;     // Physical address that caused cache miss
  373
+`endif
364 374
 reg icache_refill_ready;                                // Indicates when next word of refill data is ready to be written to cache
365 375
 reg [`LM32_INSTRUCTION_RNG] icache_refill_data;         // Next word of refill data, fetched from Wishbone
366 376
 wire [`LM32_INSTRUCTION_RNG] icache_data_f;             // Instruction fetched from instruction cache
@@ -394,8 +404,10 @@ reg jtag_access;                                        // Indicates if a JTAG W
394 404
 reg alternate_eba_taken;
395 405
 `endif
396 406
 
  407
+`ifdef CFG_MMU_ENABLED
397 408
 wire [`LM32_WORD_RNG] physical_address;
398 409
 wire kernel_mode;
  410
+`endif
399 411
 
400 412
 /////////////////////////////////////////////////////
401 413
 // Functions
@@ -478,24 +490,30 @@ lm32_icache #(
478 490
     .refill_ready           (icache_refill_ready),
479 491
     .refill_data            (icache_refill_data),
480 492
     .iflush                 (iflush),
  493
+`ifdef CFG_MMU_ENABLED
481 494
     .csr		    (csr),
482 495
     .csr_write_data	    (csr_write_data),
483 496
     .csr_write_enable	    (csr_write_enable),
484 497
     .exception_x	    (exception_x),
485 498
     .eret_q_x		    (eret_q_x),
486 499
     .exception_m	    (exception_m),
  500
+`endif
487 501
     // ----- Outputs -----
488 502
     .stall_request          (icache_stall_request),
489 503
     .restart_request        (icache_restart_request),
490 504
     .refill_request         (icache_refill_request),
491 505
     .refill_address         (icache_refill_address),
  506
+`ifdef CFG_MMU_ENABLED
492 507
     .physical_refill_address (icache_physical_refill_address),
  508
+`endif
493 509
     .refilling              (icache_refilling),
494  
-    .inst                   (icache_data_f),
  510
+`ifdef CFG_MMU_ENABLED
495 511
     .itlb_miss_int	    (itlb_miss),
496 512
     .kernel_mode	    (kernel_mode),
497 513
     .pa			    (physical_address),
498  
-    .csr_read_data	    (csr_read_data)
  514
+    .csr_read_data	    (csr_read_data),
  515
+`endif
  516
+    .inst                   (icache_data_f)
499 517
     );
500 518
 `endif
501 519
 
@@ -590,21 +608,33 @@ generate
590 608
 assign first_cycle_type = `LM32_CTYPE_END;
591 609
 assign next_cycle_type = `LM32_CTYPE_END;
592 610
 assign last_word = `TRUE;
  611
+`ifdef CFG_MMU_ENABLED
593 612
 assign first_address = icache_physical_refill_address;
  613
+`else
  614
+assign first_address = icache_refill_address;
  615
+`endif
594 616
     end
595 617
     8:
596 618
     begin
597 619
 assign first_cycle_type = `LM32_CTYPE_INCREMENTING;
598 620
 assign next_cycle_type = `LM32_CTYPE_END;
599 621
 assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 1'b1;
  622
+`ifdef CFG_MMU_ENABLED
600 623
 assign first_address = {icache_physical_refill_address[`LM32_PC_WIDTH+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
  624
+`else
  625
+assign first_address = {icache_refill_address[`LM32_PC_WIDTH+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
  626
+`endif
601 627
     end
602 628
     16:
603 629
     begin
604 630
 assign first_cycle_type = `LM32_CTYPE_INCREMENTING;
605 631
 assign next_cycle_type = i_adr_o[addr_offset_msb] == 1'b1 ? `LM32_CTYPE_END : `LM32_CTYPE_INCREMENTING;
606 632
 assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 2'b11;
  633
+`ifdef CFG_MMU_ENABLED
607 634
 assign first_address = {icache_physical_refill_address[`LM32_PC_WIDTH+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
  635
+`else
  636
+assign first_address = {icache_refill_address[`LM32_PC_WIDTH+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
  637
+`endif
608 638
     end
609 639
     endcase
610 640
 endgenerate
47  lm32_load_store_unit.v
@@ -99,10 +99,12 @@ module lm32_load_store_unit (
99 99
 `ifdef CFG_IROM_ENABLED
100 100
     irom_data_m,
101 101
 `endif
  102
+`ifdef CFG_MMU_ENABLED
102 103
     csr,
103 104
     csr_write_data,
104 105
     csr_write_enable,
105 106
     eret_q_x,
  107
+`endif
106 108
     // From Wishbone
107 109
     d_dat_i,
108 110
     d_ack_i,
@@ -124,8 +126,10 @@ module lm32_load_store_unit (
124