Skip to content
This repository

HTTPS clone URL

Subversion checkout URL

You can clone with HTTPS or Subversion.

Download ZIP
  • 2 commits
  • 7 files changed
  • 0 comments
  • 1 contributor
69  lm32_cpu.v
@@ -646,12 +646,12 @@ begin
646 646
 	begin
647 647
 		if (~stall_a)
648 648
 			$display("[%t] Addressing inst @ 0x%08X", $time, pc_a);
649  
-		if (~stall_f)
  649
+/*		if (~stall_f)
650 650
 			$display("[%t] Fetching   inst @ 0x%08X", $time, pc_f);
651 651
 		if (~stall_d)
652 652
 			$display("[%t] Decoding   inst @ 0x%08X", $time, pc_d);
653 653
 		if (~stall_x)
654  
-			$display("[%t] Executing  inst @ 0x%08X", $time, pc_x);
  654
+			$display("[%t] Executing  inst @ 0x%08X", $time, pc_x);*/
655 655
 	end
656 656
 end
657 657
 `endif
@@ -872,6 +872,7 @@ lm32_instruction_unit #(
872 872
     .csr_write_enable	    (csr_write_enable_q_x),
873 873
     .eret_q_x		    (eret_q_x),
874 874
     .csr_psw		    (lm32_csr_psw_reg),
  875
+    .q_x		    (q_x),
875 876
 `endif
876 877
 `ifdef CFG_IWB_ENABLED
877 878
     // From Wishbone
@@ -2197,6 +2198,7 @@ begin
2197 2198
     `LM32_CSR_CFG2: csr_read_data_x = cfg2;
2198 2199
     `LM32_CSR_TLB_VADDRESS: csr_read_data_x = load_store_csr_read_data_x;
2199 2200
     `LM32_CSR_TLB_PADDRESS: csr_read_data_x = instruction_csr_read_data_x;
  2201
+    `LM32_CSR_PSW:	csr_read_data_x = lm32_csr_psw_reg;
2200 2202
     default:        csr_read_data_x = {`LM32_WORD_WIDTH{1'bx}};
2201 2203
     endcase
2202 2204
 end
@@ -2210,15 +2212,62 @@ begin
2210 2212
 		lm32_csr_psw_reg <= `LM32_WORD_WIDTH'h0;
2211 2213
 	end
2212 2214
 	else
2213  
-	if (csr_write_enable_q_x)
2214 2215
 	begin
2215  
-		case (csr_x)
2216  
-		// operand_1_x is csr_write_data
2217  
-		`LM32_CSR_PSW:
2218  
-			lm32_csr_psw_reg <= operand_1_x;
2219  
-		`LM32_CSR_IE:
2220  
-			lm32_csr_psw_reg[2:0] <= operand_1_x[2:0];
2221  
-		endcase
  2216
+`ifdef CFG_DEBUG_ENABLED
  2217
+		if (non_debug_exception_q_w == `TRUE)
  2218
+		begin
  2219
+		    // Save and then clear ITLB and DTLB enable
  2220
+		    lm32_csr_psw_reg[`LM32_CSR_PSW_EITLBE] <= lm32_csr_psw_reg[`LM32_CSR_PSW_ITLBE];
  2221
+		    lm32_csr_psw_reg[`LM32_CSR_PSW_EDTLBE] <= lm32_csr_psw_reg[`LM32_CSR_PSW_DTLBE];
  2222
+		    lm32_csr_psw_reg[`LM32_CSR_PSW_ITLBE] <= `FALSE;
  2223
+		    lm32_csr_psw_reg[`LM32_CSR_PSW_DTLBE] <= `FALSE;
  2224
+		end
  2225
+		else if (debug_exception_q_w == `TRUE)
  2226
+		begin
  2227
+		    // Save and then clear TLB enable
  2228
+		    lm32_csr_psw_reg[`LM32_CSR_PSW_BITLBE] <= lm32_csr_psw_reg[`LM32_CSR_PSW_ITLBE];
  2229
+		    lm32_csr_psw_reg[`LM32_CSR_PSW_ITLBE] <= `FALSE;
  2230
+		    lm32_csr_psw_reg[`LM32_CSR_PSW_BDTLBE] <= lm32_csr_psw_reg[`LM32_CSR_PSW_DTLBE];
  2231
+		    lm32_csr_psw_reg[`LM32_CSR_PSW_DTLBE] <= `FALSE;
  2232
+		end
  2233
+`else
  2234
+		if (exception_q_w == `TRUE)
  2235
+		begin
  2236
+		    // Save and then clear ITLB and DTLB enable
  2237
+		    lm32_csr_psw_reg[`LM32_CSR_PSW_EITLBE] <= lm32_csr_psw_reg[`LM32_CSR_PSW_ITLBE];
  2238
+		    lm32_csr_psw_reg[`LM32_CSR_PSW_ITLBE] <= `FALSE;
  2239
+		    lm32_csr_psw_reg[`LM32_CSR_PSW_EDTLBE] <= lm32_csr_psw_reg[`LM32_CSR_PSW_DTLBE];
  2240
+		    lm32_csr_psw_reg[`LM32_CSR_PSW_DTLBE] <= `FALSE;
  2241
+		end
  2242
+`endif
  2243
+		else if (stall_x == `FALSE)
  2244
+		begin
  2245
+		    if (eret_q_x == `TRUE)
  2246
+		    begin
  2247
+			// Restore ITLB and DTLB enable
  2248
+			lm32_csr_psw_reg[`LM32_CSR_PSW_ITLBE] <= lm32_csr_psw_reg[`LM32_CSR_PSW_EITLBE];
  2249
+			lm32_csr_psw_reg[`LM32_CSR_PSW_DTLBE] <= lm32_csr_psw_reg[`LM32_CSR_PSW_EDTLBE];
  2250
+		    end
  2251
+`ifdef CFG_DEBUG_ENABLED
  2252
+		    else if (bret_q_x == `TRUE)
  2253
+		    begin
  2254
+			// Restore ITLB and DTLB enable
  2255
+			lm32_csr_psw_reg[`LM32_CSR_PSW_ITLBE] <= lm32_csr_psw_reg[`LM32_CSR_PSW_BITLBE];
  2256
+			lm32_csr_psw_reg[`LM32_CSR_PSW_DTLBE] <= lm32_csr_psw_reg[`LM32_CSR_PSW_BDTLBE];
  2257
+		    end
  2258
+`endif
  2259
+		    else if (csr_write_enable_q_x == `TRUE)
  2260
+		    begin
  2261
+			// Handle wcsr write
  2262
+			case (csr_x)
  2263
+			// operand_1_x is csr_write_data
  2264
+			`LM32_CSR_PSW:
  2265
+				lm32_csr_psw_reg <= operand_1_x;
  2266
+			`LM32_CSR_IE:
  2267
+				lm32_csr_psw_reg[2:0] <= operand_1_x[2:0];
  2268
+			endcase
  2269
+		    end
  2270
+		end
2222 2271
 	end
2223 2272
 end
2224 2273
 `endif
24  lm32_dcache.v
@@ -80,9 +80,6 @@
80 80
 `define LM32_TLB_CTRL_SWITCH_TO_USER_MODE	5'h8
81 81
 `define LM32_TLB_CTRL_INVALIDATE_ENTRY		5'h10
82 82
 
83  
-// FIXME: update the value
84  
-`define LM32_CSR_PSW_DTLBE		 `LM32_WORD_WIDTH'h01
85  
-
86 83
 `define LM32_TLB_STATE_CHECK		 2'b01
87 84
 `define LM32_TLB_STATE_FLUSH		 2'b10
88 85
 
@@ -783,33 +780,38 @@ begin
783 780
 			end
784 781
 			if (csr_write_enable && csr_write_data[0])
785 782
 			begin
  783
+				if (csr == `LM32_CSR_TLB_PADDRESS)
  784
+				begin
  785
+					$display("[ %t ] Updating a DTLB mapping 0x%08X -> 0x%08X", $time, dtlb_update_vaddr_csr_reg, dtlb_update_paddr_csr_reg);
  786
+					dtlb_updating <= 1;
  787
+				end
786 788
 				// FIXME : test for kernel mode is removed for testing purposes ONLY
787  
-				if (csr == `LM32_CSR_TLB_CTRL /*&& (kernel_mode_reg == `LM32_KERNEL_MODE)*/)
  789
+				else if (csr == `LM32_CSR_TLB_VADDRESS /*&& (kernel_mode_reg == `LM32_KERNEL_MODE)*/)
788 790
 				begin
  791
+					dtlb_updating <= 0;
789 792
 					case (csr_write_data[5:1])
790 793
 					`LM32_DTLB_CTRL_FLUSH:
791 794
 					begin
  795
+						$display("[ %t ] Flushing DTLB", $time);
792 796
 						dtlb_flushing <= 1;
793 797
 						dtlb_flush_set <= {addr_dtlb_index_width{1'b1}};
794 798
 						dtlb_state <= `LM32_TLB_STATE_FLUSH;
795  
-						dtlb_updating <= 0;
796  
-					end
797  
-
798  
-					`LM32_DTLB_CTRL_UPDATE:
799  
-					begin
800  
-						dtlb_updating <= 1;
801 799
 					end
802 800
 
803 801
 					`LM32_TLB_CTRL_INVALIDATE_ENTRY:
804 802
 					begin
  803
+						$display("[ %t ] Invalidating DTLB entry 0x%08X", $time, dtlb_update_vaddr_csr_reg);
805 804
 						dtlb_flushing <= 1;
806  
-						dtlb_flush_set <= dtlb_update_vaddr_csr_reg[`LM32_DTLB_IDX_RNG];
  805
+//						dtlb_flush_set <= dtlb_update_vaddr_csr_reg[`LM32_DTLB_IDX_RNG];
  806
+						dtlb_flush_set <= csr_write_data[`LM32_DTLB_IDX_RNG];
807 807
 						dtlb_updating <= 0;
808 808
 						dtlb_state <= `LM32_TLB_STATE_CHECK;
809 809
 					end
810 810
 
811 811
 					endcase
812 812
 				end
  813
+				else
  814
+					dtlb_updating <= 0;
813 815
 			end
814 816
 		end
815 817
 
98  lm32_icache.v
@@ -80,9 +80,6 @@
80 80
 
81 81
 `ifdef CFG_MMU_ENABLED
82 82
 
83  
-// FIXME: update the value
84  
-`define LM32_CSR_PSW_ITLBE		`LM32_WORD_WIDTH'h02
85  
-
86 83
 `define LM32_ITLB_CTRL_FLUSH		 	5'h1
87 84
 `define LM32_ITLB_CTRL_UPDATE		 	5'h2
88 85
 `define LM32_TLB_CTRL_SWITCH_TO_KERNEL_MODE	5'h4
@@ -109,9 +106,15 @@ module lm32_icache (
109 106
     stall_f,
110 107
 `ifdef CFG_MMU_ENABLED
111 108
     stall_x,
  109
+    stall_m,
112 110
 `endif
113 111
     address_a,
114 112
     address_f,
  113
+`ifdef CFG_MMU_ENABLED
  114
+    pc_x,
  115
+    pc_m,
  116
+    pc_w,
  117
+`endif
115 118
     read_enable_f,
116 119
     refill_ready,
117 120
     refill_data,
@@ -129,6 +132,7 @@ module lm32_icache (
129 132
     exception_x,
130 133
     eret_q_x,
131 134
     exception_m,
  135
+    q_x,
132 136
 `endif
133 137
     // ----- Outputs -----
134 138
     stall_request,
@@ -213,13 +217,19 @@ input rst_i;                                        // Reset
213 217
 
214 218
 input stall_a;                                      // Stall instruction in A stage
215 219
 input stall_f;                                      // Stall instruction in F stage
  220
+`ifdef CFG_MMU_ENABLED
216 221
 input stall_x;					    // Stall instruction in X stage
  222
+input stall_m;					    // Stall instruction in X stage
  223
+`endif
217 224
 
218 225
 input valid_d;                                      // Valid instruction in D stage
219 226
 input branch_predict_taken_d;                       // Instruction in D stage is a branch and is predicted taken
220 227
    
221 228
 input [`LM32_PC_RNG] address_a;                     // Address of instruction in A stage
222 229
 input [`LM32_PC_RNG] address_f;                     // Address of instruction in F stage
  230
+input [`LM32_PC_RNG] pc_x;			    // Address of instruction in X stage
  231
+input [`LM32_PC_RNG] pc_m;			    // Address of instruction in M stage
  232
+input [`LM32_PC_RNG] pc_w;			    // Address of instruction in W stage
223 233
 input read_enable_f;                                // Indicates if cache access is valid
224 234
 
225 235
 input refill_ready;                                 // Next word of refill data is ready
@@ -238,6 +248,7 @@ input [`LM32_WORD_RNG] csr_psw;
238 248
 input exception_x;					// An exception occured in the X stage
239 249
 input exception_m;
240 250
 input eret_q_x;
  251
+input q_x;
241 252
 `endif
242 253
 
243 254
 /////////////////////////////////////////////////////
@@ -681,7 +692,7 @@ assign pa = physical_address;
681 692
 assign kernel_mode = kernel_mode_reg;
682 693
 
683 694
 assign csr_read_data = {itlb_miss_addr, 2'b0};
684  
-assign itlb_miss = (itlb_enabled == `TRUE) && (read_enable_f) && ~(itlb_data_valid);
  695
+assign itlb_miss = (itlb_enabled == `TRUE) && (read_enable_f) && ~(itlb_data_valid) && (~itlb_miss_q);
685 696
 assign itlb_miss_int = (itlb_miss || itlb_miss_q);
686 697
 assign itlb_read_tag = itlb_read_data[`LM32_ITLB_TAG_RANGE];
687 698
 assign itlb_data_valid = itlb_read_data[`LM32_ITLB_VALID_BIT];
@@ -732,9 +743,9 @@ begin
732 743
 		itlb_miss_q <= `FALSE;
733 744
 	else
734 745
 	begin
735  
-		if (itlb_miss && ~itlb_miss_q)
  746
+		if (itlb_miss && ~itlb_miss_q && ~(exception_x == `TRUE && stall_m == `FALSE && stall_x == `FALSE && q_x == `TRUE))
736 747
 			itlb_miss_q <= `TRUE;
737  
-		else if (itlb_miss_q && exception_m)
  748
+		else if (itlb_miss_q && exception_x == `TRUE && stall_m == `FALSE && stall_x == `FALSE && q_x == `TRUE)
738 749
 			itlb_miss_q <= `FALSE;
739 750
 	end
740 751
 end
@@ -764,17 +775,57 @@ begin
764 775
 	end
765 776
 end
766 777
 
  778
+reg [`LM32_PC_RNG] pc_exception;
  779
+reg in_exception;
  780
+
767 781
 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
768 782
 begin
769 783
 	if (rst_i == `TRUE)
770 784
 	begin
771 785
 		itlb_enabled <= `FALSE;
  786
+		in_exception <= `FALSE;
  787
+		pc_exception <= {`LM32_PC_WIDTH{1'b0}};
772 788
 	end
773 789
 	else
774 790
 	begin
775 791
 		if (~stall_x)
776 792
 		begin
777  
-			itlb_enabled <= csr_psw[`LM32_CSR_PSW_ITLBE];
  793
+			if (eret_q_x)
  794
+			begin
  795
+//				$display("[%t] itlb_enabled <= 0x%08X upon eret", $time, csr_psw[`LM32_CSR_PSW_EITLBE]);
  796
+				itlb_enabled <= csr_psw[`LM32_CSR_PSW_EITLBE];
  797
+			end
  798
+			else if (exception_x || in_exception)
  799
+			begin
  800
+				if (~in_exception)
  801
+				begin
  802
+					if (~exception_m)
  803
+						in_exception <= 1;
  804
+					else
  805
+						in_exception <= 0;
  806
+				end
  807
+				else
  808
+				begin
  809
+					if (exception_m)
  810
+					begin
  811
+						$display("[%t] pc_exception <= 0x%08X", $time, pc_m);
  812
+						pc_exception <= pc_m;
  813
+					end
  814
+					if (pc_exception == pc_w)
  815
+					begin
  816
+						in_exception <= 0;
  817
+					end
  818
+				end
  819
+				$display("[%t] itlb_enabled <= 0x%08X upon exception", $time, 0);
  820
+				itlb_enabled <= 0;
  821
+			end
  822
+			else
  823
+			begin
  824
+				if (itlb_enabled != csr_psw[`LM32_CSR_PSW_ITLBE])
  825
+					$display("[%t] itlb_enabled <= 0x%08X", $time, csr_psw[`LM32_CSR_PSW_ITLBE]);
  826
+
  827
+				itlb_enabled <= csr_psw[`LM32_CSR_PSW_ITLBE];
  828
+			end
778 829
 		end
779 830
 	end
780 831
 end
@@ -805,39 +856,40 @@ begin
805 856
 			end
806 857
 			if (csr_write_enable && ~csr_write_data[0])
807 858
 			begin
  859
+				if (csr == `LM32_CSR_TLB_PADDRESS /*&& (kernel_mode_reg == `LM32_KERNEL_MODE)*/)
  860
+				begin
  861
+					$display("[%t] ITLB WCSR to PADDR with csr_write_data == 0x%08X", $time, csr_write_data);
  862
+//`ifdef CFG_VERBOSE_DISPLAY_ENABLED
  863
+					$display("it's an UPDATE at %t", $time);
  864
+//`endif
  865
+					itlb_updating <= 1;
  866
+				end
808 867
 				// FIXME : test for kernel mode is removed for testing purposes ONLY
809  
-				if (csr == `LM32_CSR_TLB_CTRL /*&& (kernel_mode_reg == `LM32_KERNEL_MODE)*/)
  868
+				else if (csr == `LM32_CSR_TLB_VADDRESS /*&& (kernel_mode_reg == `LM32_KERNEL_MODE)*/)
810 869
 				begin
811  
-`ifdef CFG_VERBOSE_DISPLAY_ENABLED
  870
+//`ifdef CFG_VERBOSE_DISPLAY_ENABLED
812 871
 					$display("ITLB WCSR at %t with csr_write_data == 0x%08X", $time, csr_write_data);
813  
-`endif
  872
+//`endif
814 873
 					case (csr_write_data[5:1])
815 874
 					`LM32_ITLB_CTRL_FLUSH:
816 875
 					begin
817  
-`ifdef CFG_VERBOSE_DISPLAY_ENABLED
  876
+//`ifdef CFG_VERBOSE_DISPLAY_ENABLED
818 877
 						$display("it's a FLUSH at %t", $time);
819  
-`endif
  878
+//`endif
820 879
 						itlb_flushing <= 1;
821 880
 						itlb_flush_set <= {addr_itlb_index_width{1'b1}};
822 881
 						itlb_state <= `LM32_TLB_STATE_FLUSH;
823 882
 						itlb_updating <= 0;
824 883
 					end
825 884
 
826  
-					`LM32_ITLB_CTRL_UPDATE:
827  
-					begin
828  
-`ifdef CFG_VERBOSE_DISPLAY_ENABLED
829  
-						$display("it's an UPDATE at %t", $time);
830  
-`endif
831  
-						itlb_updating <= 1;
832  
-					end
833  
-
834 885
 					`LM32_TLB_CTRL_INVALIDATE_ENTRY:
835 886
 					begin
836  
-`ifdef CFG_VERBOSE_DISPLAY_ENABLED
  887
+//`ifdef CFG_VERBOSE_DISPLAY_ENABLED
837 888
 						$display("it's an INVALIDATE ENTRY at %t", $time);
838  
-`endif
  889
+//`endif
839 890
 						itlb_flushing <= 1;
840  
-						itlb_flush_set <= itlb_update_vaddr_csr_reg[`LM32_ITLB_IDX_RNG];
  891
+//						itlb_flush_set <= itlb_update_vaddr_csr_reg[`LM32_ITLB_IDX_RNG];
  892
+						itlb_flush_set <= csr_write_data[`LM32_ITLB_IDX_RNG];
841 893
 						itlb_updating <= 0;
842 894
 						itlb_state <= `LM32_TLB_STATE_CHECK;
843 895
 					end
15  lm32_include.v
@@ -301,6 +301,21 @@
301 301
 `define LM32_CSR_TLB_DBG		`LM32_CSR_WIDTH'h1f
302 302
 `endif
303 303
 
  304
+`ifdef CFG_MMU_ENABLED
  305
+`define LM32_CSR_PSW_IE			`LM32_WORD_WIDTH'h0
  306
+`define LM32_CSR_PSW_EIE		`LM32_WORD_WIDTH'h1
  307
+`define LM32_CSR_PSW_BIE		`LM32_WORD_WIDTH'h2
  308
+`define LM32_CSR_PSW_ITLBE		`LM32_WORD_WIDTH'h3
  309
+`define LM32_CSR_PSW_EITLBE		`LM32_WORD_WIDTH'h4
  310
+`define LM32_CSR_PSW_BITLBE		`LM32_WORD_WIDTH'h5
  311
+`define LM32_CSR_PSW_DTLBE		`LM32_WORD_WIDTH'h6
  312
+`define LM32_CSR_PSW_EDTLBE		`LM32_WORD_WIDTH'h7
  313
+`define LM32_CSR_PSW_BDTLBE		`LM32_WORD_WIDTH'h8
  314
+`define LM32_CSR_PSW_USR		`LM32_WORD_WIDTH'h9
  315
+`define LM32_CSR_PSW_EUSR		`LM32_WORD_WIDTH'ha
  316
+`define LM32_CSR_PSW_BUSR		`LM32_WORD_WIDTH'hb
  317
+`endif
  318
+
304 319
 // Values for WPC CSR
305 320
 `define LM32_WPC_C_RNG                  1:0
306 321
 `define LM32_WPC_C_DISABLED             2'b00
9  lm32_instruction_unit.v
@@ -124,6 +124,7 @@ module lm32_instruction_unit (
124 124
     csr_write_data,
125 125
     csr_write_enable,
126 126
     eret_q_x,
  127
+    q_x,
127 128
 `endif
128 129
 `ifdef CFG_IWB_ENABLED
129 130
     // From Wishbone
@@ -265,6 +266,7 @@ input [`LM32_WORD_RNG] jtag_address;                    // JTAG read/write addre
265 266
 `ifdef CFG_MMU_ENABLED
266 267
 input exception_x;                                      // An exception occured in the X stage
267 268
 input eret_q_x;
  269
+input q_x;
268 270
 input [`LM32_CSR_RNG] csr;				// CSR read/write index
269 271
 input [`LM32_WORD_RNG] csr_write_data;			// Data to write to specified CSR
270 272
 input csr_write_enable;					// CSR write enable
@@ -492,11 +494,17 @@ lm32_icache #(
492 494
     .stall_f                (stall_f),
493 495
 `ifdef CFG_MMU_ENABLED
494 496
     .stall_x		    (stall_x),
  497
+    .stall_m		    (stall_m),
495 498
 `endif
496 499
     .branch_predict_taken_d (branch_predict_taken_d),
497 500
     .valid_d                (valid_d),
498 501
     .address_a              (pc_a),
499 502
     .address_f              (pc_f),
  503
+`ifdef CFG_MMU_ENABLED
  504
+    .pc_x		    (pc_x),
  505
+    .pc_m		    (pc_m),
  506
+    .pc_w		    (pc_w),
  507
+`endif
500 508
     .read_enable_f          (icache_read_enable_f),
501 509
     .refill_ready           (icache_refill_ready),
502 510
     .refill_data            (icache_refill_data),
@@ -509,6 +517,7 @@ lm32_icache #(
509 517
     .exception_x	    (exception_x),
510 518
     .eret_q_x		    (eret_q_x),
511 519
     .exception_m	    (exception_m),
  520
+    .q_x		    (q_x),
512 521
 `endif
513 522
     // ----- Outputs -----
514 523
     .stall_request          (icache_stall_request),
2  soc.v
@@ -347,7 +347,7 @@ begin
347 347
 	if ((cpu0__inst_D_ADR_O[31:18] == 14'd0 && cpu0_dbus_wishbone_ack_i) || (cpu0__inst_I_ADR_O[31:18] == 14'd0 && cpu0_ibus_wishbone_ack_i))
348 348
 	begin
349 349
 		sram0_wishbone_err_o <= 1'b1;
350  
-		$display("NULL pointer catched !");
  350
+		$display("[%t] NULL pointer catched !", $time);
351 351
 	end
352 352
 	else
353 353
 		sram0_wishbone_err_o <= 1'b0;
262  soc.wcfg
@@ -9,7 +9,7 @@
9 9
          </top_modules>
10 10
       </db_ref>
11 11
    </db_ref_list>
12  
-   <WVObjectSize size="144" />
  12
+   <WVObjectSize size="193" />
13 13
    <wvobject fp_name="/soc/memadr" type="array" db_ref_id="1">
14 14
       <obj_property name="ElementShortName">memadr[31:0]</obj_property>
15 15
       <obj_property name="ObjectShortName">memadr[31:0]</obj_property>
@@ -60,10 +60,6 @@
60 60
       <obj_property name="ElementShortName">stall_m</obj_property>
61 61
       <obj_property name="ObjectShortName">stall_m</obj_property>
62 62
    </wvobject>
63  
-   <wvobject fp_name="/soc/lm32/cpu/load_store_unit/d_adr_o_sampling" type="logic" db_ref_id="1">
64  
-      <obj_property name="ElementShortName">d_adr_o_sampling</obj_property>
65  
-      <obj_property name="ObjectShortName">d_adr_o_sampling</obj_property>
66  
-   </wvobject>
67 63
    <wvobject fp_name="/soc/lm32/cpu/load_store_unit/dcache/physical_address" type="array" db_ref_id="1">
68 64
       <obj_property name="ElementShortName">physical_address[31:0]</obj_property>
69 65
       <obj_property name="ObjectShortName">physical_address[31:0]</obj_property>
@@ -152,10 +148,6 @@
152 148
       <obj_property name="ElementShortName">way_match[0:0]</obj_property>
153 149
       <obj_property name="ObjectShortName">way_match[0:0]</obj_property>
154 150
    </wvobject>
155  
-   <wvobject fp_name="/soc/lm32/cpu/load_store_unit/dcache/miss" type="logic" db_ref_id="1">
156  
-      <obj_property name="ElementShortName">miss</obj_property>
157  
-      <obj_property name="ObjectShortName">miss</obj_property>
158  
-   </wvobject>
159 151
    <wvobject fp_name="/soc/lm32/cpu/load_store_unit/dcache/tmem_read_address" type="array" db_ref_id="1">
160 152
       <obj_property name="ElementShortName">tmem_read_address[7:0]</obj_property>
161 153
       <obj_property name="ObjectShortName">tmem_read_address[7:0]</obj_property>
@@ -205,15 +197,6 @@
205 197
       <obj_property name="ElementShortName">restart_request</obj_property>
206 198
       <obj_property name="ObjectShortName">restart_request</obj_property>
207 199
    </wvobject>
208  
-   <wvobject fp_name="/soc/lm32/cpu/load_store_unit/dcache/refill_request" type="logic" db_ref_id="1">
209  
-      <obj_property name="ElementShortName">refill_request</obj_property>
210  
-      <obj_property name="ObjectShortName">refill_request</obj_property>
211  
-   </wvobject>
212  
-   <wvobject fp_name="/soc/lm32/cpu/load_store_unit/dcache/refill_address" type="array" db_ref_id="1">
213  
-      <obj_property name="ElementShortName">refill_address[31:0]</obj_property>
214  
-      <obj_property name="ObjectShortName">refill_address[31:0]</obj_property>
215  
-      <obj_property name="Radix">HEXRADIX</obj_property>
216  
-   </wvobject>
217 200
    <wvobject fp_name="/soc/lm32/cpu/load_store_unit/dcache/refilling" type="logic" db_ref_id="1">
218 201
       <obj_property name="ElementShortName">refilling</obj_property>
219 202
       <obj_property name="ObjectShortName">refilling</obj_property>
@@ -472,11 +455,6 @@
472 455
       <obj_property name="ElementShortName">csr_write_enable</obj_property>
473 456
       <obj_property name="ObjectShortName">csr_write_enable</obj_property>
474 457
    </wvobject>
475  
-   <wvobject fp_name="/soc/lm32/cpu/load_store_unit/dcache/latest_store_tlb_lookup" type="array" db_ref_id="1">
476  
-      <obj_property name="ElementShortName">latest_store_tlb_lookup[31:0]</obj_property>
477  
-      <obj_property name="ObjectShortName">latest_store_tlb_lookup[31:0]</obj_property>
478  
-      <obj_property name="Radix">HEXRADIX</obj_property>
479  
-   </wvobject>
480 458
    <wvobject fp_name="/soc/lm32/cpu/load_store_unit/dcache/csr_read_data" type="array" db_ref_id="1">
481 459
       <obj_property name="ElementShortName">csr_read_data[31:0]</obj_property>
482 460
       <obj_property name="ObjectShortName">csr_read_data[31:0]</obj_property>
@@ -614,10 +592,6 @@
614 592
       <obj_property name="ElementShortName">kill_f</obj_property>
615 593
       <obj_property name="ObjectShortName">kill_f</obj_property>
616 594
    </wvobject>
617  
-   <wvobject fp_name="/soc/lm32/cpu/branch_taken_m" type="logic" db_ref_id="1">
618  
-      <obj_property name="ElementShortName">branch_taken_m</obj_property>
619  
-      <obj_property name="ObjectShortName">branch_taken_m</obj_property>
620  
-   </wvobject>
621 595
    <wvobject fp_name="/soc/lm32/cpu/valid_m" type="logic" db_ref_id="1">
622 596
       <obj_property name="ElementShortName">valid_m</obj_property>
623 597
       <obj_property name="ObjectShortName">valid_m</obj_property>
@@ -626,20 +600,242 @@
626 600
       <obj_property name="ElementShortName">condition_met_m</obj_property>
627 601
       <obj_property name="ObjectShortName">condition_met_m</obj_property>
628 602
    </wvobject>
  603
+   <wvobject fp_name="/soc/lm32/cpu/dcache_refill_request" type="logic" db_ref_id="1">
  604
+      <obj_property name="ElementShortName">dcache_refill_request</obj_property>
  605
+      <obj_property name="ObjectShortName">dcache_refill_request</obj_property>
  606
+   </wvobject>
  607
+   <wvobject fp_name="/soc/lm32/cpu/icache_refill_request" type="logic" db_ref_id="1">
  608
+      <obj_property name="ElementShortName">icache_refill_request</obj_property>
  609
+      <obj_property name="ObjectShortName">icache_refill_request</obj_property>
  610
+   </wvobject>
  611
+   <wvobject fp_name="/soc/lm32/cpu/lm32_csr_psw_reg" type="array" db_ref_id="1">
  612
+      <obj_property name="ElementShortName">lm32_csr_psw_reg[31:0]</obj_property>
  613
+      <obj_property name="ObjectShortName">lm32_csr_psw_reg[31:0]</obj_property>
  614
+      <obj_property name="Radix">HEXRADIX</obj_property>
  615
+   </wvobject>
  616
+   <wvobject fp_name="/soc/lm32/cpu/instruction_unit/icache/itlb_enabled" type="logic" db_ref_id="1">
  617
+      <obj_property name="ElementShortName">itlb_enabled</obj_property>
  618
+      <obj_property name="ObjectShortName">itlb_enabled</obj_property>
  619
+   </wvobject>
  620
+   <wvobject fp_name="/soc/lm32/cpu/instruction_unit/icache/itlb_miss_int" type="logic" db_ref_id="1">
  621
+      <obj_property name="ElementShortName">itlb_miss_int</obj_property>
  622
+      <obj_property name="ObjectShortName">itlb_miss_int</obj_property>
  623
+   </wvobject>
  624
+   <wvobject fp_name="/soc/lm32/cpu/instruction_unit/icache/itlb_miss" type="logic" db_ref_id="1">
  625
+      <obj_property name="ElementShortName">itlb_miss</obj_property>
  626
+      <obj_property name="ObjectShortName">itlb_miss</obj_property>
  627
+   </wvobject>
  628
+   <wvobject fp_name="/soc/lm32/cpu/instruction_unit/icache/itlb_miss_addr" type="array" db_ref_id="1">
  629
+      <obj_property name="ElementShortName">itlb_miss_addr[31:2]</obj_property>
  630
+      <obj_property name="ObjectShortName">itlb_miss_addr[31:2]</obj_property>
  631
+      <obj_property name="Radix">HEXRADIX</obj_property>
  632
+   </wvobject>
  633
+   <wvobject fp_name="/soc/lm32/cpu/instruction_unit/icache/itlb_miss_q" type="logic" db_ref_id="1">
  634
+      <obj_property name="ElementShortName">itlb_miss_q</obj_property>
  635
+      <obj_property name="ObjectShortName">itlb_miss_q</obj_property>
  636
+   </wvobject>
  637
+   <wvobject fp_name="/soc/lm32/cpu/instruction_unit/icache/in_exception" type="logic" db_ref_id="1">
  638
+      <obj_property name="ElementShortName">in_exception</obj_property>
  639
+      <obj_property name="ObjectShortName">in_exception</obj_property>
  640
+   </wvobject>
  641
+   <wvobject fp_name="/soc/lm32/cpu/instruction_unit/icache/itlb_flushing" type="logic" db_ref_id="1">
  642
+      <obj_property name="ElementShortName">itlb_flushing</obj_property>
  643
+      <obj_property name="ObjectShortName">itlb_flushing</obj_property>
  644
+   </wvobject>
  645
+   <wvobject fp_name="/soc/lm32/cpu/instruction_unit/icache/itlb_flush_set" type="array" db_ref_id="1">
  646
+      <obj_property name="ElementShortName">itlb_flush_set[9:0]</obj_property>
  647
+      <obj_property name="ObjectShortName">itlb_flush_set[9:0]</obj_property>
  648
+   </wvobject>
  649
+   <wvobject fp_name="/soc/lm32/cpu/instruction_unit/icache/itlb_state" type="array" db_ref_id="1">
  650
+      <obj_property name="ElementShortName">itlb_state[1:0]</obj_property>
  651
+      <obj_property name="ObjectShortName">itlb_state[1:0]</obj_property>
  652
+   </wvobject>
  653
+   <wvobject fp_name="/soc/lm32/cpu/instruction_unit/icache/itlb_update_paddr_csr_reg" type="array" db_ref_id="1">
  654
+      <obj_property name="ElementShortName">itlb_update_paddr_csr_reg[31:0]</obj_property>
  655
+      <obj_property name="ObjectShortName">itlb_update_paddr_csr_reg[31:0]</obj_property>
  656
+   </wvobject>
  657
+   <wvobject fp_name="/soc/lm32/cpu/instruction_unit/icache/itlb_update_set" type="array" db_ref_id="1">
  658
+      <obj_property name="ElementShortName">itlb_update_set[9:0]</obj_property>
  659
+      <obj_property name="ObjectShortName">itlb_update_set[9:0]</obj_property>
  660
+   </wvobject>
  661
+   <wvobject fp_name="/soc/lm32/cpu/instruction_unit/icache/itlb_update_vaddr_csr_reg" type="array" db_ref_id="1">
  662
+      <obj_property name="ElementShortName">itlb_update_vaddr_csr_reg[31:0]</obj_property>
  663
+      <obj_property name="ObjectShortName">itlb_update_vaddr_csr_reg[31:0]</obj_property>
  664
+   </wvobject>
  665
+   <wvobject fp_name="/soc/lm32/cpu/instruction_unit/icache/itlb_updating" type="logic" db_ref_id="1">
  666
+      <obj_property name="ElementShortName">itlb_updating</obj_property>
  667
+      <obj_property name="ObjectShortName">itlb_updating</obj_property>
  668
+   </wvobject>
  669
+   <wvobject fp_name="/soc/lm32/cpu/instruction_unit/icache/itlb_write_data" type="array" db_ref_id="1">
  670
+      <obj_property name="ElementShortName">itlb_write_data[30:0]</obj_property>
  671
+      <obj_property name="ObjectShortName">itlb_write_data[30:0]</obj_property>
  672
+   </wvobject>
  673
+   <wvobject fp_name="/soc/lm32/cpu/instruction_unit/icache/itlb_write_port_enable" type="logic" db_ref_id="1">
  674
+      <obj_property name="ElementShortName">itlb_write_port_enable</obj_property>
  675
+      <obj_property name="ObjectShortName">itlb_write_port_enable</obj_property>
  676
+   </wvobject>
  677
+   <wvobject fp_name="/soc/lm32/cpu/instruction_unit/icache/miss" type="logic" db_ref_id="1">
  678
+      <obj_property name="ElementShortName">miss</obj_property>
  679
+      <obj_property name="ObjectShortName">miss</obj_property>
  680
+   </wvobject>
  681
+   <wvobject fp_name="/soc/lm32/cpu/instruction_unit/icache/way_valid" type="array" db_ref_id="1">
  682
+      <obj_property name="ElementShortName">way_valid[0:0]</obj_property>
  683
+      <obj_property name="ObjectShortName">way_valid[0:0]</obj_property>
  684
+   </wvobject>
  685
+   <wvobject fp_name="/soc/lm32/cpu/instruction_unit/icache/way_match" type="array" db_ref_id="1">
  686
+      <obj_property name="ElementShortName">way_match[0:0]</obj_property>
  687
+      <obj_property name="ObjectShortName">way_match[0:0]</obj_property>
  688
+   </wvobject>
  689
+   <wvobject fp_name="/soc/lm32/cpu/instruction_unit/icache/refill_address" type="array" db_ref_id="1">
  690
+      <obj_property name="ElementShortName">refill_address[31:2]</obj_property>
  691
+      <obj_property name="ObjectShortName">refill_address[31:2]</obj_property>
  692
+   </wvobject>
  693
+   <wvobject fp_name="/soc/lm32/cpu/instruction_unit/icache/restart_request" type="logic" db_ref_id="1">
  694
+      <obj_property name="ElementShortName">restart_request</obj_property>
  695
+      <obj_property name="ObjectShortName">restart_request</obj_property>
  696
+   </wvobject>
  697
+   <wvobject fp_name="/soc/lm32/cpu/kill_d" type="logic" db_ref_id="1">
  698
+      <obj_property name="ElementShortName">kill_d</obj_property>
  699
+      <obj_property name="ObjectShortName">kill_d</obj_property>
  700
+   </wvobject>
  701
+   <wvobject fp_name="/soc/lm32/cpu/kill_f" type="logic" db_ref_id="1">
  702
+      <obj_property name="ElementShortName">kill_f</obj_property>
  703
+      <obj_property name="ObjectShortName">kill_f</obj_property>
  704
+   </wvobject>
  705
+   <wvobject fp_name="/soc/lm32/cpu/kill_m" type="logic" db_ref_id="1">
  706
+      <obj_property name="ElementShortName">kill_m</obj_property>
  707
+      <obj_property name="ObjectShortName">kill_m</obj_property>
  708
+   </wvobject>
  709
+   <wvobject fp_name="/soc/lm32/cpu/kill_w" type="logic" db_ref_id="1">
  710
+      <obj_property name="ElementShortName">kill_w</obj_property>
  711
+      <obj_property name="ObjectShortName">kill_w</obj_property>
  712
+   </wvobject>
  713
+   <wvobject fp_name="/soc/lm32/cpu/kill_x" type="logic" db_ref_id="1">
  714
+      <obj_property name="ElementShortName">kill_x</obj_property>
  715
+      <obj_property name="ObjectShortName">kill_x</obj_property>
  716
+   </wvobject>
  717
+   <wvobject fp_name="/soc/lm32/cpu/valid_a" type="logic" db_ref_id="1">
  718
+      <obj_property name="ElementShortName">valid_a</obj_property>
  719
+      <obj_property name="ObjectShortName">valid_a</obj_property>
  720
+   </wvobject>
  721
+   <wvobject fp_name="/soc/lm32/cpu/valid_d" type="logic" db_ref_id="1">
  722
+      <obj_property name="ElementShortName">valid_d</obj_property>
  723
+      <obj_property name="ObjectShortName">valid_d</obj_property>
  724
+   </wvobject>
  725
+   <wvobject fp_name="/soc/lm32/cpu/valid_f" type="logic" db_ref_id="1">
  726
+      <obj_property name="ElementShortName">valid_f</obj_property>
  727
+      <obj_property name="ObjectShortName">valid_f</obj_property>
  728
+   </wvobject>
  729
+   <wvobject fp_name="/soc/lm32/cpu/valid_m" type="logic" db_ref_id="1">
  730
+      <obj_property name="ElementShortName">valid_m</obj_property>
  731
+      <obj_property name="ObjectShortName">valid_m</obj_property>
  732
+   </wvobject>
  733
+   <wvobject fp_name="/soc/lm32/cpu/valid_w" type="logic" db_ref_id="1">
  734
+      <obj_property name="ElementShortName">valid_w</obj_property>
  735
+      <obj_property name="ObjectShortName">valid_w</obj_property>
  736
+   </wvobject>
  737
+   <wvobject fp_name="/soc/lm32/cpu/valid_x" type="logic" db_ref_id="1">
  738
+      <obj_property name="ElementShortName">valid_x</obj_property>
  739
+      <obj_property name="ObjectShortName">valid_x</obj_property>
  740
+   </wvobject>
  741
+   <wvobject fp_name="/soc/lm32/cpu/branch_d" type="logic" db_ref_id="1">
  742
+      <obj_property name="ElementShortName">branch_d</obj_property>
  743
+      <obj_property name="ObjectShortName">branch_d</obj_property>
  744
+   </wvobject>
  745
+   <wvobject fp_name="/soc/lm32/cpu/branch_flushX_m" type="logic" db_ref_id="1">
  746
+      <obj_property name="ElementShortName">branch_flushX_m</obj_property>
  747
+      <obj_property name="ObjectShortName">branch_flushX_m</obj_property>
  748
+   </wvobject>
  749
+   <wvobject fp_name="/soc/lm32/cpu/branch_m" type="logic" db_ref_id="1">
  750
+      <obj_property name="ElementShortName">branch_m</obj_property>
  751
+      <obj_property name="ObjectShortName">branch_m</obj_property>
  752
+   </wvobject>
  753
+   <wvobject fp_name="/soc/lm32/cpu/branch_mispredict_taken_m" type="logic" db_ref_id="1">
  754
+      <obj_property name="ElementShortName">branch_mispredict_taken_m</obj_property>
  755
+      <obj_property name="ObjectShortName">branch_mispredict_taken_m</obj_property>
  756
+   </wvobject>
  757
+   <wvobject fp_name="/soc/lm32/cpu/branch_predict_d" type="logic" db_ref_id="1">
  758
+      <obj_property name="ElementShortName">branch_predict_d</obj_property>
  759
+      <obj_property name="ObjectShortName">branch_predict_d</obj_property>
  760
+   </wvobject>
629 761
    <wvobject fp_name="/soc/lm32/cpu/branch_predict_m" type="logic" db_ref_id="1">
630 762
       <obj_property name="ElementShortName">branch_predict_m</obj_property>
631 763
       <obj_property name="ObjectShortName">branch_predict_m</obj_property>
632 764
    </wvobject>
  765
+   <wvobject fp_name="/soc/lm32/cpu/branch_predict_taken_d" type="logic" db_ref_id="1">
  766
+      <obj_property name="ElementShortName">branch_predict_taken_d</obj_property>
  767
+      <obj_property name="ObjectShortName">branch_predict_taken_d</obj_property>
  768
+   </wvobject>
633 769
    <wvobject fp_name="/soc/lm32/cpu/branch_predict_taken_m" type="logic" db_ref_id="1">
634 770
       <obj_property name="ElementShortName">branch_predict_taken_m</obj_property>
635 771
       <obj_property name="ObjectShortName">branch_predict_taken_m</obj_property>
636 772
    </wvobject>
637  
-   <wvobject fp_name="/soc/lm32/cpu/dcache_refill_request" type="logic" db_ref_id="1">
638  
-      <obj_property name="ElementShortName">dcache_refill_request</obj_property>
639  
-      <obj_property name="ObjectShortName">dcache_refill_request</obj_property>
  773
+   <wvobject fp_name="/soc/lm32/cpu/branch_predict_taken_x" type="logic" db_ref_id="1">
  774
+      <obj_property name="ElementShortName">branch_predict_taken_x</obj_property>
  775
+      <obj_property name="ObjectShortName">branch_predict_taken_x</obj_property>
640 776
    </wvobject>
641  
-   <wvobject fp_name="/soc/lm32/cpu/icache_refill_request" type="logic" db_ref_id="1">
642  
-      <obj_property name="ElementShortName">icache_refill_request</obj_property>
643  
-      <obj_property name="ObjectShortName">icache_refill_request</obj_property>
  777
+   <wvobject fp_name="/soc/lm32/cpu/branch_predict_x" type="logic" db_ref_id="1">
  778
+      <obj_property name="ElementShortName">branch_predict_x</obj_property>
  779
+      <obj_property name="ObjectShortName">branch_predict_x</obj_property>
  780
+   </wvobject>
  781
+   <wvobject fp_name="/soc/lm32/cpu/branch_reg_d" type="logic" db_ref_id="1">
  782
+      <obj_property name="ElementShortName">branch_reg_d</obj_property>
  783
+      <obj_property name="ObjectShortName">branch_reg_d</obj_property>
  784
+   </wvobject>
  785
+   <wvobject fp_name="/soc/lm32/cpu/branch_taken_m" type="logic" db_ref_id="1">
  786
+      <obj_property name="ElementShortName">branch_taken_m</obj_property>
  787
+      <obj_property name="ObjectShortName">branch_taken_m</obj_property>
  788
+   </wvobject>
  789
+   <wvobject fp_name="/soc/lm32/cpu/branch_target_d" type="array" db_ref_id="1">
  790
+      <obj_property name="ElementShortName">branch_target_d[31:2]</obj_property>
  791
+      <obj_property name="ObjectShortName">branch_target_d[31:2]</obj_property>
  792
+   </wvobject>
  793
+   <wvobject fp_name="/soc/lm32/cpu/branch_target_m" type="array" db_ref_id="1">
  794
+      <obj_property name="ElementShortName">branch_target_m[31:2]</obj_property>
  795
+      <obj_property name="ObjectShortName">branch_target_m[31:2]</obj_property>
  796
+   </wvobject>
  797
+   <wvobject fp_name="/soc/lm32/cpu/branch_target_x" type="array" db_ref_id="1">
  798
+      <obj_property name="ElementShortName">branch_target_x[31:2]</obj_property>
  799
+      <obj_property name="ObjectShortName">branch_target_x[31:2]</obj_property>
  800
+   </wvobject>
  801
+   <wvobject fp_name="/soc/lm32/cpu/branch_x" type="logic" db_ref_id="1">
  802
+      <obj_property name="ElementShortName">branch_x</obj_property>
  803
+      <obj_property name="ObjectShortName">branch_x</obj_property>
  804
+   </wvobject>
  805
+   <wvobject fp_name="/soc/lm32/cpu/instruction_unit/icache/read_enable_f" type="logic" db_ref_id="1">
  806
+      <obj_property name="ElementShortName">read_enable_f</obj_property>
  807
+      <obj_property name="ObjectShortName">read_enable_f</obj_property>
  808
+   </wvobject>
  809
+   <wvobject fp_name="/soc/lm32/cpu/instruction_unit/icache_physical_refill_address" type="array" db_ref_id="1">
  810
+      <obj_property name="ElementShortName">icache_physical_refill_address[31:2]</obj_property>
  811
+      <obj_property name="ObjectShortName">icache_physical_refill_address[31:2]</obj_property>
  812
+   </wvobject>
  813
+   <wvobject fp_name="/soc/lm32/cpu/instruction_unit/icache_refill_address" type="array" db_ref_id="1">
  814
+      <obj_property name="ElementShortName">icache_refill_address[31:2]</obj_property>
  815
+      <obj_property name="ObjectShortName">icache_refill_address[31:2]</obj_property>
  816
+   </wvobject>
  817
+   <wvobject fp_name="/soc/lm32/cpu/instruction_unit/icache_refill_data" type="array" db_ref_id="1">
  818
+      <obj_property name="ElementShortName">icache_refill_data[31:0]</obj_property>
  819
+      <obj_property name="ObjectShortName">icache_refill_data[31:0]</obj_property>
  820
+   </wvobject>
  821
+   <wvobject fp_name="/soc/lm32/cpu/instruction_unit/icache/physical_address" type="array" db_ref_id="1">
  822
+      <obj_property name="ElementShortName">physical_address[31:0]</obj_property>
  823
+      <obj_property name="ObjectShortName">physical_address[31:0]</obj_property>
  824
+   </wvobject>
  825
+   <wvobject fp_name="/soc/lm32/cpu/instruction_unit/icache/itlb_data_valid" type="logic" db_ref_id="1">
  826
+      <obj_property name="ElementShortName">itlb_data_valid</obj_property>
  827
+      <obj_property name="ObjectShortName">itlb_data_valid</obj_property>
  828
+   </wvobject>
  829
+   <wvobject fp_name="/soc/lm32/cpu/instruction_unit/icache/itlb_lookup" type="array" db_ref_id="1">
  830
+      <obj_property name="ElementShortName">itlb_lookup[19:0]</obj_property>
  831
+      <obj_property name="ObjectShortName">itlb_lookup[19:0]</obj_property>
  832
+   </wvobject>
  833
+   <wvobject fp_name="/soc/lm32/cpu/instruction_unit/icache/itlb_read_tag" type="logic" db_ref_id="1">
  834
+      <obj_property name="ElementShortName">itlb_read_tag</obj_property>
  835
+      <obj_property name="ObjectShortName">itlb_read_tag</obj_property>
  836
+   </wvobject>
  837
+   <wvobject fp_name="/soc/lm32/cpu/load_store_unit/dcache/dtlb_enabled" type="logic" db_ref_id="1">
  838
+      <obj_property name="ElementShortName">dtlb_enabled</obj_property>
  839
+      <obj_property name="ObjectShortName">dtlb_enabled</obj_property>
644 840
    </wvobject>
645 841
 </wave_config>

No commit comments for this range

Something went wrong with that request. Please try again.