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base fork: fallen/milkymist-mmu-simulation
base: a8f9d698cab2
...
head fork: fallen/milkymist-mmu-simulation
compare: 40e890bb4533
  • 2 commits
  • 5 files changed
  • 0 commit comments
  • 1 contributor
12 Makefile
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@@ -25,10 +25,20 @@ SOURCE =jtag_cores.v \
m1reset.v \
soc.v
+DURATION ?= 500000
+
PROJECT = soc.prj
all: simulation
+dmp: dmp.data
+
+dmp.data: soc ram.data
+ echo -e "restart \n init \n run $(DURATION) \n" | ./soc 2> /dev/null 1> dmp.data
+# Dump done, now removing useless first 10 lines
+ sed -ie '1,10d' dmp.data
+ @echo You can now run dmp on the dmp.data dump file to draw the pipeline
+
nogui: soc ram.data
./soc
@@ -50,4 +60,4 @@ clean:
cleanall: clean
$(MAKE) -C tools/h2a/ clean
-.PHONY: clean cleanall simulation all tools
+.PHONY: clean cleanall simulation all tools dmp nogui
18 lm32_cpu.v
View
@@ -633,6 +633,9 @@ reg [`LM32_WORD_RNG] csr_read_data_x; // Data read from CSRs
`ifdef CFG_PIPELINE_TRACES
wire [`LM32_PC_RNG] pc_a;
`endif
+`ifdef CFG_DRAW_ME_A_PIPELINE
+wire [`LM32_PC_RNG] pc_a;
+`endif
wire [`LM32_PC_RNG] pc_f; // PC of instruction in F stage
wire [`LM32_PC_RNG] pc_d; // PC of instruction in D stage
wire [`LM32_PC_RNG] pc_x; // PC of instruction in X stage
@@ -656,6 +659,21 @@ begin
end
`endif
+`ifdef CFG_DRAW_ME_A_PIPELINE
+always @(posedge clk_i `CFG_RESET_SENSITIVITY)
+begin
+ if (~rst_i)
+ begin
+ $display("[%d] PC_A 0x%08X", $time, pc_a);
+ $display("[%d] PC_F 0x%08X", $time, pc_f);
+ $display("[%d] PC_D 0x%08X", $time, pc_d);
+ $display("[%d] PC_X 0x%08X", $time, pc_x);
+ $display("[%d] PC_M 0x%08X", $time, pc_m);
+ $display("[%d] PC_W 0x%08X", $time, pc_w);
+ end
+end
+`endif
+
`ifdef CFG_TRACE_ENABLED
reg [`LM32_PC_RNG] pc_c; // PC of last commited instruction
`endif
8 lm32_dcache.v
View
@@ -793,7 +793,9 @@ begin
begin
if (csr == `LM32_CSR_TLB_PADDRESS)
begin
+`ifdef CFG_VERBOSE_DISPLAY_ENABLED
$display("[ %t ] Updating a DTLB mapping 0x%08X -> 0x%08X", $time, dtlb_update_vaddr_csr_reg, dtlb_update_paddr_csr_reg);
+`endif
dtlb_updating <= 1;
end
// FIXME : test for kernel mode is removed for testing purposes ONLY
@@ -803,7 +805,9 @@ begin
case (csr_write_data[5:1])
`LM32_DTLB_CTRL_FLUSH:
begin
+`ifdef CFG_VERBOSE_DISPLAY_ENABLED
$display("[ %t ] Flushing DTLB", $time);
+`endif
dtlb_flushing <= 1;
dtlb_flush_set <= {addr_dtlb_index_width{1'b1}};
dtlb_state <= `LM32_TLB_STATE_FLUSH;
@@ -811,7 +815,9 @@ begin
`LM32_TLB_CTRL_INVALIDATE_ENTRY:
begin
+`ifdef CFG_VERBOSE_DISPLAY_ENABLED
$display("[ %t ] Invalidating DTLB entry 0x%08X", $time, dtlb_update_vaddr_csr_reg);
+`endif
dtlb_flushing <= 1;
// dtlb_flush_set <= dtlb_update_vaddr_csr_reg[`LM32_DTLB_IDX_RNG];
dtlb_flush_set <= csr_write_data[`LM32_DTLB_IDX_RNG];
@@ -820,7 +826,9 @@ begin
end
default:
begin
+`ifdef CFG_VERBOSE_DISPLAY_ENABLED
$display("[ %t ] DTLB TLBVADDRESS stored 0x%08X", $time, csr_write_data);
+`endif
end
endcase
end
16 lm32_icache.v
View
@@ -868,24 +868,24 @@ begin
begin
if (csr == `LM32_CSR_TLB_PADDRESS /*&& (kernel_mode_reg == `LM32_KERNEL_MODE)*/)
begin
+`ifdef CFG_VERBOSE_DISPLAY_ENABLED
$display("[%t] ITLB WCSR to PADDR with csr_write_data == 0x%08X", $time, csr_write_data);
-//`ifdef CFG_VERBOSE_DISPLAY_ENABLED
$display("it's an UPDATE at %t", $time);
-//`endif
+`endif
itlb_updating <= 1;
end
// FIXME : test for kernel mode is removed for testing purposes ONLY
else if (csr == `LM32_CSR_TLB_VADDRESS /*&& (kernel_mode_reg == `LM32_KERNEL_MODE)*/)
begin
-//`ifdef CFG_VERBOSE_DISPLAY_ENABLED
+`ifdef CFG_VERBOSE_DISPLAY_ENABLED
$display("ITLB WCSR at %t with csr_write_data == 0x%08X", $time, csr_write_data);
-//`endif
+`endif
case (csr_write_data[5:1])
`LM32_ITLB_CTRL_FLUSH:
begin
-//`ifdef CFG_VERBOSE_DISPLAY_ENABLED
+`ifdef CFG_VERBOSE_DISPLAY_ENABLED
$display("it's a FLUSH at %t", $time);
-//`endif
+`endif
itlb_flushing <= 1;
itlb_flush_set <= {addr_itlb_index_width{1'b1}};
itlb_state <= `LM32_TLB_STATE_FLUSH;
@@ -894,9 +894,9 @@ begin
`LM32_TLB_CTRL_INVALIDATE_ENTRY:
begin
-//`ifdef CFG_VERBOSE_DISPLAY_ENABLED
+`ifdef CFG_VERBOSE_DISPLAY_ENABLED
$display("[ %t ] ITLB TLBVADDRESS INVALIDATE ENTRY 0x%08X command [vaddr_reg == 0x%08X]", $time, csr_write_data, itlb_update_vaddr_csr_reg);
-//`endif
+`endif
itlb_flushing <= 1;
// itlb_flush_set <= itlb_update_vaddr_csr_reg[`LM32_ITLB_IDX_RNG];
itlb_flush_set <= csr_write_data[`LM32_ITLB_IDX_RNG];
1  lm32_include.v
View
@@ -99,6 +99,7 @@
`define CFG_RANDOM_WISHBONE_LATENCY
//`define CFG_VERBOSE_DISPLAY_ENABLED
//`define CFG_PIPELINE_TRACES
+//`define CFG_DRAW_ME_A_PIPELINE
`define CFG_UART_ENABLED
// Enable MMU

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