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12  Makefile
@@ -25,10 +25,20 @@ SOURCE =jtag_cores.v \
25 25
 	m1reset.v \
26 26
 	soc.v
27 27
 
  28
+DURATION ?= 500000
  29
+
28 30
 PROJECT = soc.prj
29 31
 
30 32
 all: simulation
31 33
 
  34
+dmp: dmp.data
  35
+
  36
+dmp.data: soc ram.data
  37
+	echo -e "restart \n init \n run $(DURATION) \n" | ./soc 2> /dev/null 1> dmp.data
  38
+# Dump done, now removing useless first 10 lines
  39
+	sed -ie '1,10d' dmp.data
  40
+	@echo You can now run dmp on the dmp.data dump file to draw the pipeline
  41
+
32 42
 nogui: soc ram.data
33 43
 	./soc
34 44
 
@@ -50,4 +60,4 @@ clean:
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 cleanall: clean
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 	$(MAKE) -C tools/h2a/ clean
52 62
 
53  
-.PHONY: clean cleanall simulation all tools
  63
+.PHONY: clean cleanall simulation all tools dmp nogui
18  lm32_cpu.v
@@ -633,6 +633,9 @@ reg [`LM32_WORD_RNG] csr_read_data_x;           // Data read from CSRs
633 633
 `ifdef CFG_PIPELINE_TRACES
634 634
 wire [`LM32_PC_RNG] pc_a;
635 635
 `endif
  636
+`ifdef CFG_DRAW_ME_A_PIPELINE
  637
+wire [`LM32_PC_RNG] pc_a;
  638
+`endif
636 639
 wire [`LM32_PC_RNG] pc_f;                       // PC of instruction in F stage
637 640
 wire [`LM32_PC_RNG] pc_d;                       // PC of instruction in D stage
638 641
 wire [`LM32_PC_RNG] pc_x;                       // PC of instruction in X stage
@@ -656,6 +659,21 @@ begin
656 659
 end
657 660
 `endif
658 661
 
  662
+`ifdef CFG_DRAW_ME_A_PIPELINE
  663
+always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  664
+begin
  665
+	if (~rst_i)
  666
+	begin
  667
+		$display("[%d] PC_A 0x%08X", $time, pc_a);
  668
+		$display("[%d] PC_F 0x%08X", $time, pc_f);
  669
+		$display("[%d] PC_D 0x%08X", $time, pc_d);
  670
+		$display("[%d] PC_X 0x%08X", $time, pc_x);
  671
+		$display("[%d] PC_M 0x%08X", $time, pc_m);
  672
+		$display("[%d] PC_W 0x%08X", $time, pc_w);
  673
+	end
  674
+end
  675
+`endif
  676
+
659 677
 `ifdef CFG_TRACE_ENABLED
660 678
 reg [`LM32_PC_RNG] pc_c;                        // PC of last commited instruction
661 679
 `endif
8  lm32_dcache.v
@@ -793,7 +793,9 @@ begin
793 793
 			begin
794 794
 				if (csr == `LM32_CSR_TLB_PADDRESS)
795 795
 				begin
  796
+`ifdef CFG_VERBOSE_DISPLAY_ENABLED
796 797
 					$display("[ %t ] Updating a DTLB mapping 0x%08X -> 0x%08X", $time, dtlb_update_vaddr_csr_reg, dtlb_update_paddr_csr_reg);
  798
+`endif
797 799
 					dtlb_updating <= 1;
798 800
 				end
799 801
 				// FIXME : test for kernel mode is removed for testing purposes ONLY
@@ -803,7 +805,9 @@ begin
803 805
 					case (csr_write_data[5:1])
804 806
 					`LM32_DTLB_CTRL_FLUSH:
805 807
 					begin
  808
+`ifdef CFG_VERBOSE_DISPLAY_ENABLED
806 809
 						$display("[ %t ] Flushing DTLB", $time);
  810
+`endif
807 811
 						dtlb_flushing <= 1;
808 812
 						dtlb_flush_set <= {addr_dtlb_index_width{1'b1}};
809 813
 						dtlb_state <= `LM32_TLB_STATE_FLUSH;
@@ -811,7 +815,9 @@ begin
811 815
 
812 816
 					`LM32_TLB_CTRL_INVALIDATE_ENTRY:
813 817
 					begin
  818
+`ifdef CFG_VERBOSE_DISPLAY_ENABLED
814 819
 						$display("[ %t ] Invalidating DTLB entry 0x%08X", $time, dtlb_update_vaddr_csr_reg);
  820
+`endif
815 821
 						dtlb_flushing <= 1;
816 822
 //						dtlb_flush_set <= dtlb_update_vaddr_csr_reg[`LM32_DTLB_IDX_RNG];
817 823
 						dtlb_flush_set <= csr_write_data[`LM32_DTLB_IDX_RNG];
@@ -820,7 +826,9 @@ begin
820 826
 					end
821 827
 					default:
822 828
 					begin
  829
+`ifdef CFG_VERBOSE_DISPLAY_ENABLED
823 830
 						$display("[ %t ] DTLB TLBVADDRESS stored 0x%08X", $time, csr_write_data);
  831
+`endif
824 832
 					end
825 833
 					endcase
826 834
 				end
16  lm32_icache.v
@@ -868,24 +868,24 @@ begin
868 868
 			begin
869 869
 				if (csr == `LM32_CSR_TLB_PADDRESS /*&& (kernel_mode_reg == `LM32_KERNEL_MODE)*/)
870 870
 				begin
  871
+`ifdef CFG_VERBOSE_DISPLAY_ENABLED
871 872
 					$display("[%t] ITLB WCSR to PADDR with csr_write_data == 0x%08X", $time, csr_write_data);
872  
-//`ifdef CFG_VERBOSE_DISPLAY_ENABLED
873 873
 					$display("it's an UPDATE at %t", $time);
874  
-//`endif
  874
+`endif
875 875
 					itlb_updating <= 1;
876 876
 				end
877 877
 				// FIXME : test for kernel mode is removed for testing purposes ONLY
878 878
 				else if (csr == `LM32_CSR_TLB_VADDRESS /*&& (kernel_mode_reg == `LM32_KERNEL_MODE)*/)
879 879
 				begin
880  
-//`ifdef CFG_VERBOSE_DISPLAY_ENABLED
  880
+`ifdef CFG_VERBOSE_DISPLAY_ENABLED
881 881
 					$display("ITLB WCSR at %t with csr_write_data == 0x%08X", $time, csr_write_data);
882  
-//`endif
  882
+`endif
883 883
 					case (csr_write_data[5:1])
884 884
 					`LM32_ITLB_CTRL_FLUSH:
885 885
 					begin
886  
-//`ifdef CFG_VERBOSE_DISPLAY_ENABLED
  886
+`ifdef CFG_VERBOSE_DISPLAY_ENABLED
887 887
 						$display("it's a FLUSH at %t", $time);
888  
-//`endif
  888
+`endif
889 889
 						itlb_flushing <= 1;
890 890
 						itlb_flush_set <= {addr_itlb_index_width{1'b1}};
891 891
 						itlb_state <= `LM32_TLB_STATE_FLUSH;
@@ -894,9 +894,9 @@ begin
894 894
 
895 895
 					`LM32_TLB_CTRL_INVALIDATE_ENTRY:
896 896
 					begin
897  
-//`ifdef CFG_VERBOSE_DISPLAY_ENABLED
  897
+`ifdef CFG_VERBOSE_DISPLAY_ENABLED
898 898
 						$display("[ %t ] ITLB TLBVADDRESS INVALIDATE ENTRY 0x%08X command [vaddr_reg == 0x%08X]", $time, csr_write_data, itlb_update_vaddr_csr_reg);
899  
-//`endif
  899
+`endif
900 900
 						itlb_flushing <= 1;
901 901
 //						itlb_flush_set <= itlb_update_vaddr_csr_reg[`LM32_ITLB_IDX_RNG];
902 902
 						itlb_flush_set <= csr_write_data[`LM32_ITLB_IDX_RNG];
1  lm32_include.v
@@ -99,6 +99,7 @@
99 99
 `define CFG_RANDOM_WISHBONE_LATENCY
100 100
 //`define CFG_VERBOSE_DISPLAY_ENABLED
101 101
 //`define CFG_PIPELINE_TRACES
  102
+//`define CFG_DRAW_ME_A_PIPELINE
102 103
 `define CFG_UART_ENABLED
103 104
 
104 105
 // Enable MMU

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