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  • 5 files changed
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2  lm32_dcache.v
@@ -297,7 +297,7 @@ wire switch_to_kernel_mode;
297 297
 wire switch_to_user_mode;
298 298
 reg [`LM32_WORD_RNG] dtlb_update_vaddr_csr_reg = `LM32_WORD_WIDTH'd0;
299 299
 reg [`LM32_WORD_RNG] dtlb_update_paddr_csr_reg = `LM32_WORD_WIDTH'd0;
300  
-reg [1:0] dtlb_state = `LM32_TLB_STATE_CHECK;
  300
+reg [1:0] dtlb_state;
301 301
 reg [`LM32_WORD_RNG] dtlb_ctrl_csr_reg = `LM32_WORD_WIDTH'd0;
302 302
 reg dtlb_updating;
303 303
 reg [addr_dtlb_index_width-1:0] dtlb_update_set;
8  lm32_icache.v
@@ -308,7 +308,7 @@ wire switch_to_kernel_mode;
308 308
 wire switch_to_user_mode;
309 309
 reg [`LM32_WORD_RNG] itlb_update_vaddr_csr_reg = `LM32_WORD_WIDTH'd0;
310 310
 reg [`LM32_WORD_RNG] itlb_update_paddr_csr_reg = `LM32_WORD_WIDTH'd0;
311  
-reg [1:0] itlb_state = `LM32_TLB_STATE_CHECK;
  311
+reg [1:0] itlb_state;
312 312
 reg [`LM32_WORD_RNG] itlb_ctrl_csr_reg = `LM32_WORD_WIDTH'd0;
313 313
 reg itlb_updating;
314 314
 reg [addr_itlb_index_width-1:0] itlb_update_set;
@@ -542,9 +542,9 @@ begin
542 542
     begin
543 543
         state <= `LM32_IC_STATE_FLUSH_INIT;
544 544
         flush_set <= {`LM32_IC_TMEM_ADDR_WIDTH{1'b1}};
545  
-        refill_address <= {`LM32_PC_WIDTH{1'bx}};
  545
+        refill_address <= {`LM32_PC_WIDTH{1'b0}};
546 546
 `ifdef CFG_MMU_ENABLED
547  
-        physical_refill_address <= {`LM32_PC_WIDTH{1'bx}};
  547
+        physical_refill_address <= {`LM32_PC_WIDTH{1'b0}};
548 548
 `endif
549 549
         restart_request <= `FALSE;
550 550
     end
@@ -587,7 +587,7 @@ begin
587 587
                 refill_address <= address_f;
588 588
                 state <= `LM32_IC_STATE_FLUSH;
589 589
             end
590  
-            else if (miss == `TRUE)
  590
+            else if (miss == `TRUE && itlb_miss_int == `FALSE)
591 591
             begin
592 592
 `ifdef CFG_MMU_ENABLED
593 593
                 physical_refill_address <= physical_address[`LM32_PC_RNG];
2  lm32_include.v
@@ -96,7 +96,7 @@
96 96
 //`define CFG_WATCHPOINTS 32'h4
97 97
 //`define CFG_EXTERNAL_BREAK_ENABLED
98 98
 //`define CFG_GDBSTUB_ENABLED
99  
-//`define CFG_RANDOM_WISHBONE_LATENCY
  99
+`define CFG_RANDOM_WISHBONE_LATENCY
100 100
 //`define CFG_VERBOSE_DISPLAY_ENABLED
101 101
 `define CFG_UART_ENABLED
102 102
 
11  m1reset.v
@@ -19,21 +19,22 @@ module m1reset(
19 19
 	input sys_clk,
20 20
 	input trigger_reset,
21 21
 	
22  
-	output reg sys_rst,
  22
+	output sys_rst,
23 23
 	output ac97_rst_n,
24 24
 	output videoin_rst_n,
25 25
 	output flash_rst_n
26 26
 );
27 27
 
28  
-reg [19:0] rst_debounce;
29  
-initial rst_debounce <= 20'h02;
30  
-initial sys_rst <= 1'b1;
  28
+reg [19:0] rst_debounce = 20'h02;
  29
+reg sys_rst_reg = 1'b1;
  30
+assign sys_rst = sys_rst_reg;
  31
+
31 32
 always @(posedge sys_clk) begin
32 33
 	if(trigger_reset)
33 34
 		rst_debounce <= 20'hFFFFF;
34 35
 	else if(rst_debounce != 20'd0)
35 36
 		rst_debounce <= rst_debounce - 20'd1;
36  
-	sys_rst <= rst_debounce != 20'd0;
  37
+	sys_rst_reg <= rst_debounce != 20'd0;
37 38
 end
38 39
 
39 40
 assign ac97_rst_n = ~sys_rst;
9  soc.v
@@ -3,11 +3,6 @@
3 3
 `include "lm32_include.v"
4 4
 
5 5
 module soc(
6  
-	input clkfx_sys_clkin,
7  
-	output reset0_ac97_rst_n,
8  
-	output reset0_flash_rst_n,
9  
-	input reset0_trigger_reset,
10  
-	output reset0_videoin_rst_n
11 6
 );
12 7
 
13 8
 reg clkfx_sys_clkout;
@@ -302,6 +297,10 @@ always @(posedge clkfx_sys_clkout) begin
302 297
 	end
303 298
 end
304 299
 
  300
+wire reset0_trigger_reset;
  301
+
  302
+assign reset0_trigger_reset = 1'b0;
  303
+
305 304
 m1reset m1reset(
306 305
 	.trigger_reset(reset0_trigger_reset),
307 306
 	.flash_rst_n(reset0_flash_rst_n),

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