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base fork: fallen/milkymist-mmu-simulation
base: aad21edf52a6
...
head fork: fallen/milkymist-mmu-simulation
compare: c5461df4f851
  • 2 commits
  • 5 files changed
  • 0 commit comments
  • 1 contributor
2  lm32_dcache.v
View
@@ -297,7 +297,7 @@ wire switch_to_kernel_mode;
wire switch_to_user_mode;
reg [`LM32_WORD_RNG] dtlb_update_vaddr_csr_reg = `LM32_WORD_WIDTH'd0;
reg [`LM32_WORD_RNG] dtlb_update_paddr_csr_reg = `LM32_WORD_WIDTH'd0;
-reg [1:0] dtlb_state = `LM32_TLB_STATE_CHECK;
+reg [1:0] dtlb_state;
reg [`LM32_WORD_RNG] dtlb_ctrl_csr_reg = `LM32_WORD_WIDTH'd0;
reg dtlb_updating;
reg [addr_dtlb_index_width-1:0] dtlb_update_set;
8 lm32_icache.v
View
@@ -308,7 +308,7 @@ wire switch_to_kernel_mode;
wire switch_to_user_mode;
reg [`LM32_WORD_RNG] itlb_update_vaddr_csr_reg = `LM32_WORD_WIDTH'd0;
reg [`LM32_WORD_RNG] itlb_update_paddr_csr_reg = `LM32_WORD_WIDTH'd0;
-reg [1:0] itlb_state = `LM32_TLB_STATE_CHECK;
+reg [1:0] itlb_state;
reg [`LM32_WORD_RNG] itlb_ctrl_csr_reg = `LM32_WORD_WIDTH'd0;
reg itlb_updating;
reg [addr_itlb_index_width-1:0] itlb_update_set;
@@ -542,9 +542,9 @@ begin
begin
state <= `LM32_IC_STATE_FLUSH_INIT;
flush_set <= {`LM32_IC_TMEM_ADDR_WIDTH{1'b1}};
- refill_address <= {`LM32_PC_WIDTH{1'bx}};
+ refill_address <= {`LM32_PC_WIDTH{1'b0}};
`ifdef CFG_MMU_ENABLED
- physical_refill_address <= {`LM32_PC_WIDTH{1'bx}};
+ physical_refill_address <= {`LM32_PC_WIDTH{1'b0}};
`endif
restart_request <= `FALSE;
end
@@ -587,7 +587,7 @@ begin
refill_address <= address_f;
state <= `LM32_IC_STATE_FLUSH;
end
- else if (miss == `TRUE)
+ else if (miss == `TRUE && itlb_miss_int == `FALSE)
begin
`ifdef CFG_MMU_ENABLED
physical_refill_address <= physical_address[`LM32_PC_RNG];
2  lm32_include.v
View
@@ -96,7 +96,7 @@
//`define CFG_WATCHPOINTS 32'h4
//`define CFG_EXTERNAL_BREAK_ENABLED
//`define CFG_GDBSTUB_ENABLED
-//`define CFG_RANDOM_WISHBONE_LATENCY
+`define CFG_RANDOM_WISHBONE_LATENCY
//`define CFG_VERBOSE_DISPLAY_ENABLED
`define CFG_UART_ENABLED
11 m1reset.v
View
@@ -19,21 +19,22 @@ module m1reset(
input sys_clk,
input trigger_reset,
- output reg sys_rst,
+ output sys_rst,
output ac97_rst_n,
output videoin_rst_n,
output flash_rst_n
);
-reg [19:0] rst_debounce;
-initial rst_debounce <= 20'h02;
-initial sys_rst <= 1'b1;
+reg [19:0] rst_debounce = 20'h02;
+reg sys_rst_reg = 1'b1;
+assign sys_rst = sys_rst_reg;
+
always @(posedge sys_clk) begin
if(trigger_reset)
rst_debounce <= 20'hFFFFF;
else if(rst_debounce != 20'd0)
rst_debounce <= rst_debounce - 20'd1;
- sys_rst <= rst_debounce != 20'd0;
+ sys_rst_reg <= rst_debounce != 20'd0;
end
assign ac97_rst_n = ~sys_rst;
9 soc.v
View
@@ -3,11 +3,6 @@
`include "lm32_include.v"
module soc(
- input clkfx_sys_clkin,
- output reset0_ac97_rst_n,
- output reset0_flash_rst_n,
- input reset0_trigger_reset,
- output reset0_videoin_rst_n
);
reg clkfx_sys_clkout;
@@ -302,6 +297,10 @@ always @(posedge clkfx_sys_clkout) begin
end
end
+wire reset0_trigger_reset;
+
+assign reset0_trigger_reset = 1'b0;
+
m1reset m1reset(
.trigger_reset(reset0_trigger_reset),
.flash_rst_n(reset0_flash_rst_n),

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