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25  lm32_cpu.v
@@ -781,6 +781,7 @@ reg ext_break_r;
781 781
 `ifdef CFG_MMU_ENABLED
782 782
 wire dtlb_miss_exception;
783 783
 wire itlb_miss_exception;
  784
+reg [`LM32_WORD_RNG] lm32_csr_psw_reg;
784 785
 `endif
785 786
 
786 787
 /////////////////////////////////////////////////////
@@ -849,6 +850,7 @@ lm32_instruction_unit #(
849 850
     .csr_write_data	    (operand_1_x),
850 851
     .csr_write_enable	    (csr_write_enable_q_x),
851 852
     .eret_q_x		    (eret_q_x),
  853
+    .csr_psw		    (lm32_csr_psw_reg),
852 854
 `endif
853 855
 `ifdef CFG_IWB_ENABLED
854 856
     // From Wishbone
@@ -1028,6 +1030,7 @@ lm32_load_store_unit #(
1028 1030
     .csr_write_data         (operand_1_x),
1029 1031
     .csr_write_enable       (csr_write_enable_q_x),
1030 1032
     .eret_q_x		    (eret_q_x),
  1033
+    .csr_psw		    (lm32_csr_psw_reg),
1031 1034
 `endif
1032 1035
     // From Wishbone
1033 1036
     .d_dat_i                (D_DAT_I),
@@ -2174,6 +2177,28 @@ begin
2174 2177
     endcase
2175 2178
 end
2176 2179
 
  2180
+`ifdef CFG_MMU_ENABLED
  2181
+
  2182
+always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  2183
+begin
  2184
+	if (rst_i)
  2185
+	begin
  2186
+		lm32_csr_psw_reg <= `LM32_WORD_WIDTH'h0;
  2187
+	end
  2188
+	else
  2189
+	if (csr_write_enable_q_x)
  2190
+	begin
  2191
+		case (csr_x)
  2192
+		// operand_1_x is csr_write_data
  2193
+		`LM32_CSR_PSW:
  2194
+			lm32_csr_psw_reg <= operand_1_x;
  2195
+		`LM32_CSR_IE:
  2196
+			lm32_csr_psw_reg[2:0] <= operand_1_x[2:0];
  2197
+		endcase
  2198
+	end
  2199
+end
  2200
+`endif
  2201
+
2177 2202
 /////////////////////////////////////////////////////
2178 2203
 // Sequential Logic
2179 2204
 /////////////////////////////////////////////////////
19  lm32_dcache.v
@@ -80,6 +80,9 @@
80 80
 `define LM32_TLB_CTRL_SWITCH_TO_USER_MODE	5'h8
81 81
 `define LM32_TLB_CTRL_INVALIDATE_ENTRY		5'h10
82 82
 
  83
+// FIXME: update the value
  84
+`define LM32_CSR_PSW_DTLBE		 `LM32_WORD_WIDTH'h01
  85
+
83 86
 `define LM32_TLB_STATE_CHECK		 2'b01
84 87
 `define LM32_TLB_STATE_FLUSH		 2'b10
85 88
 
@@ -114,6 +117,7 @@ module lm32_dcache (
114 117
     exception_x,
115 118
     eret_q_x,
116 119
     exception_m,
  120
+    csr_psw,
117 121
 `endif
118 122
     // ----- Outputs -----
119 123
     stall_request,
@@ -217,6 +221,7 @@ input csr_write_enable;					// CSR write enable
217 221
 input exception_x;					// An exception occured in the X stage
218 222
 input exception_m;
219 223
 input eret_q_x;
  224
+input [`LM32_WORD_RNG] csr_psw;
220 225
 
221 226
 `endif
222 227
 
@@ -444,7 +449,7 @@ generate
444 449
 
445 450
 assign way_match[i] = 
446 451
 `ifdef CFG_MMU_ENABLED
447  
-			(kernel_mode_reg == `LM32_USER_MODE) ?
  452
+			(dtlb_enabled == `TRUE) ?
448 453
 			({way_tag[i], way_valid[i]} == {dtlb_lookup, `TRUE}) : 
449 454
 `endif
450 455
 		      ({way_tag[i], way_valid[i]} == {address_m[`LM32_DC_ADDR_TAG_RNG], `TRUE});
@@ -554,7 +559,7 @@ assign refill = state[2];
554 559
 assign miss = (~(|way_match)) && (load_q_m == `TRUE) && (stall_m == `FALSE) && (~dtlb_miss);
555 560
 assign stall_request = (check == `FALSE) || (dtlb_state == `LM32_TLB_STATE_FLUSH 
556 561
 `ifdef CFG_MMU_ENABLED
557  
-			&& kernel_mode_reg != `LM32_KERNEL_MODE
  562
+			&& (dtlb_enabled == `TRUE)
558 563
 `endif
559 564
 			);
560 565
 
@@ -686,6 +691,8 @@ endgenerate
686 691
 `ifdef CFG_MMU_ENABLED
687 692
 // Beginning of MMU specific code
688 693
 
  694
+assign dtlb_enabled = csr_psw[`LM32_CSR_PSW_DTLBE];
  695
+
689 696
 // Compute address to use to index into the DTLB data memory
690 697
 
691 698
 assign dtlb_data_read_address = address_x[`LM32_DTLB_IDX_RNG];
@@ -697,7 +704,7 @@ assign dtlb_data_write_address = dtlb_update_vaddr_csr_reg[`LM32_DTLB_IDX_RNG];
697 704
 assign dtlb_data_read_port_enable = (stall_x == `FALSE) || !stall_m;
698 705
 assign dtlb_write_port_enable = dtlb_updating || dtlb_flushing;
699 706
 
700  
-assign physical_address = (kernel_mode_reg == `LM32_KERNEL_MODE)
  707
+assign physical_address = (dtlb_enabled == `FALSE)
701 708
 			    ? address_m
702 709
 			    : {dtlb_lookup, address_m[`LM32_PAGE_OFFSET_RNG]};
703 710
 
@@ -709,12 +716,9 @@ assign dtlb_read_tag = dtlb_read_data[`LM32_DTLB_TAG_RANGE];
709 716
 assign dtlb_data_valid = dtlb_read_data[`LM32_DTLB_VALID_BIT];
710 717
 assign dtlb_lookup = dtlb_read_data[`LM32_DTLB_LOOKUP_RANGE];
711 718
 assign csr_read_data = dtlb_miss_addr;
712  
-assign dtlb_miss = (kernel_mode_reg == `LM32_USER_MODE) && (load_q_m || store_q_m) && ~(dtlb_data_valid);
  719
+assign dtlb_miss = (dtlb_enabled == `TRUE) && (load_q_m || store_q_m) && ~(dtlb_data_valid);
713 720
 assign dtlb_miss_int = (dtlb_miss || dtlb_miss_q);
714 721
 
715  
-assign switch_to_kernel_mode = (/*(kernel_mode_reg == `LM32_KERNEL_MODE) && */csr_write_enable && (csr == `LM32_CSR_TLB_CTRL) && csr_write_data[5:0] == {`LM32_TLB_CTRL_SWITCH_TO_KERNEL_MODE, 1'b1});
716  
-assign switch_to_user_mode = (/*(kernel_mode_reg == `LM32_KERNEL_MODE) && */csr_write_enable && (csr == `LM32_CSR_TLB_CTRL) && csr_write_data[5:0] == {`LM32_TLB_CTRL_SWITCH_TO_USER_MODE, 1'b1});
717  
-
718 722
 // CSR Write
719 723
 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
720 724
 begin
@@ -757,6 +761,7 @@ always @(posedge clk_i `CFG_RESET_SENSITIVITY)
757 761
 begin
758 762
 	if (rst_i == `TRUE)
759 763
 	begin
  764
+		$display("DTLB STATE MACHINE RESET");
760 765
 		dtlb_flushing <= 1;
761 766
 		dtlb_flush_set <= {addr_dtlb_index_width{1'b1}};
762 767
 		dtlb_state <= `LM32_TLB_STATE_FLUSH;
18  lm32_icache.v
@@ -80,6 +80,9 @@
80 80
 
81 81
 `ifdef CFG_MMU_ENABLED
82 82
 
  83
+// FIXME: update the value
  84
+`define LM32_CSR_PSW_ITLBE		`LM32_WORD_WIDTH'h02
  85
+
83 86
 `define LM32_ITLB_CTRL_FLUSH		 	5'h1
84 87
 `define LM32_ITLB_CTRL_UPDATE		 	5'h2
85 88
 `define LM32_TLB_CTRL_SWITCH_TO_KERNEL_MODE	5'h4
@@ -119,6 +122,7 @@ module lm32_icache (
119 122
     csr,
120 123
     csr_write_data,
121 124
     csr_write_enable,
  125
+    csr_psw,
122 126
     exception_x,
123 127
     eret_q_x,
124 128
     exception_m,
@@ -226,6 +230,7 @@ input select_f;                                     // Instruction in F stage is
226 230
 input [`LM32_CSR_RNG] csr;				// CSR read/write index
227 231
 input [`LM32_WORD_RNG] csr_write_data;			// Data to write to specified CSR
228 232
 input csr_write_enable;					// CSR write enable
  233
+input [`LM32_WORD_RNG] csr_psw;
229 234
 input exception_x;					// An exception occured in the X stage
230 235
 input exception_m;
231 236
 input eret_q_x;
@@ -321,6 +326,7 @@ wire itlb_data_valid;
321 326
 wire [`LM32_ITLB_LOOKUP_RANGE] itlb_lookup;
322 327
 reg go_to_user_mode;
323 328
 reg go_to_user_mode_2;
  329
+wire itlb_enabled;
324 330
 
325 331
 `endif
326 332
 
@@ -427,7 +433,7 @@ generate
427 433
 
428 434
 assign way_match[i] =
429 435
 `ifdef CFG_MMU_ENABLED
430  
-			(kernel_mode_reg == `LM32_USER_MODE) ?
  436
+			(itlb_enabled == `TRUE) ?
431 437
 			({way_tag[i], way_valid[i]} == {itlb_lookup, `TRUE }) : 
432 438
 `endif
433 439
 			({way_tag[i], way_valid[i]} == {address_f[`LM32_IC_ADDR_TAG_RNG], `TRUE});
@@ -649,6 +655,8 @@ end
649 655
 endgenerate
650 656
 
651 657
 `ifdef CFG_MMU_ENABLED
  658
+
  659
+assign itlb_enabled = csr_psw[`LM32_CSR_PSW_ITLBE];
652 660
    
653 661
 // Compute address to use to index into the ITLB data memory
654 662
 assign itlb_data_read_address = address_a[`LM32_ITLB_IDX_RNG];
@@ -659,7 +667,7 @@ assign itlb_data_write_address = itlb_update_vaddr_csr_reg[`LM32_ITLB_IDX_RNG];
659 667
 assign itlb_data_read_port_enable = (stall_a == `FALSE) || !stall_f;
660 668
 assign itlb_write_port_enable = itlb_updating || itlb_flushing;
661 669
 
662  
-assign physical_address = (kernel_mode_reg == `LM32_KERNEL_MODE)
  670
+assign physical_address = (itlb_enabled == `FALSE)
663 671
 			    ? {address_f, 2'b0}
664 672
 			    : {itlb_lookup, address_f[`LM32_PAGE_OFFSET_RNG+2], 2'b0};
665 673
 
@@ -670,11 +678,8 @@ assign itlb_write_data = (itlb_flushing == `TRUE)
670 678
 assign pa = physical_address;
671 679
 assign kernel_mode = kernel_mode_reg;
672 680
 
673  
-assign switch_to_kernel_mode = (/*(kernel_mode_reg == `LM32_KERNEL_MODE) && */csr_write_enable && (csr == `LM32_CSR_TLB_CTRL) && csr_write_data[5:0] == {`LM32_TLB_CTRL_SWITCH_TO_KERNEL_MODE, 1'b0});
674  
-assign switch_to_user_mode = (/*(kernel_mode_reg == `LM32_KERNEL_MODE) && */csr_write_enable && (csr == `LM32_CSR_TLB_CTRL) && csr_write_data[5:0] == {`LM32_TLB_CTRL_SWITCH_TO_USER_MODE, 1'b0});
675  
-
676 681
 assign csr_read_data = {itlb_miss_addr, 2'b0};
677  
-assign itlb_miss = (kernel_mode_reg == `LM32_USER_MODE) && (read_enable_f) && ~(itlb_data_valid);
  682
+assign itlb_miss = (itlb_enabled == `TRUE) && (read_enable_f) && ~(itlb_data_valid);
678 683
 assign itlb_miss_int = (itlb_miss || itlb_miss_q);
679 684
 assign itlb_read_tag = itlb_read_data[`LM32_ITLB_TAG_RANGE];
680 685
 assign itlb_data_valid = itlb_read_data[`LM32_ITLB_VALID_BIT];
@@ -761,6 +766,7 @@ always @(posedge clk_i `CFG_RESET_SENSITIVITY)
761 766
 begin
762 767
 	if (rst_i == `TRUE)
763 768
 	begin
  769
+		$display("ITLB STATE MACHINE RESET");
764 770
 		itlb_flushing <= 1;
765 771
 		itlb_flush_set <= {addr_itlb_index_width{1'b1}};
766 772
 		itlb_state <= `LM32_TLB_STATE_FLUSH;
1  lm32_include.v
@@ -293,6 +293,7 @@
293 293
 `define LM32_CSR_WP3                    `LM32_CSR_WIDTH'h1b
294 294
 `endif
295 295
 `ifdef CFG_MMU_ENABLED
  296
+`define LM32_CSR_PSW			`LM32_CSR_WIDTH'hb
296 297
 `define LM32_CSR_TLB_CTRL		`LM32_CSR_WIDTH'h1c
297 298
 `define LM32_CSR_TLB_VADDRESS		`LM32_CSR_WIDTH'h1d
298 299
 `define LM32_CSR_TLB_PADDRESS		`LM32_CSR_WIDTH'h1e
3  lm32_instruction_unit.v
@@ -101,6 +101,7 @@ module lm32_instruction_unit (
101 101
     exception_m,
102 102
 `ifdef CFG_MMU_ENABLED
103 103
     exception_x,
  104
+    csr_psw,
104 105
 `endif
105 106
     branch_taken_m,
106 107
     branch_mispredict_taken_m,
@@ -264,6 +265,7 @@ input eret_q_x;
264 265
 input [`LM32_CSR_RNG] csr;				// CSR read/write index
265 266
 input [`LM32_WORD_RNG] csr_write_data;			// Data to write to specified CSR
266 267
 input csr_write_enable;					// CSR write enable
  268
+input [`LM32_WORD_RNG] csr_psw;
267 269
 `endif
268 270
 
269 271
 /////////////////////////////////////////////////////
@@ -494,6 +496,7 @@ lm32_icache #(
494 496
     .csr		    (csr),
495 497
     .csr_write_data	    (csr_write_data),
496 498
     .csr_write_enable	    (csr_write_enable),
  499
+    .csr_psw		    (csr_psw),
497 500
     .exception_x	    (exception_x),
498 501
     .eret_q_x		    (eret_q_x),
499 502
     .exception_m	    (exception_m),
2  lm32_interrupt.v
@@ -266,7 +266,7 @@ begin
266 266
             else if (csr_write_enable == `TRUE)
267 267
             begin
268 268
                 // Handle wcsr write
269  
-                if (csr == `LM32_CSR_IE)
  269
+                if ((csr == `LM32_CSR_IE) || (csr == `LM32_CSR_PSW))
270 270
                 begin
271 271
                     ie <= csr_write_data[0];
272 272
                     eie <= csr_write_data[1];
3  lm32_load_store_unit.v
@@ -104,6 +104,7 @@ module lm32_load_store_unit (
104 104
     csr_write_data,
105 105
     csr_write_enable,
106 106
     eret_q_x,
  107
+    csr_psw,
107 108
 `endif
108 109
     // From Wishbone
109 110
     d_dat_i,
@@ -177,6 +178,7 @@ input eret_q_x;
177 178
 input [`LM32_CSR_RNG] csr;				// CSR read/write index
178 179
 input [`LM32_WORD_RNG] csr_write_data;			// Data to write to specified CSR
179 180
 input csr_write_enable;					// CSR write enable
  181
+input [`LM32_WORD_RNG] csr_psw;
180 182
 `endif
181 183
 
182 184
 input [`LM32_WORD_RNG] store_operand_x;                 // Data read from register to store
@@ -440,6 +442,7 @@ lm32_dcache #(
440 442
     .exception_x	    (exception_x),
441 443
     .eret_q_x		    (eret_q_x),
442 444
     .exception_m	    (exception_m),
  445
+    .csr_psw		    (csr_psw),
443 446
 `endif
444 447
     // ----- Outputs -----
445 448
     .stall_request          (dcache_stall_request),
11  soc.v
@@ -342,6 +342,17 @@ lm32_top lm32(
342 342
 	.rst_i(reset0_sys_rst)
343 343
 );
344 344
 
  345
+always @(posedge clkfx_sys_clkout)
  346
+begin
  347
+	if ((cpu0__inst_D_ADR_O[31:18] == 14'd0 && cpu0_dbus_wishbone_ack_i) || (cpu0__inst_I_ADR_O[31:18] == 14'd0 && cpu0_ibus_wishbone_ack_i))
  348
+	begin
  349
+		sram0_wishbone_err_o <= 1'b1;
  350
+		$display("NULL pointer catched !");
  351
+	end
  352
+	else
  353
+		sram0_wishbone_err_o <= 1'b0;
  354
+end
  355
+
345 356
 reg [31:0] mem[0:16383];
346 357
 reg [31:0] memadr;
347 358
 always @(posedge clkfx_sys_clkout) begin

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