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base fork: fallen/milkymist-mmu-simulation
base: c5461df4f851
...
head fork: fallen/milkymist-mmu-simulation
compare: 720786ee0aab
  • 2 commits
  • 8 files changed
  • 0 commit comments
  • 1 contributor
View
25 lm32_cpu.v
@@ -781,6 +781,7 @@ reg ext_break_r;
`ifdef CFG_MMU_ENABLED
wire dtlb_miss_exception;
wire itlb_miss_exception;
+reg [`LM32_WORD_RNG] lm32_csr_psw_reg;
`endif
/////////////////////////////////////////////////////
@@ -849,6 +850,7 @@ lm32_instruction_unit #(
.csr_write_data (operand_1_x),
.csr_write_enable (csr_write_enable_q_x),
.eret_q_x (eret_q_x),
+ .csr_psw (lm32_csr_psw_reg),
`endif
`ifdef CFG_IWB_ENABLED
// From Wishbone
@@ -1028,6 +1030,7 @@ lm32_load_store_unit #(
.csr_write_data (operand_1_x),
.csr_write_enable (csr_write_enable_q_x),
.eret_q_x (eret_q_x),
+ .csr_psw (lm32_csr_psw_reg),
`endif
// From Wishbone
.d_dat_i (D_DAT_I),
@@ -2174,6 +2177,28 @@ begin
endcase
end
+`ifdef CFG_MMU_ENABLED
+
+always @(posedge clk_i `CFG_RESET_SENSITIVITY)
+begin
+ if (rst_i)
+ begin
+ lm32_csr_psw_reg <= `LM32_WORD_WIDTH'h0;
+ end
+ else
+ if (csr_write_enable_q_x)
+ begin
+ case (csr_x)
+ // operand_1_x is csr_write_data
+ `LM32_CSR_PSW:
+ lm32_csr_psw_reg <= operand_1_x;
+ `LM32_CSR_IE:
+ lm32_csr_psw_reg[2:0] <= operand_1_x[2:0];
+ endcase
+ end
+end
+`endif
+
/////////////////////////////////////////////////////
// Sequential Logic
/////////////////////////////////////////////////////
View
19 lm32_dcache.v
@@ -80,6 +80,9 @@
`define LM32_TLB_CTRL_SWITCH_TO_USER_MODE 5'h8
`define LM32_TLB_CTRL_INVALIDATE_ENTRY 5'h10
+// FIXME: update the value
+`define LM32_CSR_PSW_DTLBE `LM32_WORD_WIDTH'h01
+
`define LM32_TLB_STATE_CHECK 2'b01
`define LM32_TLB_STATE_FLUSH 2'b10
@@ -114,6 +117,7 @@ module lm32_dcache (
exception_x,
eret_q_x,
exception_m,
+ csr_psw,
`endif
// ----- Outputs -----
stall_request,
@@ -217,6 +221,7 @@ input csr_write_enable; // CSR write enable
input exception_x; // An exception occured in the X stage
input exception_m;
input eret_q_x;
+input [`LM32_WORD_RNG] csr_psw;
`endif
@@ -444,7 +449,7 @@ generate
assign way_match[i] =
`ifdef CFG_MMU_ENABLED
- (kernel_mode_reg == `LM32_USER_MODE) ?
+ (dtlb_enabled == `TRUE) ?
({way_tag[i], way_valid[i]} == {dtlb_lookup, `TRUE}) :
`endif
({way_tag[i], way_valid[i]} == {address_m[`LM32_DC_ADDR_TAG_RNG], `TRUE});
@@ -554,7 +559,7 @@ assign refill = state[2];
assign miss = (~(|way_match)) && (load_q_m == `TRUE) && (stall_m == `FALSE) && (~dtlb_miss);
assign stall_request = (check == `FALSE) || (dtlb_state == `LM32_TLB_STATE_FLUSH
`ifdef CFG_MMU_ENABLED
- && kernel_mode_reg != `LM32_KERNEL_MODE
+ && (dtlb_enabled == `TRUE)
`endif
);
@@ -686,6 +691,8 @@ endgenerate
`ifdef CFG_MMU_ENABLED
// Beginning of MMU specific code
+assign dtlb_enabled = csr_psw[`LM32_CSR_PSW_DTLBE];
+
// Compute address to use to index into the DTLB data memory
assign dtlb_data_read_address = address_x[`LM32_DTLB_IDX_RNG];
@@ -697,7 +704,7 @@ assign dtlb_data_write_address = dtlb_update_vaddr_csr_reg[`LM32_DTLB_IDX_RNG];
assign dtlb_data_read_port_enable = (stall_x == `FALSE) || !stall_m;
assign dtlb_write_port_enable = dtlb_updating || dtlb_flushing;
-assign physical_address = (kernel_mode_reg == `LM32_KERNEL_MODE)
+assign physical_address = (dtlb_enabled == `FALSE)
? address_m
: {dtlb_lookup, address_m[`LM32_PAGE_OFFSET_RNG]};
@@ -709,12 +716,9 @@ assign dtlb_read_tag = dtlb_read_data[`LM32_DTLB_TAG_RANGE];
assign dtlb_data_valid = dtlb_read_data[`LM32_DTLB_VALID_BIT];
assign dtlb_lookup = dtlb_read_data[`LM32_DTLB_LOOKUP_RANGE];
assign csr_read_data = dtlb_miss_addr;
-assign dtlb_miss = (kernel_mode_reg == `LM32_USER_MODE) && (load_q_m || store_q_m) && ~(dtlb_data_valid);
+assign dtlb_miss = (dtlb_enabled == `TRUE) && (load_q_m || store_q_m) && ~(dtlb_data_valid);
assign dtlb_miss_int = (dtlb_miss || dtlb_miss_q);
-assign switch_to_kernel_mode = (/*(kernel_mode_reg == `LM32_KERNEL_MODE) && */csr_write_enable && (csr == `LM32_CSR_TLB_CTRL) && csr_write_data[5:0] == {`LM32_TLB_CTRL_SWITCH_TO_KERNEL_MODE, 1'b1});
-assign switch_to_user_mode = (/*(kernel_mode_reg == `LM32_KERNEL_MODE) && */csr_write_enable && (csr == `LM32_CSR_TLB_CTRL) && csr_write_data[5:0] == {`LM32_TLB_CTRL_SWITCH_TO_USER_MODE, 1'b1});
-
// CSR Write
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
@@ -757,6 +761,7 @@ always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
begin
+ $display("DTLB STATE MACHINE RESET");
dtlb_flushing <= 1;
dtlb_flush_set <= {addr_dtlb_index_width{1'b1}};
dtlb_state <= `LM32_TLB_STATE_FLUSH;
View
18 lm32_icache.v
@@ -80,6 +80,9 @@
`ifdef CFG_MMU_ENABLED
+// FIXME: update the value
+`define LM32_CSR_PSW_ITLBE `LM32_WORD_WIDTH'h02
+
`define LM32_ITLB_CTRL_FLUSH 5'h1
`define LM32_ITLB_CTRL_UPDATE 5'h2
`define LM32_TLB_CTRL_SWITCH_TO_KERNEL_MODE 5'h4
@@ -119,6 +122,7 @@ module lm32_icache (
csr,
csr_write_data,
csr_write_enable,
+ csr_psw,
exception_x,
eret_q_x,
exception_m,
@@ -226,6 +230,7 @@ input select_f; // Instruction in F stage is
input [`LM32_CSR_RNG] csr; // CSR read/write index
input [`LM32_WORD_RNG] csr_write_data; // Data to write to specified CSR
input csr_write_enable; // CSR write enable
+input [`LM32_WORD_RNG] csr_psw;
input exception_x; // An exception occured in the X stage
input exception_m;
input eret_q_x;
@@ -321,6 +326,7 @@ wire itlb_data_valid;
wire [`LM32_ITLB_LOOKUP_RANGE] itlb_lookup;
reg go_to_user_mode;
reg go_to_user_mode_2;
+wire itlb_enabled;
`endif
@@ -427,7 +433,7 @@ generate
assign way_match[i] =
`ifdef CFG_MMU_ENABLED
- (kernel_mode_reg == `LM32_USER_MODE) ?
+ (itlb_enabled == `TRUE) ?
({way_tag[i], way_valid[i]} == {itlb_lookup, `TRUE }) :
`endif
({way_tag[i], way_valid[i]} == {address_f[`LM32_IC_ADDR_TAG_RNG], `TRUE});
@@ -649,6 +655,8 @@ end
endgenerate
`ifdef CFG_MMU_ENABLED
+
+assign itlb_enabled = csr_psw[`LM32_CSR_PSW_ITLBE];
// Compute address to use to index into the ITLB data memory
assign itlb_data_read_address = address_a[`LM32_ITLB_IDX_RNG];
@@ -659,7 +667,7 @@ assign itlb_data_write_address = itlb_update_vaddr_csr_reg[`LM32_ITLB_IDX_RNG];
assign itlb_data_read_port_enable = (stall_a == `FALSE) || !stall_f;
assign itlb_write_port_enable = itlb_updating || itlb_flushing;
-assign physical_address = (kernel_mode_reg == `LM32_KERNEL_MODE)
+assign physical_address = (itlb_enabled == `FALSE)
? {address_f, 2'b0}
: {itlb_lookup, address_f[`LM32_PAGE_OFFSET_RNG+2], 2'b0};
@@ -670,11 +678,8 @@ assign itlb_write_data = (itlb_flushing == `TRUE)
assign pa = physical_address;
assign kernel_mode = kernel_mode_reg;
-assign switch_to_kernel_mode = (/*(kernel_mode_reg == `LM32_KERNEL_MODE) && */csr_write_enable && (csr == `LM32_CSR_TLB_CTRL) && csr_write_data[5:0] == {`LM32_TLB_CTRL_SWITCH_TO_KERNEL_MODE, 1'b0});
-assign switch_to_user_mode = (/*(kernel_mode_reg == `LM32_KERNEL_MODE) && */csr_write_enable && (csr == `LM32_CSR_TLB_CTRL) && csr_write_data[5:0] == {`LM32_TLB_CTRL_SWITCH_TO_USER_MODE, 1'b0});
-
assign csr_read_data = {itlb_miss_addr, 2'b0};
-assign itlb_miss = (kernel_mode_reg == `LM32_USER_MODE) && (read_enable_f) && ~(itlb_data_valid);
+assign itlb_miss = (itlb_enabled == `TRUE) && (read_enable_f) && ~(itlb_data_valid);
assign itlb_miss_int = (itlb_miss || itlb_miss_q);
assign itlb_read_tag = itlb_read_data[`LM32_ITLB_TAG_RANGE];
assign itlb_data_valid = itlb_read_data[`LM32_ITLB_VALID_BIT];
@@ -761,6 +766,7 @@ always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
begin
+ $display("ITLB STATE MACHINE RESET");
itlb_flushing <= 1;
itlb_flush_set <= {addr_itlb_index_width{1'b1}};
itlb_state <= `LM32_TLB_STATE_FLUSH;
View
1  lm32_include.v
@@ -293,6 +293,7 @@
`define LM32_CSR_WP3 `LM32_CSR_WIDTH'h1b
`endif
`ifdef CFG_MMU_ENABLED
+`define LM32_CSR_PSW `LM32_CSR_WIDTH'hb
`define LM32_CSR_TLB_CTRL `LM32_CSR_WIDTH'h1c
`define LM32_CSR_TLB_VADDRESS `LM32_CSR_WIDTH'h1d
`define LM32_CSR_TLB_PADDRESS `LM32_CSR_WIDTH'h1e
View
3  lm32_instruction_unit.v
@@ -101,6 +101,7 @@ module lm32_instruction_unit (
exception_m,
`ifdef CFG_MMU_ENABLED
exception_x,
+ csr_psw,
`endif
branch_taken_m,
branch_mispredict_taken_m,
@@ -264,6 +265,7 @@ input eret_q_x;
input [`LM32_CSR_RNG] csr; // CSR read/write index
input [`LM32_WORD_RNG] csr_write_data; // Data to write to specified CSR
input csr_write_enable; // CSR write enable
+input [`LM32_WORD_RNG] csr_psw;
`endif
/////////////////////////////////////////////////////
@@ -494,6 +496,7 @@ lm32_icache #(
.csr (csr),
.csr_write_data (csr_write_data),
.csr_write_enable (csr_write_enable),
+ .csr_psw (csr_psw),
.exception_x (exception_x),
.eret_q_x (eret_q_x),
.exception_m (exception_m),
View
2  lm32_interrupt.v
@@ -266,7 +266,7 @@ begin
else if (csr_write_enable == `TRUE)
begin
// Handle wcsr write
- if (csr == `LM32_CSR_IE)
+ if ((csr == `LM32_CSR_IE) || (csr == `LM32_CSR_PSW))
begin
ie <= csr_write_data[0];
eie <= csr_write_data[1];
View
3  lm32_load_store_unit.v
@@ -104,6 +104,7 @@ module lm32_load_store_unit (
csr_write_data,
csr_write_enable,
eret_q_x,
+ csr_psw,
`endif
// From Wishbone
d_dat_i,
@@ -177,6 +178,7 @@ input eret_q_x;
input [`LM32_CSR_RNG] csr; // CSR read/write index
input [`LM32_WORD_RNG] csr_write_data; // Data to write to specified CSR
input csr_write_enable; // CSR write enable
+input [`LM32_WORD_RNG] csr_psw;
`endif
input [`LM32_WORD_RNG] store_operand_x; // Data read from register to store
@@ -440,6 +442,7 @@ lm32_dcache #(
.exception_x (exception_x),
.eret_q_x (eret_q_x),
.exception_m (exception_m),
+ .csr_psw (csr_psw),
`endif
// ----- Outputs -----
.stall_request (dcache_stall_request),
View
11 soc.v
@@ -342,6 +342,17 @@ lm32_top lm32(
.rst_i(reset0_sys_rst)
);
+always @(posedge clkfx_sys_clkout)
+begin
+ if ((cpu0__inst_D_ADR_O[31:18] == 14'd0 && cpu0_dbus_wishbone_ack_i) || (cpu0__inst_I_ADR_O[31:18] == 14'd0 && cpu0_ibus_wishbone_ack_i))
+ begin
+ sram0_wishbone_err_o <= 1'b1;
+ $display("NULL pointer catched !");
+ end
+ else
+ sram0_wishbone_err_o <= 1'b0;
+end
+
reg [31:0] mem[0:16383];
reg [31:0] memadr;
always @(posedge clkfx_sys_clkout) begin

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