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Fix registers initialization which is mandatory for a healthy simulation

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1 parent cbb35e0 commit 059f0bd849db41963b11a668ea454f351be3a9a5 @fallen committed Feb 16, 2012
Showing with 25 additions and 1 deletion.
  1. +19 −0 cores/lm32/rtl/lm32_cpu.v
  2. +6 −1 cores/lm32/rtl/lm32_dp_ram.v
@@ -2772,4 +2772,23 @@ begin
end
`endif
+/////////////////////////////////////////////////////
+// Behavioural Logic
+/////////////////////////////////////////////////////
+
+// synthesis translate_off
+
+// Reset register 0. Only needed for simulation.
+initial
+begin
+`ifdef LM32_EBR_REGISTER_FILE
+ reg_0.ram[0] = {`LM32_WORD_WIDTH{1'b0}};
+ reg_1.ram[0] = {`LM32_WORD_WIDTH{1'b0}};
+`else
+ registers[0] = {`LM32_WORD_WIDTH{1'b0}};
+`endif
+end
+
+// synthesis translate_on
+
endmodule
@@ -24,9 +24,14 @@ reg [data_width-1:0] ram[addr_depth-1:0];
reg [addr_width-1:0] raddr_r;
assign rdata_o = ram[raddr_r];
+integer i;
+
initial
begin
- ram[0] = {data_width{ 1'b0 }};
+ for (i = addr_depth-1 ; i >= 0 ; i = i-1)
+ begin
+ ram[i] <= {data_width{1'b0}};
+ end
end
always @ (posedge clk_i)

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