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Make DTLB generate exception uppon TLB miss

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1 parent 8e87083 commit 43f6245f780d4b2c19122ba55ca759a358470d51 @fallen committed May 30, 2012
@@ -96,6 +96,8 @@
`define CFG_WATCHPOINTS 32'h4
`define CFG_EXTERNAL_BREAK_ENABLED
`define CFG_GDBSTUB_ENABLED
+//`define CFG_RANDOM_WISHBONE_LATENCY
+//`define CFG_VERBOSE_DISPLAY_ENABLED
// Enable MMU
`define CFG_MMU_ENABLED
@@ -304,16 +306,17 @@
`define LM32_WPC_C_READ_WRITE 2'b11
// Exception IDs
-`define LM32_EID_WIDTH 3
+`define LM32_EID_WIDTH 4
`define LM32_EID_RNG (`LM32_EID_WIDTH-1):0
-`define LM32_EID_RESET 3'h0
-`define LM32_EID_BREAKPOINT 3'd1
-`define LM32_EID_INST_BUS_ERROR 3'h2
-`define LM32_EID_WATCHPOINT 3'd3
-`define LM32_EID_DATA_BUS_ERROR 3'h4
-`define LM32_EID_DIVIDE_BY_ZERO 3'h5
-`define LM32_EID_INTERRUPT 3'h6
-`define LM32_EID_SCALL 3'h7
+`define LM32_EID_RESET `LM32_EID_WIDTH'h0
+`define LM32_EID_BREAKPOINT `LM32_EID_WIDTH'd1
+`define LM32_EID_INST_BUS_ERROR `LM32_EID_WIDTH'h2
+`define LM32_EID_WATCHPOINT `LM32_EID_WIDTH'd3
+`define LM32_EID_DATA_BUS_ERROR `LM32_EID_WIDTH'h4
+`define LM32_EID_DIVIDE_BY_ZERO `LM32_EID_WIDTH'h5
+`define LM32_EID_INTERRUPT `LM32_EID_WIDTH'h6
+`define LM32_EID_SCALL `LM32_EID_WIDTH'h7
+`define LM32_EID_DTLB_MISS `LM32_EID_WIDTH'h8
// Pipeline result selection mux controls
@@ -967,6 +967,8 @@ lm32_decoder decoder (
.csr_write_enable (csr_write_enable_d)
);
+wire dtlb_miss_exception;
+
// Load/store unit
lm32_load_store_unit #(
.associativity (dcache_associativity),
@@ -985,6 +987,7 @@ lm32_load_store_unit #(
.kill_x (kill_x),
.kill_m (kill_m),
.exception_m (exception_m),
+ .exception_x (exception_x),
.store_operand_x (store_operand_x),
.load_store_address_x (adder_result_x),
.load_store_address_m (operand_m),
@@ -1006,6 +1009,7 @@ lm32_load_store_unit #(
.csr (csr_x),
.csr_write_data (operand_1_x),
.csr_write_enable (csr_write_enable_q_x),
+ .eret_q_x (eret_q_x),
// From Wishbone
.d_dat_i (D_DAT_I),
.d_ack_i (D_ACK_I),
@@ -1027,7 +1031,7 @@ lm32_load_store_unit #(
`endif
.load_data_w (load_data_w),
.stall_wb_load (stall_wb_load),
- .dtlb_miss (dtlb_miss),
+ .dtlb_miss (dtlb_miss_exception),
.csr_read_data (load_store_csr_read_data_x),
// To Wishbone
.d_dat_o (D_DAT_O),
@@ -1766,6 +1770,9 @@ assign non_debug_exception_x = (system_call_exception == `TRUE)
`endif
)
`endif
+`ifdef CFG_MMU_ENABLED
+ || (dtlb_miss_exception == `TRUE)
+`endif
;
assign exception_x = (debug_exception_x == `TRUE) || (non_debug_exception_x == `TRUE);
@@ -1789,6 +1796,9 @@ assign exception_x = (system_call_exception == `TRUE)
`endif
)
`endif
+`ifdef CFG_MMU_ENABLED
+ || (dtlb_miss_exception == `TRUE)
+`endif
;
`endif
@@ -1837,7 +1847,10 @@ begin
eid_x = `LM32_EID_INTERRUPT;
else
`endif
- eid_x = `LM32_EID_SCALL;
+ if (dtlb_miss_exception == `TRUE )
+ eid_x = `LM32_EID_DTLB_MISS;
+ else
+ eid_x = `LM32_EID_SCALL;
end
// Stall generation
@@ -2557,13 +2570,15 @@ begin
|| ((debug_exception_x == `TRUE)
&& (non_debug_exception_x == `FALSE)))
- branch_target_m <= {deba, eid_x, {3{1'b0}}};
+ branch_target_m <= {deba[31:9], eid_x, {3{1'b0}}};
else
- branch_target_m <= {eba, eid_x, {3{1'b0}}};
+ branch_target_m <= {eba[31:9], eid_x, {3{1'b0}}};
else
branch_target_m <= branch_target_x;
`else
- branch_target_m <= exception_x == `TRUE ? {eba, eid_x, {3{1'b0}}} : branch_target_x;
+//if (exception_x == `TRUE)
+// $display("branch_target_m <= 0x%08X", branch_target_m);
+ branch_target_m <= exception_x == `TRUE ? {eba[31:9], eid_x, {3{1'b0}}} : branch_target_x;
`endif
`ifdef CFG_TRACE_ENABLED
eid_m <= eid_x;
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