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Remove all uses of TLBCTRL CSR register, use PSW instead from now on

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commit 582617f830bda4b7f86d0b2bb14d8477b6f5c288 1 parent c4b1a04
Yann Sionneau authored
7 software/bios/main.c
View
@@ -46,7 +46,7 @@
enum {
CSR_IE = 1, CSR_IM, CSR_IP, CSR_ICC, CSR_DCC, CSR_CC, CSR_CFG, CSR_EBA,
CSR_DC, CSR_DEBA, CSR_JTX, CSR_JRX, CSR_BP0, CSR_BP1, CSR_BP2, CSR_BP3,
- CSR_WP0, CSR_WP1, CSR_WP2, CSR_WP3, CSR_TLBCTRL, CSR_TLBVADDR, CSR_TLBPADDR
+ CSR_WP0, CSR_WP1, CSR_WP2, CSR_WP3, CSR_PSW, CSR_TLBVADDR, CSR_TLBPADDR
};
/* General address space functions */
@@ -233,7 +233,7 @@ static int parse_csr(const char *csr)
if(!strcmp(csr, "wp1")) return CSR_WP1;
if(!strcmp(csr, "wp2")) return CSR_WP2;
if(!strcmp(csr, "wp3")) return CSR_WP3;
- if(!strcmp(csr, "tlbctrl")) return CSR_TLBCTRL;
+ if(!strcmp(csr, "psw")) return CSR_PSW;
if(!strcmp(csr, "tlbvaddr")) return CSR_TLBVADDR;
if(!strcmp(csr, "tlbpaddr")) return CSR_TLBPADDR;
@@ -266,6 +266,7 @@ static void rcsr(char *csr)
case CSR_DEBA: asm volatile ("rcsr %0,deba":"=r"(value)); break;
case CSR_JTX: asm volatile ("rcsr %0,jtx":"=r"(value)); break;
case CSR_JRX: asm volatile ("rcsr %0,jrx":"=r"(value)); break;
+ case CSR_PSW: asm volatile ("rcsr %0,psw":"=r"(value)); break;
default: printf("csr write only\n"); return;
}
@@ -312,7 +313,7 @@ static void wcsr(char *csr, char *value)
case CSR_WP1: asm volatile ("wcsr wp1,%0"::"r"(value2)); break;
case CSR_WP2: asm volatile ("wcsr wp2,%0"::"r"(value2)); break;
case CSR_WP3: asm volatile ("wcsr wp3,%0"::"r"(value2)); break;
- case CSR_TLBCTRL: asm volatile ("wcsr tlbctrl,%0"::"r"(value2)); break;
+ case CSR_PSW: asm volatile ("wcsr psw,%0"::"r"(value2)); break;
case CSR_TLBVADDR: asm volatile ("wcsr tlbvaddr,%0"::"r"(value2)); break;
case CSR_TLBPADDR: asm volatile ("wcsr tlbpaddr,%0"::"r"(value2)); break;
default: printf("csr read only\n"); return;
6 software/bios/mmu_test_gen.c
View
@@ -8,9 +8,9 @@ static inline void generate_test(int i, int j) {
int k;
puts("asm volatile(");
- puts("\t\"xor r11, r11, r11\\n\\t\"");
- puts("\t\"ori r11, r11, 0x11\\n\\t\"");
- puts("\t\"wcsr tlbctrl, r11\\n\\t\"");
+ puts("\t\"rcsr r11, PSW\\n\\t\"");
+ puts("\t\"ori r11, r11, 64\\n\\t\"");
+ puts("\t\"wcsr PSW, r11\\n\\t\"");
puts("\t\"xor r0, r0, r0\\n\\t\"");
puts("\t\"xor r0, r0, r0\\n\\t\"");
puts("\t\"xor r0, r0, r0\\n\\t\"");
29 software/include/hal/mmu.h
View
@@ -46,33 +46,32 @@ struct mmu_mapping {
};
#define enable_dtlb() do { \
- asm volatile ("xor r11, r11, r11\n\t" \
- "ori r11, r11, 0x11\n\t" \
- "wcsr tlbctrl, r11\n\t" \
- "xor r0, r0, r0":::"r11"); \
+ asm volatile ("rcsr r11, PSW\n\t" \
+ "ori r11, r11, 64\n\t" \
+ "wcsr PSW, r11\n\t" \
+ "xor r0, r0, r0" ::: "r11"); \
} while(0);
#define disable_dtlb() do { \
- asm volatile ("xor r11, r11, r11\n\t" \
- "ori r11, r11, 0x9\n\t" \
- "wcsr tlbctrl, r11\n\t" \
+ asm volatile ("rcsr r11, PSW\n\t" \
+ "mvi r10, ~(64)\n\t" \
+ "and r11, r11, r10\n\t" \
+ "wcsr PSW, r11\n\t" \
"xor r0, r0, r0\n\t" \
"xor r0, r0, r0\n\t" \
- "xor r0, r0, r0":::"r11"); \
+ "xor r0, r0, r0" ::: "r11", "r10"); \
} while(0);
#define enable_itlb() do { \
- asm volatile ("xor r11, r11, r11\n\t" \
- "ori r11, r11, 0x10\n\t" \
- "wcsr tlbctrl, r11\n\t" \
+ asm volatile ("rcsr r11, PSW\n\t" \
+ "ori r11, r11, 0x8\n\t" \
+ "wcsr PSW, r11\n\t" \
"xor r0, r0, r0\n\t" \
"xor r0, r0, r0\n\t" \
"xor r0, r0, r0\n\t" \
"xor r0, r0, r0\n\t":::"r11"); \
} while(0);
-#define LM32_CSR_PSW_ITLBE "(0x8)"
-
#define disable_itlb() do { \
asm volatile ("rcsr r11, PSW\n\t" \
"mvi r10, ~(0x8)\n\t" \
@@ -80,10 +79,6 @@ struct mmu_mapping {
"wcsr PSW, r11\n\t" ::: "r10", "r11"); \
} while (0);
-// FIXME : We MUST replace the following macro with a function which
-// enables ITLB using two different methods depending on whether
-// branch will be predicted as taken or non-taken
-
#define call_function_with_itlb_enabled(function) do { \
asm volatile ("rcsr r11, PSW\n\t" \
"ori r11, r11, 0x8\n\t" \
51 software/libhal/mmu.c
View
@@ -36,11 +36,10 @@ inline void mmu_dtlb_map(unsigned int vpfn, unsigned int pfn)
asm volatile ("ori %0, %0, 1\n\t"
"wcsr tlbpaddr, %0" :: "r"(pfn) : );
-
+/*
asm volatile ("xor r11, r11, r11\n\t"
"ori r11, r11, 0x5\n\t"
- "wcsr tlbctrl, r11" ::: "r11");
-
+ "wcsr tlbctrl, r11" ::: "r11"); */
}
inline void mmu_itlb_map(unsigned int vpfn, unsigned int pfn)
@@ -50,42 +49,34 @@ inline void mmu_itlb_map(unsigned int vpfn, unsigned int pfn)
asm volatile ("wcsr tlbpaddr, %0" :: "r"(get_pfn(pfn)) : );
- asm volatile ("xor r11, r11, r11\n\t"
+/* asm volatile ("xor r11, r11, r11\n\t"
"ori r11, r11, 0x4\n\t"
- "wcsr tlbctrl, r11" ::: "r11");
+ "wcsr tlbctrl, r11" ::: "r11"); */
}
inline void mmu_dtlb_invalidate_line(unsigned int vaddr)
{
- asm volatile ("ori %0, %0, 1\n\t"
+ asm volatile ("ori %0, %0, 0x21\n\t"
"wcsr tlbvaddr, %0" :: "r"(vaddr) : );
-
- asm volatile ("xor r11, r11, r11\n\t"
- "ori r11, r11, 0x21\n\t"
- "wcsr tlbctrl, r11" ::: "r11");
}
inline void mmu_itlb_invalidate_line(unsigned int vaddr)
{
- asm volatile ("ori %0, %0, 0\n\t"
+ asm volatile ("ori %0, %0, 0x20\n\t"
"wcsr tlbvaddr, %0" :: "r"(vaddr) : );
-
- asm volatile ("xor r11, r11, r11\n\t"
- "ori r11, r11, 0x20\n\t"
- "wcsr tlbctrl, r11" ::: "r11");
}
inline void mmu_dtlb_invalidate(void)
{
register unsigned int cmd = DTLB_CTRL_FLUSH_CMD;
- asm volatile("wcsr tlbctrl, %0" :: "r"(cmd) : );
+// asm volatile("wcsr tlbctrl, %0" :: "r"(cmd) : );
}
inline void mmu_itlb_invalidate(void)
{
register unsigned int cmd = ITLB_CTRL_FLUSH_CMD;
- asm volatile("wcsr tlbctrl, %0" :: "r"(cmd) : );
+// asm volatile("wcsr tlbctrl, %0" :: "r"(cmd) : );
}
@@ -103,11 +94,17 @@ unsigned int read_word_with_mmu_enabled(unsigned int vaddr)
cmd1 = DTLB_CTRL_ENABLE_CMD;
cmd2 = DTLB_CTRL_DISABLE_CMD;
- asm volatile("wcsr tlbctrl, %2\n\t" // Activates the MMU
+ asm volatile("rcsr r11, PSW\n\t"
+ "ori r11, r11, 64\n\t"
+ "wcsr PSW, r11\n\t" // Activates the MMU
+ //"wcsr tlbctrl, %2\n\t" // Activates the MMU
"xor r0, r0, r0\n\t"
"lw %0, (%1+0)\n\t" // Reads from virtual address "addr"
- "wcsr tlbctrl, %3\n\t" // Disactivates the MMU
- "xor r0, r0, r0\n\t" : "=&r"(data) : "r"(vaddr), "r"(cmd1), "r"(cmd2) :
+ "mvi r10, ~(64)\n\t"
+ "and r11, r11, r10\n\t"
+ "wcsr PSW, r11\n\t" // Disactivates the MMU
+ //"wcsr tlbctrl, %3\n\t" // Disactivates the MMU
+ "xor r0, r0, r0\n\t" : "=&r"(data) : "r"(vaddr)/*, "r"(cmd1), "r"(cmd2)*/ : "r11", "r10"
);
return data;
@@ -116,15 +113,15 @@ unsigned int read_word_with_mmu_enabled(unsigned int vaddr)
unsigned int write_word_with_mmu_enabled(register unsigned int vaddr, register unsigned int data)
{
asm volatile(
- "xor r11, r11, r11\n\t"
- "ori r11, r11, 0x11\n\t"
- "wcsr tlbctrl, r11\n\t" // Activates the MMU
+ "rcsr r11, PSW\n\t"
+ "ori r11, r11, 64\n\t"
+ "wcsr PSW, r11\n\t" // Activates the MMU
"xor r0, r0, r0\n\t"
"sw (%0 + 0), %1\n\t" // Reads from virtual address "addr"
- "xor r11, r11, r11\n\t"
- "ori r11, r11, 0x9\n\t"
- "wcsr tlbctrl, r11\n\t" // Disactivates the MMU
- "xor r0, r0, r0\n\t" :: "r"(vaddr), "r"(data) : "r11"
+ "mvi r10, ~(64)\n\t"
+ "and r11, r11, r10\n\t"
+ "wcsr PSW, r11\n\t" // Disactivates the MMU
+ "xor r0, r0, r0\n\t" :: "r"(vaddr), "r"(data) : "r11", "r10"
);
}
/*
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