Skip to content
This repository
Browse code

Remove all uses of TLBCTRL CSR register, use PSW instead from now on

  • Loading branch information...
commit 582617f830bda4b7f86d0b2bb14d8477b6f5c288 1 parent c4b1a04
Yann Sionneau authored September 21, 2012
7  software/bios/main.c
@@ -46,7 +46,7 @@
46 46
 enum {
47 47
 	CSR_IE = 1, CSR_IM, CSR_IP, CSR_ICC, CSR_DCC, CSR_CC, CSR_CFG, CSR_EBA,
48 48
 	CSR_DC, CSR_DEBA, CSR_JTX, CSR_JRX, CSR_BP0, CSR_BP1, CSR_BP2, CSR_BP3,
49  
-	CSR_WP0, CSR_WP1, CSR_WP2, CSR_WP3, CSR_TLBCTRL, CSR_TLBVADDR, CSR_TLBPADDR
  49
+	CSR_WP0, CSR_WP1, CSR_WP2, CSR_WP3, CSR_PSW, CSR_TLBVADDR, CSR_TLBPADDR
50 50
 };
51 51
 
52 52
 /* General address space functions */
@@ -233,7 +233,7 @@ static int parse_csr(const char *csr)
233 233
 	if(!strcmp(csr, "wp1"))  return CSR_WP1;
234 234
 	if(!strcmp(csr, "wp2"))  return CSR_WP2;
235 235
 	if(!strcmp(csr, "wp3"))  return CSR_WP3;
236  
-	if(!strcmp(csr, "tlbctrl"))   return CSR_TLBCTRL;
  236
+	if(!strcmp(csr, "psw"))   return CSR_PSW;
237 237
 	if(!strcmp(csr, "tlbvaddr"))  return CSR_TLBVADDR;
238 238
 	if(!strcmp(csr, "tlbpaddr"))  return CSR_TLBPADDR;
239 239
 
@@ -266,6 +266,7 @@ static void rcsr(char *csr)
266 266
 		case CSR_DEBA: asm volatile ("rcsr %0,deba":"=r"(value)); break;
267 267
 		case CSR_JTX:  asm volatile ("rcsr %0,jtx":"=r"(value)); break;
268 268
 		case CSR_JRX:  asm volatile ("rcsr %0,jrx":"=r"(value)); break;
  269
+		case CSR_PSW:  asm volatile ("rcsr %0,psw":"=r"(value)); break;
269 270
 		default: printf("csr write only\n"); return;
270 271
 	}
271 272
 
@@ -312,7 +313,7 @@ static void wcsr(char *csr, char *value)
312 313
 		case CSR_WP1:  asm volatile ("wcsr wp1,%0"::"r"(value2)); break;
313 314
 		case CSR_WP2:  asm volatile ("wcsr wp2,%0"::"r"(value2)); break;
314 315
 		case CSR_WP3:  asm volatile ("wcsr wp3,%0"::"r"(value2)); break;
315  
-		case CSR_TLBCTRL:   asm volatile ("wcsr tlbctrl,%0"::"r"(value2));  break;
  316
+		case CSR_PSW:   asm volatile ("wcsr psw,%0"::"r"(value2));  break;
316 317
 		case CSR_TLBVADDR:  asm volatile ("wcsr tlbvaddr,%0"::"r"(value2)); break;
317 318
 		case CSR_TLBPADDR:  asm volatile ("wcsr tlbpaddr,%0"::"r"(value2)); break;
318 319
 		default: printf("csr read only\n"); return;
6  software/bios/mmu_test_gen.c
@@ -8,9 +8,9 @@ static inline void generate_test(int i, int j) {
8 8
 	int k;
9 9
 
10 10
 	puts("asm volatile(");
11  
-	puts("\t\"xor r11, r11, r11\\n\\t\"");
12  
-	puts("\t\"ori r11, r11, 0x11\\n\\t\"");
13  
-	puts("\t\"wcsr tlbctrl, r11\\n\\t\"");
  11
+	puts("\t\"rcsr r11, PSW\\n\\t\"");
  12
+	puts("\t\"ori r11, r11, 64\\n\\t\"");
  13
+	puts("\t\"wcsr PSW, r11\\n\\t\"");
14 14
 	puts("\t\"xor r0, r0, r0\\n\\t\"");
15 15
 	puts("\t\"xor r0, r0, r0\\n\\t\"");
16 16
 	puts("\t\"xor r0, r0, r0\\n\\t\"");
29  software/include/hal/mmu.h
@@ -46,33 +46,32 @@ struct mmu_mapping {
46 46
 };
47 47
 
48 48
 #define enable_dtlb() do { \
49  
-	asm volatile	("xor r11, r11, r11\n\t" \
50  
-			 "ori r11, r11, 0x11\n\t" \
51  
-			 "wcsr tlbctrl, r11\n\t" \
52  
-			 "xor r0, r0, r0":::"r11"); \
  49
+	asm volatile	("rcsr r11, PSW\n\t" \
  50
+			 "ori r11, r11, 64\n\t" \
  51
+			 "wcsr PSW, r11\n\t" \
  52
+			 "xor r0, r0, r0" ::: "r11"); \
53 53
 } while(0);
54 54
 
55 55
 #define disable_dtlb() do { \
56  
-	asm volatile	("xor r11, r11, r11\n\t" \
57  
-			 "ori r11, r11, 0x9\n\t" \
58  
-			 "wcsr tlbctrl, r11\n\t" \
  56
+	asm volatile	("rcsr r11, PSW\n\t" \
  57
+			 "mvi r10, ~(64)\n\t" \
  58
+			 "and r11, r11, r10\n\t" \
  59
+			 "wcsr PSW, r11\n\t" \
59 60
 			 "xor r0, r0, r0\n\t" \
60 61
 			 "xor r0, r0, r0\n\t" \
61  
-			 "xor r0, r0, r0":::"r11"); \
  62
+			 "xor r0, r0, r0" ::: "r11", "r10"); \
62 63
 } while(0);
63 64
 
64 65
 #define enable_itlb() do { \
65  
-	asm volatile	("xor r11, r11, r11\n\t" \
66  
-			 "ori r11, r11, 0x10\n\t" \
67  
-			 "wcsr tlbctrl, r11\n\t" \
  66
+	asm volatile	("rcsr r11, PSW\n\t" \
  67
+			 "ori r11, r11, 0x8\n\t" \
  68
+			 "wcsr PSW, r11\n\t" \
68 69
 			 "xor r0, r0, r0\n\t" \
69 70
 			 "xor r0, r0, r0\n\t" \
70 71
 			 "xor r0, r0, r0\n\t" \
71 72
 			 "xor r0, r0, r0\n\t":::"r11"); \
72 73
 } while(0);
73 74
 
74  
-#define LM32_CSR_PSW_ITLBE	"(0x8)"
75  
-
76 75
 #define disable_itlb() do { \
77 76
 	asm volatile ("rcsr r11, PSW\n\t" \
78 77
 		      "mvi r10, ~(0x8)\n\t" \
@@ -80,10 +79,6 @@ struct mmu_mapping {
80 79
 		      "wcsr PSW, r11\n\t" ::: "r10", "r11"); \
81 80
 } while (0);
82 81
 
83  
-// FIXME : We MUST replace the following macro with a function which
84  
-// enables ITLB using two different methods depending on whether
85  
-// branch will be predicted as taken or non-taken
86  
-
87 82
 #define call_function_with_itlb_enabled(function) do { \
88 83
 	asm volatile	("rcsr r11, PSW\n\t" \
89 84
 			 "ori r11, r11, 0x8\n\t" \
51  software/libhal/mmu.c
@@ -36,11 +36,10 @@ inline void mmu_dtlb_map(unsigned int vpfn, unsigned int pfn)
36 36
 
37 37
 	asm volatile	("ori %0, %0, 1\n\t"
38 38
 			 "wcsr tlbpaddr, %0" :: "r"(pfn) : );
39  
-
  39
+/*
40 40
 	asm volatile	("xor r11, r11, r11\n\t"
41 41
 			 "ori r11, r11, 0x5\n\t"
42  
-			 "wcsr tlbctrl, r11" ::: "r11");
43  
-
  42
+			 "wcsr tlbctrl, r11" ::: "r11"); */
44 43
 }
45 44
 
46 45
 inline void mmu_itlb_map(unsigned int vpfn, unsigned int pfn)
@@ -50,42 +49,34 @@ inline void mmu_itlb_map(unsigned int vpfn, unsigned int pfn)
50 49
 
51 50
 	asm volatile	("wcsr tlbpaddr, %0" :: "r"(get_pfn(pfn)) : );
52 51
 
53  
-	asm volatile	("xor r11, r11, r11\n\t"
  52
+/*	asm volatile	("xor r11, r11, r11\n\t"
54 53
 			 "ori r11, r11, 0x4\n\t"
55  
-			 "wcsr tlbctrl, r11" ::: "r11");
  54
+			 "wcsr tlbctrl, r11" ::: "r11"); */
56 55
 }
57 56
 
58 57
 inline void mmu_dtlb_invalidate_line(unsigned int vaddr)
59 58
 {
60  
-	asm volatile ("ori %0, %0, 1\n\t"
  59
+	asm volatile ("ori %0, %0, 0x21\n\t"
61 60
 		      "wcsr tlbvaddr, %0" :: "r"(vaddr) : );
62  
-
63  
-	asm volatile ("xor r11, r11, r11\n\t"
64  
-		      "ori r11, r11, 0x21\n\t"
65  
-		      "wcsr tlbctrl, r11" ::: "r11");
66 61
 }
67 62
 
68 63
 inline void mmu_itlb_invalidate_line(unsigned int vaddr)
69 64
 {
70  
-	asm volatile ("ori %0, %0, 0\n\t"
  65
+	asm volatile ("ori %0, %0, 0x20\n\t"
71 66
 		      "wcsr tlbvaddr, %0" :: "r"(vaddr) : );
72  
-
73  
-	asm volatile ("xor r11, r11, r11\n\t"
74  
-		      "ori r11, r11, 0x20\n\t"
75  
-		      "wcsr tlbctrl, r11" ::: "r11");
76 67
 }
77 68
 
78 69
 inline void mmu_dtlb_invalidate(void)
79 70
 {
80 71
 	register unsigned int cmd = DTLB_CTRL_FLUSH_CMD;
81  
-	asm volatile("wcsr tlbctrl, %0" :: "r"(cmd) : );
  72
+//	asm volatile("wcsr tlbctrl, %0" :: "r"(cmd) : );
82 73
 
83 74
 }
84 75
 
85 76
 inline void mmu_itlb_invalidate(void)
86 77
 {
87 78
 	register unsigned int cmd = ITLB_CTRL_FLUSH_CMD;
88  
-	asm volatile("wcsr tlbctrl, %0" :: "r"(cmd) : );
  79
+//	asm volatile("wcsr tlbctrl, %0" :: "r"(cmd) : );
89 80
 
90 81
 }
91 82
 
@@ -103,11 +94,17 @@ unsigned int read_word_with_mmu_enabled(unsigned int vaddr)
103 94
 	cmd1  = DTLB_CTRL_ENABLE_CMD;
104 95
 	cmd2 = DTLB_CTRL_DISABLE_CMD;
105 96
 
106  
-	asm volatile("wcsr tlbctrl, %2\n\t" // Activates the MMU
  97
+	asm volatile("rcsr r11, PSW\n\t"
  98
+		     "ori r11, r11, 64\n\t"
  99
+		     "wcsr PSW, r11\n\t" // Activates the MMU
  100
+		     //"wcsr tlbctrl, %2\n\t" // Activates the MMU
107 101
 		     "xor r0, r0, r0\n\t"
108 102
 		     "lw  %0, (%1+0)\n\t" // Reads from virtual address "addr"
109  
-		     "wcsr tlbctrl, %3\n\t" // Disactivates the MMU
110  
-		     "xor r0, r0, r0\n\t" : "=&r"(data) : "r"(vaddr), "r"(cmd1), "r"(cmd2) : 
  103
+		     "mvi r10, ~(64)\n\t"
  104
+		     "and r11, r11, r10\n\t"
  105
+		     "wcsr PSW, r11\n\t" // Disactivates the MMU
  106
+		     //"wcsr tlbctrl, %3\n\t" // Disactivates the MMU
  107
+		     "xor r0, r0, r0\n\t" : "=&r"(data) : "r"(vaddr)/*, "r"(cmd1), "r"(cmd2)*/ : "r11", "r10"
111 108
 	);
112 109
 
113 110
 	return data;
@@ -116,15 +113,15 @@ unsigned int read_word_with_mmu_enabled(unsigned int vaddr)
116 113
 unsigned int write_word_with_mmu_enabled(register unsigned int vaddr, register unsigned int data)
117 114
 {
118 115
 	asm volatile(
119  
-		"xor r11, r11, r11\n\t"
120  
-		"ori r11, r11, 0x11\n\t"
121  
-		"wcsr tlbctrl, r11\n\t" // Activates the MMU
  116
+		"rcsr r11, PSW\n\t"
  117
+		"ori r11, r11, 64\n\t"
  118
+		"wcsr PSW, r11\n\t" // Activates the MMU
122 119
 		"xor r0, r0, r0\n\t"
123 120
 		"sw  (%0 + 0), %1\n\t" // Reads from virtual address "addr"
124  
-		"xor r11, r11, r11\n\t"
125  
-		"ori r11, r11, 0x9\n\t"
126  
-		"wcsr tlbctrl, r11\n\t" // Disactivates the MMU
127  
-		"xor r0, r0, r0\n\t" :: "r"(vaddr), "r"(data) : "r11"
  121
+		"mvi r10, ~(64)\n\t"
  122
+		"and r11, r11, r10\n\t"
  123
+		"wcsr PSW, r11\n\t" // Disactivates the MMU
  124
+		"xor r0, r0, r0\n\t" :: "r"(vaddr), "r"(data) : "r11", "r10"
128 125
 	);
129 126
 }
130 127
 /*

0 notes on commit 582617f

Please sign in to comment.
Something went wrong with that request. Please try again.