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Add ITLB and PSW CSR register and a little bit of refactoring

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commit 70b5f4839fd7f8053dfb7b5e06802be573579035 1 parent 2c801a4
Yann Sionneau authored July 22, 2012
18  boards/milkymist-one/rtl/lm32_include.v
@@ -98,6 +98,7 @@
98 98
 `define CFG_GDBSTUB_ENABLED
99 99
 //`define CFG_RANDOM_WISHBONE_LATENCY
100 100
 //`define CFG_VERBOSE_DISPLAY_ENABLED
  101
+//`define CFG_PIPELINE_TRACES
101 102
 
102 103
 // Enable MMU
103 104
 `define CFG_MMU_ENABLED
@@ -292,12 +293,28 @@
292 293
 `define LM32_CSR_WP3                    `LM32_CSR_WIDTH'h1b
293 294
 `endif
294 295
 `ifdef CFG_MMU_ENABLED
  296
+`define LM32_CSR_PSW			`LM32_CSR_WIDTH'hb
295 297
 `define LM32_CSR_TLB_CTRL		`LM32_CSR_WIDTH'h1c
296 298
 `define LM32_CSR_TLB_VADDRESS		`LM32_CSR_WIDTH'h1d
297 299
 `define LM32_CSR_TLB_PADDRESS		`LM32_CSR_WIDTH'h1e
298 300
 `define LM32_CSR_TLB_DBG		`LM32_CSR_WIDTH'h1f
299 301
 `endif
300 302
 
  303
+`ifdef CFG_MMU_ENABLED
  304
+`define LM32_CSR_PSW_IE			`LM32_WORD_WIDTH'h0
  305
+`define LM32_CSR_PSW_EIE		`LM32_WORD_WIDTH'h1
  306
+`define LM32_CSR_PSW_BIE		`LM32_WORD_WIDTH'h2
  307
+`define LM32_CSR_PSW_ITLBE		`LM32_WORD_WIDTH'h3
  308
+`define LM32_CSR_PSW_EITLBE		`LM32_WORD_WIDTH'h4
  309
+`define LM32_CSR_PSW_BITLBE		`LM32_WORD_WIDTH'h5
  310
+`define LM32_CSR_PSW_DTLBE		`LM32_WORD_WIDTH'h6
  311
+`define LM32_CSR_PSW_EDTLBE		`LM32_WORD_WIDTH'h7
  312
+`define LM32_CSR_PSW_BDTLBE		`LM32_WORD_WIDTH'h8
  313
+`define LM32_CSR_PSW_USR		`LM32_WORD_WIDTH'h9
  314
+`define LM32_CSR_PSW_EUSR		`LM32_WORD_WIDTH'ha
  315
+`define LM32_CSR_PSW_BUSR		`LM32_WORD_WIDTH'hb
  316
+`endif
  317
+
301 318
 // Values for WPC CSR
302 319
 `define LM32_WPC_C_RNG                  1:0
303 320
 `define LM32_WPC_C_DISABLED             2'b00
@@ -317,6 +334,7 @@
317 334
 `define LM32_EID_INTERRUPT              `LM32_EID_WIDTH'h6
318 335
 `define LM32_EID_SCALL                  `LM32_EID_WIDTH'h7
319 336
 `define LM32_EID_DTLB_MISS              `LM32_EID_WIDTH'h8
  337
+`define LM32_EID_ITLB_MISS              `LM32_EID_WIDTH'h9
320 338
 
321 339
 // Pipeline result selection mux controls
322 340
 
129  cores/lm32/rtl/lm32_cpu.v
@@ -616,7 +616,8 @@ wire mc_stall_request_x;                        // Multi-cycle arithmetic unit s
616 616
 wire [`LM32_WORD_RNG] mc_result_x;
617 617
 `endif
618 618
 
619  
-wire [`LM32_WORD_RNG] load_store_csr_read_data_x;// Data read from load store CSRs
  619
+wire [`LM32_WORD_RNG] load_store_csr_read_data_x;// Data read from load store unit CSRs
  620
+wire [`LM32_WORD_RNG] instruction_csr_read_data_x;// Data read from instruction unit CSRs
620 621
 // From CSRs
621 622
 `ifdef CFG_INTERRUPTS_ENABLED
622 623
 wire [`LM32_WORD_RNG] interrupt_csr_read_data_x;// Data read from interrupt CSRs
@@ -629,11 +630,32 @@ reg [`LM32_WORD_RNG] cc;                        // Cycle counter CSR
629 630
 reg [`LM32_WORD_RNG] csr_read_data_x;           // Data read from CSRs
630 631
 
631 632
 // To/from instruction unit
  633
+`ifdef CFG_PIPELINE_TRACES
  634
+wire [`LM32_PC_RNG] pc_a;
  635
+`endif
632 636
 wire [`LM32_PC_RNG] pc_f;                       // PC of instruction in F stage
633 637
 wire [`LM32_PC_RNG] pc_d;                       // PC of instruction in D stage
634 638
 wire [`LM32_PC_RNG] pc_x;                       // PC of instruction in X stage
635 639
 wire [`LM32_PC_RNG] pc_m;                       // PC of instruction in M stage
636 640
 wire [`LM32_PC_RNG] pc_w;                       // PC of instruction in W stage
  641
+
  642
+`ifdef CFG_PIPELINE_TRACES
  643
+always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  644
+begin
  645
+	if (~rst_i)
  646
+	begin
  647
+		if (~stall_a)
  648
+			$display("[%t] Addressing inst @ 0x%08X", $time, pc_a);
  649
+		if (~stall_f)
  650
+			$display("[%t] Fetching   inst @ 0x%08X", $time, pc_f);
  651
+		if (~stall_d)
  652
+			$display("[%t] Decoding   inst @ 0x%08X", $time, pc_d);
  653
+		if (~stall_x)
  654
+			$display("[%t] Executing  inst @ 0x%08X", $time, pc_x);
  655
+	end
  656
+end
  657
+`endif
  658
+
637 659
 `ifdef CFG_TRACE_ENABLED
638 660
 reg [`LM32_PC_RNG] pc_c;                        // PC of last commited instruction
639 661
 `endif
@@ -777,6 +799,12 @@ reg data_bus_error_seen;                        // Indicates if a data bus error
777 799
 reg ext_break_r;
778 800
 `endif
779 801
 
  802
+`ifdef CFG_MMU_ENABLED
  803
+wire dtlb_miss_exception;
  804
+wire itlb_miss_exception;
  805
+reg [`LM32_WORD_RNG] lm32_csr_psw_reg;
  806
+`endif
  807
+
780 808
 /////////////////////////////////////////////////////
781 809
 // Functions
782 810
 /////////////////////////////////////////////////////
@@ -819,6 +847,9 @@ lm32_instruction_unit #(
819 847
     .branch_target_x        (branch_target_x),
820 848
 `endif
821 849
     .exception_m            (exception_m),
  850
+`ifdef CFG_MMU_ENABLED
  851
+    .exception_x            (exception_x),
  852
+`endif
822 853
     .branch_taken_m         (branch_taken_m),
823 854
     .branch_mispredict_taken_m (branch_mispredict_taken_m),
824 855
     .branch_target_m        (branch_target_m),
@@ -834,7 +865,15 @@ lm32_instruction_unit #(
834 865
     .dcache_restart_request (dcache_restart_request),
835 866
     .dcache_refill_request  (dcache_refill_request),
836 867
     .dcache_refilling       (dcache_refilling),
837  
-`endif        
  868
+`endif
  869
+`ifdef CFG_MMU_ENABLED
  870
+    .csr		    (csr_x),
  871
+    .csr_write_data	    (operand_1_x),
  872
+    .csr_write_enable	    (csr_write_enable_q_x),
  873
+    .eret_q_x		    (eret_q_x),
  874
+    .csr_psw		    (lm32_csr_psw_reg),
  875
+    .q_x		    (q_x),
  876
+`endif
838 877
 `ifdef CFG_IWB_ENABLED
839 878
     // From Wishbone
840 879
     .i_dat_i                (I_DAT_I),
@@ -849,6 +888,9 @@ lm32_instruction_unit #(
849 888
 `endif
850 889
     // ----- Outputs -------
851 890
     // To pipeline
  891
+`ifdef CFG_PIPELINE_TRACES
  892
+    .pc_a		    (pc_a),
  893
+`endif
852 894
     .pc_f                   (pc_f),
853 895
     .pc_d                   (pc_d),
854 896
     .pc_x                   (pc_x),
@@ -863,6 +905,10 @@ lm32_instruction_unit #(
863 905
 `ifdef CFG_IROM_ENABLED
864 906
     .irom_data_m            (irom_data_m),
865 907
 `endif
  908
+`ifdef CFG_MMU_ENABLED
  909
+    .itlb_miss		    (itlb_miss_exception),
  910
+    .csr_read_data	    (instruction_csr_read_data_x),
  911
+`endif
866 912
 `ifdef CFG_IWB_ENABLED
867 913
     // To Wishbone
868 914
     .i_dat_o                (I_DAT_O),
@@ -967,8 +1013,6 @@ lm32_decoder decoder (
967 1013
     .csr_write_enable       (csr_write_enable_d)
968 1014
     ); 
969 1015
 
970  
-wire dtlb_miss_exception;
971  
-
972 1016
 // Load/store unit       
973 1017
 lm32_load_store_unit #(
974 1018
     .associativity          (dcache_associativity),
@@ -1006,10 +1050,13 @@ lm32_load_store_unit #(
1006 1050
 `ifdef CFG_IROM_ENABLED
1007 1051
     .irom_data_m            (irom_data_m),
1008 1052
 `endif
  1053
+`ifdef CFG_MMU_ENABLED
1009 1054
     .csr		    (csr_x),
1010 1055
     .csr_write_data         (operand_1_x),
1011 1056
     .csr_write_enable       (csr_write_enable_q_x),
1012 1057
     .eret_q_x		    (eret_q_x),
  1058
+    .csr_psw		    (lm32_csr_psw_reg),
  1059
+`endif
1013 1060
     // From Wishbone
1014 1061
     .d_dat_i                (D_DAT_I),
1015 1062
     .d_ack_i                (D_ACK_I),
@@ -1031,8 +1078,10 @@ lm32_load_store_unit #(
1031 1078
 `endif
1032 1079
     .load_data_w            (load_data_w),
1033 1080
     .stall_wb_load          (stall_wb_load),
  1081
+`ifdef CFG_MMU_ENABLED
1034 1082
     .dtlb_miss		    (dtlb_miss_exception),
1035 1083
     .csr_read_data          (load_store_csr_read_data_x),
  1084
+`endif
1036 1085
     // To Wishbone
1037 1086
     .d_dat_o                (D_DAT_O),
1038 1087
     .d_adr_o                (D_ADR_O),
@@ -1771,7 +1820,7 @@ assign non_debug_exception_x = (system_call_exception == `TRUE)
1771 1820
                                )
1772 1821
 `endif
1773 1822
 `ifdef CFG_MMU_ENABLED
1774  
-			|| (dtlb_miss_exception == `TRUE)
  1823
+			|| (dtlb_miss_exception == `TRUE || itlb_miss_exception == `TRUE)
1775 1824
 `endif
1776 1825
                             ;
1777 1826
 
@@ -1797,7 +1846,7 @@ assign exception_x =           (system_call_exception == `TRUE)
1797 1846
                                )
1798 1847
 `endif
1799 1848
 `ifdef CFG_MMU_ENABLED
1800  
-			|| (dtlb_miss_exception == `TRUE)
  1849
+			|| (dtlb_miss_exception == `TRUE || itlb_miss_exception == `TRUE)
1801 1850
 `endif
1802 1851
                             ;
1803 1852
 `endif
@@ -1847,9 +1896,13 @@ begin
1847 1896
         eid_x = `LM32_EID_INTERRUPT;
1848 1897
     else
1849 1898
 `endif
1850  
-	if (dtlb_miss_exception == `TRUE )
  1899
+`ifdef CFG_MMU_ENABLED
  1900
+	if (dtlb_miss_exception == `TRUE)
1851 1901
 		eid_x = `LM32_EID_DTLB_MISS;
  1902
+	else if (itlb_miss_exception == `TRUE)
  1903
+		eid_x = `LM32_EID_ITLB_MISS;
1852 1904
 	else
  1905
+`endif
1853 1906
 		eid_x = `LM32_EID_SCALL;
1854 1907
 end
1855 1908
 
@@ -2144,11 +2197,69 @@ begin
2144 2197
 `endif
2145 2198
     `LM32_CSR_CFG2: csr_read_data_x = cfg2;
2146 2199
     `LM32_CSR_TLB_VADDRESS: csr_read_data_x = load_store_csr_read_data_x;
2147  
-      
  2200
+    `LM32_CSR_TLB_PADDRESS: csr_read_data_x = instruction_csr_read_data_x;
  2201
+    `LM32_CSR_PSW:	csr_read_data_x = lm32_csr_psw_reg;
2148 2202
     default:        csr_read_data_x = {`LM32_WORD_WIDTH{1'bx}};
2149 2203
     endcase
2150 2204
 end
2151 2205
 
  2206
+`ifdef CFG_MMU_ENABLED
  2207
+
  2208
+always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  2209
+begin
  2210
+	if (rst_i)
  2211
+	begin
  2212
+		lm32_csr_psw_reg <= `LM32_WORD_WIDTH'h0;
  2213
+	end
  2214
+	else
  2215
+	begin
  2216
+`ifdef CFG_DEBUG_ENABLED
  2217
+		if (non_debug_exception_q_w == `TRUE)
  2218
+		begin
  2219
+		    // Save and then clear ITLB enable
  2220
+		    lm32_csr_psw_reg[`LM32_CSR_PSW_EITLBE] <= lm32_csr_psw_reg[`LM32_CSR_PSW_ITLBE];
  2221
+		    lm32_csr_psw_reg[`LM32_CSR_PSW_ITLBE] <= `FALSE;
  2222
+		end
  2223
+		else if (debug_exception_q_w == `TRUE)
  2224
+		begin
  2225
+		    // Save and then clear TLB enable
  2226
+		    lm32_csr_psw_reg[`LM32_CSR_PSW_BITLBE] <= lm32_csr_psw_reg[`LM32_CSR_PSW_ITLBE];
  2227
+		    lm32_csr_psw_reg[`LM32_CSR_PSW_ITLBE] <= `FALSE;
  2228
+		end
  2229
+`else
  2230
+		if (exception_q_w == `TRUE)
  2231
+		begin
  2232
+		    // Save and then clear ITLB enable
  2233
+		    lm32_csr_psw_reg[`LM32_CSR_PSW_EITLBE] <= lm32_csr_psw_reg[`LM32_CSR_PSW_ITLBE];
  2234
+		    lm32_csr_psw_reg[`LM32_CSR_PSW_ITLBE] <= `FALSE;
  2235
+		end
  2236
+`endif
  2237
+		else if (stall_x == `FALSE)
  2238
+		begin
  2239
+		    if (eret_q_x == `TRUE)
  2240
+			// Restore ITLB enable
  2241
+			lm32_csr_psw_reg[`LM32_CSR_PSW_ITLBE] <= lm32_csr_psw_reg[`LM32_CSR_PSW_EITLBE];
  2242
+`ifdef CFG_DEBUG_ENABLED
  2243
+		    else if (bret_q_x == `TRUE)
  2244
+			// Restore ITLB enable
  2245
+			lm32_csr_psw_reg[`LM32_CSR_PSW_ITLBE] <= lm32_csr_psw_reg[`LM32_CSR_PSW_BITLBE];
  2246
+`endif
  2247
+		    else if (csr_write_enable_q_x == `TRUE)
  2248
+		    begin
  2249
+			// Handle wcsr write
  2250
+			case (csr_x)
  2251
+			// operand_1_x is csr_write_data
  2252
+			`LM32_CSR_PSW:
  2253
+				lm32_csr_psw_reg <= operand_1_x;
  2254
+			`LM32_CSR_IE:
  2255
+				lm32_csr_psw_reg[2:0] <= operand_1_x[2:0];
  2256
+			endcase
  2257
+		    end
  2258
+		end
  2259
+	end
  2260
+end
  2261
+`endif
  2262
+
2152 2263
 /////////////////////////////////////////////////////
2153 2264
 // Sequential Logic
2154 2265
 /////////////////////////////////////////////////////
@@ -2231,7 +2342,7 @@ begin
2231 2342
 end
2232 2343
 `endif
2233 2344
 
2234  
-// Valid bits to indicate whether an instruction in a partcular pipeline stage is valid or not  
  2345
+// Valid bits to indicate whether an instruction in a particular pipeline stage is valid or not
2235 2346
 
2236 2347
 `ifdef CFG_ICACHE_ENABLED
2237 2348
 `ifdef CFG_DCACHE_ENABLED
355  cores/lm32/rtl/lm32_dcache.v
@@ -2,7 +2,7 @@
2 2
 //   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
3 3
 //   ------------------------------------------------------------------
4 4
 //   Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
5  
-//   ALL RIGHTS RESERVED 
  5
+//   ALL RIGHTS RESERVED
6 6
 //   ------------------------------------------------------------------
7 7
 //
8 8
 //   IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
@@ -11,7 +11,7 @@
11 11
 //
12 12
 //      Lattice Semiconductor grants permission to use this code
13 13
 //      pursuant to the terms of the Lattice Semiconductor Corporation
14  
-//      Open Source License Agreement.  
  14
+//      Open Source License Agreement.
15 15
 //
16 16
 //   Disclaimer:
17 17
 //
@@ -48,14 +48,11 @@
48 48
 //                  : cache memory. Additional parameters must be defined when
49 49
 //                  : invoking lm32_ram.v
50 50
 // =============================================================================
51  
-								 
  51
+
52 52
 `include "lm32_include.v"
53 53
 
54 54
 `ifdef CFG_DCACHE_ENABLED
55 55
 
56  
-`define LM32_KERNEL_MODE		 1
57  
-`define LM32_USER_MODE			 0
58  
-
59 56
 `define LM32_DC_ADDR_OFFSET_RNG          addr_offset_msb:addr_offset_lsb
60 57
 `define LM32_DC_ADDR_SET_RNG             addr_set_msb:addr_set_lsb
61 58
 `define LM32_DC_ADDR_TAG_RNG             addr_tag_msb:addr_tag_lsb
@@ -76,6 +73,7 @@
76 73
 `define LM32_DC_STATE_CHECK              3'b010
77 74
 `define LM32_DC_STATE_REFILL             3'b100
78 75
 
  76
+`ifdef CFG_MMU_ENABLED
79 77
 `define LM32_DTLB_CTRL_FLUSH		 	5'h1
80 78
 `define LM32_DTLB_CTRL_UPDATE		 	5'h2
81 79
 `define LM32_TLB_CTRL_SWITCH_TO_KERNEL_MODE	5'h4
@@ -85,14 +83,18 @@
85 83
 `define LM32_TLB_STATE_CHECK		 2'b01
86 84
 `define LM32_TLB_STATE_FLUSH		 2'b10
87 85
 
  86
+`define LM32_KERNEL_MODE		 1
  87
+`define LM32_USER_MODE			 0
  88
+`endif
  89
+
88 90
 /////////////////////////////////////////////////////
89 91
 // Module interface
90 92
 /////////////////////////////////////////////////////
91 93
 
92  
-module lm32_dcache ( 
  94
+module lm32_dcache (
93 95
     // ----- Inputs -----
94 96
     clk_i,
95  
-    rst_i,    
  97
+    rst_i,
96 98
     stall_a,
97 99
     stall_x,
98 100
     stall_m,
@@ -105,24 +107,28 @@ module lm32_dcache (
105 107
     refill_ready,
106 108
     refill_data,
107 109
     dflush,
  110
+`ifdef CFG_MMU_ENABLED
108 111
     csr,
109 112
     csr_write_data,
110 113
     csr_write_enable,
111 114
     exception_x,
112 115
     eret_q_x,
113 116
     exception_m,
  117
+    csr_psw,
  118
+`endif
114 119
     // ----- Outputs -----
115 120
     stall_request,
116 121
     restart_request,
117 122
     refill_request,
118 123
     refill_address,
119 124
     refilling,
120  
-    load_data,
121  
-   // To pipeline
  125
+`ifdef CFG_MMU_ENABLED
122 126
     dtlb_miss_int,
123 127
     kernel_mode,
124 128
     pa,
125  
-    csr_read_data
  129
+    csr_read_data,
  130
+`endif
  131
+    load_data
126 132
     );
127 133
 
128 134
 /////////////////////////////////////////////////////
@@ -135,6 +141,8 @@ parameter bytes_per_line = 16;                          // Number of bytes per c
135 141
 parameter base_address = 0;                             // Base address of cachable memory
136 142
 parameter limit = 0;                                    // Limit (highest address) of cachable memory
137 143
 
  144
+`ifdef CFG_MMU_ENABLED
  145
+
138 146
 parameter dtlb_sets = 1024;				// Number of lines of DTLB
139 147
 parameter page_size = 4096;				// System page size
140 148
 
@@ -167,6 +175,7 @@ localparam addr_dtlb_tag_msb = addr_dtlb_tag_lsb + addr_dtlb_tag_width - 1;
167 175
 `define LM32_DTLB_ADDR_TAG_RNG		addr_dtlb_tag_msb:addr_dtlb_tag_lsb
168 176
 `define LM32_DTLB_VALID_BIT		vpfn_width+addr_dtlb_tag_width
169 177
 
  178
+`endif
170 179
 
171 180
 localparam addr_offset_width = clogb2(bytes_per_line)-1-2;
172 181
 localparam addr_set_width = clogb2(sets)-1;
@@ -201,6 +210,7 @@ input [`LM32_WORD_RNG] refill_data;                     // Refill data
201 210
 
202 211
 input dflush;                                           // Indicates cache should be flushed
203 212
 
  213
+`ifdef CFG_MMU_ENABLED
204 214
 
205 215
 input [`LM32_CSR_RNG] csr;				// CSR read/write index
206 216
 input [`LM32_WORD_RNG] csr_write_data;			// Data to write to specified CSR
@@ -208,19 +218,19 @@ input csr_write_enable;					// CSR write enable
208 218
 input exception_x;					// An exception occured in the X stage
209 219
 input exception_m;
210 220
 input eret_q_x;
  221
+input [`LM32_WORD_RNG] csr_psw;
  222
+
  223
+`endif
211 224
 
212 225
 /////////////////////////////////////////////////////
213 226
 // Outputs
214 227
 /////////////////////////////////////////////////////
215 228
 
216  
-output csr_read_data;
217  
-wire [`LM32_WORD_RNG] csr_read_data;
218  
-
219 229
 output stall_request;                                   // Request pipeline be stalled because cache is busy
220 230
 wire   stall_request;
221 231
 output restart_request;                                 // Request to restart instruction that caused the cache miss
222 232
 reg    restart_request;
223  
-output refill_request;                                  // Request a refill 
  233
+output refill_request;                                  // Request a refill
224 234
 reg    refill_request;
225 235
 output [`LM32_WORD_RNG] refill_address;                 // Address to refill from
226 236
 reg    [`LM32_WORD_RNG] refill_address;
@@ -229,13 +239,21 @@ reg    refilling;
229 239
 output [`LM32_WORD_RNG] load_data;                      // Data read from cache
230 240
 wire   [`LM32_WORD_RNG] load_data;
231 241
 
  242
+`ifdef CFG_MMU_ENABLED
  243
+
232 244
 output kernel_mode;
233 245
 wire kernel_mode;
234  
-
  246
+output csr_read_data;
  247
+wire [`LM32_WORD_RNG] csr_read_data;
235 248
 output dtlb_miss_int;
  249
+wire dtlb_miss_int;
  250
+output [`LM32_WORD_RNG] pa;
  251
+wire [`LM32_WORD_RNG] pa;
  252
+
  253
+`endif
236 254
 
237 255
 /////////////////////////////////////////////////////
238  
-// Internal nets and registers 
  256
+// Internal nets and registers
239 257
 /////////////////////////////////////////////////////
240 258
 
241 259
 wire read_port_enable;                                  // Cache memory read port clock enable
@@ -252,7 +270,7 @@ wire [`LM32_DC_TMEM_ADDR_RNG] tmem_read_address;        // Tag memory read addre
252 270
 wire [`LM32_DC_TMEM_ADDR_RNG] tmem_write_address;       // Tag memory write address
253 271
 wire [`LM32_DC_DMEM_ADDR_RNG] dmem_read_address;        // Data memory read address
254 272
 wire [`LM32_DC_DMEM_ADDR_RNG] dmem_write_address;       // Data memory write address
255  
-wire [`LM32_DC_TAGS_RNG] tmem_write_data;               // Tag memory write data        
  273
+wire [`LM32_DC_TAGS_RNG] tmem_write_data;               // Tag memory write data
256 274
 reg [`LM32_WORD_RNG] dmem_write_data;                   // Data memory write data
257 275
 
258 276
 reg [`LM32_DC_STATE_RNG] state;                         // Current state of FSM
@@ -272,13 +290,8 @@ wire dtlb_data_read_port_enable;
272 290
 wire dtlb_write_port_enable;
273 291
 wire [vpfn_width + addr_dtlb_tag_width + 1 - 1:0] dtlb_write_data; // +1 is for valid_bit
274 292
 wire [vpfn_width + addr_dtlb_tag_width + 1 - 1:0] dtlb_read_data; // +1 is for valid_bit
275  
-
276 293
 wire [`LM32_WORD_RNG] physical_address;
277 294
 
278  
-wire [`LM32_WORD_RNG] pa;
279  
-output [`LM32_WORD_RNG] pa;
280  
-reg [`LM32_WORD_RNG] latest_store_tlb_lookup; 
281  
-
282 295
 assign pa = physical_address;
283 296
 
284 297
 reg kernel_mode_reg = `LM32_KERNEL_MODE;
@@ -286,7 +299,7 @@ wire switch_to_kernel_mode;
286 299
 wire switch_to_user_mode;
287 300
 reg [`LM32_WORD_RNG] dtlb_update_vaddr_csr_reg = `LM32_WORD_WIDTH'd0;
288 301
 reg [`LM32_WORD_RNG] dtlb_update_paddr_csr_reg = `LM32_WORD_WIDTH'd0;
289  
-reg [1:0] dtlb_state = `LM32_TLB_STATE_CHECK;
  302
+reg [1:0] dtlb_state;
290 303
 reg [`LM32_WORD_RNG] dtlb_ctrl_csr_reg = `LM32_WORD_WIDTH'd0;
291 304
 reg dtlb_updating;
292 305
 reg [addr_dtlb_index_width-1:0] dtlb_update_set;
@@ -294,7 +307,6 @@ reg dtlb_flushing;
294 307
 reg [addr_dtlb_index_width-1:0] dtlb_flush_set;
295 308
 wire dtlb_miss;
296 309
 reg dtlb_miss_q = `FALSE;
297  
-wire dtlb_miss_int;
298 310
 reg [`LM32_WORD_RNG] dtlb_miss_addr;
299 311
 wire dtlb_data_valid;
300 312
 wire [`LM32_DTLB_LOOKUP_RANGE] dtlb_lookup;
@@ -313,15 +325,15 @@ assign kernel_mode = kernel_mode_reg;
313 325
 // Instantiations
314 326
 /////////////////////////////////////////////////////
315 327
 
316  
-
  328
+`ifdef CFG_MMU_ENABLED
317 329
 // DTLB instantiation
318  
-lm32_ram 
  330
+lm32_ram
319 331
   #(
320 332
     // ----- Parameters -------
321 333
     .data_width (vpfn_width + addr_dtlb_tag_width + 1),
322 334
     .address_width (addr_dtlb_index_width)
323 335
 // Modified for Milkymist: removed non-portable RAM parameters
324  
-    ) dtlb_data_ram 
  336
+    ) dtlb_data_ram
325 337
     (
326 338
      // ----- Inputs -------
327 339
      .read_clk (clk_i),
@@ -332,34 +344,25 @@ lm32_ram
332 344
      .write_address (dtlb_data_write_address),
333 345
      .enable_write (`TRUE),
334 346
      .write_enable (dtlb_write_port_enable),
335  
-     .write_data (dtlb_write_data),    
  347
+     .write_data (dtlb_write_data),
336 348
      // ----- Outputs -------
337 349
      .read_data (dtlb_read_data)
338 350
      );
339  
-
340  
-`ifdef CFG_VERBOSE_DISPLAY_ENABLED
341  
-always @(posedge clk_i)
342  
-begin
343  
-	if (dtlb_write_port_enable)
344  
-	begin
345  
-		$display("[DTLB data : %d] Writing 0x%08X to 0x%08X", $time, dtlb_write_data, dtlb_data_write_address);
346  
-	end
347  
-end
348 351
 `endif
349 352
 
350 353
    generate
351  
-      for (i = 0; i < associativity; i = i + 1)    
  354
+      for (i = 0; i < associativity; i = i + 1)
352 355
 	begin : memories
353 356
 	   // Way data
354 357
            if (`LM32_DC_DMEM_ADDR_WIDTH < 11)
355 358
              begin : data_memories
356  
-		lm32_ram 
  359
+		lm32_ram
357 360
 		  #(
358 361
 		    // ----- Parameters -------
359 362
 		    .data_width (32),
360 363
 		    .address_width (`LM32_DC_DMEM_ADDR_WIDTH)
361 364
 // Modified for Milkymist: removed non-portable RAM parameters
362  
-		    ) way_0_data_ram 
  365
+		    ) way_0_data_ram
363 366
 		    (
364 367
 		     // ----- Inputs -------
365 368
 		     .read_clk (clk_i),
@@ -370,22 +373,22 @@ end
370 373
 		     .write_address (dmem_write_address),
371 374
 		     .enable_write (write_port_enable),
372 375
 		     .write_enable (way_dmem_we[i]),
373  
-		     .write_data (dmem_write_data),    
  376
+		     .write_data (dmem_write_data),
374 377
 		     // ----- Outputs -------
375 378
 		     .read_data (way_data[i])
376  
-		     );    
  379
+		     );
377 380
              end
378 381
            else
379 382
              begin
380  
-		for (j = 0; j < 4; j = j + 1)    
  383
+		for (j = 0; j < 4; j = j + 1)
381 384
 		  begin : byte_memories
382  
-		     lm32_ram 
  385
+		     lm32_ram
383 386
 		       #(
384 387
 			 // ----- Parameters -------
385 388
 			 .data_width (8),
386 389
 			 .address_width (`LM32_DC_DMEM_ADDR_WIDTH)
387 390
 // Modified for Milkymist: removed non-portable RAM parameters
388  
-			 ) way_0_data_ram 
  391
+			 ) way_0_data_ram
389 392
 			 (
390 393
 			  // ----- Inputs -------
391 394
 			  .read_clk (clk_i),
@@ -396,21 +399,21 @@ end
396 399
 			  .write_address (dmem_write_address),
397 400
 			  .enable_write (write_port_enable),
398 401
 			  .write_enable (way_dmem_we[i] & (store_byte_select[j] | refill)),
399  
-			  .write_data (dmem_write_data[(j+1)*8-1:j*8]),    
  402
+			  .write_data (dmem_write_data[(j+1)*8-1:j*8]),
400 403
 			  // ----- Outputs -------
401 404
 			  .read_data (way_data[i][(j+1)*8-1:j*8])
402 405
 			  );
403 406
 		  end
404 407
              end
405  
-	   
  408
+
406 409
 	   // Way tags
407  
-	   lm32_ram 
  410
+	   lm32_ram
408 411
 	     #(
409 412
 	       // ----- Parameters -------
410 413
 	       .data_width (`LM32_DC_TAGS_WIDTH),
411 414
 	       .address_width (`LM32_DC_TMEM_ADDR_WIDTH)
412 415
 // Modified for Milkymist: removed non-portable RAM parameters
413  
-	       ) way_0_tag_ram 
  416
+	       ) way_0_tag_ram
414 417
 	       (
415 418
 		// ----- Inputs -------
416 419
 		.read_clk (clk_i),
@@ -426,37 +429,13 @@ end
426 429
 		.read_data ({way_tag[i], way_valid[i]})
427 430
 		);
428 431
 	end
429  
-      
  432
+
430 433
    endgenerate
431 434
 
432 435
 /////////////////////////////////////////////////////
433 436
 // Combinational logic
434 437
 /////////////////////////////////////////////////////
435 438
 
436  
-// CSR Write
437  
-always @(posedge clk_i `CFG_RESET_SENSITIVITY)
438  
-begin
439  
-	if (rst_i == `TRUE)
440  
-	begin
441  
-		dtlb_ctrl_csr_reg <= `LM32_WORD_WIDTH'd0;
442  
-		dtlb_update_vaddr_csr_reg <= `LM32_WORD_WIDTH'd0;
443  
-		dtlb_update_paddr_csr_reg <= `LM32_WORD_WIDTH'd0;
444  
-	end
445  
-	else
446  
-	begin
447  
-		if (csr_write_enable)
448  
-		begin
449  
-			case (csr)
450  
-			`LM32_CSR_TLB_CTRL:	if (csr_write_data[0]) dtlb_ctrl_csr_reg[31:1] <= csr_write_data[31:1];
451  
-			`LM32_CSR_TLB_VADDRESS: if (csr_write_data[0]) dtlb_update_vaddr_csr_reg[31:1] <= csr_write_data[31:1];
452  
-			`LM32_CSR_TLB_PADDRESS: if (csr_write_data[0]) dtlb_update_paddr_csr_reg[31:1] <= csr_write_data[31:1];
453  
-			endcase
454  
-		end
455  
-		dtlb_ctrl_csr_reg[0] <= 0;
456  
-		dtlb_update_vaddr_csr_reg[0] <= 0;
457  
-		dtlb_update_paddr_csr_reg[0] <= 0;
458  
-	end
459  
-end
460 439
 
461 440
 
462 441
 
@@ -465,25 +444,24 @@ generate
465 444
     for (i = 0; i < associativity; i = i + 1)
466 445
     begin : match
467 446
 
468  
-assign dtlb_read_tag = dtlb_read_data[`LM32_DTLB_TAG_RANGE];
469  
-assign dtlb_data_valid = dtlb_read_data[`LM32_DTLB_VALID_BIT];
470  
-assign dtlb_lookup = dtlb_read_data[`LM32_DTLB_LOOKUP_RANGE];
471  
-
472  
-assign way_match[i] = (kernel_mode_reg == `LM32_KERNEL_MODE) ?
473  
-		      ({way_tag[i], way_valid[i]} == {address_m[`LM32_DC_ADDR_TAG_RNG], `TRUE})
474  
-		      : ({way_tag[i], way_valid[i]} == {dtlb_lookup, `TRUE});
  447
+assign way_match[i] = 
  448
+`ifdef CFG_MMU_ENABLED
  449
+			(dtlb_enabled == `TRUE) ?
  450
+			({way_tag[i], way_valid[i]} == {dtlb_lookup, `TRUE}) : 
  451
+`endif
  452
+		      ({way_tag[i], way_valid[i]} == {address_m[`LM32_DC_ADDR_TAG_RNG], `TRUE});
475 453
     end
476 454
 endgenerate
477 455
 
478  
-// Select data from way that matched the address being read     
  456
+// Select data from way that matched the address being read
479 457
 generate
480  
-    if (associativity == 1)    
  458
+    if (associativity == 1)
481 459
 	 begin : data_1
482 460
 assign load_data = way_data[0];
483 461
     end
484 462
     else if (associativity == 2)
485 463
 	 begin : data_2
486  
-assign load_data = way_match[0] ? way_data[0] : way_data[1]; 
  464
+assign load_data = way_match[0] ? way_data[0] : way_data[1];
487 465
     end
488 466
 endgenerate
489 467
 
@@ -518,45 +496,26 @@ end
518 496
 endgenerate
519 497
 
520 498
 // Compute address to use to index into the data memories
521  
-generate 
  499
+generate
522 500
      if (bytes_per_line > 4)
523  
-assign dmem_write_address = (refill == `TRUE) 
  501
+assign dmem_write_address = (refill == `TRUE)
524 502
                             ? {refill_address[`LM32_DC_ADDR_SET_RNG], refill_offset}
525 503
                             : address_m[`LM32_DC_ADDR_IDX_RNG];
526 504
     else
527  
-assign dmem_write_address = (refill == `TRUE) 
  505
+assign dmem_write_address = (refill == `TRUE)
528 506
                             ? refill_address[`LM32_DC_ADDR_SET_RNG]
529 507
                             : address_m[`LM32_DC_ADDR_IDX_RNG];
530 508
 endgenerate
531 509
 assign dmem_read_address = address_x[`LM32_DC_ADDR_IDX_RNG];
532  
-// Compute address to use to index into the tag memories   
  510
+// Compute address to use to index into the tag memories
533 511
 assign tmem_write_address = (flushing == `TRUE)
534 512
                             ? flush_set
535 513
                             : refill_address[`LM32_DC_ADDR_SET_RNG];
536 514
 assign tmem_read_address = address_x[`LM32_DC_ADDR_SET_RNG];
537 515
 
538  
-// Compute address to use to index into the DTLB data memory
539  
-
540  
-assign dtlb_data_read_address = address_x[`LM32_DTLB_IDX_RNG];
541  
-assign dtlb_tag_read_address = address_x[`LM32_DTLB_IDX_RNG];
542  
-
543  
-// tlb_update_address will receive data from a CSR register
544  
-assign dtlb_data_write_address = dtlb_update_vaddr_csr_reg[`LM32_DTLB_IDX_RNG];
545  
-
546  
-assign dtlb_data_read_port_enable = (stall_x == `FALSE) || !stall_m;
547  
-assign dtlb_write_port_enable = dtlb_updating || dtlb_flushing;
548  
-
549  
-assign physical_address = (kernel_mode_reg == `LM32_KERNEL_MODE)
550  
-			    ? address_m
551  
-			    : {dtlb_lookup, address_m[`LM32_PAGE_OFFSET_RNG]};
552  
-
553  
-assign dtlb_write_data = (dtlb_flushing == `TRUE)
554  
-			 ? {`FALSE, {addr_dtlb_tag_width{1'b0}}, {vpfn_width{1'b0}}}
555  
-			 : {`TRUE, {dtlb_update_vaddr_csr_reg[`LM32_DTLB_ADDR_TAG_RNG]}, dtlb_update_paddr_csr_reg[`LM32_DTLB_ADDRESS_PFN_RNG]};
556  
-
557 516
 // Compute signal to indicate when we are on the last refill accesses
558  
-generate 
559  
-    if (bytes_per_line > 4)                            
  517
+generate
  518
+    if (bytes_per_line > 4)
560 519
 assign last_refill = refill_offset == {addr_offset_width{1'b1}};
561 520
     else
562 521
 assign last_refill = `TRUE;
@@ -571,12 +530,12 @@ assign valid_store = (store_q_m == `TRUE) && (check == `TRUE);
571 530
 
572 531
 // Compute data and tag memory write enables
573 532
 generate
574  
-    if (associativity == 1) 
575  
-    begin : we_1     
  533
+    if (associativity == 1)
  534
+    begin : we_1
576 535
 assign way_dmem_we[0] = (refill_ready == `TRUE) || ((valid_store == `TRUE) && (way_match[0] == `TRUE));
577 536
 assign way_tmem_we[0] = (refill_ready == `TRUE) || (flushing == `TRUE);
578  
-    end 
579  
-    else 
  537
+    end
  538
+    else
580 539
     begin : we_2
581 540
 assign way_dmem_we[0] = ((refill_ready == `TRUE) && (refill_way_select[0] == `TRUE)) || ((valid_store == `TRUE) && (way_match[0] == `TRUE));
582 541
 assign way_dmem_we[1] = ((refill_ready == `TRUE) && (refill_way_select[1] == `TRUE)) || ((valid_store == `TRUE) && (way_match[1] == `TRUE));
@@ -595,35 +554,39 @@ assign check = state[1];
595 554
 assign refill = state[2];
596 555
 
597 556
 assign miss = (~(|way_match)) && (load_q_m == `TRUE) && (stall_m == `FALSE) && (~dtlb_miss);
598  
-assign stall_request = (check == `FALSE) || (dtlb_state == `LM32_TLB_STATE_FLUSH && kernel_mode_reg != `LM32_KERNEL_MODE);
599  
-                      
  557
+assign stall_request = (check == `FALSE) || (dtlb_state == `LM32_TLB_STATE_FLUSH 
  558
+`ifdef CFG_MMU_ENABLED
  559
+			&& (dtlb_enabled == `TRUE)
  560
+`endif
  561
+			);
  562
+
600 563
 /////////////////////////////////////////////////////
601 564
 // Sequential logic
602 565
 /////////////////////////////////////////////////////
603 566
 
604 567
 // Record way selected for replacement on a cache miss
605 568
 generate
606  
-    if (associativity >= 2) 
607  
-    begin : way_select      
  569
+    if (associativity >= 2)
  570
+    begin : way_select
608 571
 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
609 572
 begin
610 573
     if (rst_i == `TRUE)
611 574
         refill_way_select <= {{associativity-1{1'b0}}, 1'b1};
612 575
     else
613  
-    begin        
  576
+    begin
614 577
         if (refill_request == `TRUE)
615 578
             refill_way_select <= {refill_way_select[0], refill_way_select[1]};
616 579
     end
617 580
 end
618  
-    end 
619  
-endgenerate   
  581
+    end
  582
+endgenerate
620 583
 
621 584
 // Record whether we are currently refilling
622 585
 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
623 586
 begin
624 587
     if (rst_i == `TRUE)
625 588
         refilling <= `FALSE;
626  
-    else 
  589
+    else
627 590
         refilling <= refill;
628 591
 end
629 592
 
@@ -638,18 +601,18 @@ begin
638 601
         refill_address <= {`LM32_WORD_WIDTH{1'b0}};
639 602
         restart_request <= `FALSE;
640 603
     end
641  
-    else 
  604
+    else
642 605
     begin
643 606
         case (state)
644 607
 
645  
-        // Flush the cache 
  608
+        // Flush the cache
646 609
         `LM32_DC_STATE_FLUSH:
647 610
         begin
648 611
             if (flush_set == {`LM32_DC_TMEM_ADDR_WIDTH{1'b0}})
649 612
                 state <= `LM32_DC_STATE_CHECK;
650 613
             flush_set <= flush_set - 1'b1;
651 614
         end
652  
-        
  615
+
653 616
         // Check for cache misses
654 617
         `LM32_DC_STATE_CHECK:
655 618
         begin
@@ -658,7 +621,11 @@ begin
658 621
             if (miss == `TRUE)
659 622
             begin
660 623
                 refill_request <= `TRUE;
  624
+`ifdef CFG_MMU_ENABLED
661 625
                 refill_address <= physical_address;
  626
+`else
  627
+		refill_address <= address_m;		
  628
+`endif
662 629
                 state <= `LM32_DC_STATE_REFILL;
663 630
             end
664 631
             else if (dflush == `TRUE)
@@ -678,28 +645,102 @@ begin
678 645
                 end
679 646
             end
680 647
         end
681  
-        
682  
-        endcase        
  648
+
  649
+        endcase
  650
+    end
  651
+end
  652
+
  653
+
  654
+generate
  655
+    if (bytes_per_line > 4)
  656
+    begin
  657
+// Refill offset
  658
+always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  659
+begin
  660
+    if (rst_i == `TRUE)
  661
+        refill_offset <= {addr_offset_width{1'b0}};
  662
+    else
  663
+    begin
  664
+        case (state)
  665
+
  666
+        // Check for cache misses
  667
+        `LM32_DC_STATE_CHECK:
  668
+        begin
  669
+            if (miss == `TRUE)
  670
+                refill_offset <= {addr_offset_width{1'b0}};
  671
+        end
  672
+
  673
+        // Refill a cache line
  674
+        `LM32_DC_STATE_REFILL:
  675
+        begin
  676
+            if (refill_ready == `TRUE)
  677
+                refill_offset <= refill_offset + 1'b1;
  678
+        end
  679
+
  680
+        endcase
683 681
     end
684 682
 end
  683
+    end
  684
+endgenerate
  685
+
  686
+`endif
685 687
 
  688
+`ifdef CFG_MMU_ENABLED
  689
+// Beginning of MMU specific code
  690
+
  691
+assign dtlb_enabled = csr_psw[`LM32_CSR_PSW_DTLBE];
  692
+
  693
+// Compute address to use to index into the DTLB data memory
  694
+
  695
+assign dtlb_data_read_address = address_x[`LM32_DTLB_IDX_RNG];
  696
+assign dtlb_tag_read_address = address_x[`LM32_DTLB_IDX_RNG];
  697
+
  698
+// tlb_update_address will receive data from a CSR register
  699
+assign dtlb_data_write_address = dtlb_update_vaddr_csr_reg[`LM32_DTLB_IDX_RNG];
  700
+
  701
+assign dtlb_data_read_port_enable = (stall_x == `FALSE) || !stall_m;
  702
+assign dtlb_write_port_enable = dtlb_updating || dtlb_flushing;
  703
+
  704
+assign physical_address = (dtlb_enabled == `FALSE)
  705
+			    ? address_m
  706
+			    : {dtlb_lookup, address_m[`LM32_PAGE_OFFSET_RNG]};
  707
+
  708
+assign dtlb_write_data = (dtlb_flushing == `TRUE)
  709
+			 ? {`FALSE, {addr_dtlb_tag_width{1'b0}}, {vpfn_width{1'b0}}}
  710
+			 : {`TRUE, {dtlb_update_vaddr_csr_reg[`LM32_DTLB_ADDR_TAG_RNG]}, dtlb_update_paddr_csr_reg[`LM32_DTLB_ADDRESS_PFN_RNG]};
  711
+
  712
+assign dtlb_read_tag = dtlb_read_data[`LM32_DTLB_TAG_RANGE];
  713
+assign dtlb_data_valid = dtlb_read_data[`LM32_DTLB_VALID_BIT];
  714
+assign dtlb_lookup = dtlb_read_data[`LM32_DTLB_LOOKUP_RANGE];
  715
+assign csr_read_data = dtlb_miss_addr;
  716
+assign dtlb_miss = (dtlb_enabled == `TRUE) && (load_q_m || store_q_m) && ~(dtlb_data_valid);
  717
+assign dtlb_miss_int = (dtlb_miss || dtlb_miss_q);
  718
+
  719
+// CSR Write
686 720
 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
687 721
 begin
688 722
 	if (rst_i == `TRUE)
689  
-		latest_store_tlb_lookup <= `LM32_WORD_WIDTH'd0;
  723
+	begin
  724
+		dtlb_ctrl_csr_reg <= `LM32_WORD_WIDTH'd0;
  725
+		dtlb_update_vaddr_csr_reg <= `LM32_WORD_WIDTH'd0;
  726
+		dtlb_update_paddr_csr_reg <= `LM32_WORD_WIDTH'd0;
  727
+	end
690 728
 	else
691 729
 	begin
692  
-		if (write_port_enable && (|way_dmem_we))
  730
+		if (csr_write_enable)
693 731
 		begin
694  
-			latest_store_tlb_lookup <= {dtlb_lookup, address_m[`LM32_PAGE_OFFSET_RNG]};
  732
+			case (csr)
  733
+			`LM32_CSR_TLB_CTRL:	if (csr_write_data[0]) dtlb_ctrl_csr_reg[31:1] <= csr_write_data[31:1];
  734
+			`LM32_CSR_TLB_VADDRESS: if (csr_write_data[0]) dtlb_update_vaddr_csr_reg[31:1] <= csr_write_data[31:1];
  735
+			`LM32_CSR_TLB_PADDRESS: if (csr_write_data[0]) dtlb_update_paddr_csr_reg[31:1] <= csr_write_data[31:1];
  736
+			endcase
695 737
 		end
  738
+		dtlb_ctrl_csr_reg[0] <= 0;
  739
+		dtlb_update_vaddr_csr_reg[0] <= 0;
  740
+		dtlb_update_paddr_csr_reg[0] <= 0;
696 741
 	end
697 742
 end
698 743
 
699  
-assign csr_read_data = dtlb_miss_addr;
700  
-
701  
-assign dtlb_miss = (kernel_mode_reg == `LM32_USER_MODE) && (load_q_m || store_q_m) && ~(dtlb_data_valid);
702  
-
703 744
 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
704 745
 begin
705 746
 	if (rst_i == `TRUE)
@@ -713,12 +754,11 @@ begin
713 754
 	end
714 755
 end
715 756
 
716  
-assign dtlb_miss_int = (dtlb_miss || dtlb_miss_q);
717  
-
718 757
 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
719 758
 begin
720 759
 	if (rst_i == `TRUE)
721 760
 	begin
  761
+		$display("DTLB STATE MACHINE RESET");
722 762
 		dtlb_flushing <= 1;
723 763
 		dtlb_flush_set <= {addr_dtlb_index_width{1'b1}};
724 764
 		dtlb_state <= `LM32_TLB_STATE_FLUSH;
@@ -782,10 +822,6 @@ begin
782 822
 	end
783 823
 end
784 824
 
785  
-assign switch_to_kernel_mode = (/*(kernel_mode_reg == `LM32_KERNEL_MODE) && */csr_write_enable && (csr == `LM32_CSR_TLB_CTRL) && csr_write_data[5:0] == {`LM32_TLB_CTRL_SWITCH_TO_KERNEL_MODE, 1'b1});
786  
-assign switch_to_user_mode = (/*(kernel_mode_reg == `LM32_KERNEL_MODE) && */csr_write_enable && (csr == `LM32_CSR_TLB_CTRL) && csr_write_data[5:0] == {`LM32_TLB_CTRL_SWITCH_TO_USER_MODE, 1'b1});
787  
-
788  
-
789 825
 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
790 826
 begin
791 827
 	if (rst_i == `TRUE)
@@ -799,39 +835,16 @@ begin
799 835
 	end
800 836
 end
801 837
 
802  
-generate
803  
-    if (bytes_per_line > 4)
804  
-    begin
805  
-// Refill offset
806  
-always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  838
+`ifdef CFG_VERBOSE_DISPLAY_ENABLED
  839
+always @(posedge clk_i)
807 840
 begin
808  
-    if (rst_i == `TRUE)
809  
-        refill_offset <= {addr_offset_width{1'b0}};
810  
-    else 
811  
-    begin
812  
-        case (state)
813  
-        
814  
-        // Check for cache misses
815  
-        `LM32_DC_STATE_CHECK:
816  
-        begin
817  
-            if (miss == `TRUE)
818  
-                refill_offset <= {addr_offset_width{1'b0}};
819  
-        end
820  
-
821  
-        // Refill a cache line
822  
-        `LM32_DC_STATE_REFILL:
823  
-        begin
824  
-            if (refill_ready == `TRUE)
825  
-                refill_offset <= refill_offset + 1'b1;
826  
-        end
827  
-        
828  
-        endcase        
829  
-    end
  841
+	if (dtlb_write_port_enable)
  842
+	begin
  843
+		$display("[DTLB data : %d] Writing 0x%08X to 0x%08X", $time, dtlb_write_data, dtlb_data_write_address);
  844
+	end
830 845
 end
831  
-    end
832  
-endgenerate
833  
-
834  
-endmodule
  846
+`endif
835 847
 
836 848
 `endif
837 849
 
  850
+endmodule
448  cores/lm32/rtl/lm32_icache.v
@@ -57,7 +57,6 @@
57 57
 `include "lm32_include.v"
58 58
 
59 59
 `ifdef CFG_ICACHE_ENABLED
60  
-
61 60
 `define LM32_IC_ADDR_OFFSET_RNG          addr_offset_msb:addr_offset_lsb
62 61
 `define LM32_IC_ADDR_SET_RNG             addr_set_msb:addr_set_lsb
63 62
 `define LM32_IC_ADDR_TAG_RNG             addr_tag_msb:addr_tag_lsb
@@ -79,6 +78,22 @@
79 78
 `define LM32_IC_STATE_CHECK              4'b0100
80 79
 `define LM32_IC_STATE_REFILL             4'b1000
81 80
 
  81
+`ifdef CFG_MMU_ENABLED
  82
+
  83
+`define LM32_ITLB_CTRL_FLUSH		 	5'h1
  84
+`define LM32_ITLB_CTRL_UPDATE		 	5'h2
  85
+`define LM32_TLB_CTRL_SWITCH_TO_KERNEL_MODE	5'h4
  86
+`define LM32_TLB_CTRL_SWITCH_TO_USER_MODE	5'h8
  87
+`define LM32_TLB_CTRL_INVALIDATE_ENTRY		5'h10
  88
+
  89
+`define LM32_TLB_STATE_CHECK		 2'b01
  90
+`define LM32_TLB_STATE_FLUSH		 2'b10
  91
+
  92
+`define LM32_KERNEL_MODE		 1
  93
+`define LM32_USER_MODE			 0
  94
+
  95
+`endif
  96
+
82 97
 /////////////////////////////////////////////////////
83 98
 // Module interface
84 99
 /////////////////////////////////////////////////////
@@ -89,8 +104,17 @@ module lm32_icache (
89 104
     rst_i,    
90 105
     stall_a,
91 106
     stall_f,
  107
+`ifdef CFG_MMU_ENABLED
  108
+    stall_x,
  109
+    stall_m,
  110
+`endif
92 111
     address_a,
93 112
     address_f,
  113
+`ifdef CFG_MMU_ENABLED
  114
+    pc_x,
  115
+    pc_m,
  116
+    pc_w,
  117
+`endif
94 118
     read_enable_f,
95