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Add ITLB and PSW CSR register and a little bit of refactoring

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commit 70b5f4839fd7f8053dfb7b5e06802be573579035 1 parent 2c801a4
@fallen authored
View
18 boards/milkymist-one/rtl/lm32_include.v
@@ -98,6 +98,7 @@
`define CFG_GDBSTUB_ENABLED
//`define CFG_RANDOM_WISHBONE_LATENCY
//`define CFG_VERBOSE_DISPLAY_ENABLED
+//`define CFG_PIPELINE_TRACES
// Enable MMU
`define CFG_MMU_ENABLED
@@ -292,12 +293,28 @@
`define LM32_CSR_WP3 `LM32_CSR_WIDTH'h1b
`endif
`ifdef CFG_MMU_ENABLED
+`define LM32_CSR_PSW `LM32_CSR_WIDTH'hb
`define LM32_CSR_TLB_CTRL `LM32_CSR_WIDTH'h1c
`define LM32_CSR_TLB_VADDRESS `LM32_CSR_WIDTH'h1d
`define LM32_CSR_TLB_PADDRESS `LM32_CSR_WIDTH'h1e
`define LM32_CSR_TLB_DBG `LM32_CSR_WIDTH'h1f
`endif
+`ifdef CFG_MMU_ENABLED
+`define LM32_CSR_PSW_IE `LM32_WORD_WIDTH'h0
+`define LM32_CSR_PSW_EIE `LM32_WORD_WIDTH'h1
+`define LM32_CSR_PSW_BIE `LM32_WORD_WIDTH'h2
+`define LM32_CSR_PSW_ITLBE `LM32_WORD_WIDTH'h3
+`define LM32_CSR_PSW_EITLBE `LM32_WORD_WIDTH'h4
+`define LM32_CSR_PSW_BITLBE `LM32_WORD_WIDTH'h5
+`define LM32_CSR_PSW_DTLBE `LM32_WORD_WIDTH'h6
+`define LM32_CSR_PSW_EDTLBE `LM32_WORD_WIDTH'h7
+`define LM32_CSR_PSW_BDTLBE `LM32_WORD_WIDTH'h8
+`define LM32_CSR_PSW_USR `LM32_WORD_WIDTH'h9
+`define LM32_CSR_PSW_EUSR `LM32_WORD_WIDTH'ha
+`define LM32_CSR_PSW_BUSR `LM32_WORD_WIDTH'hb
+`endif
+
// Values for WPC CSR
`define LM32_WPC_C_RNG 1:0
`define LM32_WPC_C_DISABLED 2'b00
@@ -317,6 +334,7 @@
`define LM32_EID_INTERRUPT `LM32_EID_WIDTH'h6
`define LM32_EID_SCALL `LM32_EID_WIDTH'h7
`define LM32_EID_DTLB_MISS `LM32_EID_WIDTH'h8
+`define LM32_EID_ITLB_MISS `LM32_EID_WIDTH'h9
// Pipeline result selection mux controls
View
129 cores/lm32/rtl/lm32_cpu.v
@@ -616,7 +616,8 @@ wire mc_stall_request_x; // Multi-cycle arithmetic unit s
wire [`LM32_WORD_RNG] mc_result_x;
`endif
-wire [`LM32_WORD_RNG] load_store_csr_read_data_x;// Data read from load store CSRs
+wire [`LM32_WORD_RNG] load_store_csr_read_data_x;// Data read from load store unit CSRs
+wire [`LM32_WORD_RNG] instruction_csr_read_data_x;// Data read from instruction unit CSRs
// From CSRs
`ifdef CFG_INTERRUPTS_ENABLED
wire [`LM32_WORD_RNG] interrupt_csr_read_data_x;// Data read from interrupt CSRs
@@ -629,11 +630,32 @@ reg [`LM32_WORD_RNG] cc; // Cycle counter CSR
reg [`LM32_WORD_RNG] csr_read_data_x; // Data read from CSRs
// To/from instruction unit
+`ifdef CFG_PIPELINE_TRACES
+wire [`LM32_PC_RNG] pc_a;
+`endif
wire [`LM32_PC_RNG] pc_f; // PC of instruction in F stage
wire [`LM32_PC_RNG] pc_d; // PC of instruction in D stage
wire [`LM32_PC_RNG] pc_x; // PC of instruction in X stage
wire [`LM32_PC_RNG] pc_m; // PC of instruction in M stage
wire [`LM32_PC_RNG] pc_w; // PC of instruction in W stage
+
+`ifdef CFG_PIPELINE_TRACES
+always @(posedge clk_i `CFG_RESET_SENSITIVITY)
+begin
+ if (~rst_i)
+ begin
+ if (~stall_a)
+ $display("[%t] Addressing inst @ 0x%08X", $time, pc_a);
+ if (~stall_f)
+ $display("[%t] Fetching inst @ 0x%08X", $time, pc_f);
+ if (~stall_d)
+ $display("[%t] Decoding inst @ 0x%08X", $time, pc_d);
+ if (~stall_x)
+ $display("[%t] Executing inst @ 0x%08X", $time, pc_x);
+ end
+end
+`endif
+
`ifdef CFG_TRACE_ENABLED
reg [`LM32_PC_RNG] pc_c; // PC of last commited instruction
`endif
@@ -777,6 +799,12 @@ reg data_bus_error_seen; // Indicates if a data bus error
reg ext_break_r;
`endif
+`ifdef CFG_MMU_ENABLED
+wire dtlb_miss_exception;
+wire itlb_miss_exception;
+reg [`LM32_WORD_RNG] lm32_csr_psw_reg;
+`endif
+
/////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////
@@ -819,6 +847,9 @@ lm32_instruction_unit #(
.branch_target_x (branch_target_x),
`endif
.exception_m (exception_m),
+`ifdef CFG_MMU_ENABLED
+ .exception_x (exception_x),
+`endif
.branch_taken_m (branch_taken_m),
.branch_mispredict_taken_m (branch_mispredict_taken_m),
.branch_target_m (branch_target_m),
@@ -834,7 +865,15 @@ lm32_instruction_unit #(
.dcache_restart_request (dcache_restart_request),
.dcache_refill_request (dcache_refill_request),
.dcache_refilling (dcache_refilling),
-`endif
+`endif
+`ifdef CFG_MMU_ENABLED
+ .csr (csr_x),
+ .csr_write_data (operand_1_x),
+ .csr_write_enable (csr_write_enable_q_x),
+ .eret_q_x (eret_q_x),
+ .csr_psw (lm32_csr_psw_reg),
+ .q_x (q_x),
+`endif
`ifdef CFG_IWB_ENABLED
// From Wishbone
.i_dat_i (I_DAT_I),
@@ -849,6 +888,9 @@ lm32_instruction_unit #(
`endif
// ----- Outputs -------
// To pipeline
+`ifdef CFG_PIPELINE_TRACES
+ .pc_a (pc_a),
+`endif
.pc_f (pc_f),
.pc_d (pc_d),
.pc_x (pc_x),
@@ -863,6 +905,10 @@ lm32_instruction_unit #(
`ifdef CFG_IROM_ENABLED
.irom_data_m (irom_data_m),
`endif
+`ifdef CFG_MMU_ENABLED
+ .itlb_miss (itlb_miss_exception),
+ .csr_read_data (instruction_csr_read_data_x),
+`endif
`ifdef CFG_IWB_ENABLED
// To Wishbone
.i_dat_o (I_DAT_O),
@@ -967,8 +1013,6 @@ lm32_decoder decoder (
.csr_write_enable (csr_write_enable_d)
);
-wire dtlb_miss_exception;
-
// Load/store unit
lm32_load_store_unit #(
.associativity (dcache_associativity),
@@ -1006,10 +1050,13 @@ lm32_load_store_unit #(
`ifdef CFG_IROM_ENABLED
.irom_data_m (irom_data_m),
`endif
+`ifdef CFG_MMU_ENABLED
.csr (csr_x),
.csr_write_data (operand_1_x),
.csr_write_enable (csr_write_enable_q_x),
.eret_q_x (eret_q_x),
+ .csr_psw (lm32_csr_psw_reg),
+`endif
// From Wishbone
.d_dat_i (D_DAT_I),
.d_ack_i (D_ACK_I),
@@ -1031,8 +1078,10 @@ lm32_load_store_unit #(
`endif
.load_data_w (load_data_w),
.stall_wb_load (stall_wb_load),
+`ifdef CFG_MMU_ENABLED
.dtlb_miss (dtlb_miss_exception),
.csr_read_data (load_store_csr_read_data_x),
+`endif
// To Wishbone
.d_dat_o (D_DAT_O),
.d_adr_o (D_ADR_O),
@@ -1771,7 +1820,7 @@ assign non_debug_exception_x = (system_call_exception == `TRUE)
)
`endif
`ifdef CFG_MMU_ENABLED
- || (dtlb_miss_exception == `TRUE)
+ || (dtlb_miss_exception == `TRUE || itlb_miss_exception == `TRUE)
`endif
;
@@ -1797,7 +1846,7 @@ assign exception_x = (system_call_exception == `TRUE)
)
`endif
`ifdef CFG_MMU_ENABLED
- || (dtlb_miss_exception == `TRUE)
+ || (dtlb_miss_exception == `TRUE || itlb_miss_exception == `TRUE)
`endif
;
`endif
@@ -1847,9 +1896,13 @@ begin
eid_x = `LM32_EID_INTERRUPT;
else
`endif
- if (dtlb_miss_exception == `TRUE )
+`ifdef CFG_MMU_ENABLED
+ if (dtlb_miss_exception == `TRUE)
eid_x = `LM32_EID_DTLB_MISS;
+ else if (itlb_miss_exception == `TRUE)
+ eid_x = `LM32_EID_ITLB_MISS;
else
+`endif
eid_x = `LM32_EID_SCALL;
end
@@ -2144,11 +2197,69 @@ begin
`endif
`LM32_CSR_CFG2: csr_read_data_x = cfg2;
`LM32_CSR_TLB_VADDRESS: csr_read_data_x = load_store_csr_read_data_x;
-
+ `LM32_CSR_TLB_PADDRESS: csr_read_data_x = instruction_csr_read_data_x;
+ `LM32_CSR_PSW: csr_read_data_x = lm32_csr_psw_reg;
default: csr_read_data_x = {`LM32_WORD_WIDTH{1'bx}};
endcase
end
+`ifdef CFG_MMU_ENABLED
+
+always @(posedge clk_i `CFG_RESET_SENSITIVITY)
+begin
+ if (rst_i)
+ begin
+ lm32_csr_psw_reg <= `LM32_WORD_WIDTH'h0;
+ end
+ else
+ begin
+`ifdef CFG_DEBUG_ENABLED
+ if (non_debug_exception_q_w == `TRUE)
+ begin
+ // Save and then clear ITLB enable
+ lm32_csr_psw_reg[`LM32_CSR_PSW_EITLBE] <= lm32_csr_psw_reg[`LM32_CSR_PSW_ITLBE];
+ lm32_csr_psw_reg[`LM32_CSR_PSW_ITLBE] <= `FALSE;
+ end
+ else if (debug_exception_q_w == `TRUE)
+ begin
+ // Save and then clear TLB enable
+ lm32_csr_psw_reg[`LM32_CSR_PSW_BITLBE] <= lm32_csr_psw_reg[`LM32_CSR_PSW_ITLBE];
+ lm32_csr_psw_reg[`LM32_CSR_PSW_ITLBE] <= `FALSE;
+ end
+`else
+ if (exception_q_w == `TRUE)
+ begin
+ // Save and then clear ITLB enable
+ lm32_csr_psw_reg[`LM32_CSR_PSW_EITLBE] <= lm32_csr_psw_reg[`LM32_CSR_PSW_ITLBE];
+ lm32_csr_psw_reg[`LM32_CSR_PSW_ITLBE] <= `FALSE;
+ end
+`endif
+ else if (stall_x == `FALSE)
+ begin
+ if (eret_q_x == `TRUE)
+ // Restore ITLB enable
+ lm32_csr_psw_reg[`LM32_CSR_PSW_ITLBE] <= lm32_csr_psw_reg[`LM32_CSR_PSW_EITLBE];
+`ifdef CFG_DEBUG_ENABLED
+ else if (bret_q_x == `TRUE)
+ // Restore ITLB enable
+ lm32_csr_psw_reg[`LM32_CSR_PSW_ITLBE] <= lm32_csr_psw_reg[`LM32_CSR_PSW_BITLBE];
+`endif
+ else if (csr_write_enable_q_x == `TRUE)
+ begin
+ // Handle wcsr write
+ case (csr_x)
+ // operand_1_x is csr_write_data
+ `LM32_CSR_PSW:
+ lm32_csr_psw_reg <= operand_1_x;
+ `LM32_CSR_IE:
+ lm32_csr_psw_reg[2:0] <= operand_1_x[2:0];
+ endcase
+ end
+ end
+ end
+end
+`endif
+
/////////////////////////////////////////////////////
// Sequential Logic
/////////////////////////////////////////////////////
@@ -2231,7 +2342,7 @@ begin
end
`endif
-// Valid bits to indicate whether an instruction in a partcular pipeline stage is valid or not
+// Valid bits to indicate whether an instruction in a particular pipeline stage is valid or not
`ifdef CFG_ICACHE_ENABLED
`ifdef CFG_DCACHE_ENABLED
View
355 cores/lm32/rtl/lm32_dcache.v
@@ -2,7 +2,7 @@
// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// ------------------------------------------------------------------
// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
-// ALL RIGHTS RESERVED
+// ALL RIGHTS RESERVED
// ------------------------------------------------------------------
//
// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
@@ -11,7 +11,7 @@
//
// Lattice Semiconductor grants permission to use this code
// pursuant to the terms of the Lattice Semiconductor Corporation
-// Open Source License Agreement.
+// Open Source License Agreement.
//
// Disclaimer:
//
@@ -48,14 +48,11 @@
// : cache memory. Additional parameters must be defined when
// : invoking lm32_ram.v
// =============================================================================
-
+
`include "lm32_include.v"
`ifdef CFG_DCACHE_ENABLED
-`define LM32_KERNEL_MODE 1
-`define LM32_USER_MODE 0
-
`define LM32_DC_ADDR_OFFSET_RNG addr_offset_msb:addr_offset_lsb
`define LM32_DC_ADDR_SET_RNG addr_set_msb:addr_set_lsb
`define LM32_DC_ADDR_TAG_RNG addr_tag_msb:addr_tag_lsb
@@ -76,6 +73,7 @@
`define LM32_DC_STATE_CHECK 3'b010
`define LM32_DC_STATE_REFILL 3'b100
+`ifdef CFG_MMU_ENABLED
`define LM32_DTLB_CTRL_FLUSH 5'h1
`define LM32_DTLB_CTRL_UPDATE 5'h2
`define LM32_TLB_CTRL_SWITCH_TO_KERNEL_MODE 5'h4
@@ -85,14 +83,18 @@
`define LM32_TLB_STATE_CHECK 2'b01
`define LM32_TLB_STATE_FLUSH 2'b10
+`define LM32_KERNEL_MODE 1
+`define LM32_USER_MODE 0
+`endif
+
/////////////////////////////////////////////////////
// Module interface
/////////////////////////////////////////////////////
-module lm32_dcache (
+module lm32_dcache (
// ----- Inputs -----
clk_i,
- rst_i,
+ rst_i,
stall_a,
stall_x,
stall_m,
@@ -105,24 +107,28 @@ module lm32_dcache (
refill_ready,
refill_data,
dflush,
+`ifdef CFG_MMU_ENABLED
csr,
csr_write_data,
csr_write_enable,
exception_x,
eret_q_x,
exception_m,
+ csr_psw,
+`endif
// ----- Outputs -----
stall_request,
restart_request,
refill_request,
refill_address,
refilling,
- load_data,
- // To pipeline
+`ifdef CFG_MMU_ENABLED
dtlb_miss_int,
kernel_mode,
pa,
- csr_read_data
+ csr_read_data,
+`endif
+ load_data
);
/////////////////////////////////////////////////////
@@ -135,6 +141,8 @@ parameter bytes_per_line = 16; // Number of bytes per c
parameter base_address = 0; // Base address of cachable memory
parameter limit = 0; // Limit (highest address) of cachable memory
+`ifdef CFG_MMU_ENABLED
+
parameter dtlb_sets = 1024; // Number of lines of DTLB
parameter page_size = 4096; // System page size
@@ -167,6 +175,7 @@ localparam addr_dtlb_tag_msb = addr_dtlb_tag_lsb + addr_dtlb_tag_width - 1;
`define LM32_DTLB_ADDR_TAG_RNG addr_dtlb_tag_msb:addr_dtlb_tag_lsb
`define LM32_DTLB_VALID_BIT vpfn_width+addr_dtlb_tag_width
+`endif
localparam addr_offset_width = clogb2(bytes_per_line)-1-2;
localparam addr_set_width = clogb2(sets)-1;
@@ -201,6 +210,7 @@ input [`LM32_WORD_RNG] refill_data; // Refill data
input dflush; // Indicates cache should be flushed
+`ifdef CFG_MMU_ENABLED
input [`LM32_CSR_RNG] csr; // CSR read/write index
input [`LM32_WORD_RNG] csr_write_data; // Data to write to specified CSR
@@ -208,19 +218,19 @@ input csr_write_enable; // CSR write enable
input exception_x; // An exception occured in the X stage
input exception_m;
input eret_q_x;
+input [`LM32_WORD_RNG] csr_psw;
+
+`endif
/////////////////////////////////////////////////////
// Outputs
/////////////////////////////////////////////////////
-output csr_read_data;
-wire [`LM32_WORD_RNG] csr_read_data;
-
output stall_request; // Request pipeline be stalled because cache is busy
wire stall_request;
output restart_request; // Request to restart instruction that caused the cache miss
reg restart_request;
-output refill_request; // Request a refill
+output refill_request; // Request a refill
reg refill_request;
output [`LM32_WORD_RNG] refill_address; // Address to refill from
reg [`LM32_WORD_RNG] refill_address;
@@ -229,13 +239,21 @@ reg refilling;
output [`LM32_WORD_RNG] load_data; // Data read from cache
wire [`LM32_WORD_RNG] load_data;
+`ifdef CFG_MMU_ENABLED
+
output kernel_mode;
wire kernel_mode;
-
+output csr_read_data;
+wire [`LM32_WORD_RNG] csr_read_data;
output dtlb_miss_int;
+wire dtlb_miss_int;
+output [`LM32_WORD_RNG] pa;
+wire [`LM32_WORD_RNG] pa;
+
+`endif
/////////////////////////////////////////////////////
-// Internal nets and registers
+// Internal nets and registers
/////////////////////////////////////////////////////
wire read_port_enable; // Cache memory read port clock enable
@@ -252,7 +270,7 @@ wire [`LM32_DC_TMEM_ADDR_RNG] tmem_read_address; // Tag memory read addre
wire [`LM32_DC_TMEM_ADDR_RNG] tmem_write_address; // Tag memory write address
wire [`LM32_DC_DMEM_ADDR_RNG] dmem_read_address; // Data memory read address
wire [`LM32_DC_DMEM_ADDR_RNG] dmem_write_address; // Data memory write address
-wire [`LM32_DC_TAGS_RNG] tmem_write_data; // Tag memory write data
+wire [`LM32_DC_TAGS_RNG] tmem_write_data; // Tag memory write data
reg [`LM32_WORD_RNG] dmem_write_data; // Data memory write data
reg [`LM32_DC_STATE_RNG] state; // Current state of FSM
@@ -272,13 +290,8 @@ wire dtlb_data_read_port_enable;
wire dtlb_write_port_enable;
wire [vpfn_width + addr_dtlb_tag_width + 1 - 1:0] dtlb_write_data; // +1 is for valid_bit
wire [vpfn_width + addr_dtlb_tag_width + 1 - 1:0] dtlb_read_data; // +1 is for valid_bit
-
wire [`LM32_WORD_RNG] physical_address;
-wire [`LM32_WORD_RNG] pa;
-output [`LM32_WORD_RNG] pa;
-reg [`LM32_WORD_RNG] latest_store_tlb_lookup;
-
assign pa = physical_address;
reg kernel_mode_reg = `LM32_KERNEL_MODE;
@@ -286,7 +299,7 @@ wire switch_to_kernel_mode;
wire switch_to_user_mode;
reg [`LM32_WORD_RNG] dtlb_update_vaddr_csr_reg = `LM32_WORD_WIDTH'd0;
reg [`LM32_WORD_RNG] dtlb_update_paddr_csr_reg = `LM32_WORD_WIDTH'd0;
-reg [1:0] dtlb_state = `LM32_TLB_STATE_CHECK;
+reg [1:0] dtlb_state;
reg [`LM32_WORD_RNG] dtlb_ctrl_csr_reg = `LM32_WORD_WIDTH'd0;
reg dtlb_updating;
reg [addr_dtlb_index_width-1:0] dtlb_update_set;
@@ -294,7 +307,6 @@ reg dtlb_flushing;
reg [addr_dtlb_index_width-1:0] dtlb_flush_set;
wire dtlb_miss;
reg dtlb_miss_q = `FALSE;
-wire dtlb_miss_int;
reg [`LM32_WORD_RNG] dtlb_miss_addr;
wire dtlb_data_valid;
wire [`LM32_DTLB_LOOKUP_RANGE] dtlb_lookup;
@@ -313,15 +325,15 @@ assign kernel_mode = kernel_mode_reg;
// Instantiations
/////////////////////////////////////////////////////
-
+`ifdef CFG_MMU_ENABLED
// DTLB instantiation
-lm32_ram
+lm32_ram
#(
// ----- Parameters -------
.data_width (vpfn_width + addr_dtlb_tag_width + 1),
.address_width (addr_dtlb_index_width)
// Modified for Milkymist: removed non-portable RAM parameters
- ) dtlb_data_ram
+ ) dtlb_data_ram
(
// ----- Inputs -------
.read_clk (clk_i),
@@ -332,34 +344,25 @@ lm32_ram
.write_address (dtlb_data_write_address),
.enable_write (`TRUE),
.write_enable (dtlb_write_port_enable),
- .write_data (dtlb_write_data),
+ .write_data (dtlb_write_data),
// ----- Outputs -------
.read_data (dtlb_read_data)
);
-
-`ifdef CFG_VERBOSE_DISPLAY_ENABLED
-always @(posedge clk_i)
-begin
- if (dtlb_write_port_enable)
- begin
- $display("[DTLB data : %d] Writing 0x%08X to 0x%08X", $time, dtlb_write_data, dtlb_data_write_address);
- end
-end
`endif
generate
- for (i = 0; i < associativity; i = i + 1)
+ for (i = 0; i < associativity; i = i + 1)
begin : memories
// Way data
if (`LM32_DC_DMEM_ADDR_WIDTH < 11)
begin : data_memories
- lm32_ram
+ lm32_ram
#(
// ----- Parameters -------
.data_width (32),
.address_width (`LM32_DC_DMEM_ADDR_WIDTH)
// Modified for Milkymist: removed non-portable RAM parameters
- ) way_0_data_ram
+ ) way_0_data_ram
(
// ----- Inputs -------
.read_clk (clk_i),
@@ -370,22 +373,22 @@ end
.write_address (dmem_write_address),
.enable_write (write_port_enable),
.write_enable (way_dmem_we[i]),
- .write_data (dmem_write_data),
+ .write_data (dmem_write_data),
// ----- Outputs -------
.read_data (way_data[i])
- );
+ );
end
else
begin
- for (j = 0; j < 4; j = j + 1)
+ for (j = 0; j < 4; j = j + 1)
begin : byte_memories
- lm32_ram
+ lm32_ram
#(
// ----- Parameters -------
.data_width (8),
.address_width (`LM32_DC_DMEM_ADDR_WIDTH)
// Modified for Milkymist: removed non-portable RAM parameters
- ) way_0_data_ram
+ ) way_0_data_ram
(
// ----- Inputs -------
.read_clk (clk_i),
@@ -396,21 +399,21 @@ end
.write_address (dmem_write_address),
.enable_write (write_port_enable),
.write_enable (way_dmem_we[i] & (store_byte_select[j] | refill)),
- .write_data (dmem_write_data[(j+1)*8-1:j*8]),
+ .write_data (dmem_write_data[(j+1)*8-1:j*8]),
// ----- Outputs -------
.read_data (way_data[i][(j+1)*8-1:j*8])
);
end
end
-
+
// Way tags
- lm32_ram
+ lm32_ram
#(
// ----- Parameters -------
.data_width (`LM32_DC_TAGS_WIDTH),
.address_width (`LM32_DC_TMEM_ADDR_WIDTH)
// Modified for Milkymist: removed non-portable RAM parameters
- ) way_0_tag_ram
+ ) way_0_tag_ram
(
// ----- Inputs -------
.read_clk (clk_i),
@@ -426,37 +429,13 @@ end
.read_data ({way_tag[i], way_valid[i]})
);
end
-
+
endgenerate
/////////////////////////////////////////////////////
// Combinational logic
/////////////////////////////////////////////////////
-// CSR Write
-always @(posedge clk_i `CFG_RESET_SENSITIVITY)
-begin
- if (rst_i == `TRUE)
- begin
- dtlb_ctrl_csr_reg <= `LM32_WORD_WIDTH'd0;
- dtlb_update_vaddr_csr_reg <= `LM32_WORD_WIDTH'd0;
- dtlb_update_paddr_csr_reg <= `LM32_WORD_WIDTH'd0;
- end
- else
- begin
- if (csr_write_enable)
- begin
- case (csr)
- `LM32_CSR_TLB_CTRL: if (csr_write_data[0]) dtlb_ctrl_csr_reg[31:1] <= csr_write_data[31:1];
- `LM32_CSR_TLB_VADDRESS: if (csr_write_data[0]) dtlb_update_vaddr_csr_reg[31:1] <= csr_write_data[31:1];
- `LM32_CSR_TLB_PADDRESS: if (csr_write_data[0]) dtlb_update_paddr_csr_reg[31:1] <= csr_write_data[31:1];
- endcase
- end
- dtlb_ctrl_csr_reg[0] <= 0;
- dtlb_update_vaddr_csr_reg[0] <= 0;
- dtlb_update_paddr_csr_reg[0] <= 0;
- end
-end
@@ -465,25 +444,24 @@ generate
for (i = 0; i < associativity; i = i + 1)
begin : match
-assign dtlb_read_tag = dtlb_read_data[`LM32_DTLB_TAG_RANGE];
-assign dtlb_data_valid = dtlb_read_data[`LM32_DTLB_VALID_BIT];
-assign dtlb_lookup = dtlb_read_data[`LM32_DTLB_LOOKUP_RANGE];
-
-assign way_match[i] = (kernel_mode_reg == `LM32_KERNEL_MODE) ?
- ({way_tag[i], way_valid[i]} == {address_m[`LM32_DC_ADDR_TAG_RNG], `TRUE})
- : ({way_tag[i], way_valid[i]} == {dtlb_lookup, `TRUE});
+assign way_match[i] =
+`ifdef CFG_MMU_ENABLED
+ (dtlb_enabled == `TRUE) ?
+ ({way_tag[i], way_valid[i]} == {dtlb_lookup, `TRUE}) :
+`endif
+ ({way_tag[i], way_valid[i]} == {address_m[`LM32_DC_ADDR_TAG_RNG], `TRUE});
end
endgenerate
-// Select data from way that matched the address being read
+// Select data from way that matched the address being read
generate
- if (associativity == 1)
+ if (associativity == 1)
begin : data_1
assign load_data = way_data[0];
end
else if (associativity == 2)
begin : data_2
-assign load_data = way_match[0] ? way_data[0] : way_data[1];
+assign load_data = way_match[0] ? way_data[0] : way_data[1];
end
endgenerate
@@ -518,45 +496,26 @@ end
endgenerate
// Compute address to use to index into the data memories
-generate
+generate
if (bytes_per_line > 4)
-assign dmem_write_address = (refill == `TRUE)
+assign dmem_write_address = (refill == `TRUE)
? {refill_address[`LM32_DC_ADDR_SET_RNG], refill_offset}
: address_m[`LM32_DC_ADDR_IDX_RNG];
else
-assign dmem_write_address = (refill == `TRUE)
+assign dmem_write_address = (refill == `TRUE)
? refill_address[`LM32_DC_ADDR_SET_RNG]
: address_m[`LM32_DC_ADDR_IDX_RNG];
endgenerate
assign dmem_read_address = address_x[`LM32_DC_ADDR_IDX_RNG];
-// Compute address to use to index into the tag memories
+// Compute address to use to index into the tag memories
assign tmem_write_address = (flushing == `TRUE)
? flush_set
: refill_address[`LM32_DC_ADDR_SET_RNG];
assign tmem_read_address = address_x[`LM32_DC_ADDR_SET_RNG];
-// Compute address to use to index into the DTLB data memory
-
-assign dtlb_data_read_address = address_x[`LM32_DTLB_IDX_RNG];
-assign dtlb_tag_read_address = address_x[`LM32_DTLB_IDX_RNG];
-
-// tlb_update_address will receive data from a CSR register
-assign dtlb_data_write_address = dtlb_update_vaddr_csr_reg[`LM32_DTLB_IDX_RNG];
-
-assign dtlb_data_read_port_enable = (stall_x == `FALSE) || !stall_m;
-assign dtlb_write_port_enable = dtlb_updating || dtlb_flushing;
-
-assign physical_address = (kernel_mode_reg == `LM32_KERNEL_MODE)
- ? address_m
- : {dtlb_lookup, address_m[`LM32_PAGE_OFFSET_RNG]};
-
-assign dtlb_write_data = (dtlb_flushing == `TRUE)
- ? {`FALSE, {addr_dtlb_tag_width{1'b0}}, {vpfn_width{1'b0}}}
- : {`TRUE, {dtlb_update_vaddr_csr_reg[`LM32_DTLB_ADDR_TAG_RNG]}, dtlb_update_paddr_csr_reg[`LM32_DTLB_ADDRESS_PFN_RNG]};
-
// Compute signal to indicate when we are on the last refill accesses
-generate
- if (bytes_per_line > 4)
+generate
+ if (bytes_per_line > 4)
assign last_refill = refill_offset == {addr_offset_width{1'b1}};
else
assign last_refill = `TRUE;
@@ -571,12 +530,12 @@ assign valid_store = (store_q_m == `TRUE) && (check == `TRUE);
// Compute data and tag memory write enables
generate
- if (associativity == 1)
- begin : we_1
+ if (associativity == 1)
+ begin : we_1
assign way_dmem_we[0] = (refill_ready == `TRUE) || ((valid_store == `TRUE) && (way_match[0] == `TRUE));
assign way_tmem_we[0] = (refill_ready == `TRUE) || (flushing == `TRUE);
- end
- else
+ end
+ else
begin : we_2
assign way_dmem_we[0] = ((refill_ready == `TRUE) && (refill_way_select[0] == `TRUE)) || ((valid_store == `TRUE) && (way_match[0] == `TRUE));
assign way_dmem_we[1] = ((refill_ready == `TRUE) && (refill_way_select[1] == `TRUE)) || ((valid_store == `TRUE) && (way_match[1] == `TRUE));
@@ -595,35 +554,39 @@ assign check = state[1];
assign refill = state[2];
assign miss = (~(|way_match)) && (load_q_m == `TRUE) && (stall_m == `FALSE) && (~dtlb_miss);
-assign stall_request = (check == `FALSE) || (dtlb_state == `LM32_TLB_STATE_FLUSH && kernel_mode_reg != `LM32_KERNEL_MODE);
-
+assign stall_request = (check == `FALSE) || (dtlb_state == `LM32_TLB_STATE_FLUSH
+`ifdef CFG_MMU_ENABLED
+ && (dtlb_enabled == `TRUE)
+`endif
+ );
+
/////////////////////////////////////////////////////
// Sequential logic
/////////////////////////////////////////////////////
// Record way selected for replacement on a cache miss
generate
- if (associativity >= 2)
- begin : way_select
+ if (associativity >= 2)
+ begin : way_select
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
refill_way_select <= {{associativity-1{1'b0}}, 1'b1};
else
- begin
+ begin
if (refill_request == `TRUE)
refill_way_select <= {refill_way_select[0], refill_way_select[1]};
end
end
- end
-endgenerate
+ end
+endgenerate
// Record whether we are currently refilling
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
refilling <= `FALSE;
- else
+ else
refilling <= refill;
end
@@ -638,18 +601,18 @@ begin
refill_address <= {`LM32_WORD_WIDTH{1'b0}};
restart_request <= `FALSE;
end
- else
+ else
begin
case (state)
- // Flush the cache
+ // Flush the cache
`LM32_DC_STATE_FLUSH:
begin
if (flush_set == {`LM32_DC_TMEM_ADDR_WIDTH{1'b0}})
state <= `LM32_DC_STATE_CHECK;
flush_set <= flush_set - 1'b1;
end
-
+
// Check for cache misses
`LM32_DC_STATE_CHECK:
begin
@@ -658,7 +621,11 @@ begin
if (miss == `TRUE)
begin
refill_request <= `TRUE;
+`ifdef CFG_MMU_ENABLED
refill_address <= physical_address;
+`else
+ refill_address <= address_m;
+`endif
state <= `LM32_DC_STATE_REFILL;
end
else if (dflush == `TRUE)
@@ -678,28 +645,102 @@ begin
end
end
end
-
- endcase
+
+ endcase
+ end
+end
+
+
+generate
+ if (bytes_per_line > 4)
+ begin
+// Refill offset
+always @(posedge clk_i `CFG_RESET_SENSITIVITY)
+begin
+ if (rst_i == `TRUE)
+ refill_offset <= {addr_offset_width{1'b0}};
+ else
+ begin
+ case (state)
+
+ // Check for cache misses
+ `LM32_DC_STATE_CHECK:
+ begin
+ if (miss == `TRUE)
+ refill_offset <= {addr_offset_width{1'b0}};
+ end
+
+ // Refill a cache line
+ `LM32_DC_STATE_REFILL:
+ begin
+ if (refill_ready == `TRUE)
+ refill_offset <= refill_offset + 1'b1;
+ end
+
+ endcase
end
end
+ end
+endgenerate
+
+`endif
+`ifdef CFG_MMU_ENABLED
+// Beginning of MMU specific code
+
+assign dtlb_enabled = csr_psw[`LM32_CSR_PSW_DTLBE];
+
+// Compute address to use to index into the DTLB data memory
+
+assign dtlb_data_read_address = address_x[`LM32_DTLB_IDX_RNG];
+assign dtlb_tag_read_address = address_x[`LM32_DTLB_IDX_RNG];
+
+// tlb_update_address will receive data from a CSR register
+assign dtlb_data_write_address = dtlb_update_vaddr_csr_reg[`LM32_DTLB_IDX_RNG];
+
+assign dtlb_data_read_port_enable = (stall_x == `FALSE) || !stall_m;
+assign dtlb_write_port_enable = dtlb_updating || dtlb_flushing;
+
+assign physical_address = (dtlb_enabled == `FALSE)
+ ? address_m
+ : {dtlb_lookup, address_m[`LM32_PAGE_OFFSET_RNG]};
+
+assign dtlb_write_data = (dtlb_flushing == `TRUE)
+ ? {`FALSE, {addr_dtlb_tag_width{1'b0}}, {vpfn_width{1'b0}}}
+ : {`TRUE, {dtlb_update_vaddr_csr_reg[`LM32_DTLB_ADDR_TAG_RNG]}, dtlb_update_paddr_csr_reg[`LM32_DTLB_ADDRESS_PFN_RNG]};
+
+assign dtlb_read_tag = dtlb_read_data[`LM32_DTLB_TAG_RANGE];
+assign dtlb_data_valid = dtlb_read_data[`LM32_DTLB_VALID_BIT];
+assign dtlb_lookup = dtlb_read_data[`LM32_DTLB_LOOKUP_RANGE];
+assign csr_read_data = dtlb_miss_addr;
+assign dtlb_miss = (dtlb_enabled == `TRUE) && (load_q_m || store_q_m) && ~(dtlb_data_valid);
+assign dtlb_miss_int = (dtlb_miss || dtlb_miss_q);
+
+// CSR Write
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
- latest_store_tlb_lookup <= `LM32_WORD_WIDTH'd0;
+ begin
+ dtlb_ctrl_csr_reg <= `LM32_WORD_WIDTH'd0;
+ dtlb_update_vaddr_csr_reg <= `LM32_WORD_WIDTH'd0;
+ dtlb_update_paddr_csr_reg <= `LM32_WORD_WIDTH'd0;
+ end
else
begin
- if (write_port_enable && (|way_dmem_we))
+ if (csr_write_enable)
begin
- latest_store_tlb_lookup <= {dtlb_lookup, address_m[`LM32_PAGE_OFFSET_RNG]};
+ case (csr)
+ `LM32_CSR_TLB_CTRL: if (csr_write_data[0]) dtlb_ctrl_csr_reg[31:1] <= csr_write_data[31:1];
+ `LM32_CSR_TLB_VADDRESS: if (csr_write_data[0]) dtlb_update_vaddr_csr_reg[31:1] <= csr_write_data[31:1];
+ `LM32_CSR_TLB_PADDRESS: if (csr_write_data[0]) dtlb_update_paddr_csr_reg[31:1] <= csr_write_data[31:1];
+ endcase
end
+ dtlb_ctrl_csr_reg[0] <= 0;
+ dtlb_update_vaddr_csr_reg[0] <= 0;
+ dtlb_update_paddr_csr_reg[0] <= 0;
end
end
-assign csr_read_data = dtlb_miss_addr;
-
-assign dtlb_miss = (kernel_mode_reg == `LM32_USER_MODE) && (load_q_m || store_q_m) && ~(dtlb_data_valid);
-
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
@@ -713,12 +754,11 @@ begin
end
end
-assign dtlb_miss_int = (dtlb_miss || dtlb_miss_q);
-
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
begin
+ $display("DTLB STATE MACHINE RESET");
dtlb_flushing <= 1;
dtlb_flush_set <= {addr_dtlb_index_width{1'b1}};
dtlb_state <= `LM32_TLB_STATE_FLUSH;
@@ -782,10 +822,6 @@ begin
end
end
-assign switch_to_kernel_mode = (/*(kernel_mode_reg == `LM32_KERNEL_MODE) && */csr_write_enable && (csr == `LM32_CSR_TLB_CTRL) && csr_write_data[5:0] == {`LM32_TLB_CTRL_SWITCH_TO_KERNEL_MODE, 1'b1});
-assign switch_to_user_mode = (/*(kernel_mode_reg == `LM32_KERNEL_MODE) && */csr_write_enable && (csr == `LM32_CSR_TLB_CTRL) && csr_write_data[5:0] == {`LM32_TLB_CTRL_SWITCH_TO_USER_MODE, 1'b1});
-
-
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
@@ -799,39 +835,16 @@ begin
end
end
-generate
- if (bytes_per_line > 4)
- begin
-// Refill offset
-always @(posedge clk_i `CFG_RESET_SENSITIVITY)
+`ifdef CFG_VERBOSE_DISPLAY_ENABLED
+always @(posedge clk_i)
begin
- if (rst_i == `TRUE)
- refill_offset <= {addr_offset_width{1'b0}};
- else
- begin
- case (state)
-
- // Check for cache misses
- `LM32_DC_STATE_CHECK:
- begin
- if (miss == `TRUE)
- refill_offset <= {addr_offset_width{1'b0}};
- end
-
- // Refill a cache line
- `LM32_DC_STATE_REFILL:
- begin
- if (refill_ready == `TRUE)
- refill_offset <= refill_offset + 1'b1;
- end
-
- endcase
- end
+ if (dtlb_write_port_enable)
+ begin
+ $display("[DTLB data : %d] Writing 0x%08X to 0x%08X", $time, dtlb_write_data, dtlb_data_write_address);
+ end
end
- end
-endgenerate
-
-endmodule
+`endif
`endif
+endmodule
View
448 cores/lm32/rtl/lm32_icache.v
@@ -57,7 +57,6 @@
`include "lm32_include.v"
`ifdef CFG_ICACHE_ENABLED
-
`define LM32_IC_ADDR_OFFSET_RNG addr_offset_msb:addr_offset_lsb
`define LM32_IC_ADDR_SET_RNG addr_set_msb:addr_set_lsb
`define LM32_IC_ADDR_TAG_RNG addr_tag_msb:addr_tag_lsb
@@ -79,6 +78,22 @@
`define LM32_IC_STATE_CHECK 4'b0100
`define LM32_IC_STATE_REFILL 4'b1000
+`ifdef CFG_MMU_ENABLED
+
+`define LM32_ITLB_CTRL_FLUSH 5'h1
+`define LM32_ITLB_CTRL_UPDATE 5'h2
+`define LM32_TLB_CTRL_SWITCH_TO_KERNEL_MODE 5'h4
+`define LM32_TLB_CTRL_SWITCH_TO_USER_MODE 5'h8
+`define LM32_TLB_CTRL_INVALIDATE_ENTRY 5'h10
+
+`define LM32_TLB_STATE_CHECK 2'b01
+`define LM32_TLB_STATE_FLUSH 2'b10
+
+`define LM32_KERNEL_MODE 1
+`define LM32_USER_MODE 0
+
+`endif
+
/////////////////////////////////////////////////////
// Module interface
/////////////////////////////////////////////////////
@@ -89,8 +104,17 @@ module lm32_icache (
rst_i,
stall_a,
stall_f,
+`ifdef CFG_MMU_ENABLED
+ stall_x,
+ stall_m,
+`endif
address_a,
address_f,
+`ifdef CFG_MMU_ENABLED
+ pc_x,
+ pc_m,
+ pc_w,
+`endif
read_enable_f,
refill_ready,
refill_data,
@@ -100,12 +124,31 @@ module lm32_icache (
`endif
valid_d,
branch_predict_taken_d,
+`ifdef CFG_MMU_ENABLED
+ csr,
+ csr_write_data,
+ csr_write_enable,
+ csr_psw,
+ exception_x,
+ eret_q_x,
+ exception_m,
+ q_x,
+`endif
// ----- Outputs -----
stall_request,
restart_request,
refill_request,
refill_address,
+`ifdef CFG_MMU_ENABLED
+ physical_refill_address,
+`endif
refilling,
+`ifdef CFG_MMU_ENABLED
+ itlb_miss_int,
+ kernel_mode,
+ pa,
+ csr_read_data,
+`endif
inst
);
@@ -119,6 +162,42 @@ parameter bytes_per_line = 16; // Number of bytes per c
parameter base_address = 0; // Base address of cachable memory
parameter limit = 0; // Limit (highest address) of cachable memory
+`ifdef CFG_MMU_ENABLED
+
+parameter itlb_sets = 1024; // Number of lines of ITLB
+parameter page_size = 4096; // System page size
+
+`define LM32_ITLB_IDX_RNG addr_itlb_index_msb:addr_itlb_index_lsb
+`define LM32_ITLB_ADDRESS_PFN_RNG addr_pfn_msb:addr_pfn_lsb
+`define LM32_PAGE_OFFSET_RNG addr_page_offset_msb:addr_page_offset_lsb
+`define LM32_ITLB_INVALID_ADDRESS { vpfn_width{1'b1} }
+
+localparam addr_page_offset_lsb = 0;
+localparam addr_page_offset_msb = addr_page_offset_lsb + clogb2(page_size) - 2;
+localparam addr_itlb_index_width = clogb2(itlb_sets) - 1;
+localparam addr_itlb_index_lsb = addr_page_offset_msb + 1;
+localparam addr_itlb_index_msb = addr_itlb_index_lsb + addr_itlb_index_width - 1;
+localparam addr_pfn_lsb = addr_page_offset_msb + 1;
+localparam addr_pfn_msb = `LM32_WORD_WIDTH - 1;
+localparam vpfn_width = `LM32_WORD_WIDTH - (clogb2(page_size) - 1);
+localparam addr_itlb_tag_width = vpfn_width - addr_itlb_index_width;
+localparam addr_itlb_tag_lsb = addr_itlb_index_msb + 1;
+localparam addr_itlb_tag_msb = addr_itlb_tag_lsb + addr_itlb_tag_width - 1;
+
+`define LM32_ITLB_TAG_INVALID { addr_itlb_tag_width{ 1'b0 } }
+`define LM32_ITLB_LOOKUP_RANGE vpfn_width-1:0
+
+/* The following define is the range containing the TAG inside the itlb_read_data wire which contains the ITLB value from BlockRAM
+ * Indeed itlb_read_data contains { VALID_BIT, TAG_VALUE, LOOKUP_VALUE }
+ * LM32_ITLB_TAG_RANGE is the range to extract the TAG_VALUE */
+`define LM32_ITLB_TAG_RANGE vpfn_width+addr_itlb_tag_width-1:vpfn_width
+
+/* The following define is the range containing the TAG inside a memory address like itlb_update_vaddr_csr_reg for instance. */
+`define LM32_ITLB_ADDR_TAG_RNG addr_itlb_tag_msb:addr_itlb_tag_lsb
+`define LM32_ITLB_VALID_BIT vpfn_width+addr_itlb_tag_width
+
+`endif
+
localparam addr_offset_width = clogb2(bytes_per_line)-1-2;
localparam addr_set_width = clogb2(sets)-1;
localparam addr_offset_lsb = 2;
@@ -138,12 +217,19 @@ input rst_i; // Reset
input stall_a; // Stall instruction in A stage
input stall_f; // Stall instruction in F stage
+`ifdef CFG_MMU_ENABLED
+input stall_x; // Stall instruction in X stage
+input stall_m; // Stall instruction in X stage
+`endif
input valid_d; // Valid instruction in D stage
input branch_predict_taken_d; // Instruction in D stage is a branch and is predicted taken
input [`LM32_PC_RNG] address_a; // Address of instruction in A stage
input [`LM32_PC_RNG] address_f; // Address of instruction in F stage
+input [`LM32_PC_RNG] pc_x; // Address of instruction in X stage
+input [`LM32_PC_RNG] pc_m; // Address of instruction in M stage
+input [`LM32_PC_RNG] pc_w; // Address of instruction in W stage
input read_enable_f; // Indicates if cache access is valid
input refill_ready; // Next word of refill data is ready
@@ -153,11 +239,27 @@ input iflush; // Flush the cache
`ifdef CFG_IROM_ENABLED
input select_f; // Instruction in F stage is mapped through instruction cache
`endif
-
+
+`ifdef CFG_MMU_ENABLED
+input [`LM32_CSR_RNG] csr; // CSR read/write index
+input [`LM32_WORD_RNG] csr_write_data; // Data to write to specified CSR
+input csr_write_enable; // CSR write enable
+input [`LM32_WORD_RNG] csr_psw;
+input exception_x; // An exception occured in the X stage
+input exception_m;
+input eret_q_x;
+input q_x;
+`endif
+
/////////////////////////////////////////////////////
// Outputs
/////////////////////////////////////////////////////
+`ifdef CFG_MMU_ENABLED
+output csr_read_data;
+wire [`LM32_WORD_RNG] csr_read_data;
+`endif
+
output stall_request; // Request to stall the pipeline
wire stall_request;
output restart_request; // Request to restart instruction that caused the cache miss
@@ -166,11 +268,24 @@ output refill_request; // Request to refill a cache
wire refill_request;
output [`LM32_PC_RNG] refill_address; // Base address of cache refill
reg [`LM32_PC_RNG] refill_address;
+`ifdef CFG_MMU_ENABLED
+output [`LM32_PC_RNG] physical_refill_address;
+reg [`LM32_PC_RNG] physical_refill_address;
+`endif
output refilling; // Indicates the instruction cache is currently refilling
reg refilling;
output [`LM32_INSTRUCTION_RNG] inst; // Instruction read from cache
wire [`LM32_INSTRUCTION_RNG] inst;
+`ifdef CFG_MMU_ENABLED
+output kernel_mode;
+wire kernel_mode;
+output itlb_miss_int;
+wire itlb_miss_int;
+output [`LM32_WORD_RNG] pa;
+wire [`LM32_WORD_RNG] pa;
+`endif
+
/////////////////////////////////////////////////////
// Internal nets and registers
/////////////////////////////////////////////////////
@@ -199,7 +314,39 @@ reg [`LM32_IC_ADDR_OFFSET_RNG] refill_offset;
wire last_refill;
reg [`LM32_IC_TMEM_ADDR_RNG] flush_set;
-genvar i;
+`ifdef CFG_MMU_ENABLED
+
+wire [addr_itlb_index_width-1:0] itlb_data_read_address;
+wire [addr_itlb_index_width-1:0] itlb_data_write_address;
+wire itlb_data_read_port_enable;
+wire itlb_write_port_enable;
+wire [vpfn_width + addr_itlb_tag_width + 1 - 1:0] itlb_write_data; // +1 is for valid_bit
+wire [vpfn_width + addr_itlb_tag_width + 1 - 1:0] itlb_read_data; // +1 is for valid_bit
+wire [`LM32_WORD_RNG] physical_address;
+reg kernel_mode_reg = `LM32_KERNEL_MODE;
+wire switch_to_kernel_mode;
+wire switch_to_user_mode;
+reg [`LM32_WORD_RNG] itlb_update_vaddr_csr_reg = `LM32_WORD_WIDTH'd0;
+reg [`LM32_WORD_RNG] itlb_update_paddr_csr_reg = `LM32_WORD_WIDTH'd0;
+reg [1:0] itlb_state;
+reg [`LM32_WORD_RNG] itlb_ctrl_csr_reg = `LM32_WORD_WIDTH'd0;
+reg itlb_updating;
+reg [addr_itlb_index_width-1:0] itlb_update_set;
+reg itlb_flushing;
+reg [addr_itlb_index_width-1:0] itlb_flush_set;
+wire itlb_miss;
+reg itlb_miss_q = `FALSE;
+reg [`LM32_PC_RNG] itlb_miss_addr;
+wire itlb_data_valid;
+wire [`LM32_ITLB_LOOKUP_RANGE] itlb_lookup;
+reg go_to_user_mode;
+reg go_to_user_mode_2;
+reg itlb_enabled;
+
+`endif
+
+genvar i, j;
+
/////////////////////////////////////////////////////
// Functions
@@ -211,6 +358,32 @@ genvar i;
// Instantiations
/////////////////////////////////////////////////////
+`ifdef CFG_MMU_ENABLED
+// ITLB instantiation
+lm32_ram
+ #(
+ // ----- Parameters -------
+ .data_width (vpfn_width + addr_itlb_tag_width + 1),
+ .address_width (addr_itlb_index_width)
+// Modified for Milkymist: removed non-portable RAM parameters
+ ) itlb_data_ram
+ (
+ // ----- Inputs -------
+ .read_clk (clk_i),
+ .write_clk (clk_i),
+ .reset (rst_i),
+ .read_address (itlb_data_read_address),
+ .enable_read (itlb_data_read_port_enable),
+ .write_address (itlb_data_write_address),
+ .enable_write (`TRUE),
+ .write_enable (itlb_write_port_enable),
+ .write_data (itlb_write_data),
+ // ----- Outputs -------
+ .read_data (itlb_read_data)
+ );
+`endif
+
+
generate
for (i = 0; i < associativity; i = i + 1)
begin : memories
@@ -272,7 +445,14 @@ endgenerate
generate
for (i = 0; i < associativity; i = i + 1)
begin : match
-assign way_match[i] = ({way_tag[i], way_valid[i]} == {address_f[`LM32_IC_ADDR_TAG_RNG], `TRUE});
+
+assign way_match[i] =
+`ifdef CFG_MMU_ENABLED
+ (itlb_enabled == `TRUE) ?
+ ({way_tag[i], way_valid[i]} == {itlb_lookup, `TRUE }) :
+`endif
+ ({way_tag[i], way_valid[i]} == {address_f[`LM32_IC_ADDR_TAG_RNG], `TRUE});
+
end
endgenerate
@@ -304,6 +484,7 @@ assign tmem_write_address = flushing
? flush_set
: refill_address[`LM32_IC_ADDR_SET_RNG];
+
// Compute signal to indicate when we are on the last refill accesses
generate
if (bytes_per_line > 4)
@@ -330,7 +511,11 @@ endgenerate
// On the last refill cycle set the valid bit, for all other writes it should be cleared
assign tmem_write_data[`LM32_IC_TAGS_VALID_RNG] = last_refill & !flushing;
+`ifdef CFG_MMU_ENABLED
+assign tmem_write_data[`LM32_IC_TAGS_TAG_RNG] = physical_refill_address[`LM32_IC_ADDR_TAG_RNG];
+`else
assign tmem_write_data[`LM32_IC_TAGS_TAG_RNG] = refill_address[`LM32_IC_ADDR_TAG_RNG];
+`endif
// Signals that indicate which state we are in
assign flushing = |state[1:0];
@@ -378,7 +563,10 @@ begin
begin
state <= `LM32_IC_STATE_FLUSH_INIT;
flush_set <= {`LM32_IC_TMEM_ADDR_WIDTH{1'b1}};
- refill_address <= {`LM32_PC_WIDTH{1'bx}};
+ refill_address <= {`LM32_PC_WIDTH{1'b0}};
+`ifdef CFG_MMU_ENABLED
+ physical_refill_address <= {`LM32_PC_WIDTH{1'b0}};
+`endif
restart_request <= `FALSE;
end
else
@@ -414,11 +602,17 @@ begin
restart_request <= `FALSE;
if (iflush == `TRUE)
begin
+`ifdef CFG_MMU_ENABLED
+ physical_refill_address <= physical_address[`LM32_PC_RNG];
+`endif
refill_address <= address_f;
state <= `LM32_IC_STATE_FLUSH;
end
- else if (miss == `TRUE)
+ else if (miss == `TRUE && itlb_miss_int == `FALSE)
begin
+`ifdef CFG_MMU_ENABLED
+ physical_refill_address <= physical_address[`LM32_PC_RNG];
+`endif
refill_address <= address_f;
state <= `LM32_IC_STATE_REFILL;
end
@@ -474,7 +668,247 @@ begin
end
end
endgenerate
-
+
+`ifdef CFG_MMU_ENABLED
+
+// Compute address to use to index into the ITLB data memory
+assign itlb_data_read_address = address_a[`LM32_ITLB_IDX_RNG];
+
+// tlb_update_address will receive data from a CSR register
+assign itlb_data_write_address = itlb_update_vaddr_csr_reg[`LM32_ITLB_IDX_RNG];
+
+assign itlb_data_read_port_enable = (stall_a == `FALSE) || !stall_f;
+assign itlb_write_port_enable = itlb_updating || itlb_flushing;
+
+assign physical_address = (itlb_enabled == `FALSE)
+ ? {address_f, 2'b0}
+ : {itlb_lookup, address_f[`LM32_PAGE_OFFSET_RNG+2], 2'b0};
+
+assign itlb_write_data = (itlb_flushing == `TRUE)
+ ? {`FALSE, {addr_itlb_tag_width{1'b0}}, {vpfn_width{1'b0}}}
+ : {`TRUE, {itlb_update_vaddr_csr_reg[`LM32_ITLB_ADDR_TAG_RNG]}, itlb_update_paddr_csr_reg[`LM32_ITLB_ADDRESS_PFN_RNG]};
+
+assign pa = physical_address;
+assign kernel_mode = kernel_mode_reg;
+
+assign csr_read_data = {itlb_miss_addr, 2'b0};
+assign itlb_miss = (itlb_enabled == `TRUE) && (read_enable_f) && ~(itlb_data_valid) && (~itlb_miss_q);
+assign itlb_miss_int = (itlb_miss || itlb_miss_q);
+assign itlb_read_tag = itlb_read_data[`LM32_ITLB_TAG_RANGE];
+assign itlb_data_valid = itlb_read_data[`LM32_ITLB_VALID_BIT];
+assign itlb_lookup = itlb_read_data[`LM32_ITLB_LOOKUP_RANGE];
+
+`ifdef CFG_VERBOSE_DISPLAY_ENABLED
+always @(posedge clk_i)
+begin
+ if (itlb_write_port_enable)
+ begin
+ $display("[ITLB data : %d] Writing 0x%08X to 0x%08X", $time, itlb_write_data, itlb_data_write_address);
+ end
+end
+`endif
+
+always @(posedge clk_i `CFG_RESET_SENSITIVITY)
+begin
+ if (rst_i == `TRUE)
+ go_to_user_mode <= `FALSE;
+ else
+ go_to_user_mode <= (eret_q_x || switch_to_user_mode);
+end
+
+always @(posedge clk_i `CFG_RESET_SENSITIVITY)
+begin
+ if (rst_i == `TRUE)
+ go_to_user_mode_2 <= `FALSE;
+ else
+ go_to_user_mode_2 <= go_to_user_mode;
+end
+
+always @(posedge clk_i `CFG_RESET_SENSITIVITY)
+begin
+ if (rst_i == `TRUE)
+ kernel_mode_reg <= `LM32_KERNEL_MODE;
+ else
+ begin
+ if (exception_x || switch_to_kernel_mode)
+ kernel_mode_reg <= `LM32_KERNEL_MODE;
+ else if (go_to_user_mode_2)
+ kernel_mode_reg <= `LM32_USER_MODE;
+ end
+end
+
+always @(posedge clk_i `CFG_RESET_SENSITIVITY)
+begin
+ if (rst_i == `TRUE)
+ itlb_miss_q <= `FALSE;
+ else
+ begin
+ if (itlb_miss && ~itlb_miss_q)
+ itlb_miss_q <= `TRUE;
+ else if (itlb_miss_q && /* exception_m == `TRUE */ exception_x == `TRUE && stall_m == `FALSE && stall_x == `FALSE && q_x == `TRUE)
+ itlb_miss_q <= `FALSE;
+ end
+end
+
+// CSR Write
+always @(posedge clk_i `CFG_RESET_SENSITIVITY)
+begin
+ if (rst_i == `TRUE)
+ begin
+ itlb_ctrl_csr_reg <= `LM32_WORD_WIDTH'd0;
+ itlb_update_vaddr_csr_reg <= `LM32_WORD_WIDTH'd0;
+ itlb_update_paddr_csr_reg <= `LM32_WORD_WIDTH'd0;
+ end
+ else
+ begin
+ if (csr_write_enable)
+ begin
+ case (csr)
+ `LM32_CSR_TLB_CTRL: if (~csr_write_data[0]) itlb_ctrl_csr_reg[31:1] <= csr_write_data[31:1];
+ `LM32_CSR_TLB_VADDRESS: if (~csr_write_data[0]) itlb_update_vaddr_csr_reg[31:1] <= csr_write_data[31:1];
+ `LM32_CSR_TLB_PADDRESS: if (~csr_write_data[0]) itlb_update_paddr_csr_reg[31:1] <= csr_write_data[31:1];
+ endcase
+ end
+ itlb_ctrl_csr_reg[0] <= 0;
+ itlb_update_vaddr_csr_reg[0] <= 0;
+ itlb_update_paddr_csr_reg[0] <= 0;
+ end
+end
+
+reg [`LM32_PC_RNG] pc_exception;
+reg in_exception;
+
+always @(posedge clk_i `CFG_RESET_SENSITIVITY)
+begin
+ if (rst_i == `TRUE)
+ begin
+ itlb_enabled <= `FALSE;
+ in_exception <= `FALSE;
+ pc_exception <= {`LM32_PC_WIDTH{1'b0}};
+ end
+ else
+ begin
+ if (~stall_x)
+ begin
+ if (eret_q_x)
+ begin
+// $display("[%t] itlb_enabled <= 0x%08X upon eret", $time, csr_psw[`LM32_CSR_PSW_EITLBE]);
+ itlb_enabled <= csr_psw[`LM32_CSR_PSW_EITLBE];
+ end
+ else if (exception_x || in_exception)
+ begin
+ if (~in_exception)
+ begin
+ in_exception <= 1;
+ end
+ else
+ begin
+ if (exception_m)
+ begin
+ $display("[%t] pc_exception <= 0x%08X", $time, pc_m);
+ pc_exception <= pc_m;
+ end
+ if (pc_exception == pc_w)
+ begin
+ in_exception <= 0;
+ end
+ $display("[%t] itlb_enabled <= 0x%08X upon exception", $time, 0);
+ itlb_enabled <= 0;
+ end
+ end
+ else
+ begin
+ if (itlb_enabled != csr_psw[`LM32_CSR_PSW_ITLBE])
+// $display("[%t] itlb_enabled <= 0x%08X", $time, csr_psw[`LM32_CSR_PSW_ITLBE]);
+
+ itlb_enabled <= csr_psw[`LM32_CSR_PSW_ITLBE];
+ end
+ end
+ end
+end
+
+always @(posedge clk_i `CFG_RESET_SENSITIVITY)
+begin
+ if (rst_i == `TRUE)
+ begin
+ $display("ITLB STATE MACHINE RESET");
+ itlb_flushing <= 1;
+ itlb_flush_set <= {addr_itlb_index_width{1'b1}};
+ itlb_state <= `LM32_TLB_STATE_FLUSH;
+ itlb_updating <= 0;
+ itlb_miss_addr <= {`LM32_PC_WIDTH{1'b0}};
+ end
+ else
+ begin
+ case (itlb_state)
+
+ `LM32_TLB_STATE_CHECK:
+ begin
+ itlb_updating <= 0;
+ itlb_flushing <= 0;
+ if (itlb_miss == `TRUE)
+ begin
+ itlb_miss_addr <= address_f;
+ $display("WARNING : ITLB MISS on addr 0x%08X at time %t", address_f * 4, $time);
+ end
+ if (csr_write_enable && ~csr_write_data[0])
+ begin
+ // FIXME : test for kernel mode is removed for testing purposes ONLY
+ if (csr == `LM32_CSR_TLB_CTRL /*&& (kernel_mode_reg == `LM32_KERNEL_MODE)*/)
+ begin
+`ifdef CFG_VERBOSE_DISPLAY_ENABLED
+ $display("ITLB WCSR at %t with csr_write_data == 0x%08X", $time, csr_write_data);
+`endif
+ case (csr_write_data[5:1])
+ `LM32_ITLB_CTRL_FLUSH:
+ begin
+`ifdef CFG_VERBOSE_DISPLAY_ENABLED
+ $display("it's a FLUSH at %t", $time);
+`endif
+ itlb_flushing <= 1;
+ itlb_flush_set <= {addr_itlb_index_width{1'b1}};
+ itlb_state <= `LM32_TLB_STATE_FLUSH;
+ itlb_updating <= 0;
+ end
+
+ `LM32_ITLB_CTRL_UPDATE:
+ begin
+`ifdef CFG_VERBOSE_DISPLAY_ENABLED
+ $display("it's an UPDATE at %t", $time);
+`endif
+ itlb_updating <= 1;
+ end
+
+ `LM32_TLB_CTRL_INVALIDATE_ENTRY:
+ begin
+`ifdef CFG_VERBOSE_DISPLAY_ENABLED
+ $display("it's an INVALIDATE ENTRY at %t", $time);
+`endif
+ itlb_flushing <= 1;
+ itlb_flush_set <= itlb_update_vaddr_csr_reg[`LM32_ITLB_IDX_RNG];
+ itlb_updating <= 0;
+ itlb_state <= `LM32_TLB_STATE_CHECK;
+ end
+
+ endcase
+ end
+ end
+ end
+
+ `LM32_TLB_STATE_FLUSH:
+ begin
+ itlb_updating <= 0;
+ if (itlb_flush_set == {addr_itlb_index_width{1'b0}})
+ itlb_state <= `LM32_TLB_STATE_CHECK;
+ itlb_flush_set <= itlb_flush_set - 1'b1;
+ end
+
+ endcase
+ end
+end
+
+`endif
+
endmodule
`endif
View
115 cores/lm32/rtl/lm32_instruction_unit.v
@@ -99,6 +99,10 @@ module lm32_instruction_unit (
branch_target_x,
`endif
exception_m,
+`ifdef CFG_MMU_ENABLED
+ exception_x,
+ csr_psw,
+`endif
branch_taken_m,
branch_mispredict_taken_m,
branch_target_m,
@@ -115,6 +119,13 @@ module lm32_instruction_unit (
irom_address_xm,
irom_we_xm,
`endif
+`ifdef CFG_MMU_ENABLED
+ csr,
+ csr_write_data,
+ csr_write_enable,
+ eret_q_x,
+ q_x,
+`endif
`ifdef CFG_IWB_ENABLED
// From Wishbone
i_dat_i,
@@ -129,6 +140,9 @@ module lm32_instruction_unit (
`endif
// ----- Outputs -------
// To pipeline
+`ifdef CFG_PIPELINE_TRACES
+ pc_a,
+`endif
pc_f,
pc_d,
pc_x,
@@ -143,6 +157,10 @@ module lm32_instruction_unit (
`ifdef CFG_IROM_ENABLED
irom_data_m,
`endif
+`ifdef CFG_MMU_ENABLED
+ itlb_miss,
+ csr_read_data,
+`endif
`ifdef CFG_IWB_ENABLED
// To Wishbone
i_dat_o,
@@ -245,6 +263,16 @@ input [`LM32_BYTE_RNG] jtag_write_data; // JTAG wrirte data
input [`LM32_WORD_RNG] jtag_address; // JTAG read/write address
`endif
+`ifdef CFG_MMU_ENABLED
+input exception_x; // An exception occured in the X stage
+input eret_q_x;
+input q_x;
+input [`LM32_CSR_RNG] csr; // CSR read/write index
+input [`LM32_WORD_RNG] csr_write_data; // Data to write to specified CSR
+input csr_write_enable; // CSR write enable
+input [`LM32_WORD_RNG] csr_psw;
+`endif
+
/////////////////////////////////////////////////////
// Outputs
/////////////////////////////////////////////////////
@@ -327,11 +355,21 @@ wire [`LM32_INSTRUCTION_RNG] instruction_f;
output [`LM32_INSTRUCTION_RNG] instruction_d; // D stage instruction to be decoded
reg [`LM32_INSTRUCTION_RNG] instruction_d;
+`ifdef CFG_MMU_ENABLED
+output csr_read_data;
+wire [`LM32_WORD_RNG] csr_read_data;
+output itlb_miss;
+wire itlb_miss;
+`endif
+
/////////////////////////////////////////////////////
// Internal nets and registers
/////////////////////////////////////////////////////
reg [`LM32_PC_RNG] pc_a; // A stage PC
+`ifdef CFG_PIPELINE_TRACES
+output [`LM32_PC_RNG] pc_a;
+`endif
`ifdef LM32_CACHE_ENABLED
reg [`LM32_PC_RNG] restart_address; // Address to restart from after a cache miss
@@ -340,6 +378,9 @@ reg [`LM32_PC_RNG] restart_address; // Address to restart fr
`ifdef CFG_ICACHE_ENABLED
wire icache_read_enable_f; // Indicates if instruction cache miss is valid
wire [`LM32_PC_RNG] icache_refill_address; // Address that caused cache miss
+`ifdef CFG_MMU_ENABLED
+wire [`LM32_PC_RNG] icache_physical_refill_address; // Physical address that caused cache miss
+`endif
reg icache_refill_ready; // Indicates when next word of refill data is ready to be written to cache
reg [`LM32_INSTRUCTION_RNG] icache_refill_data; // Next word of refill data, fetched from Wishbone
wire [`LM32_INSTRUCTION_RNG] icache_data_f; // Instruction fetched from instruction cache
@@ -373,6 +414,11 @@ reg jtag_access; // Indicates if a JTAG W
reg alternate_eba_taken;
`endif
+`ifdef CFG_MMU_ENABLED
+wire [`LM32_WORD_RNG] physical_address;
+wire kernel_mode;
+`endif
+
/////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////
@@ -446,20 +492,48 @@ lm32_icache #(
.rst_i (rst_i),
.stall_a (stall_a),
.stall_f (stall_f),
+`ifdef CFG_MMU_ENABLED
+ .stall_x (stall_x),
+ .stall_m (stall_m),
+`endif
.branch_predict_taken_d (branch_predict_taken_d),
.valid_d (valid_d),
.address_a (pc_a),
.address_f (pc_f),
+`ifdef CFG_MMU_ENABLED
+ .pc_x (pc_x),
+ .pc_m (pc_m),
+ .pc_w (pc_w),
+`endif
.read_enable_f (icache_read_enable_f),
.refill_ready (icache_refill_ready),
.refill_data (icache_refill_data),
.iflush (iflush),
+`ifdef CFG_MMU_ENABLED
+ .csr (csr),
+ .csr_write_data (csr_write_data),
+ .csr_write_enable (csr_write_enable),
+ .csr_psw (csr_psw),
+ .exception_x (exception_x),
+ .eret_q_x (eret_q_x),
+ .exception_m (exception_m),
+ .q_x (q_x),
+`endif
// ----- Outputs -----
.stall_request (icache_stall_request),
.restart_request (icache_restart_request),
.refill_request (icache_refill_request),
.refill_address (icache_refill_address),
+`ifdef CFG_MMU_ENABLED
+ .physical_refill_address (icache_physical_refill_address),
+`endif
.refilling (icache_refilling),
+`ifdef CFG_MMU_ENABLED
+ .itlb_miss_int (itlb_miss),
+ .kernel_mode (kernel_mode),
+ .pa (physical_address),
+ .csr_read_data (csr_read_data),
+`endif
.inst (icache_data_f)
);
`endif
@@ -487,27 +561,52 @@ begin
// The request from the latest pipeline stage must take priority
`ifdef CFG_DCACHE_ENABLED
if (dcache_restart_request == `TRUE)
+ begin
+`ifdef CFG_PIPELINE_TRACES
+ $display("[%t] We restart to 0x%08X because of DCACHE", $time, restart_address);
+`endif
pc_a = restart_address;
+ end
else
`endif
if (branch_taken_m == `TRUE)
if ((branch_mispredict_taken_m == `TRUE) && (exception_m == `FALSE))
+ begin
+`ifdef CFG_PIPELINE_TRACES
+ $display("[%t] Mispredict, goto pc_x == 0x%08X", $time, pc_x);
+`endif
pc_a = pc_x;
+ end
else
+ begin
+`ifdef CFG_PIPELINE_TRACES
+ $display("[%t] Correctly predicted, goto branch_target_m == 0x%08X", $time, branch_target_m);
+`endif
pc_a = branch_target_m;
-`ifdef CFG_FAST_UNCONDITIONAL_BRANCH
+ end
+`ifdef CFG_FAST_UNCONDITIONAL_BRANCH
else if (branch_taken_x == `TRUE)
pc_a = branch_target_x;
`endif
else
if ( (valid_d == `TRUE) && (branch_predict_taken_d == `TRUE) )
+ begin
+`ifdef CFG_PIPELINE_TRACES
+ $display("[%t] We go to branch_predict_address_d == 0x%08X", $time, branch_predict_address_d);
+`endif
pc_a = branch_predict_address_d;
+ end
else
`ifdef CFG_ICACHE_ENABLED
if (icache_restart_request == `TRUE)
+ begin
+`ifdef CFG_PIPELINE_TRACES
+ $display("[%t] We restart to 0x%08X because of ICACHE", $time, restart_address);
+`endif
pc_a = restart_address;
+ end
else
-`endif
+`endif
pc_a = pc_f + 1'b1;
end
@@ -555,21 +654,33 @@ generate
assign first_cycle_type = `LM32_CTYPE_END;
assign next_cycle_type = `LM32_CTYPE_END;
assign last_word = `TRUE;
+`ifdef CFG_MMU_ENABLED
+assign first_address = icache_physical_refill_address;
+`else
assign first_address = icache_refill_address;
+`endif
end
8:
begin
assign first_cycle_type = `LM32_CTYPE_INCREMENTING;
assign next_cycle_type = `LM32_CTYPE_END;
assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 1'b1;
+`ifdef CFG_MMU_ENABLED
+assign first_address = {icache_physical_refill_address[`LM32_PC_WIDTH+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
+`else
assign first_address = {icache_refill_address[`LM32_PC_WIDTH+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
+`endif
end
16:
begin
assign first_cycle_type = `LM32_CTYPE_INCREMENTING;
assign next_cycle_type = i_adr_o[addr_offset_msb] == 1'b1 ? `LM32_CTYPE_END : `LM32_CTYPE_INCREMENTING;
assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 2'b11;
+`ifdef CFG_MMU_ENABLED
+assign first_address = {icache_physical_refill_address[`LM32_PC_WIDTH+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
+`else
assign first_address = {icache_refill_address[`LM32_PC_WIDTH+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
+`endif
end
endcase
endgenerate
View
2  cores/lm32/rtl/lm32_interrupt.v
@@ -266,7 +266,7 @@ begin
else if (csr_write_enable == `TRUE)
begin
// Handle wcsr write
- if (csr == `LM32_CSR_IE)
+ if ((csr == `LM32_CSR_IE) || (csr == `LM32_CSR_PSW))
begin
ie <= csr_write_data[0];
eie <= csr_write_data[1];
View
50 cores/lm32/rtl/lm32_load_store_unit.v
@@ -99,10 +99,13 @@ module lm32_load_store_unit (
`ifdef CFG_IROM_ENABLED
irom_data_m,
`endif
+`ifdef CFG_MMU_ENABLED
csr,
csr_write_data,
csr_write_enable,
eret_q_x,
+ csr_psw,
+`endif
// From Wishbone
d_dat_i,
d_ack_i,
@@ -124,8 +127,10 @@ module lm32_load_store_unit (
`endif
load_data_w,
stall_wb_load,
+`ifdef CFG_MMU_ENABLED
dtlb_miss,
csr_read_data,
+`endif
// To Wishbone
d_dat_o,
d_adr_o,
@@ -169,11 +174,12 @@ input exception_m; // An exception occured
input exception_x; // An exception occured in the X stage
input eret_q_x;
-
+`ifdef CFG_MMU_ENABLED
input [`LM32_CSR_RNG] csr; // CSR read/write index
input [`LM32_WORD_RNG] csr_write_data; // Data to write to specified CSR
input csr_write_enable; // CSR write enable
-
+input [`LM32_WORD_RNG] csr_psw;
+`endif
input [`LM32_WORD_RNG] store_operand_x; // Data read from register to store
input [`LM32_WORD_RNG] load_store_address_x; // X stage load/store address
@@ -196,8 +202,10 @@ input dflush; // Flush the data cache
input [`LM32_WORD_RNG] irom_data_m; // Data from Instruction-ROM
`endif
+`ifdef CFG_MMU_ENABLED
wire dtlb_miss;
output dtlb_miss;
+`endif
input [`LM32_WORD_RNG] d_dat_i; // Data Wishbone interface read data
input d_ack_i; // Data Wishbone interface acknowledgement
@@ -219,8 +227,10 @@ output dcache_refilling;
wire dcache_refilling;
`endif
+`ifdef CFG_MMU_ENABLED
output csr_read_data;
wire [`LM32_WORD_RNG] csr_read_data;
+`endif
`ifdef CFG_IROM_ENABLED
output irom_store_data_m; // Store data to Instruction ROM
@@ -279,7 +289,6 @@ reg dcache_select_m;
wire [`LM32_WORD_RNG] dcache_data_m; // Data read from cache
wire [`LM32_WORD_RNG] dcache_refill_address; // Address to refill data cache from
reg dcache_refill_ready; // Indicates the next word of refill data is ready
-reg d_adr_o_sampling;
wire [`LM32_CTYPE_RNG] first_cycle_type; // First Wishbone cycle type
wire [`LM32_CTYPE_RNG] next_cycle_type; // Next Wishbone cycle type
wire last_word; // Indicates if this is the last word in the cache line
@@ -303,8 +312,10 @@ reg wb_select_m;
reg [`LM32_WORD_RNG] wb_data_m; // Data read from Wishbone
reg wb_load_complete; // Indicates when a Wishbone load is complete
+`ifdef CFG_MMU_ENABLED
wire [`LM32_WORD_RNG] physical_address;
wire kernel_mode;
+`endif
/////////////////////////////////////////////////////
// Functions
@@ -424,23 +435,28 @@ lm32_dcache #(
.refill_ready (dcache_refill_ready),
.refill_data (wb_data_m),
.dflush (dflush),
+`ifdef CFG_MMU_ENABLED
.csr (csr),
.csr_write_data (csr_write_data),
.csr_write_enable (csr_write_enable),
.exception_x (exception_x),
.eret_q_x (eret_q_x),
.exception_m (exception_m),
+ .csr_psw (csr_psw),
+`endif
// ----- Outputs -----
.stall_request (dcache_stall_request),
.restart_request (dcache_restart_request),
.refill_request (dcache_refill_request),
.refill_address (dcache_refill_address),
.refilling (dcache_refilling),
- .load_data (dcache_data_m),
+`ifdef CFG_MMU_ENABLED
.dtlb_miss_int (dtlb_miss),
.kernel_mode (kernel_mode),
.pa (physical_address),
- .csr_read_data (csr_read_data)
+ .csr_read_data (csr_read_data),
+`endif
+ .load_data (dcache_data_m)
);
`endif
@@ -664,7 +680,6 @@ always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
begin
- d_adr_o_sampling <= `FALSE;
d_cyc_o <= `FALSE;
d_stb_o <= `FALSE;
d_dat_o <= {`LM32_WORD_WIDTH{1'b0}};
@@ -701,7 +716,6 @@ begin
else
`endif
begin
- d_adr_o_sampling <= 0;
// Refill/access complete
d_cyc_o <= `FALSE;
d_stb_o <= `FALSE;
@@ -728,10 +742,11 @@ begin
if (dcache_refill_request == `TRUE)
begin
// Start cache refill
+`ifdef CFG_MMU_ENABLED
`ifdef CFG_VERBOSE_DISPLAY_ENABLED
$display("Sampling address to refill 0x%08X\n", first_address);
`endif
- d_adr_o_sampling <= 1;
+`endif
d_adr_o <= first_address;
d_cyc_o <= `TRUE;
d_sel_o <= {`LM32_WORD_WIDTH/8{`TRUE}};
@@ -756,12 +771,17 @@ begin
)
begin
// Data cache is write through, so all stores go to memory
+`ifdef CFG_MMU_ENABLED
`ifdef CFG_VERBOSE_DISPLAY_ENABLED
$display("Sampling address to write through 0x%08X\n", store_data_m);
`endif
- d_adr_o_sampling <= 1;
+`endif
d_dat_o <= store_data_m;
- d_adr_o <= (kernel_mode == `LM32_KERNEL_MODE) ? load_store_address_m : physical_address;
+ d_adr_o <=
+`ifdef CFG_MMU_ENABLED
+ (kernel_mode == `LM32_USER_MODE) ? physical_address :
+`endif
+ load_store_address_m;
d_cyc_o <= `TRUE;
d_sel_o <= byte_enable_m;
d_stb_o <= `TRUE;
@@ -775,12 +795,18 @@ begin
)
begin
// Read requested address
+`ifdef CFG_MMU_ENABLED
`ifdef CFG_VERBOSE_DISPLAY_ENABLED
$display("Sampling address to read 0x%08X\n", (kernel_mode == `LM32_KERNEL_MODE) ? load_store_address_m : physical_address);
`endif
- d_adr_o_sampling <= 1;
+`endif
stall_wb_load <= `FALSE;
- d_adr_o <= (kernel_mode == `LM32_KERNEL_MODE) ? load_store_address_m : physical_address;
+ d_adr_o <=
+`ifdef CFG_MMU_ENABLED
+ (kernel_mode == `LM32_USER_MODE) ? physical_address :
+`endif
+ load_store_address_m;
+
d_cyc_o <= `TRUE;
d_sel_o <= byte_enable_m;
d_stb_o <= `TRUE;
View
4 software/bios/Makefile
@@ -1,8 +1,8 @@
MMDIR=../..
include $(MMDIR)/software/include.mak
-OBJECTS=crt0.o isr.o main.o unlzma.o boot.o boot-helper.o splash.o dtlb_load_test.o dtlb_exception_handling_tests.o dtlb_miss_handler.o
-SEGMENTS=-j .text -j .data -j .rodata
+OBJECTS=crt0.o isr.o main.o unlzma.o boot.o boot-helper.o splash.o dtlb_load_test.o dtlb_exception_handling_tests.o tlb_miss_handler.o itlbtest.o
+SEGMENTS=-j .text -j .data -j .rodata -j .got -j .got.plt
LIBS=$(MMDIR)/software/libhpdmc/libhpdmc.a $(MMDIR)/software/libbase/libbase-light.a \
$(MMDIR)/software/libhal/libhal.a $(MMDIR)/software/libnet/libnet.a
CFLAGS += -g
View
10 software/bios/crt0.S
@@ -117,6 +117,16 @@ _dtlb_miss_exception_handler:
nop
nop
+_itlb_miss_exception_handler:
+ sw (sp+0), ra
+ calli .save_all
+ calli itlb_miss_handler
+ bi .restore_all_and_eret
+ nop
+ nop
+ nop
+ nop
+
macaddress:
.byte 0x10
.byte 0xe2
View
8 software/bios/dtlb_exception_handling_tests.c
@@ -27,10 +27,10 @@ void dtlb_exception_handling_tests() {
asm volatile("mv %0, sp" : "=r"(stack) :: );
- ret = mmu_map(stack, stack);
+ ret = mmu_map(stack, stack, DTLB_MAPPING | MAPPING_CAN_READ | MAPPING_CAN_WRITE);
check_for_error(ret);
- ret = mmu_map(stack-0x1000, stack-0x1000);
+ ret = mmu_map(stack-0x1000, stack-0x1000, DTLB_MAPPING | MAPPING_CAN_READ | MAPPING_CAN_WRITE);
check_for_error(ret);
printf("stack == 0x%08X\n", stack);
@@ -38,7 +38,7 @@ void dtlb_exception_handling_tests() {
addr = 0x44004004;
printf("\n=> Mapping 0x%08X to 0x%08X\n", addr, addr);
- ret = mmu_map(addr, addr);
+ ret = mmu_map(addr, addr, DTLB_MAPPING | MAPPING_CAN_READ | MAPPING_CAN_WRITE);
check_for_error(ret);
data = 42;
@@ -63,7 +63,7 @@ void dtlb_exception_handling_tests() {
printf("\n<= Reading %d from virtual address 0x%08X\n\n", data, addr);
printf("=> Mapping 0x%08X to 0%08X\n", addr, addr+0x1000);
- ret = mmu_map(addr, addr+0x1000); // Map to something else
+ ret = mmu_map(addr, addr+0x1000, DTLB_MAPPING | MAPPING_CAN_READ | MAPPING_CAN_WRITE); // Map to something else
check_for_error(ret);
printf("=> Invalidating the mapping of virtual address 0x%08X in the TLB\n", addr);
View
43 software/bios/dtlb_miss_handler.c
@@ -1,43 +0,0 @@
-/*
- * Milkymist SoC (Software)
- * Copyright (C) 2012 Yann Sionneau <yann.sionneau@gmail.com>
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, version 3 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <hal/mmu.h>
-#include <base/mmu.h>
-
-void dtlb_miss_handler(void)
-{
- unsigned int vaddr, paddr;
-
- // retrieve virtual address which caused the page fault
- asm volatile("rcsr %0, dtlbma" : "=r"(vaddr) :: );
-
- /*
- * check if there is an existing mapping for that virtual address
- * if yes: refill the DTLB with it
- * if not: we panic() !
- */
- paddr = get_mmu_mapping_for(vaddr);
- if (paddr == A_BAD_ADDR)
- {
- puts("[TLB miss handler] Unrecoverable page fault !");
- panic();
- }
-
- printf("[TLB miss handler] Refilling DTLB with mapping 0x%08X->0x%08X\n", vaddr, paddr);
- mmu_dtlb_map(vaddr, paddr);
-
-}
View
6 software/bios/main.c
@@ -431,6 +431,7 @@ static void help()
puts("mmuread - reads from memory with MMU enabled");
puts("mmuwrite - writes to memory with MMU enabled");
puts("dtlbtest - runs DTLB MMU load store tests");
+ puts("itlbtest - runs ITLB MMU tests");
puts("detest - runs DTLB MMU exception handling tests");
}
@@ -616,6 +617,7 @@ static void do_command(char *c)
else if(strcmp(token, "rcsr") == 0) rcsr(get_token(&c));
else if(strcmp(token, "wcsr") == 0) wcsr(get_token(&c), get_token(&c));
else if(strcmp(token, "dtlbtest") == 0) dtlbtest();
+ else if(strcmp(token, "itlbtest") == 0) itlbtest();
else if(strcmp(token, "detest") == 0) dtlb_exception_handling_tests();
else if(strcmp(token, "dmap") == 0) dmap(get_token(&c), get_token(&c));
else if(strcmp(token, "dunmap") == 0) dunmap(get_token(&c));
@@ -794,6 +796,10 @@ int main(int i, char **c)
printf("I: Booting in rescue mode\n");
uart_set_polling_mode(1);
+/*
+ mmu_dtlb_invalidate();
+ mmu_itlb_invalidate();
+*/
while(1) {
putsnonl("\e[1mBIOS>\e[0m ");
readstr(buffer, 64);
View
91 software/bios/tlb_miss_handler.c
@@ -0,0 +1,91 @@
+/*
+ * Milkymist SoC (Software)
+ * Copyright (C) 2012 Yann Sionneau <yann.sionneau@gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 3 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <hal/mmu.h>