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Add support for rcsr TLBCTRL

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commit 8505b54f58a50aca182864b8b1d7f9840651ba68 1 parent 8018524
@fallen authored
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3  cores/lm32/rtl/lm32_cpu.v
@@ -616,6 +616,7 @@ wire mc_stall_request_x; // Multi-cycle arithmetic unit s
wire [`LM32_WORD_RNG] mc_result_x;
`endif
+wire [`LM32_WORD_RNG] load_store_csr_read_data_x;// Data read from load store CSRs
// From CSRs
`ifdef CFG_INTERRUPTS_ENABLED
wire [`LM32_WORD_RNG] interrupt_csr_read_data_x;// Data read from interrupt CSRs
@@ -1027,6 +1028,7 @@ lm32_load_store_unit #(
.load_data_w (load_data_w),
.stall_wb_load (stall_wb_load),
.dtlb_miss (dtlb_miss),
+ .csr_read_data (load_store_csr_read_data_x),
// To Wishbone
.d_dat_o (D_DAT_O),
.d_adr_o (D_ADR_O),
@@ -2128,6 +2130,7 @@ begin
`LM32_CSR_JRX: csr_read_data_x = jrx_csr_read_data;
`endif
`LM32_CSR_CFG2: csr_read_data_x = cfg2;
+ `LM32_CSR_TLB_CTRL: csr_read_data_x = load_store_csr_read_data_x;
default: csr_read_data_x = {`LM32_WORD_WIDTH{1'bx}};
endcase
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23 cores/lm32/rtl/lm32_dcache.v
@@ -117,7 +117,8 @@ module lm32_dcache (
// To pipeline
dtlb_miss,
kernel_mode,
- pa
+ pa,
+ csr_read_data
);
/////////////////////////////////////////////////////
@@ -195,6 +196,9 @@ input csr_write_enable; // CSR write enable
// Outputs
/////////////////////////////////////////////////////
+output csr_read_data;
+reg [`LM32_WORD_RNG] csr_read_data;
+
output stall_request; // Request pipeline be stalled because cache is busy
wire stall_request;
output restart_request; // Request to restart instruction that caused the cache miss
@@ -261,6 +265,7 @@ wire [`LM32_WORD_RNG] physical_address;
wire [`LM32_WORD_RNG] pa;
output [`LM32_WORD_RNG] pa;
+reg [`LM32_WORD_RNG] latest_store_tlb_lookup;
assign pa = physical_address;
@@ -442,9 +447,9 @@ begin
`LM32_CSR_TLB_PADDRESS: if (csr_write_data[0]) dtlb_update_paddr_csr_reg[31:1] <= csr_write_data[31:1];
endcase
end
- dtlb_ctrl_csr_reg[31] <= 0;
- dtlb_update_vaddr_csr_reg[31] <= 0;
- dtlb_update_paddr_csr_reg[31] <= 0;
+ dtlb_ctrl_csr_reg[0] <= 0;
+ dtlb_update_vaddr_csr_reg[0] <= 0;
+ dtlb_update_paddr_csr_reg[0] <= 0;
end
// Compute which ways in the cache match the address being read
@@ -692,6 +697,16 @@ end
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
+ if (write_port_enable)
+ begin
+ latest_store_tlb_lookup <= { dtlb_read_data , address_m[`LM32_PAGE_OFFSET_RNG] };
+ end
+end
+
+assign csr_read_data = latest_store_tlb_lookup;
+
+always @(posedge clk_i `CFG_RESET_SENSITIVITY)
+begin
if (rst_i == `TRUE)
begin
dtlb_flushing <= 1;
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7 cores/lm32/rtl/lm32_load_store_unit.v
@@ -123,6 +123,7 @@ module lm32_load_store_unit (
load_data_w,
stall_wb_load,
dtlb_miss,
+ csr_read_data,
// To Wishbone
d_dat_o,
d_adr_o,
@@ -212,6 +213,9 @@ output dcache_refilling;
wire dcache_refilling;
`endif
+output csr_read_data;
+wire [`LM32_WORD_RNG] csr_read_data;
+
`ifdef CFG_IROM_ENABLED
output irom_store_data_m; // Store data to Instruction ROM
wire [`LM32_WORD_RNG] irom_store_data_m;
@@ -425,7 +429,8 @@ lm32_dcache #(
.load_data (dcache_data_m),
.dtlb_miss (dtlb_miss),
.kernel_mode (kernel_mode),
- .pa (physical_address)
+ .pa (physical_address),
+ .csr_read_data (csr_read_data)
);
`endif
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