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Initialize ram blocks for simulation

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commit d255d7c992ecda0dcb65b85e0b2b6270ca294acf 1 parent 5b90cf4
@fallen authored
Showing with 10 additions and 0 deletions.
  1. +10 −0 cores/lm32/rtl/lm32_ram.v
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10 cores/lm32/rtl/lm32_ram.v
@@ -125,4 +125,14 @@ always @(posedge read_clk)
if (enable_read)
ra <= read_address;
+reg [31:0] i;
+
+initial
+begin
+ for (i = 0; i < 2**address_width; i = i + 1)
+ begin
+ mem[i] = {data_width{1'b0}};
+ end
+end
+
endmodule
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