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base fork: fallen/milkymist-mmu
base: 0a6157251ae1
...
head fork: fallen/milkymist-mmu
compare: c4b1a0467fba
  • 2 commits
  • 3 files changed
  • 0 commit comments
  • 1 contributor
View
4 cores/lm32/rtl/lm32_cpu.v
@@ -646,12 +646,12 @@ begin
begin
if (~stall_a)
$display("[%t] Addressing inst @ 0x%08X", $time, pc_a);
- if (~stall_f)
+/* if (~stall_f)
$display("[%t] Fetching inst @ 0x%08X", $time, pc_f);
if (~stall_d)
$display("[%t] Decoding inst @ 0x%08X", $time, pc_d);
if (~stall_x)
- $display("[%t] Executing inst @ 0x%08X", $time, pc_x);
+ $display("[%t] Executing inst @ 0x%08X", $time, pc_x);*/
end
end
`endif
View
15 cores/lm32/rtl/lm32_dcache.v
@@ -780,21 +780,20 @@ begin
end
if (csr_write_enable && csr_write_data[0])
begin
+ if (csr == `LM32_CSR_TLB_PADDRESS)
+ begin
+ dtlb_updating <= 1;
+ end
// FIXME : test for kernel mode is removed for testing purposes ONLY
- if (csr == `LM32_CSR_TLB_CTRL /*&& (kernel_mode_reg == `LM32_KERNEL_MODE)*/)
+ else if (csr == `LM32_CSR_TLB_VADDRESS /*&& (kernel_mode_reg == `LM32_KERNEL_MODE)*/)
begin
+ dtlb_updating <= 0;
case (csr_write_data[5:1])
`LM32_DTLB_CTRL_FLUSH:
begin
dtlb_flushing <= 1;
dtlb_flush_set <= {addr_dtlb_index_width{1'b1}};
dtlb_state <= `LM32_TLB_STATE_FLUSH;
- dtlb_updating <= 0;
- end
-
- `LM32_DTLB_CTRL_UPDATE:
- begin
- dtlb_updating <= 1;
end
`LM32_TLB_CTRL_INVALIDATE_ENTRY:
@@ -807,6 +806,8 @@ begin
endcase
end
+ else
+ dtlb_updating <= 0;
end
end
View
29 cores/lm32/rtl/lm32_icache.v
@@ -745,7 +745,7 @@ begin
begin
if (itlb_miss && ~itlb_miss_q && ~(exception_x == `TRUE && stall_m == `FALSE && stall_x == `FALSE && q_x == `TRUE))
itlb_miss_q <= `TRUE;
- else if (itlb_miss_q && /* exception_m == `TRUE */ exception_x == `TRUE && stall_m == `FALSE && stall_x == `FALSE && q_x == `TRUE)
+ else if (itlb_miss_q && exception_x == `TRUE && stall_m == `FALSE && stall_x == `FALSE && q_x == `TRUE)
itlb_miss_q <= `FALSE;
end
end
@@ -799,7 +799,10 @@ begin
begin
if (~in_exception)
begin
- in_exception <= 1;
+ if (~exception_m)
+ in_exception <= 1;
+ else
+ in_exception <= 0;
end
else
begin
@@ -812,14 +815,14 @@ begin
begin
in_exception <= 0;
end
+ end
$display("[%t] itlb_enabled <= 0x%08X upon exception", $time, 0);
itlb_enabled <= 0;
- end
end
else
begin
if (itlb_enabled != csr_psw[`LM32_CSR_PSW_ITLBE])
-// $display("[%t] itlb_enabled <= 0x%08X", $time, csr_psw[`LM32_CSR_PSW_ITLBE]);
+ $display("[%t] itlb_enabled <= 0x%08X", $time, csr_psw[`LM32_CSR_PSW_ITLBE]);
itlb_enabled <= csr_psw[`LM32_CSR_PSW_ITLBE];
end
@@ -853,8 +856,16 @@ begin
end
if (csr_write_enable && ~csr_write_data[0])
begin
+ if (csr == `LM32_CSR_TLB_PADDRESS /*&& (kernel_mode_reg == `LM32_KERNEL_MODE)*/)
+ begin
+ $display("[%t] ITLB WCSR to PADDR with csr_write_data == 0x%08X", $time, csr_write_data);
+`ifdef CFG_VERBOSE_DISPLAY_ENABLED
+ $display("it's an UPDATE at %t", $time);
+`endif
+ itlb_updating <= 1;
+ end
// FIXME : test for kernel mode is removed for testing purposes ONLY
- if (csr == `LM32_CSR_TLB_CTRL /*&& (kernel_mode_reg == `LM32_KERNEL_MODE)*/)
+ else if (csr == `LM32_CSR_TLB_VADDRESS /*&& (kernel_mode_reg == `LM32_KERNEL_MODE)*/)
begin
`ifdef CFG_VERBOSE_DISPLAY_ENABLED
$display("ITLB WCSR at %t with csr_write_data == 0x%08X", $time, csr_write_data);
@@ -871,14 +882,6 @@ begin
itlb_updating <= 0;
end
- `LM32_ITLB_CTRL_UPDATE:
- begin
-`ifdef CFG_VERBOSE_DISPLAY_ENABLED
- $display("it's an UPDATE at %t", $time);
-`endif
- itlb_updating <= 1;
- end
-
`LM32_TLB_CTRL_INVALIDATE_ENTRY:
begin
`ifdef CFG_VERBOSE_DISPLAY_ENABLED

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