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4  cores/lm32/rtl/lm32_cpu.v
@@ -646,12 +646,12 @@ begin
646 646
 	begin
647 647
 		if (~stall_a)
648 648
 			$display("[%t] Addressing inst @ 0x%08X", $time, pc_a);
649  
-		if (~stall_f)
  649
+/*		if (~stall_f)
650 650
 			$display("[%t] Fetching   inst @ 0x%08X", $time, pc_f);
651 651
 		if (~stall_d)
652 652
 			$display("[%t] Decoding   inst @ 0x%08X", $time, pc_d);
653 653
 		if (~stall_x)
654  
-			$display("[%t] Executing  inst @ 0x%08X", $time, pc_x);
  654
+			$display("[%t] Executing  inst @ 0x%08X", $time, pc_x);*/
655 655
 	end
656 656
 end
657 657
 `endif
15  cores/lm32/rtl/lm32_dcache.v
@@ -780,21 +780,20 @@ begin
780 780
 			end
781 781
 			if (csr_write_enable && csr_write_data[0])
782 782
 			begin
  783
+				if (csr == `LM32_CSR_TLB_PADDRESS)
  784
+				begin
  785
+					dtlb_updating <= 1;
  786
+				end
783 787
 				// FIXME : test for kernel mode is removed for testing purposes ONLY
784  
-				if (csr == `LM32_CSR_TLB_CTRL /*&& (kernel_mode_reg == `LM32_KERNEL_MODE)*/)
  788
+				else if (csr == `LM32_CSR_TLB_VADDRESS /*&& (kernel_mode_reg == `LM32_KERNEL_MODE)*/)
785 789
 				begin
  790
+					dtlb_updating <= 0;
786 791
 					case (csr_write_data[5:1])
787 792
 					`LM32_DTLB_CTRL_FLUSH:
788 793
 					begin
789 794
 						dtlb_flushing <= 1;
790 795
 						dtlb_flush_set <= {addr_dtlb_index_width{1'b1}};
791 796
 						dtlb_state <= `LM32_TLB_STATE_FLUSH;
792  
-						dtlb_updating <= 0;
793  
-					end
794  
-
795  
-					`LM32_DTLB_CTRL_UPDATE:
796  
-					begin
797  
-						dtlb_updating <= 1;
798 797
 					end
799 798
 
800 799
 					`LM32_TLB_CTRL_INVALIDATE_ENTRY:
@@ -807,6 +806,8 @@ begin
807 806
 
808 807
 					endcase
809 808
 				end
  809
+				else
  810
+					dtlb_updating <= 0;
810 811
 			end
811 812
 		end
812 813
 
29  cores/lm32/rtl/lm32_icache.v
@@ -745,7 +745,7 @@ begin
745 745
 	begin
746 746
 		if (itlb_miss && ~itlb_miss_q && ~(exception_x == `TRUE && stall_m == `FALSE && stall_x == `FALSE && q_x == `TRUE))
747 747
 			itlb_miss_q <= `TRUE;
748  
-		else if (itlb_miss_q && /* exception_m == `TRUE */ exception_x == `TRUE && stall_m == `FALSE && stall_x == `FALSE && q_x == `TRUE)
  748
+		else if (itlb_miss_q && exception_x == `TRUE && stall_m == `FALSE && stall_x == `FALSE && q_x == `TRUE)
749 749
 			itlb_miss_q <= `FALSE;
750 750
 	end
751 751
 end
@@ -799,7 +799,10 @@ begin
799 799
 			begin
800 800
 				if (~in_exception)
801 801
 				begin
802  
-					in_exception <= 1;
  802
+					if (~exception_m)
  803
+						in_exception <= 1;
  804
+					else
  805
+						in_exception <= 0;
803 806
 				end
804 807
 				else
805 808
 				begin
@@ -812,14 +815,14 @@ begin
812 815
 					begin
813 816
 						in_exception <= 0;
814 817
 					end
  818
+				end
815 819
 				$display("[%t] itlb_enabled <= 0x%08X upon exception", $time, 0);
816 820
 				itlb_enabled <= 0;
817  
-				end
818 821
 			end
819 822
 			else
820 823
 			begin
821 824
 				if (itlb_enabled != csr_psw[`LM32_CSR_PSW_ITLBE])
822  
-//					$display("[%t] itlb_enabled <= 0x%08X", $time, csr_psw[`LM32_CSR_PSW_ITLBE]);
  825
+					$display("[%t] itlb_enabled <= 0x%08X", $time, csr_psw[`LM32_CSR_PSW_ITLBE]);
823 826
 
824 827
 				itlb_enabled <= csr_psw[`LM32_CSR_PSW_ITLBE];
825 828
 			end
@@ -853,8 +856,16 @@ begin
853 856
 			end
854 857
 			if (csr_write_enable && ~csr_write_data[0])
855 858
 			begin
  859
+				if (csr == `LM32_CSR_TLB_PADDRESS /*&& (kernel_mode_reg == `LM32_KERNEL_MODE)*/)
  860
+				begin
  861
+					$display("[%t] ITLB WCSR to PADDR with csr_write_data == 0x%08X", $time, csr_write_data);
  862
+`ifdef CFG_VERBOSE_DISPLAY_ENABLED
  863
+					$display("it's an UPDATE at %t", $time);
  864
+`endif
  865
+					itlb_updating <= 1;
  866
+				end
856 867
 				// FIXME : test for kernel mode is removed for testing purposes ONLY
857  
-				if (csr == `LM32_CSR_TLB_CTRL /*&& (kernel_mode_reg == `LM32_KERNEL_MODE)*/)
  868
+				else if (csr == `LM32_CSR_TLB_VADDRESS /*&& (kernel_mode_reg == `LM32_KERNEL_MODE)*/)
858 869
 				begin
859 870
 `ifdef CFG_VERBOSE_DISPLAY_ENABLED
860 871
 					$display("ITLB WCSR at %t with csr_write_data == 0x%08X", $time, csr_write_data);
@@ -871,14 +882,6 @@ begin
871 882
 						itlb_updating <= 0;
872 883
 					end
873 884
 
874  
-					`LM32_ITLB_CTRL_UPDATE:
875  
-					begin
876  
-`ifdef CFG_VERBOSE_DISPLAY_ENABLED
877  
-						$display("it's an UPDATE at %t", $time);
878  
-`endif
879  
-						itlb_updating <= 1;
880  
-					end
881  
-
882 885
 					`LM32_TLB_CTRL_INVALIDATE_ENTRY:
883 886
 					begin
884 887
 `ifdef CFG_VERBOSE_DISPLAY_ENABLED

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