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20  cores/lm32/rtl/lm32_cpu.v
@@ -2216,33 +2216,45 @@ begin
2216 2216
 `ifdef CFG_DEBUG_ENABLED
2217 2217
 		if (non_debug_exception_q_w == `TRUE)
2218 2218
 		begin
2219  
-		    // Save and then clear ITLB enable
  2219
+		    // Save and then clear ITLB and DTLB enable
2220 2220
 		    lm32_csr_psw_reg[`LM32_CSR_PSW_EITLBE] <= lm32_csr_psw_reg[`LM32_CSR_PSW_ITLBE];
  2221
+		    lm32_csr_psw_reg[`LM32_CSR_PSW_EDTLBE] <= lm32_csr_psw_reg[`LM32_CSR_PSW_DTLBE];
2221 2222
 		    lm32_csr_psw_reg[`LM32_CSR_PSW_ITLBE] <= `FALSE;
  2223
+		    lm32_csr_psw_reg[`LM32_CSR_PSW_DTLBE] <= `FALSE;
2222 2224
 		end
2223 2225
 		else if (debug_exception_q_w == `TRUE)
2224 2226
 		begin
2225 2227
 		    // Save and then clear TLB enable
2226 2228
 		    lm32_csr_psw_reg[`LM32_CSR_PSW_BITLBE] <= lm32_csr_psw_reg[`LM32_CSR_PSW_ITLBE];
2227 2229
 		    lm32_csr_psw_reg[`LM32_CSR_PSW_ITLBE] <= `FALSE;
  2230
+		    lm32_csr_psw_reg[`LM32_CSR_PSW_BDTLBE] <= lm32_csr_psw_reg[`LM32_CSR_PSW_DTLBE];
  2231
+		    lm32_csr_psw_reg[`LM32_CSR_PSW_DTLBE] <= `FALSE;
2228 2232
 		end
2229 2233
 `else
2230 2234
 		if (exception_q_w == `TRUE)
2231 2235
 		begin
2232  
-		    // Save and then clear ITLB enable
  2236
+		    // Save and then clear ITLB and DTLB enable
2233 2237
 		    lm32_csr_psw_reg[`LM32_CSR_PSW_EITLBE] <= lm32_csr_psw_reg[`LM32_CSR_PSW_ITLBE];
2234 2238
 		    lm32_csr_psw_reg[`LM32_CSR_PSW_ITLBE] <= `FALSE;
  2239
+		    lm32_csr_psw_reg[`LM32_CSR_PSW_EDTLBE] <= lm32_csr_psw_reg[`LM32_CSR_PSW_DTLBE];
  2240
+		    lm32_csr_psw_reg[`LM32_CSR_PSW_DTLBE] <= `FALSE;
2235 2241
 		end
2236 2242
 `endif
2237 2243
 		else if (stall_x == `FALSE)
2238 2244
 		begin
2239 2245
 		    if (eret_q_x == `TRUE)
2240  
-			// Restore ITLB enable
  2246
+		    begin
  2247
+			// Restore ITLB and DTLB enable
2241 2248
 			lm32_csr_psw_reg[`LM32_CSR_PSW_ITLBE] <= lm32_csr_psw_reg[`LM32_CSR_PSW_EITLBE];
  2249
+			lm32_csr_psw_reg[`LM32_CSR_PSW_DTLBE] <= lm32_csr_psw_reg[`LM32_CSR_PSW_EDTLBE];
  2250
+		    end
2242 2251
 `ifdef CFG_DEBUG_ENABLED
2243 2252
 		    else if (bret_q_x == `TRUE)
2244  
-			// Restore ITLB enable
  2253
+		    begin
  2254
+			// Restore ITLB and DTLB enable
2245 2255
 			lm32_csr_psw_reg[`LM32_CSR_PSW_ITLBE] <= lm32_csr_psw_reg[`LM32_CSR_PSW_BITLBE];
  2256
+			lm32_csr_psw_reg[`LM32_CSR_PSW_DTLBE] <= lm32_csr_psw_reg[`LM32_CSR_PSW_BDTLBE];
  2257
+		    end
2246 2258
 `endif
2247 2259
 		    else if (csr_write_enable_q_x == `TRUE)
2248 2260
 		    begin
6  software/bios/dtlb_exception_handling_tests.c
@@ -51,7 +51,7 @@ void dtlb_exception_handling_tests() {
51 51
 	printf("\n<= Reading %d from virtual address 0x%08X\n\n", data, addr);
52 52
 
53 53
 	printf("=> Invalidating the mapping of virtual address 0x%08X in the TLB\n", addr);
54  
-	mmu_dtlb_invalidate_line(addr);
  54
+	mmu_dtlb_invalidate_line(get_pfn(addr));
55 55
 
56 56
 	data = 43;
57 57
 	printf("=> Writing %d to physical address 0x%08X\n", data, addr);
@@ -67,7 +67,7 @@ void dtlb_exception_handling_tests() {
67 67
 	check_for_error(ret);
68 68
 
69 69
 	printf("=> Invalidating the mapping of virtual address 0x%08X in the TLB\n", addr);
70  
-	mmu_dtlb_invalidate_line(addr); // AND invalidate the mapping
  70
+	mmu_dtlb_invalidate_line(get_pfn(addr)); // AND invalidate the mapping
71 71
 
72 72
 	data = 44;
73 73
 	printf("=> Writting %d to physical address 0x%08X\n", data, addr+0x1000);
@@ -77,5 +77,7 @@ void dtlb_exception_handling_tests() {
77 77
 	printf("=> Activating the MMU and reading form virtual address 0x%08X\n", addr);
78 78
 	data = read_word_with_mmu_enabled(addr);
79 79
 	printf("\n<= Reading %d from virtual address 0x%08X\n\n", data, addr);
  80
+	data = *(unsigned int *)addr;
  81
+	printf("\n<= Reading %d from physical address 0x%08X\n\n", data, addr);
80 82
 
81 83
 }

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