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base fork: fallen/milkymist-mmu
base: 5b90cf4bb2
...
head fork: fallen/milkymist-mmu
compare: 5cf64084e3
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  • 16 commits
  • 9 files changed
  • 0 commit comments
  • 1 contributor
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13 boards/milkymist-one/rtl/lm32_include.v
@@ -97,6 +97,9 @@
`define CFG_EXTERNAL_BREAK_ENABLED
`define CFG_GDBSTUB_ENABLED
+// Enable MMU
+`define CFG_MMU_ENABLED
+
//
// End of common configuration options
//
@@ -240,6 +243,10 @@
`define LM32_ADDRESS_LSBS_WIDTH 2
// Width and range of a CSR index
+`ifdef CFG_MMU_ENABLED
+`define LM32_CSR_WIDTH 5
+`define LM32_CSR_RNG (`LM32_CSR_WIDTH-1):0
+`else
`ifdef CFG_DEBUG_ENABLED
`define LM32_CSR_WIDTH 5
`define LM32_CSR_RNG (`LM32_CSR_WIDTH-1):0
@@ -252,6 +259,7 @@
`define LM32_CSR_RNG (`LM32_CSR_WIDTH-1):0
`endif
`endif
+`endif
// CSR indices
`define LM32_CSR_IE `LM32_CSR_WIDTH'h0
@@ -280,10 +288,13 @@
`define LM32_CSR_WP1 `LM32_CSR_WIDTH'h19
`define LM32_CSR_WP2 `LM32_CSR_WIDTH'h1a
`define LM32_CSR_WP3 `LM32_CSR_WIDTH'h1b
-`endif
+`endif
+`ifdef CFG_MMU_ENABLED
`define LM32_CSR_TLB_CTRL `LM32_CSR_WIDTH'h1c
`define LM32_CSR_TLB_VADDRESS `LM32_CSR_WIDTH'h1d
`define LM32_CSR_TLB_PADDRESS `LM32_CSR_WIDTH'h1e
+`define LM32_CSR_TLB_DBG `LM32_CSR_WIDTH'h1f
+`endif
// Values for WPC CSR
`define LM32_WPC_C_RNG 1:0
View
18 boards/milkymist-one/rtl/setup.v
@@ -22,17 +22,17 @@
* able to cut down synthesis times.
*/
`define ENABLE_MEMORYCARD
-`define ENABLE_ETHERNET
-`define ENABLE_USB
+//`define ENABLE_ETHERNET
+//`define ENABLE_USB
-`define ENABLE_AC97
-`define ENABLE_PFPU
-`define ENABLE_TMU
+//`define ENABLE_AC97
+//`define ENABLE_PFPU
+//`define ENABLE_TMU
`define ENABLE_FMLMETER
-`define ENABLE_VIDEOIN
-`define ENABLE_MIDI
-`define ENABLE_DMX
-`define ENABLE_IR
+//`define ENABLE_VIDEOIN
+//`define ENABLE_MIDI
+//`define ENABLE_DMX
+//`define ENABLE_IR
`ifndef ENABLE_TMU
`define ENABLE_MEMTEST
View
2  cores/lm32/rtl/lm32_cpu.v
@@ -2130,7 +2130,7 @@ begin
`LM32_CSR_JRX: csr_read_data_x = jrx_csr_read_data;
`endif
`LM32_CSR_CFG2: csr_read_data_x = cfg2;
- `LM32_CSR_TLB_CTRL: csr_read_data_x = load_store_csr_read_data_x;
+ `LM32_CSR_TLB_DBG: csr_read_data_x = load_store_csr_read_data_x;
default: csr_read_data_x = {`LM32_WORD_WIDTH{1'bx}};
endcase
View
25 cores/lm32/rtl/lm32_dcache.v
@@ -141,13 +141,13 @@ parameter page_size = 4096; // System page size
`define LM32_DTLB_INVALID_ADDRESS { vpfn_width{1'b1} }
localparam addr_page_offset_lsb = 0;
-localparam addr_page_offset_msb = addr_page_offset_lsb + clogb2_v1(page_size) - 1;
-localparam addr_dtlb_index_width = clogb2_v1(dtlb_sets);
+localparam addr_page_offset_msb = addr_page_offset_lsb + clogb2(page_size) - 2;
+localparam addr_dtlb_index_width = clogb2(dtlb_sets) - 1;
localparam addr_dtlb_index_lsb = addr_page_offset_msb + 1;
localparam addr_dtlb_index_msb = addr_dtlb_index_lsb + addr_dtlb_index_width - 1;
localparam addr_pfn_lsb = addr_page_offset_msb + 1;
localparam addr_pfn_msb = `LM32_WORD_WIDTH - 1;
-localparam vpfn_width = `LM32_WORD_WIDTH - clogb2_v1(page_size);
+localparam vpfn_width = `LM32_WORD_WIDTH - (clogb2(page_size) - 1);
localparam addr_dtlb_tag_width = vpfn_width - addr_dtlb_index_width;
localparam addr_dtlb_tag_lsb = addr_dtlb_index_msb + 1;
localparam addr_dtlb_tag_msb = addr_dtlb_tag_lsb + addr_dtlb_tag_width - 1;
@@ -212,8 +212,8 @@ reg refilling;
output [`LM32_WORD_RNG] load_data; // Data read from cache
wire [`LM32_WORD_RNG] load_data;
-output [`LM32_WORD_RNG] kernel_mode;
-wire [`LM32_WORD_RNG] kernel_mode;
+output kernel_mode;
+wire kernel_mode;
output dtlb_miss;
@@ -279,7 +279,7 @@ reg [addr_dtlb_index_width-1:0] dtlb_update_set;
reg dtlb_flushing;
reg [addr_dtlb_index_width-1:0] dtlb_flush_set;
reg dtlb_miss;
-reg dtlb_miss_addr;
+reg [`LM32_WORD_RNG] dtlb_miss_addr;
genvar i, j;
@@ -551,8 +551,8 @@ assign dtlb_tag_write_address = (dtlb_flushing == `TRUE)
? dtlb_flush_set
: dtlb_update_vaddr_csr_reg[`LM32_DTLB_IDX_RNG];
-assign dtlb_data_read_port_enable = (stall_x == `FALSE);
-assign dtlb_tag_read_port_enable = (stall_x == `FALSE);
+assign dtlb_data_read_port_enable = (stall_x == `FALSE) || !stall_m;
+assign dtlb_tag_read_port_enable = (stall_x == `FALSE) || !stall_m;
assign dtlb_write_port_enable = dtlb_updating || dtlb_flushing;
assign dtlb_write_tag = (dtlb_flushing == `TRUE)
? `LM32_DTLB_INVALID_TAG
@@ -697,7 +697,7 @@ end
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
- if (write_port_enable)
+ if (write_port_enable && (|way_dmem_we))
begin
latest_store_tlb_lookup <= { dtlb_read_data , address_m[`LM32_PAGE_OFFSET_RNG] };
end
@@ -715,6 +715,7 @@ begin
dtlb_flushing <= 1;
dtlb_flush_set <= {addr_dtlb_index_width{1'b1}};
dtlb_state <= `LM32_TLB_STATE_FLUSH;
+ dtlb_updating <= 0;
end
else
begin
@@ -728,6 +729,8 @@ begin
begin
// FIXME : We need to generate an exception
dtlb_miss_addr <= address_m;
+ dtlb_updating <= 0;
+ $display("ERROR : DTLB MISS on addr 0x%08X", address_m);
end
else if (csr_write_enable && csr_write_data[0])
begin
@@ -740,6 +743,7 @@ begin
dtlb_flushing <= 1;
dtlb_flush_set <= {addr_dtlb_index_width{1'b1}};
dtlb_state <= `LM32_TLB_STATE_FLUSH;
+ dtlb_updating <= 0;
end
`LM32_DTLB_CTRL_UPDATE:
@@ -750,11 +754,13 @@ begin
`LM32_TLB_CTRL_SWITCH_TO_KERNEL_MODE:
begin
kernel_mode_reg <= `LM32_KERNEL_MODE;
+ dtlb_updating <= 0;
end
`LM32_TLB_CTRL_SWITCH_TO_USER_MODE:
begin
kernel_mode_reg <= `LM32_USER_MODE;
+ dtlb_updating <= 0;
end
endcase
@@ -764,6 +770,7 @@ begin
`LM32_TLB_STATE_FLUSH:
begin
+ dtlb_updating <= 0;
if (dtlb_flush_set == {addr_dtlb_index_width{1'b0}})
dtlb_state <= `LM32_TLB_STATE_CHECK;
dtlb_flush_set <= dtlb_flush_set - 1'b1;
View
2  cores/lm32/rtl/lm32_load_store_unit.v
@@ -297,7 +297,7 @@ reg [`LM32_WORD_RNG] wb_data_m; // Data read from Wishbo
reg wb_load_complete; // Indicates when a Wishbone load is complete
wire [`LM32_WORD_RNG] physical_address;
-wire [`LM32_WORD_RNG] kernel_mode;
+wire kernel_mode;
/////////////////////////////////////////////////////
// Functions
View
10 cores/lm32/rtl/lm32_ram.v
@@ -125,4 +125,14 @@ always @(posedge read_clk)
if (enable_read)
ra <= read_address;
+reg [31:0] i;
+
+initial
+begin
+ for (i = 0; i < 2**address_width; i = i + 1)
+ begin
+ mem[i] = {data_width{1'b0}};
+ end
+end
+
endmodule
View
7 software/bios/crt0.S
@@ -110,6 +110,13 @@ macaddress:
.byte 0x00
_crt0:
+ mvi r3, 1
+ mvi r2, 0xdf
+/* give time for DTLB to flush itself */
+loop:
+ nop
+ sub r2, r2, r3
+ bne r2, r0, loop
/* Setup stack and global pointer */
mvhi sp, hi(_fstack)
ori sp, sp, lo(_fstack)
View
14 software/bios/main.c
@@ -699,34 +699,22 @@ int main(int i, char **c)
irq_setmask(0);
irq_enable(1);
uart_init();
-// vga_init(!(rescue || (CSR_GPIO_IN & GPIO_BTN2)));
putsnonl(banner);
crcbios();
brd_init();
-// tmu_init(); /* < for hardware-accelerated scrolling */
-// usb_init();
-// ukb_init();
if(rescue)
printf("I: Booting in rescue mode\n");
-// splash_display();
-// ethreset(); /* < that pesky ethernet PHY needs two resets at times... */
-// print_mac();
boot_sequence();
-// vga_unblank();
-// vga_set_console(1);
uart_force_sync(1);
irq_enable(0);
- puts("this is a test");
- printf("This is another test : %d %p\n", 1, printf);
-
for (k = 0 ; k < 65000 ; ++k)
asm volatile("nop");
- dtlbtest();
+ dtlb_load_test();
while(1) {
if (++k == 0)
View
65 software/bios/mmu_test_gen.c
@@ -8,19 +8,18 @@ static inline void generate_test(int i, int j) {
int k;
puts("asm volatile(");
-// puts("\t\"xor r11, r11, r11\\n\\t\"");
-// puts("\t\"ori r11, r11, 0x11\\n\\t\"");
-// puts("\t\"wcsr tlbctrl, r11\\n\\t\"");
+ puts("\t\"xor r11, r11, r11\\n\\t\"");
+ puts("\t\"ori r11, r11, 0x11\\n\\t\"");
+ puts("\t\"wcsr tlbctrl, r11\\n\\t\"");
puts("\t\"xor r0, r0, r0\\n\\t\"");
puts("\t\"xor r0, r0, r0\\n\\t\"");
puts("\t\"xor r0, r0, r0\\n\\t\"");
for (k = 0 ; k < 6 ; k++) {
if (k == i) {
- printf("\t\"sw (%3+0), %2\\n\\t\"");
- printf("\t\"rcsr %1, TLBCTRL");
+ printf("\t\"sw (%2+0), %1");
}
else if(k == j) {
- printf("\t\"lw %0, (%3+0)");
+ printf("\t\"lw %0, (%2+0)");
}
else
printf("\t\"xor r0, r0, r0");
@@ -29,53 +28,31 @@ static inline void generate_test(int i, int j) {
puts("\"");
}
- puts(": \"=&r\"(value_verif), \"=&r\"(tlb_lookup) : \"r\"(value), \"r\"(addr) :\"r11\"\n);");
+ puts(": \"=&r\"(value_verif) : \"r\"(value), \"r\"(addr) :\"r11\"\n);");
}
int main(void) {
puts("#include <hal/mmu.h>\n");
+ puts("#include <base/console.h>\n");
+ puts("#include <stdio.h>\n");
puts("void dtlb_load_test(void) {\n");
puts(
"char a, b, c, d;\n"
- "// map vaddr 0x4400 1000 to paddr 0x4400 0000\n"
- "register unsigned int value, addr, value_verif, stack, tlb_lookup;\n"
+ "// map vaddr 0x4400 2000 to paddr 0x4400 1000\n"
+ "register unsigned int value, addr, value_verif, stack, data;\n"
"int success, failure;\n"
- "mmu_dtlb_map(0x44001000, 0x44000000);\n" // for the test
- "mmu_dtlb_map(0x873000, 0x873000);\n"
- "mmu_dtlb_map(0x872000, 0x872000);\n"
- "mmu_dtlb_map(0x871000, 0x871000);\n"
- "mmu_dtlb_map(0x870000, 0x870000);\n"
- "mmu_dtlb_map(0x86F000, 0x86F000);\n" // for dtlb_load_test and constants
- "mmu_dtlb_map(0x86E000, 0x86E000);\n" // for constants
- "mmu_dtlb_map(0x86D000, 0x86D000);\n"
- "mmu_dtlb_map(0x86C000, 0x86C000);\n"
- "mmu_dtlb_map(0x86B000, 0x86B000);\n"
- "mmu_dtlb_map(0x86A000, 0x86A000);\n"
- "mmu_dtlb_map(0x869000, 0x869000);\n"
- "mmu_dtlb_map(0x868000, 0x868000);\n"
- "mmu_dtlb_map(0x867000, 0x867000);\n" // for isr and uart_isr
- "mmu_dtlb_map(0x866000, 0x866000);\n" // for printf
- //"mmu_dtlb_map(0x866000, 0x866000);\n" // for the fun
- "mmu_dtlb_map(0x865000, 0x865000);\n" // for puts
- "mmu_dtlb_map(0x864000, 0x864000);\n" // for dtlb_load_test
- "mmu_dtlb_map(0x863000, 0x863000);\n"
- "mmu_dtlb_map(0x862000, 0x862000);\n"
- "mmu_dtlb_map(0x861000, 0x861000);\n"
- "mmu_dtlb_map(0x860000, 0x860000);\n"
- "mmu_dtlb_map(0xe0000000, 0xe0000000);\n"
+ "unsigned int count;\n"
"asm volatile(\"mv %0, sp\" : \"=r\"(stack) :: );\n"
- "mmu_dtlb_map(stack, stack);\n"
- "mmu_dtlb_map(stack+0x1000, stack+0x1000);\n"
- "mmu_dtlb_map(stack-0x1000, stack-0x1000);\n"
+ "mmu_dtlb_map(0x44002000, 0x44001000);\n"
"printf(\"stack == 0x%08X\\n\", stack);"
"a = 0;\n"
"b = 1;\n"
"c = 2;\n"
"d = 3;\n"
- "addr = 0x44001000;\n"
+ "addr = 0x44002000;\n"
"success = 0;\n"
"failure = 0;"
);
@@ -91,16 +68,19 @@ int main(void) {
"value |= c << 8;\n"
"value |= d;\n"
"addr += 4;\n"
-
- //"enable_dtlb();"
-
);
generate_test(i, j);
puts("disable_dtlb();");
- puts("printf(\"tlb_lookup = 0x%08X\\n\", tlb_lookup);");
+ puts("printf(\"addr == 0x%08X\\n\", addr);");
+ puts("printf(\"[MMU OFF] *(0x%08X) == 0x%08X\\n\", addr, *(unsigned int *)addr);");
+ puts("enable_dtlb();");
+ puts("asm volatile(\"lw %0, (%1+0)\" : \"=&r\"(data) : \"r\"(addr) : );");
+ puts("disable_dtlb();");
+ puts("printf(\"[MMU ON] *(0x%08X) == 0x%08X\\n\", addr, data);");
+ puts("printf(\"[MMU OFF] *(0x%08X) == 0x%08X\\n\", addr-0x1000, *(unsigned int *)(addr - 0x1000));");
printf("printf(\"Test n° %02d : \");\n", test_num);
puts( "if (value == value_verif) {\n"
"\tputs(\"PASS\");\n"
@@ -117,6 +97,11 @@ int main(void) {
"d++;\n\n"
);
test_num++;
+
+ puts("\
+ for (count = 0 ; count <= 10000000 ; ++count) {\n\
+ \t asm volatile(\"nop\");\n\
+ }");
}
}

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