Browse files

Fixed #5 : Matt has provided updated RIFFA framework which now suppor…

…ts ML605 board.
  • Loading branch information...
1 parent d488e35 commit 5159df7ff1362a1f5de3732a69e5e6a5488b836a @farhanrahman committed Sep 20, 2012
Showing with 2,479,384 additions and 7,092 deletions.
  1. +0 −3 flash/RiffaInt/RiffaInt/xilinx.sys
  2. +0 −3 flash/RiffaInt/xilinx.sys
  3. BIN flash/SysAceFiles/111/RiffaInt/RiffaInt/rev0/rev0.ace
  4. +0 −3 flash/SysAceFiles/111/RiffaInt/RiffaInt/xilinx.sys
  5. +0 −3 flash/SysAceFiles/111/RiffaInt/xilinx.sys
  6. BIN flash/SysAceFiles/1688/RiffaInt/RiffaInt/rev0/rev0.ace
  7. +0 −3 flash/SysAceFiles/1688/RiffaInt/RiffaInt/xilinx.sys
  8. +0 −3 flash/SysAceFiles/1688/RiffaInt/xilinx.sys
  9. BIN flash/SysAceFiles/321616/RiffaInt/RiffaInt/rev0/rev0.ace
  10. +0 −3 flash/SysAceFiles/321616/RiffaInt/RiffaInt/xilinx.sys
  11. +0 −3 flash/SysAceFiles/321616/RiffaInt/xilinx.sys
  12. BIN flash/SysAceFiles/481616/RiffaInt/RiffaInt/rev0/rev0.ace
  13. BIN flash/SysAceFiles/811/RiffaInt/RiffaInt/rev0/rev0.ace
  14. 0 flash/{ → ml505}/RiffaInt/RiffaInt/rev0/rev0.ace
  15. 0 flash/{SysAceFiles/811 → ml505/RiffaInt}/RiffaInt/xilinx.sys
  16. 0 flash/{SysAceFiles/811/RiffaInt → ml505}/RiffaInt/xilinx.sys
  17. BIN flash/ml605/RiffaInt/RiffaInt/rev0/rev0.ace
  18. 0 flash/{SysAceFiles/481616 → ml605/RiffaInt}/RiffaInt/xilinx.sys
  19. 0 flash/{SysAceFiles/481616/RiffaInt → ml605}/RiffaInt/xilinx.sys
  20. +2 −0 project/base_systems/ml505/hdl/system_central_notifier_0_wrapper.vhd
  21. BIN project/base_systems/ml505/implementation/system.bit
  22. +51 −57 project/base_systems/ml505/implementation/system_summary.html
  23. +1 −1 project/base_systems/ml505/implementation/system_summary.xml
  24. +6,960 −6,960 project/base_systems/ml505/implementation/system_usage.xml
  25. +3 −3 project/base_systems/ml505/pcores/riffa_v1_00_a/sw/linux/testapp/main.c
  26. +75 −0 project/base_systems/ml605/data/system.ucf
  27. +1,345 −0 ...se_systems/ml605/hdl/elaborate/bram_block_0_elaborate_v1_00_a/hdl/vhdl/bram_block_0_elaborate.vhd
  28. +1,345 −0 ...se_systems/ml605/hdl/elaborate/bram_block_1_elaborate_v1_00_a/hdl/vhdl/bram_block_1_elaborate.vhd
  29. +1,258 −0 project/base_systems/ml605/hdl/elaborate/clock_generator_0_v4_03_a/hdl/vhdl/clock_generator.vhd
  30. +2,402 −0 project/base_systems/ml605/hdl/system.vhd
  31. +94 −0 project/base_systems/ml605/hdl/system_bram_block_0_wrapper.vhd
  32. +94 −0 project/base_systems/ml605/hdl/system_bram_block_1_wrapper.vhd
  33. +1,390 −0 project/base_systems/ml605/hdl/system_central_notifier_0_wrapper.vhd
  34. +126 −0 project/base_systems/ml605/hdl/system_clock_generator_0_wrapper.vhd
  35. +363 −0 project/base_systems/ml605/hdl/system_mb_plb_wrapper.vhd
  36. +77 −0 project/base_systems/ml605/hdl/system_pcie_diff_clk_0_wrapper.vhd
  37. +420 −0 project/base_systems/ml605/hdl/system_plbv46_pcie_0_wrapper.vhd
  38. +122 −0 project/base_systems/ml605/hdl/system_proc_sys_reset_0_wrapper.vhd
  39. +178 −0 project/base_systems/ml605/hdl/system_riffa_0_wrapper.vhd
  40. +170 −0 project/base_systems/ml605/hdl/system_simpbus_mst_plbv46_adapter_0_wrapper.vhd
  41. +212 −0 project/base_systems/ml605/hdl/system_simpbus_slv_plbv46_adapter_0_wrapper.vhd
  42. +62 −0 project/base_systems/ml605/hdl/system_stub.vhd
  43. +209 −0 project/base_systems/ml605/hdl/system_xps_bram_if_cntlr_0_wrapper.vhd
  44. +209 −0 project/base_systems/ml605/hdl/system_xps_bram_if_cntlr_1_wrapper.vhd
  45. +297 −0 project/base_systems/ml605/hdl/system_xps_central_dma_0_wrapper.vhd
  46. BIN project/base_systems/ml605/implementation/system.bit
  47. +546 −0 project/base_systems/ml605/implementation/system_summary.html
  48. +10 −0 project/base_systems/ml605/implementation/system_summary.xml
  49. +9,420 −0 project/base_systems/ml605/implementation/system_usage.xml
  50. +82 −0 project/base_systems/ml605/pcores/riffa_v1_00_a/data/riffa_v2_1_0.mpd
  51. +71 −0 project/base_systems/ml605/pcores/riffa_v1_00_a/data/riffa_v2_1_0.pao
  52. +128 −0 project/base_systems/ml605/pcores/riffa_v1_00_a/hdl/verilog/riffa_example_impl.v
  53. +224 −0 project/base_systems/ml605/pcores/riffa_v1_00_a/hdl/vhdl/dma_handler.vhd
  54. +93 −0 project/base_systems/ml605/pcores/riffa_v1_00_a/hdl/vhdl/doorbell_reset.vhd
  55. +308 −0 project/base_systems/ml605/pcores/riffa_v1_00_a/hdl/vhdl/riffa.vhd
  56. +647 −0 project/base_systems/ml605/pcores/riffa_v1_00_a/hdl/vhdl/riffa_interface.vhd
  57. +185 −0 project/base_systems/ml605/pcores/riffa_v1_00_a/hdl/vhdl/test_core.vhd
  58. +363 −0 project/base_systems/ml605/pcores/riffa_v1_00_a/hdl/vhdl/top_connector.vhd
  59. +28 −0 project/base_systems/ml605/pcores/riffa_v1_00_a/sw/linux/testapp/Makefile
  60. +2 −0 project/base_systems/ml605/pcores/riffa_v1_00_a/sw/linux/testapp/data.txt
  61. +544 −0 project/base_systems/ml605/pcores/riffa_v1_00_a/sw/linux/testapp/fpga_comm.c
  62. +397 −0 project/base_systems/ml605/pcores/riffa_v1_00_a/sw/linux/testapp/fpga_comm.h
  63. +8,066 −0 project/base_systems/ml605/pcores/riffa_v1_00_a/sw/linux/testapp/logs/log0/log.txt
  64. +806,600 −0 project/base_systems/ml605/pcores/riffa_v1_00_a/sw/linux/testapp/logs/log1/log.txt
  65. +1,632,500 −0 project/base_systems/ml605/pcores/riffa_v1_00_a/sw/linux/testapp/logs/log2/log.txt
  66. +201 −0 project/base_systems/ml605/pcores/riffa_v1_00_a/sw/linux/testapp/main.c
  67. BIN project/base_systems/ml605/pcores/riffa_v1_00_a/sw/linux/testapp/riffaexample
  68. +12 −0 project/base_systems/ml605/pcores/riffa_v1_00_a/sw/linux/testapp/test.py
  69. +23 −0 project/base_systems/ml605/pcores/riffa_v1_00_a/sw/linux/testapp/throughput_test.py
  70. BIN project/base_systems/ml605/ready_to_download_via_jtag.bit
  71. +213 −0 project/base_systems/ml605/system.mhs
  72. +26 −0 project/base_systems/ml605/system.xmp
  73. +1 −1 riffa/pcores/central_notifier_v2_00_a/data/central_notifier_v2_1_0.bbd
  74. +1 −0 riffa/pcores/central_notifier_v2_00_a/data/central_notifier_v2_1_0.mpd
  75. +6 −0 riffa/pcores/central_notifier_v2_00_a/data/central_notifier_v2_1_0.pao
  76. +3 −2 riffa/pcores/central_notifier_v2_00_a/hdl/verilog/central_notifier_impl.v
  77. +29 −11 riffa/pcores/central_notifier_v2_00_a/hdl/verilog/dma_queue.v
  78. +474 −0 riffa/pcores/central_notifier_v2_00_a/hdl/verilog/fifo_ramb_32w512d_v6.v
  79. +472 −0 riffa/pcores/central_notifier_v2_00_a/hdl/verilog/fifo_ramd_36w32d_v6.v
  80. +177 −0 riffa/pcores/central_notifier_v2_00_a/hdl/verilog/ramb_sp_32w256d_v6.v
  81. +62 −32 riffa/pcores/central_notifier_v2_00_a/hdl/verilog/reg_handler.v
  82. +4 −0 riffa/pcores/central_notifier_v2_00_a/hdl/vhdl/central_notifier.vhd
  83. +1 −1 src/riffa.vhd
View
3 flash/RiffaInt/RiffaInt/xilinx.sys
@@ -1,3 +0,0 @@
-#Automatically generated. PLEASE DO NOT MODIFY.
-dir = RiffaInt;
-cfgaddr0 = rev0;
View
3 flash/RiffaInt/xilinx.sys
@@ -1,3 +0,0 @@
-#Automatically generated. PLEASE DO NOT MODIFY.
-dir = RiffaInt;
-cfgaddr0 = rev0;
View
BIN flash/SysAceFiles/111/RiffaInt/RiffaInt/rev0/rev0.ace
Binary file not shown.
View
3 flash/SysAceFiles/111/RiffaInt/RiffaInt/xilinx.sys
@@ -1,3 +0,0 @@
-#Automatically generated. PLEASE DO NOT MODIFY.
-dir = RiffaInt;
-cfgaddr0 = rev0;
View
3 flash/SysAceFiles/111/RiffaInt/xilinx.sys
@@ -1,3 +0,0 @@
-#Automatically generated. PLEASE DO NOT MODIFY.
-dir = RiffaInt;
-cfgaddr0 = rev0;
View
BIN flash/SysAceFiles/1688/RiffaInt/RiffaInt/rev0/rev0.ace
Binary file not shown.
View
3 flash/SysAceFiles/1688/RiffaInt/RiffaInt/xilinx.sys
@@ -1,3 +0,0 @@
-#Automatically generated. PLEASE DO NOT MODIFY.
-dir = RiffaInt;
-cfgaddr0 = rev0;
View
3 flash/SysAceFiles/1688/RiffaInt/xilinx.sys
@@ -1,3 +0,0 @@
-#Automatically generated. PLEASE DO NOT MODIFY.
-dir = RiffaInt;
-cfgaddr0 = rev0;
View
BIN flash/SysAceFiles/321616/RiffaInt/RiffaInt/rev0/rev0.ace
Binary file not shown.
View
3 flash/SysAceFiles/321616/RiffaInt/RiffaInt/xilinx.sys
@@ -1,3 +0,0 @@
-#Automatically generated. PLEASE DO NOT MODIFY.
-dir = RiffaInt;
-cfgaddr0 = rev0;
View
3 flash/SysAceFiles/321616/RiffaInt/xilinx.sys
@@ -1,3 +0,0 @@
-#Automatically generated. PLEASE DO NOT MODIFY.
-dir = RiffaInt;
-cfgaddr0 = rev0;
View
BIN flash/SysAceFiles/481616/RiffaInt/RiffaInt/rev0/rev0.ace
Binary file not shown.
View
BIN flash/SysAceFiles/811/RiffaInt/RiffaInt/rev0/rev0.ace
Binary file not shown.
View
0 flash/RiffaInt/RiffaInt/rev0/rev0.ace → flash/ml505/RiffaInt/RiffaInt/rev0/rev0.ace
File renamed without changes.
View
0 flash/SysAceFiles/811/RiffaInt/xilinx.sys → flash/ml505/RiffaInt/RiffaInt/xilinx.sys
File renamed without changes.
View
0 ...AceFiles/811/RiffaInt/RiffaInt/xilinx.sys → flash/ml505/RiffaInt/xilinx.sys
File renamed without changes.
View
BIN flash/ml605/RiffaInt/RiffaInt/rev0/rev0.ace
Binary file not shown.
View
0 flash/SysAceFiles/481616/RiffaInt/xilinx.sys → flash/ml605/RiffaInt/RiffaInt/xilinx.sys
File renamed without changes.
View
0 ...Files/481616/RiffaInt/RiffaInt/xilinx.sys → flash/ml605/RiffaInt/xilinx.sys
File renamed without changes.
View
2 project/base_systems/ml505/hdl/system_central_notifier_0_wrapper.vhd
@@ -465,6 +465,7 @@ architecture STRUCTURE of system_central_notifier_0_wrapper is
component central_notifier is
generic (
+ C_ARCH : string;
C_SIMPBUS_AWIDTH : INTEGER;
C_SIMPBUS_DWIDTH : INTEGER;
C_NUM_CHANNELS : INTEGER;
@@ -927,6 +928,7 @@ begin
central_notifier_0 : central_notifier
generic map (
+ C_ARCH => "V5",
C_SIMPBUS_AWIDTH => 32,
C_SIMPBUS_DWIDTH => 32,
C_NUM_CHANNELS => 1,
View
BIN project/base_systems/ml505/implementation/system.bit
Binary file not shown.
View
108 project/base_systems/ml505/implementation/system_summary.html
@@ -2,7 +2,7 @@
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
-<TD ALIGN=CENTER COLSPAN='4'><B>Project Status (09/04/2012 - 18:11:27)</B></TD></TR>
+<TD ALIGN=CENTER COLSPAN='4'><B>Project Status (09/20/2012 - 12:06:23)</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>system.xmp</TD>
@@ -19,7 +19,7 @@
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>EDK 14.1</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
-<TD ALIGN=LEFT><A HREF_DISABLED='/home/fr909/git/riffa/project/base_systems/ml505/implementation/_xmsgs/*.xmsgs?&DataKey=Warning'>257 Warnings (101 new)</A></TD>
+<TD ALIGN=LEFT><A HREF_DISABLED='/home/fr909/git/riffa/project/base_systems/ml505/implementation/_xmsgs/*.xmsgs?&DataKey=Warning'>293 Warnings (38 new)</A></TD>
</TR>
</TABLE>
@@ -29,23 +29,23 @@
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='5'><B>XPS Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=EDKReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
-<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/fr909/git/riffa/project/base_systems/ml505/platgen.log'>Platgen Log File</A></TD><TD>Tue Sep 4 17:59:12 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='/home/fr909/git/riffa/project/base_systems/ml505/__xps/ise/_xmsgs/platgen.xmsgs?&DataKey=Info'>24 Infos (5 new)</A></TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/fr909/git/riffa/project/base_systems/ml505/platgen.log'>Platgen Log File</A></TD><TD>Thu Sep 20 11:58:26 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='/home/fr909/git/riffa/project/base_systems/ml505/__xps/ise/_xmsgs/platgen.xmsgs?&DataKey=Info'>24 Infos (1 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/fr909/git/riffa/project/base_systems/ml505/simgen.log'>Simgen Log File</A></TD><TD>Fri Aug 10 16:21:46 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='/home/fr909/git/riffa/project/base_systems/ml505/__xps/ise/_xmsgs/simgen.xmsgs?&DataKey=Warning'>32 Warnings (32 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='/home/fr909/git/riffa/project/base_systems/ml505/__xps/ise/_xmsgs/simgen.xmsgs?&DataKey=Info'>22 Infos (22 new)</A></TD></TR>
<TR ALIGN=LEFT><TD>BitInit Log File</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
-<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/fr909/git/riffa/project/base_systems/ml505/system.log'>System Log File</A></TD><TD>Tue Sep 4 18:11:25 2012</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/fr909/git/riffa/project/base_systems/ml505/system.log'>System Log File</A></TD><TD>Thu Sep 20 12:06:17 2012</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>XPS Synthesis Summary (estimated values)</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=EDKSynthesisSumary"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report</B></TD><TD><B>Generated</B></TD><TD><B>Flip Flops Used</B></TD><TD><B>LUTs Used</B></TD><TD><B>BRAMS Used</B></TD><TD COLSPAN='2'><B>Errors</B></TD></TR>
-<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/fr909/git/riffa/project/base_systems/ml505/synthesis/system_xst.srp'>system</A></TD><TD>Tue Sep 4 17:59:57 2012</TD><TD ALIGN=RIGHT>9785</TD><TD ALIGN=RIGHT>13295</TD><TD ALIGN=RIGHT>47</TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
-<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/fr909/git/riffa/project/base_systems/ml505/synthesis/system_xps_bram_if_cntlr_1_wrapper_xst.srp'>system_xps_bram_if_cntlr_1_wrapper</A></TD><TD>Tue Sep 4 17:59:04 2012</TD><TD ALIGN=RIGHT>156</TD><TD ALIGN=RIGHT>160</TD><TD>&nbsp;</TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/fr909/git/riffa/project/base_systems/ml505/synthesis/system_xst.srp'>system</A></TD><TD>Thu Sep 20 11:59:06 2012</TD><TD ALIGN=RIGHT>9704</TD><TD ALIGN=RIGHT>13292</TD><TD ALIGN=RIGHT>47</TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/fr909/git/riffa/project/base_systems/ml505/synthesis/system_xps_bram_if_cntlr_1_wrapper_xst.srp'>system_xps_bram_if_cntlr_1_wrapper</A></TD><TD>Thu Sep 20 11:58:18 2012</TD><TD ALIGN=RIGHT>156</TD><TD ALIGN=RIGHT>160</TD><TD>&nbsp;</TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/fr909/git/riffa/project/base_systems/ml505/synthesis/system_riffa_0_wrapper_xst.srp'>system_riffa_0_wrapper</A></TD><TD>Thu Sep 20 11:58:10 2012</TD><TD ALIGN=RIGHT>415</TD><TD ALIGN=RIGHT>825</TD><TD>&nbsp;</TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/fr909/git/riffa/project/base_systems/ml505/synthesis/system_simpbus_mst_plbv46_adapter_0_wrapper_xst.srp'>system_simpbus_mst_plbv46_adapter_0_wrapper</A></TD><TD>Thu Sep 20 11:57:59 2012</TD><TD ALIGN=RIGHT>159</TD><TD ALIGN=RIGHT>95</TD><TD>&nbsp;</TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/fr909/git/riffa/project/base_systems/ml505/synthesis/system_simpbus_slv_plbv46_adapter_0_wrapper_xst.srp'>system_simpbus_slv_plbv46_adapter_0_wrapper</A></TD><TD>Thu Sep 20 11:57:52 2012</TD><TD ALIGN=RIGHT>181</TD><TD ALIGN=RIGHT>52</TD><TD>&nbsp;</TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/fr909/git/riffa/project/base_systems/ml505/synthesis/system_central_notifier_0_wrapper_xst.srp'>system_central_notifier_0_wrapper</A></TD><TD>Thu Sep 20 11:57:44 2012</TD><TD ALIGN=RIGHT>416</TD><TD ALIGN=RIGHT>2252</TD><TD ALIGN=RIGHT>1</TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/fr909/git/riffa/project/base_systems/ml505/synthesis/system_clock_generator_0_wrapper_xst.srp'>system_clock_generator_0_wrapper</A></TD><TD>Thu Sep 20 11:57:21 2012</TD><TD>&nbsp;</TD><TD ALIGN=RIGHT>1</TD><TD>&nbsp;</TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/fr909/git/riffa/project/base_systems/ml505/synthesis/system_bram_block_1_wrapper_xst.srp'>system_bram_block_1_wrapper</A></TD><TD>Tue Sep 4 17:58:57 2012</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD ALIGN=RIGHT>16</TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/fr909/git/riffa/project/base_systems/ml505/synthesis/system_riffa_example_0_wrapper_xst.srp'>system_riffa_example_0_wrapper</A></TD><TD>Tue Sep 4 17:58:46 2012</TD><TD ALIGN=RIGHT>76</TD><TD ALIGN=RIGHT>78</TD><TD>&nbsp;</TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
-<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/fr909/git/riffa/project/base_systems/ml505/synthesis/system_riffa_0_wrapper_xst.srp'>system_riffa_0_wrapper</A></TD><TD>Tue Sep 4 17:58:39 2012</TD><TD ALIGN=RIGHT>412</TD><TD ALIGN=RIGHT>723</TD><TD>&nbsp;</TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
-<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/fr909/git/riffa/project/base_systems/ml505/synthesis/system_simpbus_mst_plbv46_adapter_0_wrapper_xst.srp'>system_simpbus_mst_plbv46_adapter_0_wrapper</A></TD><TD>Tue Sep 4 17:58:29 2012</TD><TD ALIGN=RIGHT>159</TD><TD ALIGN=RIGHT>95</TD><TD>&nbsp;</TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
-<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/fr909/git/riffa/project/base_systems/ml505/synthesis/system_simpbus_slv_plbv46_adapter_0_wrapper_xst.srp'>system_simpbus_slv_plbv46_adapter_0_wrapper</A></TD><TD>Tue Sep 4 17:58:22 2012</TD><TD ALIGN=RIGHT>181</TD><TD ALIGN=RIGHT>52</TD><TD>&nbsp;</TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
-<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/fr909/git/riffa/project/base_systems/ml505/synthesis/system_central_notifier_0_wrapper_xst.srp'>system_central_notifier_0_wrapper</A></TD><TD>Tue Sep 4 17:58:14 2012</TD><TD ALIGN=RIGHT>416</TD><TD ALIGN=RIGHT>2277</TD><TD ALIGN=RIGHT>1</TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
-<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/fr909/git/riffa/project/base_systems/ml505/synthesis/system_clock_generator_0_wrapper_xst.srp'>system_clock_generator_0_wrapper</A></TD><TD>Tue Sep 4 17:57:51 2012</TD><TD ALIGN=RIGHT>8</TD><TD ALIGN=RIGHT>3</TD><TD>&nbsp;</TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/fr909/git/riffa/project/base_systems/ml505/synthesis/system_xps_central_dma_0_wrapper_xst.srp'>system_xps_central_dma_0_wrapper</A></TD><TD>Tue Sep 4 17:57:45 2012</TD><TD ALIGN=RIGHT>562</TD><TD ALIGN=RIGHT>713</TD><TD>&nbsp;</TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/fr909/git/riffa/project/base_systems/ml505/synthesis/system_mb_plb_wrapper_xst.srp'>system_mb_plb_wrapper</A></TD><TD>Tue Sep 4 17:57:22 2012</TD><TD ALIGN=RIGHT>163</TD><TD ALIGN=RIGHT>445</TD><TD>&nbsp;</TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/fr909/git/riffa/project/base_systems/ml505/synthesis/system_xps_bram_if_cntlr_0_wrapper_xst.srp'>system_xps_bram_if_cntlr_0_wrapper</A></TD><TD>Fri Aug 31 10:45:27 2012</TD><TD ALIGN=RIGHT>156</TD><TD ALIGN=RIGHT>160</TD><TD>&nbsp;</TD><TD ALIGN=RIGHT COLSPAN='2'>0</TD></TR>
@@ -60,13 +60,13 @@
<TD ALIGN=LEFT><B>Slice Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD><B>Utilization</B></TD><TD COLSPAN='2'><B>Note(s)</B></TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Registers</TD>
-<TD ALIGN=RIGHT>9,490</TD>
+<TD ALIGN=RIGHT>9,408</TD>
<TD ALIGN=RIGHT>69,120</TD>
<TD ALIGN=RIGHT>13%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Flip Flops</TD>
-<TD ALIGN=RIGHT>9,489</TD>
+<TD ALIGN=RIGHT>9,407</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
@@ -78,19 +78,19 @@
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice LUTs</TD>
-<TD ALIGN=RIGHT>11,824</TD>
+<TD ALIGN=RIGHT>11,868</TD>
<TD ALIGN=RIGHT>69,120</TD>
<TD ALIGN=RIGHT>17%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as logic</TD>
-<TD ALIGN=RIGHT>11,446</TD>
+<TD ALIGN=RIGHT>11,492</TD>
<TD ALIGN=RIGHT>69,120</TD>
<TD ALIGN=RIGHT>16%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O6 output only</TD>
-<TD ALIGN=RIGHT>10,231</TD>
+<TD ALIGN=RIGHT>10,279</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
@@ -102,7 +102,7 @@
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O5 and O6</TD>
-<TD ALIGN=RIGHT>947</TD>
+<TD ALIGN=RIGHT>945</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
@@ -144,73 +144,73 @@
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as exclusive route-thru</TD>
-<TD ALIGN=RIGHT>41</TD>
+<TD ALIGN=RIGHT>39</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of route-thrus</TD>
-<TD ALIGN=RIGHT>385</TD>
+<TD ALIGN=RIGHT>331</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number using O6 output only</TD>
-<TD ALIGN=RIGHT>305</TD>
+<TD ALIGN=RIGHT>304</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number using O5 output only</TD>
-<TD ALIGN=RIGHT>77</TD>
+<TD ALIGN=RIGHT>25</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number using O5 and O6</TD>
-<TD ALIGN=RIGHT>3</TD>
+<TD ALIGN=RIGHT>2</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of occupied Slices</TD>
-<TD ALIGN=RIGHT>5,212</TD>
+<TD ALIGN=RIGHT>5,601</TD>
<TD ALIGN=RIGHT>17,280</TD>
-<TD ALIGN=RIGHT>30%</TD>
+<TD ALIGN=RIGHT>32%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of LUT Flip Flop pairs used</TD>
-<TD ALIGN=RIGHT>14,696</TD>
+<TD ALIGN=RIGHT>14,938</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number with an unused Flip Flop</TD>
-<TD ALIGN=RIGHT>5,206</TD>
-<TD ALIGN=RIGHT>14,696</TD>
-<TD ALIGN=RIGHT>35%</TD>
+<TD ALIGN=RIGHT>5,530</TD>
+<TD ALIGN=RIGHT>14,938</TD>
+<TD ALIGN=RIGHT>37%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number with an unused LUT</TD>
-<TD ALIGN=RIGHT>2,872</TD>
-<TD ALIGN=RIGHT>14,696</TD>
-<TD ALIGN=RIGHT>19%</TD>
+<TD ALIGN=RIGHT>3,070</TD>
+<TD ALIGN=RIGHT>14,938</TD>
+<TD ALIGN=RIGHT>20%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of fully used LUT-FF pairs</TD>
-<TD ALIGN=RIGHT>6,618</TD>
-<TD ALIGN=RIGHT>14,696</TD>
-<TD ALIGN=RIGHT>45%</TD>
+<TD ALIGN=RIGHT>6,338</TD>
+<TD ALIGN=RIGHT>14,938</TD>
+<TD ALIGN=RIGHT>42%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of unique control sets</TD>
-<TD ALIGN=RIGHT>956</TD>
+<TD ALIGN=RIGHT>951</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of slice register sites lost<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;to control set restrictions</TD>
-<TD ALIGN=RIGHT>2,185</TD>
+<TD ALIGN=RIGHT>2,175</TD>
<TD ALIGN=RIGHT>69,120</TD>
<TD ALIGN=RIGHT>3%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
@@ -258,13 +258,13 @@
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BlockRAM/FIFO</TD>
-<TD ALIGN=RIGHT>49</TD>
+<TD ALIGN=RIGHT>48</TD>
<TD ALIGN=RIGHT>148</TD>
-<TD ALIGN=RIGHT>33%</TD>
+<TD ALIGN=RIGHT>32%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number using BlockRAM only</TD>
-<TD ALIGN=RIGHT>49</TD>
+<TD ALIGN=RIGHT>48</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
@@ -288,13 +288,13 @@
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFG/BUFGCTRLs</TD>
-<TD ALIGN=RIGHT>7</TD>
+<TD ALIGN=RIGHT>4</TD>
<TD ALIGN=RIGHT>32</TD>
-<TD ALIGN=RIGHT>21%</TD>
+<TD ALIGN=RIGHT>12%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as BUFGs</TD>
-<TD ALIGN=RIGHT>7</TD>
+<TD ALIGN=RIGHT>4</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
@@ -305,12 +305,6 @@
<TD ALIGN=RIGHT>12%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
-<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of DCM_ADVs</TD>
-<TD ALIGN=RIGHT>2</TD>
-<TD ALIGN=RIGHT>12</TD>
-<TD ALIGN=RIGHT>16%</TD>
-<TD COLSPAN='2'>&nbsp;</TD>
-</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of GTP_DUALs</TD>
<TD ALIGN=RIGHT>1</TD>
<TD ALIGN=RIGHT>8</TD>
@@ -330,7 +324,7 @@
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Average Fanout of Non-Clock Nets</TD>
-<TD ALIGN=RIGHT>4.26</TD>
+<TD ALIGN=RIGHT>4.28</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
@@ -367,19 +361,19 @@
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
-<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/fr909/git/riffa/project/base_systems/ml505/implementation/system.bld'>Translation Report</A></TD><TD>Current</TD><TD>Tue Sep 4 18:00:20 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='/home/fr909/git/riffa/project/base_systems/ml505/implementation/_xmsgs/ngdbuild.xmsgs?&DataKey=Warning'>64 Warnings (1 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='/home/fr909/git/riffa/project/base_systems/ml505/implementation/_xmsgs/ngdbuild.xmsgs?&DataKey=Info'>3 Infos (1 new)</A></TD></TR>
-<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/fr909/git/riffa/project/base_systems/ml505/implementation/system_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Tue Sep 4 18:03:50 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='/home/fr909/git/riffa/project/base_systems/ml505/implementation/_xmsgs/map.xmsgs?&DataKey=Warning'>147 Warnings (64 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='/home/fr909/git/riffa/project/base_systems/ml505/implementation/_xmsgs/map.xmsgs?&DataKey=Info'>888 Infos (45 new)</A></TD></TR>
-<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/fr909/git/riffa/project/base_systems/ml505/implementation/system.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Tue Sep 4 18:05:58 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='/home/fr909/git/riffa/project/base_systems/ml505/implementation/_xmsgs/par.xmsgs?&DataKey=Warning'>41 Warnings (36 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
-<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/fr909/git/riffa/project/base_systems/ml505/implementation/system.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Tue Sep 4 18:06:22 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='/home/fr909/git/riffa/project/base_systems/ml505/implementation/_xmsgs/trce.xmsgs?&DataKey=Info'>3 Infos (0 new)</A></TD></TR>
-<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/fr909/git/riffa/project/base_systems/ml505/implementation/system.bgn'>Bitgen Report</A></TD><TD>Current</TD><TD>Tue Sep 4 18:07:26 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='/home/fr909/git/riffa/project/base_systems/ml505/implementation/_xmsgs/bitgen.xmsgs?&DataKey=Warning'>5 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='/home/fr909/git/riffa/project/base_systems/ml505/implementation/_xmsgs/bitgen.xmsgs?&DataKey=Info'>2 Infos (0 new)</A></TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/fr909/git/riffa/project/base_systems/ml505/implementation/system.bld'>Translation Report</A></TD><TD>Current</TD><TD>Thu Sep 20 11:59:28 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='/home/fr909/git/riffa/project/base_systems/ml505/implementation/_xmsgs/ngdbuild.xmsgs?&DataKey=Warning'>64 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='/home/fr909/git/riffa/project/base_systems/ml505/implementation/_xmsgs/ngdbuild.xmsgs?&DataKey=Info'>1 Info (1 new)</A></TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/fr909/git/riffa/project/base_systems/ml505/implementation/system_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Thu Sep 20 12:02:50 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='/home/fr909/git/riffa/project/base_systems/ml505/implementation/_xmsgs/map.xmsgs?&DataKey=Warning'>147 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='/home/fr909/git/riffa/project/base_systems/ml505/implementation/_xmsgs/map.xmsgs?&DataKey=Info'>963 Infos (119 new)</A></TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/fr909/git/riffa/project/base_systems/ml505/implementation/system.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Thu Sep 20 12:04:52 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='/home/fr909/git/riffa/project/base_systems/ml505/implementation/_xmsgs/par.xmsgs?&DataKey=Warning'>77 Warnings (38 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/fr909/git/riffa/project/base_systems/ml505/implementation/system.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Thu Sep 20 12:05:15 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='/home/fr909/git/riffa/project/base_systems/ml505/implementation/_xmsgs/trce.xmsgs?&DataKey=Info'>3 Infos (0 new)</A></TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/fr909/git/riffa/project/base_systems/ml505/implementation/system.bgn'>Bitgen Report</A></TD><TD>Current</TD><TD>Thu Sep 20 12:06:17 2012</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='/home/fr909/git/riffa/project/base_systems/ml505/implementation/_xmsgs/bitgen.xmsgs?&DataKey=Warning'>5 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
-<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/fr909/git/riffa/project/base_systems/ml505/implementation/usage_statistics_webtalk.html'>WebTalk Report</A></TD><TD>Current</TD><TD COLSPAN='2'>Tue Sep 4 18:07:28 2012</TD></TR>
-<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/fr909/git/riffa/project/base_systems/ml505/implementation/webtalk.log'>WebTalk Log File</A></TD><TD>Current</TD><TD COLSPAN='2'>Tue Sep 4 18:07:29 2012</TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/fr909/git/riffa/project/base_systems/ml505/implementation/usage_statistics_webtalk.html'>WebTalk Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Tue Sep 4 18:07:28 2012</TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/fr909/git/riffa/project/base_systems/ml505/implementation/webtalk.log'>WebTalk Log File</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Tue Sep 4 18:07:29 2012</TD></TR>
</TABLE>
-<br><center><b>Date Generated:</b> 09/04/2012 - 18:11:27</center>
+<br><center><b>Date Generated:</b> 09/20/2012 - 12:06:23</center>
</BODY></HTML>
View
2 project/base_systems/ml505/implementation/system_summary.xml
@@ -4,7 +4,7 @@
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
-<DesignSummary rev="7">
+<DesignSummary rev="9">
<CmdHistory>
</CmdHistory>
</DesignSummary>
View
13,920 project/base_systems/ml505/implementation/system_usage.xml
6,960 additions, 6,960 deletions not shown because the diff is too large. Please use a local Git client to view these changes.
View
6 project/base_systems/ml505/pcores/riffa_v1_00_a/sw/linux/testapp/main.c
@@ -44,9 +44,9 @@
#define DATA_SIZE (20*1024*1024)
#define FILE_NAME "data.txt"
#define LOG_FILE "log.txt"
-#define DEBUG 0
-#define INFO 0
-#define LOG 1
+#define DEBUG 1
+#define INFO 1
+#define LOG 0
#define MAX(a,b) a > b ? a : b
struct timeval start, end;
View
75 project/base_systems/ml605/data/system.ucf
@@ -0,0 +1,75 @@
+# Virtex 6 ML605 Evaluation Platform
+
+###############################################################################
+# System level pin location constraints
+###############################################################################
+Net fpga_0_clk_1_sys_clk_p_pin LOC = J9;
+Net fpga_0_clk_1_sys_clk_p_pin IOSTANDARD = LVDS_25;
+Net fpga_0_clk_1_sys_clk_p_pin DIFF_TERM = TRUE;
+Net fpga_0_clk_1_sys_clk_n_pin LOC = H9;
+Net fpga_0_clk_1_sys_clk_n_pin IOSTANDARD = LVDS_25;
+Net fpga_0_clk_1_sys_clk_n_pin DIFF_TERM = TRUE;
+Net fpga_0_rst_1_sys_rst_pin LOC = H10;
+Net fpga_0_rst_1_sys_rst_pin IOSTANDARD = SSTL15;
+Net fpga_0_rst_1_sys_rst_pin PULLUP;
+Net fpga_0_rst_1_sys_rst_pin TIG;
+
+NET "CLK_S" TNM_NET = sys_clk_pin;
+TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 200000 kHz;
+
+NET "fpga_0_PCIe_perstn" TIG;
+NET "fpga_0_PCIe_perstn" LOC = AE13 | IOSTANDARD = LVCMOS25 | PULLUP | NODELAY ;
+
+###############################################################################
+# System level clock constraints
+###############################################################################
+NET "plbv46_pcie_0/REFCLK" TNM_NET = "PCIe_RefClk" ;
+NET "*/pcie_clocking_i/clk_125" TNM_NET = "PCIe_CLK_125" ;
+TIMESPEC "TS_PCIe_RefClk" = PERIOD "PCIe_RefClk" 250.00 MHz HIGH 50 % ;
+TIMESPEC "TS_PCIe_CLK_125" = PERIOD "PCIe_CLK_125" TS_PCIe_RefClk/2.0 HIGH 50 % PRIORITY 100;
+
+###############################################################################
+###### PCIe_Bridge constraints
+###############################################################################
+# SYS clock 250 MHz (input) signal. The sys_clk_p and sys_clk_n
+# signals are the PCI Express reference clock. Virtex-6 FPGA GT
+# Transceiver architecture requires the use of a dedicated clock
+# resources (FPGA input pins) associated with each GT Transceiver.
+# To use these pins an IBUFDS primitive (refclk_ibuf) is
+# instantiated in user's design.
+# See the Virtex-6 FPGA GT Transceiver User Guide
+# (UG) for guidelines regarding clock resource selection.
+#Net fpga_0_PCIe_Diff_Clk_P_pin LOC=V6 | IOSTANDARD = LVDS_25;
+#Net fpga_0_PCIe_Diff_Clk_N_pin LOC=V5 | IOSTANDARD = LVDS_25;
+INST "*/PCIe_Diff_Clk_0/USE_IBUFDS_GTXE1.GEN_IBUFDS_GTXE1[0].IBUFDS_GTXE1_I" LOC = IBUFDS_GTXE1_X0Y4;
+
+# Transceiver instance placement. This constraint selects the
+# transceivers to be used, which also dictates the pinout for the
+# transmit and receive differential pairs. See the
+# Virtex-6 FPGA GT Transceiver User Guide (UG) for more
+# information.
+# PCIe Lane 0
+#Net fpga_0_PCIe_Bridge_RXN_pin LOC=J4 | IOSTANDARD = LVDS_25;
+#Net fpga_0_PCIe_Bridge_RXP_pin LOC=J3 | IOSTANDARD = LVDS_25;
+#Net fpga_0_PCIe_Bridge_TXN_pin LOC=F2 | IOSTANDARD = LVDS_25;
+#Net fpga_0_PCIe_Bridge_TXP_pin LOC=F1 | IOSTANDARD = LVDS_25;
+INST "*/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX" LOC = GTXE1_X0Y15;
+
+# PCI Express Block placement. This constraint selects the PCI Express
+# Block to be used. #
+INST "*/pcie_2_0_i/pcie_block_i" LOC = PCIE_X0Y1;
+
+
+#
+# MMCM Placment. This constraint selects the MMCM Placement
+#
+INST "*/pcie_clocking_i/mmcm_adv_i" LOC = MMCM_ADV_X0Y7;
+
+################################################################################
+# Bridge clock domain crossing constraints
+################################################################################
+ NET "plbv46_pcie_0/*SPLB_Clk" TNM_NET = "SPLB_Clk";
+ NET "plbv46_pcie_0/*Bridge_Clk" TNM_NET = "Bridge_Clk";
+ TIMESPEC "TS_PLB_PCIe" = FROM "SPLB_Clk" TO "Bridge_Clk" 8 ns datapathonly;
+ TIMESPEC "TS_PCIe_PLB" = FROM "Bridge_Clk" TO "SPLB_Clk" 10 ns datapathonly;
+
View
1,345 ...ms/ml605/hdl/elaborate/bram_block_0_elaborate_v1_00_a/hdl/vhdl/bram_block_0_elaborate.vhd
@@ -0,0 +1,1345 @@
+-------------------------------------------------------------------------------
+-- bram_block_0_elaborate.vhd
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+entity bram_block_0_elaborate is
+ generic (
+ C_MEMSIZE : integer;
+ C_PORT_DWIDTH : integer;
+ C_PORT_AWIDTH : integer;
+ C_NUM_WE : integer;
+ C_FAMILY : string
+ );
+ port (
+ BRAM_Rst_A : in std_logic;
+ BRAM_Clk_A : in std_logic;
+ BRAM_EN_A : in std_logic;
+ BRAM_WEN_A : in std_logic_vector(0 to C_NUM_WE-1);
+ BRAM_Addr_A : in std_logic_vector(0 to C_PORT_AWIDTH-1);
+ BRAM_Din_A : out std_logic_vector(0 to C_PORT_DWIDTH-1);
+ BRAM_Dout_A : in std_logic_vector(0 to C_PORT_DWIDTH-1);
+ BRAM_Rst_B : in std_logic;
+ BRAM_Clk_B : in std_logic;
+ BRAM_EN_B : in std_logic;
+ BRAM_WEN_B : in std_logic_vector(0 to C_NUM_WE-1);
+ BRAM_Addr_B : in std_logic_vector(0 to C_PORT_AWIDTH-1);
+ BRAM_Din_B : out std_logic_vector(0 to C_PORT_DWIDTH-1);
+ BRAM_Dout_B : in std_logic_vector(0 to C_PORT_DWIDTH-1)
+ );
+
+ attribute keep_hierarchy : STRING;
+ attribute keep_hierarchy of bram_block_0_elaborate : entity is "yes";
+
+end bram_block_0_elaborate;
+
+architecture STRUCTURE of bram_block_0_elaborate is
+
+ component RAMB36E1 is
+ generic (
+ WRITE_MODE_A : string;
+ WRITE_MODE_B : string;
+ INIT_FILE : string;
+ READ_WIDTH_A : integer;
+ READ_WIDTH_B : integer;
+ WRITE_WIDTH_A : integer;
+ WRITE_WIDTH_B : integer;
+ RAM_EXTENSION_A : string;
+ RAM_EXTENSION_B : string
+ );
+ port (
+ DBITERR : out std_logic;
+ ECCPARITY : out std_logic_vector(7 downto 0);
+ INJECTDBITERR : in std_logic;
+ INJECTSBITERR : in std_logic;
+ RDADDRECC : out std_logic_vector(8 downto 0);
+ SBITERR : out std_logic;
+ ADDRARDADDR : in std_logic_vector(15 downto 0);
+ CASCADEINA : in std_logic;
+ CASCADEOUTA : out std_logic;
+ CLKARDCLK : in std_logic;
+ DIADI : in std_logic_vector(31 downto 0);
+ DIPADIP : in std_logic_vector(3 downto 0);
+ DOADO : out std_logic_vector(31 downto 0);
+ DOPADOP : out std_logic_vector(3 downto 0);
+ ENARDEN : in std_logic;
+ REGCEAREGCE : in std_logic;
+ RSTRAMARSTRAM : in std_logic;
+ RSTREGARSTREG : in std_logic;
+ WEA : in std_logic_vector(3 downto 0);
+ ADDRBWRADDR : in std_logic_vector(15 downto 0);
+ CASCADEINB : in std_logic;
+ CASCADEOUTB : out std_logic;
+ CLKBWRCLK : in std_logic;
+ DIBDI : in std_logic_vector(31 downto 0);
+ DIPBDIP : in std_logic_vector(3 downto 0);
+ DOBDO : out std_logic_vector(31 downto 0);
+ DOPBDOP : out std_logic_vector(3 downto 0);
+ ENBWREN : in std_logic;
+ REGCEB : in std_logic;
+ RSTRAMB : in std_logic;
+ RSTREGB : in std_logic;
+ WEBWE : in std_logic_vector(7 downto 0)
+ );
+ end component;
+
+ attribute BMM_INFO : STRING;
+
+ attribute BMM_INFO of ramb36e1_0: label is " ";
+ attribute BMM_INFO of ramb36e1_1: label is " ";
+ attribute BMM_INFO of ramb36e1_2: label is " ";
+ attribute BMM_INFO of ramb36e1_3: label is " ";
+ attribute BMM_INFO of ramb36e1_4: label is " ";
+ attribute BMM_INFO of ramb36e1_5: label is " ";
+ attribute BMM_INFO of ramb36e1_6: label is " ";
+ attribute BMM_INFO of ramb36e1_7: label is " ";
+ attribute BMM_INFO of ramb36e1_8: label is " ";
+ attribute BMM_INFO of ramb36e1_9: label is " ";
+ attribute BMM_INFO of ramb36e1_10: label is " ";
+ attribute BMM_INFO of ramb36e1_11: label is " ";
+ attribute BMM_INFO of ramb36e1_12: label is " ";
+ attribute BMM_INFO of ramb36e1_13: label is " ";
+ attribute BMM_INFO of ramb36e1_14: label is " ";
+ attribute BMM_INFO of ramb36e1_15: label is " ";
+ -- Internal signals
+
+ signal net_gnd0 : std_logic;
+ signal net_gnd4 : std_logic_vector(3 downto 0);
+ signal pgassign1 : std_logic_vector(0 to 0);
+ signal pgassign2 : std_logic_vector(0 to 0);
+ signal pgassign3 : std_logic_vector(0 to 29);
+ signal pgassign4 : std_logic_vector(0 to 3);
+ signal pgassign5 : std_logic_vector(15 downto 0);
+ signal pgassign6 : std_logic_vector(31 downto 0);
+ signal pgassign7 : std_logic_vector(31 downto 0);
+ signal pgassign8 : std_logic_vector(3 downto 0);
+ signal pgassign9 : std_logic_vector(15 downto 0);
+ signal pgassign10 : std_logic_vector(31 downto 0);
+ signal pgassign11 : std_logic_vector(31 downto 0);
+ signal pgassign12 : std_logic_vector(7 downto 0);
+ signal pgassign13 : std_logic_vector(15 downto 0);
+ signal pgassign14 : std_logic_vector(31 downto 0);
+ signal pgassign15 : std_logic_vector(31 downto 0);
+ signal pgassign16 : std_logic_vector(3 downto 0);
+ signal pgassign17 : std_logic_vector(15 downto 0);
+ signal pgassign18 : std_logic_vector(31 downto 0);
+ signal pgassign19 : std_logic_vector(31 downto 0);
+ signal pgassign20 : std_logic_vector(7 downto 0);
+ signal pgassign21 : std_logic_vector(15 downto 0);
+ signal pgassign22 : std_logic_vector(31 downto 0);
+ signal pgassign23 : std_logic_vector(31 downto 0);
+ signal pgassign24 : std_logic_vector(3 downto 0);
+ signal pgassign25 : std_logic_vector(15 downto 0);
+ signal pgassign26 : std_logic_vector(31 downto 0);
+ signal pgassign27 : std_logic_vector(31 downto 0);
+ signal pgassign28 : std_logic_vector(7 downto 0);
+ signal pgassign29 : std_logic_vector(15 downto 0);
+ signal pgassign30 : std_logic_vector(31 downto 0);
+ signal pgassign31 : std_logic_vector(31 downto 0);
+ signal pgassign32 : std_logic_vector(3 downto 0);
+ signal pgassign33 : std_logic_vector(15 downto 0);
+ signal pgassign34 : std_logic_vector(31 downto 0);
+ signal pgassign35 : std_logic_vector(31 downto 0);
+ signal pgassign36 : std_logic_vector(7 downto 0);
+ signal pgassign37 : std_logic_vector(15 downto 0);
+ signal pgassign38 : std_logic_vector(31 downto 0);
+ signal pgassign39 : std_logic_vector(31 downto 0);
+ signal pgassign40 : std_logic_vector(3 downto 0);
+ signal pgassign41 : std_logic_vector(15 downto 0);
+ signal pgassign42 : std_logic_vector(31 downto 0);
+ signal pgassign43 : std_logic_vector(31 downto 0);
+ signal pgassign44 : std_logic_vector(7 downto 0);
+ signal pgassign45 : std_logic_vector(15 downto 0);
+ signal pgassign46 : std_logic_vector(31 downto 0);
+ signal pgassign47 : std_logic_vector(31 downto 0);
+ signal pgassign48 : std_logic_vector(3 downto 0);
+ signal pgassign49 : std_logic_vector(15 downto 0);
+ signal pgassign50 : std_logic_vector(31 downto 0);
+ signal pgassign51 : std_logic_vector(31 downto 0);
+ signal pgassign52 : std_logic_vector(7 downto 0);
+ signal pgassign53 : std_logic_vector(15 downto 0);
+ signal pgassign54 : std_logic_vector(31 downto 0);
+ signal pgassign55 : std_logic_vector(31 downto 0);
+ signal pgassign56 : std_logic_vector(3 downto 0);
+ signal pgassign57 : std_logic_vector(15 downto 0);
+ signal pgassign58 : std_logic_vector(31 downto 0);
+ signal pgassign59 : std_logic_vector(31 downto 0);
+ signal pgassign60 : std_logic_vector(7 downto 0);
+ signal pgassign61 : std_logic_vector(15 downto 0);
+ signal pgassign62 : std_logic_vector(31 downto 0);
+ signal pgassign63 : std_logic_vector(31 downto 0);
+ signal pgassign64 : std_logic_vector(3 downto 0);
+ signal pgassign65 : std_logic_vector(15 downto 0);
+ signal pgassign66 : std_logic_vector(31 downto 0);
+ signal pgassign67 : std_logic_vector(31 downto 0);
+ signal pgassign68 : std_logic_vector(7 downto 0);
+ signal pgassign69 : std_logic_vector(15 downto 0);
+ signal pgassign70 : std_logic_vector(31 downto 0);
+ signal pgassign71 : std_logic_vector(31 downto 0);
+ signal pgassign72 : std_logic_vector(3 downto 0);
+ signal pgassign73 : std_logic_vector(15 downto 0);
+ signal pgassign74 : std_logic_vector(31 downto 0);
+ signal pgassign75 : std_logic_vector(31 downto 0);
+ signal pgassign76 : std_logic_vector(7 downto 0);
+ signal pgassign77 : std_logic_vector(15 downto 0);
+ signal pgassign78 : std_logic_vector(31 downto 0);
+ signal pgassign79 : std_logic_vector(31 downto 0);
+ signal pgassign80 : std_logic_vector(3 downto 0);
+ signal pgassign81 : std_logic_vector(15 downto 0);
+ signal pgassign82 : std_logic_vector(31 downto 0);
+ signal pgassign83 : std_logic_vector(31 downto 0);
+ signal pgassign84 : std_logic_vector(7 downto 0);
+ signal pgassign85 : std_logic_vector(15 downto 0);
+ signal pgassign86 : std_logic_vector(31 downto 0);
+ signal pgassign87 : std_logic_vector(31 downto 0);
+ signal pgassign88 : std_logic_vector(3 downto 0);
+ signal pgassign89 : std_logic_vector(15 downto 0);
+ signal pgassign90 : std_logic_vector(31 downto 0);
+ signal pgassign91 : std_logic_vector(31 downto 0);
+ signal pgassign92 : std_logic_vector(7 downto 0);
+ signal pgassign93 : std_logic_vector(15 downto 0);
+ signal pgassign94 : std_logic_vector(31 downto 0);
+ signal pgassign95 : std_logic_vector(31 downto 0);
+ signal pgassign96 : std_logic_vector(3 downto 0);
+ signal pgassign97 : std_logic_vector(15 downto 0);
+ signal pgassign98 : std_logic_vector(31 downto 0);
+ signal pgassign99 : std_logic_vector(31 downto 0);
+ signal pgassign100 : std_logic_vector(7 downto 0);
+ signal pgassign101 : std_logic_vector(15 downto 0);
+ signal pgassign102 : std_logic_vector(31 downto 0);
+ signal pgassign103 : std_logic_vector(31 downto 0);
+ signal pgassign104 : std_logic_vector(3 downto 0);
+ signal pgassign105 : std_logic_vector(15 downto 0);
+ signal pgassign106 : std_logic_vector(31 downto 0);
+ signal pgassign107 : std_logic_vector(31 downto 0);
+ signal pgassign108 : std_logic_vector(7 downto 0);
+ signal pgassign109 : std_logic_vector(15 downto 0);
+ signal pgassign110 : std_logic_vector(31 downto 0);
+ signal pgassign111 : std_logic_vector(31 downto 0);
+ signal pgassign112 : std_logic_vector(3 downto 0);
+ signal pgassign113 : std_logic_vector(15 downto 0);
+ signal pgassign114 : std_logic_vector(31 downto 0);
+ signal pgassign115 : std_logic_vector(31 downto 0);
+ signal pgassign116 : std_logic_vector(7 downto 0);
+ signal pgassign117 : std_logic_vector(15 downto 0);
+ signal pgassign118 : std_logic_vector(31 downto 0);
+ signal pgassign119 : std_logic_vector(31 downto 0);
+ signal pgassign120 : std_logic_vector(3 downto 0);
+ signal pgassign121 : std_logic_vector(15 downto 0);
+ signal pgassign122 : std_logic_vector(31 downto 0);
+ signal pgassign123 : std_logic_vector(31 downto 0);
+ signal pgassign124 : std_logic_vector(7 downto 0);
+ signal pgassign125 : std_logic_vector(15 downto 0);
+ signal pgassign126 : std_logic_vector(31 downto 0);
+ signal pgassign127 : std_logic_vector(31 downto 0);
+ signal pgassign128 : std_logic_vector(3 downto 0);
+ signal pgassign129 : std_logic_vector(15 downto 0);
+ signal pgassign130 : std_logic_vector(31 downto 0);
+ signal pgassign131 : std_logic_vector(31 downto 0);
+ signal pgassign132 : std_logic_vector(7 downto 0);
+
+begin
+
+ -- Internal assignments
+
+ pgassign1(0 to 0) <= B"1";
+ pgassign2(0 to 0) <= B"0";
+ pgassign3(0 to 29) <= B"000000000000000000000000000000";
+ pgassign4(0 to 3) <= B"0000";
+ pgassign5(15 downto 15) <= B"1";
+ pgassign5(14 downto 1) <= BRAM_Addr_A(16 to 29);
+ pgassign5(0 downto 0) <= B"0";
+ pgassign6(31 downto 2) <= B"000000000000000000000000000000";
+ pgassign6(1 downto 0) <= BRAM_Dout_A(0 to 1);
+ BRAM_Din_A(0 to 1) <= pgassign7(1 downto 0);
+ pgassign8(3 downto 3) <= BRAM_WEN_A(0 to 0);
+ pgassign8(2 downto 2) <= BRAM_WEN_A(0 to 0);
+ pgassign8(1 downto 1) <= BRAM_WEN_A(0 to 0);
+ pgassign8(0 downto 0) <= BRAM_WEN_A(0 to 0);
+ pgassign9(15 downto 15) <= B"1";
+ pgassign9(14 downto 1) <= BRAM_Addr_B(16 to 29);
+ pgassign9(0 downto 0) <= B"0";
+ pgassign10(31 downto 2) <= B"000000000000000000000000000000";
+ pgassign10(1 downto 0) <= BRAM_Dout_B(0 to 1);
+ BRAM_Din_B(0 to 1) <= pgassign11(1 downto 0);
+ pgassign12(7 downto 4) <= B"0000";
+ pgassign12(3 downto 3) <= BRAM_WEN_B(0 to 0);
+ pgassign12(2 downto 2) <= BRAM_WEN_B(0 to 0);
+ pgassign12(1 downto 1) <= BRAM_WEN_B(0 to 0);
+ pgassign12(0 downto 0) <= BRAM_WEN_B(0 to 0);
+ pgassign13(15 downto 15) <= B"1";
+ pgassign13(14 downto 1) <= BRAM_Addr_A(16 to 29);
+ pgassign13(0 downto 0) <= B"0";
+ pgassign14(31 downto 2) <= B"000000000000000000000000000000";
+ pgassign14(1 downto 0) <= BRAM_Dout_A(2 to 3);
+ BRAM_Din_A(2 to 3) <= pgassign15(1 downto 0);
+ pgassign16(3 downto 3) <= BRAM_WEN_A(0 to 0);
+ pgassign16(2 downto 2) <= BRAM_WEN_A(0 to 0);
+ pgassign16(1 downto 1) <= BRAM_WEN_A(0 to 0);
+ pgassign16(0 downto 0) <= BRAM_WEN_A(0 to 0);
+ pgassign17(15 downto 15) <= B"1";
+ pgassign17(14 downto 1) <= BRAM_Addr_B(16 to 29);
+ pgassign17(0 downto 0) <= B"0";
+ pgassign18(31 downto 2) <= B"000000000000000000000000000000";
+ pgassign18(1 downto 0) <= BRAM_Dout_B(2 to 3);
+ BRAM_Din_B(2 to 3) <= pgassign19(1 downto 0);
+ pgassign20(7 downto 4) <= B"0000";
+ pgassign20(3 downto 3) <= BRAM_WEN_B(0 to 0);
+ pgassign20(2 downto 2) <= BRAM_WEN_B(0 to 0);
+ pgassign20(1 downto 1) <= BRAM_WEN_B(0 to 0);
+ pgassign20(0 downto 0) <= BRAM_WEN_B(0 to 0);
+ pgassign21(15 downto 15) <= B"1";
+ pgassign21(14 downto 1) <= BRAM_Addr_A(16 to 29);
+ pgassign21(0 downto 0) <= B"0";
+ pgassign22(31 downto 2) <= B"000000000000000000000000000000";
+ pgassign22(1 downto 0) <= BRAM_Dout_A(4 to 5);
+ BRAM_Din_A(4 to 5) <= pgassign23(1 downto 0);
+ pgassign24(3 downto 3) <= BRAM_WEN_A(0 to 0);
+ pgassign24(2 downto 2) <= BRAM_WEN_A(0 to 0);
+ pgassign24(1 downto 1) <= BRAM_WEN_A(0 to 0);
+ pgassign24(0 downto 0) <= BRAM_WEN_A(0 to 0);
+ pgassign25(15 downto 15) <= B"1";
+ pgassign25(14 downto 1) <= BRAM_Addr_B(16 to 29);
+ pgassign25(0 downto 0) <= B"0";
+ pgassign26(31 downto 2) <= B"000000000000000000000000000000";
+ pgassign26(1 downto 0) <= BRAM_Dout_B(4 to 5);
+ BRAM_Din_B(4 to 5) <= pgassign27(1 downto 0);
+ pgassign28(7 downto 4) <= B"0000";
+ pgassign28(3 downto 3) <= BRAM_WEN_B(0 to 0);
+ pgassign28(2 downto 2) <= BRAM_WEN_B(0 to 0);
+ pgassign28(1 downto 1) <= BRAM_WEN_B(0 to 0);
+ pgassign28(0 downto 0) <= BRAM_WEN_B(0 to 0);
+ pgassign29(15 downto 15) <= B"1";
+ pgassign29(14 downto 1) <= BRAM_Addr_A(16 to 29);
+ pgassign29(0 downto 0) <= B"0";
+ pgassign30(31 downto 2) <= B"000000000000000000000000000000";
+ pgassign30(1 downto 0) <= BRAM_Dout_A(6 to 7);
+ BRAM_Din_A(6 to 7) <= pgassign31(1 downto 0);
+ pgassign32(3 downto 3) <= BRAM_WEN_A(0 to 0);
+ pgassign32(2 downto 2) <= BRAM_WEN_A(0 to 0);
+ pgassign32(1 downto 1) <= BRAM_WEN_A(0 to 0);
+ pgassign32(0 downto 0) <= BRAM_WEN_A(0 to 0);
+ pgassign33(15 downto 15) <= B"1";
+ pgassign33(14 downto 1) <= BRAM_Addr_B(16 to 29);
+ pgassign33(0 downto 0) <= B"0";
+ pgassign34(31 downto 2) <= B"000000000000000000000000000000";
+ pgassign34(1 downto 0) <= BRAM_Dout_B(6 to 7);
+ BRAM_Din_B(6 to 7) <= pgassign35(1 downto 0);
+ pgassign36(7 downto 4) <= B"0000";
+ pgassign36(3 downto 3) <= BRAM_WEN_B(0 to 0);
+ pgassign36(2 downto 2) <= BRAM_WEN_B(0 to 0);
+ pgassign36(1 downto 1) <= BRAM_WEN_B(0 to 0);
+ pgassign36(0 downto 0) <= BRAM_WEN_B(0 to 0);
+ pgassign37(15 downto 15) <= B"1";
+ pgassign37(14 downto 1) <= BRAM_Addr_A(16 to 29);
+ pgassign37(0 downto 0) <= B"0";
+ pgassign38(31 downto 2) <= B"000000000000000000000000000000";
+ pgassign38(1 downto 0) <= BRAM_Dout_A(8 to 9);
+ BRAM_Din_A(8 to 9) <= pgassign39(1 downto 0);
+ pgassign40(3 downto 3) <= BRAM_WEN_A(1 to 1);
+ pgassign40(2 downto 2) <= BRAM_WEN_A(1 to 1);
+ pgassign40(1 downto 1) <= BRAM_WEN_A(1 to 1);
+ pgassign40(0 downto 0) <= BRAM_WEN_A(1 to 1);
+ pgassign41(15 downto 15) <= B"1";
+ pgassign41(14 downto 1) <= BRAM_Addr_B(16 to 29);
+ pgassign41(0 downto 0) <= B"0";
+ pgassign42(31 downto 2) <= B"000000000000000000000000000000";
+ pgassign42(1 downto 0) <= BRAM_Dout_B(8 to 9);
+ BRAM_Din_B(8 to 9) <= pgassign43(1 downto 0);
+ pgassign44(7 downto 4) <= B"0000";
+ pgassign44(3 downto 3) <= BRAM_WEN_B(1 to 1);
+ pgassign44(2 downto 2) <= BRAM_WEN_B(1 to 1);
+ pgassign44(1 downto 1) <= BRAM_WEN_B(1 to 1);
+ pgassign44(0 downto 0) <= BRAM_WEN_B(1 to 1);
+ pgassign45(15 downto 15) <= B"1";
+ pgassign45(14 downto 1) <= BRAM_Addr_A(16 to 29);
+ pgassign45(0 downto 0) <= B"0";
+ pgassign46(31 downto 2) <= B"000000000000000000000000000000";
+ pgassign46(1 downto 0) <= BRAM_Dout_A(10 to 11);
+ BRAM_Din_A(10 to 11) <= pgassign47(1 downto 0);
+ pgassign48(3 downto 3) <= BRAM_WEN_A(1 to 1);
+ pgassign48(2 downto 2) <= BRAM_WEN_A(1 to 1);
+ pgassign48(1 downto 1) <= BRAM_WEN_A(1 to 1);
+ pgassign48(0 downto 0) <= BRAM_WEN_A(1 to 1);
+ pgassign49(15 downto 15) <= B"1";
+ pgassign49(14 downto 1) <= BRAM_Addr_B(16 to 29);
+ pgassign49(0 downto 0) <= B"0";
+ pgassign50(31 downto 2) <= B"000000000000000000000000000000";
+ pgassign50(1 downto 0) <= BRAM_Dout_B(10 to 11);
+ BRAM_Din_B(10 to 11) <= pgassign51(1 downto 0);
+ pgassign52(7 downto 4) <= B"0000";
+ pgassign52(3 downto 3) <= BRAM_WEN_B(1 to 1);
+ pgassign52(2 downto 2) <= BRAM_WEN_B(1 to 1);
+ pgassign52(1 downto 1) <= BRAM_WEN_B(1 to 1);
+ pgassign52(0 downto 0) <= BRAM_WEN_B(1 to 1);
+ pgassign53(15 downto 15) <= B"1";
+ pgassign53(14 downto 1) <= BRAM_Addr_A(16 to 29);
+ pgassign53(0 downto 0) <= B"0";
+ pgassign54(31 downto 2) <= B"000000000000000000000000000000";
+ pgassign54(1 downto 0) <= BRAM_Dout_A(12 to 13);
+ BRAM_Din_A(12 to 13) <= pgassign55(1 downto 0);
+ pgassign56(3 downto 3) <= BRAM_WEN_A(1 to 1);
+ pgassign56(2 downto 2) <= BRAM_WEN_A(1 to 1);
+ pgassign56(1 downto 1) <= BRAM_WEN_A(1 to 1);
+ pgassign56(0 downto 0) <= BRAM_WEN_A(1 to 1);
+ pgassign57(15 downto 15) <= B"1";
+ pgassign57(14 downto 1) <= BRAM_Addr_B(16 to 29);
+ pgassign57(0 downto 0) <= B"0";
+ pgassign58(31 downto 2) <= B"000000000000000000000000000000";
+ pgassign58(1 downto 0) <= BRAM_Dout_B(12 to 13);
+ BRAM_Din_B(12 to 13) <= pgassign59(1 downto 0);
+ pgassign60(7 downto 4) <= B"0000";
+ pgassign60(3 downto 3) <= BRAM_WEN_B(1 to 1);
+ pgassign60(2 downto 2) <= BRAM_WEN_B(1 to 1);
+ pgassign60(1 downto 1) <= BRAM_WEN_B(1 to 1);
+ pgassign60(0 downto 0) <= BRAM_WEN_B(1 to 1);
+ pgassign61(15 downto 15) <= B"1";
+ pgassign61(14 downto 1) <= BRAM_Addr_A(16 to 29);
+ pgassign61(0 downto 0) <= B"0";
+ pgassign62(31 downto 2) <= B"000000000000000000000000000000";
+ pgassign62(1 downto 0) <= BRAM_Dout_A(14 to 15);
+ BRAM_Din_A(14 to 15) <= pgassign63(1 downto 0);
+ pgassign64(3 downto 3) <= BRAM_WEN_A(1 to 1);
+ pgassign64(2 downto 2) <= BRAM_WEN_A(1 to 1);
+ pgassign64(1 downto 1) <= BRAM_WEN_A(1 to 1);
+ pgassign64(0 downto 0) <= BRAM_WEN_A(1 to 1);
+ pgassign65(15 downto 15) <= B"1";
+ pgassign65(14 downto 1) <= BRAM_Addr_B(16 to 29);
+ pgassign65(0 downto 0) <= B"0";
+ pgassign66(31 downto 2) <= B"000000000000000000000000000000";
+ pgassign66(1 downto 0) <= BRAM_Dout_B(14 to 15);
+ BRAM_Din_B(14 to 15) <= pgassign67(1 downto 0);
+ pgassign68(7 downto 4) <= B"0000";
+ pgassign68(3 downto 3) <= BRAM_WEN_B(1 to 1);
+ pgassign68(2 downto 2) <= BRAM_WEN_B(1 to 1);
+ pgassign68(1 downto 1) <= BRAM_WEN_B(1 to 1);
+ pgassign68(0 downto 0) <= BRAM_WEN_B(1 to 1);
+ pgassign69(15 downto 15) <= B"1";
+ pgassign69(14 downto 1) <= BRAM_Addr_A(16 to 29);
+ pgassign69(0 downto 0) <= B"0";
+ pgassign70(31 downto 2) <= B"000000000000000000000000000000";
+ pgassign70(1 downto 0) <= BRAM_Dout_A(16 to 17);
+ BRAM_Din_A(16 to 17) <= pgassign71(1 downto 0);
+ pgassign72(3 downto 3) <= BRAM_WEN_A(2 to 2);
+ pgassign72(2 downto 2) <= BRAM_WEN_A(2 to 2);
+ pgassign72(1 downto 1) <= BRAM_WEN_A(2 to 2);
+ pgassign72(0 downto 0) <= BRAM_WEN_A(2 to 2);
+ pgassign73(15 downto 15) <= B"1";
+ pgassign73(14 downto 1) <= BRAM_Addr_B(16 to 29);
+ pgassign73(0 downto 0) <= B"0";
+ pgassign74(31 downto 2) <= B"000000000000000000000000000000";
+ pgassign74(1 downto 0) <= BRAM_Dout_B(16 to 17);
+ BRAM_Din_B(16 to 17) <= pgassign75(1 downto 0);
+ pgassign76(7 downto 4) <= B"0000";
+ pgassign76(3 downto 3) <= BRAM_WEN_B(2 to 2);
+ pgassign76(2 downto 2) <= BRAM_WEN_B(2 to 2);
+ pgassign76(1 downto 1) <= BRAM_WEN_B(2 to 2);
+ pgassign76(0 downto 0) <= BRAM_WEN_B(2 to 2);
+ pgassign77(15 downto 15) <= B"1";
+ pgassign77(14 downto 1) <= BRAM_Addr_A(16 to 29);
+ pgassign77(0 downto 0) <= B"0";
+ pgassign78(31 downto 2) <= B"000000000000000000000000000000";
+ pgassign78(1 downto 0) <= BRAM_Dout_A(18 to 19);
+ BRAM_Din_A(18 to 19) <= pgassign79(1 downto 0);
+ pgassign80(3 downto 3) <= BRAM_WEN_A(2 to 2);
+ pgassign80(2 downto 2) <= BRAM_WEN_A(2 to 2);
+ pgassign80(1 downto 1) <= BRAM_WEN_A(2 to 2);
+ pgassign80(0 downto 0) <= BRAM_WEN_A(2 to 2);
+ pgassign81(15 downto 15) <= B"1";
+ pgassign81(14 downto 1) <= BRAM_Addr_B(16 to 29);
+ pgassign81(0 downto 0) <= B"0";
+ pgassign82(31 downto 2) <= B"000000000000000000000000000000";
+ pgassign82(1 downto 0) <= BRAM_Dout_B(18 to 19);
+ BRAM_Din_B(18 to 19) <= pgassign83(1 downto 0);
+ pgassign84(7 downto 4) <= B"0000";
+ pgassign84(3 downto 3) <= BRAM_WEN_B(2 to 2);
+ pgassign84(2 downto 2) <= BRAM_WEN_B(2 to 2);
+ pgassign84(1 downto 1) <= BRAM_WEN_B(2 to 2);
+ pgassign84(0 downto 0) <= BRAM_WEN_B(2 to 2);
+ pgassign85(15 downto 15) <= B"1";
+ pgassign85(14 downto 1) <= BRAM_Addr_A(16 to 29);
+ pgassign85(0 downto 0) <= B"0";
+ pgassign86(31 downto 2) <= B"000000000000000000000000000000";
+ pgassign86(1 downto 0) <= BRAM_Dout_A(20 to 21);
+ BRAM_Din_A(20 to 21) <= pgassign87(1 downto 0);
+ pgassign88(3 downto 3) <= BRAM_WEN_A(2 to 2);
+ pgassign88(2 downto 2) <= BRAM_WEN_A(2 to 2);
+ pgassign88(1 downto 1) <= BRAM_WEN_A(2 to 2);
+ pgassign88(0 downto 0) <= BRAM_WEN_A(2 to 2);
+ pgassign89(15 downto 15) <= B"1";
+ pgassign89(14 downto 1) <= BRAM_Addr_B(16 to 29);
+ pgassign89(0 downto 0) <= B"0";
+ pgassign90(31 downto 2) <= B"000000000000000000000000000000";
+ pgassign90(1 downto 0) <= BRAM_Dout_B(20 to 21);
+ BRAM_Din_B(20 to 21) <= pgassign91(1 downto 0);
+ pgassign92(7 downto 4) <= B"0000";
+ pgassign92(3 downto 3) <= BRAM_WEN_B(2 to 2);
+ pgassign92(2 downto 2) <= BRAM_WEN_B(2 to 2);
+ pgassign92(1 downto 1) <= BRAM_WEN_B(2 to 2);
+ pgassign92(0 downto 0) <= BRAM_WEN_B(2 to 2);
+ pgassign93(15 downto 15) <= B"1";
+ pgassign93(14 downto 1) <= BRAM_Addr_A(16 to 29);
+ pgassign93(0 downto 0) <= B"0";
+ pgassign94(31 downto 2) <= B"000000000000000000000000000000";
+ pgassign94(1 downto 0) <= BRAM_Dout_A(22 to 23);
+ BRAM_Din_A(22 to 23) <= pgassign95(1 downto 0);
+ pgassign96(3 downto 3) <= BRAM_WEN_A(2 to 2);
+ pgassign96(2 downto 2) <= BRAM_WEN_A(2 to 2);
+ pgassign96(1 downto 1) <= BRAM_WEN_A(2 to 2);
+ pgassign96(0 downto 0) <= BRAM_WEN_A(2 to 2);
+ pgassign97(15 downto 15) <= B"1";
+ pgassign97(14 downto 1) <= BRAM_Addr_B(16 to 29);
+ pgassign97(0 downto 0) <= B"0";
+ pgassign98(31 downto 2) <= B"000000000000000000000000000000";
+ pgassign98(1 downto 0) <= BRAM_Dout_B(22 to 23);
+ BRAM_Din_B(22 to 23) <= pgassign99(1 downto 0);
+ pgassign100(7 downto 4) <= B"0000";
+ pgassign100(3 downto 3) <= BRAM_WEN_B(2 to 2);
+ pgassign100(2 downto 2) <= BRAM_WEN_B(2 to 2);
+ pgassign100(1 downto 1) <= BRAM_WEN_B(2 to 2);
+ pgassign100(0 downto 0) <= BRAM_WEN_B(2 to 2);
+ pgassign101(15 downto 15) <= B"1";
+ pgassign101(14 downto 1) <= BRAM_Addr_A(16 to 29);
+ pgassign101(0 downto 0) <= B"0";
+ pgassign102(31 downto 2) <= B"000000000000000000000000000000";
+ pgassign102(1 downto 0) <= BRAM_Dout_A(24 to 25);
+ BRAM_Din_A(24 to 25) <= pgassign103(1 downto 0);
+ pgassign104(3 downto 3) <= BRAM_WEN_A(3 to 3);
+ pgassign104(2 downto 2) <= BRAM_WEN_A(3 to 3);
+ pgassign104(1 downto 1) <= BRAM_WEN_A(3 to 3);
+ pgassign104(0 downto 0) <= BRAM_WEN_A(3 to 3);
+ pgassign105(15 downto 15) <= B"1";
+ pgassign105(14 downto 1) <= BRAM_Addr_B(16 to 29);
+ pgassign105(0 downto 0) <= B"0";
+ pgassign106(31 downto 2) <= B"000000000000000000000000000000";
+ pgassign106(1 downto 0) <= BRAM_Dout_B(24 to 25);
+ BRAM_Din_B(24 to 25) <= pgassign107(1 downto 0);
+ pgassign108(7 downto 4) <= B"0000";
+ pgassign108(3 downto 3) <= BRAM_WEN_B(3 to 3);
+ pgassign108(2 downto 2) <= BRAM_WEN_B(3 to 3);
+ pgassign108(1 downto 1) <= BRAM_WEN_B(3 to 3);
+ pgassign108(0 downto 0) <= BRAM_WEN_B(3 to 3);
+ pgassign109(15 downto 15) <= B"1";
+ pgassign109(14 downto 1) <= BRAM_Addr_A(16 to 29);
+ pgassign109(0 downto 0) <= B"0";
+ pgassign110(31 downto 2) <= B"000000000000000000000000000000";
+ pgassign110(1 downto 0) <= BRAM_Dout_A(26 to 27);
+ BRAM_Din_A(26 to 27) <= pgassign111(1 downto 0);
+ pgassign112(3 downto 3) <= BRAM_WEN_A(3 to 3);
+ pgassign112(2 downto 2) <= BRAM_WEN_A(3 to 3);
+ pgassign112(1 downto 1) <= BRAM_WEN_A(3 to 3);
+ pgassign112(0 downto 0) <= BRAM_WEN_A(3 to 3);
+ pgassign113(15 downto 15) <= B"1";
+ pgassign113(14 downto 1) <= BRAM_Addr_B(16 to 29);
+ pgassign113(0 downto 0) <= B"0";
+ pgassign114(31 downto 2) <= B"000000000000000000000000000000";
+ pgassign114(1 downto 0) <= BRAM_Dout_B(26 to 27);
+ BRAM_Din_B(26 to 27) <= pgassign115(1 downto 0);
+ pgassign116(7 downto 4) <= B"0000";
+ pgassign116(3 downto 3) <= BRAM_WEN_B(3 to 3);
+ pgassign116(2 downto 2) <= BRAM_WEN_B(3 to 3);
+ pgassign116(1 downto 1) <= BRAM_WEN_B(3 to 3);
+ pgassign116(0 downto 0) <= BRAM_WEN_B(3 to 3);
+ pgassign117(15 downto 15) <= B"1";
+ pgassign117(14 downto 1) <= BRAM_Addr_A(16 to 29);
+ pgassign117(0 downto 0) <= B"0";
+ pgassign118(31 downto 2) <= B"000000000000000000000000000000";
+ pgassign118(1 downto 0) <= BRAM_Dout_A(28 to 29);
+ BRAM_Din_A(28 to 29) <= pgassign119(1 downto 0);
+ pgassign120(3 downto 3) <= BRAM_WEN_A(3 to 3);
+ pgassign120(2 downto 2) <= BRAM_WEN_A(3 to 3);
+ pgassign120(1 downto 1) <= BRAM_WEN_A(3 to 3);
+ pgassign120(0 downto 0) <= BRAM_WEN_A(3 to 3);
+ pgassign121(15 downto 15) <= B"1";
+ pgassign121(14 downto 1) <= BRAM_Addr_B(16 to 29);
+ pgassign121(0 downto 0) <= B"0";
+ pgassign122(31 downto 2) <= B"000000000000000000000000000000";
+ pgassign122(1 downto 0) <= BRAM_Dout_B(28 to 29);
+ BRAM_Din_B(28 to 29) <= pgassign123(1 downto 0);
+ pgassign124(7 downto 4) <= B"0000";
+ pgassign124(3 downto 3) <= BRAM_WEN_B(3 to 3);
+ pgassign124(2 downto 2) <= BRAM_WEN_B(3 to 3);
+ pgassign124(1 downto 1) <= BRAM_WEN_B(3 to 3);
+ pgassign124(0 downto 0) <= BRAM_WEN_B(3 to 3);
+ pgassign125(15 downto 15) <= B"1";
+ pgassign125(14 downto 1) <= BRAM_Addr_A(16 to 29);
+ pgassign125(0 downto 0) <= B"0";
+ pgassign126(31 downto 2) <= B"000000000000000000000000000000";
+ pgassign126(1 downto 0) <= BRAM_Dout_A(30 to 31);
+ BRAM_Din_A(30 to 31) <= pgassign127(1 downto 0);
+ pgassign128(3 downto 3) <= BRAM_WEN_A(3 to 3);
+ pgassign128(2 downto 2) <= BRAM_WEN_A(3 to 3);
+ pgassign128(1 downto 1) <= BRAM_WEN_A(3 to 3);
+ pgassign128(0 downto 0) <= BRAM_WEN_A(3 to 3);
+ pgassign129(15 downto 15) <= B"1";
+ pgassign129(14 downto 1) <= BRAM_Addr_B(16 to 29);
+ pgassign129(0 downto 0) <= B"0";
+ pgassign130(31 downto 2) <= B"000000000000000000000000000000";
+ pgassign130(1 downto 0) <= BRAM_Dout_B(30 to 31);
+ BRAM_Din_B(30 to 31) <= pgassign131(1 downto 0);
+ pgassign132(7 downto 4) <= B"0000";
+ pgassign132(3 downto 3) <= BRAM_WEN_B(3 to 3);
+ pgassign132(2 downto 2) <= BRAM_WEN_B(3 to 3);
+ pgassign132(1 downto 1) <= BRAM_WEN_B(3 to 3);
+ pgassign132(0 downto 0) <= BRAM_WEN_B(3 to 3);
+ net_gnd0 <= '0';
+ net_gnd4(3 downto 0) <= B"0000";
+
+ ramb36e1_0 : RAMB36E1
+ generic map (
+ WRITE_MODE_A => "WRITE_FIRST",
+ WRITE_MODE_B => "WRITE_FIRST",
+ INIT_FILE => "bram_block_0_combined_0.mem",
+ READ_WIDTH_A => 2,
+ READ_WIDTH_B => 2,
+ WRITE_WIDTH_A => 2,
+ WRITE_WIDTH_B => 2,
+ RAM_EXTENSION_A => "NONE",
+ RAM_EXTENSION_B => "NONE"
+ )
+ port map (
+ DBITERR => open,
+ ECCPARITY => open,
+ INJECTDBITERR => net_gnd0,
+ INJECTSBITERR => net_gnd0,
+ RDADDRECC => open,
+ SBITERR => open,
+ ADDRARDADDR => pgassign5,
+ CASCADEINA => net_gnd0,
+ CASCADEOUTA => open,
+ CLKARDCLK => BRAM_Clk_A,
+ DIADI => pgassign6,
+ DIPADIP => net_gnd4,
+ DOADO => pgassign7,
+ DOPADOP => open,
+ ENARDEN => BRAM_EN_A,
+ REGCEAREGCE => net_gnd0,
+ RSTRAMARSTRAM => BRAM_Rst_A,
+ RSTREGARSTREG => net_gnd0,
+ WEA => pgassign8,
+ ADDRBWRADDR => pgassign9,
+ CASCADEINB => net_gnd0,
+ CASCADEOUTB => open,
+ CLKBWRCLK => BRAM_Clk_B,
+ DIBDI => pgassign10,
+ DIPBDIP => net_gnd4,
+ DOBDO => pgassign11,
+ DOPBDOP => open,
+ ENBWREN => BRAM_EN_B,
+ REGCEB => net_gnd0,
+ RSTRAMB => BRAM_Rst_B,
+ RSTREGB => net_gnd0,
+ WEBWE => pgassign12
+ );
+
+ ramb36e1_1 : RAMB36E1
+ generic map (
+ WRITE_MODE_A => "WRITE_FIRST",
+ WRITE_MODE_B => "WRITE_FIRST",
+ INIT_FILE => "bram_block_0_combined_1.mem",
+ READ_WIDTH_A => 2,
+ READ_WIDTH_B => 2,
+ WRITE_WIDTH_A => 2,
+ WRITE_WIDTH_B => 2,
+ RAM_EXTENSION_A => "NONE",
+ RAM_EXTENSION_B => "NONE"
+ )
+ port map (
+ DBITERR => open,
+ ECCPARITY => open,
+ INJECTDBITERR => net_gnd0,
+ INJECTSBITERR => net_gnd0,
+ RDADDRECC => open,
+ SBITERR => open,
+ ADDRARDADDR => pgassign13,
+ CASCADEINA => net_gnd0,
+ CASCADEOUTA => open,
+ CLKARDCLK => BRAM_Clk_A,
+ DIADI => pgassign14,
+ DIPADIP => net_gnd4,
+ DOADO => pgassign15,
+ DOPADOP => open,
+ ENARDEN => BRAM_EN_A,
+ REGCEAREGCE => net_gnd0,
+ RSTRAMARSTRAM => BRAM_Rst_A,
+ RSTREGARSTREG => net_gnd0,
+ WEA => pgassign16,
+ ADDRBWRADDR => pgassign17,
+ CASCADEINB => net_gnd0,
+ CASCADEOUTB => open,
+ CLKBWRCLK => BRAM_Clk_B,
+ DIBDI => pgassign18,
+ DIPBDIP => net_gnd4,
+ DOBDO => pgassign19,
+ DOPBDOP => open,
+ ENBWREN => BRAM_EN_B,
+ REGCEB => net_gnd0,
+ RSTRAMB => BRAM_Rst_B,
+ RSTREGB => net_gnd0,
+ WEBWE => pgassign20
+ );
+
+ ramb36e1_2 : RAMB36E1
+ generic map (
+ WRITE_MODE_A => "WRITE_FIRST",
+ WRITE_MODE_B => "WRITE_FIRST",
+ INIT_FILE => "bram_block_0_combined_2.mem",
+ READ_WIDTH_A => 2,
+ READ_WIDTH_B => 2,
+ WRITE_WIDTH_A => 2,
+ WRITE_WIDTH_B => 2,
+ RAM_EXTENSION_A => "NONE",
+ RAM_EXTENSION_B => "NONE"
+ )
+ port map (
+ DBITERR => open,
+ ECCPARITY => open,
+ INJECTDBITERR => net_gnd0,
+ INJECTSBITERR => net_gnd0,
+ RDADDRECC => open,
+ SBITERR => open,
+ ADDRARDADDR => pgassign21,
+ CASCADEINA => net_gnd0,
+ CASCADEOUTA => open,
+ CLKARDCLK => BRAM_Clk_A,
+ DIADI => pgassign22,
+ DIPADIP => net_gnd4,
+ DOADO => pgassign23,
+ DOPADOP => open,
+ ENARDEN => BRAM_EN_A,
+ REGCEAREGCE => net_gnd0,
+ RSTRAMARSTRAM => BRAM_Rst_A,
+ RSTREGARSTREG => net_gnd0,
+ WEA => pgassign24,
+ ADDRBWRADDR => pgassign25,
+ CASCADEINB => net_gnd0,
+ CASCADEOUTB => open,
+ CLKBWRCLK => BRAM_Clk_B,
+ DIBDI => pgassign26,
+ DIPBDIP => net_gnd4,
+ DOBDO => pgassign27,
+ DOPBDOP => open,
+ ENBWREN => BRAM_EN_B,
+ REGCEB => net_gnd0,
+ RSTRAMB => BRAM_Rst_B,
+ RSTREGB => net_gnd0,
+ WEBWE => pgassign28
+ );
+
+ ramb36e1_3 : RAMB36E1
+ generic map (
+ WRITE_MODE_A => "WRITE_FIRST",
+ WRITE_MODE_B => "WRITE_FIRST",
+ INIT_FILE => "bram_block_0_combined_3.mem",
+ READ_WIDTH_A => 2,
+ READ_WIDTH_B => 2,
+ WRITE_WIDTH_A => 2,
+ WRITE_WIDTH_B => 2,
+ RAM_EXTENSION_A => "NONE",
+ RAM_EXTENSION_B => "NONE"
+ )
+ port map (
+ DBITERR => open,
+ ECCPARITY => open,
+ INJECTDBITERR => net_gnd0,
+ INJECTSBITERR => net_gnd0,
+ RDADDRECC => open,
+ SBITERR => open,
+ ADDRARDADDR => pgassign29,
+ CASCADEINA => net_gnd0,
+ CASCADEOUTA => open,
+ CLKARDCLK => BRAM_Clk_A,
+ DIADI => pgassign30,
+ DIPADIP => net_gnd4,
+ DOADO => pgassign31,
+ DOPADOP => open,
+ ENARDEN => BRAM_EN_A,
+ REGCEAREGCE => net_gnd0,
+ RSTRAMARSTRAM => BRAM_Rst_A,
+ RSTREGARSTREG => net_gnd0,
+ WEA => pgassign32,
+ ADDRBWRADDR => pgassign33,
+ CASCADEINB => net_gnd0,
+ CASCADEOUTB => open,
+ CLKBWRCLK => BRAM_Clk_B,
+ DIBDI => pgassign34,
+ DIPBDIP => net_gnd4,
+ DOBDO => pgassign35,
+ DOPBDOP => open,
+ ENBWREN => BRAM_EN_B,
+ REGCEB => net_gnd0,
+ RSTRAMB => BRAM_Rst_B,
+ RSTREGB => net_gnd0,
+ WEBWE => pgassign36
+ );
+
+ ramb36e1_4 : RAMB36E1
+ generic map (
+ WRITE_MODE_A => "WRITE_FIRST",
+ WRITE_MODE_B => "WRITE_FIRST",
+ INIT_FILE => "bram_block_0_combined_4.mem",
+ READ_WIDTH_A => 2,
+ READ_WIDTH_B => 2,
+ WRITE_WIDTH_A => 2,
+ WRITE_WIDTH_B => 2,
+ RAM_EXTENSION_A => "NONE",
+ RAM_EXTENSION_B => "NONE"
+ )
+ port map (
+ DBITERR => open,
+ ECCPARITY => open,
+ INJECTDBITERR => net_gnd0,
+ INJECTSBITERR => net_gnd0,
+ RDADDRECC => open,
+ SBITERR => open,
+ ADDRARDADDR => pgassign37,
+ CASCADEINA => net_gnd0,
+ CASCADEOUTA => open,
+ CLKARDCLK => BRAM_Clk_A,
+ DIADI => pgassign38,
+ DIPADIP => net_gnd4,
+ DOADO => pgassign39,
+ DOPADOP => open,
+ ENARDEN => BRAM_EN_A,
+ REGCEAREGCE => net_gnd0,
+ RSTRAMARSTRAM => BRAM_Rst_A,
+ RSTREGARSTREG => net_gnd0,
+ WEA => pgassign40,
+ ADDRBWRADDR => pgassign41,
+ CASCADEINB => net_gnd0,
+ CASCADEOUTB => open,
+ CLKBWRCLK => BRAM_Clk_B,
+ DIBDI => pgassign42,
+ DIPBDIP => net_gnd4,
+ DOBDO => pgassign43,
+ DOPBDOP => open,
+ ENBWREN => BRAM_EN_B,
+ REGCEB => net_gnd0,
+ RSTRAMB => BRAM_Rst_B,
+ RSTREGB => net_gnd0,
+ WEBWE => pgassign44
+ );
+
+ ramb36e1_5 : RAMB36E1
+ generic map (
+ WRITE_MODE_A => "WRITE_FIRST",
+ WRITE_MODE_B => "WRITE_FIRST",
+ INIT_FILE => "bram_block_0_combined_5.mem",
+ READ_WIDTH_A => 2,
+ READ_WIDTH_B => 2,
+ WRITE_WIDTH_A => 2,
+ WRITE_WIDTH_B => 2,
+ RAM_EXTENSION_A => "NONE",
+ RAM_EXTENSION_B => "NONE"
+ )
+ port map (
+ DBITERR => open,
+ ECCPARITY => open,
+ INJECTDBITERR => net_gnd0,
+ INJECTSBITERR => net_gnd0,
+ RDADDRECC => open,
+ SBITERR => open,
+ ADDRARDADDR => pgassign45,
+ CASCADEINA => net_gnd0,
+ CASCADEOUTA => open,
+ CLKARDCLK => BRAM_Clk_A,
+ DIADI => pgassign46,
+ DIPADIP => net_gnd4,
+ DOADO => pgassign47,
+ DOPADOP => open,
+ ENARDEN => BRAM_EN_A,
+ REGCEAREGCE => net_gnd0,
+ RSTRAMARSTRAM => BRAM_Rst_A,
+ RSTREGARSTREG => net_gnd0,
+ WEA => pgassign48,
+ ADDRBWRADDR => pgassign49,
+ CASCADEINB => net_gnd0,
+ CASCADEOUTB => open,
+ CLKBWRCLK => BRAM_Clk_B,
+ DIBDI => pgassign50,
+ DIPBDIP => net_gnd4,
+ DOBDO => pgassign51,
+ DOPBDOP => open,
+ ENBWREN => BRAM_EN_B,
+ REGCEB => net_gnd0,
+ RSTRAMB => BRAM_Rst_B,
+ RSTREGB => net_gnd0,
+ WEBWE => pgassign52
+ );
+
+ ramb36e1_6 : RAMB36E1
+ generic map (
+ WRITE_MODE_A => "WRITE_FIRST",
+ WRITE_MODE_B => "WRITE_FIRST",
+ INIT_FILE => "bram_block_0_combined_6.mem",
+ READ_WIDTH_A => 2,
+ READ_WIDTH_B => 2,
+ WRITE_WIDTH_A => 2,
+ WRITE_WIDTH_B => 2,
+ RAM_EXTENSION_A => "NONE",
+ RAM_EXTENSION_B => "NONE"
+ )
+ port map (
+ DBITERR => open,
+ ECCPARITY => open,
+ INJECTDBITERR => net_gnd0,
+ INJECTSBITERR => net_gnd0,
+ RDADDRECC => open,
+ SBITERR => open,
+ ADDRARDADDR => pgassign53,
+ CASCADEINA => net_gnd0,
+ CASCADEOUTA => open,
+ CLKARDCLK => BRAM_Clk_A,
+ DIADI => pgassign54,
+ DIPADIP => net_gnd4,
+ DOADO => pgassign55,
+ DOPADOP => open,
+ ENARDEN => BRAM_EN_A,
+ REGCEAREGCE => net_gnd0,
+ RSTRAMARSTRAM => BRAM_Rst_A,
+ RSTREGARSTREG => net_gnd0,
+ WEA => pgassign56,
+ ADDRBWRADDR => pgassign57,
+ CASCADEINB => net_gnd0,
+ CASCADEOUTB => open,
+ CLKBWRCLK => BRAM_Clk_B,
+ DIBDI => pgassign58,
+ DIPBDIP => net_gnd4,
+ DOBDO => pgassign59,
+ DOPBDOP => open,
+ ENBWREN => BRAM_EN_B,
+ REGCEB => net_gnd0,
+ RSTRAMB => BRAM_Rst_B,
+ RSTREGB => net_gnd0,
+ WEBWE => pgassign60
+ );
+
+ ramb36e1_7 : RAMB36E1
+ generic map (
+ WRITE_MODE_A => "WRITE_FIRST",
+ WRITE_MODE_B => "WRITE_FIRST",
+ INIT_FILE => "bram_block_0_combined_7.mem",
+ READ_WIDTH_A => 2,
+ READ_WIDTH_B => 2,
+ WRITE_WIDTH_A => 2,
+ WRITE_WIDTH_B => 2,
+ RAM_EXTENSION_A => "NONE",
+ RAM_EXTENSION_B => "NONE"
+ )
+ port map (
+ DBITERR => open,
+ ECCPARITY => open,
+ INJECTDBITERR => net_gnd0,
+ INJECTSBITERR => net_gnd0,
+ RDADDRECC => open,
+ SBITERR => open,
+ ADDRARDADDR => pgassign61,
+ CASCADEINA => net_gnd0,
+ CASCADEOUTA => open,
+ CLKARDCLK => BRAM_Clk_A,
+ DIADI => pgassign62,
+ DIPADIP => net_gnd4,
+ DOADO => pgassign63,
+ DOPADOP => open,
+ ENARDEN => BRAM_EN_A,
+ REGCEAREGCE => net_gnd0,
+ RSTRAMARSTRAM => BRAM_Rst_A,
+ RSTREGARSTREG => net_gnd0,
+ WEA => pgassign64,
+ ADDRBWRADDR => pgassign65,
+ CASCADEINB => net_gnd0,
+ CASCADEOUTB => open,
+ CLKBWRCLK => BRAM_Clk_B,
+ DIBDI => pgassign66,
+ DIPBDIP => net_gnd4,
+ DOBDO => pgassign67,
+ DOPBDOP => open,
+ ENBWREN => BRAM_EN_B,
+ REGCEB => net_gnd0,
+ RSTRAMB => BRAM_Rst_B,
+ RSTREGB => net_gnd0,
+ WEBWE => pgassign68
+ );
+
+ ramb36e1_8 : RAMB36E1
+ generic map (
+ WRITE_MODE_A => "WRITE_FIRST",
+ WRITE_MODE_B => "WRITE_FIRST",
+ INIT_FILE => "bram_block_0_combined_8.mem",
+ READ_WIDTH_A => 2,
+ READ_WIDTH_B => 2,
+ WRITE_WIDTH_A => 2,
+ WRITE_WIDTH_B => 2,
+ RAM_EXTENSION_A => "NONE",
+ RAM_EXTENSION_B => "NONE"
+ )
+ port map (
+ DBITERR => open,
+ ECCPARITY => open,
+ INJECTDBITERR => net_gnd0,
+ INJECTSBITERR => net_gnd0,
+ RDADDRECC => open,
+ SBITERR => open,
+ ADDRARDADDR => pgassign69,
+ CASCADEINA => net_gnd0,
+ CASCADEOUTA => open,
+ CLKARDCLK => BRAM_Clk_A,
+ DIADI => pgassign70,
+ DIPADIP => net_gnd4,
+ DOADO => pgassign71,
+ DOPADOP => open,
+ ENARDEN => BRAM_EN_A,
+ REGCEAREGCE => net_gnd0,
+ RSTRAMARSTRAM => BRAM_Rst_A,
+ RSTREGARSTREG => net_gnd0,
+ WEA => pgassign72,
+ ADDRBWRADDR => pgassign73,
+ CASCADEINB => net_gnd0,
+ CASCADEOUTB => open,
+ CLKBWRCLK => BRAM_Clk_B,
+ DIBDI => pgassign74,
+ DIPBDIP => net_gnd4,
+ DOBDO => pgassign75,
+ DOPBDOP => open,
+ ENBWREN => BRAM_EN_B,
+ REGCEB => net_gnd0,
+ RSTRAMB => BRAM_Rst_B,
+ RSTREGB => net_gnd0,
+ WEBWE => pgassign76
+ );
+
+ ramb36e1_9 : RAMB36E1
+ generic map (
+ WRITE_MODE_A => "WRITE_FIRST",
+ WRITE_MODE_B => "WRITE_FIRST",
+ INIT_FILE => "bram_block_0_combined_9.mem",
+ READ_WIDTH_A => 2,
+ READ_WIDTH_B => 2,
+ WRITE_WIDTH_A => 2,
+ WRITE_WIDTH_B => 2,
+ RAM_EXTENSION_A => "NONE",
+ RAM_EXTENSION_B => "NONE"
+ )
+ port map (
+ DBITERR => open,
+ ECCPARITY => open,
+ INJECTDBITERR => net_gnd0,
+ INJECTSBITERR => net_gnd0,
+ RDADDRECC => open,
+ SBITERR => open,
+ ADDRARDADDR => pgassign77,
+ CASCADEINA => net_gnd0,
+ CASCADEOUTA => open,
+ CLKARDCLK => BRAM_Clk_A,
+ DIADI => pgassign78,
+ DIPADIP => net_gnd4,
+ DOADO => pgassign79,
+ DOPADOP => open,
+ ENARDEN => BRAM_EN_A,
+ REGCEAREGCE => net_gnd0,
+ RSTRAMARSTRAM => BRAM_Rst_A,
+ RSTREGARSTREG => net_gnd0,
+ WEA => pgassign80,
+ ADDRBWRADDR => pgassign81,
+ CASCADEINB => net_gnd0,
+ CASCADEOUTB => open,
+ CLKBWRCLK => BRAM_Clk_B,
+ DIBDI => pgassign82,
+ DIPBDIP => net_gnd4,
+ DOBDO => pgassign83,
+ DOPBDOP => open,
+ ENBWREN => BRAM_EN_B,
+ REGCEB => net_gnd0,
+ RSTRAMB => BRAM_Rst_B,
+ RSTREGB => net_gnd0,
+ WEBWE => pgassign84
+ );
+
+ ramb36e1_10 : RAMB36E1
+ generic map (
+ WRITE_MODE_A => "WRITE_FIRST",
+ WRITE_MODE_B => "WRITE_FIRST",
+ INIT_FILE => "bram_block_0_combined_10.mem",
+ READ_WIDTH_A => 2,
+ READ_WIDTH_B => 2,
+ WRITE_WIDTH_A => 2,
+ WRITE_WIDTH_B => 2,
+ RAM_EXTENSION_A => "NONE",
+ RAM_EXTENSION_B => "NONE"
+ )
+ port map (
+ DBITERR => open,
+ ECCPARITY => open,
+ INJECTDBITERR => net_gnd0,
+ INJECTSBITERR => net_gnd0,
+ RDADDRECC => open,
+ SBITERR => open,
+ ADDRARDADDR => pgassign85,
+ CASCADEINA => net_gnd0,
+ CASCADEOUTA => open,
+ CLKARDCLK => BRAM_Clk_A,
+ DIADI => pgassign86,
+ DIPADIP => net_gnd4,
+ DOADO => pgassign87,
+ DOPADOP => open,
+ ENARDEN => BRAM_EN_A,
+ REGCEAREGCE => net_gnd0,
+ RSTRAMARSTRAM => BRAM_Rst_A,
+ RSTREGARSTREG => net_gnd0,
+ WEA => pgassign88,
+ ADDRBWRADDR => pgassign89,
+ CASCADEINB => net_gnd0,
+ CASCADEOUTB => open,
+ CLKBWRCLK => BRAM_Clk_B,
+ DIBDI => pgassign90,
+ DIPBDIP => net_gnd4,
+ DOBDO => pgassign91,
+ DOPBDOP => open,
+ ENBWREN => BRAM_EN_B,
+ REGCEB => net_gnd0,
+ RSTRAMB => BRAM_Rst_B,
+ RSTREGB => net_gnd0,
+ WEBWE => pgassign92
+ );
+
+ ramb36e1_11 : RAMB36E1
+ generic map (
+ WRITE_MODE_A => "WRITE_FIRST",
+ WRITE_MODE_B => "WRITE_FIRST",
+ INIT_FILE => "bram_block_0_combined_11.mem",
+ READ_WIDTH_A => 2,
+ READ_WIDTH_B => 2,
+ WRITE_WIDTH_A => 2,
+ WRITE_WIDTH_B => 2,
+ RAM_EXTENSION_A => "NONE",
+ RAM_EXTENSION_B => "NONE"
+ )
+ port map (
+ DBITERR => open,
+ ECCPARITY => open,
+ INJECTDBITERR => net_gnd0,
+ INJECTSBITERR => net_gnd0,
+ RDADDRECC => open,
+ SBITERR => open,
+ ADDRARDADDR => pgassign93,
+ CASCADEINA => net_gnd0,
+ CASCADEOUTA => open,
+ CLKARDCLK => BRAM_Clk_A,
+ DIADI => pgassign94,
+ DIPADIP => net_gnd4,
+ DOADO => pgassign95,
+ DOPADOP => open,
+ ENARDEN => BRAM_EN_A,
+ REGCEAREGCE => net_gnd0,
+ RSTRAMARSTRAM => BRAM_Rst_A,
+ RSTREGARSTREG => net_gnd0,
+ WEA => pgassign96,
+ ADDRBWRADDR => pgassign97,
+ CASCADEINB => net_gnd0,
+ CASCADEOUTB => open,
+ CLKBWRCLK => BRAM_Clk_B,
+ DIBDI => pgassign98,
+ DIPBDIP => net_gnd4,
+ DOBDO => pgassign99,
+ DOPBDOP => open,
+ ENBWREN => BRAM_EN_B,
+ REGCEB => net_gnd0,
+ RSTRAMB => BRAM_Rst_B,
+ RSTREGB => net_gnd0,
+ WEBWE => pgassign100
+ );
+
+ ramb36e1_12 : RAMB36E1
+ generic map (
+ WRITE_MODE_A => "WRITE_FIRST",
+ WRITE_MODE_B => "WRITE_FIRST",
+ INIT_FILE => "bram_block_0_combined_12.mem",
+ READ_WIDTH_A => 2,
+ READ_WIDTH_B => 2,
+ WRITE_WIDTH_A => 2,
+ WRITE_WIDTH_B => 2,
+ RAM_EXTENSION_A => "NONE",
+ RAM_EXTENSION_B => "NONE"
+ )
+ port map (
+ DBITERR => open,
+ ECCPARITY => open,
+ INJECTDBITERR => net_gnd0,
+ INJECTSBITERR => net_gnd0,
+ RDADDRECC => open,
+ SBITERR => open,
+ ADDRARDADDR => pgassign101,
+ CASCADEINA => net_gnd0,
+ CASCADEOUTA => open,
+ CLKARDCLK => BRAM_Clk_A,
+ DIADI => pgassign102,
+ DIPADIP => net_gnd4,
+ DOADO => pgassign103,
+ DOPADOP => open,
+ ENARDEN => BRAM_EN_A,
+ REGCEAREGCE => net_gnd0,
+ RSTRAMARSTRAM => BRAM_Rst_A,
+ RSTREGARSTREG => net_gnd0,
+ WEA => pgassign104,
+ ADDRBWRADDR => pgassign105,
+ CASCADEINB => net_gnd0,
+ CASCADEOUTB => open,
+ CLKBWRCLK => BRAM_Clk_B,
+ DIBDI => pgassign106,
+ DIPBDIP => net_gnd4,
+ DOBDO => pgassign107,
+ DOPBDOP => open,
+ ENBWREN => BRAM_EN_B,
+ REGCEB => net_gnd0,
+ RSTRAMB => BRAM_Rst_B,
+ RSTREGB => net_gnd0,
+ WEBWE => pgassign108
+ );
+
+ ramb36e1_13 : RAMB36E1
+ generic map (
+ WRITE_MODE_A => "WRITE_FIRST",
+ WRITE_MODE_B => "WRITE_FIRST",
+ INIT_FILE => "bram_block_0_combined_13.mem",
+ READ_WIDTH_A => 2,
+ READ_WIDTH_B => 2,
+ WRITE_WIDTH_A => 2,
+ WRITE_WIDTH_B => 2,
+ RAM_EXTENSION_A => "NONE",
+ RAM_EXTENSION_B => "NONE"
+ )
+ port map (
+ DBITERR => open,
+ ECCPARITY => open,
+ INJECTDBITERR => net_gnd0,
+ INJECTSBITERR => net_gnd0,
+ RDADDRECC => open,
+ SBITERR => open,
+ ADDRARDADDR => pgassign109,
+ CASCADEINA => net_gnd0,
+ CASCADEOUTA => open,
+ CLKARDCLK => BRAM_Clk_A,
+ DIADI => pgassign110,
+ DIPADIP => net_gnd4,
+ DOADO => pgassign111,
+ DOPADOP => open,
+ ENARDEN => BRAM_EN_A,
+ REGCEAREGCE => net_gnd0,
+ RSTRAMARSTRAM => BRAM_Rst_A,
+ RSTREGARSTREG => net_gnd0,
+ WEA => pgassign112,
+ ADDRBWRADDR => pgassign113,
+ CASCADEINB => net_gnd0,
+ CASCADEOUTB => open,
+ CLKBWRCLK => BRAM_Clk_B,
+ DIBDI => pgassign114,
+ DIPBDIP => net_gnd4,
+ DOBDO => pgassign115,
+ DOPBDOP => open,
+ ENBWREN => BRAM_EN_B,
+ REGCEB => net_gnd0,
+ RSTRAMB => BRAM_Rst_B,
+ RSTREGB => net_gnd0,
+ WEBWE => pgassign116
+ );
+
+ ramb36e1_14 : RAMB36E1
+ generic map (
+ WRITE_MODE_A => "WRITE_FIRST",
+ WRITE_MODE_B => "WRITE_FIRST",
+ INIT_FILE => "bram_block_0_combined_14.mem",
+ READ_WIDTH_A => 2,
+ READ_WIDTH_B => 2,
+ WRITE_WIDTH_A => 2,
+ WRITE_WIDTH_B => 2,
+ RAM_EXTENSION_A => "NONE",
+ RAM_EXTENSION_B => "NONE"
+ )
+ port map (
+ DBITERR => open,
+ ECCPARITY => open,
+ INJECTDBITERR => net_gnd0,
+ INJECTSBITERR => net_gnd0,
+ RDADDRECC => open,
+ SBITERR => open,
+ ADDRARDADDR => pgassign117,
+ CASCADEINA => net_gnd0,
+ CASCADEOUTA => open,
+ CLKARDCLK => BRAM_Clk_A,
+ DIADI => pgassign118,
+ DIPADIP => net_gnd4,
+ DOADO => pgassign119,
+ DOPADOP => open,
+ ENARDEN => BRAM_EN_A,
+ REGCEAREGCE => net_gnd0,
+ RSTRAMARSTRAM => BRAM_Rst_A,
+ RSTREGARSTREG => net_gnd0,
+ WEA => pgassign120,
+ ADDRBWRADDR => pgassign121,
+ CASCADEINB => net_gnd0,
+ CASCADEOUTB => open,
+ CLKBWRCLK => BRAM_Clk_B,
+ DIBDI => pgassign122,
+ DIPBDIP => net_gnd4,
+ DOBDO => pgassign123,
+ DOPBDOP => open,
+ ENBWREN => BRAM_EN_B,
+ REGCEB => net_gnd0,
+ RSTRAMB => BRAM_Rst_B,
+ RSTREGB => net_gnd0,
+ WEBWE => pgassign124
+ );
+
+ ramb36e1_15 : RAMB36E1
+ generic map (
+ WRITE_MODE_A => "WRITE_FIRST",
+ WRITE_MODE_B => "WRITE_FIRST",
+ INIT_FILE => "bram_block_0_combined_15.mem",
+ READ_WIDTH_A => 2,
+ READ_WIDTH_B => 2,
+ WRITE_WIDTH_A => 2,
+ WRITE_WIDTH_B => 2,
+ RAM_EXTENSION_A => "NONE",
+ RAM_EXTENSION_B => "NONE"
+ )
+ port map (
+ DBITERR => open,
+ ECCPARITY => open,
+ INJECTDBITERR => net_gnd0,
+ INJECTSBITERR => net_gnd0,
+ RDADDRECC => open,
+ SBITERR => open,
+ ADDRARDADDR => pgassign125,
+ CASCADEINA => net_gnd0,
+ CASCADEOUTA => open,
+ CLKARDCLK => BRAM_Clk_A,
+ DIADI => pgassign126,
+ DIPADIP => net_gnd4,
+ DOADO => pgassign127,
+ DOPADOP => open,
+ ENARDEN => BRAM_EN_A,
+ REGCEAREGCE => net_gnd0,
+ RSTRAMARSTRAM => BRAM_Rst_A,
+ RSTREGARSTREG => net_gnd0,
+ WEA => pgassign128,
+ ADDRBWRADDR => pgassign129,
+ CASCADEINB => net_gnd0,
+ CASCADEOUTB => open,
+ CLKBWRCLK => BRAM_Clk_B,
+ DIBDI => pgassign130,
+ DIPBDIP => net_gnd4,
+ DOBDO => pgassign131,
+ DOPBDOP => open,
+ ENBWREN => BRAM_EN_B,
+ REGCEB => net_gnd0,
+ RSTRAMB => BRAM_Rst_B,
+ RSTREGB => net_gnd0,
+ WEBWE => pgassign132
+ );
+
+end architecture STRUCTURE;
+
View
1,345 ...ms/ml605/hdl/elaborate/bram_block_1_elaborate_v1_00_a/hdl/vhdl/bram_block_1_elaborate.vhd
@@ -0,0 +1,1345 @@
+-------------------------------------------------------------------------------
+-- bram_block_1_elaborate.vhd
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+entity bram_block_1_elaborate is
+ generic (
+ C_MEMSIZE : integer;
+ C_PORT_DWIDTH : integer;
+ C_PORT_AWIDTH : integer;
+ C_NUM_WE : integer;
+ C_FAMILY : string
+ );
+ port (
+ BRAM_Rst_A : in std_logic;
+ BRAM_Clk_A : in std_logic;
+ BRAM_EN_A : in std_logic;
+ BRAM_WEN_A : in std_logic_vector(0 to C_NUM_WE-1);
+ BRAM_Addr_A : in std_logic_vector(0 to C_PORT_AWIDTH-1);
+ BRAM_Din_A : out std_logic_vector(0 to C_PORT_DWIDTH-1);
+ BRAM_Dout_A : in std_logic_vector(0 to C_PORT_DWIDTH-1);
+ BRAM_Rst_B : in std_logic;
+ BRAM_Clk_B : in std_logic;
+ BRAM_EN_B : in std_logic;
+ BRAM_WEN_B :