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added generated hdl files by XPS, added system.bit and system.ucf

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1 parent 0707f36 commit bde4e98d8a378a21c6d17ad183ebd2aada01e46a @farhanrahman committed Aug 6, 2012
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@@ -18,7 +18,7 @@ UROP
blockkdiagram/
synthesis/
project/base_systems/ml505/blockdiagram/*
-project/base_systems/ml505/implementation/*
+#project/base_systems/ml505/implementation/*
project/base_systems/ml506/implementation/*
project/base_systems/ml506/blockdiagram/*
@@ -0,0 +1,147 @@
+-------------------------------------------------------------------------------
+-- system_riffa_0_wrapper.vhd
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+library riffa_v1_00_a;
+use riffa_v1_00_a.all;
+
+entity system_riffa_0_wrapper is
+ port (
+ SYS_CLK : in std_logic;
+ SYS_RST : in std_logic;
+ INTERRUPT : out std_logic;
+ INTERRUPT_ERR : out std_logic;
+ INTERRUPT_ACK : in std_logic;
+ DOORBELL : in std_logic;
+ DOORBELL_ERR : in std_logic;
+ DOORBELL_LEN : in std_logic_vector(31 downto 0);
+ DOORBELL_ARG : in std_logic_vector(31 downto 0);
+ DMA_REQ : out std_logic;
+ DMA_REQ_ACK : in std_logic;
+ DMA_SRC : out std_logic_vector(31 downto 0);
+ DMA_DST : out std_logic_vector(31 downto 0);
+ DMA_LEN : out std_logic_vector(31 downto 0);
+ DMA_SIG : out std_logic;
+ DMA_DONE : in std_logic;
+ DMA_ERR : in std_logic;
+ BUF_REQ : out std_logic;
+ BUF_REQ_ACK : in std_logic;
+ BUF_REQ_ADDR : in std_logic_vector(31 downto 0);
+ BUF_REQ_SIZE : in std_logic_vector(4 downto 0);
+ BUF_REQ_RDY : in std_logic;
+ BUF_REQ_ERR : in std_logic;
+ BUF_REQD : in std_logic;
+ BUF_REQD_ADDR : out std_logic_vector(31 downto 0);
+ BUF_REQD_SIZE : out std_logic_vector(4 downto 0);
+ BUF_REQD_RDY : out std_logic;
+ BUF_REQD_ERR : out std_logic;
+ BRAM_Rst : out std_logic;
+ BRAM_Clk : out std_logic;
+ BRAM_EN : out std_logic;
+ BRAM_WEN : out std_logic_vector(0 to 3);
+ BRAM_Addr : out std_logic_vector(0 to 31);
+ BRAM_Din : in std_logic_vector(0 to 31);
+ BRAM_Dout : out std_logic_vector(0 to 31)
+ );
+end system_riffa_0_wrapper;
+
+architecture STRUCTURE of system_riffa_0_wrapper is
+
+ component riffa is
+ generic (
+ C_SIMPBUS_AWIDTH : INTEGER;
+ C_BRAM_ADDR : std_logic_vector;
+ C_BRAM_SIZE : INTEGER
+ );
+ port (
+ SYS_CLK : in std_logic;
+ SYS_RST : in std_logic;
+ INTERRUPT : out std_logic;
+ INTERRUPT_ERR : out std_logic;
+ INTERRUPT_ACK : in std_logic;
+ DOORBELL : in std_logic;
+ DOORBELL_ERR : in std_logic;
+ DOORBELL_LEN : in std_logic_vector((C_SIMPBUS_AWIDTH-1) downto 0);
+ DOORBELL_ARG : in std_logic_vector(31 downto 0);
+ DMA_REQ : out std_logic;
+ DMA_REQ_ACK : in std_logic;
+ DMA_SRC : out std_logic_vector((C_SIMPBUS_AWIDTH-1) downto 0);
+ DMA_DST : out std_logic_vector((C_SIMPBUS_AWIDTH-1) downto 0);
+ DMA_LEN : out std_logic_vector((C_SIMPBUS_AWIDTH-1) downto 0);
+ DMA_SIG : out std_logic;
+ DMA_DONE : in std_logic;
+ DMA_ERR : in std_logic;
+ BUF_REQ : out std_logic;
+ BUF_REQ_ACK : in std_logic;
+ BUF_REQ_ADDR : in std_logic_vector((C_SIMPBUS_AWIDTH-1) downto 0);
+ BUF_REQ_SIZE : in std_logic_vector(4 downto 0);
+ BUF_REQ_RDY : in std_logic;
+ BUF_REQ_ERR : in std_logic;
+ BUF_REQD : in std_logic;
+ BUF_REQD_ADDR : out std_logic_vector((C_SIMPBUS_AWIDTH-1) downto 0);
+ BUF_REQD_SIZE : out std_logic_vector(4 downto 0);
+ BUF_REQD_RDY : out std_logic;
+ BUF_REQD_ERR : out std_logic;
+ BRAM_Rst : out std_logic;
+ BRAM_Clk : out std_logic;
+ BRAM_EN : out std_logic;
+ BRAM_WEN : out std_logic_vector(0 to 3);
+ BRAM_Addr : out std_logic_vector(0 to 31);
+ BRAM_Din : in std_logic_vector(0 to 31);
+ BRAM_Dout : out std_logic_vector(0 to 31)
+ );
+ end component;
+
+begin
+
+ riffa_0 : riffa
+ generic map (
+ C_SIMPBUS_AWIDTH => 32,
+ C_BRAM_ADDR => X"90000000",
+ C_BRAM_SIZE => 65536
+ )
+ port map (
+ SYS_CLK => SYS_CLK,
+ SYS_RST => SYS_RST,
+ INTERRUPT => INTERRUPT,
+ INTERRUPT_ERR => INTERRUPT_ERR,
+ INTERRUPT_ACK => INTERRUPT_ACK,
+ DOORBELL => DOORBELL,
+ DOORBELL_ERR => DOORBELL_ERR,
+ DOORBELL_LEN => DOORBELL_LEN,
+ DOORBELL_ARG => DOORBELL_ARG,
+ DMA_REQ => DMA_REQ,
+ DMA_REQ_ACK => DMA_REQ_ACK,
+ DMA_SRC => DMA_SRC,
+ DMA_DST => DMA_DST,
+ DMA_LEN => DMA_LEN,
+ DMA_SIG => DMA_SIG,
+ DMA_DONE => DMA_DONE,
+ DMA_ERR => DMA_ERR,
+ BUF_REQ => BUF_REQ,
+ BUF_REQ_ACK => BUF_REQ_ACK,
+ BUF_REQ_ADDR => BUF_REQ_ADDR,
+ BUF_REQ_SIZE => BUF_REQ_SIZE,
+ BUF_REQ_RDY => BUF_REQ_RDY,
+ BUF_REQ_ERR => BUF_REQ_ERR,
+ BUF_REQD => BUF_REQD,
+ BUF_REQD_ADDR => BUF_REQD_ADDR,
+ BUF_REQD_SIZE => BUF_REQD_SIZE,
+ BUF_REQD_RDY => BUF_REQD_RDY,
+ BUF_REQD_ERR => BUF_REQD_ERR,
+ BRAM_Rst => BRAM_Rst,
+ BRAM_Clk => BRAM_Clk,
+ BRAM_EN => BRAM_EN,
+ BRAM_WEN => BRAM_WEN,
+ BRAM_Addr => BRAM_Addr,
+ BRAM_Din => BRAM_Din,
+ BRAM_Dout => BRAM_Dout
+ );
+
+end architecture STRUCTURE;
+
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@@ -0,0 +1,34 @@
+# XUPV5-LX110T Evaluation Platform
+Net fpga_0_PCIe_Bridge_RXN_pin LOC=AF1 | IOSTANDARD = LVDS_25;
+Net fpga_0_PCIe_Bridge_RXP_pin LOC=AE1 | IOSTANDARD = LVDS_25;
+Net fpga_0_PCIe_Bridge_TXN_pin LOC=AE2 | IOSTANDARD = LVDS_25;
+Net fpga_0_PCIe_Bridge_TXP_pin LOC=AD2 | IOSTANDARD = LVDS_25;
+Net fpga_0_clk_1_sys_clk_pin TNM_NET = sys_clk_pin;
+TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 100000 kHz;
+Net fpga_0_clk_1_sys_clk_pin TNM_NET = sys_clk_pin | LOC = AH15 | IOSTANDARD=LVCMOS33;
+Net fpga_0_rst_1_sys_rst_pin TIG;
+Net fpga_0_rst_1_sys_rst_pin LOC = E9 | IOSTANDARD=LVCMOS33 | PULLUP;
+Net fpga_0_PCIe_Diff_Clk_IBUF_DS_P_pin LOC=AF4 | IOSTANDARD = LVDS_25;
+Net fpga_0_PCIe_Diff_Clk_IBUF_DS_N_pin LOC=AF3 | IOSTANDARD = LVDS_25;
+
+###### PCIe_Bridge
+Net "pcie_bridge/*SPLB_Clk" TNM_NET = "SPLB_Clk";
+Net "pcie_bridge/*Bridge_Clk" TNM_NET = "Bridge_Clk";
+
+## Timing constraints between clock-domain boundaries
+#
+TIMESPEC "TS_PLB_PCIe" = FROM "SPLB_Clk" TO "Bridge_Clk" 8 ns datapathonly;
+TIMESPEC "TS_PCIe_PLB" = FROM "Bridge_Clk" TO "SPLB_Clk" 8 ns datapathonly;
+
+# BlockRAM placement
+INST "pcie_bridge/*pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst" LOC = RAMB36_X3Y11;
+INST "pcie_bridge/*pcie_mim_wrapper_i/bram_tl_rx/generate_tdp2[1].ram_tdp2_inst" LOC = RAMB36_X3Y9;
+INST "pcie_bridge/*pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst" LOC = RAMB36_X3Y10;
+INST "pcie_bridge/*pcie_mim_wrapper_i/bram_tl_rx/generate_tdp2[0].ram_tdp2_inst" LOC = RAMB36_X3Y8;
+INST "pcie_bridge/*pcie_mim_wrapper_i/bram_retry/generate_sdp.ram_sdp_inst" LOC = RAMB36_X3Y7;
+
+# Timing critical placements
+INST "pcie_bridge/*tx_bridge/shift_pipe1" LOC = "SLICE_X59Y56";
+INST "pcie_bridge/*arb_inst/completion_available" LOC = "SLICE_X58Y46";
+INST "pcie_bridge/*management_interface/mgmt_rdata_d1_3" LOC = "SLICE_X59Y45";
+

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