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farhanrahman edited this page Aug 7, 2012 · 8 revisions

Welcome to the riffa-interface wiki!

The aim of the project is to make it easy for a user to attach an IP core to the PCI express bus. This would allow the user to send data to an FPGA board and receive the computed data from the IP core back to the PC. The project uses the RIFFA library written by Matthew Jacobsen. The library provides the foundations for high bandwidth communication through the PCIe bus and provides communication and synchronisation capabilities on both software and hardware side. The example code provided by RIFFA expects the users' IP core to do some computation and send data back to the PC with a DMA transfer. This output of the IP core is however limited to the size of the BRAM and it is not expected to do multiple DMA transfers once the BRAM gets full and thus requires sending back data to the PC before control is given back to the core to resume outputting data onto the RAM.

The project is currently being developed and tested on the XUPV5-LX110T Development Platform and the operating system that is being used is Ubuntu 10.04 LTS which is currently one of the operating systems compatible with RIFFA.

Software/CAD tools dependencies

The project makes use of the following CAD tools and simulation softwares:

  • Xilinx Platform Studio :

    • Used for laying out the design and connection of ports between different IP cores provided by Xilinx and user defined cores.
    • Generating system.bit file (bitstream) that is used by Xilinx Impact to generate a SystemAce file that gets written onto a Compact Flash card attached to the development board. Once the computer boots up, the FPGA is programmed depending on the configuration bits settings. Look into the Creating SystemAce file with Impact and programming FPGA board section for more details.
    • Generation of post synthesis VHDL files
  • ModelSim PE and ModelSim SE (Student Edition):

    • Simulation and testing
  • Xilinx Impact :

    • Tool used to generate SystemAce file and JTAG boundary scan tests/detection of board.
  • Synplify Premier:

    • Optional but used to synthesis check and simulating synthesised VHDL code. Quite useful to quickly check for synthesis warnings/errors.

It is recommended to download [Xilinx ISE Design Suite version 14.1] (http://www.xilinx.com/support/download/index.htm) and the latest ModelSim PE/ModelSim SE.

Setting up workstation and FPGA development board

Before continuing on to the Riffa-Interface documentation follow the Setup Guide to setup the workstation:

Setup Guide

#Wiki Index

Use the following Wiki index to access different topics regarding usage of the Riffa-Interface.