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#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <string.h>
#include <errno.h>
#include <signal.h>
#include <fcntl.h>
#include <ctype.h>
#include <termios.h>
#include <sys/types.h>
#include <sys/mman.h>
struct Dm365Register
{
int address;
const char* module;
const char* name;
const char* description;
};
static struct Dm365Register registers[] =
{
{0x1c71000, "ISIF", "SYNCEN", "Synchronization Enable"},
{0x1c71004, "ISIF", "MODESET", "Mode Setup"},
{0x1c71008, "ISIF", "HDW", "HD pulse width"},
{0x1c7100c, "ISIF", "VDW", "VD pulse width"},
{0x1c71010, "ISIF", "PPLN", "Pixels per line"},
{0x1c71014, "ISIF", "LPFR", "Lines per frame"},
{0x1c71018, "ISIF", "SPH", "Start pixel horizontal"},
{0x1c7101c, "ISIF", "LNH", "Number of pixels in line"},
{0x1c71020, "ISIF", "SLV0", "Start line vertical - field 0"},
{0x1c71024, "ISIF", "SLV1", "Start line vertical - field 1"},
{0x1c71028, "ISIF", "LNV", "Number of lines vertical"},
{0x1c7102c, "ISIF", "CULH", "Culling - horizontal"},
{0x1c71030, "ISIF", "CULV", "Culling - vertical"},
{0x1c71034, "ISIF", "HSIZE", "Horizontal size"},
{0x1c71038, "ISIF", "SDOFST", "SDRAM Line Offset"},
{0x1c7103c, "ISIF", "CADU", "SDRAM Address - high"},
{0x1c71040, "ISIF", "CADL", "SDRAM Address - low"},
{0x1c7104c, "ISIF", "CCOLP", "CCD Color Pattern"},
{0x1c71050, "ISIF", "CRGAIN", "CCD Gain Adjustment - R/Ye"},
{0x1c71054, "ISIF", "CGRGAIN", "CCD Gain Adjustment - Gr/Cy"},
{0x1c71058, "ISIF", "CGBGAIN", "CCD Gain Adjustment - Gb/G"},
{0x1c7105c, "ISIF", "CBGAIN", "CCD Gain Adjustment - B/Mg"},
{0x1c71060, "ISIF", "COFSTA", "CCD Offset Adjustment"},
{0x1c71064, "ISIF", "FLSHCFG0", "FLSHCFG0"},
{0x1c71068, "ISIF", "FLSHCFG1", "FLSHCFG1"},
{0x1c7106c, "ISIF", "FLSHCFG2", "FLSHCFG2"},
{0x1c71070, "ISIF", "VDINT0", "VD Interrupt #0"},
{0x1c71074, "ISIF", "VDINT1", "VD Interrupt #1"},
{0x1c71078, "ISIF", "VDINT2", "VD Interrupt #2"},
{0x1c71080, "ISIF", "CGAMMAWD", "Gamma Correction settings"},
{0x1c71084, "ISIF", "REC656IF", "CCIR 656 Control"},
{0x1c71088, "ISIF", "CCDCFG", "CCD Configuration"},
{0x1c7108c, "ISIF", "DFCCTL", "Defect Correction - Control"},
{0x1c71090, "ISIF", "VDFSATLV", "Defect Correction - Vertical Saturation Level"},
{0x1c71094, "ISIF", "DFCMEMCTL", "Defect Correction - Memory Control"},
{0x1c71098, "ISIF", "DFCMEM0", "Defect Correction - Set V Position"},
{0x1c7109c, "ISIF", "DFCMEM1", "Defect Correction - Set H Position"},
{0x1c710a0, "ISIF", "DFCMEM2", "Defect Correction - Set SUB1"},
{0x1c710a4, "ISIF", "DFCMEM3", "Defect Correction - Set SUB2"},
{0x1c710a8, "ISIF", "DFCMEM4", "Defect Correction - Set SUB3"},
{0x1c710ac, "ISIF", "CLAMPCFG", "Black Clamp configuration"},
{0x1c710b0, "ISIF", "CLDCOFST", "DC offset for Black Clamp"},
{0x1c710b4, "ISIF", "CLSV", "Black Clamp Start position"},
{0x1c710b8, "ISIF", "CLHWIN0", "Horizontal Black Clamp configuration"},
{0x1c710bc, "ISIF", "CLHWIN1", "Horizontal Black Clamp configuration"},
{0x1c710c0, "ISIF", "CLHWIN2", "Horizontal Black Clamp configuration"},
{0x1c710c4, "ISIF", "CLVRV", "Vertical Black Clamp configuration"},
{0x1c710c8, "ISIF", "CLVWIN0", "Vertical Black Clamp configuration"},
{0x1c710cc, "ISIF", "CLVWIN1", "Vertical Black Clamp configuration"},
{0x1c710d0, "ISIF", "CLVWIN2", "Vertical Black Clamp configuration"},
{0x1c710d4, "ISIF", "CLVWIN3", "Vertical Black Clamp configuration"},
{0x1c7111c, "ISIF", "FMTSPH", "CCD Formatter - Start pixel horizontal"},
{0x1c71120, "ISIF", "FMTLNH", "CCD Formatter - number of pixels"},
{0x1c71124, "ISIF", "FMTSLV", "CCD Formatter - start line vertical"},
{0x1c71128, "ISIF", "FMTLNV", "CCD Formatter - number of lines"},
{0x1c7112c, "ISIF", "FMTRLEN", "CCD Formatter - Read out line length"},
{0x1c71130, "ISIF", "FMTHCNT", "CCD Formatter - HD cycles"},
{0x1c711a4, "ISIF", "CSCCTL", "Color Space Converter Enable"},
{0x1c711a8, "ISIF", "CSCM0", "Color Space Converter - Coefficients #0"},
{0x1c711ac, "ISIF", "CSCM1", "Color Space Converter - Coefficients #1"},
{0x1c711b0, "ISIF", "CSCM2", "Color Space Converter - Coefficients #2"},
{0x1c711b4, "ISIF", "CSCM3", "Color Space Converter - Coefficients #3"},
{0x1c711b8, "ISIF", "CSCM4", "Color Space Converter - Coefficients #4"},
{0x1c711bc, "ISIF", "CSCM5", "Color Space Converter - Coefficients #5"},
{0x1c711c0, "ISIF", "CSCM6", "Color Space Converter - Coefficients #6"},
{0x1c711c4, "ISIF", "CSCM7", "Color Space Converter - Coefficients #7"},
{0x1c71200, "IPIPEIF", "ENABLE", "IPIPE I/F Enable"},
{0x1c71204, "IPIPEIF", "CFG1", "IPIPE I/F Configuration 1"},
{0x1c71208, "IPIPEIF", "PPLN", "IPIPE I/F Interval of HD / Start pixel in HD"},
{0x1c7120c, "IPIPEIF", "LPFR", "IPIPE I/F Interval of VD / Start line in VD"},
{0x1c71210, "IPIPEIF", "HNUM", "IPIPE I/F Number of valid pixels per line"},
{0x1c71214, "IPIPEIF", "VNUM", "IPIPE I/F Number of valid lines per frame"},
{0x1c71218, "IPIPEIF", "ADDRU", "IPIPE I/F Memory address (upper)"},
{0x1c7121c, "IPIPEIF", "ADDRL", "IPIPE I/F Memory address (lower)"},
{0x1c71220, "IPIPEIF", "ADOFS", "IPIPE I/F Address offset of each line"},
{0x1c71224, "IPIPEIF", "RSZ", "IPIPE I/F Horizontal resizing parameter"},
{0x1c71228, "IPIPEIF", "GAIN", "IPIPE I/F Gain parameter"},
{0x1c7122c, "IPIPEIF", "DPCM", "IPIPE I/F DPCM configuration"},
{0x1c71230, "IPIPEIF", "CFG2", "IPIPE I/F Configuration 2"},
{0x1c71234, "IPIPEIF", "INIRSZ", "IPIPE I/F Initial position of resize"},
{0x1c71238, "IPIPEIF", "OCLIP", "IPIPE I/F Output clipping value"},
{0x1c7123c, "IPIPEIF", "DTUDF", "IPIPE I/F Data underflow error status"},
{0x1c71240, "IPIPEIF", "CLKDIV", "IPIPE I/F Clock rate configuration"},
{0x1c71244, "IPIPEIF", "DPC1", "IPIPE I/F Defect pixel correction"},
{0x1c71248, "IPIPEIF", "DPC2", "IPIPE I/F Defect pixel correction"},
{0x1c71254, "IPIPEIF", "RSZ3A", "IPIPE I/F Horizontal resizing parameter for H3A"},
{0x1c71258, "IPIPEIF", "INIRSZ3A", "IPIPE I/F Initial position of resize for H3A"},
{0x1c70800, "IPIPE", "SRC_EN", "IPIPE Enable"},
{0x1c70804, "IPIPE", "SRC_MODE", "One Shot Mode"},
{0x1c70808, "IPIPE", "SRC_FMT", "Input/Output Data Paths"},
{0x1c7080c, "IPIPE", "SRC_COL", "Color Pattern"},
{0x1c70810, "IPIPE", "SRC_VPS", "Vertical Start Position"},
{0x1c70814, "IPIPE", "SRC_VSZ", "Vertical Processing Size"},
{0x1c70818, "IPIPE", "SRC_HPS", "Horizontal Start Position"},
{0x1c7081c, "IPIPE", "SRC_HSZ", "Horizontal Processing Size"},
{0x1c70824, "IPIPE", "DMA_STA", "Status Flags (Reserved)"},
{0x1c70828, "IPIPE", "GCK_MMR", "MMR Gated Clock Control"},
{0x1c7082c, "IPIPE", "GCK_PIX", "PCLK Gated Clock Control"},
{0x1c70834, "IPIPE", "DPC_LUT_EN", "LUTDPC (=LUT Defect Pixel Correction): Enable"},
{0x1c70838, "IPIPE", "DPC_LUT_SEL", "LUTDPC: Processing Mode Selection"},
{0x1c7083c, "IPIPE", "DPC_LUT_ADR", "LUTDPC: Start Address in LUT"},
{0x1c70840, "IPIPE", "DPC_LUT_SIZ", "LUTDPC: Number of available entries in LUT"},
{0x1c709d0, "IPIPE", "WB2_OFT_R", "WB2 (=White Balance): Offset"},
{0x1c709d4, "IPIPE", "WB2_OFT_GR", "WB2: Offset"},
{0x1c709d8, "IPIPE", "WB2_OFT_GB", "WB2: Offset"},
{0x1c709dc, "IPIPE", "WB2_OFT_B", "WB2: Offset"},
{0x1c709e0, "IPIPE", "WB2_WGN_R", "WB2: Gain"},
{0x1c709e4, "IPIPE", "WB2_WGN_GR", "WB2: Gain"},
{0x1c709e8, "IPIPE", "WB2_WGN_GB", "WB2: Gain"},
{0x1c709ec, "IPIPE", "WB2_WGN_B", "WB2: Gain"},
{0x1c70a2c, "IPIPE", "RGB1_MUL_RR", "RGB1 (=1st RGB2RGB conv): Matrix Coefficient"},
{0x1c70a30, "IPIPE", "RGB1_MUL_GR", "RGB1: Matrix Coefficient"},
{0x1c70a34, "IPIPE", "RGB1_MUL_BR", "RGB1: Matrix Coefficient"},
{0x1c70a38, "IPIPE", "RGB1_MUL_RG", "RGB1: Matrix Coefficient"},
{0x1c70a3c, "IPIPE", "RGB1_MUL_GG", "RGB1: Matrix Coefficient"},
{0x1c70a40, "IPIPE", "RGB1_MUL_BG", "RGB1: Matrix Coefficient"},
{0x1c70a44, "IPIPE", "RGB1_MUL_RB", "RGB1: Matrix Coefficient"},
{0x1c70a48, "IPIPE", "RGB1_MUL_GB", "RGB1: Matrix Coefficient"},
{0x1c70a4c, "IPIPE", "RGB1_MUL_BB", "RGB1: Matrix Coefficient"},
{0x1c70a50, "IPIPE", "RGB1_OFT_OR", "RGB1: Offset"},
{0x1c70a54, "IPIPE", "RGB1_OFT_OG", "RGB1: Offset"},
{0x1c70a58, "IPIPE", "RGB1_OFT_OB", "RGB1: Offset"},
{0x1c70a5c, "IPIPE", "GMM_CFG", "Gamma Correction Configuration"},
{0x1c70a94, "IPIPE", "YUV_ADJ", "YUV (RGB2YCbCr conv): Luminance Adjustment (Contrast and"},
{0x1c70a98, "IPIPE", "YUV_MUL_RY", "YUV: Matrix Coefficient"},
{0x1c70a9c, "IPIPE", "YUV_MUL_GY", "YUV: Matrix Coefficient"},
{0x1c70aa0, "IPIPE", "YUV_MUL_BY", "YUV: Matrix Coefficient"},
{0x1c70aa4, "IPIPE", "YUV_MUL_RCB", "YUV: Matrix Coefficient"},
{0x1c70aa8, "IPIPE", "YUV_MUL_GCB", "YUV: Matrix Coefficient"},
{0x1c70aac, "IPIPE", "YUV_MUL_BCB", "YUV: Matrix Coefficient"},
{0x1c70ab0, "IPIPE", "YUV_MUL_RCR", "YUV: Matrix Coefficient"},
{0x1c70ab4, "IPIPE", "YUV_MUL_GCR", "YUV: Matrix Coefficient"},
{0x1c70ab8, "IPIPE", "YUV_MUL_BCR", "YUV: Matrix Coefficient"},
{0x1c70abc, "IPIPE", "YUV_OFT_Y", "YUV: Offset"},
{0x1c70ac0, "IPIPE", "YUV_OFT_CB", "YUV: Offset"},
{0x1c70ac4, "IPIPE", "YUV_OFT_CR", "YUV: Offset"},
{0x1c70ac8, "IPIPE", "YUV_PHS", "Chrominance Position (for 422 Down Sampler)"},
{0x1c70ad4, "IPIPE", "YEE_EN", "YEE (=Edge Enhancer): Enable"},
{0x1c70ad8, "IPIPE", "YEE_TYP", "YEE: Method Selection"},
{0x1c70fdc, "IPIPE", "YEE_SHF", "YEE: HPF Shift Length"},
{0x1c70ae0, "IPIPE", "YEE_MUL_00", "YEE: HPF Coefficient"},
{0x1c70ae4, "IPIPE", "YEE_MUL_01", "YEE: HPF Coefficient"},
{0x1c70ae8, "IPIPE", "YEE_MUL_02", "YEE: HPF Coefficient"},
{0x1c70aec, "IPIPE", "YEE_MUL_10", "YEE: HPF Coefficient"},
{0x1c70af0, "IPIPE", "YEE_MUL_11", "YEE: HPF Coefficient"},
{0x1c70af4, "IPIPE", "YEE_MUL_12", "YEE: HPF Coefficient"},
{0x1c70af8, "IPIPE", "YEE_MUL_20", "YEE: HPF Coefficient"},
{0x1c70afc, "IPIPE", "YEE_MUL_21", "YEE: HPF Coefficient"},
{0x1c70b00, "IPIPE", "YEE_MUL_22", "YEE: HPF Coefficient"},
{0x1c70b04, "IPIPE", "YEE_THR", "YEE: Lower Threshold before Referring to LUT"},
{0x1c70b08, "IPIPE", "YEE_E_GAN", "YEE: Edge Sharpener Gain"},
{0x1c70b0c, "IPIPE", "YEE_E_THR_1", "YEE: Edge Sharpener HP Value Lower Threshold"},
{0x1c70b10, "IPIPE", "YEE_E_THR_2", "YEE: Edge Sharpener HP Value Upper Limit"},
{0x1c70b14, "IPIPE", "YEE_G_GAN", "YEE: Edge Sharpener Gain on Gradient"},
{0x1c70b18, "IPIPE", "YEE_G_OFT", "YEE: Edge Sharpener Offset on Gradient"},
{0x1c70b80, "IPIPE", "BOX_EN", "BOX (=Boxcar) Enable"},
{0x1c70b84, "IPIPE", "BOX_MODE", "BOX: One Shot Mode"},
{0x1c70b88, "IPIPE", "BOX_TYP", "BOX: Block Size (16x16 or 8x8)"},
{0x1c70b8c, "IPIPE", "BOX_SHF", "BOX: Down Shift Value of Input"},
{0x1c70b90, "IPIPE", "BOX_SDR_SAD_H", "BOX: SDRAM Address MSB"},
{0x1c70b94, "IPIPE", "BOX_SDR_SAD_L", "BOX: SDRAM Address LSB"},
{0x1c70b9c, "IPIPE", "HST_EN", "HST (=Histogram): Enable"},
{0x1c70ba0, "IPIPE", "HST_MODE", "HST: One Shot Mode"},
{0x1c70ba4, "IPIPE", "HST_SEL", "HST: Source Select"},
{0x1c70ba8, "IPIPE", "HST_PARA", "HST: Parameters Select"},
{0x1c70bac, "IPIPE", "HST_0_VPS", "HST: Vertical Start Position"},
{0x1c70bb0, "IPIPE", "HST_0_VSZ", "HST: Vertical Size"},
{0x1c70bb4, "IPIPE", "HST_0_HPS", "HST: Horizontal Start Position"},
{0x1c70bb8, "IPIPE", "HST_0_HSZ", "HST: Horizontal Size"},
{0x1c70bbc, "IPIPE", "HST_1_VPS", "HST: Vertical Start Position"},
{0x1c70bc0, "IPIPE", "HST_1_VSZ", "HST: Vertical Size"},
{0x1c70bc4, "IPIPE", "HST_1_HPS", "HST: Horizontal Start Position"},
{0x1c70bc8, "IPIPE", "HST_1_HSZ", "HST: Horizontal Size"},
{0x1c70bcc, "IPIPE", "HST_2_VPS", "HST: Vertical Start Position"},
{0x1c70bd0, "IPIPE", "HST_2_VSZ", "HST: Vertical Size"},
{0x1c70bd4, "IPIPE", "HST_2_HPS", "HST: Horizontal Start Position"},
{0x1c70bd8, "IPIPE", "HST_2_HSZ", "HST: Horizontal Size"},
{0x1c70bdc, "IPIPE", "HST_3_VPS", "HST: Vertical Start Position"},
{0x1c70be0, "IPIPE", "HST_3_VSZ", "HST: Vertical Size"},
{0x1c70be4, "IPIPE", "HST_3_HPS", "HST: Horizontal Start Position"},
{0x1c70be8, "IPIPE", "HST_3_HSZ", "HST: Horizontal Size"},
{0x1c70bec, "IPIPE", "HST_TBL", "HST: Table Select"},
{0x1c70bf0, "IPIPE", "HST_MUL_R", "HST: Matrix Coefficient"},
{0x1c70bf4, "IPIPE", "HST_MUL_GR", "HST: Matrix Coefficient"},
{0x1c70bf8, "IPIPE", "HST_MUL_GB", "HST: Matrix Coefficient"},
{0x1c70bfc, "IPIPE", "HST_MUL_B", "HST: Matrix Coefficient"},
{0x1c70400, "RSZ", "SRC_EN", "RSZ Enable"},
{0x1c70404, "RSZ", "SRC_MODE", "One Shot Mode"},
{0x1c70408, "RSZ", "SRC_FMT0", "Input Data Paths"},
{0x1c7040c, "RSZ", "SRC_FMT1", "Source Image Format"},
{0x1c70410, "RSZ", "SRC_VPS", "Vertical Start Position"},
{0x1c70414, "RSZ", "SRC_VSZ", "Vertical Processing Size"},
{0x1c70418, "RSZ", "SRC_HPS", "Horizontal Start Position"},
{0x1c7041c, "RSZ", "SRC_HSZ", "Horizontal Processing Size"},
{0x1c70420, "RSZ", "DMA_RZA", "SDRAM Request Minimum Interval for RZA"},
{0x1c70424, "RSZ", "DMA_RZB", "SDRAM Request Minimum Interval for RZB"},
{0x1c70428, "RSZ", "DMA_STA", "Status of Resizer (Reserved)"},
{0x1c7042c, "RSZ", "GCK_MMR", "MMR Gated Clock Control"},
{0x1c70434, "RSZ", "GCK_SDR", "SDR Gated Clock Control"},
{0x1c70438, "RSZ", "IRQ_RZA", "Interval of RZA circular IRQ"},
{0x1c7043c, "RSZ", "IRQ_RZB", "Interval of RZB circular IRQ"},
{0x1c70440, "RSZ", "YUV_Y_MIN", "Saturation (Luminance Minimum)"},
{0x1c70444, "RSZ", "YUV_Y_MAX", "Saturation (Luminance Maximum)"},
{0x1c70448, "RSZ", "YUV_C_MIN", "Saturation (Chrominance Minimum)"},
{0x1c7044c, "RSZ", "YUV_C_MAX", "Saturation (Chrominance Maximum)"},
{0x1c70450, "RSZ", "YUV_PHS", "Chrominance Position"},
{0x1c70454, "RSZ", "SEQ", "Processing Mode"},
{0x1c70458, "RSZ", "RZA_EN", "RZA (Resizer Channel A): Enable"},
{0x1c7045c, "RSZ", "RZA_MODE", "RZA: One Shot Mode"},
{0x1c70460, "RSZ", "RZA_420", "RZA: Output Format"},
{0x1c70464, "RSZ", "RZA_I_VPS", "RZA: Vertical Start Position of the Input"},
{0x1c70468, "RSZ", "RZA_I_HPS", "RZA: Horizontal Start Position of the Input"},
{0x1c7046c, "RSZ", "RZA_O_VSZ", "RZA: Vertical Size of the Output"},
{0x1c70470, "RSZ", "RZA_O_HSZ", "RZA: Horizontal Size of the Output"},
{0x1c70474, "RSZ", "RZA_V_PHS_Y", "RZA: Initial Phase of Vertical Resizing Process for Luminance"},
{0x1c70478, "RSZ", "RZA_V_PHS_C", "RZA: Initial Phase of Vertical Resizing Process for Chrominance"},
{0x1c7047c, "RSZ", "RZA_V_DIF", "RZA: Vertical Resize Parameter"},
{0x1c70480, "RSZ", "RZA_V_TYP", "RZA: Interpolation method for Vertical Rescaling"},
{0x1c70484, "RSZ", "RZA_V_LPF", "RZA: Vertical LPF Intensity"},
{0x1c70488, "RSZ", "RZA_H_PHS", "RZA: Initial Phase of Horizontal Resizing Process"},
{0x1c7048c, "RSZ", "RZA_H_PHS_ADJ", "RZA: Additional Initial Phase of Vertical Resizing Process for Luminance"},
{0x1c70490, "RSZ", "RZA_H_DIF", "RZA: Horizontal Resize Parameter"},
{0x1c70494, "RSZ", "RZA_H_TYP", "RZA: Interpolation method for Horizontal Rescaling"},
{0x1c70498, "RSZ", "RZA_H_LPF", "RZA: Horizontal LPF Intensity"},
{0x1c7049c, "RSZ", "RZA_DWN_EN", "RZA: Down Scale Mode Enable"},
{0x1c704a0, "RSZ", "RZA_DWN_AV", "RZA: Down Scale Mode Averaging Size"},
{0x1c704a4, "RSZ", "RZA_RGB_EN", "RZA: RGB Output Enable"},
{0x1c704a8, "RSZ", "RZA_RGB_TYP", "RZA: RGB Output Bit Mode"},
{0x1c704ac, "RSZ", "RZA_RGB_BLD", "RZA: YC422 to YC444 conversion method"},
{0x1c704b0, "RSZ", "RZA_SDR_Y_BAD_H", "RZA: SDRAM Base Address MSB"},
{0x1c704b4, "RSZ", "RZA_SDR_Y_BAD_L", "RZA: SDRAM Base Address LSB"},
{0x1c704b8, "RSZ", "RZA_SDR_Y_SAD_H", "RZA: SDRAM Start Address MSB"},
{0x1c704bc, "RSZ", "RZA_SDR_Y_SAD_L", "RZA: SDRAM Start Address LSB"},
{0x1c704c0, "RSZ", "RZA_SDR_Y_OFT", "RZA: SDRAM Line Offset"},
{0x1c704c4, "RSZ", "RZA_SDR_Y_PTR_S", "RZA: Start Line of SDRAM Pointer"},
{0x1c704c8, "RSZ", "RZA_SDR_Y_PTR_E", "RZA: End line of SDRAM Pointer"},
{0x1c704cc, "RSZ", "RZA_SDR_C_BAD_H", "RZA: SDRAM Base Address MSB (for 420 Chroma)"},
{0x1c704d0, "RSZ", "RZA_SDR_C_BAD_L", "RZA: SDRAM Base Address LSB (for 420 Chroma)"},
{0x1c704d4, "RSZ", "RZA_SDR_C_SAD_H", "RZA: SDRAM Start Address MSB (for 420 Chroma)"},
{0x1c704d8, "RSZ", "RZA_SDR_C_SAD_L", "RZA: SDRAM Start Address LSB (for 420 Chroma)"},
{0x1c704dc, "RSZ", "RZA_SDR_C_OFT", "RZA: SDRAM Line Offset (for 420 Chroma)"},
{0x1c704e0, "RSZ", "RZA_SDR_C_PTR_S", "RZA: Start Line of SDRAM Pointer (for 420 Chroma)"},
{0x1c704e4, "RSZ", "RZA_SDR_C_PTR_E", "RZA: End line of SDRAM Pointer (for 420 Chroma)"},
{0x1c704e8, "RSZ", "RZB_EN", "RZB (Resizer Channel B): Enable"},
{0x1c704ec, "RSZ", "RZB_MODE", "RZB: One Shot Mode"},
{0x1c704f0, "RSZ", "RZB_420", "RZB: Output Format"},
{0x1c704f4, "RSZ", "RZB_I_VPS", "RZB: Vertical Start Position of the Input"},
{0x1c704f8, "RSZ", "RZB_I_HPS", "RZB: Horizontal Start Position of the Input"},
{0x1c704fc, "RSZ", "RZB_O_VSZ", "RZB: Vertical Size of the Output"},
{0x1c70500, "RSZ", "RZB_O_HSZ", "RZB: Horizontal Size of the Output"},
{0x1c70504, "RSZ", "RZB_V_PHS_Y", "RZB: Initial Phase of Vertical Resizing Process for Luminance"},
{0x1c70508, "RSZ", "RZB_V_PHS_C", "RZB: Initial Phase of Vertical Resizing Process for Chrominance"},
{0x1c7050c, "RSZ", "RZB_V_DIF", "RZB: Vertical Resize Parameter"},
{0x1c70510, "RSZ", "RZB_V_TYP", "RZB: Interpolation method for Vertical Rescaling"},
{0x1c70514, "RSZ", "RZB_V_LPF", "RZB: Vertical LPF Intensity"},
{0x1c70518, "RSZ", "RZB_H_PHS", "RZB: Initial Phase of Horizontal Resizing Process"},
{0x1c7051c, "RSZ", "RZB_H_PHS_ADJ", "RZB: Additional Initial Phase of Horizontal Resizing Process for Luminance"},
{0x1c70520, "RSZ", "RZB_H_DIF", "RZB: Horizontal Resize Parameter"},
{0x1c70524, "RSZ", "RZB_H_TYP", "RZB: Interpolation method for Horizontal Rescaling"},
{0x1c70528, "RSZ", "RZB_H_LPF", "RZB: Horizontal LPF Intensity"},
{0x1c7052c, "RSZ", "RZB_DWN_EN", "RZB: Down Scale Mode Enable"},
{0x1c70530, "RSZ", "RZB_DWN_AV", "RZB: Down Scale Mode Averaging Size"},
{0x1c70534, "RSZ", "RZB_RGB_EN", "RZB: RGB Output Enable"},
{0x1c70538, "RSZ", "RZB_RGB_TYP", "RZB: RGB Output Bit Mode"},
{0x1c7053c, "RSZ", "RZB_RGB_BLD", "RZB: YC422 to YC444 conversion method"},
{0x1c70540, "RSZ", "RZB_SDR_Y_BAD_H", "RZB: SDRAM Base Address MSB"},
{0x1c70544, "RSZ", "RZB_SDR_Y_BAD_L", "RZB: SDRAM Base Address LSB"},
{0x1c70548, "RSZ", "RZB_SDR_Y_SAD_H", "RZB: SDRAM Start Address MSB"},
{0x1c7054c, "RSZ", "RZB_SDR_Y_SAD_L", "RZB: SDRAM Start Address LSB"},
{0x1c70550, "RSZ", "RZB_SDR_Y_OFT", "RZB: SDRAM Line Offset"},
{0x1c70554, "RSZ", "RZB_SDR_Y_PTR_S", "RZB: Start Line of SDRAM Pointer"},
{0x1c70558, "RSZ", "RZB_SDR_Y_PTR_E", "RZB: End line of SDRAM Pointer"},
{0x1c7055c, "RSZ", "RZB_SDR_C_BAD_H", "RZB: SDRAM Base Address MSB (for 420 Chroma)"},
{0x1c70560, "RSZ", "RZB_SDR_C_BAD_L", "RZB: SDRAM Base Address LSB (for 420 Chroma)"},
{0x1c70564, "RSZ", "RZB_SDR_C_SAD_H", "RZB: SDRAM Start Address MSB (for 420 Chroma)"},
{0x1c70568, "RSZ", "RZB_SDR_C_SAD_L", "RZB: SDRAM Start Address LSB (for 420 Chroma)"},
{0x1c7056c, "RSZ", "RZB_SDR_C_OFT", "RZB: SDRAM Line Offset (for 420 Chroma)"},
{0x1c70570, "RSZ", "RZB_SDR_C_PTR_S", "RZB: Start Line of SDRAM Pointer (for 420 Chroma)"},
{0x1c70574, "RSZ", "RZB_SDR_C_PTR_E", "RZB: End line of SDRAM Pointer (for 420 Chroma)"},
{0x1c71400, "H3A", "PID", "Peripheral Revision and Class Information"},
{0x1c71404, "H3A", "PCR", "Peripheral Control Register"},
{0x1c71408, "H3A", "AFPAX1", "Setup for the AF Engine Paxel Configuration"},
{0x1c7140c, "H3A", "AFPAX2", "Setup for the AF Engine Paxel Configuration"},
{0x1c71410, "H3A", "AFPAXSTART", "Start Position for AF Engine Paxels"},
{0x1c71418, "H3A", "AFBUFST", "SDRAM/DDRAM Start address for AF Engine"},
{0x1c7144c, "H3A", "AEWWIN1", "Configuration for AE/AWB Windows"},
{0x1c71450, "H3A", "AEWINSTART", "Start position for AE/AWB Windows"},
{0x1c71454, "H3A", "AEWINBLK", "Start position and height for black line of AE/AWB Windows"},
{0x1c71458, "H3A", "AEWSUBWIN", "Configuration for subsample data in AE/AWB window"},
{0x1c7145c, "H3A", "AEWBUFST", "SDRAM/DDRAM Start address for AE/AWB Engine Output Data"},
{0x1c71460, "H3A", "RSDR_ADDR", "AE/AWB Engine Configuration"},
{0x1c71464, "H3A", "LINE_START", "Line start position for ISIF interface"},
{0x1c71468, "H3A", "VFV_CFG1", "AF Vertical Focus Configuration 1 Register"},
{0x1c7146c, "H3A", "VFV_CFG2", "AF Vertical Focus Configuration 2 Register"},
{0x1c71470, "H3A", "VFV_CFG3", "AF Vertical Focus Configuration 3 Register"},
{0x1c71474, "H3A", "VFV_CFG4", "AF Vertical Focus Configuration 4 Register"},
{0x1c71478, "H3A", "HFV_THR", "Configures the Horizontal Thresholds for the AF IIR filters"},
{0x1c70000, "ISP", "PID", "Peripheral Revision and Class Information(NA)"},
{0x1c70004, "ISP", "PCCR", "Peripheral Clock Control Register"},
{0x1c70008, "ISP", "BCR", "Buffer logic Control Register"},
{0x1c7000c, "ISP", "INTSTAT", "Interrupt Status Register"},
{0x1c70010, "ISP", "INTSEL1", "Interrupt Selection Register1"},
{0x1c70014, "ISP", "INTSEL2", "Interrupt Selection Register2"},
{0x1c70018, "ISP", "INTSEL3", "Interrupt Selection Register3"},
{0x1c7001c, "ISP", "EVTSEL", "Event Selection Register"},
{0x1c7002c, "ISP", "MPSR", "Memory Priority Select Register"},
{0x1c70200, "VPSS", "VPBE_CLK_CTRL", "VPBE Clock Control Register"},
{0x1c71c00, "OSD", "MODE", "OSD Mode Setup"},
{0x1c71c04, "OSD", "VIDWINMD", "Video Window Mode Setup"},
{0x1c71c08, "OSD", "OSDWIN0MD", "Bitmap Window 0 Mode Setup"},
{0x1c71c0c, "OSD", "OSDWIN1MD", "OSD Window 1 Mode Setup"},
{0x1c71c0c, "OSD", "OSDATRMD", "OSD Attribute Window Mode Setup"},
{0x1c71c10, "OSD", "RECTCUR", "Rectangular Cursor Setup"},
{0x1c71c18, "OSD", "VIDWIN0OFST", "Video Window 0 Offset"},
{0x1c71c1c, "OSD", "VIDWIN1OFST", "Video Window 1 Offset"},
{0x1c71c20, "OSD", "OSDWIN0OFST", "Bitmap Window 0 Offset"},
{0x1c71c24, "OSD", "OSDWIN1OFST", "Bitmap Window 1/Attribute Window Offset"},
{0x1c71c28, "OSD", "VIDWINADH", "Video Window 0/1 Address - High"},
{0x1c71c2c, "OSD", "VIDWIN0ADL", "Video Window 0 Address - Low"},
{0x1c71c30, "OSD", "VIDWIN1ADL", "Video Window 1 Address - Low"},
{0x1c71c34, "OSD", "OSDWINADH", "BMP Window 0/1 Address - High"},
{0x1c71c38, "OSD", "OSDWIN0ADL", "BMP Window 0 Address - Low"},
{0x1c71c3c, "OSD", "OSDWIN1ADL", "Bitmap Window 1/Attribute Address - Low"},
{0x1c71c40, "OSD", "BASEPX", "Base Pixel X"},
{0x1c71c44, "OSD", "BASEPY", "Base Pixel Y"},
{0x1c71c48, "OSD", "VIDWIN0XP", "Video Window 0 X-Position"},
{0x1c71c4c, "OSD", "VIDWIN0YP", "Video Window 0 Y-Position"},
{0x1c71c50, "OSD", "VIDWIN0XL", "Video Window 0 X-Size"},
{0x1c71c54, "OSD", "VIDWIN0YL", "Video Window 0 Y-Size"},
{0x1c71c58, "OSD", "VIDWIN1XP", "Video Window 1 X-Position"},
{0x1c71c5c, "OSD", "VIDWIN1YP", "Video Window 1 Y-Position"},
{0x1c71c60, "OSD", "VIDWIN1XL", "Video Window 1 X-Size"},
{0x1c71c64, "OSD", "VIDWIN1YL", "Video Window 1 Y-Size"},
{0x1c71c68, "OSD", "OSDWIN0XP", "Bitmap Window 0 X-Position"},
{0x1c71c6c, "OSD", "OSDWIN0YP", "Bitmap Window 0 Y-Position"},
{0x1c71c70, "OSD", "OSDWIN0XL", "Bitmap Window 0 X-Size"},
{0x1c71c74, "OSD", "OSDWIN0YL", "Bitmap Window 0 Y-Size"},
{0x1c71c78, "OSD", "OSDWIN1XP", "Bitmap Window 1 X-Position"},
{0x1c71c7c, "OSD", "OSDWIN1YP", "Bitmap Window 1 Y-Position"},
{0x1c71c80, "OSD", "OSDWIN1XL", "Bitmap Window 1 X-Size"},
{0x1c71c84, "OSD", "OSDWIN1YL", "Bitmap Window 1 Y-Size"},
{0x1c71c88, "OSD", "CURXP", "Rectangular Cursor Window X-Position"},
{0x1c71c8c, "OSD", "CURYP", "Rectangular Cursor Window Y-Position"},
{0x1c71c90, "OSD", "CURXL", "Rectangular Cursor Window X-Size"},
{0x1c71c94, "OSD", "CURYL", "Rectangular Cursor Window Y-Size"},
{0x1c71ca0, "OSD", "W0BMP01", "Window 0 Bitmap Value to Palette Map 0/1"},
{0x1c71ca4, "OSD", "W0BMP23", "Window 0 Bitmap Value to Palette Map 2/3"},
{0x1c71ca8, "OSD", "W0BMP45", "Window 0 Bitmap Value to Palette Map 4/5"},
{0x1c71cac, "OSD", "W0BMP67", "Window 0 Bitmap Value to Palette Map 6/7"},
{0x1c71cb0, "OSD", "W0BMP89", "Window 0 Bitmap Value to Palette Map 8/9"},
{0x1c71cb4, "OSD", "W0BMPAB", "Window 0 Bitmap Value to Palette Map A/B"},
{0x1c71cb8, "OSD", "W0BMPCD", "Window 0 Bitmap Value to Palette Map C/D"},
{0x1c71cbc, "OSD", "W0BMPEF", "Window 0 Bitmap Value to Palette Map E/F"},
{0x1c71cc0, "OSD", "W1BMP01", "Window 1 Bitmap Value to Palette Map 0/1"},
{0x1c71cc4, "OSD", "W1BMP23", "Window 1 Bitmap Value to Palette Map 2/3"},
{0x1c71cc8, "OSD", "W1BMP45", "Window 1 Bitmap Value to Palette Map 4/5"},
{0x1c71ccc, "OSD", "W1BMP67", "Window 1 Bitmap Value to Palette Map 6/7"},
{0x1c71cd0, "OSD", "W1BMP89", "Window 1 Bitmap Value to Palette Map 8/9"},
{0x1c71cd4, "OSD", "W1BMPAB", "Window 1 Bitmap Value to Palette Map A/B"},
{0x1c71cd8, "OSD", "W1BMPCD", "Window 1 Bitmap Value to Palette Map C/D"},
{0x1c71cdc, "OSD", "W1BMPEF", "Window 1 Bitmap Value to Palette Map E/F"},
{0x1c71ce0, "OSD", "VBNDRY", "Test Mode"},
{0x1c71ce4, "OSD", "EXTMODE", "Extended Mode"},
{0x1c71ce8, "OSD", "MISCCTL", "Miscellaneous Control"},
{0x1c71cec, "OSD", "CLUTRAMYCB", "CLUT RAM Y/Cb Setup"},
{0x1c71cf0, "OSD", "CLUTRAMCR", "CLUT RAM Cr/Mapping Setup"},
{0x1c71cf4, "OSD", "TRANSPVALL", "Transparent Color Code - Lower"},
{0x1c71cf8, "OSD", "TRANSPVALU", "Transparent Color Code - Upper"},
{0x1c71cfc, "OSD", "TRANSPBMPIDX", "Transparent Index Code for Bitmaps"},
{0x1c71e00, "VENC", "VMOD", "Video Mode"},
{0x1c71e04, "VENC", "VIOCTL", "Video Interface I/O Control"},
{0x1c71e08, "VENC", "VDPRO", "Video Data Processing"},
{0x1c71e0c, "VENC", "SYNCCTL", "Sync Control"},
{0x1c71e10, "VENC", "HSPLS", "Horizontal Sync Pulse Width"},
{0x1c71e14, "VENC", "VSPLS", "Vertical Sync Pulse Width"},
{0x1c71e18, "VENC", "HINTVL", "Horizontal Interval"},
{0x1c71e1c, "VENC", "HSTART", "Horizontal Valid Data Start Position"},
{0x1c71e20, "VENC", "HVALID", "Horizontal Data Valid Range"},
{0x1c71e24, "VENC", "VINTVL", "Vertical Interval"},
{0x1c71e28, "VENC", "VSTART", "Vertical Valid Data Start Position"},
{0x1c71e2c, "VENC", "VVALID", "Vertical Data Valid Range"},
{0x1c71e30, "VENC", "HSDLY", "Horizontal Sync Delay"},
{0x1c71e34, "VENC", "VSDLY", "Vertical Sync Delay"},
{0x1c71e38, "VENC", "YCCCTL", "YCbCr Control"},
{0x1c71e3c, "VENC", "RGBCTL", "RGB Control"},
{0x1c71e40, "VENC", "RGBCLP", "RGB Level Clipping"},
{0x1c71e44, "VENC", "LINECTL", "Line ID Control"},
{0x1c71e48, "VENC", "CULLLINE", "Culling Line Control"},
{0x1c71e4c, "VENC", "LCDOUT", "LCD Output Signal Control"},
{0x1c71e50, "VENC", "BRT0", "Brightness Start Position Signal Control"},
{0x1c71e54, "VENC", "BRT1", "Brightness Width Signal Control"},
{0x1c71e58, "VENC", "ACCTL", "LCD_AC Signal Control"},
{0x1c71e5c, "VENC", "PWM0", "PWM Output Period"},
{0x1c71e60, "VENC", "PWM1", "PWM Output Pulse Width"},
{0x1c71e64, "VENC", "DCLKCTL", "DCLK Control"},
{0x1c71e68, "VENC", "DCLKPTN0", "DCLK Pattern 0"},
{0x1c71e6c, "VENC", "DCLKPTN1", "DCLK Pattern 1"},
{0x1c71e70, "VENC", "DCLKPTN2", "DCLK Pattern 2"},
{0x1c71e74, "VENC", "DCLKPTN3", "DCLK Pattern 3"},
{0x1c71e78, "VENC", "DCLKPTN0A", "DCLK Auxiliary Pattern 0"},
{0x1c71e7c, "VENC", "DCLKPTN1A", "DCLK Auxiliary Pattern 1"},
{0x1c71e80, "VENC", "DCLKPTN2A", "DCLK Auxiliary Pattern 2"},
{0x1c71e84, "VENC", "DCLKPTN3A", "DCLK Auxiliary Pattern 3"},
{0x1c71e88, "VENC", "DCLKHSTT", "Horizontal DCLK Mask Start Position"},
{0x1c71e8c, "VENC", "DCLKHSTTA", "Horizontal Auxiliary DCLK Mask Start Position"},
{0x1c71e90, "VENC", "DCLKHVLD", "Horizontal DCLK Mask Range"},
{0x1c71e94, "VENC", "DCLKVSTT", "Vertical DCLK Mask Start Position"},
{0x1c71e98, "VENC", "DCLKVVLD", "Vertical DCLK Mask Range"},
{0x1c71e9c, "VENC", "CAPCTL", "Closed Caption Control"},
{0x1c71ea0, "VENC", "CAPDO", "Closed Caption Odd Field Data"},
{0x1c71ea4, "VENC", "CAPDE", "Closed Caption Even Field Data"},
{0x1c71ea8, "VENC", "ATR0", "Video Attribute Data 0"},
{0x1c71eac, "VENC", "ATR1", "Video Attribute Data 1"},
{0x1c71eb0, "VENC", "ATR2", "Video Attribute Data 2"},
{0x1c71eb4, "VENC", "RSV0", "Reserved 0"},
{0x1c71eb8, "VENC", "VSTAT", "Video Status"},
{0x1c71ebc, "VENC", "RAMADR", "GCP/FRC Table RAM Address"},
{0x1c71ec0, "VENC", "RAMPORT", "GCP/FRC Table RAM Data Port"},
{0x1c71ec4, "VENC", "DACTST", "DAC Test"},
{0x1c71ec8, "VENC", "YCOLVL", "YOUT and COUT Levels"},
{0x1c71ecc, "VENC", "SCPROG", "Sub-Carrier Programming"},
{0x1c71ed0, "VENC", "RSV1", "Reserved 1"},
{0x1c71ed4, "VENC", "RSV2", "Reserved 2"},
{0x1c71ed8, "VENC", "RSV3", "Reserved 3"},
{0x1c71edc, "VENC", "CVBS", "Composite Mode"},
{0x1c71ee0, "VENC", "CMPNT", "Component Mode"},
{0x1c71ee4, "VENC", "ETMG0", "CVBS Timing Control 0"},
{0x1c71ee8, "VENC", "ETMG1", "CVBS Timing Control 1"},
{0x1c71eec, "VENC", "ETMG2", "CVBS Timing Control 2"},
{0x1c71ef0, "VENC", "ETMG3", "CVBS Timing Control 3"},
{0x1c71ef4, "VENC", "DACSEL", "DAC Output Select"},
{0x1c71f00, "VENC", "ARGBX0", "Analog RGB Matrix 0"},
{0x1c71f04, "VENC", "ARGBX1", "Analog RGB Matrix 1"},
{0x1c71f08, "VENC", "ARGBX2", "Analog RGB Matrix 2"},
{0x1c71f0c, "VENC", "ARGBX3", "Analog RGB Matrix 3"},
{0x1c71f10, "VENC", "ARGBX4", "Analog RGB Matrix 4"},
{0x1c71f14, "VENC", "DRGBX0", "Digital RGB Matrix 0"},
{0x1c71f18, "VENC", "DRGBX1", "Digital RGB Matrix 1"},
{0x1c71f1c, "VENC", "DRGBX2", "Digital RGB Matrix 2"},
{0x1c71f20, "VENC", "DRGBX3", "Digital RGB Matrix 3"},
{0x1c71f24, "VENC", "DRGBX4", "Digital RGB Matrix 4"},
{0x1c71f28, "VENC", "VSTARTA", "Vertical Data Valid Start Position For Even Field"},
{0x1c71f2c, "VENC", "OSDCLK0", "OSD Clock Control 0"},
{0x1c71f30, "VENC", "OSDCLK1", "OSD Clock Control 1"},
{0x1c71f34, "VENC", "HVLDCL0", "Horizontal Valid Culling Control 0"},
{0x1c71f38, "VENC", "HVLDCL1", "Horizontal Valid Culling Control 1"},
{0x1c71f3c, "VENC", "OSDHADV", "OSD Horizontal Sync Advance"},
{0x1c71f40, "VENC", "CLKCTL", "Clock Control"},
{0x1c71f44, "VENC", "GAMCTL", "Enable Gamma Correction"},
{0x1c71f48, "VENC", "VVALIDA", "Vertical Data Valid Area For Even Field"},
{0x1c71f4c, "VENC", "BATR0", "Video Attribute 0 For Type B Packet"},
{0x1c71f50, "VENC", "BATR1", "Video Attribute 1 For Type B Packet"},
{0x1c71f54, "VENC", "BATR2", "Video Attribute 2 For Type B Packet"},
{0x1c71f58, "VENC", "BATR3", "Video Attribute 3 For Type B Packet"},
{0x1c71f5c, "VENC", "BATR4", "Video Attribute 4 For Type B Packet"},
{0x1c71f60, "VENC", "BATR5", "Video Attribute 5 For Type B Packet"},
{0x1c71f64, "VENC", "BATR6", "Video Attribute 6 For Type B Packet"},
{0x1c71f68, "VENC", "BATR7", "Video Attribute 7 For Type B Packet"},
{0x1c71f6c, "VENC", "BATR8", "Video Attribute 8 For Type B Packet"},
{0x1c71f70, "VENC", "DACAMP", "Gain and Offset"},
{0x1c71f74, "VENC", "XHINTVL", "Horizontal Interval Extension"},
{0x1c48000, "INTC", "FIQ0", "Fast Interrupt Request Status 0 Register"},
{0x1c48004, "INTC", "FIQ1", "Fast Interrupt Request Status 1 Register"},
{0x1c48008, "INTC", "IRQ0", "Interrupt Request Status 0 Register"},
{0x1c4800c, "INTC", "IRQ1", "Interrupt Request Status 1 Register"},
{0x1c48010, "INTC", "FIQENTRY", "Fast Interrupt Request Entry Address Register"},
{0x1c48014, "INTC", "IRQENTRY", "Interrupt Request Entry Address Register"},
{0x1c48018, "INTC", "EINT0", "Interrupt Enable Register 0"},
{0x1c4801c, "INTC", "EINT1", "Interrupt Enable Register 1"},
{0x1c48020, "INTC", "INTCTL", "Interrupt Operation Control Register"},
{0x1c48024, "INTC", "EABASE", "Interrupt Entry Table Base Address"},
{0x1c48030, "INTC", "INTPRI0", "Interrupt Priority 0 Register"},
{0x1c48034, "INTC", "INTPRI1", "Interrupt Priority 1 Register"},
{0x1c48038, "INTC", "INTPRI2", "Interrupt Priority 2 Register"},
{0x1c4803c, "INTC", "INTPRI3", "Interrupt Priority 3 Register"},
{0x1c48040, "INTC", "INTPRI4", "Interrupt Priority 4 Register"},
{0x1c48044, "INTC", "INTPRI5", "Interrupt Priority 5 Register"},
{0x1c48048, "INTC", "INTPRI6", "Interrupt Priority 6 Register"},
{0x1c4804c, "INTC", "INTPRI7", "Interrupt Priority 7 Register"},
{0x1c40000, "SystemModule", "PINMUX0", "Pin Mux 0 Register"},
{0x1c40004, "SystemModule", "PINMUX1", "Pin Mux 1 Register"},
{0x1c40008, "SystemModule", "PINMUX2", "Pin Mux 2 Register"},
{0x1c4000c, "SystemModule", "PINMUX3", "Pin Mux 3 Register"},
{0x1c40010, "SystemModule", "PINMUX4", "Pin Mux 4 Register"},
{0x1c40014, "SystemModule", "BOOTCFG", "Boot Configuration Register"},
{0x1c40018, "SystemModule", "ARM_INTMUX", "Multiplexing Control for ARM Interrupts Register"},
{0x1c4001c, "SystemModule", "EDMA_EVTMUX", "Multiplexing Control for EDMA Events Register"},
{0x1c40024, "SystemModule", "HPI_CTL", "HPI Control Register"},
{0x1c40028, "SystemModule", "DEVICE_ID", "Device ID Register"},
{0x1c4002c, "SystemModule", "VDAC_CONFIG", "Video DAC Configuration Register"},
{0x1c40030, "SystemModule", "TIMER64_CTL", "Timer Input Control Register"},
{0x1c40034, "SystemModule", "USB_PHY_CTRL", "USB PHY Control Register"},
{0x1c40038, "SystemModule", "MISC", "Miscellaneous Control Register"},
{0x1c4003c, "SystemModule", "MSTPRI0", "Master Priorities 0 Register"},
{0x1c40040, "SystemModule", "MSTPRI1", "Master Priorities 1 Register"},
{0x1c40044, "SystemModule", "VPSS_CLK_CTRL", "VPSS Clock Mux Control Register"},
{0x1c40048, "SystemModule", "PERI_CLKCTL", "Peripheral Clock Control Register"},
{0x1c4004c, "SystemModule", "DEEPSLEEP", "DEEPSLEEP Control Register"},
{0x1c40054, "SystemModule", "DEBOUNCE0", "De-bounce GIO0 input Register"},
{0x1c40058, "SystemModule", "DEBOUNCE1", "De-bounce GIO1 input Register"},
{0x1c4005c, "SystemModule", "DEBOUNCE2", "De-bounce GIO2 input Register"},
{0x1c40060, "SystemModule", "DEBOUNCE3", "De-bounce GIO3 input Register"},
{0x1c40064, "SystemModule", "DEBOUNCE4", "De-bounce GIO4 input Register"},
{0x1c40068, "SystemModule", "DEBOUNCE5", "De-bounce GIO5 input Register"},
{0x1c4006c, "SystemModule", "DEBOUNCE6", "De-bounce GIO6 input Register"},
{0x1c40070, "SystemModule", "DEBOUNCE7", "De-bounce GIO7 input Register"},
{0x1c40074, "SystemModule", "VTPIOCR", "VTP IO Control Register"},
{0x1c40078, "SystemModule", "PUPDCTL0", "IO cell pull up/down control 0 Register"},
{0x1c4007c, "SystemModule", "PUPDCTL1", "IO cell pull up/down control 1 Register"},
{0x1c40080, "SystemModule", "HDVICPBT", "HDVICP boot Register"},
{0x1c40084, "SystemModule", "PLLC1_CONFIG", "PLLC1 configuration Register"},
{0x1c40088, "SystemModule", "PLLC2_CONFIG", "PLLC2 configuration Register"},
{0x1c67000, "GPIO", "PID", "Peripheral Identification Register"},
{0x1c67008, "GPIO", "BINTEN", "GPIO Interrupt Per-Bank Enable Register"},
{0x1c67010, "GPIO", "DIR01", "GPIO Banks 0 and 1 Direction Register"},
{0x1c67014, "GPIO", "OUT_DATA01", "GPIO Banks 0 and 1 Output Data Register"},
{0x1c67018, "GPIO", "SET_DATA01", "GPIO Banks 0 and 1 Set Data Register"},
{0x1c6701c, "GPIO", "CLR_DATA01", "GPIO Banks 0 and 1 Clear Data Register"},
{0x1c67020, "GPIO", "IN_DATA01", "GPIO Banks 0 and 1 Input Data Register"},
{0x1c67024, "GPIO", "SET_RIS_TRIG01", "GPIO Banks 0 and 1 Set Rising Edge Interrupt Register"},
{0x1c67028, "GPIO", "CLR_RIS_TRIG01", "GPIO Banks 0 and 1 Clear Rising Edge Interrupt Register"},
{0x1c6702c, "GPIO", "SET_FAL_TRIG01", "GPIO Banks 0 and 1 Set Falling Edge Interrupt Register"},
{0x1c67030, "GPIO", "CLR_FAL_TRIG01", "GPIO Banks 0 and 1 Clear Falling Edge Interrupt Register"},
{0x1c67034, "GPIO", "INTSTAT01", "GPIO Banks 0 and 1 Interrupt Status Register"},
{0x1c67038, "GPIO", "DIR23", "GPIO Banks 2 and 3 Direction Register"},
{0x1c6703c, "GPIO", "OUT_DATA23", "GPIO Banks 2 and 3 Output Data Register"},
{0x1c67040, "GPIO", "SET_DATA23", "GPIO Banks 2 and 3 Set Data Register"},
{0x1c67044, "GPIO", "CLR_DATA23", "GPIO Banks 2 and 3 Clear Data Register"},
{0x1c67048, "GPIO", "IN_DATA23", "GPIO Banks 2 and 3 Input Data Register"},
{0x1c67060, "GPIO", "DIR45", "GPIO Banks 4 and 5 Direction Register"},
{0x1c67064, "GPIO", "OUT_DATA45", "GPIO Banks 4 and 5 Output Data Register"},
{0x1c67068, "GPIO", "SET_DATA45", "GPIO Banks 4 and 5 Set Data Register"},
{0x1c6706c, "GPIO", "CLR_DATA45", "GPIO Banks 4 and 5 Clear Data Register"},
{0x1c67070, "GPIO", "IN_DATA45", "GPIO Banks 4 and 5 Input Data Register"},
{0x1c67088, "GPIO", "DIR6", "GPIO Banks 6 Direction Register"},
{0x1c6708c, "GPIO", "OUT_DATA6", "GPIO Banks 6 Output Data Register"},
{0x1c67090, "GPIO", "SET_DATA6", "GPIO Banks 6 Set Data Register"},
{0x1c67094, "GPIO", "CLR_DATA6", "GPIO Banks 6 Clear Data Register"},
{0x1c6709c, "GPIO", "IN_DATA6", "GPIO Banks 6 Input Data Register"},
{0x1d0c000, "VoiceCodec", "VC_PID", "Voice Codec PID Register"},
{0x1d0c004, "VoiceCodec", "VC_CTRL", "Voice Codec Control Register"},
{0x1d0c008, "VoiceCodec", "VC_INTEN", "Voice Codec Interrupt enable Register"},
{0x1d0c00c, "VoiceCodec", "VC_INTSTATUS", "Voice Codec Interrupt status Register"},
{0x1d0c010, "VoiceCodec", "VC_INTCLR", "Voice Codec Interrupt status clear Register"},
{0x1d0c014, "VoiceCodec", "VC_EMUL_CTRL", "Voice Codec Emulator Control Register"},
{0x1d0c020, "VoiceCodec", "RFIFO", "Voice Codec Read FIFO access Register"},
{0x1d0c024, "VoiceCodec", "WFIFO", "Voice Codec Write FIFO access Register"},
{0x1d0c028, "VoiceCodec", "FIFOSTAT", "Voice Codec FIFO Status Register"},
{0x1d0c080, "VoiceCodec", "VC_REG00", "Notch filter 1 parameter Register"},
{0x1d0c084, "VoiceCodec", "VC_REG01", "Notch filter 1 parameter Register"},
{0x1d0c088, "VoiceCodec", "VC_REG02", "Notch filter 2 parameter Register"},
{0x1d0c08c, "VoiceCodec", "VC_REG03", "Notch filter 2 parameter Register"},
{0x1d0c090, "VoiceCodec", "VC_REG04", "Voice Codec Recording mode control Register"},
{0x1d0c094, "VoiceCodec", "VC_REG05", "Programmable Gain Amplifier (PGA) and Microphone gain control Register"},
{0x1d0c098, "VoiceCodec", "VC_REG06", "Automatic Level control Register"},
{0x1d0c0a4, "VoiceCodec", "VC_REG09", "Digital soft mute/attenuation control Register"},
{0x1d0c0a8, "VoiceCodec", "VC_REG10", "Zero cross detection control Register"},
{0x1d0c0b0, "VoiceCodec", "VC_REG12", "Voice Codec Power up/down control Register"},
{0x1c40800, "PLLC1", "PID", "Peripheral ID and revision information"},
{0x1c408e4, "PLLC1", "RSTYPE", "Reset Type Status Register"},
{0x1c40900, "PLLC1", "PLLCTL", "Controls PLL operations"},
{0x1c40904, "PLLC1", "OCSEL", "OBSCLK Select Register"},
{0x1c40908, "PLLC1", "PLLSECCTL", "PLL Secondary Control Register"},
{0x1c40910, "PLLC1", "PLLM", "PLL Multiplier Control"},
{0x1c40914, "PLLC1", "PREDIV", "Pre-divider control"},
{0x1c40918, "PLLC1", "PLLDIV1", "PLL Controller Divider 1 Register (SYSCLK1)"},
{0x1c4091c, "PLLC1", "PLLDIV2", "PLL Controller Divider 2 Register (SYSCLK2)"},
{0x1c40920, "PLLC1", "PLLDIV3", "PLL Controller Divider 3 Register (SYSCLK3)"},
{0x1c40924, "PLLC1", "OSCDIV1", "Oscillator Divider 1 Register"},
{0x1c40928, "PLLC1", "POSTDIV", "Post-divider control"},
{0x1c4092c, "PLLC1", "BPDIV", "Bypass divider control"},
{0x1c40938, "PLLC1", "PLLCMD", "PLL Controller Command register"},
{0x1c4093c, "PLLC1", "PLLSTAT", "PLL Controller Status register"},
{0x1c40940, "PLLC1", "ALNCTL", "Align control register"},
{0x1c40944, "PLLC1", "DCHANGE", "PLL divider ratio change status register"},
{0x1c40948, "PLLC1", "CKEN", "Clock enable control AUXCLK"},
{0x1c4094c, "PLLC1", "CKSTAT", "Clock status for SYSCLKBP and AUXCLK"},
{0x1c40950, "PLLC1", "SYSTAT", "Clock status for SYSCLKn clocks"},
{0x1c40960, "PLLC1", "PLLDIV4", "PLL Controller Divider 4 Register (SYSCLK4)"},
{0x1c40964, "PLLC1", "PLLDIV5", "PLL Controller Divider 5 Register (SYSCLK5)"},
{0x1c40968, "PLLC1", "PLLDIV6", "PLL Controller Divider 6 Register (SYSCLK6)"},
{0x1c4096c, "PLLC1", "PLLDIV7", "PLL Controller Divider 7 Register (SYSCLK7)"},
{0x1c40970, "PLLC1", "PLLDIV8", "PLL Controller Divider 8 Register (SYSCLK8)"},
{0x1c40974, "PLLC1", "PLLDIV9", "PLL Controller Divider 9 Register (SYSCLK9)"},
{0x1c40c00, "PLLC2", "PID", "Peripheral ID and revision information"},
{0x1c40ce4, "PLLC2", "RSTYPE", "Reset Type Status Register"},
{0x1c40d00, "PLLC2", "PLLCTL", "Controls PLL operations"},
{0x1c40d04, "PLLC2", "OCSEL", "OBSCLK Select Register"},
{0x1c40d08, "PLLC2", "PLLSECCTL", "PLL Secondary Control Register"},
{0x1c40d10, "PLLC2", "PLLM", "PLL Multiplier Control"},
{0x1c40d14, "PLLC2", "PREDIV", "Pre-divider control"},
{0x1c40d18, "PLLC2", "PLLDIV1", "PLL Controller Divider 1 Register (SYSCLK1)"},
{0x1c40d1c, "PLLC2", "PLLDIV2", "PLL Controller Divider 2 Register (SYSCLK2)"},
{0x1c40d20, "PLLC2", "PLLDIV3", "PLL Controller Divider 3 Register (SYSCLK3)"},
{0x1c40d24, "PLLC2", "OSCDIV1", "Oscillator Divider 1 Register"},
{0x1c40d28, "PLLC2", "POSTDIV", "Post-divider control"},
{0x1c40d2c, "PLLC2", "BPDIV", "Bypass divider control"},
{0x1c40d38, "PLLC2", "PLLCMD", "PLL Controller Command register"},
{0x1c40d3c, "PLLC2", "PLLSTAT", "PLL Controller Status register"},
{0x1c40d40, "PLLC2", "ALNCTL", "Align control register"},
{0x1c40d44, "PLLC2", "DCHANGE", "PLL divider ratio change status register"},
{0x1c40d48, "PLLC2", "CKEN", "Clock enable control AUXCLK"},
{0x1c40d4c, "PLLC2", "CKSTAT", "Clock status for SYSCLKBP and AUXCLK"},
{0x1c40d50, "PLLC2", "SYSTAT", "Clock status for SYSCLKn clocks"},
{0x1c40d60, "PLLC2", "PLLDIV4", "PLL Controller Divider 4 Register (SYSCLK4)"},
{0x1c40d64, "PLLC2", "PLLDIV5", "PLL Controller Divider 5 Register (SYSCLK5)"},
{0x1C67800, "SPI2", "SPIGCR0", "SPI global control register 0"},
{0x1C67804, "SPI2", "SPIGCR1", "SPI global control register 1"},
{0x1C67808, "SPI2", "SPIINT", "SPI interrupt register"},
{0x1C6780c, "SPI2", "SPILVL", "SPI interrupt level register"},
{0x1C67810, "SPI2", "SPIFLG", "SPI flag register"},
{0x1C67814, "SPI2", "SPIPC0", "SPI pin control register"},
{0x1C6781c, "SPI2", "SPIPC2", "SPI pin control register 2"},
{0x1C6783c, "SPI2", "SPIDAT1", "SPI shift register"},
{0x1C67840, "SPI2", "SPIBUF", "SPI buffer register"},
{0x1C67844, "SPI2", "SPIEMU", "SPI emulation register"},
{0x1C67848, "SPI2", "SPIDELAY", "SPI delay register"},
{0x1C6784c, "SPI2", "SPIDEF", "SPI default chip select register"},
{0x1C67850, "SPI2", "SPIFMT0", "SPI data format register 0"},
{0x1C67854, "SPI2", "SPIFMT1", "SPI data format register 1"},
{0x1C67858, "SPI2", "SPIFMT2", "SPI data format register 2"},
{0x1C6785c, "SPI2", "SPIFMT3", "SPI data format register 3"},
{0x1C67860, "SPI2", "INTVEC0", "SPI interrupt vector register 0"},
{0x1C67864, "SPI2", "INTVEC1", "SPI interrupt vector register 1"},
{0x1C21400, "Timer0", "PID12", "Peripheral Identification Register 12"},
{0x1C21404, "Timer0", "EMUMGT", "Emulation Management Register"},
{0x1C21410, "Timer0", "TIM12", "Timer Counter Register 12"},
{0x1C21414, "Timer0", "TIM34", "Timer Counter Register 34"},
{0x1C21418, "Timer0", "PRD12", "Timer Period Register 12"},
{0x1C2141C, "Timer0", "PRD34", "Timer Period Register 34"},
{0x1C21420, "Timer0", "TCR", "Timer Control Register"},
{0x1C21424, "Timer0", "TGCR", "Timer Global Control Register"},
{0x1C21428, "Timer0", "WDTCR", "Watchdog Timer Control Register"},
{0x1C21434, "Timer0", "REL12", "Timer Reload Register 12"},
{0x1C21438, "Timer0", "REL34", "Timer Reload Register 34"},
{0x1C2143C, "Timer0", "CAP12", "Timer Capture Register 12"},
{0x1C21440, "Timer0", "CAP34", "Timer Capture Register 34"},
{0x1C21444, "Timer0", "INTCTL_STAT", "Timer Interrupt Control and Status Register"},
{0x1C21800, "Timer1", "PID12", "Peripheral Identification Register 12"},
{0x1C21804, "Timer1", "EMUMGT", "Emulation Management Register"},
{0x1C21810, "Timer1", "TIM12", "Timer Counter Register 12"},
{0x1C21814, "Timer1", "TIM34", "Timer Counter Register 34"},
{0x1C21818, "Timer1", "PRD12", "Timer Period Register 12"},
{0x1C2181C, "Timer1", "PRD34", "Timer Period Register 34"},
{0x1C21820, "Timer1", "TCR", "Timer Control Register"},
{0x1C21824, "Timer1", "TGCR", "Timer Global Control Register"},
{0x1C21828, "Timer1", "WDTCR", "Watchdog Timer Control Register"},
{0x1C21834, "Timer1", "REL12", "Timer Reload Register 12"},
{0x1C21838, "Timer1", "REL34", "Timer Reload Register 34"},
{0x1C2183C, "Timer1", "CAP12", "Timer Capture Register 12"},
{0x1C21840, "Timer1", "CAP34", "Timer Capture Register 34"},
{0x1C21844, "Timer1", "INTCTL_STAT", "Timer Interrupt Control and Status Register"},
{0x1C20800, "Timer3", "PID12", "Peripheral Identification Register 12"},
{0x1C20804, "Timer3", "EMUMGT", "Emulation Management Register"},
{0x1C20810, "Timer3", "TIM12", "Timer Counter Register 12"},
{0x1C20814, "Timer3", "TIM34", "Timer Counter Register 34"},
{0x1C20818, "Timer3", "PRD12", "Timer Period Register 12"},
{0x1C2081C, "Timer3", "PRD34", "Timer Period Register 34"},
{0x1C20820, "Timer3", "TCR", "Timer Control Register"},
{0x1C20824, "Timer3", "TGCR", "Timer Global Control Register"},
{0x1C20828, "Timer3", "WDTCR", "Watchdog Timer Control Register"},
{0x1C20834, "Timer3", "REL12", "Timer Reload Register 12"},
{0x1C20838, "Timer3", "REL34", "Timer Reload Register 34"},
{0x1C2083C, "Timer3", "CAP12", "Timer Capture Register 12"},
{0x1C20840, "Timer3", "CAP34", "Timer Capture Register 34"},
{0x1C20844, "Timer3", "INTCTL_STAT", "Timer Interrupt Control and Status Register"},
{0x1C23800, "Timer4", "PID12", "Peripheral Identification Register 12"},
{0x1C23804, "Timer4", "EMUMGT", "Emulation Management Register"},
{0x1C23810, "Timer4", "TIM12", "Timer Counter Register 12"},
{0x1C23814, "Timer4", "TIM34", "Timer Counter Register 34"},
{0x1C23818, "Timer4", "PRD12", "Timer Period Register 12"},
{0x1C2381C, "Timer4", "PRD34", "Timer Period Register 34"},
{0x1C23820, "Timer4", "TCR", "Timer Control Register"},
{0x1C23824, "Timer4", "TGCR", "Timer Global Control Register"},
{0x1C23828, "Timer4", "WDTCR", "Watchdog Timer Control Register"},
{0x1C23834, "Timer4", "REL12", "Timer Reload Register 12"},
{0x1C23838, "Timer4", "REL34", "Timer Reload Register 34"},
{0x1C2383C, "Timer4", "CAP12", "Timer Capture Register 12"},
{0x1C23840, "Timer4", "CAP34", "Timer Capture Register 34"},
{0x1C23844, "Timer4", "INTCTL_STAT", "Timer Interrupt Control and Status Register"},
{0x1C22000, "PWM0", "PID", "PWM Peripheral Identification Register"},
{0x1C22004, "PWM0", "PCR", "PWM Peripheral Control Register"},
{0x1C22008, "PWM0", "CFG", "PWM Configuration Register"},
{0x1C2200C, "PWM0", "START", "PWM Start Register"},
{0x1C22010, "PWM0", "RPT", "PWM Repeat Count Register"},
{0x1C22014, "PWM0", "PER", "PWM Period Register"},
{0x1C22018, "PWM0", "PH1D", "PWM First-Phase Duration Register"},
{0x1C22400, "PWM1", "PID", "PWM Peripheral Identification Register" },
{0x1C22404, "PWM1", "PCR", "PWM Peripheral Control Register"},
{0x1C22408, "PWM1", "CFG", "PWM Configuration Register"},
{0x1C2240C, "PWM1", "START", "PWM Start Register"},
{0x1C22410, "PWM1", "RPT", "PWM Repeat Count Register"},
{0x1C22414, "PWM1", "PER", "PWM Period Register"},
{0x1C22418, "PWM1", "PH1D", "PWM First-Phase Duration Register"},
{0x1C22800, "PWM2", "PID", "PWM Peripheral Identification Register" },
{0x1C22804, "PWM2", "PCR", "PWM Peripheral Control Register"},
{0x1C22808, "PWM2", "CFG", "PWM Configuration Register"},
{0x1C2280C, "PWM2", "START", "PWM Start Register"},
{0x1C22810, "PWM2", "RPT", "PWM Repeat Count Register"},
{0x1C22814, "PWM2", "PER", "PWM Period Register"},
{0x1C22818, "PWM2", "PH1D", "PWM First-Phase Duration Register"},
{0x1C22C00, "PWM3", "PID", "PWM Peripheral Identification Register" },
{0x1C22C04, "PWM3", "PCR", "PWM Peripheral Control Register"},
{0x1C22C08, "PWM3", "CFG", "PWM Configuration Register"},
{0x1C22C0C, "PWM3", "START", "PWM Start Register"},
{0x1C22C10, "PWM3", "RPT", "PWM Repeat Count Register"},
{0x1C22C14, "PWM3", "PER", "PWM Period Register"},
{0x1C22C18, "PWM3", "PH1D", "PWM First-Phase Duration Register"},
{0x1C00000, "EDMACC", "PID", "EDMA CC Peripheral Identification Register"},
{0x1C00004, "EDMACC", "CCCFG", "EDMA3CC Configuration Register"},
{0x1C00200, "EDMACC", "QCHMAP0", "QDMA Channel 0 Mapping Register"},
{0x1C00204, "EDMACC", "QCHMAP1", "QDMA Channel 1 Mapping Register"},
{0x1C00208, "EDMACC", "QCHMAP2", "QDMA Channel 2 Mapping Register"},
{0x1C0020C, "EDMACC", "QCHMAP3", "QDMA Channel 3 Mapping Register"},
{0x1C00210, "EDMACC", "QCHMAP4", "QDMA Channel 4 Mapping Register"},
{0x1C00214, "EDMACC", "QCHMAP5", "QDMA Channel 5 Mapping Register"},
{0x1C00218, "EDMACC", "QCHMAP6", "QDMA Channel 6 Mapping Register"},
{0x1C0021C, "EDMACC", "QCHMAP7", "QDMA Channel 7 Mapping Register"},
{0x1C00240, "EDMACC", "DMAQNUM0", "DMA Queue Number Register 0"},
{0x1C00244, "EDMACC", "DMAQNUM1", "DMA Queue Number Register 1"},
{0x1C00248, "EDMACC", "DMAQNUM2", "DMA Queue Number Register 2"},
{0x1C0024C, "EDMACC", "DMAQNUM3", "DMA Queue Number Register 3"},
{0x1C00250, "EDMACC", "DMAQNUM4", "DMA Queue Number Register 4"},
{0x1C00254, "EDMACC", "DMAQNUM5", "DMA Queue Number Register 5"},
{0x1C00258, "EDMACC", "DMAQNUM6", "DMA Queue Number Register 6"},
{0x1C0025C, "EDMACC", "DMAQNUM7", "DMA Queue Number Register 7"},
{0x1C00260, "EDMACC", "QDMAQNUM", "QDMA Queue Number Register"},
{0x1C00284, "EDMACC", "QUEPRI", "Queue Priority Register"},
{0x1C00300, "EDMACC", "EMR", "Event Missed Register"},
{0x1C00304, "EDMACC", "EMRH", "Event Missed Register High"},
{0x1C00308, "EDMACC", "EMCR", "Event Missed Clear Register"},
{0x1C0030C, "EDMACC", "EMCRH", "Event Missed Clear Register High"},
{0x1C00310, "EDMACC", "QEMR", "QDMA Event Missed Register"},
{0x1C00314, "EDMACC", "QEMCR", "QDMA Event Missed Clear Register High"},
{0x1C00318, "EDMACC", "CCERR", "EDMA3CC Error Register"},
{0x1C0031C, "EDMACC", "CCERRCLR", "EDMA3CC Error Clear Register"},
{0x1C00320, "EDMACC", "EEVAL", "Error Evaluate Register"},
{0x1C00340, "EDMACC", "DRAE0", "DMA Region Access Enable for Region 0"},
{0x1C00344, "EDMACC", "DRAE0H", "DMA Region Access Enable for Region 0 High"},
{0x1C00350, "EDMACC", "DRAE2", "DMA Region Access Enable for Region 2"},
{0x1C00354, "EDMACC", "DRAE2H", "DMA Region Access Enable for Region 2 High"},
{0x1C00360, "EDMACC", "DRAE4", "DMA Region Access Enable for Region 4"},
{0x1C00364, "EDMACC", "DRAE4H", "DMA Region Access Enable for Region 4 High"},
{0x1C00368, "EDMACC", "DRAE5", "DMA Region Access Enable for Region 5"},
{0x1C0036C, "EDMACC", "DRAE5H", "DMA Region Access Enable for Region 5 High"},
{0x1C00600, "EDMACC", "QSTAT0", "Queue 0 Status Register"},
{0x1C00604, "EDMACC", "QSTAT1", "Queue 1 Status Register"},
{0x1C00608, "EDMACC", "QSTAT2", "Queue 2 Status Register"},
{0x1C0060C, "EDMACC", "QSTAT3", "Queue 3 Status Register"},
{0x1C00620, "EDMACC", "QWMTHRA", "Queue Watermark Threshold A Register"},
{0x1C00640, "EDMACC", "CCSTAT", "EDMA3CC Status Register"},
{0x1C01000, "EDMACC", "ER", "Event Register"},
{0x1C01004, "EDMACC", "ERH", "Event Register High"},
{0x1C01008, "EDMACC", "ECR", "Event Clear Register"},
{0x1C0100C, "EDMACC", "ECRH", "Event Clear Register High"},
{0x1C01010, "EDMACC", "ESR", "Event Set Register"},
{0x1C01014, "EDMACC", "ESRH", "Event Set Register High"},
{0x1C01018, "EDMACC", "CER", "Chained Event Register"},
{0x1C0101C, "EDMACC", "CERH", "Chained Event Register High"},
{0x1C01020, "EDMACC", "EER", "Event Enable Register"},
{0x1C01024, "EDMACC", "EERH", "Event Enable Register High"},
{0x1C01028, "EDMACC", "EECR", "Event Enable Clear Register"},
{0x1C0102C, "EDMACC", "EECRH", "Event Enable Clear Register High"},
{0x1C01030, "EDMACC", "EESR", "Event Enable Set Register"},
{0x1C01034, "EDMACC", "EESRH", "Event Enable Set Register High"},
{0x1C01038, "EDMACC", "SER", "Secondary Event Register"},
{0x1C0103C, "EDMACC", "SERH", "Secondary Event Register High"},
{0x1C01040, "EDMACC", "SECR", "Secondary Event Clear Register"},
{0x1C01044, "EDMACC", "SECRH", "Secondary Event Clear Register High"},
{0x1C01050, "EDMACC", "IER", "Interrupt Enable Register"},
{0x1C01054, "EDMACC", "IERH", "Interrupt Enable Register High"},
{0x1C01058, "EDMACC", "IECR", "Interrupt Enable Clear Register"},
{0x1C0105C, "EDMACC", "IECRH", "Interrupt Enable Clear Register High"},
{0x1C01060, "EDMACC", "IESR", "Interrupt Enable Set Register"},
{0x1C01064, "EDMACC", "IESRH", "Interrupt Enable Set Register High"},
{0x1C01068, "EDMACC", "IPR", "Interrupt Pending Register"},
{0x1C0106C, "EDMACC", "IPRH", "Interrupt Pending Register High"},
{0x1C01070, "EDMACC", "ICR", "Interrupt Clear Register"},
{0x1C01074, "EDMACC", "ICRH", "Interrupt Clear Register High"},
{0x1C01078, "EDMACC", "IEVAL", "Interrupt Evaluate Register"},
{0x1C01080, "EDMACC", "QER", "QDMA Event Register"},
{0x1C01084, "EDMACC", "QEER", "QDMA Event Enable Register"},
{0x1C01088, "EDMACC", "QEECR", "QDMA Event Enable Clear Register"},
{0x1C0108C, "EDMACC", "QEESR", "QDMA Event Enable Set Register"},
{0x1C01090, "EDMACC", "QSER", "QDMA Secondary Event Register"},
{0x1C01094, "EDMACC", "QSECR", "QDMA Secondary Event Clear Register"},
{0x20000004, "DDR2", "SDRSTAT", "SDRSTAT Status Register"},
{0x20000008, "DDR2", "SDCR", "SDRAM Configuration Register"},
{0x2000000C, "DDR2", "SDRCR", "SDRAM Refresh Control Register"},
{0x20000010, "DDR2", "SDTIMR", "SDRAM Timing Register"},
{0x20000014, "DDR2", "SDTIMR2", "SDRAM Timing Register 2"},
{0x2000001C, "DDR2", "SDCR2", "SDRAM Configuration Register 2"},
{0x20000020, "DDR2", "PBBPR", "Peripheral Bus Burst Priority Register"},
{0x200000C0, "DDR2", "IRR", "Interrupt Raw Register"},
{0x200000C4, "DDR2", "IMR", "Interrupt Masked Register"},
{0x200000C8, "DDR2", "IMSR", "Interrupt Mask Set Register"},
{0x200000CC, "DDR2", "IMCR", "Interrupt Mask Clear Register"},
{0x200000E4, "DDR2", "DDRPHYCR1", "DDR PHY Control Register 1"},
{0x01C23C00, "ADC", "ADCTL", "Control register"},
{0x01C23C04, "ADC", "CMPTGT", "Comparator target channel"},
{0x01C23C08, "ADC", "CMPLDAT", "Comparison A/D Lower data"},
{0x01C23C0C, "ADC", "CMPUDAT", "Comparison A/D Upper data"},
{0x01C23C10, "ADC", "SETDIV", "SETUP divide value for start A/D conversion"},
{0x01C23C14, "ADC", "CHSEL", "Analog Input channel select"},
{0x01C23C18, "ADC", "AD0DAT", "A/D conversion data 0"},
{0x01C23C1C, "ADC", "AD1DAT", "A/D conversion data 1"},
{0x01C23C20, "ADC", "AD2DAT", "A/D conversion data 2"},
{0x01C23C24, "ADC", "AD3DAT", "A/D conversion data 3"},
{0x01C23C28, "ADC", "AD4DAT", "A/D conversion data 4"},
{0x01C23C2C, "ADC", "AD5DAT", "A/D conversion data 5"},
{0x01C23C30, "ADC", "EMUCTRL", "Emulation Control"},
{0x01C6440F, "USB", "TESTMODE", "USB 2.0 TestModes"},
{0x01D11000, "MMCSD0", "MMCCTL", "MMC Control Register"},
{0x01D11004, "MMCSD0", "MMCCLK", "MMC Memory Clock Control Register"},
{0x01D11008, "MMCSD0", "MMCST0", "MMC Status Register 0"},
{0x01D1100C, "MMCSD0", "MMCST1", "MMC Status Register 1"},
{0x01D11010, "MMCSD0", "MMCIM", ""},
{0x01D11014, "MMCSD0", "MMCTOR", ""},
{0x01D11018, "MMCSD0", "MMCTOD", ""},
{0x01D1101C, "MMCSD0", "MMCBLEN", ""},
{0x01D11020, "MMCSD0", "MMCNBLK", ""},
{0x01D11024, "MMCSD0", "MMCNBLC", ""},
{0x01D11028, "MMCSD0", "MMCDRR", ""},
{0x01D1102C, "MMCSD0", "MMCDXR", ""},
{0x01D11030, "MMCSD0", "MMCCMD", ""},
{0x01D11034, "MMCSD0", "MMCARGHL", ""},
{0x01D11038, "MMCSD0", "MMCRSP01", ""},
{0x01D1103C, "MMCSD0", "MMCRSP23", ""},
{0x01D11040, "MMCSD0", "MMCRSP45", ""},
{0x01D11044, "MMCSD0", "MMCRSP67", ""},
{0x01D11048, "MMCSD0", "MMCDRSP", ""},
{0x01D11050, "MMCSD0", "MMCCIDX", ""},
{0x01D11064, "MMCSD0", "SDIOCTL", ""},
{0x01D11068, "MMCSD0", "SDIOST0", ""},
{0x01D1106C, "MMCSD0", "SDIOIEN", ""},
{0x01D11070, "MMCSD0", "SDIOIST", ""},
{0x01D11074, "MMCSD0", "MMCFIFOCTL", ""},
};
#define NUM_REGISTERS (sizeof(registers) / sizeof(registers[0]))
#define MAP_SIZE 4096UL
#define MAP_MASK (MAP_SIZE - 1)
static int fd = -1;
static void* map_base = (void*) -1;
static off_t current_base = 0;
void cleanup_mmap()
{
if (map_base != (void*) -1)
{
munmap(map_base, MAP_SIZE);
map_base = (void*) -1;
}
}
void* update_mmap(off_t address)
{
void* virt_addr;
off_t base = address & ~MAP_MASK;
if (base != current_base)
{
cleanup_mmap();
map_base = mmap(0, MAP_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED, fd, base);
if (map_base == (void *) -1)
{
printf("Error from mmap!\n");
exit(1);
}
current_base = base;
}
virt_addr = map_base + (address & MAP_MASK);
return virt_addr;
}
int read_register(off_t address)
{
void* virt_addr = update_mmap(address);
return *((unsigned long *) virt_addr);
}
void write_register(off_t address, int value)
{
void* virt_addr = update_mmap(address);
*((unsigned long *) virt_addr) = value;
}
int main(int argc, char **argv) {
int i;
if ((fd = open("/dev/mem", O_RDWR | O_SYNC)) == -1)
{
printf("Error opening /dev/mem\n");
return -1;
}
if (argc == 1)
{
for (i = 0; i < NUM_REGISTERS; i++)
{
struct Dm365Register* reg = &registers[i];
int value = read_register(reg->address);
printf("%s.%s(0x%08x): 0x%08x\n", reg->module, reg->name, reg->address, value);
}
}
else if (argc == 2)
{
for (i = 0; i < NUM_REGISTERS; i++)
{
struct Dm365Register* reg = &registers[i];
if (strcmp(reg->module, argv[1]) == 0)
{
int value = read_register(reg->address);
printf("%s.%s(0x%08x): 0x%08x\n", reg->module, reg->name, reg->address, value);
}
}
}
else if (argc == 3)
{
char* regname = argv[1];
int value = strtoul(argv[2], NULL, 0);
int address = strtoul(regname, NULL, 0);
if (address == 0)
{
// Conversion didn't work, so look up symbolic name.
char* module = argv[1];
char* name = strchr(module, '.');
if (name == NULL)
{
printf("Couldn't parse register %s\n", argv[1]);
return 1;
}
*name = 0;
++name;
for (i = 0; i < NUM_REGISTERS; i++)
{
struct Dm365Register* reg = &registers[i];
if (strcmp(reg->module, module) == 0 &&
strcmp(reg->name, name) == 0)
{
write_register(reg->address, value);
printf("%s.%s(0x%08x): 0x%08x\n", reg->module, reg->name, reg->address, value);
break;
}
}
}
else
{
write_register(address, value);
printf("0x%08x: 0x%08x\n", address, value);
}
}
cleanup_mmap();
close(fd);
return 0;
}