diff --git a/CHANGELOG.md b/CHANGELOG.md
index 0e3430f95e8..7afd5f619b6 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -5,6 +5,8 @@
 ### Fixed
 
 - Fixed passing through cache information from host in CPUID leaf 0x80000006.
+- Fixed the T2S CPU template to set the RRSBA bit of the IA32_ARCH_CAPABILITIES
+  MSR to 1 in accordance with an Intel microcode update.
 
 ## [1.2.1]
 
diff --git a/resources/tests/msr/msr_list_T2S_4.14.csv b/resources/tests/msr/msr_list_T2S_4.14.csv
index f201a716ddd..7c37903b774 100644
--- a/resources/tests/msr/msr_list_T2S_4.14.csv
+++ b/resources/tests/msr/msr_list_T2S_4.14.csv
@@ -265,7 +265,7 @@ MSR_ADDR,STATUS,VALUE
 0x107,unimplemented,0x0
 0x108,unimplemented,0x0
 0x109,unimplemented,0x0
-0x10a,implemented,0xc4c
+0x10a,implemented,0x80c4c
 0x10b,unimplemented,0x0
 0x10c,unimplemented,0x0
 0x10d,unimplemented,0x0
diff --git a/resources/tests/msr/msr_list_T2S_5.10.csv b/resources/tests/msr/msr_list_T2S_5.10.csv
index a2faab71cea..26f28e5a82a 100644
--- a/resources/tests/msr/msr_list_T2S_5.10.csv
+++ b/resources/tests/msr/msr_list_T2S_5.10.csv
@@ -265,7 +265,7 @@ MSR_ADDR,STATUS,VALUE
 0x107,unimplemented,0x0
 0x108,unimplemented,0x0
 0x109,unimplemented,0x0
-0x10a,implemented,0xc4c
+0x10a,implemented,0x80c4c
 0x10b,unimplemented,0x0
 0x10c,unimplemented,0x0
 0x10d,unimplemented,0x0
diff --git a/src/cpuid/src/template/intel/t2s.rs b/src/cpuid/src/template/intel/t2s.rs
index d6a4ed43a26..4f3b9638868 100644
--- a/src/cpuid/src/template/intel/t2s.rs
+++ b/src/cpuid/src/template/intel/t2s.rs
@@ -35,7 +35,8 @@ pub fn update_msr_entries(msr_entries: &mut Vec<kvm_msr_entry>) {
         | ArchCapaMSRFlags::SKIP_L1DFL_VMENTRY
         | ArchCapaMSRFlags::IF_PSCHANGE_MC_NO
         | ArchCapaMSRFlags::MISC_PACKAGE_CTRLS
-        | ArchCapaMSRFlags::ENERGY_FILTERING_CTL;
+        | ArchCapaMSRFlags::ENERGY_FILTERING_CTL
+        | ArchCapaMSRFlags::RRSBA;
     msr_entries.push(kvm_msr_entry {
         index: MSR_IA32_ARCH_CAPABILITIES,
         data: capabilities.bits(),