From 5a162eed16c0e4d99e01ef4356aa737f07a8a4d0 Mon Sep 17 00:00:00 2001 From: Egor Lazarchuk Date: Wed, 26 Feb 2025 17:00:16 +0000 Subject: [PATCH 1/3] feat: add support got Graviton 4 cpu detection First step to test m8g is to identify if you run on m8g. Signed-off-by: Egor Lazarchuk --- tests/framework/utils_cpuid.py | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/tests/framework/utils_cpuid.py b/tests/framework/utils_cpuid.py index dabfb220240..979f4478c8b 100644 --- a/tests/framework/utils_cpuid.py +++ b/tests/framework/utils_cpuid.py @@ -28,6 +28,7 @@ class CpuModel(str, Enum): AMD_GENOA = "AMD_GENOA" ARM_NEOVERSE_N1 = "ARM_NEOVERSE_N1" ARM_NEOVERSE_V1 = "ARM_NEOVERSE_V1" + ARM_NEOVERSE_V2 = "ARM_NEOVERSE_V2" INTEL_SKYLAKE = "INTEL_SKYLAKE" INTEL_CASCADELAKE = "INTEL_CASCADELAKE" INTEL_ICELAKE = "INTEL_ICELAKE" @@ -41,7 +42,11 @@ class CpuModel(str, Enum): "Intel(R) Xeon(R) Platinum 8375C CPU": "INTEL_ICELAKE", }, CpuVendor.AMD: {"AMD EPYC 7R13": "AMD_MILAN", "AMD EPYC 9R14": "AMD_GENOA"}, - CpuVendor.ARM: {"0xd0c": "ARM_NEOVERSE_N1", "0xd40": "ARM_NEOVERSE_V1"}, + CpuVendor.ARM: { + "0xd0c": "ARM_NEOVERSE_N1", + "0xd40": "ARM_NEOVERSE_V1", + "0xd4f": "ARM_NEOVERSE_V2", + }, } From 429152d3559f178d460a8fedf2011fb2ca987689 Mon Sep 17 00:00:00 2001 From: Egor Lazarchuk Date: Wed, 26 Feb 2025 14:40:57 +0000 Subject: [PATCH 2/3] feat: add Graviton 4 guest cpu features Add new set of guest features specific for graviton 4. Signed-off-by: Egor Lazarchuk --- .../integration_tests/functional/test_cpu_features_aarch64.py | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/tests/integration_tests/functional/test_cpu_features_aarch64.py b/tests/integration_tests/functional/test_cpu_features_aarch64.py index 2068194a894..5b667d0b34d 100644 --- a/tests/integration_tests/functional/test_cpu_features_aarch64.py +++ b/tests/integration_tests/functional/test_cpu_features_aarch64.py @@ -24,6 +24,8 @@ G3_SVE_AND_PAC = set("paca pacg sve svebf16 svei8mm".split()) +G4_FEATS = (G3_FEATS | set("bti flagm2 frint sb".split())) - set("sm3 sm4".split()) + def test_guest_cpu_features(uvm_any): """Check the CPU features for a microvm with different CPU templates""" @@ -43,6 +45,8 @@ def test_guest_cpu_features(uvm_any): expected_cpu_features = G3_FEATS | G3_SVE_AND_PAC case CpuModel.ARM_NEOVERSE_V1, None: expected_cpu_features = G3_FEATS + case CpuModel.ARM_NEOVERSE_V2, None: + expected_cpu_features = G4_FEATS guest_feats = set(vm.ssh.check_output(CPU_FEATURES_CMD).stdout.split()) assert guest_feats == expected_cpu_features From f6994595873ddb65c206d1b54e5f557e53d3c838 Mon Sep 17 00:00:00 2001 From: Egor Lazarchuk Date: Wed, 26 Feb 2025 16:53:55 +0000 Subject: [PATCH 3/3] feat: add Graviton 4 host vs guest cpu difference Add additional Graviton 4 cpu features to the host vs guest test. Signed-off-by: Egor Lazarchuk --- .../functional/test_cpu_features_host_vs_guest.py | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/tests/integration_tests/functional/test_cpu_features_host_vs_guest.py b/tests/integration_tests/functional/test_cpu_features_host_vs_guest.py index d2fd4936328..c8075faa505 100644 --- a/tests/integration_tests/functional/test_cpu_features_host_vs_guest.py +++ b/tests/integration_tests/functional/test_cpu_features_host_vs_guest.py @@ -257,12 +257,21 @@ def test_host_vs_guest_cpu_features(uvm_nano): assert host_feats - guest_feats == expected_host_minus_guest assert guest_feats - host_feats == expected_guest_minus_host - case CpuModel.ARM_NEOVERSE_V1: + case CpuModel.ARM_NEOVERSE_V1 | CpuModel.ARM_NEOVERSE_V2: expected_guest_minus_host = set() # KVM does not enable PAC or SVE features by default # and Firecracker does not enable them either. expected_host_minus_guest = {"paca", "pacg", "sve", "svebf16", "svei8mm"} + if CPU_MODEL == CpuModel.ARM_NEOVERSE_V2: + expected_host_minus_guest |= { + "svebitperm", + "svesha3", + "sveaes", + "sve2", + "svepmull", + } + # Upstream kernel v6.11+ hides "ssbs" from "lscpu" on Neoverse-N1 and Neoverse-V1 since # they have an errata whereby an MSR to the SSBS special-purpose register does not # affect subsequent speculative instructions, permitting speculative store bypassing for