From 889ea0e14fcecb8ec306f50308019d740b4fa34d Mon Sep 17 00:00:00 2001 From: Takahiro Itazuri Date: Mon, 24 Nov 2025 10:30:26 +0000 Subject: [PATCH 1/3] test: Update MSR baseline We got to specify IA32_MTRRdefType MSR to allow guest OS to set page attributes for memory regions, which cause guest OS to chage IA32_PAT MSR value. Note that we don't need to add IA32_PAT MSR to the exception list because guest OS always set the same value to it and it doesn't change every boot. Rather, by keeping monitoring it, we may be able to catch changes caused by guest OS updates. [1]: https://github.com/firecracker-microvm/firecracker/pull/5526 Signed-off-by: Takahiro Itazuri --- ...TEL_SAPPHIRE_RAPIDS_5.10host_5.10guest.csv | 14 ++++++------- ...NTEL_SAPPHIRE_RAPIDS_5.10host_6.1guest.csv | 18 ++++++++--------- ...NTEL_SAPPHIRE_RAPIDS_6.1host_5.10guest.csv | 14 ++++++------- ...INTEL_SAPPHIRE_RAPIDS_6.1host_6.1guest.csv | 18 ++++++++--------- ..._list_T2A_AMD_MILAN_5.10host_5.10guest.csv | 20 +++++++++---------- ...r_list_T2A_AMD_MILAN_5.10host_6.1guest.csv | 20 +++++++++---------- ...r_list_T2A_AMD_MILAN_6.1host_5.10guest.csv | 14 ++++++------- ...sr_list_T2A_AMD_MILAN_6.1host_6.1guest.csv | 20 +++++++++---------- ...L_INTEL_CASCADELAKE_5.10host_5.10guest.csv | 20 +++++++++---------- ...CL_INTEL_CASCADELAKE_5.10host_6.1guest.csv | 20 +++++++++---------- ...CL_INTEL_CASCADELAKE_6.1host_5.10guest.csv | 20 +++++++++---------- ...2CL_INTEL_CASCADELAKE_6.1host_6.1guest.csv | 20 +++++++++---------- ..._T2CL_INTEL_ICELAKE_5.10host_5.10guest.csv | 20 +++++++++---------- ...t_T2CL_INTEL_ICELAKE_5.10host_6.1guest.csv | 20 +++++++++---------- ...t_T2CL_INTEL_ICELAKE_6.1host_5.10guest.csv | 20 +++++++++---------- ...st_T2CL_INTEL_ICELAKE_6.1host_6.1guest.csv | 20 +++++++++---------- ...S_INTEL_CASCADELAKE_5.10host_5.10guest.csv | 20 +++++++++---------- ...2S_INTEL_CASCADELAKE_5.10host_6.1guest.csv | 20 +++++++++---------- ...2S_INTEL_CASCADELAKE_6.1host_5.10guest.csv | 20 +++++++++---------- ...T2S_INTEL_CASCADELAKE_6.1host_6.1guest.csv | 20 +++++++++---------- 20 files changed, 189 insertions(+), 189 deletions(-) diff --git a/tests/data/msr/msr_list_SPR_TO_T2_5.10_INTEL_SAPPHIRE_RAPIDS_5.10host_5.10guest.csv b/tests/data/msr/msr_list_SPR_TO_T2_5.10_INTEL_SAPPHIRE_RAPIDS_5.10host_5.10guest.csv index b7dbb17cdef..416d10d55f0 100644 --- a/tests/data/msr/msr_list_SPR_TO_T2_5.10_INTEL_SAPPHIRE_RAPIDS_5.10host_5.10guest.csv +++ b/tests/data/msr/msr_list_SPR_TO_T2_5.10_INTEL_SAPPHIRE_RAPIDS_5.10host_5.10guest.csv @@ -1,9 +1,9 @@ MSR_ADDR,VALUE 0x0,0x0 0x1,0x0 -0x10,0x7e1358a6 -0x11,0x24b8008 -0x12,0x24b9001 +0x10,0x1014d0f7c +0x11,0x24cb008 +0x12,0x24cc001 0x17,0x0 0x1b,0xfee00d00 0x2a,0x0 @@ -65,8 +65,8 @@ MSR_ADDR,VALUE 0x26d,0x0 0x26e,0x0 0x26f,0x0 -0x277,0x7040600070406 -0x2ff,0x0 +0x277,0x407050600070106 +0x2ff,0x806 0x400,0x0 0x401,0x0 0x402,0x0 @@ -200,7 +200,7 @@ MSR_ADDR,VALUE 0x619,0x0 0x639,0x0 0x641,0x0 -0x6e0,0x14bdb6296 +0x6e0,0x101d7c3a2 0x800,0x0 0x801,0x0 0x802,0x0 @@ -462,7 +462,7 @@ MSR_ADDR,VALUE 0xc0000082,0xffffffff81a00080 0xc0000083,0xffffffff81a015c0 0xc0000084,0x47700 -0xc0000100,0x7f0fa9f42740 +0xc0000100,0x6c49380 0xc0000101,0xffff88803ec00000 0xc0000102,0x0 0xc0000103,0x0 diff --git a/tests/data/msr/msr_list_SPR_TO_T2_5.10_INTEL_SAPPHIRE_RAPIDS_5.10host_6.1guest.csv b/tests/data/msr/msr_list_SPR_TO_T2_5.10_INTEL_SAPPHIRE_RAPIDS_5.10host_6.1guest.csv index a95b4a6e1e8..508a22bc964 100644 --- a/tests/data/msr/msr_list_SPR_TO_T2_5.10_INTEL_SAPPHIRE_RAPIDS_5.10host_6.1guest.csv +++ b/tests/data/msr/msr_list_SPR_TO_T2_5.10_INTEL_SAPPHIRE_RAPIDS_5.10host_6.1guest.csv @@ -1,9 +1,9 @@ MSR_ADDR,VALUE 0x0,0x0 0x1,0x0 -0x10,0x6f36e74e -0x11,0x25cb008 -0x12,0x25cc001 +0x10,0xd2097b66 +0x11,0x27fd008 +0x12,0x27fe001 0x17,0x0 0x1b,0xfee00d00 0x2a,0x0 @@ -24,7 +24,7 @@ MSR_ADDR,VALUE 0x140,0x0 0x174,0x10 0x175,0xfffffe0000003000 -0x176,0xffffffff81a01620 +0x176,0xffffffff81c01630 0x179,0x20 0x17a,0x0 0x186,0x0 @@ -65,8 +65,8 @@ MSR_ADDR,VALUE 0x26d,0x0 0x26e,0x0 0x26f,0x0 -0x277,0x7040600070406 -0x2ff,0x0 +0x277,0x407050600070106 +0x2ff,0x806 0x400,0x0 0x401,0x0 0x402,0x0 @@ -200,7 +200,7 @@ MSR_ADDR,VALUE 0x619,0x0 0x639,0x0 0x641,0x0 -0x6e0,0x13b15c936 +0x6e0,0xd2b602dc 0x800,0x0 0x801,0x0 0x802,0x0 @@ -459,10 +459,10 @@ MSR_ADDR,VALUE 0x8ff,0x0 0xc0000080,0xd01 0xc0000081,0x23001000000000 -0xc0000082,0xffffffff81a00080 +0xc0000082,0xffffffff81c00080 0xc0000083,0x0 0xc0000084,0x257fd5 -0xc0000100,0x7f9c1c8ac740 +0xc0000100,0x592380 0xc0000101,0xffff88803ec00000 0xc0000102,0x0 0xc0000103,0x0 diff --git a/tests/data/msr/msr_list_SPR_TO_T2_6.1_INTEL_SAPPHIRE_RAPIDS_6.1host_5.10guest.csv b/tests/data/msr/msr_list_SPR_TO_T2_6.1_INTEL_SAPPHIRE_RAPIDS_6.1host_5.10guest.csv index b9eb3de2a59..f579777a139 100644 --- a/tests/data/msr/msr_list_SPR_TO_T2_6.1_INTEL_SAPPHIRE_RAPIDS_6.1host_5.10guest.csv +++ b/tests/data/msr/msr_list_SPR_TO_T2_6.1_INTEL_SAPPHIRE_RAPIDS_6.1host_5.10guest.csv @@ -1,9 +1,9 @@ MSR_ADDR,VALUE 0x0,0x0 0x1,0x0 -0x10,0x7c90dcf2 -0x11,0x24a1008 -0x12,0x24a2001 +0x10,0x12d75c18e +0x11,0x24cb008 +0x12,0x24cc001 0x17,0x0 0x1b,0xfee00d00 0x2a,0x0 @@ -65,8 +65,8 @@ MSR_ADDR,VALUE 0x26d,0x0 0x26e,0x0 0x26f,0x0 -0x277,0x7040600070406 -0x2ff,0x0 +0x277,0x407050600070106 +0x2ff,0x806 0x400,0x0 0x401,0x0 0x402,0x0 @@ -200,7 +200,7 @@ MSR_ADDR,VALUE 0x619,0x0 0x639,0x0 0x641,0x0 -0x6e0,0x7d409184 +0x6e0,0x12e64deb6 0x800,0x0 0x801,0x0 0x802,0x0 @@ -462,7 +462,7 @@ MSR_ADDR,VALUE 0xc0000082,0xffffffff81a00080 0xc0000083,0xffffffff81a015c0 0xc0000084,0x47700 -0xc0000100,0x3d11f380 +0xc0000100,0x3402d380 0xc0000101,0xffff88803ec00000 0xc0000102,0x0 0xc0000103,0x0 diff --git a/tests/data/msr/msr_list_SPR_TO_T2_6.1_INTEL_SAPPHIRE_RAPIDS_6.1host_6.1guest.csv b/tests/data/msr/msr_list_SPR_TO_T2_6.1_INTEL_SAPPHIRE_RAPIDS_6.1host_6.1guest.csv index d8e39b1d2fb..c844cf63c1f 100644 --- a/tests/data/msr/msr_list_SPR_TO_T2_6.1_INTEL_SAPPHIRE_RAPIDS_6.1host_6.1guest.csv +++ b/tests/data/msr/msr_list_SPR_TO_T2_6.1_INTEL_SAPPHIRE_RAPIDS_6.1host_6.1guest.csv @@ -1,9 +1,9 @@ MSR_ADDR,VALUE 0x0,0x0 0x1,0x0 -0x10,0x6f38b066 -0x11,0x25cb008 -0x12,0x25cc001 +0x10,0xcecb4324 +0x11,0x27fd008 +0x12,0x27fe001 0x17,0x0 0x1b,0xfee00d00 0x2a,0x0 @@ -24,7 +24,7 @@ MSR_ADDR,VALUE 0x140,0x0 0x174,0x10 0x175,0xfffffe0000003000 -0x176,0xffffffff81a01620 +0x176,0xffffffff81c01630 0x179,0x20 0x17a,0x0 0x186,0x0 @@ -65,8 +65,8 @@ MSR_ADDR,VALUE 0x26d,0x0 0x26e,0x0 0x26f,0x0 -0x277,0x7040600070406 -0x2ff,0x0 +0x277,0x407050600070106 +0x2ff,0x806 0x400,0x0 0x401,0x0 0x402,0x0 @@ -200,7 +200,7 @@ MSR_ADDR,VALUE 0x619,0x0 0x639,0x0 0x641,0x0 -0x6e0,0x6f8e7c12 +0x6e0,0xcf54a28e 0x800,0x0 0x801,0x0 0x802,0x0 @@ -459,10 +459,10 @@ MSR_ADDR,VALUE 0x8ff,0x0 0xc0000080,0xd01 0xc0000081,0x23001000000000 -0xc0000082,0xffffffff81a00080 +0xc0000082,0xffffffff81c00080 0xc0000083,0x0 0xc0000084,0x257fd5 -0xc0000100,0x14cb9380 +0xc0000100,0x31d67380 0xc0000101,0xffff88803ec00000 0xc0000102,0x0 0xc0000103,0x0 diff --git a/tests/data/msr/msr_list_T2A_AMD_MILAN_5.10host_5.10guest.csv b/tests/data/msr/msr_list_T2A_AMD_MILAN_5.10host_5.10guest.csv index e99d878d100..c7a0246ff31 100644 --- a/tests/data/msr/msr_list_T2A_AMD_MILAN_5.10host_5.10guest.csv +++ b/tests/data/msr/msr_list_T2A_AMD_MILAN_5.10host_5.10guest.csv @@ -1,9 +1,9 @@ MSR_ADDR,VALUE 0x0,0x0 0x1,0x0 -0x10,0xfd7a7f6d -0x11,0x2501008 -0x12,0x2502001 +0x10,0x20a051a0c +0x11,0x24cb008 +0x12,0x24cc001 0x17,0x0 0x1b,0xfee00d00 0x2a,0x0 @@ -21,7 +21,7 @@ MSR_ADDR,VALUE 0x140,0x0 0x174,0x10 0x175,0xfffffe0000003000 -0x176,0xffffffff81601450 +0x176,0xffffffff81a01510 0x179,0x20 0x17a,0x0 0x186,0x0 @@ -62,8 +62,8 @@ MSR_ADDR,VALUE 0x26d,0x0 0x26e,0x0 0x26f,0x0 -0x277,0x7040600070406 -0x2ff,0x0 +0x277,0x407050600070106 +0x2ff,0x806 0x400,0x0 0x401,0x0 0x402,0x0 @@ -197,7 +197,7 @@ MSR_ADDR,VALUE 0x619,0x0 0x639,0x0 0x641,0x0 -0x6e0,0x1bc5fe0e2 +0x6e0,0x20b2717e2 0x802,0x0 0x803,0x50014 0x808,0x10 @@ -241,10 +241,10 @@ MSR_ADDR,VALUE 0x83e,0x0 0xc0000080,0xd01 0xc0000081,0x23001000000000 -0xc0000082,0xffffffff81600040 -0xc0000083,0xffffffff81601500 +0xc0000082,0xffffffff81a00080 +0xc0000083,0xffffffff81a015c0 0xc0000084,0x47700 -0xc0000100,0x7ff85489f740 +0xc0000100,0x18df1380 0xc0000101,0xffff88803ec00000 0xc0000102,0x0 0xc0000103,0x0 diff --git a/tests/data/msr/msr_list_T2A_AMD_MILAN_5.10host_6.1guest.csv b/tests/data/msr/msr_list_T2A_AMD_MILAN_5.10host_6.1guest.csv index 55ee4e401d1..bce30c9db18 100644 --- a/tests/data/msr/msr_list_T2A_AMD_MILAN_5.10host_6.1guest.csv +++ b/tests/data/msr/msr_list_T2A_AMD_MILAN_5.10host_6.1guest.csv @@ -1,9 +1,9 @@ MSR_ADDR,VALUE 0x0,0x0 0x1,0x0 -0x10,0xfd7a7f6d -0x11,0x2501008 -0x12,0x2502001 +0x10,0x13f0df111 +0x11,0x27fd008 +0x12,0x27fe001 0x17,0x0 0x1b,0xfee00d00 0x2a,0x0 @@ -21,7 +21,7 @@ MSR_ADDR,VALUE 0x140,0x0 0x174,0x10 0x175,0xfffffe0000003000 -0x176,0xffffffff81601450 +0x176,0xffffffff81c01630 0x179,0x20 0x17a,0x0 0x186,0x0 @@ -62,8 +62,8 @@ MSR_ADDR,VALUE 0x26d,0x0 0x26e,0x0 0x26f,0x0 -0x277,0x7040600070406 -0x2ff,0x0 +0x277,0x407050600070106 +0x2ff,0x806 0x400,0x0 0x401,0x0 0x402,0x0 @@ -197,7 +197,7 @@ MSR_ADDR,VALUE 0x619,0x0 0x639,0x0 0x641,0x0 -0x6e0,0x1bc5fe0e2 +0x6e0,0x14034d011 0x802,0x0 0x803,0x50014 0x808,0x10 @@ -241,10 +241,10 @@ MSR_ADDR,VALUE 0x83e,0x0 0xc0000080,0xd01 0xc0000081,0x23001000000000 -0xc0000082,0xffffffff81600040 -0xc0000083,0xffffffff81601500 +0xc0000082,0xffffffff81c00080 +0xc0000083,0xffffffff81c016f0 0xc0000084,0x257fd5 -0xc0000100,0x7ff85489f740 +0xc0000100,0x7004380 0xc0000101,0xffff88803ec00000 0xc0000102,0x0 0xc0000103,0x0 diff --git a/tests/data/msr/msr_list_T2A_AMD_MILAN_6.1host_5.10guest.csv b/tests/data/msr/msr_list_T2A_AMD_MILAN_6.1host_5.10guest.csv index b7e64457995..5ee57872b88 100644 --- a/tests/data/msr/msr_list_T2A_AMD_MILAN_6.1host_5.10guest.csv +++ b/tests/data/msr/msr_list_T2A_AMD_MILAN_6.1host_5.10guest.csv @@ -1,9 +1,9 @@ MSR_ADDR,VALUE 0x0,0x0 0x1,0x0 -0x10,0x91048477 -0x11,0x24a1008 -0x12,0x24a2001 +0x10,0x13df71122 +0x11,0x24e6008 +0x12,0x24e7001 0x17,0x0 0x1b,0xfee00d00 0x2a,0x0 @@ -62,8 +62,8 @@ MSR_ADDR,VALUE 0x26d,0x0 0x26e,0x0 0x26f,0x0 -0x277,0x7040600070406 -0x2ff,0x0 +0x277,0x407050600070106 +0x2ff,0x806 0x400,0x0 0x401,0x0 0x402,0x0 @@ -197,7 +197,7 @@ MSR_ADDR,VALUE 0x619,0x0 0x639,0x0 0x641,0x0 -0x6e0,0x91ac122f +0x6e0,0x13e9cecf6 0x802,0x0 0x803,0x50014 0x808,0x10 @@ -244,7 +244,7 @@ MSR_ADDR,VALUE 0xc0000082,0xffffffff81a00080 0xc0000083,0xffffffff81a015c0 0xc0000084,0x47700 -0xc0000100,0x369e2380 +0xc0000100,0x29a0c380 0xc0000101,0xffff88803ec00000 0xc0000102,0x0 0xc0000103,0x0 diff --git a/tests/data/msr/msr_list_T2A_AMD_MILAN_6.1host_6.1guest.csv b/tests/data/msr/msr_list_T2A_AMD_MILAN_6.1host_6.1guest.csv index 9d40e380ef1..f7cc8d04ebe 100644 --- a/tests/data/msr/msr_list_T2A_AMD_MILAN_6.1host_6.1guest.csv +++ b/tests/data/msr/msr_list_T2A_AMD_MILAN_6.1host_6.1guest.csv @@ -1,9 +1,9 @@ MSR_ADDR,VALUE 0x0,0x0 0x1,0x0 -0x10,0x8ae2ee59 -0x11,0x25cb008 -0x12,0x25cc001 +0x10,0x12a9d3006 +0x11,0x27fd008 +0x12,0x27fe001 0x17,0x0 0x1b,0xfee00d00 0x2a,0x0 @@ -21,7 +21,7 @@ MSR_ADDR,VALUE 0x140,0x0 0x174,0x10 0x175,0x3000 -0x176,0x81a01620 +0x176,0x81c01630 0x179,0x20 0x17a,0x0 0x186,0x0 @@ -62,8 +62,8 @@ MSR_ADDR,VALUE 0x26d,0x0 0x26e,0x0 0x26f,0x0 -0x277,0x7040600070406 -0x2ff,0x0 +0x277,0x407050600070106 +0x2ff,0x806 0x400,0x0 0x401,0x0 0x402,0x0 @@ -197,7 +197,7 @@ MSR_ADDR,VALUE 0x619,0x0 0x639,0x0 0x641,0x0 -0x6e0,0x8b556120 +0x6e0,0x12b7e327c 0x802,0x0 0x803,0x50014 0x808,0x10 @@ -241,10 +241,10 @@ MSR_ADDR,VALUE 0x83e,0x0 0xc0000080,0xd01 0xc0000081,0x23001000000000 -0xc0000082,0xffffffff81a00080 -0xc0000083,0xffffffff81a016e0 +0xc0000082,0xffffffff81c00080 +0xc0000083,0xffffffff81c016f0 0xc0000084,0x257fd5 -0xc0000100,0x3279380 +0xc0000100,0x344cb380 0xc0000101,0xffff88803ec00000 0xc0000102,0x0 0xc0000103,0x0 diff --git a/tests/data/msr/msr_list_T2CL_INTEL_CASCADELAKE_5.10host_5.10guest.csv b/tests/data/msr/msr_list_T2CL_INTEL_CASCADELAKE_5.10host_5.10guest.csv index b9f669e2db9..5afa7c8d626 100644 --- a/tests/data/msr/msr_list_T2CL_INTEL_CASCADELAKE_5.10host_5.10guest.csv +++ b/tests/data/msr/msr_list_T2CL_INTEL_CASCADELAKE_5.10host_5.10guest.csv @@ -1,9 +1,9 @@ MSR_ADDR,VALUE 0x0,0x0 0x1,0x0 -0x10,0xbe7f66e8 -0x11,0x2748008 -0x12,0x2749001 +0x10,0x15dc62d60 +0x11,0x24cb008 +0x12,0x24cc001 0x17,0x0 0x1b,0xfee00d00 0x2a,0x0 @@ -24,7 +24,7 @@ MSR_ADDR,VALUE 0x140,0x0 0x174,0x10 0x175,0xfffffe0000003000 -0x176,0xffffffff81801450 +0x176,0xffffffff81a01510 0x179,0x20 0x17a,0x0 0x186,0x0 @@ -65,8 +65,8 @@ MSR_ADDR,VALUE 0x26d,0x0 0x26e,0x0 0x26f,0x0 -0x277,0x7040600070406 -0x2ff,0x0 +0x277,0x407050600070106 +0x2ff,0x806 0x400,0x0 0x401,0x0 0x402,0x0 @@ -200,7 +200,7 @@ MSR_ADDR,VALUE 0x619,0x0 0x639,0x0 0x641,0x0 -0x6e0,0x1e27998b4 +0x6e0,0x15ea1f8d0 0x800,0x0 0x801,0x0 0x802,0x0 @@ -459,10 +459,10 @@ MSR_ADDR,VALUE 0x8ff,0x0 0xc0000080,0xd01 0xc0000081,0x23001000000000 -0xc0000082,0xffffffff81800040 -0xc0000083,0xffffffff81801500 +0xc0000082,0xffffffff81a00080 +0xc0000083,0xffffffff81a015c0 0xc0000084,0x47700 -0xc0000100,0x7f6a7d9dd740 +0xc0000100,0x1de55380 0xc0000101,0xffff88803ec00000 0xc0000102,0x0 0xc0000103,0x0 diff --git a/tests/data/msr/msr_list_T2CL_INTEL_CASCADELAKE_5.10host_6.1guest.csv b/tests/data/msr/msr_list_T2CL_INTEL_CASCADELAKE_5.10host_6.1guest.csv index 80cb763e988..cfb9a2bd4f6 100644 --- a/tests/data/msr/msr_list_T2CL_INTEL_CASCADELAKE_5.10host_6.1guest.csv +++ b/tests/data/msr/msr_list_T2CL_INTEL_CASCADELAKE_5.10host_6.1guest.csv @@ -1,9 +1,9 @@ MSR_ADDR,VALUE 0x0,0x0 0x1,0x0 -0x10,0xbe7f66e8 -0x11,0x2748008 -0x12,0x2749001 +0x10,0x1337dcd0a +0x11,0x27fd008 +0x12,0x27fe001 0x17,0x0 0x1b,0xfee00d00 0x2a,0x0 @@ -24,7 +24,7 @@ MSR_ADDR,VALUE 0x140,0x0 0x174,0x10 0x175,0xfffffe0000003000 -0x176,0xffffffff81801450 +0x176,0xffffffff81c01630 0x179,0x20 0x17a,0x0 0x186,0x0 @@ -65,8 +65,8 @@ MSR_ADDR,VALUE 0x26d,0x0 0x26e,0x0 0x26f,0x0 -0x277,0x7040600070406 -0x2ff,0x0 +0x277,0x407050600070106 +0x2ff,0x806 0x400,0x0 0x401,0x0 0x402,0x0 @@ -200,7 +200,7 @@ MSR_ADDR,VALUE 0x619,0x0 0x639,0x0 0x641,0x0 -0x6e0,0x1e27998b4 +0x6e0,0x13444450a 0x800,0x0 0x801,0x0 0x802,0x0 @@ -459,10 +459,10 @@ MSR_ADDR,VALUE 0x8ff,0x0 0xc0000080,0xd01 0xc0000081,0x23001000000000 -0xc0000082,0xffffffff81800040 -0xc0000083,0xffffffff81801500 +0xc0000082,0xffffffff81c00080 +0xc0000083,0x0 0xc0000084,0x257fd5 -0xc0000100,0x7f6a7d9dd740 +0xc0000100,0x5660380 0xc0000101,0xffff88803ec00000 0xc0000102,0x0 0xc0000103,0x0 diff --git a/tests/data/msr/msr_list_T2CL_INTEL_CASCADELAKE_6.1host_5.10guest.csv b/tests/data/msr/msr_list_T2CL_INTEL_CASCADELAKE_6.1host_5.10guest.csv index 87492873df0..7b21869db44 100644 --- a/tests/data/msr/msr_list_T2CL_INTEL_CASCADELAKE_6.1host_5.10guest.csv +++ b/tests/data/msr/msr_list_T2CL_INTEL_CASCADELAKE_6.1host_5.10guest.csv @@ -1,9 +1,9 @@ MSR_ADDR,VALUE 0x0,0x0 0x1,0x0 -0x10,0xf8c468e6 -0x11,0x2502008 -0x12,0x2503001 +0x10,0x13c845eb6 +0x11,0x24e6008 +0x12,0x24e7001 0x17,0x0 0x1b,0xfee00d00 0x2a,0x0 @@ -24,7 +24,7 @@ MSR_ADDR,VALUE 0x140,0x0 0x174,0x10 0x175,0xfffffe0000003000 -0x176,0xffffffff81601450 +0x176,0xffffffff81a01510 0x179,0x20 0x17a,0x0 0x186,0x0 @@ -65,8 +65,8 @@ MSR_ADDR,VALUE 0x26d,0x0 0x26e,0x0 0x26f,0x0 -0x277,0x7040600070406 -0x2ff,0x0 +0x277,0x407050600070106 +0x2ff,0x806 0x400,0x0 0x401,0x0 0x402,0x0 @@ -200,7 +200,7 @@ MSR_ADDR,VALUE 0x619,0x0 0x639,0x0 0x641,0x0 -0x6e0,0x2188bb06a +0x6e0,0x13d1abfbe 0x800,0x0 0x801,0x0 0x802,0x0 @@ -459,10 +459,10 @@ MSR_ADDR,VALUE 0x8ff,0x0 0xc0000080,0xd01 0xc0000081,0x23001000000000 -0xc0000082,0xffffffff81600040 -0xc0000083,0xffffffff81601500 +0xc0000082,0xffffffff81a00080 +0xc0000083,0xffffffff81a015c0 0xc0000084,0x47700 -0xc0000100,0x7fe9b31fd740 +0xc0000100,0x2820b380 0xc0000101,0xffff88803ec00000 0xc0000102,0x0 0xc0000103,0x0 diff --git a/tests/data/msr/msr_list_T2CL_INTEL_CASCADELAKE_6.1host_6.1guest.csv b/tests/data/msr/msr_list_T2CL_INTEL_CASCADELAKE_6.1host_6.1guest.csv index 60b90877f14..648b37aebca 100644 --- a/tests/data/msr/msr_list_T2CL_INTEL_CASCADELAKE_6.1host_6.1guest.csv +++ b/tests/data/msr/msr_list_T2CL_INTEL_CASCADELAKE_6.1host_6.1guest.csv @@ -1,9 +1,9 @@ MSR_ADDR,VALUE 0x0,0x0 0x1,0x0 -0x10,0xf8c468e6 -0x11,0x2502008 -0x12,0x2503001 +0x10,0x1324e0ba2 +0x11,0x27fd008 +0x12,0x27fe001 0x17,0x0 0x1b,0xfee00d00 0x2a,0x0 @@ -24,7 +24,7 @@ MSR_ADDR,VALUE 0x140,0x0 0x174,0x10 0x175,0xfffffe0000003000 -0x176,0xffffffff81601450 +0x176,0xffffffff81c01630 0x179,0x20 0x17a,0x0 0x186,0x0 @@ -65,8 +65,8 @@ MSR_ADDR,VALUE 0x26d,0x0 0x26e,0x0 0x26f,0x0 -0x277,0x7040600070406 -0x2ff,0x0 +0x277,0x407050600070106 +0x2ff,0x806 0x400,0x0 0x401,0x0 0x402,0x0 @@ -200,7 +200,7 @@ MSR_ADDR,VALUE 0x619,0x0 0x639,0x0 0x641,0x0 -0x6e0,0x2188bb06a +0x6e0,0x132f90c4a 0x800,0x0 0x801,0x0 0x802,0x0 @@ -459,10 +459,10 @@ MSR_ADDR,VALUE 0x8ff,0x0 0xc0000080,0xd01 0xc0000081,0x23001000000000 -0xc0000082,0xffffffff81600040 -0xc0000083,0xffffffff81601500 +0xc0000082,0xffffffff81c00080 +0xc0000083,0x0 0xc0000084,0x257fd5 -0xc0000100,0x7fe9b31fd740 +0xc0000100,0x3c223380 0xc0000101,0xffff88803ec00000 0xc0000102,0x0 0xc0000103,0x0 diff --git a/tests/data/msr/msr_list_T2CL_INTEL_ICELAKE_5.10host_5.10guest.csv b/tests/data/msr/msr_list_T2CL_INTEL_ICELAKE_5.10host_5.10guest.csv index 77603710923..b9f68165ea0 100644 --- a/tests/data/msr/msr_list_T2CL_INTEL_ICELAKE_5.10host_5.10guest.csv +++ b/tests/data/msr/msr_list_T2CL_INTEL_ICELAKE_5.10host_5.10guest.csv @@ -1,9 +1,9 @@ MSR_ADDR,VALUE 0x0,0x0 0x1,0x0 -0x10,0x114970c7a -0x11,0x2502008 -0x12,0x2503001 +0x10,0x237a664c4 +0x11,0x24e6008 +0x12,0x24e7001 0x17,0x0 0x1b,0xfee00d00 0x2a,0x0 @@ -24,7 +24,7 @@ MSR_ADDR,VALUE 0x140,0x0 0x174,0x10 0x175,0xfffffe0000003000 -0x176,0xffffffff81601450 +0x176,0xffffffff81a01510 0x179,0x20 0x17a,0x0 0x186,0x0 @@ -65,8 +65,8 @@ MSR_ADDR,VALUE 0x26d,0x0 0x26e,0x0 0x26f,0x0 -0x277,0x7040600070406 -0x2ff,0x0 +0x277,0x407050600070106 +0x2ff,0x806 0x400,0x0 0x401,0x0 0x402,0x0 @@ -200,7 +200,7 @@ MSR_ADDR,VALUE 0x619,0x0 0x639,0x0 0x641,0x0 -0x6e0,0x21a0368a2 +0x6e0,0x238d35bf2 0x800,0x0 0x801,0x0 0x802,0x0 @@ -459,10 +459,10 @@ MSR_ADDR,VALUE 0x8ff,0x0 0xc0000080,0xd01 0xc0000081,0x23001000000000 -0xc0000082,0xffffffff81600040 -0xc0000083,0xffffffff81601500 +0xc0000082,0xffffffff81a00080 +0xc0000083,0xffffffff81a015c0 0xc0000084,0x47700 -0xc0000100,0x7f8958489740 +0xc0000100,0x3f300380 0xc0000101,0xffff88803ec00000 0xc0000102,0x0 0xc0000103,0x0 diff --git a/tests/data/msr/msr_list_T2CL_INTEL_ICELAKE_5.10host_6.1guest.csv b/tests/data/msr/msr_list_T2CL_INTEL_ICELAKE_5.10host_6.1guest.csv index 95c5c5aa987..d63f8277c98 100644 --- a/tests/data/msr/msr_list_T2CL_INTEL_ICELAKE_5.10host_6.1guest.csv +++ b/tests/data/msr/msr_list_T2CL_INTEL_ICELAKE_5.10host_6.1guest.csv @@ -1,9 +1,9 @@ MSR_ADDR,VALUE 0x0,0x0 0x1,0x0 -0x10,0x114970c7a -0x11,0x2502008 -0x12,0x2503001 +0x10,0x11a6f98c0 +0x11,0x27fd008 +0x12,0x27fe001 0x17,0x0 0x1b,0xfee00d00 0x2a,0x0 @@ -24,7 +24,7 @@ MSR_ADDR,VALUE 0x140,0x0 0x174,0x10 0x175,0xfffffe0000003000 -0x176,0xffffffff81601450 +0x176,0xffffffff81c01630 0x179,0x20 0x17a,0x0 0x186,0x0 @@ -65,8 +65,8 @@ MSR_ADDR,VALUE 0x26d,0x0 0x26e,0x0 0x26f,0x0 -0x277,0x7040600070406 -0x2ff,0x0 +0x277,0x407050600070106 +0x2ff,0x806 0x400,0x0 0x401,0x0 0x402,0x0 @@ -200,7 +200,7 @@ MSR_ADDR,VALUE 0x619,0x0 0x639,0x0 0x641,0x0 -0x6e0,0x21a0368a2 +0x6e0,0x11b19f31e 0x800,0x0 0x801,0x0 0x802,0x0 @@ -459,10 +459,10 @@ MSR_ADDR,VALUE 0x8ff,0x0 0xc0000080,0xd01 0xc0000081,0x23001000000000 -0xc0000082,0xffffffff81600040 -0xc0000083,0xffffffff81601500 +0xc0000082,0xffffffff81c00080 +0xc0000083,0x0 0xc0000084,0x257fd5 -0xc0000100,0x7f8958489740 +0xc0000100,0x302e7380 0xc0000101,0xffff88803ec00000 0xc0000102,0x0 0xc0000103,0x0 diff --git a/tests/data/msr/msr_list_T2CL_INTEL_ICELAKE_6.1host_5.10guest.csv b/tests/data/msr/msr_list_T2CL_INTEL_ICELAKE_6.1host_5.10guest.csv index bbf58bcee35..c868ab6d856 100644 --- a/tests/data/msr/msr_list_T2CL_INTEL_ICELAKE_6.1host_5.10guest.csv +++ b/tests/data/msr/msr_list_T2CL_INTEL_ICELAKE_6.1host_5.10guest.csv @@ -1,9 +1,9 @@ MSR_ADDR,VALUE 0x0,0x0 0x1,0x0 -0x10,0x119817846 -0x11,0x2748008 -0x12,0x2749001 +0x10,0x15bd5f0d0 +0x11,0x24e6008 +0x12,0x24e7001 0x17,0x0 0x1b,0xfee00d00 0x2a,0x0 @@ -24,7 +24,7 @@ MSR_ADDR,VALUE 0x140,0x0 0x174,0x10 0x175,0xfffffe0000003000 -0x176,0xffffffff81801450 +0x176,0xffffffff81a01510 0x179,0x20 0x17a,0x0 0x186,0x0 @@ -65,8 +65,8 @@ MSR_ADDR,VALUE 0x26d,0x0 0x26e,0x0 0x26f,0x0 -0x277,0x7040600070406 -0x2ff,0x0 +0x277,0x407050600070106 +0x2ff,0x806 0x400,0x0 0x401,0x0 0x402,0x0 @@ -200,7 +200,7 @@ MSR_ADDR,VALUE 0x619,0x0 0x639,0x0 0x641,0x0 -0x6e0,0x2188ab264 +0x6e0,0x15cca5b5a 0x800,0x0 0x801,0x0 0x802,0x0 @@ -459,10 +459,10 @@ MSR_ADDR,VALUE 0x8ff,0x0 0xc0000080,0xd01 0xc0000081,0x23001000000000 -0xc0000082,0xffffffff81800040 -0xc0000083,0xffffffff81801500 +0xc0000082,0xffffffff81a00080 +0xc0000083,0xffffffff81a015c0 0xc0000084,0x47700 -0xc0000100,0x7fb8f2024740 +0xc0000100,0x3c720380 0xc0000101,0xffff88803ec00000 0xc0000102,0x0 0xc0000103,0x0 diff --git a/tests/data/msr/msr_list_T2CL_INTEL_ICELAKE_6.1host_6.1guest.csv b/tests/data/msr/msr_list_T2CL_INTEL_ICELAKE_6.1host_6.1guest.csv index 0c685d44b30..0dedf6d0e76 100644 --- a/tests/data/msr/msr_list_T2CL_INTEL_ICELAKE_6.1host_6.1guest.csv +++ b/tests/data/msr/msr_list_T2CL_INTEL_ICELAKE_6.1host_6.1guest.csv @@ -1,9 +1,9 @@ MSR_ADDR,VALUE 0x0,0x0 0x1,0x0 -0x10,0x119817846 -0x11,0x2748008 -0x12,0x2749001 +0x10,0x11bc7e610 +0x11,0x27fd008 +0x12,0x27fe001 0x17,0x0 0x1b,0xfee00d00 0x2a,0x0 @@ -24,7 +24,7 @@ MSR_ADDR,VALUE 0x140,0x0 0x174,0x10 0x175,0xfffffe0000003000 -0x176,0xffffffff81801450 +0x176,0xffffffff81c01630 0x179,0x20 0x17a,0x0 0x186,0x0 @@ -65,8 +65,8 @@ MSR_ADDR,VALUE 0x26d,0x0 0x26e,0x0 0x26f,0x0 -0x277,0x7040600070406 -0x2ff,0x0 +0x277,0x407050600070106 +0x2ff,0x806 0x400,0x0 0x401,0x0 0x402,0x0 @@ -200,7 +200,7 @@ MSR_ADDR,VALUE 0x619,0x0 0x639,0x0 0x641,0x0 -0x6e0,0x2188ab264 +0x6e0,0x11c6b41d8 0x800,0x0 0x801,0x0 0x802,0x0 @@ -459,10 +459,10 @@ MSR_ADDR,VALUE 0x8ff,0x0 0xc0000080,0xd01 0xc0000081,0x23001000000000 -0xc0000082,0xffffffff81800040 -0xc0000083,0xffffffff81801500 +0xc0000082,0xffffffff81c00080 +0xc0000083,0x0 0xc0000084,0x257fd5 -0xc0000100,0x7fb8f2024740 +0xc0000100,0x11deb380 0xc0000101,0xffff88803ec00000 0xc0000102,0x0 0xc0000103,0x0 diff --git a/tests/data/msr/msr_list_T2S_INTEL_CASCADELAKE_5.10host_5.10guest.csv b/tests/data/msr/msr_list_T2S_INTEL_CASCADELAKE_5.10host_5.10guest.csv index e3b8a2a897d..0ac1a098e44 100644 --- a/tests/data/msr/msr_list_T2S_INTEL_CASCADELAKE_5.10host_5.10guest.csv +++ b/tests/data/msr/msr_list_T2S_INTEL_CASCADELAKE_5.10host_5.10guest.csv @@ -1,9 +1,9 @@ MSR_ADDR,VALUE 0x0,0x0 0x1,0x0 -0x10,0xc1aa1fac -0x11,0x2502008 -0x12,0x2503001 +0x10,0x151a50ae2 +0x11,0x24e6008 +0x12,0x24e7001 0x17,0x0 0x1b,0xfee00d00 0x2a,0x0 @@ -23,7 +23,7 @@ MSR_ADDR,VALUE 0x140,0x0 0x174,0x10 0x175,0xfffffe0000003000 -0x176,0xffffffff81601450 +0x176,0xffffffff81a01510 0x179,0x20 0x17a,0x0 0x186,0x0 @@ -64,8 +64,8 @@ MSR_ADDR,VALUE 0x26d,0x0 0x26e,0x0 0x26f,0x0 -0x277,0x7040600070406 -0x2ff,0x0 +0x277,0x407050600070106 +0x2ff,0x806 0x400,0x0 0x401,0x0 0x402,0x0 @@ -199,7 +199,7 @@ MSR_ADDR,VALUE 0x619,0x0 0x639,0x0 0x641,0x0 -0x6e0,0x235ffcde0 +0x6e0,0x15254e698 0x800,0x0 0x801,0x0 0x802,0x0 @@ -458,10 +458,10 @@ MSR_ADDR,VALUE 0x8ff,0x0 0xc0000080,0xd01 0xc0000081,0x23001000000000 -0xc0000082,0xffffffff81600040 -0xc0000083,0xffffffff81601500 +0xc0000082,0xffffffff81a00080 +0xc0000083,0xffffffff81a015c0 0xc0000084,0x47700 -0xc0000100,0x7f3ce0258740 +0xc0000100,0x1ac8380 0xc0000101,0xffff88803ec00000 0xc0000102,0x0 0xc0000103,0x0 diff --git a/tests/data/msr/msr_list_T2S_INTEL_CASCADELAKE_5.10host_6.1guest.csv b/tests/data/msr/msr_list_T2S_INTEL_CASCADELAKE_5.10host_6.1guest.csv index 04349378f2e..6deebfd2b1a 100644 --- a/tests/data/msr/msr_list_T2S_INTEL_CASCADELAKE_5.10host_6.1guest.csv +++ b/tests/data/msr/msr_list_T2S_INTEL_CASCADELAKE_5.10host_6.1guest.csv @@ -1,9 +1,9 @@ MSR_ADDR,VALUE 0x0,0x0 0x1,0x0 -0x10,0xc1aa1fac -0x11,0x2502008 -0x12,0x2503001 +0x10,0x1f40deb9a +0x11,0x27fd008 +0x12,0x27fe001 0x17,0x0 0x1b,0xfee00d00 0x2a,0x0 @@ -23,7 +23,7 @@ MSR_ADDR,VALUE 0x140,0x0 0x174,0x10 0x175,0xfffffe0000003000 -0x176,0xffffffff81601450 +0x176,0xffffffff81c01630 0x179,0x20 0x17a,0x0 0x186,0x0 @@ -64,8 +64,8 @@ MSR_ADDR,VALUE 0x26d,0x0 0x26e,0x0 0x26f,0x0 -0x277,0x7040600070406 -0x2ff,0x0 +0x277,0x407050600070106 +0x2ff,0x806 0x400,0x0 0x401,0x0 0x402,0x0 @@ -199,7 +199,7 @@ MSR_ADDR,VALUE 0x619,0x0 0x639,0x0 0x641,0x0 -0x6e0,0x235ffcde0 +0x6e0,0x1f4f53e20 0x800,0x0 0x801,0x0 0x802,0x0 @@ -458,10 +458,10 @@ MSR_ADDR,VALUE 0x8ff,0x0 0xc0000080,0xd01 0xc0000081,0x23001000000000 -0xc0000082,0xffffffff81600040 -0xc0000083,0xffffffff81601500 +0xc0000082,0xffffffff81c00080 +0xc0000083,0x0 0xc0000084,0x257fd5 -0xc0000100,0x7f3ce0258740 +0xc0000100,0x20301380 0xc0000101,0xffff88803ec00000 0xc0000102,0x0 0xc0000103,0x0 diff --git a/tests/data/msr/msr_list_T2S_INTEL_CASCADELAKE_6.1host_5.10guest.csv b/tests/data/msr/msr_list_T2S_INTEL_CASCADELAKE_6.1host_5.10guest.csv index 89a8bcf738b..09e90c70eee 100644 --- a/tests/data/msr/msr_list_T2S_INTEL_CASCADELAKE_6.1host_5.10guest.csv +++ b/tests/data/msr/msr_list_T2S_INTEL_CASCADELAKE_6.1host_5.10guest.csv @@ -1,9 +1,9 @@ MSR_ADDR,VALUE 0x0,0x0 0x1,0x0 -0x10,0xf68480f8 -0x11,0x2502008 -0x12,0x2503001 +0x10,0x1554f11b4 +0x11,0x24e6008 +0x12,0x24e7001 0x17,0x0 0x1b,0xfee00d00 0x2a,0x0 @@ -23,7 +23,7 @@ MSR_ADDR,VALUE 0x140,0x0 0x174,0x10 0x175,0xfffffe0000003000 -0x176,0xffffffff81601450 +0x176,0xffffffff81a01510 0x179,0x20 0x17a,0x0 0x186,0x0 @@ -64,8 +64,8 @@ MSR_ADDR,VALUE 0x26d,0x0 0x26e,0x0 0x26f,0x0 -0x277,0x7040600070406 -0x2ff,0x0 +0x277,0x407050600070106 +0x2ff,0x806 0x400,0x0 0x401,0x0 0x402,0x0 @@ -199,7 +199,7 @@ MSR_ADDR,VALUE 0x619,0x0 0x639,0x0 0x641,0x0 -0x6e0,0x2506c90aa +0x6e0,0x15659fdee 0x800,0x0 0x801,0x0 0x802,0x0 @@ -458,10 +458,10 @@ MSR_ADDR,VALUE 0x8ff,0x0 0xc0000080,0xd01 0xc0000081,0x23001000000000 -0xc0000082,0xffffffff81600040 -0xc0000083,0xffffffff81601500 +0xc0000082,0xffffffff81a00080 +0xc0000083,0xffffffff81a015c0 0xc0000084,0x47700 -0xc0000100,0x7f03eb8b3740 +0xc0000100,0x25c3380 0xc0000101,0xffff88803ec00000 0xc0000102,0x0 0xc0000103,0x0 diff --git a/tests/data/msr/msr_list_T2S_INTEL_CASCADELAKE_6.1host_6.1guest.csv b/tests/data/msr/msr_list_T2S_INTEL_CASCADELAKE_6.1host_6.1guest.csv index 1a13ee8d065..4a9ca9e5afd 100644 --- a/tests/data/msr/msr_list_T2S_INTEL_CASCADELAKE_6.1host_6.1guest.csv +++ b/tests/data/msr/msr_list_T2S_INTEL_CASCADELAKE_6.1host_6.1guest.csv @@ -1,9 +1,9 @@ MSR_ADDR,VALUE 0x0,0x0 0x1,0x0 -0x10,0xf68480f8 -0x11,0x2502008 -0x12,0x2503001 +0x10,0x13d3c66ee +0x11,0x27fd008 +0x12,0x27fe001 0x17,0x0 0x1b,0xfee00d00 0x2a,0x0 @@ -23,7 +23,7 @@ MSR_ADDR,VALUE 0x140,0x0 0x174,0x10 0x175,0xfffffe0000003000 -0x176,0xffffffff81601450 +0x176,0xffffffff81c01630 0x179,0x20 0x17a,0x0 0x186,0x0 @@ -64,8 +64,8 @@ MSR_ADDR,VALUE 0x26d,0x0 0x26e,0x0 0x26f,0x0 -0x277,0x7040600070406 -0x2ff,0x0 +0x277,0x407050600070106 +0x2ff,0x806 0x400,0x0 0x401,0x0 0x402,0x0 @@ -199,7 +199,7 @@ MSR_ADDR,VALUE 0x619,0x0 0x639,0x0 0x641,0x0 -0x6e0,0x2506c90aa +0x6e0,0x13de4b094 0x800,0x0 0x801,0x0 0x802,0x0 @@ -458,10 +458,10 @@ MSR_ADDR,VALUE 0x8ff,0x0 0xc0000080,0xd01 0xc0000081,0x23001000000000 -0xc0000082,0xffffffff81600040 -0xc0000083,0xffffffff81601500 +0xc0000082,0xffffffff81c00080 +0xc0000083,0x0 0xc0000084,0x257fd5 -0xc0000100,0x7f03eb8b3740 +0xc0000100,0x1e840380 0xc0000101,0xffff88803ec00000 0xc0000102,0x0 0xc0000103,0x0 From 852841d65e4be68198857434c149a27ecb754146 Mon Sep 17 00:00:00 2001 From: Takahiro Itazuri Date: Mon, 24 Nov 2025 11:46:18 +0000 Subject: [PATCH 2/3] chore: Remove 'not nonci' marker specification from PR optional test There is only one test marked as no_block_pr right now and it is test_guest_cpu_config_change. Signed-off-by: Takahiro Itazuri --- .buildkite/pipeline_pr_no_block.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.buildkite/pipeline_pr_no_block.py b/.buildkite/pipeline_pr_no_block.py index 3e34076b80c..5b0f3a0474d 100755 --- a/.buildkite/pipeline_pr_no_block.py +++ b/.buildkite/pipeline_pr_no_block.py @@ -22,7 +22,7 @@ "❓ Optional", pipeline.devtool_test( devtool_opts="--performance -c 1-10 -m 0", - pytest_opts="integration_tests/ -m 'no_block_pr and not nonci' --log-cli-level=INFO", + pytest_opts="integration_tests/ -m no_block_pr --log-cli-level=INFO", ), ) if not run_all_tests(get_changed_files()): From 8499e72031521287095492a5c45c8a867c121d40 Mon Sep 17 00:00:00 2001 From: Takahiro Itazuri Date: Mon, 24 Nov 2025 11:48:57 +0000 Subject: [PATCH 3/3] chore: Run test_cpu_rdmsr in PR optional test Adds no_block_pr marker to test_cpu_rdmsr to run in the PR optional test. Also change the marker specification for the CPU template pipeline to keep it run in the pipeline. Signed-off-by: Takahiro Itazuri --- .buildkite/pipeline_cpu_template.py | 2 +- tests/integration_tests/functional/test_cpu_features_x86_64.py | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/.buildkite/pipeline_cpu_template.py b/.buildkite/pipeline_cpu_template.py index f984f85648e..1f2d2644856 100755 --- a/.buildkite/pipeline_cpu_template.py +++ b/.buildkite/pipeline_cpu_template.py @@ -23,7 +23,7 @@ class BkStep(str, Enum): cpu_template_test = { "rdmsr": { BkStep.COMMAND: [ - "tools/devtool -y test --no-build -- -m nonci -n4 --dist worksteal integration_tests/functional/test_cpu_features_x86_64.py -k 'test_cpu_rdmsr' " + "tools/devtool -y test --no-build -- -m no_block_pr -n4 --dist worksteal integration_tests/functional/test_cpu_features_x86_64.py -k 'test_cpu_rdmsr' " ], BkStep.LABEL: "📖 rdmsr", "instances": [ diff --git a/tests/integration_tests/functional/test_cpu_features_x86_64.py b/tests/integration_tests/functional/test_cpu_features_x86_64.py index bf37139a685..d821d852e98 100644 --- a/tests/integration_tests/functional/test_cpu_features_x86_64.py +++ b/tests/integration_tests/functional/test_cpu_features_x86_64.py @@ -253,7 +253,7 @@ def test_brand_string(uvm_plain_any): @pytest.mark.timeout(900) -@pytest.mark.nonci +@pytest.mark.no_block_pr def test_cpu_rdmsr( msr_reader_bin, microvm_factory, cpu_template_any, guest_kernel, rootfs, results_dir ):