From 48cb4bc95ba85230fb90c5c34f8a4245df424692 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Wed, 4 Sep 2019 16:49:55 -0700 Subject: [PATCH 1/7] [docs] Update TracerV docs: HW is generated by default --- docs/Advanced-Usage/Debugging/TracerV.rst | 61 +---------------------- 1 file changed, 2 insertions(+), 59 deletions(-) diff --git a/docs/Advanced-Usage/Debugging/TracerV.rst b/docs/Advanced-Usage/Debugging/TracerV.rst index a8c76a1a76..f0f9e81e98 100644 --- a/docs/Advanced-Usage/Debugging/TracerV.rst +++ b/docs/Advanced-Usage/Debugging/TracerV.rst @@ -3,65 +3,8 @@ Debugging Using TracerV FireSim can provide a cycle-by-cycle trace of the CPU's architectural state over the course of execution. This can be useful for profiling or debugging. -The tracing functionality is provided by the TracerV widget. - -Building a Design with TracerV ------------------------------- - -To use TracerV in your design, you must build and use one of the target -configurations that contain the tracer. For instance, if you are using the -FireSimRocketChipQuadCoreConfig, switch to the -FireSimRocketCoreQuadCoreTracedConfig. - -In TargetConfigs.scala: - -.. code-block:: scala - - class FireSimRocketChipQuadCoreTracedConfig extends Config( - new WithTraceRocket ++ new FireSimRocketChipQuadCoreConfig) - -In SimConfigs.scala: - -.. code-block:: scala - - class FireSimDDR3FRFCFSLLC4MBConfig extends Config( - new WithSerialWidget ++ - new WithUARTWidget ++ - new WithSimpleNICWidget ++ - new WithBlockDevWidget ++ - new FRFCFS16GBQuadRankLLC4MB ++ - new WithTracerVWidget ++ // <--- add this - new BasePlatformConfig) - -In config_build_recipes.ini: - -.. code-block:: ini - - [firesim-quadcore-traced-nic-ddr3-llc4mb] - DESIGN=FireSim - TARGET_CONFIG=FireSimRocketChipQuadCoreTracedConfig - PLATFORM_CONFIG=FireSimDDR3FRFCFSLLC4MBConfig - instancetype=c4.4xlarge - deploytriplet=None - -In config_build.ini: - -.. code-block:: ini - - [builds] - firesim-quadcore-traced-nic-ddr3-llc4mb - -Then run "firesim buildafi" to build an FPGA image. Add the resulting AGFI as -a new entry in config_hwdb.ini. - -.. code-block:: ini - - [firesim-quadcore-traced-nic-ddr3-llc4mb] - agfi=agfi-XXXXX - deploytripletoverride=None - customruntimeconfig=None - -Finally, use this image as the defaulthwconfig in config_runtime.ini. +The tracing functionality is provided by the TracerV widget, which is generated by default +but not enabled at runtime. Enabling Tracing at Runtime --------------------------- From d74fac93bdb23b6be03ebd8e6245969dcbb92735 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Mon, 9 Sep 2019 16:11:13 -0700 Subject: [PATCH 2/7] [docs] Provide more detail about tracerv +args --- docs/Advanced-Usage/Debugging/TracerV.rst | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/docs/Advanced-Usage/Debugging/TracerV.rst b/docs/Advanced-Usage/Debugging/TracerV.rst index f0f9e81e98..41e4868a42 100644 --- a/docs/Advanced-Usage/Debugging/TracerV.rst +++ b/docs/Advanced-Usage/Debugging/TracerV.rst @@ -31,5 +31,25 @@ the "tracing" section. startcycle=XXXX endcycle=YYYY +TracerV Runtime Arguments (+args) +--------------------------------- + +Under the hood, TracerV settings in your config_runtime.ini are being translated to plusargs +that are passed the simulator during ``firesim runworkload``. You can pass these same plusargs to MIDAS- and FPGA-level +simulators if you invoke them directly or by setting ``EXTRA_SIM_ARGS=`` if you invoke them through ``make``. + +**+tracefile0=** + Specifies the file into which the trace will be dumped. + +**+trace-start0=** + (From config_runtime.ini startcycle) Specifies the target cycle at which to start dumping the trace to file. + +**+trace-end0=** + (From config_runtime.ini endcycle) Specifies the target cycle at which to stop dumping the trace to file. + +**+trace-humanreadable0** + Dumps the output trace as hexidecimal strings instead of raw binary. Each line + represents a single target-cycle of collected trace (one token). + Interpreting the Trace Result ----------------------------- From b5da33cb238ad87461d6364aebe566f919e7d509 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Tue, 10 Sep 2019 09:23:54 -0700 Subject: [PATCH 3/7] [docs] Update tracerv subtitle for ML simulation --- docs/Advanced-Usage/Debugging/TracerV.rst | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/docs/Advanced-Usage/Debugging/TracerV.rst b/docs/Advanced-Usage/Debugging/TracerV.rst index 41e4868a42..74d4b9335b 100644 --- a/docs/Advanced-Usage/Debugging/TracerV.rst +++ b/docs/Advanced-Usage/Debugging/TracerV.rst @@ -31,12 +31,12 @@ the "tracing" section. startcycle=XXXX endcycle=YYYY -TracerV Runtime Arguments (+args) ---------------------------------- +MIDAS- & FPGA-Level Simulation Arguments (+args) +------------------------------------------------ Under the hood, TracerV settings in your config_runtime.ini are being translated to plusargs that are passed the simulator during ``firesim runworkload``. You can pass these same plusargs to MIDAS- and FPGA-level -simulators if you invoke them directly or by setting ``EXTRA_SIM_ARGS=`` if you invoke them through ``make``. +simulators (if you invoke them directly) or by setting ``EXTRA_SIM_ARGS=`` if you invoke them through ``make``. **+tracefile0=** Specifies the file into which the trace will be dumped. From 5ad8d7d6317390d42ed00086064315e78e83452a Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Thu, 18 Jul 2019 15:56:49 -0700 Subject: [PATCH 4/7] Add a .readthedocs.yml to appease the RTD deprecation gods --- .readthedocs.yml | 9 +++++++++ 1 file changed, 9 insertions(+) create mode 100644 .readthedocs.yml diff --git a/.readthedocs.yml b/.readthedocs.yml new file mode 100644 index 0000000000..43ffb580d7 --- /dev/null +++ b/.readthedocs.yml @@ -0,0 +1,9 @@ +version: 2 +formats: all +sphinx: + configuration: docs/conf.py +submodules: + exclude: all +python: + install: + - requirements: docs/requirements.txt From 20356d5e42a39fb680996c8df0c62422aa62366c Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Fri, 27 Sep 2019 19:20:26 +0000 Subject: [PATCH 5/7] [config] Prepend FASEDEndpoints to EndpointMap in configs --- sim/src/main/scala/firesim/SimConfigs.scala | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/sim/src/main/scala/firesim/SimConfigs.scala b/sim/src/main/scala/firesim/SimConfigs.scala index 892f27c3ee..6c4a5a91f8 100644 --- a/sim/src/main/scala/firesim/SimConfigs.scala +++ b/sim/src/main/scala/firesim/SimConfigs.scala @@ -56,8 +56,7 @@ class WithTracerVWidget extends Config((site, here, up) => { // Instantiates an AXI4 memory model that executes (1 / clockDivision) of the frequency // of the RTL transformed model (Rocket Chip) class WithDefaultMemModel(clockDivision: Int = 1) extends Config((site, here, up) => { - case EndpointKey => up(EndpointKey) ++ EndpointMap(Seq( - new FASEDAXI4Endpoint(midas.core.ReciprocalClockRatio(clockDivision)))) + case EndpointKey => EndpointMap(Seq(new FASEDAXI4Endpoint(midas.core.ReciprocalClockRatio(clockDivision)))) ++ up(EndpointKey, site) case LlcKey => None // Only used if a DRAM model is requested case DramOrganizationKey => DramOrganizationParams(maxBanks = 8, maxRanks = 4, dramSize = BigInt(1) << 34) From d2c3552c3552806da48a3812c99550007c6b2f57 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Sat, 12 Oct 2019 05:03:08 +0000 Subject: [PATCH 6/7] Bump MIDAS --- sim/midas | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sim/midas b/sim/midas index ef15b8697c..b14229b312 160000 --- a/sim/midas +++ b/sim/midas @@ -1 +1 @@ -Subproject commit ef15b8697c44fbf0c00f17b38a368b35c020e1ac +Subproject commit b14229b312d2c0651ddf2017b23f605d0c440443 From df8a79d124984d7378197ac9398f3b719e1a9066 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Sat, 12 Oct 2019 05:29:25 +0000 Subject: [PATCH 7/7] Bump FireMarshal --- sw/firesim-software | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sw/firesim-software b/sw/firesim-software index 136040aa93..ff9647740d 160000 --- a/sw/firesim-software +++ b/sw/firesim-software @@ -1 +1 @@ -Subproject commit 136040aa9355bf0e3c52027e0c1c698424eac5bc +Subproject commit ff9647740d31d2ea5ec97ae74003422226c9c36b