From c2204d6593dbd5d02928ee7c842b765e455f2a59 Mon Sep 17 00:00:00 2001 From: Nandor Licker Date: Wed, 25 Jan 2023 01:08:59 +0200 Subject: [PATCH] Added a bridge registry to own all bridge instances (#1369) --- .clang-tidy | 2 +- docs/Golden-Gate/Bridge-Walkthrough.rst | 4 +- sim/make/cpp-lint.mk | 1 + .../src/main/cc/bridges/cpu_managed_stream.cc | 32 +- .../src/main/cc/bridges/cpu_managed_stream.h | 5 +- .../main/cc/bridges/fpga_managed_stream.cc | 28 +- .../src/main/cc/bridges/fpga_managed_stream.h | 4 +- sim/midas/src/main/cc/core/constructor.h | 645 ++++++++++-------- sim/midas/src/main/cc/core/simif.cc | 48 +- sim/midas/src/main/cc/core/simif.h | 58 +- sim/midas/src/main/cc/core/widget_registry.cc | 73 ++ sim/midas/src/main/cc/core/widget_registry.h | 120 ++++ sim/midas/src/main/cc/emul/simif_emul.cc | 2 - sim/midas/src/main/cc/emul/simif_emul.h | 14 + sim/midas/src/main/cc/simif_f1.cc | 2 - sim/midas/src/main/cc/simif_f1_xsim.cc | 2 - sim/midas/src/main/cc/simif_vitis.cc | 7 + sim/src/main/cc/bridges/BridgeHarness.cc | 33 +- sim/src/main/cc/bridges/BridgeHarness.h | 13 +- sim/src/main/cc/fasedtests/fasedtests_top.cc | 70 +- sim/src/main/cc/firesim/firesim_top.cc | 89 +-- sim/src/main/cc/midasexamples/AssertTest.h | 8 +- .../main/cc/midasexamples/AutoCounterTest.h | 14 +- .../cc/midasexamples/PassthroughModelTest.h | 2 - sim/src/main/cc/midasexamples/PrintfTest.h | 23 +- .../TestAssertGlobalResetCondition.cc | 15 +- .../main/cc/midasexamples/TestAssertModule.cc | 6 +- .../cc/midasexamples/TestAssertTorture.cc | 16 +- .../TestAutoCounter32bRollover.cc | 3 - .../TestAutoCounterCoverModule.cc | 3 - .../TestAutoCounterGlobalResetCondition.cc | 3 - .../cc/midasexamples/TestAutoCounterModule.cc | 3 - .../TestAutoCounterPrintfModule.cc | 3 - sim/src/main/cc/midasexamples/TestGCD.cc | 2 - sim/src/main/cc/midasexamples/TestHarness.cc | 46 +- sim/src/main/cc/midasexamples/TestHarness.h | 54 +- .../main/cc/midasexamples/TestMultiSRAM.cc | 2 +- .../TestMulticlockAssertModule.cc | 10 +- .../midasexamples/TestNarrowPrintfModule.cc | 5 +- .../cc/midasexamples/TestPlusArgsModule.cc | 17 +- .../cc/midasexamples/TestPrintfCycleBounds.cc | 3 - .../main/cc/midasexamples/TestPrintfModule.cc | 3 - .../midasexamples/TestResetPulseBridgeTest.cc | 15 +- .../cc/midasexamples/TestTerminationModule.cc | 19 +- .../TestTerminationModuleAssert.cc | 21 +- .../TestTriggerPredicatedPrintf.cc | 7 +- .../midasexamples/TestTriggerWiringModule.cc | 9 +- 47 files changed, 856 insertions(+), 708 deletions(-) create mode 100644 sim/midas/src/main/cc/core/widget_registry.cc create mode 100644 sim/midas/src/main/cc/core/widget_registry.h diff --git a/.clang-tidy b/.clang-tidy index 2f32940bb7..e575ea422a 100644 --- a/.clang-tidy +++ b/.clang-tidy @@ -11,7 +11,7 @@ Checks: > bugprone-copy-constructor-init, bugprone-dangling-handle, bugprone-dynamic-static-initializers, - #bugprone-macro-parentheses, + bugprone-macro-parentheses, bugprone-macro-repeated-side-effects, bugprone-misplaced-widening-cast, bugprone-move-forwarding-reference, diff --git a/docs/Golden-Gate/Bridge-Walkthrough.rst b/docs/Golden-Gate/Bridge-Walkthrough.rst index 5f9242c942..8b402c8415 100644 --- a/docs/Golden-Gate/Bridge-Walkthrough.rst +++ b/docs/Golden-Gate/Bridge-Walkthrough.rst @@ -132,11 +132,11 @@ Registering the Driver ++++++++++++++++++++++ With the Bridge Driver implemented, we now have to register it in the main simulator -simulator class defined in ``sim/src/main/cc/firesim/firesim_top.cc``. Here, we +simulator class defined in ``sim/midas/src/main/cc/core/constructor.h``. Here, we rely on the C preprocessor macros to instantiate the bridge driver only when the corresponding BridgeModule is present: -.. literalinclude:: ../../sim/src/main/cc/firesim/firesim_top.cc +.. literalinclude:: ../../sim/midas/src/main/cc/core/constructor.h :language: c++ :start-after: DOC include start: Bridge Driver Registration :end-before: DOC include end: Bridge Driver Registration diff --git a/sim/make/cpp-lint.mk b/sim/make/cpp-lint.mk index 6b68bf3501..5879116c01 100644 --- a/sim/make/cpp-lint.mk +++ b/sim/make/cpp-lint.mk @@ -20,6 +20,7 @@ clang_tidy_files := $(shell \ | grep -v firesim_top \ | grep -v generated-src \ | grep -v output \ + | grep -v constructor.h \ ) clang_tidy_flags :=\ diff --git a/sim/midas/src/main/cc/bridges/cpu_managed_stream.cc b/sim/midas/src/main/cc/bridges/cpu_managed_stream.cc index cb5aea7dd4..9cb50fd7f2 100644 --- a/sim/midas/src/main/cc/bridges/cpu_managed_stream.cc +++ b/sim/midas/src/main/cc/bridges/cpu_managed_stream.cc @@ -1,6 +1,7 @@ #include "cpu_managed_stream.h" +#include "core/simif.h" -#include +#include #include /** @@ -87,28 +88,19 @@ size_t CPUManagedStreams::FPGAToCPUDriver::pull(void *dest, return bytes_read; } -CPUManagedStreamWidget::CPUManagedStreamWidget(CPUManagedStreamIO &io) { -#ifdef CPUMANAGEDSTREAMENGINE_0_PRESENT - for (size_t i = 0; i < CPUMANAGEDSTREAMENGINE_0_from_cpu_stream_count; i++) { +CPUManagedStreamWidget::CPUManagedStreamWidget( + CPUManagedStreamIO &io, + std::vector &&from_cpu, + std::vector &&to_cpu) { + for (auto &¶ms : from_cpu) { cpu_to_fpga_streams.push_back( - std::make_unique( - CPUManagedStreams::StreamParameters( - std::string(CPUMANAGEDSTREAMENGINE_0_from_cpu_names[i]), - CPUMANAGEDSTREAMENGINE_0_from_cpu_dma_addrs[i], - CPUMANAGEDSTREAMENGINE_0_from_cpu_count_addrs[i], - CPUMANAGEDSTREAMENGINE_0_from_cpu_buffer_sizes[i]), - io)); + std::make_unique(std::move(params), + io)); } - for (size_t i = 0; i < CPUMANAGEDSTREAMENGINE_0_to_cpu_stream_count; i++) { + for (auto &¶ms : to_cpu) { fpga_to_cpu_streams.push_back( - std::make_unique( - CPUManagedStreams::StreamParameters( - std::string(CPUMANAGEDSTREAMENGINE_0_to_cpu_names[i]), - CPUMANAGEDSTREAMENGINE_0_to_cpu_dma_addrs[i], - CPUMANAGEDSTREAMENGINE_0_to_cpu_count_addrs[i], - CPUMANAGEDSTREAMENGINE_0_to_cpu_buffer_sizes[i]), - io)); + std::make_unique(std::move(params), + io)); } -#endif // CPUMANAGEDSTREAMENGINE_0_PRESENT } diff --git a/sim/midas/src/main/cc/bridges/cpu_managed_stream.h b/sim/midas/src/main/cc/bridges/cpu_managed_stream.h index 19a9699969..831b3954d2 100644 --- a/sim/midas/src/main/cc/bridges/cpu_managed_stream.h +++ b/sim/midas/src/main/cc/bridges/cpu_managed_stream.h @@ -159,7 +159,10 @@ class CPUManagedStreamWidget final : public StreamEngine { * * @param io Reference to a functor implementing low-level IO. */ - CPUManagedStreamWidget(CPUManagedStreamIO &io); + CPUManagedStreamWidget( + CPUManagedStreamIO &io, + std::vector &&from_cpu, + std::vector &&to_cpu); }; #endif // __BRIDGES_CPU_MANAGED_STREAM_H diff --git a/sim/midas/src/main/cc/bridges/fpga_managed_stream.cc b/sim/midas/src/main/cc/bridges/fpga_managed_stream.cc index 93bcf9e782..3fc41ce73c 100644 --- a/sim/midas/src/main/cc/bridges/fpga_managed_stream.cc +++ b/sim/midas/src/main/cc/bridges/fpga_managed_stream.cc @@ -56,30 +56,20 @@ void FPGAManagedStreams::FPGAToCPUDriver::flush() { } } -FPGAManagedStreamWidget::FPGAManagedStreamWidget(FPGAManagedStreamIO &io) { -#ifdef FPGAMANAGEDSTREAMENGINE_0_PRESENT - char *fpga_address_memory_base = io.get_memory_base(); - auto offset = 0; +FPGAManagedStreamWidget::FPGAManagedStreamWidget( + FPGAManagedStreamIO &io, + std::vector &&to_cpu) { - for (size_t i = 0; i < FPGAMANAGEDSTREAMENGINE_0_to_cpu_stream_count; i++) { - uint32_t buffer_capacity = - FPGAMANAGEDSTREAMENGINE_0_to_cpu_fpgaBufferDepth[i]; + char *fpga_address_memory_base = io.get_memory_base(); + uint64_t offset = 0; + for (auto &¶ms : to_cpu) { + uint32_t capacity = params.buffer_capacity; fpga_to_cpu_streams.push_back( std::make_unique( - FPGAManagedStreams::StreamParameters( - std::string(FPGAMANAGEDSTREAMENGINE_0_to_cpu_names[i]), - buffer_capacity, - FPGAMANAGEDSTREAMENGINE_0_to_cpu_toHostPhysAddrHighAddrs[i], - FPGAMANAGEDSTREAMENGINE_0_to_cpu_toHostPhysAddrLowAddrs[i], - FPGAMANAGEDSTREAMENGINE_0_to_cpu_bytesAvailableAddrs[i], - FPGAMANAGEDSTREAMENGINE_0_to_cpu_bytesConsumedAddrs[i], - FPGAMANAGEDSTREAMENGINE_0_to_cpu_toHostStreamDoneInitAddrs[i], - FPGAMANAGEDSTREAMENGINE_0_to_cpu_toHostStreamFlushAddrs[i], - FPGAMANAGEDSTREAMENGINE_0_to_cpu_toHostStreamFlushDoneAddrs[i]), + std::move(params), (void *)(fpga_address_memory_base + offset), offset, io)); - offset += buffer_capacity; + offset += capacity; } -#endif // FPGAMANAGEDSTREAMENGINE_0_PRESENT } diff --git a/sim/midas/src/main/cc/bridges/fpga_managed_stream.h b/sim/midas/src/main/cc/bridges/fpga_managed_stream.h index c0c7ca908d..cd0a77a23e 100644 --- a/sim/midas/src/main/cc/bridges/fpga_managed_stream.h +++ b/sim/midas/src/main/cc/bridges/fpga_managed_stream.h @@ -116,7 +116,9 @@ class FPGAManagedStreamWidget final : public StreamEngine { * * @param io Reference to a functor implementing the low-level IO. */ - FPGAManagedStreamWidget(FPGAManagedStreamIO &io); + FPGAManagedStreamWidget( + FPGAManagedStreamIO &io, + std::vector &&to_cpu); }; #endif // __BRIDGES_FPGA_MANAGED_STREAM_H diff --git a/sim/midas/src/main/cc/core/constructor.h b/sim/midas/src/main/cc/core/constructor.h index 08e5718892..a125200919 100644 --- a/sim/midas/src/main/cc/core/constructor.h +++ b/sim/midas/src/main/cc/core/constructor.h @@ -1,33 +1,15 @@ +// DOC include start: Bridge Driver Registration + // Helper file to be included in a method to instantiate all bridges available. -// Each bridge is constructed and passed to the `add_bridge_driver` method. +// Each bridge is constructed and passed to the `registry.add_widget` method. // Top-levels can filter the bridges they want to add by creating overloads -// of the `add_bridge_driver` method with appropriate types. - -#ifdef PEEKPOKEBRIDGEMODULE_0_PRESENT -add_bridge_driver(new peek_poke_t(*simif, - PEEKPOKEBRIDGEMODULE_0_substruct_create, - POKE_SIZE, - (const uint32_t *)INPUT_ADDRS, - (const char *const *)INPUT_NAMES, - (const uint32_t *)INPUT_CHUNKS, - PEEK_SIZE, - (const uint32_t *)OUTPUT_ADDRS, - (const char *const *)OUTPUT_NAMES, - (const uint32_t *)OUTPUT_CHUNKS)); -#endif +// of the `registry.add_widget` method with appropriate types. -#ifdef RESETPULSEBRIDGEMODULE_checks -RESETPULSEBRIDGEMODULE_checks; -#endif // RESETPULSEBRIDGEMODULE_checks - -// Bridge Driver Instantiation Template -#define INSTANTIATE_RESET_PULSE(FUNC, IDX) \ - FUNC(new reset_pulse_t(*simif, \ - args, \ - RESETPULSEBRIDGEMODULE_##IDX##_substruct_create, \ - RESETPULSEBRIDGEMODULE_##IDX##_max_pulse_length, \ - RESETPULSEBRIDGEMODULE_##IDX##_default_pulse_length, \ - IDX)); +// Here we instantiate our driver once for each bridge in the target +// Golden Gate emits a __PRESENT macro for each +// instance which you may use to conditionally instantiate your driver. +// This file can be included in the setup method of any top-level to pass +// an instance of each driver to the `add_bridge_driver` method. #ifdef CLOCKBRIDGEMODULE_checks CLOCKBRIDGEMODULE_checks; @@ -39,54 +21,181 @@ LOADMEMWIDGET_checks; SIMULATIONMASTER_checks; #endif // SIMULATIONMASTER_checks -#ifdef RESETPULSEBRIDGEMODULE_0_PRESENT -INSTANTIATE_RESET_PULSE(add_bridge_driver, 0) +#ifdef ASSERTBRIDGEMODULE_checks +ASSERTBRIDGEMODULE_checks; +#endif // ASSERTBRIDGEMODULE_checks + +#ifdef TERMINATIONBRIDGEMODULE_checks +TERMINATIONBRIDGEMODULE_checks; +#endif // TERMINATIONBRIDGEMODULE_checks + +#ifdef RESETPULSEBRIDGEMODULE_checks +RESETPULSEBRIDGEMODULE_checks; +#endif // RESETPULSEBRIDGEMODULE_checks + +#ifdef FASEDMEMORYTIMINGMODEL_checks +FASEDMEMORYTIMINGMODEL_checks; #endif +#ifdef AUTOCOUNTERBRIDGEMODULE_checks +AUTOCOUNTERBRIDGEMODULE_checks; +#endif // AUTOCOUNTERBRIDGEMODULE_checks + +#ifdef PRINTBRIDGEMODULE_checks +PRINTBRIDGEMODULE_checks; +#endif // PRINTBRIDGEMODULE_checks + +#ifdef PLUSARGSBRIDGEMODULE_checks +PLUSARGSBRIDGEMODULE_checks; +#endif // PLUSARGSBRIDGEMODULE_checks + +#ifdef BLOCKDEVBRIDGEMODULE_checks +BLOCKDEVBRIDGEMODULE_checks; +#endif // BLOCKDEVBRIDGEMODULE_checks + +#ifdef SERIALBRIDGEMODULE_checks +SERIALBRIDGEMODULE_checks; +#endif // SERIALBRIDGEMODULE_checks + +#ifdef TRACERVBRIDGEMODULE_checks +TRACERVBRIDGEMODULE_checks; +#endif // TRACERVBRIDGEMODULE_checks + +#ifdef SIMPLENICBRIDGEMODULE_checks +SIMPLENICBRIDGEMODULE_checks; +#endif // SIMPLENICBRIDGEMODULE_checks + +#ifdef PEEKPOKEBRIDGEMODULE_checks +PEEKPOKEBRIDGEMODULE_checks; +#endif // PEEKPOKEBRIDGEMODULE_checks + #ifdef UARTBRIDGEMODULE_checks UARTBRIDGEMODULE_checks; #endif // UARTBRIDGEMODULE_checks +#ifdef LOADMEMWIDGET_0_PRESENT +registry.add_widget(new loadmem_t(simif, + LOADMEMWIDGET_0_substruct_create, + config.mem, + LOADMEMWIDGET_0_mem_data_chunk)); +#endif // LOADMEMWIDGET_0_PRESENT + +#ifdef CLOCKBRIDGEMODULE_0_PRESENT +registry.add_widget(new clockmodule_t(simif, + CLOCKBRIDGEMODULE_0_substruct_create)); +#endif // CLOCKBRIDGEMODULE_0_PRESENT + +#ifdef SIMULATIONMASTER_0_PRESENT +registry.add_widget(new master_t(simif, SIMULATIONMASTER_0_substruct_create)); +#endif // SIMULATIONMASTER_0_PRESENT + +#ifdef CPUMANAGEDSTREAMENGINE_0_PRESENT +{ + std::vector from_cpu; + for (size_t i = 0; i < CPUMANAGEDSTREAMENGINE_0_from_cpu_stream_count; i++) { + from_cpu.emplace_back( + std::string(CPUMANAGEDSTREAMENGINE_0_from_cpu_names[i]), + CPUMANAGEDSTREAMENGINE_0_from_cpu_dma_addrs[i], + CPUMANAGEDSTREAMENGINE_0_from_cpu_count_addrs[i], + CPUMANAGEDSTREAMENGINE_0_from_cpu_buffer_sizes[i]); + } + + std::vector to_cpu; + for (size_t i = 0; i < CPUMANAGEDSTREAMENGINE_0_to_cpu_stream_count; i++) { + to_cpu.emplace_back(std::string(CPUMANAGEDSTREAMENGINE_0_to_cpu_names[i]), + CPUMANAGEDSTREAMENGINE_0_to_cpu_dma_addrs[i], + CPUMANAGEDSTREAMENGINE_0_to_cpu_count_addrs[i], + CPUMANAGEDSTREAMENGINE_0_to_cpu_buffer_sizes[i]); + } + registry.add_widget( + new CPUManagedStreamWidget(simif.get_cpu_managed_stream_io(), + std::move(from_cpu), + std::move(to_cpu))); +} +#endif // CPUMANAGEDSTREAMENGINE_0_PRESENT + +#ifdef FPGAMANAGEDSTREAMENGINE_0_PRESENT +{ + std::vector to_cpu; + for (size_t i = 0; i < FPGAMANAGEDSTREAMENGINE_0_to_cpu_stream_count; i++) { + to_cpu.emplace_back(FPGAManagedStreams::StreamParameters( + std::string(FPGAMANAGEDSTREAMENGINE_0_to_cpu_names[i]), + FPGAMANAGEDSTREAMENGINE_0_to_cpu_fpgaBufferDepth[i], + FPGAMANAGEDSTREAMENGINE_0_to_cpu_toHostPhysAddrHighAddrs[i], + FPGAMANAGEDSTREAMENGINE_0_to_cpu_toHostPhysAddrLowAddrs[i], + FPGAMANAGEDSTREAMENGINE_0_to_cpu_bytesAvailableAddrs[i], + FPGAMANAGEDSTREAMENGINE_0_to_cpu_bytesConsumedAddrs[i], + FPGAMANAGEDSTREAMENGINE_0_to_cpu_toHostStreamDoneInitAddrs[i], + FPGAMANAGEDSTREAMENGINE_0_to_cpu_toHostStreamFlushAddrs[i], + FPGAMANAGEDSTREAMENGINE_0_to_cpu_toHostStreamFlushDoneAddrs[i])); + } + registry.add_widget(new FPGAManagedStreamWidget( + simif.get_fpga_managed_stream_io(), std::move(to_cpu))); +} +#endif // FPGAMANAGEDSTREAMENGINE_0_PRESENT + +#define INSTANTIATE_RESET_PULSE(FUNC, IDX) \ + registry.add_widget( \ + new reset_pulse_t(simif, \ + args, \ + RESETPULSEBRIDGEMODULE_##IDX##_substruct_create, \ + RESETPULSEBRIDGEMODULE_##IDX##_max_pulse_length, \ + RESETPULSEBRIDGEMODULE_##IDX##_default_pulse_length, \ + IDX)); + +#ifdef RESETPULSEBRIDGEMODULE_0_PRESENT +INSTANTIATE_RESET_PULSE(registry.add_widget, 0) +#endif + +#ifdef PEEKPOKEBRIDGEMODULE_0_PRESENT +registry.add_widget(new peek_poke_t(simif, + PEEKPOKEBRIDGEMODULE_0_substruct_create, + POKE_SIZE, + (const uint32_t *)INPUT_ADDRS, + (const char *const *)INPUT_NAMES, + (const uint32_t *)INPUT_CHUNKS, + PEEK_SIZE, + (const uint32_t *)OUTPUT_ADDRS, + (const char *const *)OUTPUT_NAMES, + (const uint32_t *)OUTPUT_CHUNKS)); +#endif + #ifdef UARTBRIDGEMODULE_0_PRESENT -add_bridge_driver( - new uart_t(*simif, args, UARTBRIDGEMODULE_0_substruct_create, 0)); +registry.add_widget( + new uart_t(simif, args, UARTBRIDGEMODULE_0_substruct_create, 0)); #endif #ifdef UARTBRIDGEMODULE_1_PRESENT -add_bridge_driver( - new uart_t(*simif, args, UARTBRIDGEMODULE_1_substruct_create, 1)); +registry.add_widget( + new uart_t(simif, args, UARTBRIDGEMODULE_1_substruct_create, 1)); #endif #ifdef UARTBRIDGEMODULE_2_PRESENT -add_bridge_driver( - new uart_t(*simif, args, UARTBRIDGEMODULE_2_substruct_create, 2)); +registry.add_widget( + new uart_t(simif, args, UARTBRIDGEMODULE_2_substruct_create, 2)); #endif #ifdef UARTBRIDGEMODULE_3_PRESENT -add_bridge_driver( - new uart_t(*simif, args, UARTBRIDGEMODULE_3_substruct_create, 3)); +registry.add_widget( + new uart_t(simif, args, UARTBRIDGEMODULE_3_substruct_create, 3)); #endif #ifdef UARTBRIDGEMODULE_4_PRESENT -add_bridge_driver( - new uart_t(*simif, args, UARTBRIDGEMODULE_4_substruct_create, 4)); +registry.add_widget( + new uart_t(simif, args, UARTBRIDGEMODULE_4_substruct_create, 4)); #endif #ifdef UARTBRIDGEMODULE_5_PRESENT -add_bridge_driver( - new uart_t(*simif, args, UARTBRIDGEMODULE_5_substruct_create, 5)); +registry.add_widget( + new uart_t(simif, args, UARTBRIDGEMODULE_5_substruct_create, 5)); #endif #ifdef UARTBRIDGEMODULE_6_PRESENT -add_bridge_driver( - new uart_t(*simif, args, UARTBRIDGEMODULE_6_substruct_create, 6)); +registry.add_widget( + new uart_t(simif, args, UARTBRIDGEMODULE_6_substruct_create, 6)); #endif #ifdef UARTBRIDGEMODULE_7_PRESENT -add_bridge_driver( - new uart_t(*simif, args, UARTBRIDGEMODULE_7_substruct_create, 7)); -#endif - -#ifdef FASEDMEMORYTIMINGMODEL_checks -FASEDMEMORYTIMINGMODEL_checks; +registry.add_widget( + new uart_t(simif, args, UARTBRIDGEMODULE_7_substruct_create, 7)); #endif -#define INSTANTIATE_FASED(FUNC, IDX) \ - FUNC(new FASEDMemoryTimingModel( \ - *simif, \ +#define INSTANTIATE_FASED(IDX) \ + registry.add_widget(new FASEDMemoryTimingModel( \ + simif, \ AddressMap(FASEDMEMORYTIMINGMODEL_##IDX##_R_num_registers, \ (const unsigned int *)FASEDMEMORYTIMINGMODEL_##IDX##_R_addrs, \ (const char *const *)FASEDMEMORYTIMINGMODEL_##IDX##_R_names, \ @@ -99,192 +208,180 @@ FASEDMEMORYTIMINGMODEL_checks; "_" #IDX)); #ifdef FASEDMEMORYTIMINGMODEL_0 -INSTANTIATE_FASED(add_bridge_driver, 0) +INSTANTIATE_FASED(0) #endif #ifdef FASEDMEMORYTIMINGMODEL_1 -INSTANTIATE_FASED(add_bridge_driver, 1) +INSTANTIATE_FASED(1) #endif #ifdef FASEDMEMORYTIMINGMODEL_2 -INSTANTIATE_FASED(add_bridge_driver, 2) +INSTANTIATE_FASED(2) #endif #ifdef FASEDMEMORYTIMINGMODEL_3 -INSTANTIATE_FASED(add_bridge_driver, 3) +INSTANTIATE_FASED(3) #endif #ifdef FASEDMEMORYTIMINGMODEL_4 -INSTANTIATE_FASED(add_bridge_driver, 4) +INSTANTIATE_FASED(4) #endif #ifdef FASEDMEMORYTIMINGMODEL_5 -INSTANTIATE_FASED(add_bridge_driver, 5) +INSTANTIATE_FASED(5) #endif #ifdef FASEDMEMORYTIMINGMODEL_6 -INSTANTIATE_FASED(add_bridge_driver, 6) +INSTANTIATE_FASED(6) #endif #ifdef FASEDMEMORYTIMINGMODEL_7 -INSTANTIATE_FASED(add_bridge_driver, 7) +INSTANTIATE_FASED(7) #endif #ifdef FASEDMEMORYTIMINGMODEL_8 -INSTANTIATE_FASED(add_bridge_driver, 8) +INSTANTIATE_FASED(8) #endif #ifdef FASEDMEMORYTIMINGMODEL_9 -INSTANTIATE_FASED(add_bridge_driver, 9) +INSTANTIATE_FASED(9) #endif #ifdef FASEDMEMORYTIMINGMODEL_10 -INSTANTIATE_FASED(add_bridge_driver, 10) +INSTANTIATE_FASED(registry.add_widget, 10) #endif #ifdef FASEDMEMORYTIMINGMODEL_11 -INSTANTIATE_FASED(add_bridge_driver, 11) +INSTANTIATE_FASED(registry.add_widget, 11) #endif #ifdef FASEDMEMORYTIMINGMODEL_12 -INSTANTIATE_FASED(add_bridge_driver, 12) +INSTANTIATE_FASED(registry.add_widget, 12) #endif #ifdef FASEDMEMORYTIMINGMODEL_13 -INSTANTIATE_FASED(add_bridge_driver, 13) +INSTANTIATE_FASED(registry.add_widget, 13) #endif #ifdef FASEDMEMORYTIMINGMODEL_14 -INSTANTIATE_FASED(add_bridge_driver, 14) +INSTANTIATE_FASED(registry.add_widget, 14) #endif #ifdef FASEDMEMORYTIMINGMODEL_15 -INSTANTIATE_FASED(add_bridge_driver, 15) +INSTANTIATE_FASED(registry.add_widget, 15) #endif -#ifdef SERIALBRIDGEMODULE_checks -SERIALBRIDGEMODULE_checks; -#endif // SERIALBRIDGEMODULE_checks - #define INSTANTIATE_SERIAL(FUNC, IDX) \ - FUNC(new serial_t(*simif, \ + FUNC(new serial_t(simif, \ args, \ SERIALBRIDGEMODULE_##IDX##_substruct_create, \ - simif->get_loadmem(), \ + registry.get_widget(), \ SERIALBRIDGEMODULE_##IDX##_has_memory, \ SERIALBRIDGEMODULE_##IDX##_memory_offset, \ IDX)); #ifdef SERIALBRIDGEMODULE_0_PRESENT -INSTANTIATE_SERIAL(add_bridge_driver, 0) +INSTANTIATE_SERIAL(registry.add_widget, 0) #endif #ifdef SERIALBRIDGEMODULE_1_PRESENT -INSTANTIATE_SERIAL(add_bridge_driver, 1) +INSTANTIATE_SERIAL(registry.add_widget, 1) #endif #ifdef SERIALBRIDGEMODULE_2_PRESENT -INSTANTIATE_SERIAL(add_bridge_driver, 2) +INSTANTIATE_SERIAL(registry.add_widget, 2) #endif #ifdef SERIALBRIDGEMODULE_3_PRESENT -INSTANTIATE_SERIAL(add_bridge_driver, 3) +INSTANTIATE_SERIAL(registry.add_widget, 3) #endif #ifdef SERIALBRIDGEMODULE_4_PRESENT -INSTANTIATE_SERIAL(add_bridge_driver, 4) +INSTANTIATE_SERIAL(registry.add_widget, 4) #endif #ifdef SERIALBRIDGEMODULE_5_PRESENT -INSTANTIATE_SERIAL(add_bridge_driver, 5) +INSTANTIATE_SERIAL(registry.add_widget, 5) #endif #ifdef SERIALBRIDGEMODULE_6_PRESENT -INSTANTIATE_SERIAL(add_bridge_driver, 6) +INSTANTIATE_SERIAL(registry.add_widget, 6) #endif #ifdef SERIALBRIDGEMODULE_7_PRESENT -INSTANTIATE_SERIAL(add_bridge_driver, 7) +INSTANTIATE_SERIAL(registry.add_widget, 7) #endif #ifdef SERIALBRIDGEMODULE_8_PRESENT -INSTANTIATE_SERIAL(add_bridge_driver, 8) +INSTANTIATE_SERIAL(registry.add_widget, 8) #endif #ifdef SERIALBRIDGEMODULE_9_PRESENT -INSTANTIATE_SERIAL(add_bridge_driver, 9) +INSTANTIATE_SERIAL(registry.add_widget, 9) #endif #ifdef SERIALBRIDGEMODULE_10_PRESENT -INSTANTIATE_SERIAL(add_bridge_driver, 10) +INSTANTIATE_SERIAL(registry.add_widget, 10) #endif #ifdef SERIALBRIDGEMODULE_11_PRESENT -INSTANTIATE_SERIAL(add_bridge_driver, 11) +INSTANTIATE_SERIAL(registry.add_widget, 11) #endif #ifdef SERIALBRIDGEMODULE_12_PRESENT -INSTANTIATE_SERIAL(add_bridge_driver, 12) +INSTANTIATE_SERIAL(registry.add_widget, 12) #endif #ifdef SERIALBRIDGEMODULE_13_PRESENT -INSTANTIATE_SERIAL(add_bridge_driver, 13) +INSTANTIATE_SERIAL(registry.add_widget, 13) #endif #ifdef SERIALBRIDGEMODULE_14_PRESENT -INSTANTIATE_SERIAL(add_bridge_driver, 14) +INSTANTIATE_SERIAL(registry.add_widget, 14) #endif #ifdef SERIALBRIDGEMODULE_15_PRESENT -INSTANTIATE_SERIAL(add_bridge_driver, 15) +INSTANTIATE_SERIAL(registry.add_widget, 15) #endif -#ifdef BLOCKDEVBRIDGEMODULE_checks -BLOCKDEVBRIDGEMODULE_checks; -#endif // BLOCKDEVBRIDGEMODULE_checks - #ifdef BLOCKDEVBRIDGEMODULE_0_PRESENT -add_bridge_driver(new blockdev_t(*simif, - args, - BLOCKDEVBRIDGEMODULE_0_num_trackers, - BLOCKDEVBRIDGEMODULE_0_latency_bits, - BLOCKDEVBRIDGEMODULE_0_substruct_create, - 0)); +registry.add_widget(new blockdev_t(simif, + args, + BLOCKDEVBRIDGEMODULE_0_num_trackers, + BLOCKDEVBRIDGEMODULE_0_latency_bits, + BLOCKDEVBRIDGEMODULE_0_substruct_create, + 0)); #endif #ifdef BLOCKDEVBRIDGEMODULE_1_PRESENT -add_bridge_driver(new blockdev_t(*simif, - args, - BLOCKDEVBRIDGEMODULE_1_num_trackers, - BLOCKDEVBRIDGEMODULE_1_latency_bits, - BLOCKDEVBRIDGEMODULE_1_substruct_create, - 1)); +registry.add_widget(new blockdev_t(simif, + args, + BLOCKDEVBRIDGEMODULE_1_num_trackers, + BLOCKDEVBRIDGEMODULE_1_latency_bits, + BLOCKDEVBRIDGEMODULE_1_substruct_create, + 1)); #endif #ifdef BLOCKDEVBRIDGEMODULE_2_PRESENT -add_bridge_driver(new blockdev_t(*simif, - args, - BLOCKDEVBRIDGEMODULE_2_num_trackers, - BLOCKDEVBRIDGEMODULE_2_latency_bits, - BLOCKDEVBRIDGEMODULE_2_substruct_create, - 2)); +registry.add_widget(new blockdev_t(simif, + args, + BLOCKDEVBRIDGEMODULE_2_num_trackers, + BLOCKDEVBRIDGEMODULE_2_latency_bits, + BLOCKDEVBRIDGEMODULE_2_substruct_create, + 2)); #endif #ifdef BLOCKDEVBRIDGEMODULE_3_PRESENT -add_bridge_driver(new blockdev_t(*simif, - args, - BLOCKDEVBRIDGEMODULE_3_num_trackers, - BLOCKDEVBRIDGEMODULE_3_latency_bits, - BLOCKDEVBRIDGEMODULE_3_substruct_create, - 3)); +registry.add_widget(new blockdev_t(simif, + args, + BLOCKDEVBRIDGEMODULE_3_num_trackers, + BLOCKDEVBRIDGEMODULE_3_latency_bits, + BLOCKDEVBRIDGEMODULE_3_substruct_create, + 3)); #endif #ifdef BLOCKDEVBRIDGEMODULE_4_PRESENT -add_bridge_driver(new blockdev_t(*simif, - args, - BLOCKDEVBRIDGEMODULE_4_num_trackers, - BLOCKDEVBRIDGEMODULE_4_latency_bits, - BLOCKDEVBRIDGEMODULE_4_substruct_create, - 4)); +registry.add_widget(new blockdev_t(simif, + args, + BLOCKDEVBRIDGEMODULE_4_num_trackers, + BLOCKDEVBRIDGEMODULE_4_latency_bits, + BLOCKDEVBRIDGEMODULE_4_substruct_create, + 4)); #endif #ifdef BLOCKDEVBRIDGEMODULE_5_PRESENT -add_bridge_driver(new blockdev_t(*simif, - args, - BLOCKDEVBRIDGEMODULE_5_num_trackers, - BLOCKDEVBRIDGEMODULE_5_latency_bits, - BLOCKDEVBRIDGEMODULE_5_substruct_create, - 5)); +registry.add_widget(new blockdev_t(simif, + args, + BLOCKDEVBRIDGEMODULE_5_num_trackers, + BLOCKDEVBRIDGEMODULE_5_latency_bits, + BLOCKDEVBRIDGEMODULE_5_substruct_create, + 5)); #endif #ifdef BLOCKDEVBRIDGEMODULE_6_PRESENT -add_bridge_driver(new blockdev_t(*simif, - args, - BLOCKDEVBRIDGEMODULE_6_num_trackers, - BLOCKDEVBRIDGEMODULE_6_latency_bits, - BLOCKDEVBRIDGEMODULE_6_substruct_create, - 6)); +registry.add_widget(new blockdev_t(simif, + args, + BLOCKDEVBRIDGEMODULE_6_num_trackers, + BLOCKDEVBRIDGEMODULE_6_latency_bits, + BLOCKDEVBRIDGEMODULE_6_substruct_create, + 6)); #endif #ifdef BLOCKDEVBRIDGEMODULE_7_PRESENT -add_bridge_driver(new blockdev_t(*simif, - args, - BLOCKDEVBRIDGEMODULE_7_num_trackers, - BLOCKDEVBRIDGEMODULE_7_latency_bits, - BLOCKDEVBRIDGEMODULE_7_substruct_create, - 7)); +registry.add_widget(new blockdev_t(simif, + args, + BLOCKDEVBRIDGEMODULE_7_num_trackers, + BLOCKDEVBRIDGEMODULE_7_latency_bits, + BLOCKDEVBRIDGEMODULE_7_substruct_create, + 7)); #endif -#ifdef SIMPLENICBRIDGEMODULE_checks -SIMPLENICBRIDGEMODULE_checks; -#endif // SIMPLENICBRIDGEMODULE_checks - #define INSTANTIATE_SIMPLENIC(FUNC, IDX) \ - FUNC(new simplenic_t(*simif, \ - simif->get_managed_stream(), \ + FUNC(new simplenic_t(simif, \ + *registry.get_stream_engine(), \ args, \ SIMPLENICBRIDGEMODULE_##IDX##_substruct_create, \ IDX, \ @@ -294,38 +391,33 @@ SIMPLENICBRIDGEMODULE_checks; SIMPLENICBRIDGEMODULE_##IDX##_from_cpu_stream_depth)); #ifdef SIMPLENICBRIDGEMODULE_0_PRESENT -INSTANTIATE_SIMPLENIC(add_bridge_driver, 0) +INSTANTIATE_SIMPLENIC(registry.add_widget, 0) #endif #ifdef SIMPLENICBRIDGEMODULE_1_PRESENT -INSTANTIATE_SIMPLENIC(add_bridge_driver, 1) +INSTANTIATE_SIMPLENIC(registry.add_widget, 1) #endif #ifdef SIMPLENICBRIDGEMODULE_2_PRESENT -INSTANTIATE_SIMPLENIC(add_bridge_driver, 2) +INSTANTIATE_SIMPLENIC(registry.add_widget, 2) #endif #ifdef SIMPLENICBRIDGEMODULE_3_PRESENT -INSTANTIATE_SIMPLENIC(add_bridge_driver, 3) +INSTANTIATE_SIMPLENIC(registry.add_widget, 3) #endif #ifdef SIMPLENICBRIDGEMODULE_4_PRESENT -INSTANTIATE_SIMPLENIC(add_bridge_driver, 4) +INSTANTIATE_SIMPLENIC(registry.add_widget, 4) #endif #ifdef SIMPLENICBRIDGEMODULE_5_PRESENT -INSTANTIATE_SIMPLENIC(add_bridge_driver, 5) +INSTANTIATE_SIMPLENIC(registry.add_widget, 5) #endif #ifdef SIMPLENICBRIDGEMODULE_6_PRESENT -INSTANTIATE_SIMPLENIC(add_bridge_driver, 6) +INSTANTIATE_SIMPLENIC(registry.add_widget, 6) #endif #ifdef SIMPLENICBRIDGEMODULE_7_PRESENT -INSTANTIATE_SIMPLENIC(add_bridge_driver, 7) +INSTANTIATE_SIMPLENIC(registry.add_widget, 7) #endif -#ifdef TRACERVBRIDGEMODULE_checks -TRACERVBRIDGEMODULE_checks; -#endif // TRACERVBRIDGEMODULE_checks - -// Bridge Driver Instantiation Template #define INSTANTIATE_TRACERV(FUNC, IDX) \ - FUNC(new tracerv_t(*simif, \ - simif->get_managed_stream(), \ + FUNC(new tracerv_t(simif, \ + *registry.get_stream_engine(), \ args, \ TRACERVBRIDGEMODULE_##IDX##_substruct_create, \ TRACERVBRIDGEMODULE_##IDX##_to_cpu_stream_idx, \ @@ -337,100 +429,100 @@ TRACERVBRIDGEMODULE_checks; IDX)); #ifdef TRACERVBRIDGEMODULE_0_PRESENT -INSTANTIATE_TRACERV(add_bridge_driver, 0) +INSTANTIATE_TRACERV(registry.add_widget, 0) #endif #ifdef TRACERVBRIDGEMODULE_1_PRESENT -INSTANTIATE_TRACERV(add_bridge_driver, 1) +INSTANTIATE_TRACERV(registry.add_widget, 1) #endif #ifdef TRACERVBRIDGEMODULE_2_PRESENT -INSTANTIATE_TRACERV(add_bridge_driver, 2) +INSTANTIATE_TRACERV(registry.add_widget, 2) #endif #ifdef TRACERVBRIDGEMODULE_3_PRESENT -INSTANTIATE_TRACERV(add_bridge_driver, 3) +INSTANTIATE_TRACERV(registry.add_widget, 3) #endif #ifdef TRACERVBRIDGEMODULE_4_PRESENT -INSTANTIATE_TRACERV(add_bridge_driver, 4) +INSTANTIATE_TRACERV(registry.add_widget, 4) #endif #ifdef TRACERVBRIDGEMODULE_5_PRESENT -INSTANTIATE_TRACERV(add_bridge_driver, 5) +INSTANTIATE_TRACERV(registry.add_widget, 5) #endif #ifdef TRACERVBRIDGEMODULE_6_PRESENT -INSTANTIATE_TRACERV(add_bridge_driver, 6) +INSTANTIATE_TRACERV(registry.add_widget, 6) #endif #ifdef TRACERVBRIDGEMODULE_7_PRESENT -INSTANTIATE_TRACERV(add_bridge_driver, 7) +INSTANTIATE_TRACERV(registry.add_widget, 7) #endif #ifdef TRACERVBRIDGEMODULE_8_PRESENT -INSTANTIATE_TRACERV(add_bridge_driver, 8) +INSTANTIATE_TRACERV(registry.add_widget, 8) #endif #ifdef TRACERVBRIDGEMODULE_9_PRESENT -INSTANTIATE_TRACERV(add_bridge_driver, 9) +INSTANTIATE_TRACERV(registry.add_widget, 9) #endif #ifdef TRACERVBRIDGEMODULE_10_PRESENT -INSTANTIATE_TRACERV(add_bridge_driver, 10) +INSTANTIATE_TRACERV(registry.add_widget, 10) #endif #ifdef TRACERVBRIDGEMODULE_11_PRESENT -INSTANTIATE_TRACERV(add_bridge_driver, 11) +INSTANTIATE_TRACERV(registry.add_widget, 11) #endif #ifdef TRACERVBRIDGEMODULE_12_PRESENT -INSTANTIATE_TRACERV(add_bridge_driver, 12) +INSTANTIATE_TRACERV(registry.add_widget, 12) #endif #ifdef TRACERVBRIDGEMODULE_13_PRESENT -INSTANTIATE_TRACERV(add_bridge_driver, 13) +INSTANTIATE_TRACERV(registry.add_widget, 13) #endif #ifdef TRACERVBRIDGEMODULE_14_PRESENT -INSTANTIATE_TRACERV(add_bridge_driver, 14) +INSTANTIATE_TRACERV(registry.add_widget, 14) #endif #ifdef TRACERVBRIDGEMODULE_15_PRESENT -INSTANTIATE_TRACERV(add_bridge_driver, 15) +INSTANTIATE_TRACERV(registry.add_widget, 15) #endif #ifdef TRACERVBRIDGEMODULE_16_PRESENT -INSTANTIATE_TRACERV(add_bridge_driver, 16) +INSTANTIATE_TRACERV(registry.add_widget, 16) #endif #ifdef TRACERVBRIDGEMODULE_17_PRESENT -INSTANTIATE_TRACERV(add_bridge_driver, 17) +INSTANTIATE_TRACERV(registry.add_widget, 17) #endif #ifdef TRACERVBRIDGEMODULE_18_PRESENT -INSTANTIATE_TRACERV(add_bridge_driver, 18) +INSTANTIATE_TRACERV(registry.add_widget, 18) #endif #ifdef TRACERVBRIDGEMODULE_19_PRESENT -INSTANTIATE_TRACERV(add_bridge_driver, 19) +INSTANTIATE_TRACERV(registry.add_widget, 19) #endif #ifdef TRACERVBRIDGEMODULE_20_PRESENT -INSTANTIATE_TRACERV(add_bridge_driver, 20) +INSTANTIATE_TRACERV(registry.add_widget, 20) #endif #ifdef TRACERVBRIDGEMODULE_21_PRESENT -INSTANTIATE_TRACERV(add_bridge_driver, 21) +INSTANTIATE_TRACERV(registry.add_widget, 21) #endif #ifdef TRACERVBRIDGEMODULE_22_PRESENT -INSTANTIATE_TRACERV(add_bridge_driver, 22) +INSTANTIATE_TRACERV(registry.add_widget, 22) #endif #ifdef TRACERVBRIDGEMODULE_23_PRESENT -INSTANTIATE_TRACERV(add_bridge_driver, 23) +INSTANTIATE_TRACERV(registry.add_widget, 23) #endif #ifdef TRACERVBRIDGEMODULE_24_PRESENT -INSTANTIATE_TRACERV(add_bridge_driver, 24) +INSTANTIATE_TRACERV(registry.add_widget, 24) #endif #ifdef TRACERVBRIDGEMODULE_25_PRESENT -INSTANTIATE_TRACERV(add_bridge_driver, 25) +INSTANTIATE_TRACERV(registry.add_widget, 25) #endif #ifdef TRACERVBRIDGEMODULE_26_PRESENT -INSTANTIATE_TRACERV(add_bridge_driver, 26) +INSTANTIATE_TRACERV(registry.add_widget, 26) #endif #ifdef TRACERVBRIDGEMODULE_27_PRESENT -INSTANTIATE_TRACERV(add_bridge_driver, 27) +INSTANTIATE_TRACERV(registry.add_widget, 27) #endif #ifdef TRACERVBRIDGEMODULE_28_PRESENT -INSTANTIATE_TRACERV(add_bridge_driver, 28) +INSTANTIATE_TRACERV(registry.add_widget, 28) #endif #ifdef TRACERVBRIDGEMODULE_29_PRESENT -INSTANTIATE_TRACERV(add_bridge_driver, 29) +INSTANTIATE_TRACERV(registry.add_widget, 29) #endif #ifdef TRACERVBRIDGEMODULE_30_PRESENT -INSTANTIATE_TRACERV(add_bridge_driver, 30) +INSTANTIATE_TRACERV(registry.add_widget, 30) #endif #ifdef TRACERVBRIDGEMODULE_31_PRESENT -INSTANTIATE_TRACERV(add_bridge_driver, 31) +INSTANTIATE_TRACERV(registry.add_widget, 31) #endif #ifdef DROMAJOBRIDGEMODULE_0_PRESENT @@ -458,50 +550,42 @@ INSTANTIATE_TRACERV(add_bridge_driver, 31) DROMAJOBRIDGEMODULE_0_to_cpu_stream_full_address) #endif -#ifdef GROUNDTESTBRIDGEMODULE_checks -GROUNDTESTBRIDGEMODULE_checks; -#endif // GROUNDTESTBRIDGEMODULE_checks - #ifdef GROUNDTESTBRIDGEMODULE_0_PRESENT - add_bridge_driver(new groundtest_t( - *simif, args, GROUNDTESTBRIDGEMODULE_0_substruct_create)); + registry.add_widget(new groundtest_t( + simif, args, GROUNDTESTBRIDGEMODULE_0_substruct_create)); #endif #ifdef GROUNDTESTBRIDGEMODULE_1_PRESENT - add_bridge_driver(new groundtest_t( - *simif, args, GROUNDTESTBRIDGEMODULE_1_substruct_create)); + registry.add_widget(new groundtest_t( + simif, args, GROUNDTESTBRIDGEMODULE_1_substruct_create)); #endif #ifdef GROUNDTESTBRIDGEMODULE_2_PRESENT - add_bridge_driver(new groundtest_t( - *simif, args, GROUNDTESTBRIDGEMODULE_2_substruct_create)); + registry.add_widget(new groundtest_t( + simif, args, GROUNDTESTBRIDGEMODULE_2_substruct_create)); #endif #ifdef GROUNDTESTBRIDGEMODULE_3_PRESENT - add_bridge_driver(new groundtest_t( - *simif, args, GROUNDTESTBRIDGEMODULE_3_substruct_create)); + registry.add_widget(new groundtest_t( + simif, args, GROUNDTESTBRIDGEMODULE_3_substruct_create)); #endif #ifdef GROUNDTESTBRIDGEMODULE_4_PRESENT - add_bridge_driver(new groundtest_t( - *simif, args, GROUNDTESTBRIDGEMODULE_4_substruct_create)); + registry.add_widget(new groundtest_t( + simif, args, GROUNDTESTBRIDGEMODULE_4_substruct_create)); #endif #ifdef GROUNDTESTBRIDGEMODULE_5_PRESENT - add_bridge_driver(new groundtest_t( - *simif, args, GROUNDTESTBRIDGEMODULE_5_substruct_create)); + registry.add_widget(new groundtest_t( + simif, args, GROUNDTESTBRIDGEMODULE_5_substruct_create)); #endif #ifdef GROUNDTESTBRIDGEMODULE_6_PRESENT - add_bridge_driver(new groundtest_t( - *simif, args, GROUNDTESTBRIDGEMODULE_6_substruct_create)); + registry.add_widget(new groundtest_t( + simif, args, GROUNDTESTBRIDGEMODULE_6_substruct_create)); #endif #ifdef GROUNDTESTBRIDGEMODULE_7_PRESENT - add_bridge_driver(new groundtest_t( - *simif, args, GROUNDTESTBRIDGEMODULE_7_substruct_create)); + registry.add_widget(new groundtest_t( + simif, args, GROUNDTESTBRIDGEMODULE_7_substruct_create)); #endif -#ifdef AUTOCOUNTERBRIDGEMODULE_checks -AUTOCOUNTERBRIDGEMODULE_checks; -#endif // AUTOCOUNTERBRIDGEMODULE_checks - #define INSTANTIATE_AUTOCOUNTER(FUNC, IDX) \ FUNC(new autocounter_t( \ - *simif, \ + simif, \ args, \ AUTOCOUNTERBRIDGEMODULE_##IDX##_substruct_create, \ AddressMap( \ @@ -525,82 +609,74 @@ AUTOCOUNTERBRIDGEMODULE_checks; IDX)); #ifdef AUTOCOUNTERBRIDGEMODULE_0_PRESENT - INSTANTIATE_AUTOCOUNTER(add_bridge_driver, 0) + INSTANTIATE_AUTOCOUNTER(registry.add_widget, 0) #endif #ifdef AUTOCOUNTERBRIDGEMODULE_1_PRESENT - INSTANTIATE_AUTOCOUNTER(add_bridge_driver, 1) + INSTANTIATE_AUTOCOUNTER(registry.add_widget, 1) #endif #ifdef AUTOCOUNTERBRIDGEMODULE_2_PRESENT - INSTANTIATE_AUTOCOUNTER(add_bridge_driver, 2) + INSTANTIATE_AUTOCOUNTER(registry.add_widget, 2) #endif #ifdef AUTOCOUNTERBRIDGEMODULE_3_PRESENT - INSTANTIATE_AUTOCOUNTER(add_bridge_driver, 3) + INSTANTIATE_AUTOCOUNTER(registry.add_widget, 3) #endif #ifdef AUTOCOUNTERBRIDGEMODULE_4_PRESENT - INSTANTIATE_AUTOCOUNTER(add_bridge_driver, 4) + INSTANTIATE_AUTOCOUNTER(registry.add_widget, 4) #endif #ifdef AUTOCOUNTERBRIDGEMODULE_5_PRESENT - INSTANTIATE_AUTOCOUNTER(add_bridge_driver, 5) + INSTANTIATE_AUTOCOUNTER(registry.add_widget, 5) #endif #ifdef AUTOCOUNTERBRIDGEMODULE_6_PRESENT - INSTANTIATE_AUTOCOUNTER(add_bridge_driver, 6) + INSTANTIATE_AUTOCOUNTER(registry.add_widget, 6) #endif #ifdef AUTOCOUNTERBRIDGEMODULE_7_PRESENT - INSTANTIATE_AUTOCOUNTER(add_bridge_driver, 7) + INSTANTIATE_AUTOCOUNTER(registry.add_widget, 7) #endif -#ifdef ASSERTBRIDGEMODULE_checks -ASSERTBRIDGEMODULE_checks; -#endif // ASSERTBRIDGEMODULE_checks - #ifdef ASSERTBRIDGEMODULE_0_PRESENT - add_bridge_driver(new synthesized_assertions_t(*simif, args, + registry.add_widget(new synthesized_assertions_t(simif, args, ASSERTBRIDGEMODULE_0_substruct_create, ASSERTBRIDGEMODULE_0_assert_messages)); #endif #ifdef ASSERTBRIDGEMODULE_1_PRESENT - add_bridge_driver(new synthesized_assertions_t(*simif, args, + registry.add_widget(new synthesized_assertions_t(simif, args, ASSERTBRIDGEMODULE_1_substruct_create, ASSERTBRIDGEMODULE_1_assert_messages)); #endif #ifdef ASSERTBRIDGEMODULE_2_PRESENT - add_bridge_driver(new synthesized_assertions_t(*simif, args, + registry.add_widget(new synthesized_assertions_t(simif, args, ASSERTBRIDGEMODULE_2_substruct_create, ASSERTBRIDGEMODULE_2_assert_messages)); #endif #ifdef ASSERTBRIDGEMODULE_3_PRESENT - add_bridge_driver(new synthesized_assertions_t(*simif, args, + registry.add_widget(new synthesized_assertions_t(simif, args, ASSERTBRIDGEMODULE_3_substruct_create, ASSERTBRIDGEMODULE_3_assert_messages)); #endif #ifdef ASSERTBRIDGEMODULE_4_PRESENT - add_bridge_driver(new synthesized_assertions_t(*simif, args, + registry.add_widget(new synthesized_assertions_t(simif, args, ASSERTBRIDGEMODULE_4_substruct_create, ASSERTBRIDGEMODULE_4_assert_messages)); #endif #ifdef ASSERTBRIDGEMODULE_5_PRESENT - add_bridge_driver(new synthesized_assertions_t(*simif, args, + registry.add_widget(new synthesized_assertions_t(simif, args, ASSERTBRIDGEMODULE_5_substruct_create, ASSERTBRIDGEMODULE_5_assert_messages)); #endif #ifdef ASSERTBRIDGEMODULE_6_PRESENT - add_bridge_driver(new synthesized_assertions_t(*simif, args, + registry.add_widget(new synthesized_assertions_t(simif, args, ASSERTBRIDGEMODULE_6_substruct_create, ASSERTBRIDGEMODULE_6_assert_messages)); #endif #ifdef ASSERTBRIDGEMODULE_7_PRESENT - add_bridge_driver(new synthesized_assertions_t(*simif, args, + registry.add_widget(new synthesized_assertions_t(simif, args, ASSERTBRIDGEMODULE_7_substruct_create, ASSERTBRIDGEMODULE_7_assert_messages)); #endif -#ifdef PRINTBRIDGEMODULE_checks -PRINTBRIDGEMODULE_checks; -#endif // PRINTBRIDGEMODULE_checks - #define INSTANTIATE_PRINTF(FUNC, IDX) \ - FUNC(new synthesized_prints_t(*simif, \ - simif->get_managed_stream(), \ + FUNC(new synthesized_prints_t(simif, \ + *registry.get_stream_engine(), \ args, \ PRINTBRIDGEMODULE_##IDX##_substruct_create, \ PRINTBRIDGEMODULE_##IDX##_print_count, \ @@ -618,36 +694,32 @@ PRINTBRIDGEMODULE_checks; IDX)); #ifdef PRINTBRIDGEMODULE_0_PRESENT - INSTANTIATE_PRINTF(add_bridge_driver,0) + INSTANTIATE_PRINTF(registry.add_widget,0) #endif #ifdef PRINTBRIDGEMODULE_1_PRESENT - INSTANTIATE_PRINTF(add_bridge_driver,1) + INSTANTIATE_PRINTF(registry.add_widget,1) #endif #ifdef PRINTBRIDGEMODULE_2_PRESENT - INSTANTIATE_PRINTF(add_bridge_driver,2) + INSTANTIATE_PRINTF(registry.add_widget,2) #endif #ifdef PRINTBRIDGEMODULE_3_PRESENT - INSTANTIATE_PRINTF(add_bridge_driver,3) + INSTANTIATE_PRINTF(registry.add_widget,3) #endif #ifdef PRINTBRIDGEMODULE_4_PRESENT - INSTANTIATE_PRINTF(add_bridge_driver,4) + INSTANTIATE_PRINTF(registry.add_widget,4) #endif #ifdef PRINTBRIDGEMODULE_5_PRESENT - INSTANTIATE_PRINTF(add_bridge_driver,5) + INSTANTIATE_PRINTF(registry.add_widget,5) #endif #ifdef PRINTBRIDGEMODULE_6_PRESENT - INSTANTIATE_PRINTF(add_bridge_driver,6) + INSTANTIATE_PRINTF(registry.add_widget,6) #endif #ifdef PRINTBRIDGEMODULE_7_PRESENT - INSTANTIATE_PRINTF(add_bridge_driver,7) + INSTANTIATE_PRINTF(registry.add_widget,7) #endif -#ifdef PLUSARGSBRIDGEMODULE_checks -PLUSARGSBRIDGEMODULE_checks; -#endif // PLUSARGSBRIDGEMODULE_checks - #define INSTANTIATE_PLUSARGS(FUNC, IDX) \ - FUNC(new plusargs_t(*simif, \ + FUNC(new plusargs_t(simif, \ args, \ PLUSARGSBRIDGEMODULE_##IDX##_substruct_create, \ PLUSARGSBRIDGEMODULE_##IDX##_name, \ @@ -657,36 +729,32 @@ PLUSARGSBRIDGEMODULE_checks; PLUSARGSBRIDGEMODULE_##IDX##_slice_addrs)); #ifdef PLUSARGSBRIDGEMODULE_0_PRESENT - INSTANTIATE_PLUSARGS(add_bridge_driver, 0) + INSTANTIATE_PLUSARGS(registry.add_widget, 0) #endif #ifdef PLUSARGSBRIDGEMODULE_1_PRESENT - INSTANTIATE_PLUSARGS(add_bridge_driver, 1) + INSTANTIATE_PLUSARGS(registry.add_widget, 1) #endif #ifdef PLUSARGSBRIDGEMODULE_2_PRESENT - INSTANTIATE_PLUSARGS(add_bridge_driver, 2) + INSTANTIATE_PLUSARGS(registry.add_widget, 2) #endif #ifdef PLUSARGSBRIDGEMODULE_3_PRESENT - INSTANTIATE_PLUSARGS(add_bridge_driver, 3) + INSTANTIATE_PLUSARGS(registry.add_widget, 3) #endif #ifdef PLUSARGSBRIDGEMODULE_4_PRESENT - INSTANTIATE_PLUSARGS(add_bridge_driver, 4) + INSTANTIATE_PLUSARGS(registry.add_widget, 4) #endif #ifdef PLUSARGSBRIDGEMODULE_5_PRESENT - INSTANTIATE_PLUSARGS(add_bridge_driver, 5) + INSTANTIATE_PLUSARGS(registry.add_widget, 5) #endif #ifdef PLUSARGSBRIDGEMODULE_6_PRESENT - INSTANTIATE_PLUSARGS(add_bridge_driver, 6) + INSTANTIATE_PLUSARGS(registry.add_widget, 6) #endif #ifdef PLUSARGSBRIDGEMODULE_7_PRESENT - INSTANTIATE_PLUSARGS(add_bridge_driver, 7) + INSTANTIATE_PLUSARGS(registry.add_widget, 7) #endif -#ifdef TERMINATIONBRIDGEMODULE_checks -TERMINATIONBRIDGEMODULE_checks; -#endif // TERMINATIONBRIDGEMODULE_checks - #define INSTANTIATE_TERMINATION(FUNC, IDX) \ - FUNC(new termination_t(*simif, \ + FUNC(new termination_t(simif, \ args, \ TERMINATIONBRIDGEMODULE_##IDX##_substruct_create, \ TERMINATIONBRIDGEMODULE_##IDX##_message_count, \ @@ -694,50 +762,51 @@ TERMINATIONBRIDGEMODULE_checks; TERMINATIONBRIDGEMODULE_##IDX##_message)); #ifdef TERMINATIONBRIDGEMODULE_0_PRESENT - INSTANTIATE_TERMINATION(add_bridge_driver, 0) + INSTANTIATE_TERMINATION(registry.add_widget, 0) #endif #ifdef TERMINATIONBRIDGEMODULE_1_PRESENT - INSTANTIATE_TERMINATION(add_bridge_driver, 1) + INSTANTIATE_TERMINATION(registry.add_widget, 1) #endif #ifdef TERMINATIONBRIDGEMODULE_2_PRESENT - INSTANTIATE_TERMINATION(add_bridge_driver, 2) + INSTANTIATE_TERMINATION(registry.add_widget, 2) #endif #ifdef TERMINATIONBRIDGEMODULE_3_PRESENT - INSTANTIATE_TERMINATION(add_bridge_driver, 3) + INSTANTIATE_TERMINATION(registry.add_widget, 3) #endif #ifdef TERMINATIONBRIDGEMODULE_4_PRESENT - INSTANTIATE_TERMINATION(add_bridge_driver, 4) + INSTANTIATE_TERMINATION(registry.add_widget, 4) #endif #ifdef TERMINATIONBRIDGEMODULE_5_PRESENT - INSTANTIATE_TERMINATION(add_bridge_driver, 5) + INSTANTIATE_TERMINATION(registry.add_widget, 5) #endif #ifdef TERMINATIONBRIDGEMODULE_6_PRESENT - INSTANTIATE_TERMINATION(add_bridge_driver, 6) + INSTANTIATE_TERMINATION(registry.add_widget, 6) #endif #ifdef TERMINATIONBRIDGEMODULE_7_PRESENT - INSTANTIATE_TERMINATION(add_bridge_driver, 7) + INSTANTIATE_TERMINATION(registry.add_widget, 7) #endif #ifdef TERMINATIONBRIDGEMODULE_8_PRESENT - INSTANTIATE_TERMINATION(add_bridge_driver, 8) + INSTANTIATE_TERMINATION(registry.add_widget, 8) #endif #ifdef TERMINATIONBRIDGEMODULE_9_PRESENT - INSTANTIATE_TERMINATION(add_bridge_driver, 9) + INSTANTIATE_TERMINATION(registry.add_widget, 9) #endif #ifdef TERMINATIONBRIDGEMODULE_10_PRESENT - INSTANTIATE_TERMINATION(add_bridge_driver, 10) + INSTANTIATE_TERMINATION(registry.add_widget, 10) #endif #ifdef TERMINATIONBRIDGEMODULE_11_PRESENT - INSTANTIATE_TERMINATION(add_bridge_driver, 11) + INSTANTIATE_TERMINATION(registry.add_widget, 11) #endif #ifdef TERMINATIONBRIDGEMODULE_12_PRESENT - INSTANTIATE_TERMINATION(add_bridge_driver, 12) + INSTANTIATE_TERMINATION(registry.add_widget, 12) #endif #ifdef TERMINATIONBRIDGEMODULE_13_PRESENT - INSTANTIATE_TERMINATION(add_bridge_driver, 13) + INSTANTIATE_TERMINATION(registry.add_widget, 13) #endif #ifdef TERMINATIONBRIDGEMODULE_14_PRESENT - INSTANTIATE_TERMINATION(add_bridge_driver, 14) + INSTANTIATE_TERMINATION(registry.add_widget, 14) #endif #ifdef TERMINATIONBRIDGEMODULE_15_PRESENT - INSTANTIATE_TERMINATION(add_bridge_driver, 15) + INSTANTIATE_TERMINATION(registry.add_widget, 15) #endif +// DOC include end: Bridge Driver Registration diff --git a/sim/midas/src/main/cc/core/simif.cc b/sim/midas/src/main/cc/core/simif.cc index 2dad873963..162cea690b 100644 --- a/sim/midas/src/main/cc/core/simif.cc +++ b/sim/midas/src/main/cc/core/simif.cc @@ -4,18 +4,11 @@ #include "core/simulation.h" #include "core/stream_engine.h" -extern std::unique_ptr -create_simulation(const std::vector &args, simif_t *simif); +#include simif_t::simif_t(const TargetConfig &config, const std::vector &args) - : config(config), loadmem(*this, - LOADMEMWIDGET_0_substruct_create, - config.mem, - LOADMEMWIDGET_0_mem_data_chunk), - clock(*this, CLOCKBRIDGEMODULE_0_substruct_create), - master(*this, SIMULATIONMASTER_0_substruct_create), - sim(create_simulation(args, this)) { + : config(config), args(args) { for (auto &arg : args) { if (arg.find("+fastloadmem") == 0) { fastloadmem = true; @@ -31,27 +24,44 @@ simif_t::simif_t(const TargetConfig &config, simif_t::~simif_t() {} +CPUManagedStreamIO &simif_t::get_cpu_managed_stream_io() { + std::cerr << "CPU-managed streams are not supported" << std::endl; + abort(); +} + +FPGAManagedStreamIO &simif_t::get_fpga_managed_stream_io() { + std::cerr << "FPGA-managed streams are not supported" << std::endl; + abort(); +} + void simif_t::target_init() { + auto &master = registry->get_widget(); + auto &loadmem = registry->get_widget(); + // Do any post-constructor initialization required before requesting MMIO while (!master.is_init_done()) ; - if (!fastloadmem && !load_mem_path.empty()) { - loadmem.load_mem_from_file(load_mem_path); - } - - if (managed_stream) { - managed_stream->init(); + if (auto *stream = registry->get_stream_engine()) { + stream->init(); } -} - -int simif_t::simulation_run() { - target_init(); if (do_zero_out_dram) { fprintf(stderr, "Zeroing out FPGA DRAM. This will take a few seconds...\n"); loadmem.zero_out_dram(); } + if (!fastloadmem && !load_mem_path.empty()) { + loadmem.load_mem_from_file(load_mem_path); + } +} + +extern std::unique_ptr +create_simulation(const std::vector &args, simif_t &simif); + +int simif_t::simulation_run() { + registry.reset(new widget_registry_t(config, *this, args)); + sim = create_simulation(args, *this); + target_init(); return sim->execute_simulation_flow(); } diff --git a/sim/midas/src/main/cc/core/simif.h b/sim/midas/src/main/cc/core/simif.h index b1410ec754..a748659787 100644 --- a/sim/midas/src/main/cc/core/simif.h +++ b/sim/midas/src/main/cc/core/simif.h @@ -17,9 +17,12 @@ #include "bridges/loadmem.h" #include "bridges/master.h" #include "core/timing.h" +#include "core/widget_registry.h" class StreamEngine; class simulation_t; +class CPUManagedStreamIO; +class FPGAManagedStreamIO; /** \class simif_t * @@ -53,13 +56,13 @@ class simif_t { /** * Returns true if the simulation is complete. */ - inline bool done() { return master.is_done(); } + inline bool done() { return registry->get_widget().is_done(); } /** * Advance the simulation a given number of steps. */ inline void take_steps(size_t n, bool blocking) { - return master.step(n, blocking); + return registry->get_widget().step(n, blocking); } // Host-platform interface. See simif_f1; simif_emul for implementation @@ -82,6 +85,22 @@ class simif_t { */ virtual uint32_t read(size_t addr) = 0; + /** + * Return a functor accessing CPU-managed streams. + * + * This method aborts if it is not reimplemented by the desired host + * platform simif. + */ + virtual CPUManagedStreamIO &get_cpu_managed_stream_io(); + + /** + * Return a functor accessing FPGA-managed streams. + * + * This method aborts if it is not reimplemented by the desired host platform + * simif. + */ + virtual FPGAManagedStreamIO &get_fpga_managed_stream_io(); + // End host-platform interface. /** @@ -90,25 +109,26 @@ class simif_t { * The target cycle is based on the number of clock tokens enqueued * (will report a larger number). */ - uint64_t actual_tcycle() { return clock.tcycle(); } + uint64_t actual_tcycle() { + return registry->get_widget().tcycle(); + } /** * Provides the current host cycle. */ - uint64_t actual_hcycle() { return clock.hcycle(); } + uint64_t actual_hcycle() { + return registry->get_widget().hcycle(); + } /** - * Return a reference to the LoadMem widget. + * Return the name of the simulated target. */ - loadmem_t &get_loadmem() { return loadmem; } - - /// Return the name of the simulated target. std::string_view get_target_name() const { return config.target_name; } /** - * Return a reference to the managed stream engine. + * Return a reference to the registry which owns all widgets. */ - StreamEngine &get_managed_stream() { return *managed_stream; } + widget_registry_t &get_registry() { return *registry; } private: /** @@ -131,24 +151,14 @@ class simif_t { const TargetConfig config; /** - * LoadMem widget driver. - */ - loadmem_t loadmem; - - /** - * ClockBridge driver. - */ - clockmodule_t clock; - - /** - * SimulationMaster widget. + * Saved command-line arguments. */ - master_t master; + std::vector args; /** - * Widget implementing CPU-managed streams. + * Helper holding references to all bridges. */ - std::unique_ptr managed_stream; + std::unique_ptr registry; /** * Reference to the user-defined bits of the simulation. diff --git a/sim/midas/src/main/cc/core/widget_registry.cc b/sim/midas/src/main/cc/core/widget_registry.cc new file mode 100644 index 0000000000..ecccb9a5a4 --- /dev/null +++ b/sim/midas/src/main/cc/core/widget_registry.cc @@ -0,0 +1,73 @@ +// See LICENSE for license details. + +#include "widget_registry.h" + +#include "core/bridge_driver.h" + +#include "bridges/autocounter.h" +#include "bridges/clock.h" +#include "bridges/cpu_managed_stream.h" +#include "bridges/fased_memory_timing_model.h" +#include "bridges/fpga_managed_stream.h" +#include "bridges/fpga_model.h" +#include "bridges/loadmem.h" +#include "bridges/master.h" +#include "bridges/plusargs.h" +#include "bridges/reset_pulse.h" +#include "bridges/synthesized_assertions.h" +#include "bridges/synthesized_prints.h" +#include "bridges/termination.h" + +#ifdef PEEKPOKEBRIDGEMODULE_0_PRESENT +#include "bridges/peek_poke.h" +#endif +#ifdef BLOCKDEVBRIDGEMODULE_0_PRESENT +#include "bridges/blockdev.h" +#endif +#ifdef DROMAJOBRIDGEMODULE_0_PRESENT +#include "bridges/dromajo.h" +#endif +#ifdef GROUNDTESTBRIDGEMODULE_0_PRESENT +#include "bridges/groundtest.h" +#endif +#ifdef SERIALBRIDGEMODULE_0_PRESENT +#include "bridges/serial.h" +#endif +#ifdef SIMPLENICBRIDGEMODULE_0_PRESENT +#include "bridges/simplenic.h" +#endif +#ifdef TRACERVBRIDGEMODULE_0_PRESENT +#include "bridges/tracerv.h" +#endif +#ifdef UARTBRIDGEMODULE_0_PRESENT +#include "bridges/uart.h" +#endif + +widget_registry_t::widget_registry_t(const TargetConfig &config, + simif_t &simif, + const std::vector &args) + : config(config) { + + widget_registry_t ®istry = *this; +#include "constructor.h" +} + +widget_registry_t::~widget_registry_t() = default; + +void widget_registry_t::add_widget(widget_t *widget) { + widgets[widget->kind].emplace_back(widget); +} + +void widget_registry_t::add_widget(bridge_driver_t *widget) { + widgets[widget->kind].emplace_back(widget); + all_bridges.push_back(widget); +} + +void widget_registry_t::add_widget(FASEDMemoryTimingModel *widget) { + widgets[widget->kind].emplace_back(widget); + all_models.push_back(widget); +} + +void widget_registry_t::add_widget(StreamEngine *widget) { + stream_engine.reset(widget); +} diff --git a/sim/midas/src/main/cc/core/widget_registry.h b/sim/midas/src/main/cc/core/widget_registry.h new file mode 100644 index 0000000000..6b74b16f67 --- /dev/null +++ b/sim/midas/src/main/cc/core/widget_registry.h @@ -0,0 +1,120 @@ +// See LICENSE for license details. + +#ifndef __BRIDGE_REGISTRY_H +#define __BRIDGE_REGISTRY_H + +#include "core/config.h" +#include "core/widget.h" + +#include + +#include +#include +#include + +class FASEDMemoryTimingModel; +class bridge_driver_t; +class widget_t; +class StreamEngine; + +/** + * Unique class responsible for the creating and ownership of all bridges. + * + * The bridges of a design are registered with the registry through the + * `add_widget` methods for them to be retrieved later through the appropriate + * getters. + */ +class widget_registry_t final { +public: + widget_registry_t(const TargetConfig &config, + simif_t &simif, + const std::vector &args); + + ~widget_registry_t(); + + /** + * Return a list of pointers to all bridges of a type. + * + * @tparam T Type of bridge to fetch. + * @return List of non-owning pointers to bridges. + */ + template + std::vector get_bridges() { + std::vector bridge_list; + for (auto &bridge : widgets[&T::KIND]) { + bridge_list.push_back(static_cast(bridge.get())); + } + return bridge_list; + } + + /** + * Return a widget of a particular kind which has a single instance. + * + * This function should only be used with widgets that have a unique instance. + * If multiple widgets of the same kind were registered or the widget does + * not exist, the function fails. + * + * @tparam T Type of the widget to fetch + * @return Reference to the widget. + */ + template + T &get_widget() { + auto it = widgets.find(&T::KIND); + assert(it != widgets.end() && "no bridges registered"); + assert(it->second.size() == 1 && "multiple bridges registered"); + return *static_cast(it->second[0].get()); + } + + /** + * Returns all bridges in the deterministic order of their construction. + * + * Hash map traversals are not deterministic, especially if keys are pointers. + * To be able to iterate over bridges in a stable order across different runs, + * the bridges are also stored in a list in the order they are built. + */ + const std::vector &get_all_bridges() { + return all_bridges; + } + + /** + * Returns all models in the deterministic order of their construction. + */ + const std::vector &get_all_models() { + return all_models; + } + + /** + * Returns a pointer to the stream engine widget, if one exists. + */ + StreamEngine *get_stream_engine() { return stream_engine.get(); } + + void add_widget(widget_t *widget); + void add_widget(bridge_driver_t *widget); + void add_widget(FASEDMemoryTimingModel *widget); + void add_widget(StreamEngine *widget); + +private: + // Target-specific configuration. + const TargetConfig config; + + // Mapping from bridge kinds to the list of bridges of that kind. + using widget_list_t = std::vector>; + std::unordered_map widgets; + + /** + * Widget implementing CPU-managed streams. + */ + std::unique_ptr stream_engine; + + /** + * List of all bridges, maintained in a deterministic order. + */ + std::vector all_bridges; + + /** + * List of all models, maintained in a deterministic order. + */ + std::vector all_models; +}; + +#endif // __BRIDGE_REGISTRY_H diff --git a/sim/midas/src/main/cc/emul/simif_emul.cc b/sim/midas/src/main/cc/emul/simif_emul.cc index edda17ec2e..5812262a0d 100644 --- a/sim/midas/src/main/cc/emul/simif_emul.cc +++ b/sim/midas/src/main/cc/emul/simif_emul.cc @@ -43,13 +43,11 @@ simif_emul_t::simif_emul_t(const TargetConfig &config, if (std::optional conf = config.cpu_managed) { assert(!config.fpga_managed && "stream should be CPU or FPGA managed"); cpu_managed_stream_io.reset(new CPUManagedStreamIOImpl(*this, *conf)); - managed_stream.reset(new CPUManagedStreamWidget(*cpu_managed_stream_io)); } if (std::optional conf = config.fpga_managed) { assert(!config.cpu_managed && "stream should be CPU or FPGA managed"); fpga_managed_stream_io.reset(new FPGAManagedStreamIOImpl(*this, *conf)); - managed_stream.reset(new FPGAManagedStreamWidget(*fpga_managed_stream_io)); } // Set up the simulation thread. diff --git a/sim/midas/src/main/cc/emul/simif_emul.h b/sim/midas/src/main/cc/emul/simif_emul.h index 63d2e4ef8f..aaa36dbc17 100644 --- a/sim/midas/src/main/cc/emul/simif_emul.h +++ b/sim/midas/src/main/cc/emul/simif_emul.h @@ -113,6 +113,20 @@ class simif_emul_t : public simif_t { */ std::vector> slave; + /** + * Return the wrapper around the CPU-managed stream AXI interface. + */ + CPUManagedStreamIO &get_cpu_managed_stream_io() override { + return *cpu_managed_stream_io; + } + + /** + * Return the wrapper around the FPGA-managed stream AXI interface. + */ + FPGAManagedStreamIO &get_fpga_managed_stream_io() override { + return *fpga_managed_stream_io; + } + protected: // The maximum number of cycles the RTL simulator can advance before // switching back to the driver process. +fuzz-host-timings sets this to a diff --git a/sim/midas/src/main/cc/simif_f1.cc b/sim/midas/src/main/cc/simif_f1.cc index 646398bd5b..ccd47e7950 100644 --- a/sim/midas/src/main/cc/simif_f1.cc +++ b/sim/midas/src/main/cc/simif_f1.cc @@ -56,8 +56,6 @@ simif_f1_t::simif_f1_t(const TargetConfig &config, slot_id = 0; } fpga_setup(slot_id); - - managed_stream.reset(new CPUManagedStreamWidget(*this)); } void simif_f1_t::check_rc(int rc, char *infostr) { diff --git a/sim/midas/src/main/cc/simif_f1_xsim.cc b/sim/midas/src/main/cc/simif_f1_xsim.cc index 9dba2d29f9..34417cd0a2 100644 --- a/sim/midas/src/main/cc/simif_f1_xsim.cc +++ b/sim/midas/src/main/cc/simif_f1_xsim.cc @@ -46,8 +46,6 @@ simif_f1_xsim_t::simif_f1_xsim_t(const TargetConfig &config, driver_to_xsim_fd = open(driver_to_xsim, O_WRONLY); fprintf(stderr, "opening xsim to driver\n"); xsim_to_driver_fd = open(xsim_to_driver, O_RDONLY); - - managed_stream.reset(new CPUManagedStreamWidget(*this)); } void simif_f1_xsim_t::check_rc(int rc, char *infostr) {} diff --git a/sim/midas/src/main/cc/simif_vitis.cc b/sim/midas/src/main/cc/simif_vitis.cc index 6614e06fae..2c083b1061 100644 --- a/sim/midas/src/main/cc/simif_vitis.cc +++ b/sim/midas/src/main/cc/simif_vitis.cc @@ -124,6 +124,13 @@ uint32_t simif_vitis_t::read(size_t addr) { return value & 0xFFFFFFFF; } +AXIStreamIO &simif_vitis_t::get_cpu_managed_stream_io() override { + std::cerr << "FPGA-to-CPU Bridge streams are not yet supported on " + "vitis-based FPGA deployments." + << std::endl; + exit(1); +} + uint32_t simif_vitis_t::is_write_ready() { uint64_t addr = 0x4; uint32_t value; diff --git a/sim/src/main/cc/bridges/BridgeHarness.cc b/sim/src/main/cc/bridges/BridgeHarness.cc index 5854f6b51e..6c9ef82912 100644 --- a/sim/src/main/cc/bridges/BridgeHarness.cc +++ b/sim/src/main/cc/bridges/BridgeHarness.cc @@ -6,38 +6,29 @@ #include "bridges/uart.h" #include "core/bridge_driver.h" -BridgeHarness::BridgeHarness(const std::vector &args, - simif_t *simif) - : simulation_t(*simif, args), simif(simif) {} +BridgeHarness::BridgeHarness(const std::vector &args, simif_t &sim) + : simulation_t(sim, args), + peek_poke(sim.get_registry().get_widget()) {} BridgeHarness::~BridgeHarness() = default; -void BridgeHarness::add_bridge_driver(bridge_driver_t *bridge) { - bridges.emplace_back(bridge); -} - -void BridgeHarness::add_bridge_driver(peek_poke_t *bridge) { - peek_poke.reset(bridge); -} - void BridgeHarness::simulation_init() { -#include "core/constructor.h" - for (auto &bridge : bridges) { + for (auto &bridge : sim.get_registry().get_all_bridges()) { bridge->init(); } } int BridgeHarness::simulation_run() { // Reset the DUT. - peek_poke->poke("reset", 1, /*blocking=*/true); - simif->take_steps(1, /*blocking=*/true); - peek_poke->poke("reset", 0, /*blocking=*/true); - simif->take_steps(1, /*blocking=*/true); + peek_poke.poke("reset", 1, /*blocking=*/true); + sim.take_steps(1, /*blocking=*/true); + peek_poke.poke("reset", 0, /*blocking=*/true); + sim.take_steps(1, /*blocking=*/true); // Tick until all requests are serviced. - simif->take_steps(get_step_limit(), /*blocking=*/false); - for (unsigned i = 0; i < get_tick_limit() && !simif->done(); ++i) { - for (auto &bridge : bridges) { + sim.take_steps(get_step_limit(), /*blocking=*/false); + for (unsigned i = 0; i < get_tick_limit() && !sim.done(); ++i) { + for (auto &bridge : sim.get_registry().get_all_bridges()) { bridge->tick(); } } @@ -47,7 +38,7 @@ int BridgeHarness::simulation_run() { } void BridgeHarness::simulation_finish() { - for (auto &bridge : bridges) { + for (auto &bridge : sim.get_registry().get_all_bridges()) { bridge->finish(); } } diff --git a/sim/src/main/cc/bridges/BridgeHarness.h b/sim/src/main/cc/bridges/BridgeHarness.h index ea40bdb904..c5907c9bee 100644 --- a/sim/src/main/cc/bridges/BridgeHarness.h +++ b/sim/src/main/cc/bridges/BridgeHarness.h @@ -17,13 +17,10 @@ class bridge_driver_t; */ class BridgeHarness : public simulation_t { public: - BridgeHarness(const std::vector &args, simif_t *simif); + BridgeHarness(const std::vector &args, simif_t &sim); ~BridgeHarness() override; - void add_bridge_driver(bridge_driver_t *bridge); - void add_bridge_driver(peek_poke_t *bridge); - void simulation_init() override; int simulation_run() override; void simulation_finish() override; @@ -33,14 +30,12 @@ class BridgeHarness : public simulation_t { virtual unsigned get_tick_limit() const = 0; private: - simif_t *simif; - std::vector> bridges; - std::unique_ptr peek_poke; + peek_poke_t &peek_poke; }; #define TEST_MAIN(CLASS_NAME) \ std::unique_ptr create_simulation( \ - const std::vector &args, simif_t *simif) { \ - return std::make_unique(args, simif); \ + const std::vector &args, simif_t &sim) { \ + return std::make_unique(args, sim); \ } #endif // MIDAEXAMPLES_BRIDGEHARNESS_H diff --git a/sim/src/main/cc/fasedtests/fasedtests_top.cc b/sim/src/main/cc/fasedtests/fasedtests_top.cc index 29f3d56ab5..888354ff26 100644 --- a/sim/src/main/cc/fasedtests/fasedtests_top.cc +++ b/sim/src/main/cc/fasedtests/fasedtests_top.cc @@ -11,32 +11,14 @@ class fasedtests_top_t : public systematic_scheduler_t, public simulation_t { public: - fasedtests_top_t(const std::vector &args, simif_t *simif); + fasedtests_top_t(const std::vector &args, simif_t &sim); ~fasedtests_top_t() override = default; void simulation_init() override; void simulation_finish() override; int simulation_run() override; -protected: - void add_bridge_driver(bridge_driver_t *bridge) { - bridges.emplace_back(bridge); - } - void add_bridge_driver(FpgaModel *bridge) { - fpga_models.emplace_back(bridge); - } - void add_bridge_driver(peek_poke_t *bridge) { peek_poke.reset(bridge); } - private: - // Simulation interface. - simif_t *simif; - // Peek-poke bridge. - std::unique_ptr peek_poke; - // Memory mapped bridges bound to software models - std::vector> bridges; - // FPGA-hosted models with programmable registers & instrumentation - std::vector> fpga_models; - // profile interval: # of cycles to advance before profiling instrumentation // registers in models uint64_t profile_interval = -1; @@ -49,8 +31,8 @@ class fasedtests_top_t : public systematic_scheduler_t, public simulation_t { }; fasedtests_top_t::fasedtests_top_t(const std::vector &args, - simif_t *simif) - : simulation_t(*simif, args), simif(simif) { + simif_t &sim) + : simulation_t(sim, args) { max_cycles = -1; profile_interval = max_cycles; @@ -62,25 +44,32 @@ fasedtests_top_t::fasedtests_top_t(const std::vector &args, profile_interval = atoi(arg.c_str() + 18); } } + + auto *model = sim.get_registry().get_all_models()[0]; + sim.get_registry().add_widget( + new test_harness_bridge_t(sim, + sim.get_registry().get_widget(), + model->get_addr_map(), + args)); } bool fasedtests_top_t::simulation_complete() { bool is_complete = false; - for (auto &e : bridges) { + for (auto &e : sim.get_registry().get_all_bridges()) { is_complete |= e->terminate(); } return is_complete; } uint64_t fasedtests_top_t::profile_models() { - for (auto &mod : fpga_models) { + for (auto &mod : sim.get_registry().get_all_models()) { mod->profile(); } return profile_interval; } int fasedtests_top_t::exit_code() { - for (auto &e : bridges) { + for (auto &e : sim.get_registry().get_all_bridges()) { if (e->exit_code()) return e->exit_code(); } @@ -88,31 +77,25 @@ int fasedtests_top_t::exit_code() { } void fasedtests_top_t::simulation_init() { -#include "core/constructor.h" // Add functions you'd like to periodically invoke on a paused simulator here. if (profile_interval != -1) { register_task([this]() { return this->profile_models(); }, 0); } - // Test harness. - add_bridge_driver(new test_harness_bridge_t( - *simif, *peek_poke, fpga_models[0]->get_addr_map(), args)); - - for (auto &e : fpga_models) { - e->init(); + for (auto *bridge : sim.get_registry().get_all_bridges()) { + bridge->init(); } - - for (auto &e : bridges) { - e->init(); + for (auto *model : sim.get_registry().get_all_models()) { + model->init(); } } int fasedtests_top_t::simulation_run() { while (!simulation_complete() && !finished_scheduled_tasks()) { run_scheduled_tasks(); - simif->take_steps(get_largest_stepsize(), false); - while (!simif->done() && !simulation_complete()) { - for (auto &e : bridges) + sim.take_steps(get_largest_stepsize(), false); + while (!sim.done() && !simulation_complete()) { + for (auto &e : sim.get_registry().get_all_bridges()) e->tick(); } } @@ -121,16 +104,15 @@ int fasedtests_top_t::simulation_run() { } void fasedtests_top_t::simulation_finish() { - for (auto &e : fpga_models) { - e->finish(); + for (auto *bridge : sim.get_registry().get_all_bridges()) { + bridge->finish(); } - - for (auto &e : bridges) { - e->finish(); + for (auto *model : sim.get_registry().get_all_models()) { + model->finish(); } } std::unique_ptr -create_simulation(const std::vector &args, simif_t *simif) { - return std::make_unique(args, simif); +create_simulation(const std::vector &args, simif_t &sim) { + return std::make_unique(args, sim); } diff --git a/sim/src/main/cc/firesim/firesim_top.cc b/sim/src/main/cc/firesim/firesim_top.cc index c8a7c33cf1..218725261c 100644 --- a/sim/src/main/cc/firesim/firesim_top.cc +++ b/sim/src/main/cc/firesim/firesim_top.cc @@ -1,21 +1,7 @@ // See LICENSE for license details -#include "bridges/autocounter.h" -#include "bridges/blockdev.h" -#include "bridges/dromajo.h" #include "bridges/fased_memory_timing_model.h" -#include "bridges/fpga_model.h" -#include "bridges/groundtest.h" #include "bridges/heartbeat.h" -#include "bridges/peek_poke.h" -#include "bridges/plusargs.h" -#include "bridges/reset_pulse.h" -#include "bridges/serial.h" -#include "bridges/simplenic.h" -#include "bridges/synthesized_assertions.h" -#include "bridges/synthesized_prints.h" -#include "bridges/tracerv.h" -#include "bridges/uart.h" #include "core/bridge_driver.h" #include "core/simif.h" #include "core/simulation.h" @@ -23,32 +9,14 @@ class firesim_top_t : public systematic_scheduler_t, public simulation_t { public: - firesim_top_t(const std::vector &args, simif_t *simif); + firesim_top_t(const std::vector &args, simif_t &sim); ~firesim_top_t() {} void simulation_init(); void simulation_finish(); int simulation_run(); -protected: - void add_bridge_driver(peek_poke_t *peek_poke) { delete peek_poke; } - void add_bridge_driver(bridge_driver_t *bridge) { - bridges.emplace_back(bridge); - } - void add_bridge_driver(FpgaModel *bridge) { - fpga_models.emplace_back(bridge); - } - private: - // Simulator interface. - simif_t *simif; - - // A registry of all bridge drivers in the simulator - std::vector> bridges; - // FPGA-hosted models with programmable registers & instrumentation - // (i.e., bridges_drivers whose tick() is a nop) - std::vector> fpga_models; - // profile interval: # of cycles to advance before profiling instrumentation // registers in models uint64_t profile_interval = -1; @@ -60,9 +28,9 @@ class firesim_top_t : public systematic_scheduler_t, public simulation_t { int exit_code(); }; -firesim_top_t::firesim_top_t(const std::vector &args, - simif_t *simif) - : simulation_t(*simif, args), simif(simif) { +firesim_top_t::firesim_top_t(const std::vector &args, simif_t &sim) + : simulation_t(sim, args) { + max_cycles = -1; profile_interval = max_cycles; @@ -74,25 +42,27 @@ firesim_top_t::firesim_top_t(const std::vector &args, profile_interval = atoi(arg.c_str() + 18); } } + + sim.get_registry().add_widget(new heartbeat_t(sim, args)); } bool firesim_top_t::simulation_complete() { bool is_complete = false; - for (auto &e : bridges) { + for (auto &e : sim.get_registry().get_all_bridges()) { is_complete |= e->terminate(); } return is_complete; } uint64_t firesim_top_t::profile_models() { - for (auto &mod : fpga_models) { + for (auto &mod : sim.get_registry().get_all_models()) { mod->profile(); } return profile_interval; } int firesim_top_t::exit_code() { - for (auto &e : bridges) { + for (auto &e : sim.get_registry().get_all_bridges()) { if (e->exit_code()) return e->exit_code(); } @@ -100,39 +70,25 @@ int firesim_top_t::exit_code() { } void firesim_top_t::simulation_init() { - add_bridge_driver(new heartbeat_t(*simif, args)); - - // DOC include start: Bridge Driver Registration - // Here we instantiate our driver once for each bridge in the target - // Golden Gate emits a __PRESENT macro for each - // instance which you may use to conditionally instantiate your driver. - // This file can be included in the setup method of any top-level to pass - // an instance of each driver to the `add_bridge_driver` method. Drivers can - // be distinguished by overloading the method with the appropriate type. -#include "core/constructor.h" - // DOC include end: Bridge Driver Registration - // Add functions you'd like to periodically invoke on a paused simulator here. if (profile_interval != -1) { register_task([this]() { return this->profile_models(); }, 0); } - for (auto &e : fpga_models) { - e->init(); + for (auto *bridge : sim.get_registry().get_all_bridges()) { + bridge->init(); } - - for (auto &e : bridges) { - e->init(); + for (auto *model : sim.get_registry().get_all_models()) { + model->init(); } } int firesim_top_t::simulation_run() { - while (!simulation_complete() && !finished_scheduled_tasks()) { run_scheduled_tasks(); - simif->take_steps(get_largest_stepsize(), false); - while (!simif->done() && !simulation_complete()) { - for (auto &e : bridges) + sim.take_steps(get_largest_stepsize(), false); + while (!sim.done() && !simulation_complete()) { + for (auto &e : sim.get_registry().get_all_bridges()) e->tick(); } } @@ -141,16 +97,15 @@ int firesim_top_t::simulation_run() { } void firesim_top_t::simulation_finish() { - for (auto &e : fpga_models) { - e->finish(); + for (auto *bridge : sim.get_registry().get_all_bridges()) { + bridge->finish(); } - - for (auto &e : bridges) { - e->finish(); + for (auto *model : sim.get_registry().get_all_models()) { + model->finish(); } } std::unique_ptr -create_simulation(const std::vector &args, simif_t *simif) { - return std::make_unique(args, simif); +create_simulation(const std::vector &args, simif_t &sim) { + return std::make_unique(args, sim); } diff --git a/sim/src/main/cc/midasexamples/AssertTest.h b/sim/src/main/cc/midasexamples/AssertTest.h index 4161391233..19e7e5d708 100644 --- a/sim/src/main/cc/midasexamples/AssertTest.h +++ b/sim/src/main/cc/midasexamples/AssertTest.h @@ -12,14 +12,12 @@ class AssertTest : public TestHarness { ~AssertTest() override = default; - std::vector> assert_endpoints; - void add_bridge_driver(synthesized_assertions_t *bridge) override { - assert_endpoints.emplace_back(bridge); - } + std::vector assert_endpoints = + get_bridges(); void simulation_init() override { TestHarness::simulation_init(); - for (auto &assert_endpoint : assert_endpoints) { + for (auto *assert_endpoint : assert_endpoints) { assert_endpoint->init(); } } diff --git a/sim/src/main/cc/midasexamples/AutoCounterTest.h b/sim/src/main/cc/midasexamples/AutoCounterTest.h index 93f314e68c..30e327af97 100644 --- a/sim/src/main/cc/midasexamples/AutoCounterTest.h +++ b/sim/src/main/cc/midasexamples/AutoCounterTest.h @@ -4,6 +4,7 @@ #define MIDASEXAMPLES_AUTOCOUNTERMODULE_H #include "TestHarness.h" +#include "bridges/autocounter.h" class AutoCounterTest : public TestHarness { public: @@ -11,14 +12,19 @@ class AutoCounterTest : public TestHarness { ~AutoCounterTest() override = default; - std::vector> autocounter_endpoints; - void add_bridge_driver(autocounter_t *bridge) override { - autocounter_endpoints.emplace_back(bridge); + const std::vector autocounter_endpoints = + get_bridges(); + + void simulation_init() override { + assert(!autocounter_endpoints.empty() && "missing counters"); + for (auto &autocounter_endpoint : autocounter_endpoints) { + autocounter_endpoint->init(); + } } void run_and_collect(int cycles) { step(cycles, false); - while (!simif->done()) { + while (!sim.done()) { for (auto &autocounter_endpoint : autocounter_endpoints) { autocounter_endpoint->tick(); } diff --git a/sim/src/main/cc/midasexamples/PassthroughModelTest.h b/sim/src/main/cc/midasexamples/PassthroughModelTest.h index 2241b3cc44..65f497933d 100644 --- a/sim/src/main/cc/midasexamples/PassthroughModelTest.h +++ b/sim/src/main/cc/midasexamples/PassthroughModelTest.h @@ -11,8 +11,6 @@ class PassthroughModelDriver : public TestHarness { public: using TestHarness::TestHarness; - void add_bridge_driver(synthesized_assertions_t *bridge) override {} - int latency = 1; int length = 1 << 16; diff --git a/sim/src/main/cc/midasexamples/PrintfTest.h b/sim/src/main/cc/midasexamples/PrintfTest.h index dc90eb0c0a..b3c3f5f5d3 100644 --- a/sim/src/main/cc/midasexamples/PrintfTest.h +++ b/sim/src/main/cc/midasexamples/PrintfTest.h @@ -1,24 +1,29 @@ // See LICENSE for license details. -#ifndef MIDASEXAMPLES_PRINTFMODULE_H -#define MIDASEXAMPLES_PRINTFMODULE_H - -#include +#ifndef MIDASEXAMPLES_PRINTTEST_H +#define MIDASEXAMPLES_PRINTTEST_H #include "TestHarness.h" +#include "bridges/synthesized_prints.h" class PrintTest : public TestHarness { public: using TestHarness::TestHarness; - std::vector> print_endpoints; - void add_bridge_driver(synthesized_prints_t *bridge) override { - print_endpoints.emplace_back(bridge); + ~PrintTest() override = default; + + const std::vector print_endpoints = + get_bridges(); + + void simulation_init() override { + for (auto &print_endpoint : print_endpoints) { + print_endpoint->init(); + } } void run_and_collect_prints(int cycles) { step(cycles, false); - while (!simif->done()) { + while (!sim.done()) { for (auto &print_endpoint : print_endpoints) { print_endpoint->tick(); } @@ -29,4 +34,4 @@ class PrintTest : public TestHarness { } }; -#endif // MIDASEXAMPLES_PRINTFMODULE_H +#endif // MIDASEXAMPLES_PRINTTEST_H diff --git a/sim/src/main/cc/midasexamples/TestAssertGlobalResetCondition.cc b/sim/src/main/cc/midasexamples/TestAssertGlobalResetCondition.cc index 49890b5b6b..664ecdbf83 100644 --- a/sim/src/main/cc/midasexamples/TestAssertGlobalResetCondition.cc +++ b/sim/src/main/cc/midasexamples/TestAssertGlobalResetCondition.cc @@ -1,22 +1,15 @@ // See LICENSE for license details. -#include "TestHarness.h" +#include "AssertTest.h" -class TestAssertGlobalResetCondition final : public TestHarness { +class TestAssertGlobalResetCondition final : public AssertTest { public: - using TestHarness::TestHarness; - - std::vector> assert_endpoints; - void add_bridge_driver(synthesized_assertions_t *bridge) override { - assert_endpoints.emplace_back(bridge); - } + using AssertTest::AssertTest; void run_test() override { - for (auto &ep : assert_endpoints) - ep->init(); target_reset(2); step(40000, false); - while (!simif->done()) { + while (!sim.done()) { for (auto &ep : assert_endpoints) { ep->tick(); if (ep->terminate()) { diff --git a/sim/src/main/cc/midasexamples/TestAssertModule.cc b/sim/src/main/cc/midasexamples/TestAssertModule.cc index 8ab4a9957d..da6a883423 100644 --- a/sim/src/main/cc/midasexamples/TestAssertModule.cc +++ b/sim/src/main/cc/midasexamples/TestAssertModule.cc @@ -8,6 +8,9 @@ class TestAssertModule final : public AssertTest { using AssertTest::AssertTest; void run_test() override { + assert(assert_endpoints.size() == 1 && "expected one assert"); + auto *assert_endpoint = assert_endpoints[0]; + int assertions_thrown = 0; poke("reset", 1); poke("io_a", 0); @@ -40,8 +43,9 @@ class TestAssertModule final : public AssertTest { std::to_string(test_case)); break; } + auto &assert_endpoint = *assert_endpoints[0]; - while (!simif->done()) { + while (!sim.done()) { assert_endpoint.tick(); if (assert_endpoint.terminate()) { assert_endpoint.resume(); diff --git a/sim/src/main/cc/midasexamples/TestAssertTorture.cc b/sim/src/main/cc/midasexamples/TestAssertTorture.cc index 1e662f4202..c5ee28d65d 100644 --- a/sim/src/main/cc/midasexamples/TestAssertTorture.cc +++ b/sim/src/main/cc/midasexamples/TestAssertTorture.cc @@ -1,23 +1,15 @@ // See LICENSE for license details. -#include "TestHarness.h" +#include "AssertTest.h" -class TestAssertTorture final : public TestHarness { +class TestAssertTorture final : public AssertTest { public: - using TestHarness::TestHarness; - - std::vector> assert_endpoints; - void add_bridge_driver(synthesized_assertions_t *bridge) override { - assert_endpoints.emplace_back(bridge); - } + using AssertTest::AssertTest; void run_test() override { - for (auto &ep : assert_endpoints) - ep->init(); - target_reset(2); step(40000, false); - while (!simif->done()) { + while (!sim.done()) { for (auto &ep : assert_endpoints) { ep->tick(); if (ep->terminate()) { diff --git a/sim/src/main/cc/midasexamples/TestAutoCounter32bRollover.cc b/sim/src/main/cc/midasexamples/TestAutoCounter32bRollover.cc index c153d5a780..2bd4a06410 100644 --- a/sim/src/main/cc/midasexamples/TestAutoCounter32bRollover.cc +++ b/sim/src/main/cc/midasexamples/TestAutoCounter32bRollover.cc @@ -7,9 +7,6 @@ class TestAutoCounter32bRollover final : public AutoCounterTest { using AutoCounterTest::AutoCounterTest; void run_test() override { - for (auto &autocounter_endpoint : autocounter_endpoints) { - autocounter_endpoint->init(); - } poke("reset", 1); poke("io_a", 0); step(1); diff --git a/sim/src/main/cc/midasexamples/TestAutoCounterCoverModule.cc b/sim/src/main/cc/midasexamples/TestAutoCounterCoverModule.cc index 17497d1d20..4e0e12017b 100644 --- a/sim/src/main/cc/midasexamples/TestAutoCounterCoverModule.cc +++ b/sim/src/main/cc/midasexamples/TestAutoCounterCoverModule.cc @@ -7,9 +7,6 @@ class TestAutoCounterCoverModule : public AutoCounterTest { using AutoCounterTest::AutoCounterTest; void run_test() override { - for (auto &autocounter_endpoint : autocounter_endpoints) { - autocounter_endpoint->init(); - } poke("reset", 1); poke("io_a", 0); step(1); diff --git a/sim/src/main/cc/midasexamples/TestAutoCounterGlobalResetCondition.cc b/sim/src/main/cc/midasexamples/TestAutoCounterGlobalResetCondition.cc index dfe7d2999d..3a66547bf5 100644 --- a/sim/src/main/cc/midasexamples/TestAutoCounterGlobalResetCondition.cc +++ b/sim/src/main/cc/midasexamples/TestAutoCounterGlobalResetCondition.cc @@ -7,9 +7,6 @@ class TestAutoCounterGlobalResetCondition : public AutoCounterTest { using AutoCounterTest::AutoCounterTest; void run_test() override { - for (auto &autocounter_endpoint : autocounter_endpoints) { - autocounter_endpoint->init(); - } poke("reset", 1); step(4); poke("reset", 0); diff --git a/sim/src/main/cc/midasexamples/TestAutoCounterModule.cc b/sim/src/main/cc/midasexamples/TestAutoCounterModule.cc index 013bb3c5a6..5af0865ab8 100644 --- a/sim/src/main/cc/midasexamples/TestAutoCounterModule.cc +++ b/sim/src/main/cc/midasexamples/TestAutoCounterModule.cc @@ -7,9 +7,6 @@ class TestAutoCounterModule : public AutoCounterTest { using AutoCounterTest::AutoCounterTest; void run_test() override { - for (auto &autocounter_endpoint : autocounter_endpoints) { - autocounter_endpoint->init(); - } poke("reset", 1); poke("io_a", 0); step(1); diff --git a/sim/src/main/cc/midasexamples/TestAutoCounterPrintfModule.cc b/sim/src/main/cc/midasexamples/TestAutoCounterPrintfModule.cc index ce3a505ce6..69b14df6ca 100644 --- a/sim/src/main/cc/midasexamples/TestAutoCounterPrintfModule.cc +++ b/sim/src/main/cc/midasexamples/TestAutoCounterPrintfModule.cc @@ -7,9 +7,6 @@ class TestAutoCounterModule : public PrintTest { using PrintTest::PrintTest; void run_test() override { - for (auto &print_endpoint : print_endpoints) { - print_endpoint->init(); - } poke("reset", 1); poke("io_a", 0); step(1); diff --git a/sim/src/main/cc/midasexamples/TestGCD.cc b/sim/src/main/cc/midasexamples/TestGCD.cc index 2fd8c43578..7e8ff4d10c 100644 --- a/sim/src/main/cc/midasexamples/TestGCD.cc +++ b/sim/src/main/cc/midasexamples/TestGCD.cc @@ -6,8 +6,6 @@ class TestGCD final : public TestHarness { public: using TestHarness::TestHarness; - void add_bridge_driver(synthesized_assertions_t *bridge) override {} - void run_test() override { uint32_t a = 64, b = 48, z = 16; // test vectors target_reset(); diff --git a/sim/src/main/cc/midasexamples/TestHarness.cc b/sim/src/main/cc/midasexamples/TestHarness.cc index d0e94cc6d3..4461367846 100644 --- a/sim/src/main/cc/midasexamples/TestHarness.cc +++ b/sim/src/main/cc/midasexamples/TestHarness.cc @@ -1,4 +1,5 @@ #include +#include #include "TestHarness.h" @@ -6,8 +7,9 @@ static const char *blocking_fail = "The test environment has starved the simulator, preventing forward " "progress."; -TestHarness::TestHarness(const std::vector &args, simif_t *simif) - : simulation_t(*simif, args), simif(simif) { +TestHarness::TestHarness(const std::vector &args, simif_t &sim) + : simulation_t(sim, args), + peek_poke(sim.get_registry().get_widget()) { for (const auto &arg : args) { if (arg.find("+seed=") == 0) { random_seed = strtoll(arg.c_str() + 6, nullptr, 10); @@ -26,7 +28,7 @@ void TestHarness::step(uint32_t n, bool blocking) { if (log) { std::cerr << "* STEP " << n << " -> " << t + n << " *" << std::endl; } - simif->take_steps(n, blocking); + sim.take_steps(n, blocking); t += n; } @@ -37,11 +39,11 @@ void TestHarness::target_reset(int pulse_length) { } void TestHarness::poke(std::string_view id, uint32_t value, bool blocking) { - peek_poke->poke(id, value, blocking); + peek_poke.poke(id, value, blocking); - if (peek_poke->timeout()) { + if (peek_poke.timeout()) { if (log) { - std::cerr << "* FAIL : POKE on " << simif->get_target_name() << "." << id + std::cerr << "* FAIL : POKE on " << sim.get_target_name() << "." << id << " has timed out. " << blocking_fail << " : FAIL" << std::endl; } @@ -49,30 +51,30 @@ void TestHarness::poke(std::string_view id, uint32_t value, bool blocking) { } if (log) { - std::cerr << "* POKE " << simif->get_target_name() << "." << id << " <- 0x" + std::cerr << "* POKE " << sim.get_target_name() << "." << id << " <- 0x" << std::hex << value << " *" << std::endl; } } uint32_t TestHarness::peek(std::string_view id, bool blocking) { - uint32_t value = peek_poke->peek(id, blocking); + uint32_t value = peek_poke.peek(id, blocking); - if (peek_poke->timeout()) { + if (peek_poke.timeout()) { if (log) { - std::cerr << "* FAIL : PEEK on " << simif->get_target_name() << "." << id + std::cerr << "* FAIL : PEEK on " << sim.get_target_name() << "." << id << " has timed out. " << blocking_fail << " : FAIL" << std::endl; } throw; } - if (peek_poke->unstable()) { + if (peek_poke.unstable()) { std::cerr << "* WARNING : The following peek is on an unstable value!" << std::endl; } if (log) { - std::cerr << "* PEEK " << simif->get_target_name() << "." << id << " <- 0x" + std::cerr << "* PEEK " << sim.get_target_name() << "." << id << " <- 0x" << std::hex << value << " *" << std::endl; } return value; @@ -81,17 +83,17 @@ uint32_t TestHarness::peek(std::string_view id, bool blocking) { void TestHarness::poke(std::string_view id, mpz_t &value) { if (log) { std::unique_ptr v_str(mpz_get_str(nullptr, 16, value)); - std::cerr << "* POKE " << simif->get_target_name() << "." << id << " <- 0x" + std::cerr << "* POKE " << sim.get_target_name() << "." << id << " <- 0x" << std::hex << v_str.get() << " *" << std::endl; } - peek_poke->poke(id, value); + peek_poke.poke(id, value); } void TestHarness::peek(std::string_view id, mpz_t &value) { - peek_poke->peek(id, value); + peek_poke.peek(id, value); if (log) { std::unique_ptr v_str(mpz_get_str(nullptr, 16, value)); - std::cerr << "* PEEK " << simif->get_target_name() << "." << id << " <- 0x" + std::cerr << "* PEEK " << sim.get_target_name() << "." << id << " <- 0x" << std::hex << v_str.get() << " *" << std::endl; } } @@ -100,9 +102,9 @@ bool TestHarness::expect(std::string_view id, uint32_t expected) { uint32_t value = peek(id); bool pass = value == expected; if (log) { - std::cerr << "* EXPECT " << simif->get_target_name() << "." << id - << " -> 0x" << std::hex << value << " ?= 0x" << std::hex - << expected << " : " << (pass ? "PASS" : "FAIL") << std::endl; + std::cerr << "* EXPECT " << sim.get_target_name() << "." << id << " -> 0x" + << std::hex << value << " ?= 0x" << std::hex << expected << " : " + << (pass ? "PASS" : "FAIL") << std::endl; } return expect(pass, nullptr); } @@ -129,8 +131,8 @@ bool TestHarness::expect(std::string_view id, mpz_t &expected) { std::unique_ptr v_str(mpz_get_str(nullptr, 16, value)); std::unique_ptr e_str(mpz_get_str(nullptr, 16, expected)); - std::cerr << "* EXPECT " << simif->get_target_name() << "." << id - << " -> 0x" << v_str.get() << " ?= 0x" << e_str.get() << " : " + std::cerr << "* EXPECT " << sim.get_target_name() << "." << id << " -> 0x" + << v_str.get() << " ?= 0x" << e_str.get() << " : " << (pass ? "PASS" : "FAIL") << std::endl; } mpz_clear(value); @@ -138,7 +140,7 @@ bool TestHarness::expect(std::string_view id, mpz_t &expected) { } int TestHarness::teardown() { - std::cerr << "[" << simif->get_target_name() << "]"; + std::cerr << "[" << sim.get_target_name() << "]"; std::cerr << (pass ? "PASS" : "FAIL") << " Test"; if (!pass) { std::cerr << " at cycle " << fail_t; diff --git a/sim/src/main/cc/midasexamples/TestHarness.h b/sim/src/main/cc/midasexamples/TestHarness.h index 72d1e4411b..52ef69bd8c 100644 --- a/sim/src/main/cc/midasexamples/TestHarness.h +++ b/sim/src/main/cc/midasexamples/TestHarness.h @@ -5,11 +5,6 @@ #include "bridges/autocounter.h" #include "bridges/peek_poke.h" -#include "bridges/plusargs.h" -#include "bridges/reset_pulse.h" -#include "bridges/synthesized_assertions.h" -#include "bridges/synthesized_prints.h" -#include "bridges/termination.h" #include "core/bridge_driver.h" #include "core/simif.h" #include "core/simulation.h" @@ -25,35 +20,15 @@ */ class TestHarness : public simulation_t { public: - TestHarness(const std::vector &args, simif_t *simif); + TestHarness(const std::vector &args, simif_t &sim); ~TestHarness() override; - // Bridge creation callbacks. -#define BRIDGE_HANDLER(ty, name) \ - virtual void add_bridge_driver(ty *bridge) { \ - fprintf(stderr, "Cannot handle " name "\n"); \ - abort(); \ - } - - BRIDGE_HANDLER(autocounter_t, "Auto Counter bridge"); - BRIDGE_HANDLER(synthesized_assertions_t, "Synthesized Assert bridge"); - BRIDGE_HANDLER(synthesized_prints_t, "Synthesized Print bridge"); - BRIDGE_HANDLER(reset_pulse_t, "Reset Pulse bridge"); - BRIDGE_HANDLER(plusargs_t, "PlusArgs bridge"); - BRIDGE_HANDLER(termination_t, "Termination bridge"); - - void add_bridge_driver(peek_poke_t *bridge) { peek_poke.reset(bridge); } - /** * Test entry point to override. */ virtual void run_test() = 0; - void simulation_init() override { -#include "core/constructor.h" - } - int simulation_run() override { run_test(); return teardown(); @@ -68,7 +43,7 @@ class TestHarness : public simulation_t { uint32_t peek(std::string_view id, bool blocking = true); void peek(std::string_view id, mpz_t &value); uint32_t sample_value(std::string_view id) { - return peek_poke->sample_value(id); + return peek_poke.sample_value(id); } /** @@ -83,16 +58,29 @@ class TestHarness : public simulation_t { int teardown(); + /** + * Convenience method to get all bridges from the registry. + */ + template + std::vector get_bridges() { + return sim.get_registry().get_bridges(); + } + + /** + * Convenience method to get a single bridge from the registry. + */ + template + T &get_bridge() { + return sim.get_registry().get_widget(); + } + protected: - simif_t *simif; + peek_poke_t &peek_poke; /// Random number generator for tests, using a fixed default seed. uint64_t random_seed = 0; std::mt19937_64 random; -private: - std::unique_ptr peek_poke; - bool pass = true; bool log = true; @@ -102,7 +90,7 @@ class TestHarness : public simulation_t { #define TEST_MAIN(CLASS_NAME) \ std::unique_ptr create_simulation( \ - const std::vector &args, simif_t *simif) { \ - return std::make_unique(args, simif); \ + const std::vector &args, simif_t &sim) { \ + return std::make_unique(args, sim); \ } #endif // MIDAEXAMPLES_TESTHARNESS_H diff --git a/sim/src/main/cc/midasexamples/TestMultiSRAM.cc b/sim/src/main/cc/midasexamples/TestMultiSRAM.cc index c24857c1d1..4047c22eda 100644 --- a/sim/src/main/cc/midasexamples/TestMultiSRAM.cc +++ b/sim/src/main/cc/midasexamples/TestMultiSRAM.cc @@ -2,7 +2,7 @@ class TestMultiSRAM final : public MultiRegfileTest { public: - TestMultiSRAM(const std::vector &args, simif_t *simif) + TestMultiSRAM(const std::vector &args, simif_t &simif) : MultiRegfileTest(args, simif) { write_first = false; } diff --git a/sim/src/main/cc/midasexamples/TestMulticlockAssertModule.cc b/sim/src/main/cc/midasexamples/TestMulticlockAssertModule.cc index a8fac58ffb..ab2a5a57ed 100644 --- a/sim/src/main/cc/midasexamples/TestMulticlockAssertModule.cc +++ b/sim/src/main/cc/midasexamples/TestMulticlockAssertModule.cc @@ -8,14 +8,11 @@ class TestMulticlockAssertModule final : public TestHarness { public: using TestHarness::TestHarness; - std::vector> assert_endpoints; - void add_bridge_driver(synthesized_assertions_t *bridge) override { - assert_endpoints.emplace_back(bridge); - } - void run_test() override { int assertions_thrown = 0; + const auto &assert_endpoints = get_bridges(); + for (auto &ep : assert_endpoints) ep->init(); @@ -24,8 +21,9 @@ class TestMulticlockAssertModule final : public TestHarness { poke("fullrate_cycle", 186); poke("halfrate_pulseLength", 2); poke("halfrate_cycle", 129); + step(256, false); - while (!simif->done()) { + while (!sim.done()) { for (auto &ep : assert_endpoints) { ep->tick(); if (ep->terminate()) { diff --git a/sim/src/main/cc/midasexamples/TestNarrowPrintfModule.cc b/sim/src/main/cc/midasexamples/TestNarrowPrintfModule.cc index d31ed656c9..a9744d8247 100644 --- a/sim/src/main/cc/midasexamples/TestNarrowPrintfModule.cc +++ b/sim/src/main/cc/midasexamples/TestNarrowPrintfModule.cc @@ -7,9 +7,6 @@ class TestNarrowPrintfModule : public PrintTest { using PrintTest::PrintTest; void run_test() override { - for (auto &print_endpoint : print_endpoints) { - print_endpoint->init(); - } poke("reset", 1); poke("io_enable", 0); step(1); @@ -21,7 +18,7 @@ class TestNarrowPrintfModule : public PrintTest { step(256); poke("io_enable", 1); run_and_collect_prints(256); - }; + } }; TEST_MAIN(TestNarrowPrintfModule) diff --git a/sim/src/main/cc/midasexamples/TestPlusArgsModule.cc b/sim/src/main/cc/midasexamples/TestPlusArgsModule.cc index b0a9b08ad6..5b7b135808 100644 --- a/sim/src/main/cc/midasexamples/TestPlusArgsModule.cc +++ b/sim/src/main/cc/midasexamples/TestPlusArgsModule.cc @@ -1,11 +1,12 @@ // See LICENSE for license details. -#include "TestHarness.h" - #include #include #include +#include "TestHarness.h" +#include "bridges/plusargs.h" + /** * @brief PlusArgs Bridge Driver Test * @@ -35,19 +36,15 @@ class TestPlusArgsModule : public TestHarness { } public: - std::unique_ptr plusargsinator; - void add_bridge_driver(plusargs_t *bridge) override { - assert(!plusargsinator && "multiple bridges registered"); - plusargsinator.reset(bridge); - } + plusargs_t &plusargsinator; /** * Constructor. * * @param [in] args The argument list from main */ - TestPlusArgsModule(const std::vector &args, simif_t *simif) - : TestHarness(args, simif) { + TestPlusArgsModule(const std::vector &args, simif_t &simif) + : TestHarness(args, simif), plusargsinator(get_bridge()) { parse_key(args); } @@ -113,7 +110,7 @@ class TestPlusArgsModule : public TestHarness { std::cout << "No test key found, will not assert\n"; } - plusargsinator->init(); + plusargsinator.init(); target_reset(); for (int i = 0; i < 8; i++) { diff --git a/sim/src/main/cc/midasexamples/TestPrintfCycleBounds.cc b/sim/src/main/cc/midasexamples/TestPrintfCycleBounds.cc index 3cf3cdebce..8d88ec93c3 100644 --- a/sim/src/main/cc/midasexamples/TestPrintfCycleBounds.cc +++ b/sim/src/main/cc/midasexamples/TestPrintfCycleBounds.cc @@ -7,9 +7,6 @@ class TestPrintfCycleBounds final : public PrintTest { using PrintTest::PrintTest; void run_test() override { - for (auto &print_endpoint : print_endpoints) { - print_endpoint->init(); - } poke("reset", 1); poke("io_a", 0); poke("io_b", 0); diff --git a/sim/src/main/cc/midasexamples/TestPrintfModule.cc b/sim/src/main/cc/midasexamples/TestPrintfModule.cc index 314e1ed1c0..0df5aa9263 100644 --- a/sim/src/main/cc/midasexamples/TestPrintfModule.cc +++ b/sim/src/main/cc/midasexamples/TestPrintfModule.cc @@ -7,9 +7,6 @@ class TestPrintModule final : public PrintTest { using PrintTest::PrintTest; void run_test() override { - for (auto &print_endpoint : print_endpoints) { - print_endpoint->init(); - } poke("reset", 1); poke("io_a", 0); poke("io_b", 0); diff --git a/sim/src/main/cc/midasexamples/TestResetPulseBridgeTest.cc b/sim/src/main/cc/midasexamples/TestResetPulseBridgeTest.cc index c063e50b82..f97f7f7273 100644 --- a/sim/src/main/cc/midasexamples/TestResetPulseBridgeTest.cc +++ b/sim/src/main/cc/midasexamples/TestResetPulseBridgeTest.cc @@ -1,24 +1,21 @@ // See LICENSE for license details. -#include - #include "TestHarness.h" +#include "bridges/reset_pulse.h" + +#include class TestResetPulseBridge final : public TestHarness { public: using TestHarness::TestHarness; - std::unique_ptr rb; - void add_bridge_driver(reset_pulse_t *bridge) override { - assert(!rb && "multiple bridges registered"); - rb.reset(bridge); - } + reset_pulse_t &rb = get_bridge(); // Since we rely on an assertion firing to catch a failure, just run a // similation that is at least the length of the expected pulse. void run_test() override { - rb->init(); - step(2 * rb->get_max_pulse_length()); + rb.init(); + step(2 * rb.get_max_pulse_length()); } }; diff --git a/sim/src/main/cc/midasexamples/TestTerminationModule.cc b/sim/src/main/cc/midasexamples/TestTerminationModule.cc index 7f6bca47a3..9c7bdc1990 100644 --- a/sim/src/main/cc/midasexamples/TestTerminationModule.cc +++ b/sim/src/main/cc/midasexamples/TestTerminationModule.cc @@ -1,19 +1,16 @@ // See LICENSE for license details. #include "TestHarness.h" +#include "bridges/termination.h" +#include #include -#include class TestTerminationModule final : public TestHarness { public: using TestHarness::TestHarness; - std::unique_ptr terminator; - void add_bridge_driver(termination_t *bridge) override { - assert(!terminator && "multiple bridges registered"); - terminator.reset(bridge); - } + termination_t &terminator = get_bridge(); void run_test() override { poke("reset", 1); @@ -43,13 +40,13 @@ class TestTerminationModule final : public TestHarness { msgid = 2; } step(lv_validinCycle + 2, false); - while (!terminator->terminate()) { - terminator->tick(); + while (!terminator.terminate()) { + terminator.tick(); } - int str_match = terminator->exit_message() == failure_msg_list[msgid]; - expect(terminator->cycle_count() == (lv_validinCycle + reset_length), + int str_match = terminator.exit_message() == failure_msg_list[msgid]; + expect(terminator.cycle_count() == (lv_validinCycle + reset_length), "Code Exits at precise time"); - expect(terminator->exit_code() == failure_cond_list[msgid], + expect(terminator.exit_code() == failure_cond_list[msgid], "Error Code Verified"); expect(str_match, "Error Message Verified"); }; diff --git a/sim/src/main/cc/midasexamples/TestTerminationModuleAssert.cc b/sim/src/main/cc/midasexamples/TestTerminationModuleAssert.cc index fd1bf97956..a1dfa246aa 100644 --- a/sim/src/main/cc/midasexamples/TestTerminationModuleAssert.cc +++ b/sim/src/main/cc/midasexamples/TestTerminationModuleAssert.cc @@ -1,16 +1,13 @@ // See LICENSE for license details. #include "TestHarness.h" +#include "bridges/termination.h" class TestTerminationModuleAssert final : public TestHarness { public: using TestHarness::TestHarness; - std::unique_ptr terminator; - void add_bridge_driver(termination_t *bridge) override { - assert(!terminator && "multiple bridges registered"); - terminator.reset(bridge); - } + termination_t &terminator = get_bridge(); int expected_cycle_at_bridge = 0; @@ -18,9 +15,9 @@ class TestTerminationModuleAssert final : public TestHarness { void step_assume_continue(int count) { step(count, false); expected_cycle_at_bridge += count; - while (!simif->done()) { - terminator->tick(); - assert(!terminator->terminate() && "Unexpected termination signaled."); + while (!sim.done()) { + terminator.tick(); + assert(!terminator.terminate() && "Unexpected termination signaled."); } } @@ -30,9 +27,9 @@ class TestTerminationModuleAssert final : public TestHarness { // Call this repeated to give the sim time to have a poke propagate to the // bridge for (int i = 0; i < tick_attempts; i++) { - terminator->tick(); + terminator.tick(); } - expect(terminator->terminate(), + expect(terminator.terminate(), "Termination bridge correctly calls for termination."); } @@ -58,9 +55,9 @@ class TestTerminationModuleAssert final : public TestHarness { poke("io_shouldBeTrue", 0); step_once_and_wait_on_terminate(); - expect(terminator->cycle_count() == expected_cycle_at_bridge, + expect(terminator.cycle_count() == expected_cycle_at_bridge, "Termination bridge provides correct exit cycle"); - expect(terminator->exit_code() == 1, + expect(terminator.exit_code() == 1, "Termination bridge returns non-zero when used in assert mode"); }; }; diff --git a/sim/src/main/cc/midasexamples/TestTriggerPredicatedPrintf.cc b/sim/src/main/cc/midasexamples/TestTriggerPredicatedPrintf.cc index 561c674a6f..afce698b3a 100644 --- a/sim/src/main/cc/midasexamples/TestTriggerPredicatedPrintf.cc +++ b/sim/src/main/cc/midasexamples/TestTriggerPredicatedPrintf.cc @@ -6,12 +6,7 @@ class TestTriggerPredicatedPrintf final : public PrintTest { public: using PrintTest::PrintTest; - void run_test() override { - for (auto &print_endpoint : print_endpoints) { - print_endpoint->init(); - } - run_and_collect_prints(16000); - }; + void run_test() override { run_and_collect_prints(16000); }; }; TEST_MAIN(TestTriggerPredicatedPrintf) diff --git a/sim/src/main/cc/midasexamples/TestTriggerWiringModule.cc b/sim/src/main/cc/midasexamples/TestTriggerWiringModule.cc index 810fbf1a76..330e40869f 100644 --- a/sim/src/main/cc/midasexamples/TestTriggerWiringModule.cc +++ b/sim/src/main/cc/midasexamples/TestTriggerWiringModule.cc @@ -1,15 +1,14 @@ // See LICENSE for license details. #include "TestHarness.h" +#include "bridges/synthesized_assertions.h" class TestTriggerWiringModule final : public TestHarness { public: using TestHarness::TestHarness; - std::vector> assert_endpoints; - void add_bridge_driver(synthesized_assertions_t *bridge) override { - assert_endpoints.emplace_back(bridge); - } + const std::vector assert_endpoints = + get_bridges(); bool simulation_complete() { bool is_complete = false; @@ -37,7 +36,7 @@ class TestTriggerWiringModule final : public TestHarness { step(1); poke("reset", 0); step(10000, false); - while (!simif->done() && !simulation_complete()) { + while (!sim.done() && !simulation_complete()) { for (auto &ep : assert_endpoints) { ep->tick(); }