From 1a432349709111e92a2d38a9dc6ed94d0c5dd1e7 Mon Sep 17 00:00:00 2001 From: zhengyang Date: Tue, 10 Jun 2025 20:04:30 +0800 Subject: [PATCH] [BACKEND] Lowering i1 ptr to the PtrDialect --- third_party/aipu/backend/compiler.py | 1 + third_party/aipu/triton_aipu.cc | 1 + 2 files changed, 2 insertions(+) diff --git a/third_party/aipu/backend/compiler.py b/third_party/aipu/backend/compiler.py index f3554128a..28c28d17f 100644 --- a/third_party/aipu/backend/compiler.py +++ b/third_party/aipu/backend/compiler.py @@ -100,6 +100,7 @@ def make_linalg(mod, metadata, opt): pm.enable_debug() # add pass here aipu.passes.convert.add_triton_to_linalg_pipeline(pm) + aipu.passes.convert.add_triton_to_ptr(pm) pm.run(mod) return mod diff --git a/third_party/aipu/triton_aipu.cc b/third_party/aipu/triton_aipu.cc index b617232df..c11e3400a 100644 --- a/third_party/aipu/triton_aipu.cc +++ b/third_party/aipu/triton_aipu.cc @@ -44,6 +44,7 @@ void init_triton_aipu_passes_convert(py::module &&m) { ADD_PASS_WRAPPER_0("add_linalg_to_affine_loops", createConvertLinalgToAffineLoopsPass); ADD_PASS_WRAPPER_0("add_lower_affine", createLowerAffinePass); + ADD_PASS_WRAPPER_0("add_triton_to_ptr", triton::createTritonToPtrPass); m.def("add_affine_vectorize", [](mlir::PassManager &pm, int64_t vecsize) { affine::AffineVectorizeOptions vectorize_options;