diff --git a/CMakeLists.txt b/CMakeLists.txt index 8cd9d053c63bc..46d5282d8a7e5 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -975,11 +975,8 @@ if (NOT LLVM_INSTALL_TOOLCHAIN_ONLY) set_target_properties(llvm-headers PROPERTIES FOLDER "Misc") if (NOT CMAKE_CONFIGURATION_TYPES) - add_custom_target(install-llvm-headers - DEPENDS llvm-headers - COMMAND "${CMAKE_COMMAND}" - -DCMAKE_INSTALL_COMPONENT=llvm-headers - -P "${CMAKE_BINARY_DIR}/cmake_install.cmake") + add_llvm_install_targets(install-llvm-headers + COMPONENT llvm-headers) endif() endif() diff --git a/cmake/modules/AddLLVM.cmake b/cmake/modules/AddLLVM.cmake index 908e7ee51ca8f..26da2d13eed20 100644 --- a/cmake/modules/AddLLVM.cmake +++ b/cmake/modules/AddLLVM.cmake @@ -569,6 +569,32 @@ function(llvm_add_library name) endif() endfunction() +function(add_llvm_install_targets target) + cmake_parse_arguments(ARG "" "COMPONENT;PREFIX" "DEPENDS" ${ARGN}) + if(ARG_COMPONENT) + set(component_option -DCMAKE_INSTALL_COMPONENT="${ARG_COMPONENT}") + endif() + if(ARG_PREFIX) + set(prefix_option -DCMAKE_INSTALL_PREFIX="${ARG_PREFIX}") + endif() + + add_custom_target(${target} + DEPENDS ${ARG_DEPENDS} + COMMAND "${CMAKE_COMMAND}" + ${component_option} + ${prefix_option} + -P "${CMAKE_BINARY_DIR}/cmake_install.cmake" + USES_TERMINAL) + add_custom_target(${target}-stripped + DEPENDS ${ARG_DEPENDS} + COMMAND "${CMAKE_COMMAND}" + ${component_option} + ${prefix_option} + -DCMAKE_INSTALL_DO_STRIP=1 + -P "${CMAKE_BINARY_DIR}/cmake_install.cmake" + USES_TERMINAL) +endfunction() + macro(add_llvm_library name) cmake_parse_arguments(ARG "SHARED;BUILDTREE_ONLY" @@ -619,11 +645,9 @@ macro(add_llvm_library name) COMPONENT ${name}) if (NOT CMAKE_CONFIGURATION_TYPES) - add_custom_target(install-${name} - DEPENDS ${name} - COMMAND "${CMAKE_COMMAND}" - -DCMAKE_INSTALL_COMPONENT=${name} - -P "${CMAKE_BINARY_DIR}/cmake_install.cmake") + add_llvm_install_targets(install-${name} + DEPENDS ${name} + COMPONENT ${name}) endif() endif() set_property(GLOBAL APPEND PROPERTY LLVM_EXPORTS ${name}) @@ -849,11 +873,9 @@ macro(add_llvm_tool name) COMPONENT ${name}) if (NOT CMAKE_CONFIGURATION_TYPES) - add_custom_target(install-${name} - DEPENDS ${name} - COMMAND "${CMAKE_COMMAND}" - -DCMAKE_INSTALL_COMPONENT=${name} - -P "${CMAKE_BINARY_DIR}/cmake_install.cmake") + add_llvm_install_targets(install-${name} + DEPENDS ${name} + COMPONENT ${name}) endif() endif() endif() @@ -889,11 +911,9 @@ macro(add_llvm_utility name) RUNTIME DESTINATION ${LLVM_UTILS_INSTALL_DIR} COMPONENT ${name}) if (NOT CMAKE_CONFIGURATION_TYPES) - add_custom_target(install-${name} - DEPENDS ${name} - COMMAND "${CMAKE_COMMAND}" - -DCMAKE_INSTALL_COMPONENT=${name} - -P "${CMAKE_BINARY_DIR}/cmake_install.cmake") + add_llvm_install_targets(install-${name} + DEPENDS ${name} + COMPONENT ${name}) endif() endif() endmacro(add_llvm_utility name) @@ -1400,11 +1420,9 @@ function(llvm_install_library_symlink name dest type) COMPONENT ${component}) if (NOT CMAKE_CONFIGURATION_TYPES AND NOT ARG_ALWAYS_GENERATE) - add_custom_target(install-${name} - DEPENDS ${name} ${dest} install-${dest} - COMMAND "${CMAKE_COMMAND}" - -DCMAKE_INSTALL_COMPONENT=${name} - -P "${CMAKE_BINARY_DIR}/cmake_install.cmake") + add_llvm_install_targets(install-${name} + DEPENDS ${name} ${dest} install-${dest} + COMPONENT ${name}) endif() endfunction() @@ -1435,11 +1453,9 @@ function(llvm_install_symlink name dest) COMPONENT ${component}) if (NOT CMAKE_CONFIGURATION_TYPES AND NOT ARG_ALWAYS_GENERATE) - add_custom_target(install-${name} - DEPENDS ${name} ${dest} install-${dest} - COMMAND "${CMAKE_COMMAND}" - -DCMAKE_INSTALL_COMPONENT=${name} - -P "${CMAKE_BINARY_DIR}/cmake_install.cmake") + add_llvm_install_targets(install-${name} + DEPENDS ${name} ${dest} install-${dest} + COMPONENT ${name}) endif() endfunction() diff --git a/cmake/modules/AddSphinxTarget.cmake b/cmake/modules/AddSphinxTarget.cmake index 4540c5c36c8e2..22e3dcb776aa2 100644 --- a/cmake/modules/AddSphinxTarget.cmake +++ b/cmake/modules/AddSphinxTarget.cmake @@ -19,7 +19,7 @@ endif() # ``project`` should be the project name function (add_sphinx_target builder project) set(SPHINX_BUILD_DIR "${CMAKE_CURRENT_BINARY_DIR}/${builder}") - set(SPHINX_DOC_TREE_DIR "${CMAKE_CURRENT_BINARY_DIR}/_doctrees-${builder}") + set(SPHINX_DOC_TREE_DIR "${CMAKE_CURRENT_BINARY_DIR}/_doctrees-${project}-${builder}") set(SPHINX_TARGET_NAME docs-${project}-${builder}) if (SPHINX_WARNINGS_AS_ERRORS) diff --git a/cmake/modules/CMakeLists.txt b/cmake/modules/CMakeLists.txt index ac4b0b7c03047..6074e83585947 100644 --- a/cmake/modules/CMakeLists.txt +++ b/cmake/modules/CMakeLists.txt @@ -129,9 +129,7 @@ if (NOT LLVM_INSTALL_TOOLCHAIN_ONLY) if (NOT CMAKE_CONFIGURATION_TYPES) # Add a dummy target so this can be used with LLVM_DISTRIBUTION_COMPONENTS add_custom_target(cmake-exports) - add_custom_target(install-cmake-exports - COMMAND "${CMAKE_COMMAND}" - -DCMAKE_INSTALL_COMPONENT=cmake-exports - -P "${CMAKE_BINARY_DIR}/cmake_install.cmake") + add_llvm_install_targets(install-cmake-exports + COMPONENT cmake-exports) endif() endif() diff --git a/cmake/modules/CheckAtomic.cmake b/cmake/modules/CheckAtomic.cmake index dcf021b8fddaf..866eed08936d9 100644 --- a/cmake/modules/CheckAtomic.cmake +++ b/cmake/modules/CheckAtomic.cmake @@ -1,6 +1,7 @@ # atomic builtins are required for threading support. INCLUDE(CheckCXXSourceCompiles) +INCLUDE(CheckLibraryExists) # Sometimes linking against libatomic is required for atomic ops, if # the platform doesn't support lock-free atomics. diff --git a/cmake/modules/CrossCompile.cmake b/cmake/modules/CrossCompile.cmake index 8de7c2aab4f37..d42d92530bdd7 100644 --- a/cmake/modules/CrossCompile.cmake +++ b/cmake/modules/CrossCompile.cmake @@ -12,6 +12,17 @@ function(llvm_create_cross_target_internal target_name toolchain buildtype) CACHE STRING "Toolchain file for ${target_name}") endif() + if (buildtype) + set(build_type_flags "-DCMAKE_BUILD_TYPE=${buildtype}") + endif() + if (LLVM_USE_LINKER AND NOT CMAKE_CROSSCOMPILING) + set(linker_flag "-DLLVM_USE_LINKER=${LLVM_USE_LINKER}") + endif() + if (LLVM_EXTERNAL_CLANG_SOURCE_DIR) + # Propagate LLVM_EXTERNAL_CLANG_SOURCE_DIR so that clang-tblgen can be built + set(external_clang_dir "-DLLVM_EXTERNAL_CLANG_SOURCE_DIR=${LLVM_EXTERNAL_CLANG_SOURCE_DIR}") + endif() + add_custom_command(OUTPUT ${LLVM_${target_name}_BUILD} COMMAND ${CMAKE_COMMAND} -E make_directory ${LLVM_${target_name}_BUILD} COMMENT "Creating ${LLVM_${target_name}_BUILD}...") @@ -23,6 +34,10 @@ function(llvm_create_cross_target_internal target_name toolchain buildtype) COMMAND ${CMAKE_COMMAND} -G "${CMAKE_GENERATOR}" ${CROSS_TOOLCHAIN_FLAGS_${target_name}} ${CMAKE_SOURCE_DIR} -DLLVM_TARGET_IS_CROSSCOMPILE_HOST=TRUE + -DCMAKE_C_COMPILER=${CMAKE_C_COMPILER} + -DCMAKE_CXX_COMPILER=${CMAKE_CXX_COMPILER} + -DLLVM_TARGETS_TO_BUILD=Native + ${build_type_flags} ${linker_flag} ${external_clang_dir} WORKING_DIRECTORY ${LLVM_${target_name}_BUILD} DEPENDS CREATE_LLVM_${target_name} COMMENT "Configuring ${target_name} LLVM...") @@ -30,34 +45,6 @@ function(llvm_create_cross_target_internal target_name toolchain buildtype) add_custom_target(CONFIGURE_LLVM_${target_name} DEPENDS ${LLVM_${target_name}_BUILD}/CMakeCache.txt) - set_directory_properties(PROPERTIES ADDITIONAL_MAKE_CLEAN_FILES - ${LLVM_${target_name}_BUILD}) - - if(NOT IS_DIRECTORY ${LLVM_${target_name}_BUILD}) - - message(STATUS "Configuring ${target_name} build...") - execute_process(COMMAND ${CMAKE_COMMAND} -E make_directory - ${LLVM_${target_name}_BUILD} ) - - message(STATUS "Configuring ${target_name} targets...") - if (buildtype) - set(build_type_flags "-DCMAKE_BUILD_TYPE=${buildtype}") - endif() - if (LLVM_USE_LINKER AND NOT CMAKE_CROSSCOMPILING) - set(linker_flag "-DLLVM_USE_LINKER=${LLVM_USE_LINKER}") - endif() - if (LLVM_EXTERNAL_CLANG_SOURCE_DIR) - # Propagate LLVM_EXTERNAL_CLANG_SOURCE_DIR so that clang-tblgen can be built - set(external_clang_dir "-DLLVM_EXTERNAL_CLANG_SOURCE_DIR=${LLVM_EXTERNAL_CLANG_SOURCE_DIR}") - endif() - execute_process(COMMAND ${CMAKE_COMMAND} ${build_type_flags} - -G "${CMAKE_GENERATOR}" -DLLVM_TARGETS_TO_BUILD=${LLVM_TARGETS_TO_BUILD} - ${CROSS_TOOLCHAIN_FLAGS_${target_name}} ${CMAKE_SOURCE_DIR} - -DLLVM_TARGET_IS_CROSSCOMPILE_HOST=TRUE - ${external_clang_dir} ${linker_flag} - WORKING_DIRECTORY ${LLVM_${target_name}_BUILD} ) - endif(NOT IS_DIRECTORY ${LLVM_${target_name}_BUILD}) - endfunction() function(llvm_create_cross_target target_name sysroot) diff --git a/cmake/modules/LLVMConfig.cmake.in b/cmake/modules/LLVMConfig.cmake.in index 169fc9987be8c..0772016916562 100644 --- a/cmake/modules/LLVMConfig.cmake.in +++ b/cmake/modules/LLVMConfig.cmake.in @@ -72,6 +72,7 @@ set(LLVM_CMAKE_DIR "@LLVM_CONFIG_CMAKE_DIR@") set(LLVM_BINARY_DIR "@LLVM_CONFIG_BINARY_DIR@") set(LLVM_TOOLS_BINARY_DIR "@LLVM_CONFIG_TOOLS_BINARY_DIR@") set(LLVM_TOOLS_INSTALL_DIR "@LLVM_TOOLS_INSTALL_DIR@") +set(LLVM_HAVE_OPT_VIEWER_MODULES @LLVM_HAVE_OPT_VIEWER_MODULES@) if(NOT TARGET LLVMSupport) set(LLVM_EXPORTED_TARGETS "@LLVM_CONFIG_EXPORTS@") diff --git a/cmake/modules/LLVMExternalProjectUtils.cmake b/cmake/modules/LLVMExternalProjectUtils.cmake index 8ecf42acfee10..373387c755c8c 100644 --- a/cmake/modules/LLVMExternalProjectUtils.cmake +++ b/cmake/modules/LLVMExternalProjectUtils.cmake @@ -189,12 +189,9 @@ function(llvm_ExternalProject_Add name source_dir) install(CODE "execute_process\(COMMAND \${CMAKE_COMMAND} -DCMAKE_INSTALL_PREFIX=\${CMAKE_INSTALL_PREFIX} -P ${BINARY_DIR}/cmake_install.cmake \)" COMPONENT ${name}) - add_custom_target(install-${name} - DEPENDS ${name} - COMMAND "${CMAKE_COMMAND}" - -DCMAKE_INSTALL_COMPONENT=${name} - -P "${CMAKE_BINARY_DIR}/cmake_install.cmake" - USES_TERMINAL) + add_llvm_install_targets(install-${name} + DEPENDS ${name} + COMPONENT ${name}) endif() # Add top-level targets diff --git a/docs/CodeGenerator.rst b/docs/CodeGenerator.rst index bcdc722835665..5c0fb064959ef 100644 --- a/docs/CodeGenerator.rst +++ b/docs/CodeGenerator.rst @@ -1578,6 +1578,17 @@ which lowers MCInst's into machine code bytes and relocations. This is important if you want to support direct .o file emission, or would like to implement an assembler for your target. +Emitting function stack size information +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +A section containing metadata on function stack sizes will be emitted when +``TargetLoweringObjectFile::StackSizesSection`` is not null, and +``TargetOptions::EmitStackSizeSection`` is set (-stack-size-section). The +section will contain an array of pairs of function symbol references (8 byte) +and stack sizes (unsigned LEB128). The stack size values only include the space +allocated in the function prologue. Functions with dynamic stack allocations are +not included. + VLIW Packetizer --------------- diff --git a/docs/CommandGuide/llc.rst b/docs/CommandGuide/llc.rst index 5094259f9f952..95945e68d13f3 100644 --- a/docs/CommandGuide/llc.rst +++ b/docs/CommandGuide/llc.rst @@ -132,6 +132,14 @@ End-user Options Specify which EABI version should conform to. Valid EABI versions are *gnu*, *4* and *5*. Default value (*default*) depends on the triple. +.. option:: -stack-size-section + + Emit the .stack_sizes section which contains stack size metadata. The section + contains an array of pairs of function symbol references (8 byte) and stack + sizes (unsigned LEB128). The stack size values only include the space allocated + in the function prologue. Functions with dynamic stack allocations are not + included. + Tuning/Configuration Options ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/docs/GettingStarted.rst b/docs/GettingStarted.rst index a90a4b05dd114..ed2e936d1360b 100644 --- a/docs/GettingStarted.rst +++ b/docs/GettingStarted.rst @@ -57,7 +57,7 @@ Here's the short story for getting up and running quickly with LLVM: * ``cd where-you-want-llvm-to-live`` * ``cd llvm/tools/clang/tools`` * ``svn co http://llvm.org/svn/llvm-project/clang-tools-extra/trunk extra`` - + #. Checkout LLD linker **[Optional]**: * ``cd where-you-want-llvm-to-live`` @@ -466,34 +466,13 @@ populate it with the LLVM source code, Makefiles, test directories, and local copies of documentation files. If you want to get a specific release (as opposed to the most recent revision), -you can checkout it from the '``tags``' directory (instead of '``trunk``'). The +you can check it out from the '``tags``' directory (instead of '``trunk``'). The following releases are located in the following subdirectories of the '``tags``' directory: -* Release 3.4: **RELEASE_34/final** -* Release 3.3: **RELEASE_33/final** -* Release 3.2: **RELEASE_32/final** -* Release 3.1: **RELEASE_31/final** -* Release 3.0: **RELEASE_30/final** -* Release 2.9: **RELEASE_29/final** -* Release 2.8: **RELEASE_28** -* Release 2.7: **RELEASE_27** -* Release 2.6: **RELEASE_26** -* Release 2.5: **RELEASE_25** -* Release 2.4: **RELEASE_24** -* Release 2.3: **RELEASE_23** -* Release 2.2: **RELEASE_22** -* Release 2.1: **RELEASE_21** -* Release 2.0: **RELEASE_20** -* Release 1.9: **RELEASE_19** -* Release 1.8: **RELEASE_18** -* Release 1.7: **RELEASE_17** -* Release 1.6: **RELEASE_16** -* Release 1.5: **RELEASE_15** -* Release 1.4: **RELEASE_14** -* Release 1.3: **RELEASE_13** -* Release 1.2: **RELEASE_12** -* Release 1.1: **RELEASE_11** +* Release 3.5.0 and later: **RELEASE_350/final** and so on +* Release 2.9 through 3.4: **RELEASE_29/final** and so on +* Release 1.1 through 2.8: **RELEASE_11** and so on * Release 1.0: **RELEASE_1** If you would like to get the LLVM test suite (a separate package as of 1.4), you diff --git a/docs/LangRef.rst b/docs/LangRef.rst index a091cc1dd2ae7..dbd456667772c 100644 --- a/docs/LangRef.rst +++ b/docs/LangRef.rst @@ -6827,10 +6827,12 @@ Both arguments must have identical types. Semantics: """""""""" -This instruction returns the *remainder* of a division. The remainder -has the same sign as the dividend. This instruction can also take any -number of :ref:`fast-math flags `, which are optimization hints -to enable otherwise unsafe floating point optimizations: +Return the same value as a libm '``fmod``' function but without trapping or +setting ``errno``. + +The remainder has the same sign as the dividend. This instruction can also +take any number of :ref:`fast-math flags `, which are optimization +hints to enable otherwise unsafe floating-point optimizations: Example: """""""" diff --git a/docs/LibFuzzer.rst b/docs/LibFuzzer.rst index a2198f2b5a816..7a105e5ed129a 100644 --- a/docs/LibFuzzer.rst +++ b/docs/LibFuzzer.rst @@ -246,6 +246,10 @@ The most important command line options are: the process is treated as a failure case. The limit is checked in a separate thread every second. If running w/o ASAN/MSAN, you may use 'ulimit -v' instead. +``-malloc_limit_mb`` + If non-zero, the fuzzer will exit if the target tries to allocate this + number of Mb with one malloc call. + If zero (default) same limit as rss_limit_mb is applied. ``-timeout_exitcode`` Exit code (default 77) used if libFuzzer reports a timeout. ``-error_exitcode`` diff --git a/docs/MIRLangRef.rst b/docs/MIRLangRef.rst index b4ca8f2347a79..fff0d3ef0eb09 100644 --- a/docs/MIRLangRef.rst +++ b/docs/MIRLangRef.rst @@ -246,13 +246,25 @@ blocks are referenced using the following syntax: .. code-block:: text - %bb.[.] + %bb. -Examples: +Example: .. code-block:: llvm %bb.0 + +The following syntax is also supported, but the former syntax is preferred for +block references: + +.. code-block:: text + + %bb.[.] + +Example: + +.. code-block:: llvm + %bb.1.then Successors diff --git a/docs/NVPTXUsage.rst b/docs/NVPTXUsage.rst index 159fe078653c2..38222afbc63ad 100644 --- a/docs/NVPTXUsage.rst +++ b/docs/NVPTXUsage.rst @@ -499,7 +499,7 @@ The output we get from ``llc`` (as of LLVM 3.4): .reg .s32 %r<2>; .reg .s64 %rl<8>; - // BB#0: // %entry + // %bb.0: // %entry ld.param.u64 %rl1, [kernel_param_0]; mov.u32 %r1, %tid.x; mul.wide.s32 %rl2, %r1, 4; @@ -897,7 +897,7 @@ This gives us the following PTX (excerpt): .reg .s32 %r<21>; .reg .s64 %rl<8>; - // BB#0: // %entry + // %bb.0: // %entry ld.param.u64 %rl2, [kernel_param_0]; mov.u32 %r3, %tid.x; ld.param.u64 %rl3, [kernel_param_1]; @@ -921,7 +921,7 @@ This gives us the following PTX (excerpt): abs.f32 %f4, %f1; setp.gtu.f32 %p4, %f4, 0f7F800000; @%p4 bra BB0_4; - // BB#3: // %__nv_isnanf.exit5.i + // %bb.3: // %__nv_isnanf.exit5.i abs.f32 %f5, %f2; setp.le.f32 %p5, %f5, 0f7F800000; @%p5 bra BB0_5; @@ -953,7 +953,7 @@ This gives us the following PTX (excerpt): selp.f32 %f110, 0f7F800000, %f99, %p16; setp.eq.f32 %p17, %f110, 0f7F800000; @%p17 bra BB0_28; - // BB#27: + // %bb.27: fma.rn.f32 %f110, %f110, %f108, %f110; BB0_28: // %__internal_accurate_powf.exit.i setp.lt.f32 %p18, %f1, 0f00000000; diff --git a/docs/XRay.rst b/docs/XRay.rst index e9ecc13e3b286..b4443c4d8060a 100644 --- a/docs/XRay.rst +++ b/docs/XRay.rst @@ -143,7 +143,7 @@ variable, where we list down the options and their defaults below. | | | | instrumentation points | | | | | before main. | +-------------------+-----------------+---------------+------------------------+ -| xray_naive_log | ``bool`` | ``true`` | Whether to install | +| xray_naive_log | ``bool`` | ``false`` | Whether to install | | | | | the naive log | | | | | implementation. | +-------------------+-----------------+---------------+------------------------+ @@ -258,8 +258,11 @@ supports the following subcommands: - ``account``: Performs basic function call accounting statistics with various options for sorting, and output formats (supports CSV, YAML, and console-friendly TEXT). -- ``convert``: Converts an XRay log file from one format to another. Currently - only converts to YAML. +- ``convert``: Converts an XRay log file from one format to another. We can + convert from binary XRay traces (both naive and FDR mode) to YAML, + `flame-graph `_ friendly text + formats, as well as `Chrome Trace Viewer (catapult) + ` formats. - ``graph``: Generates a DOT graph of the function call relationships between functions found in an XRay trace. - ``stack``: Reconstructs function call stacks from a timeline of function diff --git a/docs/XRayExample.rst b/docs/XRayExample.rst index 56f17507d82f1..953833bc1ef65 100644 --- a/docs/XRayExample.rst +++ b/docs/XRayExample.rst @@ -60,7 +60,7 @@ to enable XRay at application start. To do this, XRay checks the $ ./bin/llc input.ll # We need to set the XRAY_OPTIONS to enable some features. - $ XRAY_OPTIONS="patch_premain=true" ./bin/llc input.ll + $ XRAY_OPTIONS="patch_premain=true xray_naive_log=true" ./bin/llc input.ll ==69819==XRay: Log file in 'xray-log.llc.m35qPB' At this point we now have an XRay trace we can start analysing. diff --git a/include/llvm/Analysis/MemoryDependenceAnalysis.h b/include/llvm/Analysis/MemoryDependenceAnalysis.h index c2974525a6ff8..391a333594e98 100644 --- a/include/llvm/Analysis/MemoryDependenceAnalysis.h +++ b/include/llvm/Analysis/MemoryDependenceAnalysis.h @@ -407,6 +407,12 @@ class MemoryDependenceResults { void getNonLocalPointerDependency(Instruction *QueryInst, SmallVectorImpl &Result); + /// Perform a dependency query specifically for QueryInst's access to Loc. + /// The other comments for getNonLocalPointerDependency apply here as well. + void getNonLocalPointerDependencyFrom(Instruction *QueryInst, + const MemoryLocation &Loc, bool isLoad, + SmallVectorImpl &Result); + /// Removes an instruction from the dependence analysis, updating the /// dependence of instructions that previously depended on it. void removeInstruction(Instruction *InstToRemove); diff --git a/include/llvm/Analysis/ScalarEvolution.h b/include/llvm/Analysis/ScalarEvolution.h index 96309debd84a6..d60c16158fdba 100644 --- a/include/llvm/Analysis/ScalarEvolution.h +++ b/include/llvm/Analysis/ScalarEvolution.h @@ -1272,9 +1272,6 @@ class ScalarEvolution { /// function as they are computed. DenseMap PredicatedBackedgeTakenCounts; - // Cache the calculated exit limits for the loops. - DenseMap ExitLimits; - /// This map contains entries for all of the PHI instructions that we /// attempt to compute constant evolutions for. This allows us to avoid /// potentially expensive recomputation of these properties. An instruction @@ -1426,9 +1423,6 @@ class ScalarEvolution { ExitLimit computeExitLimit(const Loop *L, BasicBlock *ExitingBlock, bool AllowPredicates = false); - ExitLimit computeExitLimitImpl(const Loop *L, BasicBlock *ExitingBlock, - bool AllowPredicates = false); - /// Compute the number of times the backedge of the specified loop will /// execute if its exit condition were a conditional branch of ExitCond, /// TBB, and FBB. @@ -1668,9 +1662,8 @@ class ScalarEvolution { /// to be a constant. Optional computeConstantDifference(const SCEV *LHS, const SCEV *RHS); - /// Drop memoized information computed for S. Only erase Exit Limits info if - /// we expect that the operation we have made is going to change it. - void forgetMemoizedResults(const SCEV *S, bool EraseExitLimit = true); + /// Drop memoized information computed for S. + void forgetMemoizedResults(const SCEV *S); /// Return an existing SCEV for V if there is one, otherwise return nullptr. const SCEV *getExistingSCEV(Value *V); diff --git a/include/llvm/BinaryFormat/Wasm.h b/include/llvm/BinaryFormat/Wasm.h index 26475c27df382..fe47b8f63d7e5 100644 --- a/include/llvm/BinaryFormat/Wasm.h +++ b/include/llvm/BinaryFormat/Wasm.h @@ -189,13 +189,14 @@ enum : unsigned { WASM_SEGMENT_INFO = 0x5, }; -const unsigned WASM_SYMBOL_BINDING_MASK = 0x3; - -enum : unsigned { - WASM_SYMBOL_BINDING_GLOBAL = 0x0, - WASM_SYMBOL_BINDING_WEAK = 0x1, - WASM_SYMBOL_BINDING_LOCAL = 0x2, -}; +const unsigned WASM_SYMBOL_BINDING_MASK = 0x3; +const unsigned WASM_SYMBOL_VISIBILITY_MASK = 0x4; + +const unsigned WASM_SYMBOL_BINDING_GLOBAL = 0x0; +const unsigned WASM_SYMBOL_BINDING_WEAK = 0x1; +const unsigned WASM_SYMBOL_BINDING_LOCAL = 0x2; +const unsigned WASM_SYMBOL_VISIBILITY_DEFAULT = 0x0; +const unsigned WASM_SYMBOL_VISIBILITY_HIDDEN = 0x4; #define WASM_RELOC(name, value) name = value, diff --git a/include/llvm/CodeGen/AsmPrinter.h b/include/llvm/CodeGen/AsmPrinter.h index 1d65f703b84d2..b8944a668000d 100644 --- a/include/llvm/CodeGen/AsmPrinter.h +++ b/include/llvm/CodeGen/AsmPrinter.h @@ -295,6 +295,8 @@ class AsmPrinter : public MachineFunctionPass { void emitFrameAlloc(const MachineInstr &MI); + void emitStackSizeSection(const MachineFunction &MF); + enum CFIMoveType { CFI_M_None, CFI_M_EH, CFI_M_Debug }; CFIMoveType needsCFIMoves() const; diff --git a/include/llvm/CodeGen/CommandFlags.def b/include/llvm/CodeGen/CommandFlags.def index 83cbeb0341fa7..fe96033a9c617 100644 --- a/include/llvm/CodeGen/CommandFlags.def +++ b/include/llvm/CodeGen/CommandFlags.def @@ -255,6 +255,10 @@ static cl::opt DebuggerTuningOpt( clEnumValN(DebuggerKind::LLDB, "lldb", "lldb"), clEnumValN(DebuggerKind::SCE, "sce", "SCE targets (e.g. PS4)"))); +static cl::opt EnableStackSizeSection( + "stack-size-section", + cl::desc("Emit a section containing stack size metadata"), cl::init(false)); + // Common utility function tightly tied to the options listed here. Initializes // a TargetOptions object with CodeGen flags and returns it. static TargetOptions InitTargetOptionsFromCodeGenFlags() { @@ -281,6 +285,7 @@ static TargetOptions InitTargetOptionsFromCodeGenFlags() { Options.UniqueSectionNames = UniqueSectionNames; Options.EmulatedTLS = EmulatedTLS; Options.ExceptionModel = ExceptionModel; + Options.EmitStackSizeSection = EnableStackSizeSection; Options.MCOptions = InitMCTargetOptionsFromFlags(); diff --git a/include/llvm/CodeGen/GlobalISel/InstructionSelector.h b/include/llvm/CodeGen/GlobalISel/InstructionSelector.h index 726a702d96b6a..e599a1b179ece 100644 --- a/include/llvm/CodeGen/GlobalISel/InstructionSelector.h +++ b/include/llvm/CodeGen/GlobalISel/InstructionSelector.h @@ -115,6 +115,8 @@ enum { /// - InsnID - Instruction ID /// - Ordering - The AtomicOrdering value GIM_CheckAtomicOrdering, + GIM_CheckAtomicOrderingOrStrongerThan, + GIM_CheckAtomicOrderingWeakerThan, /// Check the type for the specified operand /// - InsnID - Instruction ID diff --git a/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h b/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h index 8848274d22e9e..b0859567db41e 100644 --- a/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h +++ b/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h @@ -244,6 +244,44 @@ bool InstructionSelector::executeMatchTable( return false; break; } + case GIM_CheckAtomicOrderingOrStrongerThan: { + int64_t InsnID = MatchTable[CurrentIdx++]; + AtomicOrdering Ordering = (AtomicOrdering)MatchTable[CurrentIdx++]; + DEBUG_WITH_TYPE(TgtInstructionSelector::getName(), + dbgs() << CurrentIdx + << ": GIM_CheckAtomicOrderingOrStrongerThan(MIs[" + << InsnID << "], " << (uint64_t)Ordering << ")\n"); + assert(State.MIs[InsnID] != nullptr && "Used insn before defined"); + + if (!State.MIs[InsnID]->hasOneMemOperand()) + if (handleReject() == RejectAndGiveUp) + return false; + + for (const auto &MMO : State.MIs[InsnID]->memoperands()) + if (!isAtLeastOrStrongerThan(MMO->getOrdering(), Ordering)) + if (handleReject() == RejectAndGiveUp) + return false; + break; + } + case GIM_CheckAtomicOrderingWeakerThan: { + int64_t InsnID = MatchTable[CurrentIdx++]; + AtomicOrdering Ordering = (AtomicOrdering)MatchTable[CurrentIdx++]; + DEBUG_WITH_TYPE(TgtInstructionSelector::getName(), + dbgs() << CurrentIdx + << ": GIM_CheckAtomicOrderingWeakerThan(MIs[" + << InsnID << "], " << (uint64_t)Ordering << ")\n"); + assert(State.MIs[InsnID] != nullptr && "Used insn before defined"); + + if (!State.MIs[InsnID]->hasOneMemOperand()) + if (handleReject() == RejectAndGiveUp) + return false; + + for (const auto &MMO : State.MIs[InsnID]->memoperands()) + if (isAtLeastOrStrongerThan(MMO->getOrdering(), Ordering)) + if (handleReject() == RejectAndGiveUp) + return false; + break; + } case GIM_CheckType: { int64_t InsnID = MatchTable[CurrentIdx++]; int64_t OpIdx = MatchTable[CurrentIdx++]; diff --git a/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h b/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h index 5fe3137d6d704..1ea9dba5e990d 100644 --- a/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h +++ b/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h @@ -571,6 +571,30 @@ class MachineIRBuilder { MachineInstrBuilder buildStore(unsigned Val, unsigned Addr, MachineMemOperand &MMO); + /// Build and insert `Res = G_ATOMIC_LOAD Addr, MMO`. + /// + /// Loads the value stored at \p Addr. Puts the result in \p Res. + /// + /// \pre setBasicBlock or setMI must have been called. + /// \pre \p Res must be a generic virtual register. + /// \pre \p Addr must be a generic virtual register with pointer type. + /// + /// \return a MachineInstrBuilder for the newly created instruction. + MachineInstrBuilder buildAtomicLoad(unsigned Res, unsigned Addr, + MachineMemOperand &MMO); + + /// Build and insert `G_ATOMIC_STORE Val, Addr, MMO`. + /// + /// Stores the value \p Val to \p Addr. + /// + /// \pre setBasicBlock or setMI must have been called. + /// \pre \p Val must be a generic virtual register. + /// \pre \p Addr must be a generic virtual register with pointer type. + /// + /// \return a MachineInstrBuilder for the newly created instruction. + MachineInstrBuilder buildAtomicStore(unsigned Val, unsigned Addr, + MachineMemOperand &MMO); + /// Build and insert `Res0, ... = G_EXTRACT Src, Idx0`. /// /// \pre setBasicBlock or setMI must have been called. @@ -734,6 +758,24 @@ class MachineIRBuilder { /// \return The newly created instruction. MachineInstrBuilder buildExtractVectorElement(unsigned Res, unsigned Val, unsigned Idx); + + /// Build and insert `OldValRes = G_ATOMIC_CMPXCHG Addr, CmpVal, NewVal, + /// MMO`. + /// + /// Atomically replace the value at \p Addr with \p NewVal if it is currently + /// \p CmpVal otherwise leaves it unchanged. Puts the original value from \p + /// Addr in \p Res. + /// + /// \pre setBasicBlock or setMI must have been called. + /// \pre \p OldValRes must be a generic virtual register of scalar type. + /// \pre \p Addr must be a generic virtual register with pointer type. + /// \pre \p OldValRes, \p CmpVal, and \p NewVal must be generic virtual + /// registers of the same type. + /// + /// \return a MachineInstrBuilder for the newly created instruction. + MachineInstrBuilder buildAtomicCmpXchg(unsigned OldValRes, unsigned Addr, + unsigned CmpVal, unsigned NewVal, + MachineMemOperand &MMO); }; } // End namespace llvm. diff --git a/include/llvm/CodeGen/MachineBasicBlock.h b/include/llvm/CodeGen/MachineBasicBlock.h index 0f5b04d904598..0730eb763e17b 100644 --- a/include/llvm/CodeGen/MachineBasicBlock.h +++ b/include/llvm/CodeGen/MachineBasicBlock.h @@ -25,6 +25,7 @@ #include "llvm/MC/LaneBitmask.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/Support/BranchProbability.h" +#include "llvm/Support/Printable.h" #include #include #include @@ -771,6 +772,14 @@ class MachineBasicBlock raw_ostream& operator<<(raw_ostream &OS, const MachineBasicBlock &MBB); +/// Prints a machine basic block reference. +/// +/// The format is: +/// %bb.5 - a machine basic block with MBB.getNumber() == 5. +/// +/// Usage: OS << printMBBReference(MBB) << '\n'; +Printable printMBBReference(const MachineBasicBlock &MBB); + // This is useful when building IndexedMaps keyed on basic block pointers. struct MBB2NumberFunctor { using argument_type = const MachineBasicBlock *; diff --git a/include/llvm/CodeGen/MachineMemOperand.h b/include/llvm/CodeGen/MachineMemOperand.h index cdec9e79833e7..971244897f924 100644 --- a/include/llvm/CodeGen/MachineMemOperand.h +++ b/include/llvm/CodeGen/MachineMemOperand.h @@ -47,17 +47,27 @@ struct MachinePointerInfo { uint8_t StackID; - explicit MachinePointerInfo(const Value *v = nullptr, int64_t offset = 0, + unsigned AddrSpace; + + explicit MachinePointerInfo(const Value *v, int64_t offset = 0, uint8_t ID = 0) - : V(v), Offset(offset), StackID(ID) {} + : V(v), Offset(offset), StackID(ID) { + AddrSpace = v ? v->getType()->getPointerAddressSpace() : 0; + } - explicit MachinePointerInfo(const PseudoSourceValue *v, - int64_t offset = 0, + explicit MachinePointerInfo(const PseudoSourceValue *v, int64_t offset = 0, uint8_t ID = 0) - : V(v), Offset(offset), StackID(ID) {} + : V(v), Offset(offset), StackID(ID) { + AddrSpace = v ? v->getAddressSpace() : 0; + } + + explicit MachinePointerInfo(unsigned AddressSpace = 0) + : V((const Value *)nullptr), Offset(0), StackID(0), + AddrSpace(AddressSpace) {} MachinePointerInfo getWithOffset(int64_t O) const { - if (V.isNull()) return MachinePointerInfo(); + if (V.isNull()) + return MachinePointerInfo(AddrSpace); if (V.is()) return MachinePointerInfo(V.get(), Offset+O, StackID); return MachinePointerInfo(V.get(), Offset+O, @@ -89,6 +99,9 @@ struct MachinePointerInfo { /// Stack pointer relative access. static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID = 0); + + /// Stack memory without other information. + static MachinePointerInfo getUnknownStack(MachineFunction &MF); }; diff --git a/include/llvm/CodeGen/MachineOperand.h b/include/llvm/CodeGen/MachineOperand.h index f477745867ea3..64889eb3a2d11 100644 --- a/include/llvm/CodeGen/MachineOperand.h +++ b/include/llvm/CodeGen/MachineOperand.h @@ -116,9 +116,9 @@ class MachineOperand { /// the same register. In that case, the instruction may depend on those /// operands reading the same dont-care value. For example: /// - /// %vreg1 = XOR %vreg2, %vreg2 + /// %1 = XOR %2, %2 /// - /// Any register can be used for %vreg2, and its value doesn't matter, but + /// Any register can be used for %2, and its value doesn't matter, but /// the two operands must be the same register. /// bool IsUndef : 1; diff --git a/include/llvm/CodeGen/TargetInstrInfo.h b/include/llvm/CodeGen/TargetInstrInfo.h index 6770e503e6154..c4a3865e7f089 100644 --- a/include/llvm/CodeGen/TargetInstrInfo.h +++ b/include/llvm/CodeGen/TargetInstrInfo.h @@ -422,10 +422,10 @@ class TargetInstrInfo : public MCInstrInfo { /// and \p DefIdx. /// \p [out] InputRegs of the equivalent REG_SEQUENCE. Each element of /// the list is modeled as . - /// E.g., REG_SEQUENCE vreg1:sub1, sub0, vreg2, sub1 would produce + /// E.g., REG_SEQUENCE %1:sub1, sub0, %2, sub1 would produce /// two elements: - /// - vreg1:sub1, sub0 - /// - vreg2<:0>, sub1 + /// - %1:sub1, sub0 + /// - %2<:0>, sub1 /// /// \returns true if it is possible to build such an input sequence /// with the pair \p MI, \p DefIdx. False otherwise. @@ -442,8 +442,8 @@ class TargetInstrInfo : public MCInstrInfo { /// Build the equivalent inputs of a EXTRACT_SUBREG for the given \p MI /// and \p DefIdx. /// \p [out] InputReg of the equivalent EXTRACT_SUBREG. - /// E.g., EXTRACT_SUBREG vreg1:sub1, sub0, sub1 would produce: - /// - vreg1:sub1, sub0 + /// E.g., EXTRACT_SUBREG %1:sub1, sub0, sub1 would produce: + /// - %1:sub1, sub0 /// /// \returns true if it is possible to build such an input sequence /// with the pair \p MI, \p DefIdx. False otherwise. @@ -460,9 +460,9 @@ class TargetInstrInfo : public MCInstrInfo { /// and \p DefIdx. /// \p [out] BaseReg and \p [out] InsertedReg contain /// the equivalent inputs of INSERT_SUBREG. - /// E.g., INSERT_SUBREG vreg0:sub0, vreg1:sub1, sub3 would produce: - /// - BaseReg: vreg0:sub0 - /// - InsertedReg: vreg1:sub1, sub3 + /// E.g., INSERT_SUBREG %0:sub0, %1:sub1, sub3 would produce: + /// - BaseReg: %0:sub0 + /// - InsertedReg: %1:sub1, sub3 /// /// \returns true if it is possible to build such an input sequence /// with the pair \p MI, \p DefIdx. False otherwise. diff --git a/include/llvm/CodeGen/TargetOpcodes.def b/include/llvm/CodeGen/TargetOpcodes.def index 3497dcf195d01..3cca0eb567e0c 100644 --- a/include/llvm/CodeGen/TargetOpcodes.def +++ b/include/llvm/CodeGen/TargetOpcodes.def @@ -265,6 +265,15 @@ HANDLE_TARGET_OPCODE(G_LOAD) /// Generic store. HANDLE_TARGET_OPCODE(G_STORE) +/// Generic atomic load +HANDLE_TARGET_OPCODE(G_ATOMIC_LOAD) + +/// Generic atomic store +HANDLE_TARGET_OPCODE(G_ATOMIC_STORE) + +/// Generic atomic cmpxchg with internal success check. +HANDLE_TARGET_OPCODE(G_ATOMIC_CMPXCHG_WITH_SUCCESS) + /// Generic atomic cmpxchg. HANDLE_TARGET_OPCODE(G_ATOMIC_CMPXCHG) diff --git a/include/llvm/CodeGen/TargetRegisterInfo.h b/include/llvm/CodeGen/TargetRegisterInfo.h index 308216b799820..92d38d51feefe 100644 --- a/include/llvm/CodeGen/TargetRegisterInfo.h +++ b/include/llvm/CodeGen/TargetRegisterInfo.h @@ -1138,8 +1138,8 @@ struct VirtReg2IndexFunctor { /// /// The format is: /// %noreg - NoRegister -/// %vreg5 - a virtual register. -/// %vreg5:sub_8bit - a virtual register with sub-register index (with TRI). +/// %5 - a virtual register. +/// %5:sub_8bit - a virtual register with sub-register index (with TRI). /// %eax - a physical register /// %physreg17 - a physical register when no TRI instance given. /// diff --git a/include/llvm/DebugInfo/CodeView/TypeTableBuilder.h b/include/llvm/DebugInfo/CodeView/AppendingTypeTableBuilder.h similarity index 77% rename from include/llvm/DebugInfo/CodeView/TypeTableBuilder.h rename to include/llvm/DebugInfo/CodeView/AppendingTypeTableBuilder.h index d9afe1ab4a41f..bd1743511ed4b 100644 --- a/include/llvm/DebugInfo/CodeView/TypeTableBuilder.h +++ b/include/llvm/DebugInfo/CodeView/AppendingTypeTableBuilder.h @@ -1,4 +1,4 @@ -//===- TypeTableBuilder.h ----------------------------------------*- C++-*-===// +//===- AppendingTypeTableBuilder.h -------------------------------*- C++-*-===// // // The LLVM Compiler Infrastructure // @@ -7,19 +7,16 @@ // //===----------------------------------------------------------------------===// -#ifndef LLVM_DEBUGINFO_CODEVIEW_TYPETABLEBUILDER_H -#define LLVM_DEBUGINFO_CODEVIEW_TYPETABLEBUILDER_H +#ifndef LLVM_DEBUGINFO_CODEVIEW_APPENDINGTYPETABLEBUILDER_H +#define LLVM_DEBUGINFO_CODEVIEW_APPENDINGTYPETABLEBUILDER_H #include "llvm/ADT/ArrayRef.h" -#include "llvm/ADT/Optional.h" #include "llvm/ADT/SmallVector.h" #include "llvm/DebugInfo/CodeView/CodeView.h" #include "llvm/DebugInfo/CodeView/SimpleTypeSerializer.h" #include "llvm/DebugInfo/CodeView/TypeCollection.h" #include "llvm/DebugInfo/CodeView/TypeIndex.h" -#include "llvm/DebugInfo/CodeView/TypeRecord.h" #include "llvm/Support/Allocator.h" -#include "llvm/Support/Error.h" #include #include #include @@ -29,22 +26,18 @@ namespace llvm { namespace codeview { class ContinuationRecordBuilder; -class TypeHasher; -class TypeTableBuilder : public TypeCollection { +class AppendingTypeTableBuilder : public TypeCollection { BumpPtrAllocator &RecordStorage; SimpleTypeSerializer SimpleSerializer; - /// Private type record hashing implementation details are handled here. - std::unique_ptr Hasher; - /// Contains a list of all records indexed by TypeIndex.toArrayIndex(). SmallVector, 2> SeenRecords; public: - explicit TypeTableBuilder(BumpPtrAllocator &Storage, bool Hash = true); - ~TypeTableBuilder(); + explicit AppendingTypeTableBuilder(BumpPtrAllocator &Storage); + ~AppendingTypeTableBuilder(); // TypeTableCollection overrides Optional getFirst() override; diff --git a/include/llvm/DebugInfo/CodeView/MergingTypeTableBuilder.h b/include/llvm/DebugInfo/CodeView/MergingTypeTableBuilder.h new file mode 100644 index 0000000000000..2618fc6ba753c --- /dev/null +++ b/include/llvm/DebugInfo/CodeView/MergingTypeTableBuilder.h @@ -0,0 +1,91 @@ +//===- MergingTypeTableBuilder.h ---------------------------------*- C++-*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_DEBUGINFO_CODEVIEW_MERGINGTYPETABLEBUILDER_H +#define LLVM_DEBUGINFO_CODEVIEW_MERGINGTYPETABLEBUILDER_H + +#include "llvm/ADT/ArrayRef.h" +#include "llvm/ADT/DenseSet.h" +#include "llvm/ADT/SmallVector.h" +#include "llvm/DebugInfo/CodeView/CodeView.h" +#include "llvm/DebugInfo/CodeView/SimpleTypeSerializer.h" +#include "llvm/DebugInfo/CodeView/TypeCollection.h" +#include "llvm/DebugInfo/CodeView/TypeIndex.h" +#include "llvm/Support/Allocator.h" +#include +#include +#include +#include + +namespace llvm { +namespace codeview { + +class ContinuationRecordBuilder; +class TypeHasher; + +struct HashedType { + hash_code Hash; + ArrayRef Data; + TypeIndex Index; +}; + +class MergingTypeTableBuilder : public TypeCollection { + /// Storage for records. These need to outlive the TypeTableBuilder. + BumpPtrAllocator &RecordStorage; + + /// A serializer that can write non-continuation leaf types. Only used as + /// a convenience function so that we can provide an interface method to + /// write an unserialized record. + SimpleTypeSerializer SimpleSerializer; + + /// Hash table. + DenseSet HashedRecords; + + /// Contains a list of all records indexed by TypeIndex.toArrayIndex(). + SmallVector, 2> SeenRecords; + + /// Contains a list of all hash codes index by TypeIndex.toArrayIndex(). + SmallVector SeenHashes; + +public: + explicit MergingTypeTableBuilder(BumpPtrAllocator &Storage); + ~MergingTypeTableBuilder(); + + // TypeTableCollection overrides + Optional getFirst() override; + Optional getNext(TypeIndex Prev) override; + CVType getType(TypeIndex Index) override; + StringRef getTypeName(TypeIndex Index) override; + bool contains(TypeIndex Index) override; + uint32_t size() override; + uint32_t capacity() override; + + // public interface + void reset(); + TypeIndex nextTypeIndex() const; + + BumpPtrAllocator &getAllocator() { return RecordStorage; } + + ArrayRef> records() const; + ArrayRef hashes() const; + + TypeIndex insertRecordAs(hash_code Hash, ArrayRef &Record); + TypeIndex insertRecordBytes(ArrayRef &Record); + TypeIndex insertRecord(ContinuationRecordBuilder &Builder); + + template TypeIndex writeLeafType(T &Record) { + ArrayRef Data = SimpleSerializer.serialize(Record); + return insertRecordBytes(Data); + } +}; + +} // end namespace codeview +} // end namespace llvm + +#endif // LLVM_DEBUGINFO_CODEVIEW_MERGINGTYPETABLEBUILDER_H diff --git a/include/llvm/DebugInfo/CodeView/TypeStreamMerger.h b/include/llvm/DebugInfo/CodeView/TypeStreamMerger.h index d78fab47db668..c40396067dbf3 100644 --- a/include/llvm/DebugInfo/CodeView/TypeStreamMerger.h +++ b/include/llvm/DebugInfo/CodeView/TypeStreamMerger.h @@ -19,7 +19,7 @@ namespace llvm { namespace codeview { class TypeIndex; -class TypeTableBuilder; +class MergingTypeTableBuilder; /// \brief Merge one set of type records into another. This method assumes /// that all records are type records, and there are no Id records present. @@ -34,7 +34,7 @@ class TypeTableBuilder; /// /// \returns Error::success() if the operation succeeded, otherwise an /// appropriate error code. -Error mergeTypeRecords(TypeTableBuilder &Dest, +Error mergeTypeRecords(MergingTypeTableBuilder &Dest, SmallVectorImpl &SourceToDest, const CVTypeArray &Types); @@ -59,7 +59,7 @@ Error mergeTypeRecords(TypeTableBuilder &Dest, /// /// \returns Error::success() if the operation succeeded, otherwise an /// appropriate error code. -Error mergeIdRecords(TypeTableBuilder &Dest, ArrayRef Types, +Error mergeIdRecords(MergingTypeTableBuilder &Dest, ArrayRef Types, SmallVectorImpl &SourceToDest, const CVTypeArray &Ids); @@ -78,8 +78,8 @@ Error mergeIdRecords(TypeTableBuilder &Dest, ArrayRef Types, /// /// \returns Error::success() if the operation succeeded, otherwise an /// appropriate error code. -Error mergeTypeAndIdRecords(TypeTableBuilder &DestIds, - TypeTableBuilder &DestTypes, +Error mergeTypeAndIdRecords(MergingTypeTableBuilder &DestIds, + MergingTypeTableBuilder &DestTypes, SmallVectorImpl &SourceToDest, const CVTypeArray &IdsAndTypes); diff --git a/include/llvm/MC/MCObjectFileInfo.h b/include/llvm/MC/MCObjectFileInfo.h index d95f84d1d816e..c0b1443591c6e 100644 --- a/include/llvm/MC/MCObjectFileInfo.h +++ b/include/llvm/MC/MCObjectFileInfo.h @@ -154,6 +154,9 @@ class MCObjectFileInfo { /// It is initialized on demand so it can be overwritten (with uniquing). MCSection *EHFrameSection; + /// Section containing metadata on function stack sizes. + MCSection *StackSizesSection; + // ELF specific sections. MCSection *DataRelROSection; MCSection *MergeableConst4Section; @@ -287,6 +290,8 @@ class MCObjectFileInfo { MCSection *getStackMapSection() const { return StackMapSection; } MCSection *getFaultMapSection() const { return FaultMapSection; } + MCSection *getStackSizesSection() const { return StackSizesSection; } + // ELF specific sections. MCSection *getDataRelROSection() const { return DataRelROSection; } const MCSection *getMergeableConst4Section() const { diff --git a/include/llvm/MC/MCRegisterInfo.h b/include/llvm/MC/MCRegisterInfo.h index de98abe0dc46c..c57c9ef709dad 100644 --- a/include/llvm/MC/MCRegisterInfo.h +++ b/include/llvm/MC/MCRegisterInfo.h @@ -407,6 +407,15 @@ class MCRegisterInfo { /// \brief Map a dwarf register back to a target register. int getLLVMRegNum(unsigned RegNum, bool isEH) const; + /// \brief Map a DWARF EH register back to a target register (same as + /// getLLVMRegNum(RegNum, true)) but return -1 if there is no mapping, + /// rather than asserting that there must be one. + int getLLVMRegNumFromEH(unsigned RegNum) const; + + /// \brief Map a target EH register number to an equivalent DWARF register + /// number. + int getDwarfRegNumFromDwarfEHRegNum(unsigned RegNum) const; + /// \brief Map a target register to an equivalent SEH register /// number. Returns LLVM register number if there is no equivalent value. int getSEHRegNum(unsigned RegNum) const; diff --git a/include/llvm/MC/MCSymbolWasm.h b/include/llvm/MC/MCSymbolWasm.h index 9bae6c582faa3..309ebf96d1b0a 100644 --- a/include/llvm/MC/MCSymbolWasm.h +++ b/include/llvm/MC/MCSymbolWasm.h @@ -18,6 +18,7 @@ class MCSymbolWasm : public MCSymbol { private: bool IsFunction = false; bool IsWeak = false; + bool IsHidden = false; std::string ModuleName; SmallVector Returns; SmallVector Params; @@ -45,6 +46,9 @@ class MCSymbolWasm : public MCSymbol { bool isWeak() const { return IsWeak; } void setWeak(bool isWeak) { IsWeak = isWeak; } + bool isHidden() const { return IsHidden; } + void setHidden(bool isHidden) { IsHidden = isHidden; } + const StringRef getModuleName() const { return ModuleName; } const SmallVector &getReturns() const { diff --git a/include/llvm/Object/Wasm.h b/include/llvm/Object/Wasm.h index e138faeed3423..504f1b4903140 100644 --- a/include/llvm/Object/Wasm.h +++ b/include/llvm/Object/Wasm.h @@ -81,6 +81,14 @@ class WasmSymbol { return Flags & wasm::WASM_SYMBOL_BINDING_MASK; } + bool isHidden() const { + return getVisibility() == wasm::WASM_SYMBOL_VISIBILITY_HIDDEN; + } + + unsigned getVisibility() const { + return Flags & wasm::WASM_SYMBOL_VISIBILITY_MASK; + } + void print(raw_ostream &Out) const { Out << "Name=" << Name << ", Type=" << static_cast(Type) << ", Flags=" << Flags << " ElemIndex=" << ElementIndex diff --git a/include/llvm/ObjectYAML/CodeViewYAMLTypes.h b/include/llvm/ObjectYAML/CodeViewYAMLTypes.h index 8723077502d97..1128ac989c115 100644 --- a/include/llvm/ObjectYAML/CodeViewYAMLTypes.h +++ b/include/llvm/ObjectYAML/CodeViewYAMLTypes.h @@ -27,7 +27,7 @@ namespace llvm { namespace codeview { -class TypeTableBuilder; +class AppendingTypeTableBuilder; } namespace CodeViewYAML { @@ -47,7 +47,7 @@ struct LeafRecord { std::shared_ptr Leaf; codeview::CVType - toCodeViewRecord(codeview::TypeTableBuilder &Serializer) const; + toCodeViewRecord(codeview::AppendingTypeTableBuilder &Serializer) const; static Expected fromCodeViewRecord(codeview::CVType Type); }; diff --git a/include/llvm/Pass.h b/include/llvm/Pass.h index ff64117035091..a29b3771abb46 100644 --- a/include/llvm/Pass.h +++ b/include/llvm/Pass.h @@ -361,6 +361,12 @@ extern bool TimePassesIsEnabled; // @brief Tells if the function IR should be printed by PrinterPass. extern bool isFunctionInPrintList(StringRef FunctionName); +/// forcePrintModuleIR - returns true if IR printing passes should +// be printing module IR (even for local-pass printers e.g. function-pass) +// to provide more context, as enabled by debugging option -print-module-scope +// @brief Tells if IR printer should be printing module IR +extern bool forcePrintModuleIR(); + } // end namespace llvm // Include support files that contain important APIs commonly used by Passes, diff --git a/include/llvm/Target/GenericOpcodes.td b/include/llvm/Target/GenericOpcodes.td index b1cb3022fc1f1..3b2e8f2d08b87 100644 --- a/include/llvm/Target/GenericOpcodes.td +++ b/include/llvm/Target/GenericOpcodes.td @@ -16,9 +16,11 @@ // Unary ops. //------------------------------------------------------------------------------ +class GenericInstruction : StandardPseudoInstruction; + // Extend the underlying scalar type of an operation, leaving the high bits // unspecified. -def G_ANYEXT : Instruction { +def G_ANYEXT : GenericInstruction { let OutOperandList = (outs type0:$dst); let InOperandList = (ins type1:$src); let hasSideEffects = 0; @@ -26,7 +28,7 @@ def G_ANYEXT : Instruction { // Sign extend the underlying scalar type of an operation, copying the sign bit // into the newly-created space. -def G_SEXT : Instruction { +def G_SEXT : GenericInstruction { let OutOperandList = (outs type0:$dst); let InOperandList = (ins type1:$src); let hasSideEffects = 0; @@ -34,7 +36,7 @@ def G_SEXT : Instruction { // Zero extend the underlying scalar type of an operation, putting zero bits // into the newly-created space. -def G_ZEXT : Instruction { +def G_ZEXT : GenericInstruction { let OutOperandList = (outs type0:$dst); let InOperandList = (ins type1:$src); let hasSideEffects = 0; @@ -43,74 +45,74 @@ def G_ZEXT : Instruction { // Truncate the underlying scalar type of an operation. This is equivalent to // G_EXTRACT for scalar types, but acts elementwise on vectors. -def G_TRUNC : Instruction { +def G_TRUNC : GenericInstruction { let OutOperandList = (outs type0:$dst); let InOperandList = (ins type1:$src); let hasSideEffects = 0; } -def G_IMPLICIT_DEF : Instruction { +def G_IMPLICIT_DEF : GenericInstruction { let OutOperandList = (outs type0:$dst); let InOperandList = (ins); let hasSideEffects = 0; } -def G_PHI : Instruction { +def G_PHI : GenericInstruction { let OutOperandList = (outs type0:$dst); let InOperandList = (ins variable_ops); let hasSideEffects = 0; } -def G_FRAME_INDEX : Instruction { +def G_FRAME_INDEX : GenericInstruction { let OutOperandList = (outs type0:$dst); let InOperandList = (ins unknown:$src2); let hasSideEffects = 0; } -def G_GLOBAL_VALUE : Instruction { +def G_GLOBAL_VALUE : GenericInstruction { let OutOperandList = (outs type0:$dst); let InOperandList = (ins unknown:$src); let hasSideEffects = 0; } -def G_INTTOPTR : Instruction { +def G_INTTOPTR : GenericInstruction { let OutOperandList = (outs type0:$dst); let InOperandList = (ins type1:$src); let hasSideEffects = 0; } -def G_PTRTOINT : Instruction { +def G_PTRTOINT : GenericInstruction { let OutOperandList = (outs type0:$dst); let InOperandList = (ins type1:$src); let hasSideEffects = 0; } -def G_BITCAST : Instruction { +def G_BITCAST : GenericInstruction { let OutOperandList = (outs type0:$dst); let InOperandList = (ins type1:$src); let hasSideEffects = 0; } -def G_CONSTANT : Instruction { +def G_CONSTANT : GenericInstruction { let OutOperandList = (outs type0:$dst); let InOperandList = (ins unknown:$imm); let hasSideEffects = 0; } -def G_FCONSTANT : Instruction { +def G_FCONSTANT : GenericInstruction { let OutOperandList = (outs type0:$dst); let InOperandList = (ins unknown:$imm); let hasSideEffects = 0; } -def G_VASTART : Instruction { +def G_VASTART : GenericInstruction { let OutOperandList = (outs); let InOperandList = (ins type0:$list); let hasSideEffects = 0; let mayStore = 1; } -def G_VAARG : Instruction { +def G_VAARG : GenericInstruction { let OutOperandList = (outs type0:$val); let InOperandList = (ins type1:$list, unknown:$align); let hasSideEffects = 0; @@ -118,7 +120,7 @@ def G_VAARG : Instruction { let mayStore = 1; } -def G_BSWAP : Instruction { +def G_BSWAP : GenericInstruction { let OutOperandList = (outs type0:$dst); let InOperandList = (ins type0:$src); let hasSideEffects = 0; @@ -129,7 +131,7 @@ def G_BSWAP : Instruction { //------------------------------------------------------------------------------ // Generic addition. -def G_ADD : Instruction { +def G_ADD : GenericInstruction { let OutOperandList = (outs type0:$dst); let InOperandList = (ins type0:$src1, type0:$src2); let hasSideEffects = 0; @@ -137,7 +139,7 @@ def G_ADD : Instruction { } // Generic subtraction. -def G_SUB : Instruction { +def G_SUB : GenericInstruction { let OutOperandList = (outs type0:$dst); let InOperandList = (ins type0:$src1, type0:$src2); let hasSideEffects = 0; @@ -145,7 +147,7 @@ def G_SUB : Instruction { } // Generic multiplication. -def G_MUL : Instruction { +def G_MUL : GenericInstruction { let OutOperandList = (outs type0:$dst); let InOperandList = (ins type0:$src1, type0:$src2); let hasSideEffects = 0; @@ -153,7 +155,7 @@ def G_MUL : Instruction { } // Generic signed division. -def G_SDIV : Instruction { +def G_SDIV : GenericInstruction { let OutOperandList = (outs type0:$dst); let InOperandList = (ins type0:$src1, type0:$src2); let hasSideEffects = 0; @@ -161,7 +163,7 @@ def G_SDIV : Instruction { } // Generic unsigned division. -def G_UDIV : Instruction { +def G_UDIV : GenericInstruction { let OutOperandList = (outs type0:$dst); let InOperandList = (ins type0:$src1, type0:$src2); let hasSideEffects = 0; @@ -169,7 +171,7 @@ def G_UDIV : Instruction { } // Generic signed remainder. -def G_SREM : Instruction { +def G_SREM : GenericInstruction { let OutOperandList = (outs type0:$dst); let InOperandList = (ins type0:$src1, type0:$src2); let hasSideEffects = 0; @@ -177,7 +179,7 @@ def G_SREM : Instruction { } // Generic unsigned remainder. -def G_UREM : Instruction { +def G_UREM : GenericInstruction { let OutOperandList = (outs type0:$dst); let InOperandList = (ins type0:$src1, type0:$src2); let hasSideEffects = 0; @@ -185,7 +187,7 @@ def G_UREM : Instruction { } // Generic bitwise and. -def G_AND : Instruction { +def G_AND : GenericInstruction { let OutOperandList = (outs type0:$dst); let InOperandList = (ins type0:$src1, type0:$src2); let hasSideEffects = 0; @@ -193,7 +195,7 @@ def G_AND : Instruction { } // Generic bitwise or. -def G_OR : Instruction { +def G_OR : GenericInstruction { let OutOperandList = (outs type0:$dst); let InOperandList = (ins type0:$src1, type0:$src2); let hasSideEffects = 0; @@ -201,7 +203,7 @@ def G_OR : Instruction { } // Generic bitwise xor. -def G_XOR : Instruction { +def G_XOR : GenericInstruction { let OutOperandList = (outs type0:$dst); let InOperandList = (ins type0:$src1, type0:$src2); let hasSideEffects = 0; @@ -209,55 +211,55 @@ def G_XOR : Instruction { } // Generic left-shift. -def G_SHL : Instruction { +def G_SHL : GenericInstruction { let OutOperandList = (outs type0:$dst); let InOperandList = (ins type0:$src1, type0:$src2); let hasSideEffects = 0; } // Generic logical right-shift. -def G_LSHR : Instruction { +def G_LSHR : GenericInstruction { let OutOperandList = (outs type0:$dst); let InOperandList = (ins type0:$src1, type0:$src2); let hasSideEffects = 0; } // Generic arithmetic right-shift. -def G_ASHR : Instruction { +def G_ASHR : GenericInstruction { let OutOperandList = (outs type0:$dst); let InOperandList = (ins type0:$src1, type0:$src2); let hasSideEffects = 0; } // Generic integer comparison. -def G_ICMP : Instruction { +def G_ICMP : GenericInstruction { let OutOperandList = (outs type0:$dst); let InOperandList = (ins unknown:$tst, type1:$src1, type1:$src2); let hasSideEffects = 0; } // Generic floating-point comparison. -def G_FCMP : Instruction { +def G_FCMP : GenericInstruction { let OutOperandList = (outs type0:$dst); let InOperandList = (ins unknown:$tst, type1:$src1, type1:$src2); let hasSideEffects = 0; } // Generic select -def G_SELECT : Instruction { +def G_SELECT : GenericInstruction { let OutOperandList = (outs type0:$dst); let InOperandList = (ins type1:$tst, type0:$src1, type0:$src2); let hasSideEffects = 0; } // Generic pointer offset. -def G_GEP : Instruction { +def G_GEP : GenericInstruction { let OutOperandList = (outs type0:$dst); let InOperandList = (ins type0:$src1, type1:$src2); let hasSideEffects = 0; } -def G_PTR_MASK : Instruction { +def G_PTR_MASK : GenericInstruction { let OutOperandList = (outs type0:$dst); let InOperandList = (ins type0:$src, unknown:$bits); let hasSideEffects = 0; @@ -268,14 +270,14 @@ def G_PTR_MASK : Instruction { //------------------------------------------------------------------------------ // Generic unsigned addition consuming and producing a carry flag. -def G_UADDE : Instruction { +def G_UADDE : GenericInstruction { let OutOperandList = (outs type0:$dst, type1:$carry_out); let InOperandList = (ins type0:$src1, type0:$src2, type1:$carry_in); let hasSideEffects = 0; } // Generic signed addition producing a carry flag. -def G_SADDO : Instruction { +def G_SADDO : GenericInstruction { let OutOperandList = (outs type0:$dst, type1:$carry_out); let InOperandList = (ins type0:$src1, type0:$src2); let hasSideEffects = 0; @@ -283,21 +285,21 @@ def G_SADDO : Instruction { } // Generic unsigned subtraction consuming and producing a carry flag. -def G_USUBE : Instruction { +def G_USUBE : GenericInstruction { let OutOperandList = (outs type0:$dst, type1:$carry_out); let InOperandList = (ins type0:$src1, type0:$src2, type1:$carry_in); let hasSideEffects = 0; } // Generic unsigned subtraction producing a carry flag. -def G_SSUBO : Instruction { +def G_SSUBO : GenericInstruction { let OutOperandList = (outs type0:$dst, type1:$carry_out); let InOperandList = (ins type0:$src1, type0:$src2); let hasSideEffects = 0; } // Generic unsigned multiplication producing a carry flag. -def G_UMULO : Instruction { +def G_UMULO : GenericInstruction { let OutOperandList = (outs type0:$dst, type1:$carry_out); let InOperandList = (ins type0:$src1, type0:$src2); let hasSideEffects = 0; @@ -305,7 +307,7 @@ def G_UMULO : Instruction { } // Generic signed multiplication producing a carry flag. -def G_SMULO : Instruction { +def G_SMULO : GenericInstruction { let OutOperandList = (outs type0:$dst, type1:$carry_out); let InOperandList = (ins type0:$src1, type0:$src2); let hasSideEffects = 0; @@ -314,7 +316,7 @@ def G_SMULO : Instruction { // Multiply two numbers at twice the incoming bit width (unsigned) and return // the high half of the result. -def G_UMULH : Instruction { +def G_UMULH : GenericInstruction { let OutOperandList = (outs type0:$dst); let InOperandList = (ins type0:$src1, type0:$src2); let hasSideEffects = 0; @@ -323,7 +325,7 @@ def G_UMULH : Instruction { // Multiply two numbers at twice the incoming bit width (signed) and return // the high half of the result. -def G_SMULH : Instruction { +def G_SMULH : GenericInstruction { let OutOperandList = (outs type0:$dst); let InOperandList = (ins type0:$src1, type0:$src2); let hasSideEffects = 0; @@ -334,43 +336,43 @@ def G_SMULH : Instruction { // Floating Point Unary Ops. //------------------------------------------------------------------------------ -def G_FNEG : Instruction { +def G_FNEG : GenericInstruction { let OutOperandList = (outs type0:$dst); let InOperandList = (ins type0:$src); let hasSideEffects = 0; } -def G_FPEXT : Instruction { +def G_FPEXT : GenericInstruction { let OutOperandList = (outs type0:$dst); let InOperandList = (ins type1:$src); let hasSideEffects = 0; } -def G_FPTRUNC : Instruction { +def G_FPTRUNC : GenericInstruction { let OutOperandList = (outs type0:$dst); let InOperandList = (ins type1:$src); let hasSideEffects = 0; } -def G_FPTOSI : Instruction { +def G_FPTOSI : GenericInstruction { let OutOperandList = (outs type0:$dst); let InOperandList = (ins type1:$src); let hasSideEffects = 0; } -def G_FPTOUI : Instruction { +def G_FPTOUI : GenericInstruction { let OutOperandList = (outs type0:$dst); let InOperandList = (ins type1:$src); let hasSideEffects = 0; } -def G_SITOFP : Instruction { +def G_SITOFP : GenericInstruction { let OutOperandList = (outs type0:$dst); let InOperandList = (ins type1:$src); let hasSideEffects = 0; } -def G_UITOFP : Instruction { +def G_UITOFP : GenericInstruction { let OutOperandList = (outs type0:$dst); let InOperandList = (ins type1:$src); let hasSideEffects = 0; @@ -381,7 +383,7 @@ def G_UITOFP : Instruction { //------------------------------------------------------------------------------ // Generic FP addition. -def G_FADD : Instruction { +def G_FADD : GenericInstruction { let OutOperandList = (outs type0:$dst); let InOperandList = (ins type0:$src1, type0:$src2); let hasSideEffects = 0; @@ -389,7 +391,7 @@ def G_FADD : Instruction { } // Generic FP subtraction. -def G_FSUB : Instruction { +def G_FSUB : GenericInstruction { let OutOperandList = (outs type0:$dst); let InOperandList = (ins type0:$src1, type0:$src2); let hasSideEffects = 0; @@ -397,7 +399,7 @@ def G_FSUB : Instruction { } // Generic FP multiplication. -def G_FMUL : Instruction { +def G_FMUL : GenericInstruction { let OutOperandList = (outs type0:$dst); let InOperandList = (ins type0:$src1, type0:$src2); let hasSideEffects = 0; @@ -406,7 +408,7 @@ def G_FMUL : Instruction { // Generic fused multiply-add instruction. // Behaves like llvm fma intrinsic ie src1 * src2 + src3 -def G_FMA : Instruction { +def G_FMA : GenericInstruction { let OutOperandList = (outs type0:$dst); let InOperandList = (ins type0:$src1, type0:$src2, type0:$src3); let hasSideEffects = 0; @@ -414,49 +416,49 @@ def G_FMA : Instruction { } // Generic FP division. -def G_FDIV : Instruction { +def G_FDIV : GenericInstruction { let OutOperandList = (outs type0:$dst); let InOperandList = (ins type0:$src1, type0:$src2); let hasSideEffects = 0; } // Generic FP remainder. -def G_FREM : Instruction { +def G_FREM : GenericInstruction { let OutOperandList = (outs type0:$dst); let InOperandList = (ins type0:$src1, type0:$src2); let hasSideEffects = 0; } // Floating point exponentiation. -def G_FPOW : Instruction { +def G_FPOW : GenericInstruction { let OutOperandList = (outs type0:$dst); let InOperandList = (ins type0:$src1, type0:$src2); let hasSideEffects = 0; } // Floating point base-e exponential of a value. -def G_FEXP : Instruction { +def G_FEXP : GenericInstruction { let OutOperandList = (outs type0:$dst); let InOperandList = (ins type0:$src1); let hasSideEffects = 0; } // Floating point base-2 exponential of a value. -def G_FEXP2 : Instruction { +def G_FEXP2 : GenericInstruction { let OutOperandList = (outs type0:$dst); let InOperandList = (ins type0:$src1); let hasSideEffects = 0; } // Floating point base-2 logarithm of a value. -def G_FLOG : Instruction { +def G_FLOG : GenericInstruction { let OutOperandList = (outs type0:$dst); let InOperandList = (ins type0:$src1); let hasSideEffects = 0; } // Floating point base-2 logarithm of a value. -def G_FLOG2 : Instruction { +def G_FLOG2 : GenericInstruction { let OutOperandList = (outs type0:$dst); let InOperandList = (ins type0:$src1); let hasSideEffects = 0; @@ -467,7 +469,7 @@ def G_FLOG2 : Instruction { //------------------------------------------------------------------------------ // Generic load. Expects a MachineMemOperand in addition to explicit operands. -def G_LOAD : Instruction { +def G_LOAD : GenericInstruction { let OutOperandList = (outs type0:$dst); let InOperandList = (ins ptype1:$addr); let hasSideEffects = 0; @@ -475,16 +477,48 @@ def G_LOAD : Instruction { } // Generic store. Expects a MachineMemOperand in addition to explicit operands. -def G_STORE : Instruction { +def G_STORE : GenericInstruction { + let OutOperandList = (outs); + let InOperandList = (ins type0:$src, ptype1:$addr); + let hasSideEffects = 0; + let mayStore = 1; +} + +// Generic atomic load. Expects a MachineMemOperand in addition to explicit +// operands. Technically, we could have handled this as a G_LOAD, however we +// decided to keep it separate on the basis that atomic loads tend to have +// very different handling to non-atomic loads. +def G_ATOMIC_LOAD : GenericInstruction { + let OutOperandList = (outs type0:$dst); + let InOperandList = (ins ptype1:$addr); + let hasSideEffects = 0; + let mayLoad = 1; +} + +// Generic atomic store. Expects a MachineMemOperand in addition to explicit +// operands. Technically, we could have handled this as a G_STORE, however we +// decided to keep it separate on the basis that atomic stores tend to have +// very different handling to non-atomic stores. +def G_ATOMIC_STORE : GenericInstruction { let OutOperandList = (outs); let InOperandList = (ins type0:$src, ptype1:$addr); let hasSideEffects = 0; let mayStore = 1; } +// Generic atomic cmpxchg with internal success check. Expects a +// MachineMemOperand in addition to explicit operands. +def G_ATOMIC_CMPXCHG_WITH_SUCCESS : GenericInstruction { + let OutOperandList = (outs type0:$oldval, type1:$success); + let InOperandList = (ins type2:$addr, type0:$cmpval, type0:$newval); + let hasSideEffects = 0; + let mayLoad = 1; + let mayStore = 1; +} + // Generic atomic cmpxchg. Expects a MachineMemOperand in addition to explicit // operands. -def G_ATOMIC_CMPXCHG : Instruction { +def G_ATOMIC_CMPXCHG : GenericInstruction { let OutOperandList = (outs type0:$oldval); let InOperandList = (ins ptype1:$addr, type0:$cmpval, type0:$newval); let hasSideEffects = 0; @@ -494,7 +528,7 @@ def G_ATOMIC_CMPXCHG : Instruction { // Generic atomicrmw. Expects a MachineMemOperand in addition to explicit // operands. -class G_ATOMICRMW_OP : Instruction { +class G_ATOMICRMW_OP : GenericInstruction { let OutOperandList = (outs type0:$oldval); let InOperandList = (ins ptype1:$addr, type0:$val); let hasSideEffects = 0; @@ -502,83 +536,17 @@ class G_ATOMICRMW_OP : Instruction { let mayStore = 1; } -def G_ATOMICRMW_XCHG : G_ATOMICRMW_OP { - // FIXME: This include is surrounded by a 'let mayLoad = 0, mayStore = 0 in {}' - // block which overrides the value inherited from G_ATOMICRMW_OP. Work - // around this for now. See http://reviews.llvm.org/D40096 - let mayLoad = 1; - let mayStore = 1; -} -def G_ATOMICRMW_ADD : G_ATOMICRMW_OP { - // FIXME: This include is surrounded by a 'let mayLoad = 0, mayStore = 0 in {}' - // block which overrides the value inherited from G_ATOMICRMW_OP. Work - // around this for now. See http://reviews.llvm.org/D40096 - let mayLoad = 1; - let mayStore = 1; -} -def G_ATOMICRMW_SUB : G_ATOMICRMW_OP { - // FIXME: This include is surrounded by a 'let mayLoad = 0, mayStore = 0 in {}' - // block which overrides the value inherited from G_ATOMICRMW_OP. Work - // around this for now. See http://reviews.llvm.org/D40096 - let mayLoad = 1; - let mayStore = 1; -} -def G_ATOMICRMW_AND : G_ATOMICRMW_OP { - // FIXME: This include is surrounded by a 'let mayLoad = 0, mayStore = 0 in {}' - // block which overrides the value inherited from G_ATOMICRMW_OP. Work - // around this for now. See http://reviews.llvm.org/D40096 - let mayLoad = 1; - let mayStore = 1; -} -def G_ATOMICRMW_NAND : G_ATOMICRMW_OP { - // FIXME: This include is surrounded by a 'let mayLoad = 0, mayStore = 0 in {}' - // block which overrides the value inherited from G_ATOMICRMW_OP. Work - // around this for now. See http://reviews.llvm.org/D40096 - let mayLoad = 1; - let mayStore = 1; -} -def G_ATOMICRMW_OR : G_ATOMICRMW_OP { - // FIXME: This include is surrounded by a 'let mayLoad = 0, mayStore = 0 in {}' - // block which overrides the value inherited from G_ATOMICRMW_OP. Work - // around this for now. See http://reviews.llvm.org/D40096 - let mayLoad = 1; - let mayStore = 1; -} -def G_ATOMICRMW_XOR : G_ATOMICRMW_OP { - // FIXME: This include is surrounded by a 'let mayLoad = 0, mayStore = 0 in {}' - // block which overrides the value inherited from G_ATOMICRMW_OP. Work - // around this for now. See http://reviews.llvm.org/D40096 - let mayLoad = 1; - let mayStore = 1; -} -def G_ATOMICRMW_MAX : G_ATOMICRMW_OP { - // FIXME: This include is surrounded by a 'let mayLoad = 0, mayStore = 0 in {}' - // block which overrides the value inherited from G_ATOMICRMW_OP. Work - // around this for now. See http://reviews.llvm.org/D40096 - let mayLoad = 1; - let mayStore = 1; -} -def G_ATOMICRMW_MIN : G_ATOMICRMW_OP { - // FIXME: This include is surrounded by a 'let mayLoad = 0, mayStore = 0 in {}' - // block which overrides the value inherited from G_ATOMICRMW_OP. Work - // around this for now. See http://reviews.llvm.org/D40096 - let mayLoad = 1; - let mayStore = 1; -} -def G_ATOMICRMW_UMAX : G_ATOMICRMW_OP { - // FIXME: This include is surrounded by a 'let mayLoad = 0, mayStore = 0 in {}' - // block which overrides the value inherited from G_ATOMICRMW_OP. Work - // around this for now. See http://reviews.llvm.org/D40096 - let mayLoad = 1; - let mayStore = 1; -} -def G_ATOMICRMW_UMIN : G_ATOMICRMW_OP { - // FIXME: This include is surrounded by a 'let mayLoad = 0, mayStore = 0 in {}' - // block which overrides the value inherited from G_ATOMICRMW_OP. Work - // around this for now. See http://reviews.llvm.org/D40096 - let mayLoad = 1; - let mayStore = 1; -} +def G_ATOMICRMW_XCHG : G_ATOMICRMW_OP; +def G_ATOMICRMW_ADD : G_ATOMICRMW_OP; +def G_ATOMICRMW_SUB : G_ATOMICRMW_OP; +def G_ATOMICRMW_AND : G_ATOMICRMW_OP; +def G_ATOMICRMW_NAND : G_ATOMICRMW_OP; +def G_ATOMICRMW_OR : G_ATOMICRMW_OP; +def G_ATOMICRMW_XOR : G_ATOMICRMW_OP; +def G_ATOMICRMW_MAX : G_ATOMICRMW_OP; +def G_ATOMICRMW_MIN : G_ATOMICRMW_OP; +def G_ATOMICRMW_UMAX : G_ATOMICRMW_OP; +def G_ATOMICRMW_UMIN : G_ATOMICRMW_OP; //------------------------------------------------------------------------------ // Variadic ops @@ -587,7 +555,7 @@ def G_ATOMICRMW_UMIN : G_ATOMICRMW_OP { // Extract a register of the specified size, starting from the block given by // index. This will almost certainly be mapped to sub-register COPYs after // register banks have been selected. -def G_EXTRACT : Instruction { +def G_EXTRACT : GenericInstruction { let OutOperandList = (outs type0:$res); let InOperandList = (ins type1:$src, unknown:$offset); let hasSideEffects = 0; @@ -596,35 +564,35 @@ def G_EXTRACT : Instruction { // Extract multiple registers specified size, starting from blocks given by // indexes. This will almost certainly be mapped to sub-register COPYs after // register banks have been selected. -def G_UNMERGE_VALUES : Instruction { - let OutOperandList = (outs); - let InOperandList = (ins variable_ops); +def G_UNMERGE_VALUES : GenericInstruction { + let OutOperandList = (outs type0:$dst0, variable_ops); + let InOperandList = (ins type1:$src); let hasSideEffects = 0; } // Insert a smaller register into a larger one at the specified bit-index. -def G_INSERT : Instruction { +def G_INSERT : GenericInstruction { let OutOperandList = (outs type0:$dst); let InOperandList = (ins type0:$src, type1:$op, unknown:$offset); let hasSideEffects = 0; } -/// Concatenante multiple registers of the same size into a wider register. -def G_MERGE_VALUES : Instruction { +/// Concatenate multiple registers of the same size into a wider register. +def G_MERGE_VALUES : GenericInstruction { let OutOperandList = (outs type0:$dst); - let InOperandList = (ins variable_ops); + let InOperandList = (ins type1:$src0, variable_ops); let hasSideEffects = 0; } // Intrinsic without side effects. -def G_INTRINSIC : Instruction { +def G_INTRINSIC : GenericInstruction { let OutOperandList = (outs); let InOperandList = (ins unknown:$intrin, variable_ops); let hasSideEffects = 0; } // Intrinsic with side effects. -def G_INTRINSIC_W_SIDE_EFFECTS : Instruction { +def G_INTRINSIC_W_SIDE_EFFECTS : GenericInstruction { let OutOperandList = (outs); let InOperandList = (ins unknown:$intrin, variable_ops); let hasSideEffects = 1; @@ -637,7 +605,7 @@ def G_INTRINSIC_W_SIDE_EFFECTS : Instruction { //------------------------------------------------------------------------------ // Generic unconditional branch. -def G_BR : Instruction { +def G_BR : GenericInstruction { let OutOperandList = (outs); let InOperandList = (ins unknown:$src1); let hasSideEffects = 0; @@ -647,7 +615,7 @@ def G_BR : Instruction { } // Generic conditional branch. -def G_BRCOND : Instruction { +def G_BRCOND : GenericInstruction { let OutOperandList = (outs); let InOperandList = (ins type0:$tst, unknown:$truebb); let hasSideEffects = 0; @@ -656,7 +624,7 @@ def G_BRCOND : Instruction { } // Generic indirect branch. -def G_BRINDIRECT : Instruction { +def G_BRINDIRECT : GenericInstruction { let OutOperandList = (outs); let InOperandList = (ins type0:$src1); let hasSideEffects = 0; @@ -669,21 +637,21 @@ def G_BRINDIRECT : Instruction { //------------------------------------------------------------------------------ // Generic insertelement. -def G_INSERT_VECTOR_ELT : Instruction { +def G_INSERT_VECTOR_ELT : GenericInstruction { let OutOperandList = (outs type0:$dst); let InOperandList = (ins type0:$src, type1:$elt, type2:$idx); let hasSideEffects = 0; } // Generic extractelement. -def G_EXTRACT_VECTOR_ELT : Instruction { +def G_EXTRACT_VECTOR_ELT : GenericInstruction { let OutOperandList = (outs type0:$dst); let InOperandList = (ins type1:$src, type2:$idx); let hasSideEffects = 0; } // Generic shufflevector. -def G_SHUFFLE_VECTOR: Instruction { +def G_SHUFFLE_VECTOR: GenericInstruction { let OutOperandList = (outs type0:$dst); let InOperandList = (ins type1:$v1, type1:$v2, type2:$mask); let hasSideEffects = 0; diff --git a/include/llvm/Target/GlobalISel/SelectionDAGCompat.td b/include/llvm/Target/GlobalISel/SelectionDAGCompat.td index 575f228cd7733..71c8ce6d20c8e 100644 --- a/include/llvm/Target/GlobalISel/SelectionDAGCompat.td +++ b/include/llvm/Target/GlobalISel/SelectionDAGCompat.td @@ -23,11 +23,6 @@ class GINodeEquiv { Instruction I = i; SDNode Node = node; - - // SelectionDAG has separate nodes for atomic and non-atomic memory operations - // (ISD::LOAD, ISD::ATOMIC_LOAD, ISD::STORE, ISD::ATOMIC_STORE) but GlobalISel - // stores this information in the MachineMemoryOperand. - bit CheckMMOIsNonAtomic = 0; } // These are defined in the same order as the G_* instructions. @@ -80,19 +75,16 @@ def : GINodeEquiv; // Broadly speaking G_LOAD is equivalent to ISD::LOAD but there are some // complications that tablegen must take care of. For example, Predicates such // as isSignExtLoad require that this is not a perfect 1:1 mapping since a -// sign-extending load is (G_SEXT (G_LOAD x)) in GlobalISel. Additionally, -// G_LOAD handles both atomic and non-atomic loads where as SelectionDAG had -// separate nodes for them. This GINodeEquiv maps the non-atomic loads to -// G_LOAD with a non-atomic MachineMemOperand. -def : GINodeEquiv { let CheckMMOIsNonAtomic = 1; } +// sign-extending load is (G_SEXT (G_LOAD x)) in GlobalISel. +def : GINodeEquiv; // Broadly speaking G_STORE is equivalent to ISD::STORE but there are some // complications that tablegen must take care of. For example, predicates such // as isTruncStore require that this is not a perfect 1:1 mapping since a -// truncating store is (G_STORE (G_TRUNCATE x)) in GlobalISel. Additionally, -// G_STORE handles both atomic and non-atomic stores where as SelectionDAG had -// separate nodes for them. This GINodeEquiv maps the non-atomic stores to -// G_STORE with a non-atomic MachineMemOperand. -def : GINodeEquiv { let CheckMMOIsNonAtomic = 1; } +// truncating store is (G_STORE (G_TRUNCATE x)) in GlobalISel. +def : GINodeEquiv; + +def : GINodeEquiv; +def : GINodeEquiv; def : GINodeEquiv; def : GINodeEquiv; diff --git a/include/llvm/Target/Target.td b/include/llvm/Target/Target.td index 86fa3c03fb501..4b95e2065bc51 100644 --- a/include/llvm/Target/Target.td +++ b/include/llvm/Target/Target.td @@ -897,21 +897,27 @@ class InstrInfo { // Ensure mayLoad and mayStore have a default value, so as not to break // targets that set guessInstructionProperties=0. Any local definition of // mayLoad/mayStore takes precedence over these default values. -let mayLoad = 0, mayStore = 0, isCodeGenOnly = 1, isPseudo = 1, - hasNoSchedulingInfo = 1, Namespace = "TargetOpcode" in { -def PHI : Instruction { +class StandardPseudoInstruction : Instruction { + let mayLoad = 0; + let mayStore = 0; + let isCodeGenOnly = 1; + let isPseudo = 1; + let hasNoSchedulingInfo = 1; + let Namespace = "TargetOpcode"; +} +def PHI : StandardPseudoInstruction { let OutOperandList = (outs unknown:$dst); let InOperandList = (ins variable_ops); let AsmString = "PHINODE"; let hasSideEffects = 0; } -def INLINEASM : Instruction { +def INLINEASM : StandardPseudoInstruction { let OutOperandList = (outs); let InOperandList = (ins variable_ops); let AsmString = ""; let hasSideEffects = 0; // Note side effect is encoded in an operand. } -def CFI_INSTRUCTION : Instruction { +def CFI_INSTRUCTION : StandardPseudoInstruction { let OutOperandList = (outs); let InOperandList = (ins i32imm:$id); let AsmString = ""; @@ -919,7 +925,7 @@ def CFI_INSTRUCTION : Instruction { let hasSideEffects = 0; let isNotDuplicable = 1; } -def EH_LABEL : Instruction { +def EH_LABEL : StandardPseudoInstruction { let OutOperandList = (outs); let InOperandList = (ins i32imm:$id); let AsmString = ""; @@ -927,7 +933,7 @@ def EH_LABEL : Instruction { let hasSideEffects = 0; let isNotDuplicable = 1; } -def GC_LABEL : Instruction { +def GC_LABEL : StandardPseudoInstruction { let OutOperandList = (outs); let InOperandList = (ins i32imm:$id); let AsmString = ""; @@ -935,7 +941,7 @@ def GC_LABEL : Instruction { let hasSideEffects = 0; let isNotDuplicable = 1; } -def ANNOTATION_LABEL : Instruction { +def ANNOTATION_LABEL : StandardPseudoInstruction { let OutOperandList = (outs); let InOperandList = (ins i32imm:$id); let AsmString = ""; @@ -943,26 +949,26 @@ def ANNOTATION_LABEL : Instruction { let hasSideEffects = 0; let isNotDuplicable = 1; } -def KILL : Instruction { +def KILL : StandardPseudoInstruction { let OutOperandList = (outs); let InOperandList = (ins variable_ops); let AsmString = ""; let hasSideEffects = 0; } -def EXTRACT_SUBREG : Instruction { +def EXTRACT_SUBREG : StandardPseudoInstruction { let OutOperandList = (outs unknown:$dst); let InOperandList = (ins unknown:$supersrc, i32imm:$subidx); let AsmString = ""; let hasSideEffects = 0; } -def INSERT_SUBREG : Instruction { +def INSERT_SUBREG : StandardPseudoInstruction { let OutOperandList = (outs unknown:$dst); let InOperandList = (ins unknown:$supersrc, unknown:$subsrc, i32imm:$subidx); let AsmString = ""; let hasSideEffects = 0; let Constraints = "$supersrc = $dst"; } -def IMPLICIT_DEF : Instruction { +def IMPLICIT_DEF : StandardPseudoInstruction { let OutOperandList = (outs unknown:$dst); let InOperandList = (ins); let AsmString = ""; @@ -970,33 +976,33 @@ def IMPLICIT_DEF : Instruction { let isReMaterializable = 1; let isAsCheapAsAMove = 1; } -def SUBREG_TO_REG : Instruction { +def SUBREG_TO_REG : StandardPseudoInstruction { let OutOperandList = (outs unknown:$dst); let InOperandList = (ins unknown:$implsrc, unknown:$subsrc, i32imm:$subidx); let AsmString = ""; let hasSideEffects = 0; } -def COPY_TO_REGCLASS : Instruction { +def COPY_TO_REGCLASS : StandardPseudoInstruction { let OutOperandList = (outs unknown:$dst); let InOperandList = (ins unknown:$src, i32imm:$regclass); let AsmString = ""; let hasSideEffects = 0; let isAsCheapAsAMove = 1; } -def DBG_VALUE : Instruction { +def DBG_VALUE : StandardPseudoInstruction { let OutOperandList = (outs); let InOperandList = (ins variable_ops); let AsmString = "DBG_VALUE"; let hasSideEffects = 0; } -def REG_SEQUENCE : Instruction { +def REG_SEQUENCE : StandardPseudoInstruction { let OutOperandList = (outs unknown:$dst); let InOperandList = (ins unknown:$supersrc, variable_ops); let AsmString = ""; let hasSideEffects = 0; let isAsCheapAsAMove = 1; } -def COPY : Instruction { +def COPY : StandardPseudoInstruction { let OutOperandList = (outs unknown:$dst); let InOperandList = (ins unknown:$src); let AsmString = ""; @@ -1004,25 +1010,25 @@ def COPY : Instruction { let isAsCheapAsAMove = 1; let hasNoSchedulingInfo = 0; } -def BUNDLE : Instruction { +def BUNDLE : StandardPseudoInstruction { let OutOperandList = (outs); let InOperandList = (ins variable_ops); let AsmString = "BUNDLE"; let hasSideEffects = 1; } -def LIFETIME_START : Instruction { +def LIFETIME_START : StandardPseudoInstruction { let OutOperandList = (outs); let InOperandList = (ins i32imm:$id); let AsmString = "LIFETIME_START"; let hasSideEffects = 0; } -def LIFETIME_END : Instruction { +def LIFETIME_END : StandardPseudoInstruction { let OutOperandList = (outs); let InOperandList = (ins i32imm:$id); let AsmString = "LIFETIME_END"; let hasSideEffects = 0; } -def STACKMAP : Instruction { +def STACKMAP : StandardPseudoInstruction { let OutOperandList = (outs); let InOperandList = (ins i64imm:$id, i32imm:$nbytes, variable_ops); let hasSideEffects = 1; @@ -1030,7 +1036,7 @@ def STACKMAP : Instruction { let mayLoad = 1; let usesCustomInserter = 1; } -def PATCHPOINT : Instruction { +def PATCHPOINT : StandardPseudoInstruction { let OutOperandList = (outs unknown:$dst); let InOperandList = (ins i64imm:$id, i32imm:$nbytes, unknown:$callee, i32imm:$nargs, i32imm:$cc, variable_ops); @@ -1039,7 +1045,7 @@ def PATCHPOINT : Instruction { let mayLoad = 1; let usesCustomInserter = 1; } -def STATEPOINT : Instruction { +def STATEPOINT : StandardPseudoInstruction { let OutOperandList = (outs); let InOperandList = (ins variable_ops); let usesCustomInserter = 1; @@ -1048,7 +1054,7 @@ def STATEPOINT : Instruction { let hasSideEffects = 1; let isCall = 1; } -def LOAD_STACK_GUARD : Instruction { +def LOAD_STACK_GUARD : StandardPseudoInstruction { let OutOperandList = (outs ptr_rc:$dst); let InOperandList = (ins); let mayLoad = 1; @@ -1056,7 +1062,7 @@ def LOAD_STACK_GUARD : Instruction { let hasSideEffects = 0; bit isPseudo = 1; } -def LOCAL_ESCAPE : Instruction { +def LOCAL_ESCAPE : StandardPseudoInstruction { // This instruction is really just a label. It has to be part of the chain so // that it doesn't get dropped from the DAG, but it produces nothing and has // no side effects. @@ -1065,7 +1071,7 @@ def LOCAL_ESCAPE : Instruction { let hasSideEffects = 0; let hasCtrlDep = 1; } -def FAULTING_OP : Instruction { +def FAULTING_OP : StandardPseudoInstruction { let OutOperandList = (outs unknown:$dst); let InOperandList = (ins variable_ops); let usesCustomInserter = 1; @@ -1075,7 +1081,7 @@ def FAULTING_OP : Instruction { let isTerminator = 1; let isBranch = 1; } -def PATCHABLE_OP : Instruction { +def PATCHABLE_OP : StandardPseudoInstruction { let OutOperandList = (outs unknown:$dst); let InOperandList = (ins variable_ops); let usesCustomInserter = 1; @@ -1083,14 +1089,14 @@ def PATCHABLE_OP : Instruction { let mayStore = 1; let hasSideEffects = 1; } -def PATCHABLE_FUNCTION_ENTER : Instruction { +def PATCHABLE_FUNCTION_ENTER : StandardPseudoInstruction { let OutOperandList = (outs); let InOperandList = (ins); let AsmString = "# XRay Function Enter."; let usesCustomInserter = 1; let hasSideEffects = 0; } -def PATCHABLE_RET : Instruction { +def PATCHABLE_RET : StandardPseudoInstruction { let OutOperandList = (outs unknown:$dst); let InOperandList = (ins variable_ops); let AsmString = "# XRay Function Patchable RET."; @@ -1099,7 +1105,7 @@ def PATCHABLE_RET : Instruction { let isTerminator = 1; let isReturn = 1; } -def PATCHABLE_FUNCTION_EXIT : Instruction { +def PATCHABLE_FUNCTION_EXIT : StandardPseudoInstruction { let OutOperandList = (outs); let InOperandList = (ins); let AsmString = "# XRay Function Exit."; @@ -1107,7 +1113,7 @@ def PATCHABLE_FUNCTION_EXIT : Instruction { let hasSideEffects = 0; // FIXME: is this correct? let isReturn = 0; // Original return instruction will follow } -def PATCHABLE_TAIL_CALL : Instruction { +def PATCHABLE_TAIL_CALL : StandardPseudoInstruction { let OutOperandList = (outs unknown:$dst); let InOperandList = (ins variable_ops); let AsmString = "# XRay Tail Call Exit."; @@ -1115,7 +1121,7 @@ def PATCHABLE_TAIL_CALL : Instruction { let hasSideEffects = 1; let isReturn = 1; } -def PATCHABLE_EVENT_CALL : Instruction { +def PATCHABLE_EVENT_CALL : StandardPseudoInstruction { let OutOperandList = (outs); let InOperandList = (ins ptr_rc:$event, i8imm:$size); let AsmString = "# XRay Custom Event Log."; @@ -1125,7 +1131,7 @@ def PATCHABLE_EVENT_CALL : Instruction { let mayStore = 1; let hasSideEffects = 1; } -def FENTRY_CALL : Instruction { +def FENTRY_CALL : StandardPseudoInstruction { let OutOperandList = (outs unknown:$dst); let InOperandList = (ins variable_ops); let AsmString = "# FEntry call"; @@ -1138,8 +1144,6 @@ def FENTRY_CALL : Instruction { // Generic opcodes used in GlobalISel. include "llvm/Target/GenericOpcodes.td" -} - //===----------------------------------------------------------------------===// // AsmParser - This class can be implemented by targets that wish to implement // .s file parsing. diff --git a/include/llvm/Target/TargetOptions.h b/include/llvm/Target/TargetOptions.h index 5c2063880f8be..70fac7833f324 100644 --- a/include/llvm/Target/TargetOptions.h +++ b/include/llvm/Target/TargetOptions.h @@ -108,7 +108,7 @@ namespace llvm { DisableIntegratedAS(false), RelaxELFRelocations(false), FunctionSections(false), DataSections(false), UniqueSectionNames(true), TrapUnreachable(false), EmulatedTLS(false), - EnableIPRA(false) {} + EnableIPRA(false), EmitStackSizeSection(false) {} /// PrintMachineCode - This flag is enabled when the -print-machineinstrs /// option is specified on the command line, and should enable debugging @@ -216,6 +216,9 @@ namespace llvm { /// This flag enables InterProcedural Register Allocation (IPRA). unsigned EnableIPRA : 1; + /// Emit section containing metadata on function stack sizes. + unsigned EmitStackSizeSection : 1; + /// FloatABIType - This setting is set by -float-abi=xxx option is specfied /// on the command line. This setting may either be Default, Soft, or Hard. /// Default selects the target's default behavior. Soft selects the ABI for diff --git a/include/llvm/Target/TargetSelectionDAG.td b/include/llvm/Target/TargetSelectionDAG.td index 98eaeda89c025..06caa21d288c4 100644 --- a/include/llvm/Target/TargetSelectionDAG.td +++ b/include/llvm/Target/TargetSelectionDAG.td @@ -689,6 +689,14 @@ class PatFrag(N)->getOrdering() == AtomicOrdering::SequentiallyConsistent bit IsAtomicOrderingSequentiallyConsistent = ?; + // isAcquireOrStronger(cast(N)->getOrdering()) + // !isAcquireOrStronger(cast(N)->getOrdering()) + bit IsAtomicOrderingAcquireOrStronger = ?; + + // isReleaseOrStronger(cast(N)->getOrdering()) + // !isReleaseOrStronger(cast(N)->getOrdering()) + bit IsAtomicOrderingReleaseOrStronger = ?; + // cast(N)->getMemoryVT() == MVT::; // cast(N)->getMemoryVT() == MVT::; ValueType MemoryVT = ?; diff --git a/include/llvm/Transforms/Utils/BasicBlockUtils.h b/include/llvm/Transforms/Utils/BasicBlockUtils.h index 88873a991d5de..d42c11f1d9f6f 100644 --- a/include/llvm/Transforms/Utils/BasicBlockUtils.h +++ b/include/llvm/Transforms/Utils/BasicBlockUtils.h @@ -283,6 +283,26 @@ void SplitBlockAndInsertIfThenElse(Value *Cond, Instruction *SplitBefore, Value *GetIfCondition(BasicBlock *BB, BasicBlock *&IfTrue, BasicBlock *&IfFalse); +// Split critical edges where the source of the edge is an indirectbr +// instruction. This isn't always possible, but we can handle some easy cases. +// This is useful because MI is unable to split such critical edges, +// which means it will not be able to sink instructions along those edges. +// This is especially painful for indirect branches with many successors, where +// we end up having to prepare all outgoing values in the origin block. +// +// Our normal algorithm for splitting critical edges requires us to update +// the outgoing edges of the edge origin block, but for an indirectbr this +// is hard, since it would require finding and updating the block addresses +// the indirect branch uses. But if a block only has a single indirectbr +// predecessor, with the others being regular branches, we can do it in a +// different way. +// Say we have A -> D, B -> D, I -> D where only I -> D is an indirectbr. +// We can split D into D0 and D1, where D0 contains only the PHIs from D, +// and D1 is the D block body. We can then duplicate D0 as D0A and D0B, and +// create the following structure: +// A -> D0A, B -> D0A, I -> D0B, D0A -> D1, D0B -> D1 +bool SplitIndirectBrCriticalEdges(Function &F); + } // end namespace llvm #endif // LLVM_TRANSFORMS_UTILS_BASICBLOCKUTILS_H diff --git a/lib/Analysis/InlineCost.cpp b/lib/Analysis/InlineCost.cpp index b7fe884cc22c8..8fd74ccdc5049 100644 --- a/lib/Analysis/InlineCost.cpp +++ b/lib/Analysis/InlineCost.cpp @@ -1103,7 +1103,7 @@ bool CallAnalyzer::visitCallSite(CallSite CS) { } } - if (F == CS.getInstruction()->getParent()->getParent()) { + if (F == CS.getInstruction()->getFunction()) { // This flag will fully abort the analysis, so don't bother with anything // else. IsRecursiveCall = true; @@ -1559,14 +1559,14 @@ bool CallAnalyzer::analyzeCall(CallSite CS) { if (F.empty()) return true; - Function *Caller = CS.getInstruction()->getParent()->getParent(); + Function *Caller = CS.getInstruction()->getFunction(); // Check if the caller function is recursive itself. for (User *U : Caller->users()) { CallSite Site(U); if (!Site) continue; Instruction *I = Site.getInstruction(); - if (I->getParent()->getParent() == Caller) { + if (I->getFunction() == Caller) { IsCallerRecursive = true; break; } diff --git a/lib/Analysis/InstructionSimplify.cpp b/lib/Analysis/InstructionSimplify.cpp index 6bed2f3a9010d..145aa13dfc897 100644 --- a/lib/Analysis/InstructionSimplify.cpp +++ b/lib/Analysis/InstructionSimplify.cpp @@ -3378,6 +3378,28 @@ static Value *SimplifyFCmpInst(unsigned Predicate, Value *LHS, Value *RHS, default: break; } + } else if (C->isNegative()) { + assert(!C->isNaN() && "Unexpected NaN constant!"); + // TODO: We can catch more cases by using a range check rather than + // relying on CannotBeOrderedLessThanZero. + switch (Pred) { + case FCmpInst::FCMP_UGE: + case FCmpInst::FCMP_UGT: + case FCmpInst::FCMP_UNE: + // (X >= 0) implies (X > C) when (C < 0) + if (CannotBeOrderedLessThanZero(LHS, Q.TLI)) + return getTrue(RetTy); + break; + case FCmpInst::FCMP_OEQ: + case FCmpInst::FCMP_OLE: + case FCmpInst::FCMP_OLT: + // (X >= 0) implies !(X < C) when (C < 0) + if (CannotBeOrderedLessThanZero(LHS, Q.TLI)) + return getFalse(RetTy); + break; + default: + break; + } } } diff --git a/lib/Analysis/LoopInfo.cpp b/lib/Analysis/LoopInfo.cpp index 9a223df9394cc..9e54d60779a00 100644 --- a/lib/Analysis/LoopInfo.cpp +++ b/lib/Analysis/LoopInfo.cpp @@ -47,7 +47,7 @@ bool llvm::VerifyLoopInfo = false; #endif static cl::opt VerifyLoopInfoX("verify-loop-info", cl::location(VerifyLoopInfo), - cl::desc("Verify loop info (time consuming)")); + cl::Hidden, cl::desc("Verify loop info (time consuming)")); //===----------------------------------------------------------------------===// // Loop implementation @@ -731,6 +731,18 @@ PreservedAnalyses LoopPrinterPass::run(Function &F, } void llvm::printLoop(Loop &L, raw_ostream &OS, const std::string &Banner) { + + if (forcePrintModuleIR()) { + // handling -print-module-scope + OS << Banner << " (loop: "; + L.getHeader()->printAsOperand(OS, false); + OS << ")\n"; + + // printing whole module + OS << *L.getHeader()->getModule(); + return; + } + OS << Banner; auto *PreHeader = L.getLoopPreheader(); diff --git a/lib/Analysis/MemoryDependenceAnalysis.cpp b/lib/Analysis/MemoryDependenceAnalysis.cpp index ba90f1cf2fbd3..d41b6be75f21b 100644 --- a/lib/Analysis/MemoryDependenceAnalysis.cpp +++ b/lib/Analysis/MemoryDependenceAnalysis.cpp @@ -919,6 +919,14 @@ void MemoryDependenceResults::getNonLocalPointerDependency( Instruction *QueryInst, SmallVectorImpl &Result) { const MemoryLocation Loc = MemoryLocation::get(QueryInst); bool isLoad = isa(QueryInst); + return getNonLocalPointerDependencyFrom(QueryInst, Loc, isLoad, Result); +} + +void MemoryDependenceResults::getNonLocalPointerDependencyFrom( + Instruction *QueryInst, + const MemoryLocation &Loc, + bool isLoad, + SmallVectorImpl &Result) { BasicBlock *FromBB = QueryInst->getParent(); assert(FromBB); diff --git a/lib/Analysis/ObjCARCAnalysisUtils.cpp b/lib/Analysis/ObjCARCAnalysisUtils.cpp index e3e74aa249daf..55335f3a7cb09 100644 --- a/lib/Analysis/ObjCARCAnalysisUtils.cpp +++ b/lib/Analysis/ObjCARCAnalysisUtils.cpp @@ -21,8 +21,6 @@ using namespace llvm::objcarc; /// \brief A handy option to enable/disable all ARC Optimizations. bool llvm::objcarc::EnableARCOpts; -static cl::opt -EnableARCOptimizations("enable-objc-arc-opts", - cl::desc("enable/disable all ARC Optimizations"), - cl::location(EnableARCOpts), - cl::init(true)); +static cl::opt EnableARCOptimizations( + "enable-objc-arc-opts", cl::desc("enable/disable all ARC Optimizations"), + cl::location(EnableARCOpts), cl::init(true), cl::Hidden); diff --git a/lib/Analysis/OptimizationRemarkEmitter.cpp b/lib/Analysis/OptimizationRemarkEmitter.cpp index cd6a93668010d..4ff7611086eca 100644 --- a/lib/Analysis/OptimizationRemarkEmitter.cpp +++ b/lib/Analysis/OptimizationRemarkEmitter.cpp @@ -75,11 +75,10 @@ void OptimizationRemarkEmitter::emit( DiagnosticInfoOptimizationBase &OptDiagBase) { auto &OptDiag = cast(OptDiagBase); computeHotness(OptDiag); - // If a diagnostic has a hotness value, then only emit it if its hotness - // meets the threshold. - if (OptDiag.getHotness() && - *OptDiag.getHotness() < - F->getContext().getDiagnosticsHotnessThreshold()) { + + // Only emit it if its hotness meets the threshold. + if (OptDiag.getHotness().getValueOr(0) < + F->getContext().getDiagnosticsHotnessThreshold()) { return; } diff --git a/lib/Analysis/ScalarEvolution.cpp b/lib/Analysis/ScalarEvolution.cpp index 25e3b0c358564..8e60ca01c0276 100644 --- a/lib/Analysis/ScalarEvolution.cpp +++ b/lib/Analysis/ScalarEvolution.cpp @@ -153,11 +153,11 @@ MaxBruteForceIterations("scalar-evolution-max-iterations", cl::ReallyHidden, cl::init(100)); // FIXME: Enable this with EXPENSIVE_CHECKS when the test suite is clean. +static cl::opt VerifySCEV( + "verify-scev", cl::Hidden, + cl::desc("Verify ScalarEvolution's backedge taken counts (slow)")); static cl::opt -VerifySCEV("verify-scev", - cl::desc("Verify ScalarEvolution's backedge taken counts (slow)")); -static cl::opt - VerifySCEVMap("verify-scev-maps", + VerifySCEVMap("verify-scev-maps", cl::Hidden, cl::desc("Verify no dangling value in ScalarEvolution's " "ExprValueMap (slow)")); @@ -6414,11 +6414,9 @@ ScalarEvolution::getBackedgeTakenInfo(const Loop *L) { SmallVector Worklist; PushLoopPHIs(L, Worklist); - SmallPtrSet Visited; + SmallPtrSet Discovered; while (!Worklist.empty()) { Instruction *I = Worklist.pop_back_val(); - if (!Visited.insert(I).second) - continue; ValueExprMapType::iterator It = ValueExprMap.find_as(static_cast(I)); @@ -6433,13 +6431,37 @@ ScalarEvolution::getBackedgeTakenInfo(const Loop *L) { // own when it gets to that point. if (!isa(I) || !isa(Old)) { eraseValueFromMap(It->first); - forgetMemoizedResults(Old, false); + forgetMemoizedResults(Old); } if (PHINode *PN = dyn_cast(I)) ConstantEvolutionLoopExitValue.erase(PN); } - PushDefUseChildren(I, Worklist); + // Since we don't need to invalidate anything for correctness and we're + // only invalidating to make SCEV's results more precise, we get to stop + // early to avoid invalidating too much. This is especially important in + // cases like: + // + // %v = f(pn0, pn1) // pn0 and pn1 used through some other phi node + // loop0: + // %pn0 = phi + // ... + // loop1: + // %pn1 = phi + // ... + // + // where both loop0 and loop1's backedge taken count uses the SCEV + // expression for %v. If we don't have the early stop below then in cases + // like the above, getBackedgeTakenInfo(loop1) will clear out the trip + // count for loop0 and getBackedgeTakenInfo(loop0) will clear out the trip + // count for loop1, effectively nullifying SCEV's trip count cache. + for (auto *U : I->users()) + if (auto *I = dyn_cast(U)) { + auto *LoopForUser = LI.getLoopFor(I->getParent()); + if (LoopForUser && L->contains(LoopForUser) && + Discovered.insert(I).second) + Worklist.push_back(I); + } } } @@ -6510,12 +6532,6 @@ void ScalarEvolution::forgetLoop(const Loop *L) { PushDefUseChildren(I, Worklist); } - for (auto I = ExitLimits.begin(); I != ExitLimits.end(); ++I) { - auto &Query = I->first; - if (Query.L == CurrL) - ExitLimits.erase(I); - } - LoopPropertiesCache.erase(CurrL); // Forget all contained loops too, to avoid dangling entries in the // ValuesAtScopes map. @@ -6777,18 +6793,6 @@ ScalarEvolution::computeBackedgeTakenCount(const Loop *L, ScalarEvolution::ExitLimit ScalarEvolution::computeExitLimit(const Loop *L, BasicBlock *ExitingBlock, - bool AllowPredicates) { - ExitLimitQuery Query(L, ExitingBlock, AllowPredicates); - auto MaybeEL = ExitLimits.find(Query); - if (MaybeEL != ExitLimits.end()) - return MaybeEL->second; - ExitLimit EL = computeExitLimitImpl(L, ExitingBlock, AllowPredicates); - ExitLimits.insert({Query, EL}); - return EL; -} - -ScalarEvolution::ExitLimit -ScalarEvolution::computeExitLimitImpl(const Loop *L, BasicBlock *ExitingBlock, bool AllowPredicates) { // Okay, we've chosen an exiting block. See what condition causes us to exit // at this block and remember the exit block and whether all other targets @@ -10682,7 +10686,6 @@ ScalarEvolution::ScalarEvolution(ScalarEvolution &&Arg) BackedgeTakenCounts(std::move(Arg.BackedgeTakenCounts)), PredicatedBackedgeTakenCounts( std::move(Arg.PredicatedBackedgeTakenCounts)), - ExitLimits(std::move(Arg.ExitLimits)), ConstantEvolutionLoopExitValue( std::move(Arg.ConstantEvolutionLoopExitValue)), ValuesAtScopes(std::move(Arg.ValuesAtScopes)), @@ -11097,7 +11100,7 @@ bool ScalarEvolution::ExitLimit::hasOperand(const SCEV *S) const { } void -ScalarEvolution::forgetMemoizedResults(const SCEV *S, bool EraseExitLimit) { +ScalarEvolution::forgetMemoizedResults(const SCEV *S) { ValuesAtScopes.erase(S); LoopDispositions.erase(S); BlockDispositions.erase(S); @@ -11130,13 +11133,6 @@ ScalarEvolution::forgetMemoizedResults(const SCEV *S, bool EraseExitLimit) { RemoveSCEVFromBackedgeMap(BackedgeTakenCounts); RemoveSCEVFromBackedgeMap(PredicatedBackedgeTakenCounts); - - // TODO: There is a suspicion that we only need to do it when there is a - // SCEVUnknown somewhere inside S. Need to check this. - if (EraseExitLimit) - for (auto I = ExitLimits.begin(), E = ExitLimits.end(); I != E; ++I) - if (I->second.hasOperand(S)) - ExitLimits.erase(I); } void ScalarEvolution::addToLoopUseLists(const SCEV *S) { diff --git a/lib/Analysis/ScopedNoAliasAA.cpp b/lib/Analysis/ScopedNoAliasAA.cpp index ada053cfc1656..b97b08ad0742c 100644 --- a/lib/Analysis/ScopedNoAliasAA.cpp +++ b/lib/Analysis/ScopedNoAliasAA.cpp @@ -48,7 +48,7 @@ using namespace llvm; // can also be achieved by stripping the associated metadata tags from IR, but // this option is sometimes more convenient. static cl::opt EnableScopedNoAlias("enable-scoped-noalias", - cl::init(true)); + cl::init(true), cl::Hidden); namespace { diff --git a/lib/Analysis/TypeBasedAliasAnalysis.cpp b/lib/Analysis/TypeBasedAliasAnalysis.cpp index 1e36e314b864e..2b21b685c7a32 100644 --- a/lib/Analysis/TypeBasedAliasAnalysis.cpp +++ b/lib/Analysis/TypeBasedAliasAnalysis.cpp @@ -142,7 +142,7 @@ using namespace llvm; // A handy option for disabling TBAA functionality. The same effect can also be // achieved by stripping the !tbaa tags from IR, but this option is sometimes // more convenient. -static cl::opt EnableTBAA("enable-tbaa", cl::init(true)); +static cl::opt EnableTBAA("enable-tbaa", cl::init(true), cl::Hidden); namespace { diff --git a/lib/CodeGen/AggressiveAntiDepBreaker.cpp b/lib/CodeGen/AggressiveAntiDepBreaker.cpp index b8a006492d0cc..162e04fe4ce0f 100644 --- a/lib/CodeGen/AggressiveAntiDepBreaker.cpp +++ b/lib/CodeGen/AggressiveAntiDepBreaker.cpp @@ -141,7 +141,7 @@ AggressiveAntiDepBreaker::AggressiveAntiDepBreaker( DEBUG(dbgs() << "AntiDep Critical-Path Registers:"); DEBUG(for (unsigned r : CriticalPathSet.set_bits()) - dbgs() << " " << TRI->getName(r)); + dbgs() << " " << printReg(r, TRI)); DEBUG(dbgs() << '\n'); } @@ -216,7 +216,7 @@ void AggressiveAntiDepBreaker::Observe(MachineInstr &MI, unsigned Count, // schedule region). if (State->IsLive(Reg)) { DEBUG(if (State->GetGroup(Reg) != 0) - dbgs() << " " << TRI->getName(Reg) << "=g" << + dbgs() << " " << printReg(Reg, TRI) << "=g" << State->GetGroup(Reg) << "->g0(region live-out)"); State->UnionGroups(Reg, 0); } else if ((DefIndices[Reg] < InsertPosIndex) @@ -323,7 +323,7 @@ void AggressiveAntiDepBreaker::HandleLastUse(unsigned Reg, unsigned KillIdx, RegRefs.erase(Reg); State->LeaveGroup(Reg); DEBUG(if (header) { - dbgs() << header << TRI->getName(Reg); header = nullptr; }); + dbgs() << header << printReg(Reg, TRI); header = nullptr; }); DEBUG(dbgs() << "->g" << State->GetGroup(Reg) << tag); // Repeat for subregisters. Note that we only do this if the superregister // was not live because otherwise, regardless whether we have an explicit @@ -337,8 +337,8 @@ void AggressiveAntiDepBreaker::HandleLastUse(unsigned Reg, unsigned KillIdx, RegRefs.erase(SubregReg); State->LeaveGroup(SubregReg); DEBUG(if (header) { - dbgs() << header << TRI->getName(Reg); header = nullptr; }); - DEBUG(dbgs() << " " << TRI->getName(SubregReg) << "->g" << + dbgs() << header << printReg(Reg, TRI); header = nullptr; }); + DEBUG(dbgs() << " " << printReg(SubregReg, TRI) << "->g" << State->GetGroup(SubregReg) << tag); } } @@ -374,7 +374,7 @@ void AggressiveAntiDepBreaker::PrescanInstruction( unsigned Reg = MO.getReg(); if (Reg == 0) continue; - DEBUG(dbgs() << " " << TRI->getName(Reg) << "=g" << State->GetGroup(Reg)); + DEBUG(dbgs() << " " << printReg(Reg, TRI) << "=g" << State->GetGroup(Reg)); // If MI's defs have a special allocation requirement, don't allow // any def registers to be changed. Also assume all registers @@ -393,8 +393,8 @@ void AggressiveAntiDepBreaker::PrescanInstruction( unsigned AliasReg = *AI; if (State->IsLive(AliasReg)) { State->UnionGroups(Reg, AliasReg); - DEBUG(dbgs() << "->g" << State->GetGroup(Reg) << "(via " << - TRI->getName(AliasReg) << ")"); + DEBUG(dbgs() << "->g" << State->GetGroup(Reg) << "(via " + << printReg(AliasReg, TRI) << ")"); } } @@ -469,8 +469,7 @@ void AggressiveAntiDepBreaker::ScanInstruction(MachineInstr &MI, unsigned Reg = MO.getReg(); if (Reg == 0) continue; - DEBUG(dbgs() << " " << TRI->getName(Reg) << "=g" << - State->GetGroup(Reg)); + DEBUG(dbgs() << " " << printReg(Reg, TRI) << "=g" << State->GetGroup(Reg)); // It wasn't previously live but now it is, this is a kill. Forget // the previous live-range information and start a new live-range @@ -505,10 +504,10 @@ void AggressiveAntiDepBreaker::ScanInstruction(MachineInstr &MI, if (Reg == 0) continue; if (FirstReg != 0) { - DEBUG(dbgs() << "=" << TRI->getName(Reg)); + DEBUG(dbgs() << "=" << printReg(Reg, TRI)); State->UnionGroups(FirstReg, Reg); } else { - DEBUG(dbgs() << " " << TRI->getName(Reg)); + DEBUG(dbgs() << " " << printReg(Reg, TRI)); FirstReg = Reg; } } @@ -574,7 +573,7 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters( // If Reg has any references, then collect possible rename regs if (RegRefs.count(Reg) > 0) { - DEBUG(dbgs() << "\t\t" << TRI->getName(Reg) << ":"); + DEBUG(dbgs() << "\t\t" << printReg(Reg, TRI) << ":"); BitVector &BV = RenameRegisterMap[Reg]; assert(BV.empty()); @@ -583,7 +582,7 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters( DEBUG({ dbgs() << " ::"; for (unsigned r : BV.set_bits()) - dbgs() << " " << TRI->getName(r); + dbgs() << " " << printReg(r, TRI); dbgs() << "\n"; }); } @@ -608,8 +607,8 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters( if (renamecnt++ % DebugDiv != DebugMod) return false; - dbgs() << "*** Performing rename " << TRI->getName(SuperReg) << - " for debug ***\n"; + dbgs() << "*** Performing rename " << printReg(SuperReg, TRI) + << " for debug ***\n"; } #endif @@ -646,7 +645,7 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters( // Don't replace a register with itself. if (NewSuperReg == SuperReg) continue; - DEBUG(dbgs() << " [" << TRI->getName(NewSuperReg) << ':'); + DEBUG(dbgs() << " [" << printReg(NewSuperReg, TRI) << ':'); RenameMap.clear(); // For each referenced group register (which must be a SuperReg or @@ -663,7 +662,7 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters( NewReg = TRI->getSubReg(NewSuperReg, NewSubRegIdx); } - DEBUG(dbgs() << " " << TRI->getName(NewReg)); + DEBUG(dbgs() << " " << printReg(NewReg, TRI)); // Check if Reg can be renamed to NewReg. if (!RenameRegisterMap[Reg].test(NewReg)) { @@ -684,7 +683,7 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters( unsigned AliasReg = *AI; if (State->IsLive(AliasReg) || (KillIndices[Reg] > DefIndices[AliasReg])) { - DEBUG(dbgs() << "(alias " << TRI->getName(AliasReg) << " live)"); + DEBUG(dbgs() << "(alias " << printReg(AliasReg, TRI) << " live)"); found = true; break; } @@ -793,7 +792,7 @@ unsigned AggressiveAntiDepBreaker::BreakAntiDependencies( DEBUG(dbgs() << "Available regs:"); for (unsigned Reg = 0; Reg < TRI->getNumRegs(); ++Reg) { if (!State->IsLive(Reg)) - DEBUG(dbgs() << " " << TRI->getName(Reg)); + DEBUG(dbgs() << " " << printReg(Reg, TRI)); } DEBUG(dbgs() << '\n'); #endif @@ -849,7 +848,7 @@ unsigned AggressiveAntiDepBreaker::BreakAntiDependencies( (Edge->getKind() != SDep::Output)) continue; unsigned AntiDepReg = Edge->getReg(); - DEBUG(dbgs() << "\tAntidep reg: " << TRI->getName(AntiDepReg)); + DEBUG(dbgs() << "\tAntidep reg: " << printReg(AntiDepReg, TRI)); assert(AntiDepReg != 0 && "Anti-dependence on reg0?"); if (!MRI.isAllocatable(AntiDepReg)) { @@ -952,7 +951,7 @@ unsigned AggressiveAntiDepBreaker::BreakAntiDependencies( std::map RenameMap; if (FindSuitableFreeRegisters(GroupIndex, RenameOrder, RenameMap)) { DEBUG(dbgs() << "\tBreaking anti-dependence edge on " - << TRI->getName(AntiDepReg) << ":"); + << printReg(AntiDepReg, TRI) << ":"); // Handle each group register... for (std::map::iterator @@ -960,9 +959,9 @@ unsigned AggressiveAntiDepBreaker::BreakAntiDependencies( unsigned CurrReg = S->first; unsigned NewReg = S->second; - DEBUG(dbgs() << " " << TRI->getName(CurrReg) << "->" << - TRI->getName(NewReg) << "(" << - RegRefs.count(CurrReg) << " refs)"); + DEBUG(dbgs() << " " << printReg(CurrReg, TRI) << "->" + << printReg(NewReg, TRI) << "(" + << RegRefs.count(CurrReg) << " refs)"); // Update the references to the old register CurrReg to // refer to the new register NewReg. diff --git a/lib/CodeGen/AsmPrinter/AsmPrinter.cpp b/lib/CodeGen/AsmPrinter/AsmPrinter.cpp index c9b0f9aa556fe..1bc8b4eee0f02 100644 --- a/lib/CodeGen/AsmPrinter/AsmPrinter.cpp +++ b/lib/CodeGen/AsmPrinter/AsmPrinter.cpp @@ -964,6 +964,31 @@ void AsmPrinter::emitFrameAlloc(const MachineInstr &MI) { MCConstantExpr::create(FrameOffset, OutContext)); } +void AsmPrinter::emitStackSizeSection(const MachineFunction &MF) { + if (!MF.getTarget().Options.EmitStackSizeSection) + return; + + MCSection *StackSizeSection = getObjFileLowering().getStackSizesSection(); + if (!StackSizeSection) + return; + + const MachineFrameInfo &FrameInfo = MF.getFrameInfo(); + // Don't emit functions with dynamic stack allocations. + if (FrameInfo.hasVarSizedObjects()) + return; + + OutStreamer->PushSection(); + OutStreamer->SwitchSection(StackSizeSection); + + const MCSymbol *FunctionSymbol = getSymbol(MF.getFunction()); + uint64_t StackSize = FrameInfo.getStackSize(); + OutStreamer->EmitValue(MCSymbolRefExpr::create(FunctionSymbol, OutContext), + /* size = */ 8); + OutStreamer->EmitULEB128IntValue(StackSize); + + OutStreamer->PopSection(); +} + static bool needFuncLabelsForEHOrDebugInfo(const MachineFunction &MF, MachineModuleInfo *MMI) { if (!MF.getLandingPads().empty() || MF.hasEHFunclets() || MMI->hasDebugInfo()) @@ -1135,6 +1160,9 @@ void AsmPrinter::EmitFunctionBody() { HI.Handler->endFunction(MF); } + // Emit section containing stack size metadata. + emitStackSizeSection(*MF); + if (isVerbose()) OutStreamer->GetCommentOS() << "-- End function\n"; @@ -2682,7 +2710,8 @@ void AsmPrinter::EmitBasicBlockStart(const MachineBasicBlock &MBB) const { (isBlockOnlyReachableByFallthrough(&MBB) && !MBB.isEHFuncletEntry())) { if (isVerbose()) { // NOTE: Want this comment at start of line, don't emit with AddComment. - OutStreamer->emitRawComment(" BB#" + Twine(MBB.getNumber()) + ":", false); + OutStreamer->emitRawComment(" %bb." + Twine(MBB.getNumber()) + ":", + false); } } else { OutStreamer->EmitLabel(MBB.getSymbol()); diff --git a/lib/CodeGen/AsmPrinter/CodeViewDebug.h b/lib/CodeGen/AsmPrinter/CodeViewDebug.h index 9eff4a7fd8147..663b9b50c9da1 100644 --- a/lib/CodeGen/AsmPrinter/CodeViewDebug.h +++ b/lib/CodeGen/AsmPrinter/CodeViewDebug.h @@ -23,8 +23,8 @@ #include "llvm/ADT/SetVector.h" #include "llvm/ADT/SmallVector.h" #include "llvm/DebugInfo/CodeView/CodeView.h" +#include "llvm/DebugInfo/CodeView/MergingTypeTableBuilder.h" #include "llvm/DebugInfo/CodeView/TypeIndex.h" -#include "llvm/DebugInfo/CodeView/TypeTableBuilder.h" #include "llvm/IR/DebugLoc.h" #include "llvm/Support/Allocator.h" #include "llvm/Support/Compiler.h" @@ -52,7 +52,7 @@ class MachineFunction; class LLVM_LIBRARY_VISIBILITY CodeViewDebug : public DebugHandlerBase { MCStreamer &OS; BumpPtrAllocator Allocator; - codeview::TypeTableBuilder TypeTable; + codeview::MergingTypeTableBuilder TypeTable; /// Represents the most general definition range. struct LocalVarDefRange { diff --git a/lib/CodeGen/BranchFolding.cpp b/lib/CodeGen/BranchFolding.cpp index d31260e767fbb..92e73cb502cc0 100644 --- a/lib/CodeGen/BranchFolding.cpp +++ b/lib/CodeGen/BranchFolding.cpp @@ -613,8 +613,8 @@ ProfitableToMerge(MachineBasicBlock *MBB1, MachineBasicBlock *MBB2, CommonTailLen = ComputeCommonTailLength(MBB1, MBB2, I1, I2); if (CommonTailLen == 0) return false; - DEBUG(dbgs() << "Common tail length of BB#" << MBB1->getNumber() - << " and BB#" << MBB2->getNumber() << " is " << CommonTailLen + DEBUG(dbgs() << "Common tail length of " << printMBBReference(*MBB1) + << " and " << printMBBReference(*MBB2) << " is " << CommonTailLen << '\n'); // It's almost always profitable to merge any number of non-terminator @@ -770,7 +770,7 @@ bool BranchFolder::CreateCommonTailOnlyBlock(MachineBasicBlock *&PredBB, SameTails[commonTailIndex].getTailStartPos(); MachineBasicBlock *MBB = SameTails[commonTailIndex].getBlock(); - DEBUG(dbgs() << "\nSplitting BB#" << MBB->getNumber() << ", size " + DEBUG(dbgs() << "\nSplitting " << printMBBReference(*MBB) << ", size " << maxCommonTailLength); // If the split block unconditionally falls-thru to SuccBB, it will be @@ -920,20 +920,17 @@ bool BranchFolder::TryTailMergeBlocks(MachineBasicBlock *SuccBB, bool MadeChange = false; DEBUG(dbgs() << "\nTryTailMergeBlocks: "; - for (unsigned i = 0, e = MergePotentials.size(); i != e; ++i) - dbgs() << "BB#" << MergePotentials[i].getBlock()->getNumber() - << (i == e-1 ? "" : ", "); - dbgs() << "\n"; - if (SuccBB) { - dbgs() << " with successor BB#" << SuccBB->getNumber() << '\n'; + for (unsigned i = 0, e = MergePotentials.size(); i != e; ++i) dbgs() + << printMBBReference(*MergePotentials[i].getBlock()) + << (i == e - 1 ? "" : ", "); + dbgs() << "\n"; if (SuccBB) { + dbgs() << " with successor " << printMBBReference(*SuccBB) << '\n'; if (PredBB) - dbgs() << " which has fall-through from BB#" - << PredBB->getNumber() << "\n"; - } - dbgs() << "Looking for common tails of at least " - << MinCommonTailLength << " instruction" - << (MinCommonTailLength == 1 ? "" : "s") << '\n'; - ); + dbgs() << " which has fall-through from " + << printMBBReference(*PredBB) << "\n"; + } dbgs() << "Looking for common tails of at least " + << MinCommonTailLength << " instruction" + << (MinCommonTailLength == 1 ? "" : "s") << '\n';); // Sort by hash value so that blocks with identical end sequences sort // together. @@ -1013,13 +1010,13 @@ bool BranchFolder::TryTailMergeBlocks(MachineBasicBlock *SuccBB, // MBB is common tail. Adjust all other BB's to jump to this one. // Traversal must be forwards so erases work. - DEBUG(dbgs() << "\nUsing common tail in BB#" << MBB->getNumber() + DEBUG(dbgs() << "\nUsing common tail in " << printMBBReference(*MBB) << " for "); for (unsigned int i=0, e = SameTails.size(); i != e; ++i) { if (commonTailIndex == i) continue; - DEBUG(dbgs() << "BB#" << SameTails[i].getBlock()->getNumber() - << (i == e-1 ? "" : ", ")); + DEBUG(dbgs() << printMBBReference(*SameTails[i].getBlock()) + << (i == e - 1 ? "" : ", ")); // Hack the end off BB i, making it jump to BB commonTailIndex instead. replaceTailWithBranchTo(SameTails[i].getTailStartPos(), *MBB); // BB i is no longer a predecessor of SuccBB; remove it from the worklist. diff --git a/lib/CodeGen/BranchRelaxation.cpp b/lib/CodeGen/BranchRelaxation.cpp index 99fa4dc679156..0d87f142c7cce 100644 --- a/lib/CodeGen/BranchRelaxation.cpp +++ b/lib/CodeGen/BranchRelaxation.cpp @@ -143,7 +143,7 @@ void BranchRelaxation::verify() { LLVM_DUMP_METHOD void BranchRelaxation::dumpBBs() { for (auto &MBB : *MF) { const BasicBlockInfo &BBI = BlockInfo[MBB.getNumber()]; - dbgs() << format("BB#%u\toffset=%08x\t", MBB.getNumber(), BBI.Offset) + dbgs() << format("%bb.%u\toffset=%08x\t", MBB.getNumber(), BBI.Offset) << format("size=%#x\n", BBI.Size); } } @@ -287,13 +287,10 @@ bool BranchRelaxation::isBlockInRange( if (TII->isBranchOffsetInRange(MI.getOpcode(), DestOffset - BrOffset)) return true; - DEBUG( - dbgs() << "Out of range branch to destination BB#" << DestBB.getNumber() - << " from BB#" << MI.getParent()->getNumber() - << " to " << DestOffset - << " offset " << DestOffset - BrOffset - << '\t' << MI - ); + DEBUG(dbgs() << "Out of range branch to destination " + << printMBBReference(DestBB) << " from " + << printMBBReference(*MI.getParent()) << " to " << DestOffset + << " offset " << DestOffset - BrOffset << '\t' << MI); return false; } @@ -366,9 +363,9 @@ bool BranchRelaxation::fixupConditionalBranch(MachineInstr &MI) { // just created), so we can invert the condition. MachineBasicBlock &NextBB = *std::next(MachineFunction::iterator(MBB)); - DEBUG(dbgs() << " Insert B to BB#" << TBB->getNumber() - << ", invert condition and change dest. to BB#" - << NextBB.getNumber() << '\n'); + DEBUG(dbgs() << " Insert B to " << printMBBReference(*TBB) + << ", invert condition and change dest. to " + << printMBBReference(NextBB) << '\n'); unsigned &MBBSize = BlockInfo[MBB->getNumber()].Size; diff --git a/lib/CodeGen/CodeGenPrepare.cpp b/lib/CodeGen/CodeGenPrepare.cpp index 9d3e7230ed00a..1b01f84303669 100644 --- a/lib/CodeGen/CodeGenPrepare.cpp +++ b/lib/CodeGen/CodeGenPrepare.cpp @@ -18,7 +18,6 @@ #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/PointerIntPair.h" #include "llvm/ADT/STLExtras.h" -#include "llvm/ADT/SetVector.h" #include "llvm/ADT/SmallPtrSet.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/Statistic.h" @@ -86,10 +85,8 @@ #include "llvm/Target/TargetOptions.h" #include "llvm/Transforms/Utils/BasicBlockUtils.h" #include "llvm/Transforms/Utils/BypassSlowDivision.h" -#include "llvm/Transforms/Utils/Cloning.h" #include "llvm/Transforms/Utils/Local.h" #include "llvm/Transforms/Utils/SimplifyLibCalls.h" -#include "llvm/Transforms/Utils/ValueMapper.h" #include #include #include @@ -331,7 +328,6 @@ class TypePromotionTransaction; SmallVectorImpl &SpeculativelyMovedExts); bool splitBranchCondition(Function &F); bool simplifyOffsetableRelocate(Instruction &I); - bool splitIndirectCriticalEdges(Function &F); }; } // end anonymous namespace @@ -410,7 +406,7 @@ bool CodeGenPrepare::runOnFunction(Function &F) { // Split some critical edges where one of the sources is an indirect branch, // to help generate sane code for PHIs involving such edges. - EverMadeChange |= splitIndirectCriticalEdges(F); + EverMadeChange |= SplitIndirectBrCriticalEdges(F); bool MadeChange = true; while (MadeChange) { @@ -555,160 +551,6 @@ BasicBlock *CodeGenPrepare::findDestBlockOfMergeableEmptyBlock(BasicBlock *BB) { return DestBB; } -// Return the unique indirectbr predecessor of a block. This may return null -// even if such a predecessor exists, if it's not useful for splitting. -// If a predecessor is found, OtherPreds will contain all other (non-indirectbr) -// predecessors of BB. -static BasicBlock * -findIBRPredecessor(BasicBlock *BB, SmallVectorImpl &OtherPreds) { - // If the block doesn't have any PHIs, we don't care about it, since there's - // no point in splitting it. - PHINode *PN = dyn_cast(BB->begin()); - if (!PN) - return nullptr; - - // Verify we have exactly one IBR predecessor. - // Conservatively bail out if one of the other predecessors is not a "regular" - // terminator (that is, not a switch or a br). - BasicBlock *IBB = nullptr; - for (unsigned Pred = 0, E = PN->getNumIncomingValues(); Pred != E; ++Pred) { - BasicBlock *PredBB = PN->getIncomingBlock(Pred); - TerminatorInst *PredTerm = PredBB->getTerminator(); - switch (PredTerm->getOpcode()) { - case Instruction::IndirectBr: - if (IBB) - return nullptr; - IBB = PredBB; - break; - case Instruction::Br: - case Instruction::Switch: - OtherPreds.push_back(PredBB); - continue; - default: - return nullptr; - } - } - - return IBB; -} - -// Split critical edges where the source of the edge is an indirectbr -// instruction. This isn't always possible, but we can handle some easy cases. -// This is useful because MI is unable to split such critical edges, -// which means it will not be able to sink instructions along those edges. -// This is especially painful for indirect branches with many successors, where -// we end up having to prepare all outgoing values in the origin block. -// -// Our normal algorithm for splitting critical edges requires us to update -// the outgoing edges of the edge origin block, but for an indirectbr this -// is hard, since it would require finding and updating the block addresses -// the indirect branch uses. But if a block only has a single indirectbr -// predecessor, with the others being regular branches, we can do it in a -// different way. -// Say we have A -> D, B -> D, I -> D where only I -> D is an indirectbr. -// We can split D into D0 and D1, where D0 contains only the PHIs from D, -// and D1 is the D block body. We can then duplicate D0 as D0A and D0B, and -// create the following structure: -// A -> D0A, B -> D0A, I -> D0B, D0A -> D1, D0B -> D1 -bool CodeGenPrepare::splitIndirectCriticalEdges(Function &F) { - // Check whether the function has any indirectbrs, and collect which blocks - // they may jump to. Since most functions don't have indirect branches, - // this lowers the common case's overhead to O(Blocks) instead of O(Edges). - SmallSetVector Targets; - for (auto &BB : F) { - auto *IBI = dyn_cast(BB.getTerminator()); - if (!IBI) - continue; - - for (unsigned Succ = 0, E = IBI->getNumSuccessors(); Succ != E; ++Succ) - Targets.insert(IBI->getSuccessor(Succ)); - } - - if (Targets.empty()) - return false; - - bool Changed = false; - for (BasicBlock *Target : Targets) { - SmallVector OtherPreds; - BasicBlock *IBRPred = findIBRPredecessor(Target, OtherPreds); - // If we did not found an indirectbr, or the indirectbr is the only - // incoming edge, this isn't the kind of edge we're looking for. - if (!IBRPred || OtherPreds.empty()) - continue; - - // Don't even think about ehpads/landingpads. - Instruction *FirstNonPHI = Target->getFirstNonPHI(); - if (FirstNonPHI->isEHPad() || Target->isLandingPad()) - continue; - - BasicBlock *BodyBlock = Target->splitBasicBlock(FirstNonPHI, ".split"); - // It's possible Target was its own successor through an indirectbr. - // In this case, the indirectbr now comes from BodyBlock. - if (IBRPred == Target) - IBRPred = BodyBlock; - - // At this point Target only has PHIs, and BodyBlock has the rest of the - // block's body. Create a copy of Target that will be used by the "direct" - // preds. - ValueToValueMapTy VMap; - BasicBlock *DirectSucc = CloneBasicBlock(Target, VMap, ".clone", &F); - - for (BasicBlock *Pred : OtherPreds) { - // If the target is a loop to itself, then the terminator of the split - // block needs to be updated. - if (Pred == Target) - BodyBlock->getTerminator()->replaceUsesOfWith(Target, DirectSucc); - else - Pred->getTerminator()->replaceUsesOfWith(Target, DirectSucc); - } - - // Ok, now fix up the PHIs. We know the two blocks only have PHIs, and that - // they are clones, so the number of PHIs are the same. - // (a) Remove the edge coming from IBRPred from the "Direct" PHI - // (b) Leave that as the only edge in the "Indirect" PHI. - // (c) Merge the two in the body block. - BasicBlock::iterator Indirect = Target->begin(), - End = Target->getFirstNonPHI()->getIterator(); - BasicBlock::iterator Direct = DirectSucc->begin(); - BasicBlock::iterator MergeInsert = BodyBlock->getFirstInsertionPt(); - - assert(&*End == Target->getTerminator() && - "Block was expected to only contain PHIs"); - - while (Indirect != End) { - PHINode *DirPHI = cast(Direct); - PHINode *IndPHI = cast(Indirect); - - // Now, clean up - the direct block shouldn't get the indirect value, - // and vice versa. - DirPHI->removeIncomingValue(IBRPred); - Direct++; - - // Advance the pointer here, to avoid invalidation issues when the old - // PHI is erased. - Indirect++; - - PHINode *NewIndPHI = PHINode::Create(IndPHI->getType(), 1, "ind", IndPHI); - NewIndPHI->addIncoming(IndPHI->getIncomingValueForBlock(IBRPred), - IBRPred); - - // Create a PHI in the body block, to merge the direct and indirect - // predecessors. - PHINode *MergePHI = - PHINode::Create(IndPHI->getType(), 2, "merge", &*MergeInsert); - MergePHI->addIncoming(NewIndPHI, Target); - MergePHI->addIncoming(DirPHI, DirectSucc); - - IndPHI->replaceAllUsesWith(MergePHI); - IndPHI->eraseFromParent(); - } - - Changed = true; - } - - return Changed; -} - /// Eliminate blocks that contain only PHI nodes, debug info directives, and an /// unconditional branch. Passes before isel (e.g. LSR/loopsimplify) often split /// edges in ways that are non-optimal for isel. Start by eliminating these diff --git a/lib/CodeGen/CriticalAntiDepBreaker.cpp b/lib/CodeGen/CriticalAntiDepBreaker.cpp index 83f08e082c3af..30918a98be042 100644 --- a/lib/CodeGen/CriticalAntiDepBreaker.cpp +++ b/lib/CodeGen/CriticalAntiDepBreaker.cpp @@ -466,7 +466,7 @@ BreakAntiDependencies(const std::vector &SUnits, DEBUG(dbgs() << "Available regs:"); for (unsigned Reg = 0; Reg < TRI->getNumRegs(); ++Reg) { if (KillIndices[Reg] == ~0u) - DEBUG(dbgs() << " " << TRI->getName(Reg)); + DEBUG(dbgs() << " " << printReg(Reg, TRI)); } DEBUG(dbgs() << '\n'); } @@ -646,9 +646,9 @@ BreakAntiDependencies(const std::vector &SUnits, LastNewReg[AntiDepReg], RC, ForbidRegs)) { DEBUG(dbgs() << "Breaking anti-dependence edge on " - << TRI->getName(AntiDepReg) - << " with " << RegRefs.count(AntiDepReg) << " references" - << " using " << TRI->getName(NewReg) << "!\n"); + << printReg(AntiDepReg, TRI) << " with " + << RegRefs.count(AntiDepReg) << " references" + << " using " << printReg(NewReg, TRI) << "!\n"); // Update the references to the old register to refer to the new // register. diff --git a/lib/CodeGen/DetectDeadLanes.cpp b/lib/CodeGen/DetectDeadLanes.cpp index ef4e2aaaf484e..b82876e1c85a5 100644 --- a/lib/CodeGen/DetectDeadLanes.cpp +++ b/lib/CodeGen/DetectDeadLanes.cpp @@ -17,12 +17,12 @@ /// when subregisters are involved. /// /// Example: -/// %vreg0 = some definition -/// %vreg1 = IMPLICIT_DEF -/// %vreg2 = REG_SEQUENCE %vreg0, sub0, %vreg1, sub1 -/// %vreg3 = EXTRACT_SUBREG %vreg2, sub1 -/// = use %vreg3 -/// The %vreg0 definition is dead and %vreg3 contains an undefined value. +/// %0 = some definition +/// %1 = IMPLICIT_DEF +/// %2 = REG_SEQUENCE %0, sub0, %1, sub1 +/// %3 = EXTRACT_SUBREG %2, sub1 +/// = use %3 +/// The %0 definition is dead and %3 contains an undefined value. // //===----------------------------------------------------------------------===// diff --git a/lib/CodeGen/EarlyIfConversion.cpp b/lib/CodeGen/EarlyIfConversion.cpp index bb181b7e165f4..461da8f138f9c 100644 --- a/lib/CodeGen/EarlyIfConversion.cpp +++ b/lib/CodeGen/EarlyIfConversion.cpp @@ -185,7 +185,7 @@ bool SSAIfConv::canSpeculateInstrs(MachineBasicBlock *MBB) { // Reject any live-in physregs. It's probably CPSR/EFLAGS, and very hard to // get right. if (!MBB->livein_empty()) { - DEBUG(dbgs() << "BB#" << MBB->getNumber() << " has live-ins.\n"); + DEBUG(dbgs() << printMBBReference(*MBB) << " has live-ins.\n"); return false; } @@ -199,7 +199,7 @@ bool SSAIfConv::canSpeculateInstrs(MachineBasicBlock *MBB) { continue; if (++InstrCount > BlockInstrLimit && !Stress) { - DEBUG(dbgs() << "BB#" << MBB->getNumber() << " has more than " + DEBUG(dbgs() << printMBBReference(*MBB) << " has more than " << BlockInstrLimit << " instructions.\n"); return false; } @@ -246,7 +246,7 @@ bool SSAIfConv::canSpeculateInstrs(MachineBasicBlock *MBB) { if (!DefMI || DefMI->getParent() != Head) continue; if (InsertAfter.insert(DefMI).second) - DEBUG(dbgs() << "BB#" << MBB->getNumber() << " depends on " << *DefMI); + DEBUG(dbgs() << printMBBReference(*MBB) << " depends on " << *DefMI); if (DefMI->isTerminator()) { DEBUG(dbgs() << "Can't insert instructions below terminator.\n"); return false; @@ -361,10 +361,10 @@ bool SSAIfConv::canConvertIf(MachineBasicBlock *MBB) { if (Succ1->pred_size() != 1 || Succ1->succ_size() != 1 || Succ1->succ_begin()[0] != Tail) return false; - DEBUG(dbgs() << "\nDiamond: BB#" << Head->getNumber() - << " -> BB#" << Succ0->getNumber() - << "/BB#" << Succ1->getNumber() - << " -> BB#" << Tail->getNumber() << '\n'); + DEBUG(dbgs() << "\nDiamond: " << printMBBReference(*Head) << " -> " + << printMBBReference(*Succ0) << "/" + << printMBBReference(*Succ1) << " -> " + << printMBBReference(*Tail) << '\n'); // Live-in physregs are tricky to get right when speculating code. if (!Tail->livein_empty()) { @@ -372,9 +372,9 @@ bool SSAIfConv::canConvertIf(MachineBasicBlock *MBB) { return false; } } else { - DEBUG(dbgs() << "\nTriangle: BB#" << Head->getNumber() - << " -> BB#" << Succ0->getNumber() - << " -> BB#" << Tail->getNumber() << '\n'); + DEBUG(dbgs() << "\nTriangle: " << printMBBReference(*Head) << " -> " + << printMBBReference(*Succ0) << " -> " + << printMBBReference(*Tail) << '\n'); } // This is a triangle or a diamond. @@ -563,8 +563,8 @@ void SSAIfConv::convertIf(SmallVectorImpl &RemovedBlocks) { assert(Head->succ_empty() && "Additional head successors?"); if (!ExtraPreds && Head->isLayoutSuccessor(Tail)) { // Splice Tail onto the end of Head. - DEBUG(dbgs() << "Joining tail BB#" << Tail->getNumber() - << " into head BB#" << Head->getNumber() << '\n'); + DEBUG(dbgs() << "Joining tail " << printMBBReference(*Tail) << " into head " + << printMBBReference(*Head) << '\n'); Head->splice(Head->end(), Tail, Tail->begin(), Tail->end()); Head->transferSuccessorsAndUpdatePHIs(Tail); diff --git a/lib/CodeGen/EdgeBundles.cpp b/lib/CodeGen/EdgeBundles.cpp index b3a25544be39c..54c53eb163122 100644 --- a/lib/CodeGen/EdgeBundles.cpp +++ b/lib/CodeGen/EdgeBundles.cpp @@ -80,13 +80,15 @@ raw_ostream &WriteGraph<>(raw_ostream &O, const EdgeBundles &G, O << "digraph {\n"; for (const auto &MBB : *MF) { unsigned BB = MBB.getNumber(); - O << "\t\"BB#" << BB << "\" [ shape=box ]\n" - << '\t' << G.getBundle(BB, false) << " -> \"BB#" << BB << "\"\n" - << "\t\"BB#" << BB << "\" -> " << G.getBundle(BB, true) << '\n'; + O << "\t\"" << printMBBReference(MBB) << "\" [ shape=box ]\n" + << '\t' << G.getBundle(BB, false) << " -> \"" << printMBBReference(MBB) + << "\"\n" + << "\t\"" << printMBBReference(MBB) << "\" -> " << G.getBundle(BB, true) + << '\n'; for (MachineBasicBlock::const_succ_iterator SI = MBB.succ_begin(), SE = MBB.succ_end(); SI != SE; ++SI) - O << "\t\"BB#" << BB << "\" -> \"BB#" << (*SI)->getNumber() - << "\" [ color=lightgray ]\n"; + O << "\t\"" << printMBBReference(MBB) << "\" -> \"" + << printMBBReference(**SI) << "\" [ color=lightgray ]\n"; } O << "}\n"; return O; diff --git a/lib/CodeGen/ExecutionDepsFix.cpp b/lib/CodeGen/ExecutionDepsFix.cpp index 61990671d88d5..df51ecc0001d7 100644 --- a/lib/CodeGen/ExecutionDepsFix.cpp +++ b/lib/CodeGen/ExecutionDepsFix.cpp @@ -200,7 +200,7 @@ void ExecutionDepsFix::enterBasicBlock(MachineBasicBlock *MBB) { LiveRegs[rx].Def = -1; } } - DEBUG(dbgs() << "BB#" << MBB->getNumber() << ": entry\n"); + DEBUG(dbgs() << printMBBReference(*MBB) << ": entry\n"); return; } @@ -246,7 +246,7 @@ void ExecutionDepsFix::enterBasicBlock(MachineBasicBlock *MBB) { } } DEBUG( - dbgs() << "BB#" << MBB->getNumber() + dbgs() << printMBBReference(*MBB) << (!isBlockDone(MBB) ? ": incomplete\n" : ": all preds known\n")); } @@ -394,7 +394,7 @@ void ExecutionDepsFix::processDefs(MachineInstr *MI, bool breakDependency, continue; for (int rx : regIndices(MO.getReg())) { // This instruction explicitly defines rx. - DEBUG(dbgs() << TRI->getName(RC->getRegister(rx)) << ":\t" << CurInstr + DEBUG(dbgs() << printReg(RC->getRegister(rx), TRI) << ":\t" << CurInstr << '\t' << *MI); if (breakDependency) { diff --git a/lib/CodeGen/GlobalISel/IRTranslator.cpp b/lib/CodeGen/GlobalISel/IRTranslator.cpp index 99251bb23b140..774ea9877a7d1 100644 --- a/lib/CodeGen/GlobalISel/IRTranslator.cpp +++ b/lib/CodeGen/GlobalISel/IRTranslator.cpp @@ -238,6 +238,8 @@ bool IRTranslator::translateCompare(const User &U, bool IRTranslator::translateRet(const User &U, MachineIRBuilder &MIRBuilder) { const ReturnInst &RI = cast(U); const Value *Ret = RI.getReturnValue(); + if (Ret && DL->getTypeStoreSize(Ret->getType()) == 0) + Ret = nullptr; // The target may mess up with the insertion point, but // this is not important as a return is the last instruction // of the block anyway. @@ -337,9 +339,22 @@ bool IRTranslator::translateLoad(const User &U, MachineIRBuilder &MIRBuilder) { : MachineMemOperand::MONone; Flags |= MachineMemOperand::MOLoad; + if (DL->getTypeStoreSize(LI.getType()) == 0) + return true; + unsigned Res = getOrCreateVReg(LI); unsigned Addr = getOrCreateVReg(*LI.getPointerOperand()); + if (LI.getOrdering() != AtomicOrdering::NotAtomic) { + MIRBuilder.buildAtomicLoad( + Res, Addr, + *MF->getMachineMemOperand(MachinePointerInfo(LI.getPointerOperand()), + Flags, DL->getTypeStoreSize(LI.getType()), + getMemOpAlignment(LI), AAMDNodes(), nullptr, + LI.getSyncScopeID(), LI.getOrdering())); + return true; + } + MIRBuilder.buildLoad( Res, Addr, *MF->getMachineMemOperand(MachinePointerInfo(LI.getPointerOperand()), @@ -355,9 +370,23 @@ bool IRTranslator::translateStore(const User &U, MachineIRBuilder &MIRBuilder) { : MachineMemOperand::MONone; Flags |= MachineMemOperand::MOStore; + if (DL->getTypeStoreSize(SI.getValueOperand()->getType()) == 0) + return true; + unsigned Val = getOrCreateVReg(*SI.getValueOperand()); unsigned Addr = getOrCreateVReg(*SI.getPointerOperand()); + if (SI.getOrdering() != AtomicOrdering::NotAtomic) { + MIRBuilder.buildAtomicStore( + Val, Addr, + *MF->getMachineMemOperand( + MachinePointerInfo(SI.getPointerOperand()), Flags, + DL->getTypeStoreSize(SI.getValueOperand()->getType()), + getMemOpAlignment(SI), AAMDNodes(), nullptr, SI.getSyncScopeID(), + SI.getOrdering())); + return true; + } + MIRBuilder.buildStore( Val, Addr, *MF->getMachineMemOperand( @@ -1269,8 +1298,11 @@ bool IRTranslator::runOnMachineFunction(MachineFunction &CurMF) { // Lower the actual args into this basic block. SmallVector VRegArgs; - for (const Argument &Arg: F.args()) + for (const Argument &Arg: F.args()) { + if (DL->getTypeStoreSize(Arg.getType()) == 0) + continue; // Don't handle zero sized types. VRegArgs.push_back(getOrCreateVReg(Arg)); + } if (!CLI->lowerFormalArguments(EntryBuilder, F, VRegArgs)) { OptimizationRemarkMissed R("gisel-irtranslator", "GISelFailure", MF->getFunction()->getSubprogram(), diff --git a/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/lib/CodeGen/GlobalISel/LegalizerHelper.cpp index bb2e61582314e..53d6758dfb67a 100644 --- a/lib/CodeGen/GlobalISel/LegalizerHelper.cpp +++ b/lib/CodeGen/GlobalISel/LegalizerHelper.cpp @@ -868,6 +868,18 @@ LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty) { MI.eraseFromParent(); return Legalized; } + case TargetOpcode::G_ATOMIC_CMPXCHG_WITH_SUCCESS: { + unsigned OldValRes = MI.getOperand(0).getReg(); + unsigned SuccessRes = MI.getOperand(1).getReg(); + unsigned Addr = MI.getOperand(2).getReg(); + unsigned CmpVal = MI.getOperand(3).getReg(); + unsigned NewVal = MI.getOperand(4).getReg(); + MIRBuilder.buildAtomicCmpXchg(OldValRes, Addr, CmpVal, NewVal, + **MI.memoperands_begin()); + MIRBuilder.buildICmp(CmpInst::ICMP_EQ, SuccessRes, OldValRes, CmpVal); + MI.eraseFromParent(); + return Legalized; + } } } diff --git a/lib/CodeGen/GlobalISel/LegalizerInfo.cpp b/lib/CodeGen/GlobalISel/LegalizerInfo.cpp index 1a23b26e7ce11..9c27c59a06549 100644 --- a/lib/CodeGen/GlobalISel/LegalizerInfo.cpp +++ b/lib/CodeGen/GlobalISel/LegalizerInfo.cpp @@ -167,19 +167,25 @@ LegalizerInfo::getAction(const InstrAspect &Aspect) const { assert(TablesInitialized && "backend forgot to call computeTables"); // These *have* to be implemented for now, they're the fundamental basis of // how everything else is transformed. - - // FIXME: the long-term plan calls for expansion in terms of load/store (if - // they're not legal). - if (Aspect.Opcode == TargetOpcode::G_MERGE_VALUES || - Aspect.Opcode == TargetOpcode::G_UNMERGE_VALUES) - return std::make_pair(Legal, Aspect.Type); - if (Aspect.Type.isScalar() || Aspect.Type.isPointer()) return findScalarLegalAction(Aspect); assert(Aspect.Type.isVector()); return findVectorLegalAction(Aspect); } +/// Helper function to get LLT for the given type index. +static LLT getTypeFromTypeIdx(const MachineInstr &MI, + const MachineRegisterInfo &MRI, unsigned OpIdx, + unsigned TypeIdx) { + assert(TypeIdx < MI.getNumOperands() && "Unexpected TypeIdx"); + // G_UNMERGE_VALUES has variable number of operands, but there is only + // one source type and one destination type as all destinations must be the + // same type. So, get the last operand if TypeIdx == 1. + if (MI.getOpcode() == TargetOpcode::G_UNMERGE_VALUES && TypeIdx == 1) + return MRI.getType(MI.getOperand(MI.getNumOperands() - 1).getReg()); + return MRI.getType(MI.getOperand(OpIdx).getReg()); +} + std::tuple LegalizerInfo::getAction(const MachineInstr &MI, const MachineRegisterInfo &MRI) const { @@ -198,7 +204,7 @@ LegalizerInfo::getAction(const MachineInstr &MI, SeenTypes.set(TypeIdx); - LLT Ty = MRI.getType(MI.getOperand(i).getReg()); + LLT Ty = getTypeFromTypeIdx(MI, MRI, i, TypeIdx); auto Action = getAction({MI.getOpcode(), TypeIdx, Ty}); if (Action.first != Legal) return std::make_tuple(Action.first, TypeIdx, Action.second); diff --git a/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp b/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp index 079cd11574bd9..fbcb14d5252de 100644 --- a/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp +++ b/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp @@ -295,6 +295,8 @@ MachineInstrBuilder MachineIRBuilder::buildLoad(unsigned Res, unsigned Addr, MachineMemOperand &MMO) { assert(MRI->getType(Res).isValid() && "invalid operand type"); assert(MRI->getType(Addr).isPointer() && "invalid operand type"); + assert(MMO.getOrdering() == AtomicOrdering::NotAtomic && + "invalid atomic ordering"); return buildInstr(TargetOpcode::G_LOAD) .addDef(Res) @@ -306,6 +308,8 @@ MachineInstrBuilder MachineIRBuilder::buildStore(unsigned Val, unsigned Addr, MachineMemOperand &MMO) { assert(MRI->getType(Val).isValid() && "invalid operand type"); assert(MRI->getType(Addr).isPointer() && "invalid operand type"); + assert(MMO.getOrdering() == AtomicOrdering::NotAtomic && + "invalid atomic ordering"); return buildInstr(TargetOpcode::G_STORE) .addUse(Val) @@ -313,6 +317,34 @@ MachineInstrBuilder MachineIRBuilder::buildStore(unsigned Val, unsigned Addr, .addMemOperand(&MMO); } +MachineInstrBuilder MachineIRBuilder::buildAtomicLoad(unsigned Res, + unsigned Addr, + MachineMemOperand &MMO) { + assert(MRI->getType(Res).isValid() && "invalid operand type"); + assert(MRI->getType(Addr).isPointer() && "invalid operand type"); + assert(MMO.getOrdering() != AtomicOrdering::NotAtomic && + "invalid atomic ordering"); + + return buildInstr(TargetOpcode::G_ATOMIC_LOAD) + .addDef(Res) + .addUse(Addr) + .addMemOperand(&MMO); +} + +MachineInstrBuilder MachineIRBuilder::buildAtomicStore(unsigned Val, + unsigned Addr, + MachineMemOperand &MMO) { + assert(MRI->getType(Val).isValid() && "invalid operand type"); + assert(MRI->getType(Addr).isPointer() && "invalid operand type"); + assert(MMO.getOrdering() != AtomicOrdering::NotAtomic && + "invalid atomic ordering"); + + return buildInstr(TargetOpcode::G_ATOMIC_STORE) + .addUse(Val) + .addUse(Addr) + .addMemOperand(&MMO); +} + MachineInstrBuilder MachineIRBuilder::buildUAdde(unsigned Res, unsigned CarryOut, unsigned Op0, unsigned Op1, @@ -658,6 +690,31 @@ MachineInstrBuilder MachineIRBuilder::buildExtractVectorElement(unsigned Res, .addUse(Idx); } +MachineInstrBuilder +MachineIRBuilder::buildAtomicCmpXchg(unsigned OldValRes, unsigned Addr, + unsigned CmpVal, unsigned NewVal, + MachineMemOperand &MMO) { +#ifndef NDEBUG + LLT OldValResTy = MRI->getType(OldValRes); + LLT AddrTy = MRI->getType(Addr); + LLT CmpValTy = MRI->getType(CmpVal); + LLT NewValTy = MRI->getType(NewVal); + assert(OldValResTy.isScalar() && "invalid operand type"); + assert(AddrTy.isPointer() && "invalid operand type"); + assert(CmpValTy.isValid() && "invalid operand type"); + assert(NewValTy.isValid() && "invalid operand type"); + assert(OldValResTy == CmpValTy && "type mismatch"); + assert(OldValResTy == NewValTy && "type mismatch"); +#endif + + return buildInstr(TargetOpcode::G_ATOMIC_CMPXCHG) + .addDef(OldValRes) + .addUse(Addr) + .addUse(CmpVal) + .addUse(NewVal) + .addMemOperand(&MMO); +} + void MachineIRBuilder::validateTruncExt(unsigned Dst, unsigned Src, bool IsExtend) { #ifndef NDEBUG diff --git a/lib/CodeGen/IfConversion.cpp b/lib/CodeGen/IfConversion.cpp index 567461c19452f..1bac5685ec536 100644 --- a/lib/CodeGen/IfConversion.cpp +++ b/lib/CodeGen/IfConversion.cpp @@ -406,12 +406,12 @@ bool IfConverter::runOnMachineFunction(MachineFunction &MF) { case ICSimpleFalse: { bool isFalse = Kind == ICSimpleFalse; if ((isFalse && DisableSimpleF) || (!isFalse && DisableSimple)) break; - DEBUG(dbgs() << "Ifcvt (Simple" << (Kind == ICSimpleFalse ? - " false" : "") - << "): BB#" << BBI.BB->getNumber() << " (" - << ((Kind == ICSimpleFalse) - ? BBI.FalseBB->getNumber() - : BBI.TrueBB->getNumber()) << ") "); + DEBUG(dbgs() << "Ifcvt (Simple" + << (Kind == ICSimpleFalse ? " false" : "") + << "): " << printMBBReference(*BBI.BB) << " (" + << ((Kind == ICSimpleFalse) ? BBI.FalseBB->getNumber() + : BBI.TrueBB->getNumber()) + << ") "); RetVal = IfConvertSimple(BBI, Kind); DEBUG(dbgs() << (RetVal ? "succeeded!" : "failed!") << "\n"); if (RetVal) { @@ -435,9 +435,9 @@ bool IfConverter::runOnMachineFunction(MachineFunction &MF) { DEBUG(dbgs() << " false"); if (isRev) DEBUG(dbgs() << " rev"); - DEBUG(dbgs() << "): BB#" << BBI.BB->getNumber() << " (T:" - << BBI.TrueBB->getNumber() << ",F:" - << BBI.FalseBB->getNumber() << ") "); + DEBUG(dbgs() << "): " << printMBBReference(*BBI.BB) + << " (T:" << BBI.TrueBB->getNumber() + << ",F:" << BBI.FalseBB->getNumber() << ") "); RetVal = IfConvertTriangle(BBI, Kind); DEBUG(dbgs() << (RetVal ? "succeeded!" : "failed!") << "\n"); if (RetVal) { @@ -453,9 +453,9 @@ bool IfConverter::runOnMachineFunction(MachineFunction &MF) { } case ICDiamond: if (DisableDiamond) break; - DEBUG(dbgs() << "Ifcvt (Diamond): BB#" << BBI.BB->getNumber() << " (T:" - << BBI.TrueBB->getNumber() << ",F:" - << BBI.FalseBB->getNumber() << ") "); + DEBUG(dbgs() << "Ifcvt (Diamond): " << printMBBReference(*BBI.BB) + << " (T:" << BBI.TrueBB->getNumber() + << ",F:" << BBI.FalseBB->getNumber() << ") "); RetVal = IfConvertDiamond(BBI, Kind, NumDups, NumDups2, Token->TClobbersPred, Token->FClobbersPred); @@ -464,10 +464,9 @@ bool IfConverter::runOnMachineFunction(MachineFunction &MF) { break; case ICForkedDiamond: if (DisableForkedDiamond) break; - DEBUG(dbgs() << "Ifcvt (Forked Diamond): BB#" - << BBI.BB->getNumber() << " (T:" - << BBI.TrueBB->getNumber() << ",F:" - << BBI.FalseBB->getNumber() << ") "); + DEBUG(dbgs() << "Ifcvt (Forked Diamond): " << printMBBReference(*BBI.BB) + << " (T:" << BBI.TrueBB->getNumber() + << ",F:" << BBI.FalseBB->getNumber() << ") "); RetVal = IfConvertForkedDiamond(BBI, Kind, NumDups, NumDups2, Token->TClobbersPred, Token->FClobbersPred); diff --git a/lib/CodeGen/ImplicitNullChecks.cpp b/lib/CodeGen/ImplicitNullChecks.cpp index 02c7eeb7a4882..1962b4ca65de8 100644 --- a/lib/CodeGen/ImplicitNullChecks.cpp +++ b/lib/CodeGen/ImplicitNullChecks.cpp @@ -63,13 +63,13 @@ using namespace llvm; static cl::opt PageSize("imp-null-check-page-size", cl::desc("The page size of the target in bytes"), - cl::init(4096)); + cl::init(4096), cl::Hidden); static cl::opt MaxInstsToConsider( "imp-null-max-insts-to-consider", cl::desc("The max number of instructions to consider hoisting loads over " "(the algorithm is quadratic over this number)"), - cl::init(8)); + cl::Hidden, cl::init(8)); #define DEBUG_TYPE "implicit-null-checks" diff --git a/lib/CodeGen/IntrinsicLowering.cpp b/lib/CodeGen/IntrinsicLowering.cpp index c6cc909e25d38..65d9592e5064a 100644 --- a/lib/CodeGen/IntrinsicLowering.cpp +++ b/lib/CodeGen/IntrinsicLowering.cpp @@ -164,9 +164,9 @@ void IntrinsicLowering::AddPrototypes(Module &M) { /// LowerBSWAP - Emit the code to lower bswap of V before the specified /// instruction IP. static Value *LowerBSWAP(LLVMContext &Context, Value *V, Instruction *IP) { - assert(V->getType()->isIntegerTy() && "Can't bswap a non-integer type!"); + assert(V->getType()->isIntOrIntVectorTy() && "Can't bswap a non-integer type!"); - unsigned BitSize = V->getType()->getPrimitiveSizeInBits(); + unsigned BitSize = V->getType()->getScalarSizeInBits(); IRBuilder<> Builder(IP); @@ -190,10 +190,10 @@ static Value *LowerBSWAP(LLVMContext &Context, Value *V, Instruction *IP) { Value *Tmp1 = Builder.CreateLShr(V,ConstantInt::get(V->getType(), 24), "bswap.1"); Tmp3 = Builder.CreateAnd(Tmp3, - ConstantInt::get(Type::getInt32Ty(Context), 0xFF0000), + ConstantInt::get(V->getType(), 0xFF0000), "bswap.and3"); Tmp2 = Builder.CreateAnd(Tmp2, - ConstantInt::get(Type::getInt32Ty(Context), 0xFF00), + ConstantInt::get(V->getType(), 0xFF00), "bswap.and2"); Tmp4 = Builder.CreateOr(Tmp4, Tmp3, "bswap.or1"); Tmp2 = Builder.CreateOr(Tmp2, Tmp1, "bswap.or2"); @@ -221,27 +221,27 @@ static Value *LowerBSWAP(LLVMContext &Context, Value *V, Instruction *IP) { ConstantInt::get(V->getType(), 56), "bswap.1"); Tmp7 = Builder.CreateAnd(Tmp7, - ConstantInt::get(Type::getInt64Ty(Context), + ConstantInt::get(V->getType(), 0xFF000000000000ULL), "bswap.and7"); Tmp6 = Builder.CreateAnd(Tmp6, - ConstantInt::get(Type::getInt64Ty(Context), + ConstantInt::get(V->getType(), 0xFF0000000000ULL), "bswap.and6"); Tmp5 = Builder.CreateAnd(Tmp5, - ConstantInt::get(Type::getInt64Ty(Context), + ConstantInt::get(V->getType(), 0xFF00000000ULL), "bswap.and5"); Tmp4 = Builder.CreateAnd(Tmp4, - ConstantInt::get(Type::getInt64Ty(Context), + ConstantInt::get(V->getType(), 0xFF000000ULL), "bswap.and4"); Tmp3 = Builder.CreateAnd(Tmp3, - ConstantInt::get(Type::getInt64Ty(Context), + ConstantInt::get(V->getType(), 0xFF0000ULL), "bswap.and3"); Tmp2 = Builder.CreateAnd(Tmp2, - ConstantInt::get(Type::getInt64Ty(Context), + ConstantInt::get(V->getType(), 0xFF00ULL), "bswap.and2"); Tmp8 = Builder.CreateOr(Tmp8, Tmp7, "bswap.or1"); diff --git a/lib/CodeGen/LiveDebugVariables.cpp b/lib/CodeGen/LiveDebugVariables.cpp index 97bb7c712f6a7..5f0559b7d9997 100644 --- a/lib/CodeGen/LiveDebugVariables.cpp +++ b/lib/CodeGen/LiveDebugVariables.cpp @@ -1174,7 +1174,7 @@ void UserValue::emitDebugValues(VirtRegMap *VRM, LiveIntervals &LIS, MachineFunction::iterator MBB = LIS.getMBBFromIndex(Start)->getIterator(); SlotIndex MBBEnd = LIS.getMBBEndIdx(&*MBB); - DEBUG(dbgs() << " BB#" << MBB->getNumber() << '-' << MBBEnd); + DEBUG(dbgs() << ' ' << printMBBReference(*MBB) << '-' << MBBEnd); insertDebugValue(&*MBB, Start, Stop, Loc, Spilled, LIS, TII, TRI); // This interval may span multiple basic blocks. // Insert a DBG_VALUE into each one. @@ -1184,7 +1184,7 @@ void UserValue::emitDebugValues(VirtRegMap *VRM, LiveIntervals &LIS, if (++MBB == MFEnd) break; MBBEnd = LIS.getMBBEndIdx(&*MBB); - DEBUG(dbgs() << " BB#" << MBB->getNumber() << '-' << MBBEnd); + DEBUG(dbgs() << ' ' << printMBBReference(*MBB) << '-' << MBBEnd); insertDebugValue(&*MBB, Start, Stop, Loc, Spilled, LIS, TII, TRI); } DEBUG(dbgs() << '\n'); diff --git a/lib/CodeGen/LiveIntervalAnalysis.cpp b/lib/CodeGen/LiveIntervalAnalysis.cpp index c55519387d16b..06807542b346d 100644 --- a/lib/CodeGen/LiveIntervalAnalysis.cpp +++ b/lib/CodeGen/LiveIntervalAnalysis.cpp @@ -323,7 +323,7 @@ void LiveIntervals::computeLiveInRegUnits() { // Create phi-defs at Begin for all live-in registers. SlotIndex Begin = Indexes->getMBBStartIdx(&MBB); - DEBUG(dbgs() << Begin << "\tBB#" << MBB.getNumber()); + DEBUG(dbgs() << Begin << "\t" << printMBBReference(MBB)); for (const auto &LI : MBB.liveins()) { for (MCRegUnitIterator Units(LI.PhysReg, TRI); Units.isValid(); ++Units) { unsigned Unit = *Units; @@ -698,11 +698,11 @@ void LiveIntervals::addKillFlags(const VirtRegMap *VRM) { // Check if any of the regunits are live beyond the end of RI. That could // happen when a physreg is defined as a copy of a virtreg: // - // %eax = COPY %vreg5 - // FOO %vreg5 <--- MI, cancel kill because %eax is live. + // %eax = COPY %5 + // FOO %5 <--- MI, cancel kill because %eax is live. // BAR %eax // - // There should be no kill flag on FOO when %vreg5 is rewritten as %eax. + // There should be no kill flag on FOO when %5 is rewritten as %eax. for (auto &RUP : RU) { const LiveRange &RURange = *RUP.first; LiveRange::const_iterator &I = RUP.second; @@ -719,13 +719,13 @@ void LiveIntervals::addKillFlags(const VirtRegMap *VRM) { // When reading a partial undefined value we must not add a kill flag. // The regalloc might have used the undef lane for something else. // Example: - // %vreg1 = ... ; R32: %vreg1 - // %vreg2:high16 = ... ; R64: %vreg2 - // = read %vreg2 ; R64: %vreg2 - // = read %vreg1 ; R32: %vreg1 - // The flag is correct for %vreg2, but the register allocator may - // assign R0L to %vreg1, and R0 to %vreg2 because the low 32bits of R0 - // are actually never written by %vreg2. After assignment the + // %1 = ... ; R32: %1 + // %2:high16 = ... ; R64: %2 + // = read %2 ; R64: %2 + // = read %1 ; R32: %1 + // The flag is correct for %2, but the register allocator may + // assign R0L to %1, and R0 to %2 because the low 32bits of R0 + // are actually never written by %2. After assignment the // flag at the read instruction is invalid. LaneBitmask DefinedLanesMask; if (!SRs.empty()) { diff --git a/lib/CodeGen/LiveRangeCalc.cpp b/lib/CodeGen/LiveRangeCalc.cpp index 0074a9fd907ec..352d75ec3ae1d 100644 --- a/lib/CodeGen/LiveRangeCalc.cpp +++ b/lib/CodeGen/LiveRangeCalc.cpp @@ -377,7 +377,7 @@ bool LiveRangeCalc::findReachingDefs(LiveRange &LR, MachineBasicBlock &UseMBB, MBB->getParent()->verify(); const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo(); errs() << "The register " << printReg(PhysReg, TRI) - << " needs to be live in to BB#" << MBB->getNumber() + << " needs to be live in to " << printMBBReference(*MBB) << ", but is missing from the live-in list.\n"; report_fatal_error("Invalid global physical register"); } diff --git a/lib/CodeGen/MIRParser/MILexer.cpp b/lib/CodeGen/MIRParser/MILexer.cpp index d23df9c137bf9..ac6969237949f 100644 --- a/lib/CodeGen/MIRParser/MILexer.cpp +++ b/lib/CodeGen/MIRParser/MILexer.cpp @@ -277,6 +277,9 @@ static Cursor maybeLexMachineBasicBlock(Cursor C, MIToken &Token, C.advance(); StringRef Number = NumberRange.upto(C); unsigned StringOffset = PrefixLength + Number.size(); // Drop '%bb.' + // TODO: The format bb.. is supported only when it's not a + // reference. Once we deprecate the format where the irname shows up, we + // should only lex forward if it is a reference. if (C.peek() == '.') { C.advance(); // Skip '.' ++StringOffset; diff --git a/lib/CodeGen/MIRParser/MIParser.cpp b/lib/CodeGen/MIRParser/MIParser.cpp index 9b5539a7ca7f9..de951e42c8f62 100644 --- a/lib/CodeGen/MIRParser/MIParser.cpp +++ b/lib/CodeGen/MIRParser/MIParser.cpp @@ -1344,6 +1344,8 @@ bool MIParser::parseMBBReference(MachineBasicBlock *&MBB) { return error(Twine("use of undefined machine basic block #") + Twine(Number)); MBB = MBBInfo->second; + // TODO: Only parse the name if it's a MachineBasicBlockLabel. Deprecate once + // we drop the from the bb.. format. if (!Token.stringValue().empty() && Token.stringValue() != MBB->getName()) return error(Twine("the name of machine basic block #") + Twine(Number) + " isn't '" + Token.stringValue() + "'"); diff --git a/lib/CodeGen/MIRPrinter.cpp b/lib/CodeGen/MIRPrinter.cpp index 989e0423abe2b..aa0f38036b124 100644 --- a/lib/CodeGen/MIRPrinter.cpp +++ b/lib/CodeGen/MIRPrinter.cpp @@ -75,7 +75,8 @@ using namespace llvm; -static cl::opt SimplifyMIR("simplify-mir", +static cl::opt SimplifyMIR( + "simplify-mir", cl::Hidden, cl::desc("Leave out unnecessary information when printing MIR")); namespace { @@ -156,7 +157,6 @@ class MIPrinter { void print(const MachineBasicBlock &MBB); void print(const MachineInstr &MI); - void printMBBReference(const MachineBasicBlock &MBB); void printIRBlockReference(const BasicBlock &BB); void printIRValueReference(const Value &V); void printStackObjectReference(int FrameIndex); @@ -192,23 +192,10 @@ template <> struct BlockScalarTraits { } // end namespace yaml } // end namespace llvm -static void printRegMIR(unsigned Reg, raw_ostream &OS, - const TargetRegisterInfo *TRI) { - // TODO: Print Stack Slots. - if (!Reg) - OS << '_'; - else if (TargetRegisterInfo::isVirtualRegister(Reg)) - OS << '%' << TargetRegisterInfo::virtReg2Index(Reg); - else if (Reg < TRI->getNumRegs()) - OS << '%' << StringRef(TRI->getName(Reg)).lower(); - else - llvm_unreachable("Can't print this kind of register yet"); -} - static void printRegMIR(unsigned Reg, yaml::StringValue &Dest, const TargetRegisterInfo *TRI) { raw_string_ostream OS(Dest.Value); - printRegMIR(Reg, OS, TRI); + OS << printReg(Reg, TRI); } void MIRPrinter::print(const MachineFunction &MF) { @@ -262,7 +249,7 @@ static void printCustomRegMask(const uint32_t *RegMask, raw_ostream &OS, if (RegMask[I / 32] & (1u << (I % 32))) { if (IsRegInRegMaskFound) OS << ','; - printRegMIR(I, OS, TRI); + OS << printReg(I, TRI); IsRegInRegMaskFound = true; } } @@ -350,13 +337,11 @@ void MIRPrinter::convert(ModuleSlotTracker &MST, YamlMFI.HasMustTailInVarArgFunc = MFI.hasMustTailInVarArgFunc(); if (MFI.getSavePoint()) { raw_string_ostream StrOS(YamlMFI.SavePoint.Value); - MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping) - .printMBBReference(*MFI.getSavePoint()); + StrOS << printMBBReference(*MFI.getSavePoint()); } if (MFI.getRestorePoint()) { raw_string_ostream StrOS(YamlMFI.RestorePoint.Value); - MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping) - .printMBBReference(*MFI.getRestorePoint()); + StrOS << printMBBReference(*MFI.getRestorePoint()); } } @@ -505,8 +490,7 @@ void MIRPrinter::convert(ModuleSlotTracker &MST, Entry.ID = ID++; for (const auto *MBB : Table.MBBs) { raw_string_ostream StrOS(Str); - MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping) - .printMBBReference(*MBB); + StrOS << printMBBReference(*MBB); Entry.Blocks.push_back(StrOS.str()); Str.clear(); } @@ -628,7 +612,7 @@ void MIPrinter::print(const MachineBasicBlock &MBB) { for (auto I = MBB.succ_begin(), E = MBB.succ_end(); I != E; ++I) { if (I != MBB.succ_begin()) OS << ", "; - printMBBReference(**I); + OS << printMBBReference(**I); if (!SimplifyMIR || !canPredictProbs) OS << '(' << format("0x%08" PRIx32, MBB.getSuccProbability(I).getNumerator()) @@ -648,7 +632,7 @@ void MIPrinter::print(const MachineBasicBlock &MBB) { if (!First) OS << ", "; First = false; - printRegMIR(LI.PhysReg, OS, &TRI); + OS << printReg(LI.PhysReg, &TRI); if (!LI.LaneMask.all()) OS << ":0x" << PrintLaneMask(LI.LaneMask); } @@ -776,14 +760,6 @@ void MIPrinter::print(const MachineInstr &MI) { } } -void MIPrinter::printMBBReference(const MachineBasicBlock &MBB) { - OS << "%bb." << MBB.getNumber(); - if (const auto *BB = MBB.getBasicBlock()) { - if (BB->hasName()) - OS << '.' << BB->getName(); - } -} - static void printIRSlotNumber(raw_ostream &OS, int Slot) { if (Slot == -1) OS << ""; @@ -949,7 +925,7 @@ void MIPrinter::print(const MachineInstr &MI, unsigned OpIdx, OS << "early-clobber "; if (Op.isDebug()) OS << "debug-use "; - printRegMIR(Reg, OS, TRI); + OS << printReg(Reg, TRI); // Print the sub register. if (Op.getSubReg() != 0) OS << '.' << TRI->getSubRegIndexName(Op.getSubReg()); @@ -979,7 +955,7 @@ void MIPrinter::print(const MachineInstr &MI, unsigned OpIdx, Op.getFPImm()->printAsOperand(OS, /*PrintType=*/true, MST); break; case MachineOperand::MO_MachineBasicBlock: - printMBBReference(*Op.getMBB()); + OS << printMBBReference(*Op.getMBB()); break; case MachineOperand::MO_FrameIndex: printStackObjectReference(Op.getIndex()); @@ -1041,7 +1017,7 @@ void MIPrinter::print(const MachineInstr &MI, unsigned OpIdx, if (RegMask[Reg / 32] & (1U << (Reg % 32))) { if (IsCommaNeeded) OS << ", "; - printRegMIR(Reg, OS, TRI); + OS << printReg(Reg, TRI); IsCommaNeeded = true; } } @@ -1212,7 +1188,7 @@ static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS, OS << ""; return; } - printRegMIR(Reg, OS, TRI); + OS << printReg(Reg, TRI); } void MIPrinter::print(const MCCFIInstruction &CFI, diff --git a/lib/CodeGen/MachineBasicBlock.cpp b/lib/CodeGen/MachineBasicBlock.cpp index 8863ac2360728..5522d6694e006 100644 --- a/lib/CodeGen/MachineBasicBlock.cpp +++ b/lib/CodeGen/MachineBasicBlock.cpp @@ -70,6 +70,10 @@ raw_ostream &llvm::operator<<(raw_ostream &OS, const MachineBasicBlock &MBB) { return OS; } +Printable llvm::printMBBReference(const MachineBasicBlock &MBB) { + return Printable([&MBB](raw_ostream &OS) { return MBB.printAsOperand(OS); }); +} + /// When an MBB is added to an MF, we need to update the parent pointer of the /// MBB, the MBB numbering, and any instructions in the MBB to be on the right /// operand list for registers. @@ -281,7 +285,7 @@ void MachineBasicBlock::print(raw_ostream &OS, ModuleSlotTracker &MST, if (Indexes) OS << Indexes->getMBBStartIdx(this) << '\t'; - OS << "BB#" << getNumber() << ": "; + OS << printMBBReference(*this) << ": "; const char *Comma = ""; if (const BasicBlock *LBB = getBasicBlock()) { @@ -313,7 +317,7 @@ void MachineBasicBlock::print(raw_ostream &OS, ModuleSlotTracker &MST, if (Indexes) OS << '\t'; OS << " Predecessors according to CFG:"; for (const_pred_iterator PI = pred_begin(), E = pred_end(); PI != E; ++PI) - OS << " BB#" << (*PI)->getNumber(); + OS << " " << printMBBReference(*(*PI)); OS << '\n'; } @@ -334,7 +338,7 @@ void MachineBasicBlock::print(raw_ostream &OS, ModuleSlotTracker &MST, if (Indexes) OS << '\t'; OS << " Successors according to CFG:"; for (const_succ_iterator SI = succ_begin(), E = succ_end(); SI != E; ++SI) { - OS << " BB#" << (*SI)->getNumber(); + OS << " " << printMBBReference(*(*SI)); if (!Probs.empty()) OS << '(' << *getProbabilityIterator(SI) << ')'; } @@ -350,7 +354,7 @@ void MachineBasicBlock::print(raw_ostream &OS, ModuleSlotTracker &MST, void MachineBasicBlock::printAsOperand(raw_ostream &OS, bool /*PrintType*/) const { - OS << "BB#" << getNumber(); + OS << "%bb." << getNumber(); } void MachineBasicBlock::removeLiveIn(MCPhysReg Reg, LaneBitmask LaneMask) { @@ -767,10 +771,9 @@ MachineBasicBlock *MachineBasicBlock::SplitCriticalEdge(MachineBasicBlock *Succ, MachineBasicBlock *NMBB = MF->CreateMachineBasicBlock(); MF->insert(std::next(MachineFunction::iterator(this)), NMBB); - DEBUG(dbgs() << "Splitting critical edge:" - " BB#" << getNumber() - << " -- BB#" << NMBB->getNumber() - << " -- BB#" << Succ->getNumber() << '\n'); + DEBUG(dbgs() << "Splitting critical edge: " << printMBBReference(*this) + << " -- " << printMBBReference(*NMBB) << " -- " + << printMBBReference(*Succ) << '\n'); LiveIntervals *LIS = P.getAnalysisIfAvailable(); SlotIndexes *Indexes = P.getAnalysisIfAvailable(); @@ -1023,8 +1026,8 @@ bool MachineBasicBlock::canSplitCriticalEdge( // case that we can't handle. Since this never happens in properly optimized // code, just skip those edges. if (TBB && TBB == FBB) { - DEBUG(dbgs() << "Won't split critical edge after degenerate BB#" - << getNumber() << '\n'); + DEBUG(dbgs() << "Won't split critical edge after degenerate " + << printMBBReference(*this) << '\n'); return false; } return true; diff --git a/lib/CodeGen/MachineBlockPlacement.cpp b/lib/CodeGen/MachineBlockPlacement.cpp index f0285ea8f8eb3..87af9533b32e8 100644 --- a/lib/CodeGen/MachineBlockPlacement.cpp +++ b/lib/CodeGen/MachineBlockPlacement.cpp @@ -546,7 +546,7 @@ INITIALIZE_PASS_END(MachineBlockPlacement, DEBUG_TYPE, static std::string getBlockName(const MachineBasicBlock *BB) { std::string Result; raw_string_ostream OS(Result); - OS << "BB#" << BB->getNumber(); + OS << printMBBReference(*BB); OS << " ('" << BB->getName() << "')"; OS.flush(); return Result; diff --git a/lib/CodeGen/MachineBranchProbabilityInfo.cpp b/lib/CodeGen/MachineBranchProbabilityInfo.cpp index 21eff9dfff9c9..e4952aaaba06f 100644 --- a/lib/CodeGen/MachineBranchProbabilityInfo.cpp +++ b/lib/CodeGen/MachineBranchProbabilityInfo.cpp @@ -84,7 +84,7 @@ raw_ostream &MachineBranchProbabilityInfo::printEdgeProbability( const MachineBasicBlock *Dst) const { const BranchProbability Prob = getEdgeProbability(Src, Dst); - OS << "edge MBB#" << Src->getNumber() << " -> MBB#" << Dst->getNumber() + OS << "edge " << printMBBReference(*Src) << " -> " << printMBBReference(*Dst) << " probability is " << Prob << (isEdgeHot(Src, Dst) ? " [HOT edge]\n" : "\n"); diff --git a/lib/CodeGen/MachineDominators.cpp b/lib/CodeGen/MachineDominators.cpp index 845e8232477c5..fcfa574ee6c83 100644 --- a/lib/CodeGen/MachineDominators.cpp +++ b/lib/CodeGen/MachineDominators.cpp @@ -26,7 +26,7 @@ static bool VerifyMachineDomInfo = true; static bool VerifyMachineDomInfo = false; #endif static cl::opt VerifyMachineDomInfoX( - "verify-machine-dom-info", cl::location(VerifyMachineDomInfo), + "verify-machine-dom-info", cl::location(VerifyMachineDomInfo), cl::Hidden, cl::desc("Verify machine dominator info (time consuming)")); namespace llvm { diff --git a/lib/CodeGen/MachineFunction.cpp b/lib/CodeGen/MachineFunction.cpp index 1f55b8fa495e8..f0d5eec4deacb 100644 --- a/lib/CodeGen/MachineFunction.cpp +++ b/lib/CodeGen/MachineFunction.cpp @@ -546,7 +546,7 @@ namespace llvm { raw_string_ostream OSS(OutStr); if (isSimple()) { - OSS << "BB#" << Node->getNumber(); + OSS << printMBBReference(*Node); if (const BasicBlock *BB = Node->getBasicBlock()) OSS << ": " << BB->getName(); } else @@ -908,7 +908,7 @@ void MachineJumpTableInfo::print(raw_ostream &OS) const { for (unsigned i = 0, e = JumpTables.size(); i != e; ++i) { OS << " jt#" << i << ": "; for (unsigned j = 0, f = JumpTables[i].MBBs.size(); j != f; ++j) - OS << " BB#" << JumpTables[i].MBBs[j]->getNumber(); + OS << ' ' << printMBBReference(*JumpTables[i].MBBs[j]); } OS << '\n'; diff --git a/lib/CodeGen/MachineLICM.cpp b/lib/CodeGen/MachineLICM.cpp index 3e622b4a23c09..a251a08a51650 100644 --- a/lib/CodeGen/MachineLICM.cpp +++ b/lib/CodeGen/MachineLICM.cpp @@ -563,8 +563,8 @@ void MachineLICM::HoistPostRA(MachineInstr *MI, unsigned Def) { // Now move the instructions to the predecessor, inserting it before any // terminator instructions. - DEBUG(dbgs() << "Hoisting to BB#" << Preheader->getNumber() << " from BB#" - << MI->getParent()->getNumber() << ": " << *MI); + DEBUG(dbgs() << "Hoisting to " << printMBBReference(*Preheader) << " from " + << printMBBReference(*MI->getParent()) << ": " << *MI); // Splice the instruction to the preheader. MachineBasicBlock *MBB = MI->getParent(); @@ -601,14 +601,14 @@ bool MachineLICM::IsGuaranteedToExecute(MachineBasicBlock *BB) { } void MachineLICM::EnterScope(MachineBasicBlock *MBB) { - DEBUG(dbgs() << "Entering BB#" << MBB->getNumber() << '\n'); + DEBUG(dbgs() << "Entering " << printMBBReference(*MBB) << '\n'); // Remember livein register pressure. BackTrace.push_back(RegPressure); } void MachineLICM::ExitScope(MachineBasicBlock *MBB) { - DEBUG(dbgs() << "Exiting BB#" << MBB->getNumber() << '\n'); + DEBUG(dbgs() << "Exiting " << printMBBReference(*MBB) << '\n'); BackTrace.pop_back(); } @@ -1336,9 +1336,9 @@ bool MachineLICM::Hoist(MachineInstr *MI, MachineBasicBlock *Preheader) { DEBUG({ dbgs() << "Hoisting " << *MI; if (MI->getParent()->getBasicBlock()) - dbgs() << " from BB#" << MI->getParent()->getNumber(); + dbgs() << " from " << printMBBReference(*MI->getParent()); if (Preheader->getBasicBlock()) - dbgs() << " to BB#" << Preheader->getNumber(); + dbgs() << " to " << printMBBReference(*Preheader); dbgs() << "\n"; }); diff --git a/lib/CodeGen/MachineOperand.cpp b/lib/CodeGen/MachineOperand.cpp index cb34259fe0142..acd83dde45564 100644 --- a/lib/CodeGen/MachineOperand.cpp +++ b/lib/CodeGen/MachineOperand.cpp @@ -428,7 +428,7 @@ void MachineOperand::print(raw_ostream &OS, ModuleSlotTracker &MST, } break; case MachineOperand::MO_MachineBasicBlock: - OS << "getNumber() << ">"; + OS << printMBBReference(*getMBB()); break; case MachineOperand::MO_FrameIndex: OS << "'; @@ -534,16 +534,7 @@ LLVM_DUMP_METHOD void MachineOperand::dump() const { dbgs() << *this << '\n'; } /// getAddrSpace - Return the LLVM IR address space number that this pointer /// points into. -unsigned MachinePointerInfo::getAddrSpace() const { - if (V.isNull()) - return 0; - - if (V.is()) - return V.get()->getAddressSpace(); - - return cast(V.get()->getType()) - ->getAddressSpace(); -} +unsigned MachinePointerInfo::getAddrSpace() const { return AddrSpace; } /// isDereferenceable - Return true if V is always dereferenceable for /// Offset + Size byte. @@ -586,6 +577,10 @@ MachinePointerInfo MachinePointerInfo::getStack(MachineFunction &MF, return MachinePointerInfo(MF.getPSVManager().getStack(), Offset, ID); } +MachinePointerInfo MachinePointerInfo::getUnknownStack(MachineFunction &MF) { + return MachinePointerInfo(MF.getDataLayout().getAllocaAddrSpace()); +} + MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, Flags f, uint64_t s, unsigned int a, const AAMDNodes &AAInfo, diff --git a/lib/CodeGen/MachineOptimizationRemarkEmitter.cpp b/lib/CodeGen/MachineOptimizationRemarkEmitter.cpp index ecc569dab8357..91205d2f01e59 100644 --- a/lib/CodeGen/MachineOptimizationRemarkEmitter.cpp +++ b/lib/CodeGen/MachineOptimizationRemarkEmitter.cpp @@ -53,10 +53,9 @@ void MachineOptimizationRemarkEmitter::emit( LLVMContext &Ctx = MF.getFunction()->getContext(); - // If a diagnostic has a hotness value, then only emit it if its hotness - // meets the threshold. - if (OptDiag.getHotness() && - *OptDiag.getHotness() < Ctx.getDiagnosticsHotnessThreshold()) { + // Only emit it if its hotness meets the threshold. + if (OptDiag.getHotness().getValueOr(0) < + Ctx.getDiagnosticsHotnessThreshold()) { return; } diff --git a/lib/CodeGen/MachineOutliner.cpp b/lib/CodeGen/MachineOutliner.cpp index 055cef36e0ae0..435ece34a19f0 100644 --- a/lib/CodeGen/MachineOutliner.cpp +++ b/lib/CodeGen/MachineOutliner.cpp @@ -939,17 +939,48 @@ unsigned MachineOutliner::findCandidates( SuffixTreeNode *M = ChildPair.second; if (M && M->IsInTree && M->isLeaf()) { - // Each sequence is over [StartIt, EndIt]. - MachineBasicBlock::iterator StartIt = Mapper.InstrList[M->SuffixIdx]; - MachineBasicBlock::iterator EndIt = - Mapper.InstrList[M->SuffixIdx + StringLen - 1]; - - CandidatesForRepeatedSeq.emplace_back(M->SuffixIdx, StringLen, - FunctionList.size()); - RepeatedSequenceLocs.emplace_back(std::make_pair(StartIt, EndIt)); - // Never visit this leaf again. M->IsInTree = false; + unsigned StartIdx = M->SuffixIdx; + unsigned EndIdx = StartIdx + StringLen - 1; + + // Trick: Discard some candidates that would be incompatible with the + // ones we've already found for this sequence. This will save us some + // work in candidate selection. + // + // If two candidates overlap, then we can't outline them both. This + // happens when we have candidates that look like, say + // + // AA (where each "A" is an instruction). + // + // We might have some portion of the module that looks like this: + // AAAAAA (6 A's) + // + // In this case, there are 5 different copies of "AA" in this range, but + // at most 3 can be outlined. If only outlining 3 of these is going to + // be unbeneficial, then we ought to not bother. + // + // Note that two things DON'T overlap when they look like this: + // start1...end1 .... start2...end2 + // That is, one must either + // * End before the other starts + // * Start after the other ends + if (std::all_of(CandidatesForRepeatedSeq.begin(), + CandidatesForRepeatedSeq.end(), + [&StartIdx, &EndIdx](const Candidate &C) { + return (EndIdx < C.getStartIdx() || + StartIdx > C.getEndIdx()); + })) { + // It doesn't overlap with anything, so we can outline it. + // Each sequence is over [StartIt, EndIt]. + MachineBasicBlock::iterator StartIt = Mapper.InstrList[StartIdx]; + MachineBasicBlock::iterator EndIt = Mapper.InstrList[EndIdx]; + + // Save the candidate and its location. + CandidatesForRepeatedSeq.emplace_back(StartIdx, StringLen, + FunctionList.size()); + RepeatedSequenceLocs.emplace_back(std::make_pair(StartIt, EndIt)); + } } } @@ -961,8 +992,8 @@ unsigned MachineOutliner::findCandidates( std::vector Seq; for (unsigned i = Leaf->SuffixIdx; i < Leaf->SuffixIdx + StringLen; i++) Seq.push_back(ST.Str[i]); - OutlinedFunction OF(FunctionList.size(), Parent.OccurrenceCount, Seq, - MInfo); + OutlinedFunction OF(FunctionList.size(), CandidatesForRepeatedSeq.size(), + Seq, MInfo); unsigned Benefit = OF.getBenefit(); // Is it better to outline this candidate than not? diff --git a/lib/CodeGen/MachineScheduler.cpp b/lib/CodeGen/MachineScheduler.cpp index 6aaacb479feb7..3e796cc3add97 100644 --- a/lib/CodeGen/MachineScheduler.cpp +++ b/lib/CodeGen/MachineScheduler.cpp @@ -98,7 +98,7 @@ static cl::opt MISchedCutoff("misched-cutoff", cl::Hidden, static cl::opt SchedOnlyFunc("misched-only-func", cl::Hidden, cl::desc("Only schedule this function")); static cl::opt SchedOnlyBlock("misched-only-block", cl::Hidden, - cl::desc("Only schedule this MBB#")); + cl::desc("Only schedule this MBB#")); #else static bool ViewMISchedDAGs = false; #endif // NDEBUG @@ -548,15 +548,14 @@ void MachineSchedulerBase::scheduleRegions(ScheduleDAGInstrs &Scheduler, continue; } DEBUG(dbgs() << "********** MI Scheduling **********\n"); - DEBUG(dbgs() << MF->getName() - << ":BB#" << MBB->getNumber() << " " << MBB->getName() - << "\n From: " << *I << " To: "; + DEBUG(dbgs() << MF->getName() << ":" << printMBBReference(*MBB) << " " + << MBB->getName() << "\n From: " << *I << " To: "; if (RegionEnd != MBB->end()) dbgs() << *RegionEnd; else dbgs() << "End"; dbgs() << " RegionInstrs: " << NumRegionInstrs << '\n'); if (DumpCriticalPathLength) { errs() << MF->getName(); - errs() << ":BB# " << MBB->getNumber(); + errs() << ":%bb. " << MBB->getNumber(); errs() << " " << MBB->getName() << " \n"; } @@ -823,11 +822,11 @@ void ScheduleDAGMI::schedule() { placeDebugValues(); DEBUG({ - unsigned BBNum = begin()->getParent()->getNumber(); - dbgs() << "*** Final schedule for BB#" << BBNum << " ***\n"; - dumpSchedule(); - dbgs() << '\n'; - }); + dbgs() << "*** Final schedule for " + << printMBBReference(*begin()->getParent()) << " ***\n"; + dumpSchedule(); + dbgs() << '\n'; + }); } /// Apply each ScheduleDAGMutation step in order. @@ -1261,11 +1260,11 @@ void ScheduleDAGMILive::schedule() { placeDebugValues(); DEBUG({ - unsigned BBNum = begin()->getParent()->getNumber(); - dbgs() << "*** Final schedule for BB#" << BBNum << " ***\n"; - dumpSchedule(); - dbgs() << '\n'; - }); + dbgs() << "*** Final schedule for " + << printMBBReference(*begin()->getParent()) << " ***\n"; + dumpSchedule(); + dbgs() << '\n'; + }); } /// Build the DAG and setup three register pressure trackers. diff --git a/lib/CodeGen/MachineSink.cpp b/lib/CodeGen/MachineSink.cpp index 11257d98e3754..7857084c4e639 100644 --- a/lib/CodeGen/MachineSink.cpp +++ b/lib/CodeGen/MachineSink.cpp @@ -243,17 +243,17 @@ MachineSinking::AllUsesDominatedByBlock(unsigned Reg, // into and they are all PHI nodes. In this case, machine-sink must break // the critical edge first. e.g. // - // BB#1: derived from LLVM BB %bb4.preheader - // Predecessors according to CFG: BB#0 + // %bb.1: derived from LLVM BB %bb4.preheader + // Predecessors according to CFG: %bb.0 // ... // %reg16385 = DEC64_32r %reg16437, %eflags // ... - // JE_4 , %eflags - // Successors according to CFG: BB#37 BB#2 + // JE_4 <%bb.37>, %eflags + // Successors according to CFG: %bb.37 %bb.2 // - // BB#2: derived from LLVM BB %bb.nph - // Predecessors according to CFG: BB#0 BB#1 - // %reg16386 = PHI %reg16434, , %reg16385, + // %bb.2: derived from LLVM BB %bb.nph + // Predecessors according to CFG: %bb.0 %bb.1 + // %reg16386 = PHI %reg16434, %bb.0, %reg16385, %bb.1 BreakPHIEdge = true; for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) { MachineInstr *UseInst = MO.getParent(); @@ -321,10 +321,10 @@ bool MachineSinking::runOnMachineFunction(MachineFunction &MF) { for (auto &Pair : ToSplit) { auto NewSucc = Pair.first->SplitCriticalEdge(Pair.second, *this); if (NewSucc != nullptr) { - DEBUG(dbgs() << " *** Splitting critical edge:" - " BB#" << Pair.first->getNumber() - << " -- BB#" << NewSucc->getNumber() - << " -- BB#" << Pair.second->getNumber() << '\n'); + DEBUG(dbgs() << " *** Splitting critical edge: " + << printMBBReference(*Pair.first) << " -- " + << printMBBReference(*NewSucc) << " -- " + << printMBBReference(*Pair.second) << '\n'); MadeChange = true; ++NumSplit; } else @@ -460,33 +460,33 @@ bool MachineSinking::PostponeSplitCriticalEdge(MachineInstr &MI, // It's not always legal to break critical edges and sink the computation // to the edge. // - // BB#1: + // %bb.1: // v1024 - // Beq BB#3 + // Beq %bb.3 // - // BB#2: + // %bb.2: // ... no uses of v1024 // - // BB#3: + // %bb.3: // ... // = v1024 // - // If BB#1 -> BB#3 edge is broken and computation of v1024 is inserted: + // If %bb.1 -> %bb.3 edge is broken and computation of v1024 is inserted: // - // BB#1: + // %bb.1: // ... - // Bne BB#2 - // BB#4: + // Bne %bb.2 + // %bb.4: // v1024 = - // B BB#3 - // BB#2: + // B %bb.3 + // %bb.2: // ... no uses of v1024 // - // BB#3: + // %bb.3: // ... // = v1024 // - // This is incorrect since v1024 is not computed along the BB#1->BB#2->BB#3 + // This is incorrect since v1024 is not computed along the %bb.1->%bb.2->%bb.3 // flow. We need to ensure the new basic block where the computation is // sunk to dominates all the uses. // It's only legal to break critical edge and sink the computation to the diff --git a/lib/CodeGen/MachineTraceMetrics.cpp b/lib/CodeGen/MachineTraceMetrics.cpp index 453b47b71f7f4..d81c6f8a31e1f 100644 --- a/lib/CodeGen/MachineTraceMetrics.cpp +++ b/lib/CodeGen/MachineTraceMetrics.cpp @@ -396,7 +396,8 @@ MachineTraceMetrics::getEnsemble(MachineTraceMetrics::Strategy strategy) { } void MachineTraceMetrics::invalidate(const MachineBasicBlock *MBB) { - DEBUG(dbgs() << "Invalidate traces through BB#" << MBB->getNumber() << '\n'); + DEBUG(dbgs() << "Invalidate traces through " << printMBBReference(*MBB) + << '\n'); BlockInfo[MBB->getNumber()].invalidate(); for (unsigned i = 0; i != TS_NumStrategies; ++i) if (Ensembles[i]) @@ -476,8 +477,8 @@ class po_iterator_storage { /// Compute the trace through MBB. void MachineTraceMetrics::Ensemble::computeTrace(const MachineBasicBlock *MBB) { - DEBUG(dbgs() << "Computing " << getName() << " trace through BB#" - << MBB->getNumber() << '\n'); + DEBUG(dbgs() << "Computing " << getName() << " trace through " + << printMBBReference(*MBB) << '\n'); // Set up loop bounds for the backwards post-order traversal. LoopBounds Bounds(BlockInfo, MTM.Loops); @@ -485,13 +486,13 @@ void MachineTraceMetrics::Ensemble::computeTrace(const MachineBasicBlock *MBB) { Bounds.Downward = false; Bounds.Visited.clear(); for (auto I : inverse_post_order_ext(MBB, Bounds)) { - DEBUG(dbgs() << " pred for BB#" << I->getNumber() << ": "); + DEBUG(dbgs() << " pred for " << printMBBReference(*I) << ": "); TraceBlockInfo &TBI = BlockInfo[I->getNumber()]; // All the predecessors have been visited, pick the preferred one. TBI.Pred = pickTracePred(I); DEBUG({ if (TBI.Pred) - dbgs() << "BB#" << TBI.Pred->getNumber() << '\n'; + dbgs() << printMBBReference(*TBI.Pred) << '\n'; else dbgs() << "null\n"; }); @@ -503,13 +504,13 @@ void MachineTraceMetrics::Ensemble::computeTrace(const MachineBasicBlock *MBB) { Bounds.Downward = true; Bounds.Visited.clear(); for (auto I : post_order_ext(MBB, Bounds)) { - DEBUG(dbgs() << " succ for BB#" << I->getNumber() << ": "); + DEBUG(dbgs() << " succ for " << printMBBReference(*I) << ": "); TraceBlockInfo &TBI = BlockInfo[I->getNumber()]; // All the successors have been visited, pick the preferred one. TBI.Succ = pickTraceSucc(I); DEBUG({ if (TBI.Succ) - dbgs() << "BB#" << TBI.Succ->getNumber() << '\n'; + dbgs() << printMBBReference(*TBI.Succ) << '\n'; else dbgs() << "null\n"; }); @@ -530,8 +531,8 @@ MachineTraceMetrics::Ensemble::invalidate(const MachineBasicBlock *BadMBB) { WorkList.push_back(BadMBB); do { const MachineBasicBlock *MBB = WorkList.pop_back_val(); - DEBUG(dbgs() << "Invalidate BB#" << MBB->getNumber() << ' ' << getName() - << " height.\n"); + DEBUG(dbgs() << "Invalidate " << printMBBReference(*MBB) << ' ' + << getName() << " height.\n"); // Find any MBB predecessors that have MBB as their preferred successor. // They are the only ones that need to be invalidated. for (const MachineBasicBlock *Pred : MBB->predecessors()) { @@ -555,8 +556,8 @@ MachineTraceMetrics::Ensemble::invalidate(const MachineBasicBlock *BadMBB) { WorkList.push_back(BadMBB); do { const MachineBasicBlock *MBB = WorkList.pop_back_val(); - DEBUG(dbgs() << "Invalidate BB#" << MBB->getNumber() << ' ' << getName() - << " depth.\n"); + DEBUG(dbgs() << "Invalidate " << printMBBReference(*MBB) << ' ' + << getName() << " depth.\n"); // Find any MBB successors that have MBB as their preferred predecessor. // They are the only ones that need to be invalidated. for (const MachineBasicBlock *Succ : MBB->successors()) { @@ -859,7 +860,7 @@ computeInstrDepths(const MachineBasicBlock *MBB) { // Go through trace blocks in top-down order, stopping after the center block. while (!Stack.empty()) { MBB = Stack.pop_back_val(); - DEBUG(dbgs() << "\nDepths for BB#" << MBB->getNumber() << ":\n"); + DEBUG(dbgs() << "\nDepths for " << printMBBReference(*MBB) << ":\n"); TraceBlockInfo &TBI = BlockInfo[MBB->getNumber()]; TBI.HasValidInstrDepths = true; TBI.CriticalPath = 0; @@ -1044,7 +1045,7 @@ computeInstrHeights(const MachineBasicBlock *MBB) { SmallVector Deps; for (;!Stack.empty(); Stack.pop_back()) { MBB = Stack.back(); - DEBUG(dbgs() << "Heights for BB#" << MBB->getNumber() << ":\n"); + DEBUG(dbgs() << "Heights for " << printMBBReference(*MBB) << ":\n"); TraceBlockInfo &TBI = BlockInfo[MBB->getNumber()]; TBI.HasValidInstrHeights = true; TBI.CriticalPath = 0; @@ -1131,7 +1132,7 @@ computeInstrHeights(const MachineBasicBlock *MBB) { // Update virtual live-in heights. They were added by addLiveIns() with a 0 // height because the final height isn't known until now. - DEBUG(dbgs() << "BB#" << MBB->getNumber() << " Live-ins:"); + DEBUG(dbgs() << printMBBReference(*MBB) << " Live-ins:"); for (LiveInReg &LIR : TBI.LiveIns) { const MachineInstr *DefMI = MTM.MRI->getVRegDef(LIR.Reg); LIR.Height = Heights.lookup(DefMI); @@ -1289,7 +1290,7 @@ bool MachineTraceMetrics::Trace::isDepInTrace(const MachineInstr &DefMI, void MachineTraceMetrics::Ensemble::print(raw_ostream &OS) const { OS << getName() << " ensemble:\n"; for (unsigned i = 0, e = BlockInfo.size(); i != e; ++i) { - OS << " BB#" << i << '\t'; + OS << " %bb." << i << '\t'; BlockInfo[i].print(OS); OS << '\n'; } @@ -1299,10 +1300,10 @@ void MachineTraceMetrics::TraceBlockInfo::print(raw_ostream &OS) const { if (hasValidDepth()) { OS << "depth=" << InstrDepth; if (Pred) - OS << " pred=BB#" << Pred->getNumber(); + OS << " pred=" << printMBBReference(*Pred); else OS << " pred=null"; - OS << " head=BB#" << Head; + OS << " head=%bb." << Head; if (HasValidInstrDepths) OS << " +instrs"; } else @@ -1311,10 +1312,10 @@ void MachineTraceMetrics::TraceBlockInfo::print(raw_ostream &OS) const { if (hasValidHeight()) { OS << "height=" << InstrHeight; if (Succ) - OS << " succ=BB#" << Succ->getNumber(); + OS << " succ=" << printMBBReference(*Succ); else OS << " succ=null"; - OS << " tail=BB#" << Tail; + OS << " tail=%bb." << Tail; if (HasValidInstrHeights) OS << " +instrs"; } else @@ -1326,18 +1327,18 @@ void MachineTraceMetrics::TraceBlockInfo::print(raw_ostream &OS) const { void MachineTraceMetrics::Trace::print(raw_ostream &OS) const { unsigned MBBNum = &TBI - &TE.BlockInfo[0]; - OS << TE.getName() << " trace BB#" << TBI.Head << " --> BB#" << MBBNum - << " --> BB#" << TBI.Tail << ':'; + OS << TE.getName() << " trace %bb." << TBI.Head << " --> %bb." << MBBNum + << " --> %bb." << TBI.Tail << ':'; if (TBI.hasValidHeight() && TBI.hasValidDepth()) OS << ' ' << getInstrCount() << " instrs."; if (TBI.HasValidInstrDepths && TBI.HasValidInstrHeights) OS << ' ' << TBI.CriticalPath << " cycles."; const MachineTraceMetrics::TraceBlockInfo *Block = &TBI; - OS << "\nBB#" << MBBNum; + OS << "\n%bb." << MBBNum; while (Block->hasValidDepth() && Block->Pred) { unsigned Num = Block->Pred->getNumber(); - OS << " <- BB#" << Num; + OS << " <- " << printMBBReference(*Block->Pred); Block = &TE.BlockInfo[Num]; } @@ -1345,7 +1346,7 @@ void MachineTraceMetrics::Trace::print(raw_ostream &OS) const { OS << "\n "; while (Block->hasValidHeight() && Block->Succ) { unsigned Num = Block->Succ->getNumber(); - OS << " -> BB#" << Num; + OS << " -> " << printMBBReference(*Block->Succ); Block = &TE.BlockInfo[Num]; } OS << '\n'; diff --git a/lib/CodeGen/MachineVerifier.cpp b/lib/CodeGen/MachineVerifier.cpp index 4f6eb428c8eac..6834059234eed 100644 --- a/lib/CodeGen/MachineVerifier.cpp +++ b/lib/CodeGen/MachineVerifier.cpp @@ -471,9 +471,8 @@ void MachineVerifier::report(const char *msg, const MachineFunction *MF) { void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB) { assert(MBB); report(msg, MBB->getParent()); - errs() << "- basic block: BB#" << MBB->getNumber() - << ' ' << MBB->getName() - << " (" << (const void*)MBB << ')'; + errs() << "- basic block: " << printMBBReference(*MBB) << ' ' + << MBB->getName() << " (" << (const void *)MBB << ')'; if (Indexes) errs() << " [" << Indexes->getMBBStartIdx(MBB) << ';' << Indexes->getMBBEndIdx(MBB) << ')'; @@ -619,8 +618,8 @@ MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) { report("MBB has successor that isn't part of the function.", MBB); if (!MBBInfoMap[*I].Preds.count(MBB)) { report("Inconsistent CFG", MBB); - errs() << "MBB is not in the predecessor list of the successor BB#" - << (*I)->getNumber() << ".\n"; + errs() << "MBB is not in the predecessor list of the successor " + << printMBBReference(*(*I)) << ".\n"; } } @@ -631,8 +630,8 @@ MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) { report("MBB has predecessor that isn't part of the function.", MBB); if (!MBBInfoMap[*I].Succs.count(MBB)) { report("Inconsistent CFG", MBB); - errs() << "MBB is not in the successor list of the predecessor BB#" - << (*I)->getNumber() << ".\n"; + errs() << "MBB is not in the successor list of the predecessor " + << printMBBReference(*(*I)) << ".\n"; } } @@ -1097,8 +1096,8 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) { TII->getRegClass(MCID, MONum, TRI, *MF)) { if (!DRC->contains(Reg)) { report("Illegal physical register for instruction", MO, MONum); - errs() << TRI->getName(Reg) << " is not a " - << TRI->getRegClassName(DRC) << " register.\n"; + errs() << printReg(Reg, TRI) << " is not a " + << TRI->getRegClassName(DRC) << " register.\n"; } } } @@ -1653,7 +1652,8 @@ void MachineVerifier::checkPHIOps(const MachineBasicBlock &MBB) { if (MInfo.reachable) { seen.insert(&Pre); BBInfo &PrInfo = MBBInfoMap[&Pre]; - if (PrInfo.reachable && !PrInfo.isLiveOut(MO0.getReg())) + if (!MO0.isUndef() && PrInfo.reachable && + !PrInfo.isLiveOut(MO0.getReg())) report("PHI operand is not live-out from predecessor", &MO0, I); } } @@ -1663,8 +1663,8 @@ void MachineVerifier::checkPHIOps(const MachineBasicBlock &MBB) { for (MachineBasicBlock *Pred : MBB.predecessors()) { if (!seen.count(Pred)) { report("Missing PHI operand", &Phi); - errs() << "BB#" << Pred->getNumber() - << " is a predecessor according to the CFG.\n"; + errs() << printMBBReference(*Pred) + << " is a predecessor according to the CFG.\n"; } } } @@ -1689,7 +1689,7 @@ void MachineVerifier::visitMachineFunctionAfter() { if (MInfo.regsKilled.count(*I)) { report("Virtual register killed in block, but needed live out.", &MBB); errs() << "Virtual register " << printReg(*I) - << " is used after the block.\n"; + << " is used after the block.\n"; } } @@ -1722,13 +1722,13 @@ void MachineVerifier::verifyLiveVariables() { if (!VI.AliveBlocks.test(MBB.getNumber())) { report("LiveVariables: Block missing from AliveBlocks", &MBB); errs() << "Virtual register " << printReg(Reg) - << " must be live through the block.\n"; + << " must be live through the block.\n"; } } else { if (VI.AliveBlocks.test(MBB.getNumber())) { report("LiveVariables: Block should not be in AliveBlocks", &MBB); errs() << "Virtual register " << printReg(Reg) - << " is not needed live through the block.\n"; + << " is not needed live through the block.\n"; } } } @@ -1961,7 +1961,7 @@ void MachineVerifier::verifyLiveRangeSegment(const LiveRange &LR, if (MOI->isDef()) { if (Sub != 0) { hasSubRegDef = true; - // An operand vreg0:sub0 reads vreg0:sub1..n. Invert the lane + // An operand %0:sub0 reads %0:sub1..n. Invert the lane // mask for subregister defs. Read-undef defs will be handled by // readsReg below. SLM = ~SLM; @@ -2038,8 +2038,8 @@ void MachineVerifier::verifyLiveRangeSegment(const LiveRange &LR, report("Register not marked live out of predecessor", *PI); report_context(LR, Reg, LaneMask); report_context(*VNI); - errs() << " live into BB#" << MFI->getNumber() - << '@' << LiveInts->getMBBStartIdx(&*MFI) << ", not live before " + errs() << " live into " << printMBBReference(*MFI) << '@' + << LiveInts->getMBBStartIdx(&*MFI) << ", not live before " << PEnd << '\n'; continue; } @@ -2048,9 +2048,9 @@ void MachineVerifier::verifyLiveRangeSegment(const LiveRange &LR, if (!IsPHI && PVNI != VNI) { report("Different value live out of predecessor", *PI); report_context(LR, Reg, LaneMask); - errs() << "Valno #" << PVNI->id << " live out of BB#" - << (*PI)->getNumber() << '@' << PEnd << "\nValno #" << VNI->id - << " live into BB#" << MFI->getNumber() << '@' + errs() << "Valno #" << PVNI->id << " live out of " + << printMBBReference(*(*PI)) << '@' << PEnd << "\nValno #" + << VNI->id << " live into " << printMBBReference(*MFI) << '@' << LiveInts->getMBBStartIdx(&*MFI) << '\n'; } } @@ -2201,11 +2201,11 @@ void MachineVerifier::verifyStackFrame() { (SPState[(*I)->getNumber()].ExitValue != BBState.EntryValue || SPState[(*I)->getNumber()].ExitIsSetup != BBState.EntryIsSetup)) { report("The exit stack state of a predecessor is inconsistent.", MBB); - errs() << "Predecessor BB#" << (*I)->getNumber() << " has exit state (" - << SPState[(*I)->getNumber()].ExitValue << ", " - << SPState[(*I)->getNumber()].ExitIsSetup - << "), while BB#" << MBB->getNumber() << " has entry state (" - << BBState.EntryValue << ", " << BBState.EntryIsSetup << ").\n"; + errs() << "Predecessor " << printMBBReference(*(*I)) + << " has exit state (" << SPState[(*I)->getNumber()].ExitValue + << ", " << SPState[(*I)->getNumber()].ExitIsSetup << "), while " + << printMBBReference(*MBB) << " has entry state (" + << BBState.EntryValue << ", " << BBState.EntryIsSetup << ").\n"; } } @@ -2217,11 +2217,11 @@ void MachineVerifier::verifyStackFrame() { (SPState[(*I)->getNumber()].EntryValue != BBState.ExitValue || SPState[(*I)->getNumber()].EntryIsSetup != BBState.ExitIsSetup)) { report("The entry stack state of a successor is inconsistent.", MBB); - errs() << "Successor BB#" << (*I)->getNumber() << " has entry state (" - << SPState[(*I)->getNumber()].EntryValue << ", " - << SPState[(*I)->getNumber()].EntryIsSetup - << "), while BB#" << MBB->getNumber() << " has exit state (" - << BBState.ExitValue << ", " << BBState.ExitIsSetup << ").\n"; + errs() << "Successor " << printMBBReference(*(*I)) + << " has entry state (" << SPState[(*I)->getNumber()].EntryValue + << ", " << SPState[(*I)->getNumber()].EntryIsSetup << "), while " + << printMBBReference(*MBB) << " has exit state (" + << BBState.ExitValue << ", " << BBState.ExitIsSetup << ").\n"; } } diff --git a/lib/CodeGen/PHIElimination.cpp b/lib/CodeGen/PHIElimination.cpp index 864d6d547caa7..82bbe1528c86d 100644 --- a/lib/CodeGen/PHIElimination.cpp +++ b/lib/CodeGen/PHIElimination.cpp @@ -593,9 +593,9 @@ bool PHIElimination::SplitPHIEdges(MachineFunction &MF, if (!ShouldSplit && !NoPhiElimLiveOutEarlyExit) continue; if (ShouldSplit) { - DEBUG(dbgs() << printReg(Reg) << " live-out before critical edge BB#" - << PreMBB->getNumber() << " -> BB#" << MBB.getNumber() - << ": " << *BBI); + DEBUG(dbgs() << printReg(Reg) << " live-out before critical edge " + << printMBBReference(*PreMBB) << " -> " + << printMBBReference(MBB) << ": " << *BBI); } // If Reg is not live-in to MBB, it means it must be live-in to some diff --git a/lib/CodeGen/PeepholeOptimizer.cpp b/lib/CodeGen/PeepholeOptimizer.cpp index dfad7615bcaa5..e4c2aa464781e 100644 --- a/lib/CodeGen/PeepholeOptimizer.cpp +++ b/lib/CodeGen/PeepholeOptimizer.cpp @@ -1453,10 +1453,10 @@ bool PeepholeOptimizer::foldImmediate( // only the first copy is considered. // // e.g. -// %vreg1 = COPY %vreg0 -// %vreg2 = COPY %vreg0:sub1 +// %1 = COPY %0 +// %2 = COPY %0:sub1 // -// Should replace %vreg2 uses with %vreg1:sub1 +// Should replace %2 uses with %1:sub1 bool PeepholeOptimizer::foldRedundantCopy( MachineInstr *MI, SmallSet &CopySrcRegs, DenseMap &CopyMIs) { @@ -1621,16 +1621,16 @@ bool PeepholeOptimizer::findTargetRecurrence( /// from the phi. For example, if there is a recurrence of /// /// LoopHeader: -/// %vreg1 = phi(%vreg0, %vreg100) +/// %1 = phi(%0, %100) /// LoopLatch: -/// %vreg0 = ADD %vreg2, %vreg1 +/// %0 = ADD %2, %1 /// -/// , the fact that vreg0 and vreg2 are in the same tied operands set makes +/// , the fact that %0 and %2 are in the same tied operands set makes /// the coalescing of copy instruction generated from the phi in -/// LoopHeader(i.e. %vreg1 = COPY %vreg0) impossible, because %vreg1 and -/// %vreg2 have overlapping live range. This introduces additional move -/// instruction to the final assembly. However, if we commute %vreg2 and -/// %vreg1 of ADD instruction, the redundant move instruction can be +/// LoopHeader(i.e. %1 = COPY %0) impossible, because %1 and +/// %2 have overlapping live range. This introduces additional move +/// instruction to the final assembly. However, if we commute %2 and +/// %1 of ADD instruction, the redundant move instruction can be /// avoided. bool PeepholeOptimizer::optimizeRecurrence(MachineInstr &PHI) { SmallSet TargetRegs; diff --git a/lib/CodeGen/PostRASchedulerList.cpp b/lib/CodeGen/PostRASchedulerList.cpp index 673dc37904fe0..81dd6ef2444ff 100644 --- a/lib/CodeGen/PostRASchedulerList.cpp +++ b/lib/CodeGen/PostRASchedulerList.cpp @@ -322,8 +322,8 @@ bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) { static int bbcnt = 0; if (bbcnt++ % DebugDiv != DebugMod) continue; - dbgs() << "*** DEBUG scheduling " << Fn.getName() - << ":BB#" << MBB.getNumber() << " ***\n"; + dbgs() << "*** DEBUG scheduling " << Fn.getName() << ":" + << printMBBReference(MBB) << " ***\n"; } #endif diff --git a/lib/CodeGen/ProcessImplicitDefs.cpp b/lib/CodeGen/ProcessImplicitDefs.cpp index 7fbf7ddde0b61..48b48c5f6499c 100644 --- a/lib/CodeGen/ProcessImplicitDefs.cpp +++ b/lib/CodeGen/ProcessImplicitDefs.cpp @@ -154,7 +154,7 @@ bool ProcessImplicitDefs::runOnMachineFunction(MachineFunction &MF) { if (WorkList.empty()) continue; - DEBUG(dbgs() << "BB#" << MFI->getNumber() << " has " << WorkList.size() + DEBUG(dbgs() << printMBBReference(*MFI) << " has " << WorkList.size() << " implicit defs.\n"); Changed = true; diff --git a/lib/CodeGen/RegAllocBase.cpp b/lib/CodeGen/RegAllocBase.cpp index 6b67fd85667f2..f41a3ad000d74 100644 --- a/lib/CodeGen/RegAllocBase.cpp +++ b/lib/CodeGen/RegAllocBase.cpp @@ -40,8 +40,8 @@ STATISTIC(NumNewQueued , "Number of new live ranges queued"); // Temporary verification option until we can put verification inside // MachineVerifier. static cl::opt -VerifyRegAlloc("verify-regalloc", cl::location(RegAllocBase::VerifyEnabled), - cl::desc("Verify during register allocation")); + VerifyRegAlloc("verify-regalloc", cl::location(RegAllocBase::VerifyEnabled), + cl::Hidden, cl::desc("Verify during register allocation")); const char RegAllocBase::TimerGroupName[] = "regalloc"; const char RegAllocBase::TimerGroupDescription[] = "Register Allocation"; diff --git a/lib/CodeGen/RegAllocBasic.cpp b/lib/CodeGen/RegAllocBasic.cpp index b38373d104998..3d60f3101fcbf 100644 --- a/lib/CodeGen/RegAllocBasic.cpp +++ b/lib/CodeGen/RegAllocBasic.cpp @@ -219,8 +219,8 @@ bool RABasic::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg, Intfs.push_back(Intf); } } - DEBUG(dbgs() << "spilling " << TRI->getName(PhysReg) << - " interferences with " << VirtReg << "\n"); + DEBUG(dbgs() << "spilling " << printReg(PhysReg, TRI) + << " interferences with " << VirtReg << "\n"); assert(!Intfs.empty() && "expected interference"); // Spill each interfering vreg allocated to PhysReg or an alias. diff --git a/lib/CodeGen/RegAllocFast.cpp b/lib/CodeGen/RegAllocFast.cpp index 9da881005b57b..f26f43d79f297 100644 --- a/lib/CodeGen/RegAllocFast.cpp +++ b/lib/CodeGen/RegAllocFast.cpp @@ -813,7 +813,7 @@ void RegAllocFast::handleThroughOperands(MachineInstr &MI, void RegAllocFast::dumpState() { for (unsigned Reg = 1, E = TRI->getNumRegs(); Reg != E; ++Reg) { if (PhysRegState[Reg] == regDisabled) continue; - dbgs() << " " << TRI->getName(Reg); + dbgs() << " " << printReg(Reg, TRI); switch(PhysRegState[Reg]) { case regFree: break; diff --git a/lib/CodeGen/RegAllocGreedy.cpp b/lib/CodeGen/RegAllocGreedy.cpp index 39676fed3d0b7..7aa998bc07fd2 100644 --- a/lib/CodeGen/RegAllocGreedy.cpp +++ b/lib/CodeGen/RegAllocGreedy.cpp @@ -105,10 +105,11 @@ static cl::opt LastChanceRecoloringMaxInterference( " interference at a time"), cl::init(8)); -static cl::opt -ExhaustiveSearch("exhaustive-register-search", cl::NotHidden, - cl::desc("Exhaustive Search for registers bypassing the depth " - "and interference cutoffs of last chance recoloring")); +static cl::opt ExhaustiveSearch( + "exhaustive-register-search", cl::NotHidden, + cl::desc("Exhaustive Search for registers bypassing the depth " + "and interference cutoffs of last chance recoloring"), + cl::Hidden); static cl::opt EnableLocalReassignment( "enable-local-reassign", cl::Hidden, @@ -1396,30 +1397,30 @@ BlockFrequency RAGreedy::calcSpillCost() { /// Such sequences are created in 2 scenarios: /// /// Scenario #1: -/// vreg0 is evicted from physreg0 by vreg1. -/// Evictee vreg0 is intended for region splitting with split candidate -/// physreg0 (the reg vreg0 was evicted from). +/// %0 is evicted from physreg0 by %1. +/// Evictee %0 is intended for region splitting with split candidate +/// physreg0 (the reg %0 was evicted from). /// Region splitting creates a local interval because of interference with the -/// evictor vreg1 (normally region spliitting creates 2 interval, the "by reg" +/// evictor %1 (normally region spliitting creates 2 interval, the "by reg" /// and "by stack" intervals and local interval created when interference /// occurs). -/// One of the split intervals ends up evicting vreg2 from physreg1. -/// Evictee vreg2 is intended for region splitting with split candidate +/// One of the split intervals ends up evicting %2 from physreg1. +/// Evictee %2 is intended for region splitting with split candidate /// physreg1. -/// One of the split intervals ends up evicting vreg3 from physreg2, etc. +/// One of the split intervals ends up evicting %3 from physreg2, etc. /// /// Scenario #2 -/// vreg0 is evicted from physreg0 by vreg1. -/// vreg2 is evicted from physreg2 by vreg3 etc. -/// Evictee vreg0 is intended for region splitting with split candidate +/// %0 is evicted from physreg0 by %1. +/// %2 is evicted from physreg2 by %3 etc. +/// Evictee %0 is intended for region splitting with split candidate /// physreg1. /// Region splitting creates a local interval because of interference with the -/// evictor vreg1. -/// One of the split intervals ends up evicting back original evictor vreg1 -/// from physreg0 (the reg vreg0 was evicted from). -/// Another evictee vreg2 is intended for region splitting with split candidate +/// evictor %1. +/// One of the split intervals ends up evicting back original evictor %1 +/// from physreg0 (the reg %0 was evicted from). +/// Another evictee %2 is intended for region splitting with split candidate /// physreg1. -/// One of the split intervals ends up evicting vreg3 from physreg2, etc. +/// One of the split intervals ends up evicting %3 from physreg2, etc. /// /// \param Evictee The register considered to be split. /// \param Cand The split candidate that determines the physical register @@ -1611,7 +1612,7 @@ void RAGreedy::splitAroundRegion(LiveRangeEdit &LREdit, // Create separate intervals for isolated blocks with multiple uses. if (!IntvIn && !IntvOut) { - DEBUG(dbgs() << "BB#" << BI.MBB->getNumber() << " isolated.\n"); + DEBUG(dbgs() << printMBBReference(*BI.MBB) << " isolated.\n"); if (SA->shouldSplitSingleBlock(BI, SingleInstrs)) SE->splitSingleBlock(BI); continue; diff --git a/lib/CodeGen/RegUsageInfoCollector.cpp b/lib/CodeGen/RegUsageInfoCollector.cpp index 3aaa5a4738d5f..2b418feb29ec5 100644 --- a/lib/CodeGen/RegUsageInfoCollector.cpp +++ b/lib/CodeGen/RegUsageInfoCollector.cpp @@ -141,7 +141,7 @@ bool RegUsageInfoCollector::runOnMachineFunction(MachineFunction &MF) { for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg) if (MachineOperand::clobbersPhysReg(&(RegMask[0]), PReg)) - DEBUG(dbgs() << TRI->getName(PReg) << " "); + DEBUG(dbgs() << printReg(PReg, TRI) << " "); DEBUG(dbgs() << " \n----------------------------------------\n"); diff --git a/lib/CodeGen/RegisterCoalescer.cpp b/lib/CodeGen/RegisterCoalescer.cpp index 81f9a343dc106..09875d336fd56 100644 --- a/lib/CodeGen/RegisterCoalescer.cpp +++ b/lib/CodeGen/RegisterCoalescer.cpp @@ -70,10 +70,9 @@ STATISTIC(NumInflated , "Number of register classes inflated"); STATISTIC(NumLaneConflicts, "Number of dead lane conflicts tested"); STATISTIC(NumLaneResolves, "Number of dead lane conflicts resolved"); -static cl::opt -EnableJoining("join-liveintervals", - cl::desc("Coalesce copies (default=true)"), - cl::init(true)); +static cl::opt EnableJoining("join-liveintervals", + cl::desc("Coalesce copies (default=true)"), + cl::init(true), cl::Hidden); static cl::opt UseTerminalRule("terminal-rule", cl::desc("Apply the terminal rule"), @@ -228,9 +227,9 @@ namespace { /// flag. /// This can happen when undef uses were previously concealed by a copy /// which we coalesced. Example: - /// %vreg0:sub0 = ... - /// %vreg1 = COPY %vreg0 <-- Coalescing COPY reveals undef - /// = use %vreg1:sub1 <-- hidden undef use + /// %0:sub0 = ... + /// %1 = COPY %0 <-- Coalescing COPY reveals undef + /// = use %1:sub1 <-- hidden undef use void addUndefFlag(const LiveInterval &Int, SlotIndex UseIdx, MachineOperand &MO, unsigned SubRegIdx); @@ -992,8 +991,8 @@ bool RegisterCoalescer::removePartialRedundancy(const CoalescerPair &CP, // Now ok to move copy. if (CopyLeftBB) { - DEBUG(dbgs() << "\tremovePartialRedundancy: Move the copy to BB#" - << CopyLeftBB->getNumber() << '\t' << CopyMI); + DEBUG(dbgs() << "\tremovePartialRedundancy: Move the copy to " + << printMBBReference(*CopyLeftBB) << '\t' << CopyMI); // Insert new copy to CopyLeftBB. auto InsPos = CopyLeftBB->getFirstTerminator(); @@ -1011,8 +1010,8 @@ bool RegisterCoalescer::removePartialRedundancy(const CoalescerPair &CP, // the deleted list. ErasedInstrs.erase(NewCopyMI); } else { - DEBUG(dbgs() << "\tremovePartialRedundancy: Remove the copy from BB#" - << MBB.getNumber() << '\t' << CopyMI); + DEBUG(dbgs() << "\tremovePartialRedundancy: Remove the copy from " + << printMBBReference(MBB) << '\t' << CopyMI); } // Remove CopyMI. @@ -1143,10 +1142,10 @@ bool RegisterCoalescer::reMaterializeTrivialDef(const CoalescerPair &CP, NewMI.setDebugLoc(DL); // In a situation like the following: - // %vreg0:subreg = instr ; DefMI, subreg = DstIdx - // %vreg1 = copy %vreg0:subreg ; CopyMI, SrcIdx = 0 - // instead of widening %vreg1 to the register class of %vreg0 simply do: - // %vreg1 = instr + // %0:subreg = instr ; DefMI, subreg = DstIdx + // %1 = copy %0:subreg ; CopyMI, SrcIdx = 0 + // instead of widening %1 to the register class of %0 simply do: + // %1 = instr const TargetRegisterClass *NewRC = CP.getNewRC(); if (DstIdx != 0) { MachineOperand &DefMO = NewMI.getOperand(0); @@ -1226,12 +1225,12 @@ bool RegisterCoalescer::reMaterializeTrivialDef(const CoalescerPair &CP, // This could happen if the rematerialization instruction is rematerializing // more than actually is used in the register. // An example would be: - // vreg1 = LOAD CONSTANTS 5, 8 ; Loading both 5 and 8 in different subregs + // %1 = LOAD CONSTANTS 5, 8 ; Loading both 5 and 8 in different subregs // ; Copying only part of the register here, but the rest is undef. - // vreg2:sub_16bit = COPY vreg1:sub_16bit + // %2:sub_16bit = COPY %1:sub_16bit // ==> // ; Materialize all the constants but only using one - // vreg2 = LOAD_CONSTANTS 5, 8 + // %2 = LOAD_CONSTANTS 5, 8 // // at this point for the part that wasn't defined before we could have // subranges missing the definition. @@ -1254,11 +1253,11 @@ bool RegisterCoalescer::reMaterializeTrivialDef(const CoalescerPair &CP, // Make sure that the subrange for resultant undef is removed // For example: - // vreg1:sub1 = LOAD CONSTANT 1 - // vreg2 = COPY vreg1 + // %1:sub1 = LOAD CONSTANT 1 + // %2 = COPY %1 // ==> - // vreg2:sub1 = LOAD CONSTANT 1 - // ; Correct but need to remove the subrange for vreg2:sub0 + // %2:sub1 = LOAD CONSTANT 1 + // ; Correct but need to remove the subrange for %2:sub0 // ; as it is now undef if (NewIdx != 0 && DstInt.hasSubRanges()) { // The affected subregister segments can be removed. @@ -1292,15 +1291,15 @@ bool RegisterCoalescer::reMaterializeTrivialDef(const CoalescerPair &CP, // Otherwise, variables that live through may miss some // interferences, thus creating invalid allocation. // E.g., i386 code: - // vreg1 = somedef ; vreg1 GR8 - // vreg2 = remat ; vreg2 GR32 - // CL = COPY vreg2.sub_8bit - // = somedef vreg1 ; vreg1 GR8 + // %1 = somedef ; %1 GR8 + // %2 = remat ; %2 GR32 + // CL = COPY %2.sub_8bit + // = somedef %1 ; %1 GR8 // => - // vreg1 = somedef ; vreg1 GR8 + // %1 = somedef ; %1 GR8 // ECX = remat ; CL - // = somedef vreg1 ; vreg1 GR8 - // vreg1 will see the inteferences with CL but not with CH since + // = somedef %1 ; %1 GR8 + // %1 will see the inteferences with CL but not with CH since // no live-ranges would have been created for ECX. // Fix that! SlotIndex NewMIIdx = LIS->getInstructionIndex(NewMI); @@ -1353,9 +1352,9 @@ bool RegisterCoalescer::eliminateUndefCopy(MachineInstr *CopyMI) { // ProcessImpicitDefs may leave some copies of values, it only removes // local variables. When we have a copy like: // - // %vreg1 = COPY %vreg2 + // %1 = COPY %2 // - // We delete the copy and remove the corresponding value number from %vreg1. + // We delete the copy and remove the corresponding value number from %1. // Any uses of that value number are marked as . // Note that we do not query CoalescerPair here but redo isMoveInstr as the @@ -1820,18 +1819,18 @@ bool RegisterCoalescer::joinReservedPhysReg(CoalescerPair &CP) { MachineInstr *CopyMI; if (CP.isFlipped()) { // Physreg is copied into vreg - // %vregY = COPY %x + // %y = COPY %physreg_x // ... //< no other def of %x here - // use %vregY + // use %y // => // ... // use %x CopyMI = MRI->getVRegDef(SrcReg); } else { // VReg is copied into physreg: - // %vregX = def + // %y = def // ... //< no other def or use of %y here - // %y = COPY %vregX + // %y = COPY %physreg_x // => // %y = def // ... @@ -2377,7 +2376,7 @@ JoinVals::analyzeValue(unsigned ValNo, JoinVals &Other) { if (OtherV.ErasableImplicitDef && DefMI && DefMI->getParent() != Indexes->getMBBFromIndex(V.OtherVNI->def)) { DEBUG(dbgs() << "IMPLICIT_DEF defined at " << V.OtherVNI->def - << " extends into BB#" << DefMI->getParent()->getNumber() + << " extends into " << printMBBReference(*DefMI->getParent()) << ", keeping it.\n"); OtherV.ErasableImplicitDef = false; } diff --git a/lib/CodeGen/RegisterScavenging.cpp b/lib/CodeGen/RegisterScavenging.cpp index 758a81fa5f737..5aeec854dad4a 100644 --- a/lib/CodeGen/RegisterScavenging.cpp +++ b/lib/CodeGen/RegisterScavenging.cpp @@ -288,8 +288,8 @@ bool RegScavenger::isRegUsed(unsigned Reg, bool includeReserved) const { unsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RC) const { for (unsigned Reg : *RC) { if (!isRegUsed(Reg)) { - DEBUG(dbgs() << "Scavenger found unused reg: " << TRI->getName(Reg) << - "\n"); + DEBUG(dbgs() << "Scavenger found unused reg: " << printReg(Reg, TRI) + << "\n"); return Reg; } } @@ -561,15 +561,15 @@ unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC, // If we found an unused register there is no reason to spill it. if (!isRegUsed(SReg)) { - DEBUG(dbgs() << "Scavenged register: " << TRI->getName(SReg) << "\n"); + DEBUG(dbgs() << "Scavenged register: " << printReg(SReg, TRI) << "\n"); return SReg; } ScavengedInfo &Scavenged = spill(SReg, *RC, SPAdj, I, UseMI); Scavenged.Restore = &*std::prev(UseMI); - DEBUG(dbgs() << "Scavenged register (with spill): " << TRI->getName(SReg) << - "\n"); + DEBUG(dbgs() << "Scavenged register (with spill): " << printReg(SReg, TRI) + << "\n"); return SReg; } @@ -599,7 +599,7 @@ unsigned RegScavenger::scavengeRegisterBackwards(const TargetRegisterClass &RC, Scavenged.Restore = &*std::prev(SpillBefore); LiveUnits.removeReg(Reg); DEBUG(dbgs() << "Scavenged register with spill: " << printReg(Reg, TRI) - << " until " << *SpillBefore); + << " until " << *SpillBefore); } else { DEBUG(dbgs() << "Scavenged free register: " << printReg(Reg, TRI) << '\n'); } diff --git a/lib/CodeGen/RegisterUsageInfo.cpp b/lib/CodeGen/RegisterUsageInfo.cpp index fa74d41852997..4e42deb406e1f 100644 --- a/lib/CodeGen/RegisterUsageInfo.cpp +++ b/lib/CodeGen/RegisterUsageInfo.cpp @@ -97,7 +97,7 @@ void PhysicalRegisterUsageInfo::print(raw_ostream &OS, const Module *M) const { for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg) { if (MachineOperand::clobbersPhysReg(&(FPRMPair->second[0]), PReg)) - OS << TRI->getName(PReg) << " "; + OS << printReg(PReg, TRI) << " "; } OS << "\n"; } diff --git a/lib/CodeGen/RenameIndependentSubregs.cpp b/lib/CodeGen/RenameIndependentSubregs.cpp index 72b7960f327b0..b423d67436405 100644 --- a/lib/CodeGen/RenameIndependentSubregs.cpp +++ b/lib/CodeGen/RenameIndependentSubregs.cpp @@ -10,20 +10,20 @@ /// Rename independent subregisters looks for virtual registers with /// independently used subregisters and renames them to new virtual registers. /// Example: In the following: -/// %vreg0:sub0 = ... -/// %vreg0:sub1 = ... -/// use %vreg0:sub0 -/// %vreg0:sub0 = ... -/// use %vreg0:sub0 -/// use %vreg0:sub1 +/// %0:sub0 = ... +/// %0:sub1 = ... +/// use %0:sub0 +/// %0:sub0 = ... +/// use %0:sub0 +/// use %0:sub1 /// sub0 and sub1 are never used together, and we have two independent sub0 /// definitions. This pass will rename to: -/// %vreg0:sub0 = ... -/// %vreg1:sub1 = ... -/// use %vreg1:sub1 -/// %vreg2:sub1 = ... -/// use %vreg2:sub1 -/// use %vreg0:sub0 +/// %0:sub0 = ... +/// %1:sub1 = ... +/// use %1:sub1 +/// %2:sub1 = ... +/// use %2:sub1 +/// use %0:sub0 // //===----------------------------------------------------------------------===// diff --git a/lib/CodeGen/ScheduleDAGInstrs.cpp b/lib/CodeGen/ScheduleDAGInstrs.cpp index b1a4851491030..4b45edcf0de7d 100644 --- a/lib/CodeGen/ScheduleDAGInstrs.cpp +++ b/lib/CodeGen/ScheduleDAGInstrs.cpp @@ -1043,7 +1043,7 @@ static void toggleKills(const MachineRegisterInfo &MRI, LivePhysRegs &LiveRegs, } void ScheduleDAGInstrs::fixupKills(MachineBasicBlock &MBB) { - DEBUG(dbgs() << "Fixup kills for BB#" << MBB.getNumber() << '\n'); + DEBUG(dbgs() << "Fixup kills for " << printMBBReference(MBB) << '\n'); LiveRegs.init(*TRI); LiveRegs.addLiveOuts(MBB); diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index b417807045bd7..ffce8545a149c 100644 --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -496,12 +496,9 @@ namespace { /// This is a helper function for visitAND and visitZERO_EXTEND. Returns /// true if the (and (load x) c) pattern matches an extload. ExtVT returns - /// the type of the loaded value to be extended. LoadedVT returns the type - /// of the original loaded value. NarrowLoad returns whether the load would - /// need to be narrowed in order to match. + /// the type of the loaded value to be extended. bool isAndLoadExtLoad(ConstantSDNode *AndC, LoadSDNode *LoadN, - EVT LoadResultTy, EVT &ExtVT, EVT &LoadedVT, - bool &NarrowLoad); + EVT LoadResultTy, EVT &ExtVT); /// Helper function for MergeConsecutiveStores which merges the /// component store chains. @@ -3693,22 +3690,20 @@ SDValue DAGCombiner::visitANDLike(SDValue N0, SDValue N1, SDNode *N) { } bool DAGCombiner::isAndLoadExtLoad(ConstantSDNode *AndC, LoadSDNode *LoadN, - EVT LoadResultTy, EVT &ExtVT, EVT &LoadedVT, - bool &NarrowLoad) { + EVT LoadResultTy, EVT &ExtVT) { if (!AndC->getAPIntValue().isMask()) return false; unsigned ActiveBits = AndC->getAPIntValue().countTrailingOnes(); ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits); - LoadedVT = LoadN->getMemoryVT(); + EVT LoadedVT = LoadN->getMemoryVT(); if (ExtVT == LoadedVT && (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, LoadResultTy, ExtVT))) { // ZEXTLOAD will match without needing to change the size of the value being // loaded. - NarrowLoad = false; return true; } @@ -3728,7 +3723,6 @@ bool DAGCombiner::isAndLoadExtLoad(ConstantSDNode *AndC, LoadSDNode *LoadN, if (!TLI.shouldReduceLoadWidth(LoadN, ISD::ZEXTLOAD, ExtVT)) return false; - NarrowLoad = true; return true; } @@ -3923,55 +3917,13 @@ SDValue DAGCombiner::visitAND(SDNode *N) { if (!VT.isVector() && N1C && (N0.getOpcode() == ISD::LOAD || (N0.getOpcode() == ISD::ANY_EXTEND && N0.getOperand(0).getOpcode() == ISD::LOAD))) { - bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND; - LoadSDNode *LN0 = HasAnyExt - ? cast(N0.getOperand(0)) - : cast(N0); - if (LN0->getExtensionType() != ISD::SEXTLOAD && - LN0->isUnindexed() && N0.hasOneUse() && SDValue(LN0, 0).hasOneUse()) { - auto NarrowLoad = false; - EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT; - EVT ExtVT, LoadedVT; - if (isAndLoadExtLoad(N1C, LN0, LoadResultTy, ExtVT, LoadedVT, - NarrowLoad)) { - if (!NarrowLoad) { - SDValue NewLoad = - DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(LN0), LoadResultTy, - LN0->getChain(), LN0->getBasePtr(), ExtVT, - LN0->getMemOperand()); - AddToWorklist(N); - CombineTo(LN0, NewLoad, NewLoad.getValue(1)); - return SDValue(N, 0); // Return N so it doesn't get rechecked! - } else { - EVT PtrType = LN0->getOperand(1).getValueType(); - - unsigned Alignment = LN0->getAlignment(); - SDValue NewPtr = LN0->getBasePtr(); - - // For big endian targets, we need to add an offset to the pointer - // to load the correct bytes. For little endian systems, we merely - // need to read fewer bytes from the same pointer. - if (DAG.getDataLayout().isBigEndian()) { - unsigned LVTStoreBytes = LoadedVT.getStoreSize(); - unsigned EVTStoreBytes = ExtVT.getStoreSize(); - unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; - SDLoc DL(LN0); - NewPtr = DAG.getNode(ISD::ADD, DL, PtrType, - NewPtr, DAG.getConstant(PtrOff, DL, PtrType)); - Alignment = MinAlign(Alignment, PtrOff); - } - - AddToWorklist(NewPtr.getNode()); + if (SDValue Res = ReduceLoadWidth(N)) { + LoadSDNode *LN0 = N0->getOpcode() == ISD::ANY_EXTEND + ? cast(N0.getOperand(0)) : cast(N0); - SDValue Load = DAG.getExtLoad( - ISD::ZEXTLOAD, SDLoc(LN0), LoadResultTy, LN0->getChain(), NewPtr, - LN0->getPointerInfo(), ExtVT, Alignment, - LN0->getMemOperand()->getFlags(), LN0->getAAInfo()); - AddToWorklist(N); - CombineTo(LN0, Load, Load.getValue(1)); - return SDValue(N, 0); // Return N so it doesn't get rechecked! - } - } + AddToWorklist(N); + CombineTo(LN0, Res, Res.getValue(1)); + return SDValue(N, 0); } } @@ -4700,6 +4652,16 @@ SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, const SDLoc &DL) { bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT); if (!HasROTL && !HasROTR) return nullptr; + // Check for truncated rotate. + if (LHS.getOpcode() == ISD::TRUNCATE && RHS.getOpcode() == ISD::TRUNCATE && + LHS.getOperand(0).getValueType() == RHS.getOperand(0).getValueType()) { + assert(LHS.getValueType() == RHS.getValueType()); + if (SDNode *Rot = MatchRotate(LHS.getOperand(0), RHS.getOperand(0), DL)) { + return DAG.getNode(ISD::TRUNCATE, SDLoc(LHS), LHS.getValueType(), + SDValue(Rot, 0)).getNode(); + } + } + // Match "(X shl/srl V1) & V2" where V2 may not be present. SDValue LHSShift; // The shift. SDValue LHSMask; // AND value if any. @@ -7694,11 +7656,9 @@ SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) { if (!N0.hasOneUse()) { if (N0.getOpcode() == ISD::AND) { auto *AndC = cast(N0.getOperand(1)); - auto NarrowLoad = false; EVT LoadResultTy = AndC->getValueType(0); - EVT ExtVT, LoadedVT; - if (isAndLoadExtLoad(AndC, LN0, LoadResultTy, ExtVT, LoadedVT, - NarrowLoad)) + EVT ExtVT; + if (isAndLoadExtLoad(AndC, LN0, LoadResultTy, ExtVT)) DoXform = false; } if (DoXform) @@ -8021,8 +7981,9 @@ SDValue DAGCombiner::visitAssertExt(SDNode *N) { /// If the result of a wider load is shifted to right of N bits and then /// truncated to a narrower type and where N is a multiple of number of bits of /// the narrower type, transform it to a narrower load from address + N / num of -/// bits of new type. If the result is to be extended, also fold the extension -/// to form a extending load. +/// bits of new type. Also narrow the load if the result is masked with an AND +/// to effectively produce a smaller type. If the result is to be extended, also +/// fold the extension to form a extending load. SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) { unsigned Opc = N->getOpcode(); @@ -8059,6 +8020,15 @@ SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) { else ExtVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() - ShiftAmt); + } else if (Opc == ISD::AND) { + // An AND with a constant mask is the same as a truncate + zero-extend. + auto AndC = dyn_cast(N->getOperand(1)); + if (!AndC || !AndC->getAPIntValue().isMask()) + return SDValue(); + + unsigned ActiveBits = AndC->getAPIntValue().countTrailingOnes(); + ExtType = ISD::ZEXTLOAD; + ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits); } if (LegalOperations && !TLI.isLoadExtLegal(ExtType, VT, ExtVT)) return SDValue(); diff --git a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp index 83daa8c4029e5..d86ed0b6f8a52 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp @@ -1253,6 +1253,9 @@ SDValue DAGTypeLegalizer::PromoteIntOp_MGATHER(MaskedGatherSDNode *N, // The Mask EVT DataVT = N->getValueType(0); NewOps[OpNo] = PromoteTargetBoolean(N->getOperand(OpNo), DataVT); + } else if (OpNo == 4) { + // Need to sign extend the index since the bits will likely be used. + NewOps[OpNo] = SExtPromotedInteger(N->getOperand(OpNo)); } else NewOps[OpNo] = GetPromotedInteger(N->getOperand(OpNo)); @@ -1273,6 +1276,9 @@ SDValue DAGTypeLegalizer::PromoteIntOp_MSCATTER(MaskedScatterSDNode *N, // The Mask EVT DataVT = N->getValue().getValueType(); NewOps[OpNo] = PromoteTargetBoolean(N->getOperand(OpNo), DataVT); + } else if (OpNo == 4) { + // Need to sign extend the index since the bits will likely be used. + NewOps[OpNo] = SExtPromotedInteger(N->getOperand(OpNo)); } else NewOps[OpNo] = GetPromotedInteger(N->getOperand(OpNo)); return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0); diff --git a/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp index cc3a520775344..9ab82382c6590 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp @@ -1058,20 +1058,21 @@ void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo, EVT VecVT = Vec.getValueType(); EVT EltVT = VecVT.getVectorElementType(); SDValue StackPtr = DAG.CreateStackTemporary(VecVT); - SDValue Store = - DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, MachinePointerInfo()); + auto &MF = DAG.getMachineFunction(); + auto FrameIndex = cast(StackPtr.getNode())->getIndex(); + auto PtrInfo = MachinePointerInfo::getFixedStack(MF, FrameIndex); + SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, PtrInfo); // Store the new element. This may be larger than the vector element type, // so use a truncating store. SDValue EltPtr = TLI.getVectorElementPointer(DAG, StackPtr, VecVT, Idx); Type *VecType = VecVT.getTypeForEVT(*DAG.getContext()); unsigned Alignment = DAG.getDataLayout().getPrefTypeAlignment(VecType); - Store = - DAG.getTruncStore(Store, dl, Elt, EltPtr, MachinePointerInfo(), EltVT); + Store = DAG.getTruncStore(Store, dl, Elt, EltPtr, + MachinePointerInfo::getUnknownStack(MF), EltVT); // Load the Lo part from the stack slot. - Lo = - DAG.getLoad(Lo.getValueType(), dl, Store, StackPtr, MachinePointerInfo()); + Lo = DAG.getLoad(Lo.getValueType(), dl, Store, StackPtr, PtrInfo); // Increment the pointer to the other part. unsigned IncrementSize = Lo.getValueSizeInBits() / 8; @@ -1080,7 +1081,8 @@ void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo, StackPtr.getValueType())); // Load the Hi part from the stack slot. - Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, MachinePointerInfo(), + Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, + PtrInfo.getWithOffset(IncrementSize), MinAlign(Alignment, IncrementSize)); } @@ -1764,13 +1766,16 @@ SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) { // Store the vector to the stack. SDValue StackPtr = DAG.CreateStackTemporary(VecVT); - SDValue Store = - DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, MachinePointerInfo()); + auto &MF = DAG.getMachineFunction(); + auto FrameIndex = cast(StackPtr.getNode())->getIndex(); + auto PtrInfo = MachinePointerInfo::getFixedStack(MF, FrameIndex); + SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, PtrInfo); // Load back the required element. StackPtr = TLI.getVectorElementPointer(DAG, StackPtr, VecVT, Idx); - return DAG.getExtLoad(ISD::EXTLOAD, dl, N->getValueType(0), Store, StackPtr, - MachinePointerInfo(), EltVT); + return DAG.getExtLoad( + ISD::EXTLOAD, dl, N->getValueType(0), Store, StackPtr, + MachinePointerInfo::getUnknownStack(DAG.getMachineFunction()), EltVT); } SDValue DAGTypeLegalizer::SplitVecOp_ExtVecInRegOp(SDNode *N) { diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp index acbae1bae33bb..49f304c8cc869 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp @@ -346,9 +346,8 @@ static void GetCostForDef(const ScheduleDAGSDNodes::RegDefIter &RegDefPos, /// Schedule - Schedule the DAG using list scheduling. void ScheduleDAGRRList::Schedule() { - DEBUG(dbgs() - << "********** List Scheduling BB#" << BB->getNumber() - << " '" << BB->getName() << "' **********\n"); + DEBUG(dbgs() << "********** List Scheduling " << printMBBReference(*BB) + << " '" << BB->getName() << "' **********\n"); CurCycle = 0; IssueCount = 0; @@ -1430,10 +1429,12 @@ SUnit *ScheduleDAGRRList::PickNodeToScheduleBottomUp() { SmallVector LRegs; if (!DelayForLiveRegsBottomUp(CurSU, LRegs)) break; - DEBUG(dbgs() << " Interfering reg " << - (LRegs[0] == TRI->getNumRegs() ? "CallResource" - : TRI->getName(LRegs[0])) - << " SU #" << CurSU->NodeNum << '\n'); + DEBUG(dbgs() << " Interfering reg "; + if (LRegs[0] == TRI->getNumRegs()) + dbgs() << "CallResource"; + else + dbgs() << printReg(LRegs[0], TRI); + dbgs() << " SU #" << CurSU->NodeNum << '\n'); std::pair LRegsPair = LRegsMap.insert(std::make_pair(CurSU, LRegs)); if (LRegsPair.second) { diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGVLIW.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGVLIW.cpp index 54c1531a018ea..07b46b9183ab7 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGVLIW.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGVLIW.cpp @@ -93,9 +93,8 @@ class ScheduleDAGVLIW : public ScheduleDAGSDNodes { /// Schedule - Schedule the DAG using list scheduling. void ScheduleDAGVLIW::Schedule() { - DEBUG(dbgs() - << "********** List Scheduling BB#" << BB->getNumber() - << " '" << BB->getName() << "' **********\n"); + DEBUG(dbgs() << "********** List Scheduling " << printMBBReference(*BB) + << " '" << BB->getName() << "' **********\n"); // Build the scheduling graph. BuildSchedGraph(AA); diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index 22e7885d00501..bcc972e0b4f97 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -2463,27 +2463,49 @@ void SelectionDAG::computeKnownBits(SDValue Op, KnownBits &Known, case ISD::SHL: if (const APInt *ShAmt = getValidShiftAmountConstant(Op)) { computeKnownBits(Op.getOperand(0), Known, DemandedElts, Depth + 1); - Known.Zero <<= *ShAmt; - Known.One <<= *ShAmt; + unsigned Shift = ShAmt->getZExtValue(); + Known.Zero <<= Shift; + Known.One <<= Shift; // Low bits are known zero. - Known.Zero.setLowBits(ShAmt->getZExtValue()); + Known.Zero.setLowBits(Shift); } break; case ISD::SRL: if (const APInt *ShAmt = getValidShiftAmountConstant(Op)) { computeKnownBits(Op.getOperand(0), Known, DemandedElts, Depth + 1); - Known.Zero.lshrInPlace(*ShAmt); - Known.One.lshrInPlace(*ShAmt); + unsigned Shift = ShAmt->getZExtValue(); + Known.Zero.lshrInPlace(Shift); + Known.One.lshrInPlace(Shift); // High bits are known zero. - Known.Zero.setHighBits(ShAmt->getZExtValue()); + Known.Zero.setHighBits(Shift); + } else if (auto *BV = dyn_cast(Op.getOperand(1))) { + // If the shift amount is a vector of constants see if we can bound + // the number of upper zero bits. + unsigned ShiftAmountMin = BitWidth; + for (unsigned i = 0; i != BV->getNumOperands(); ++i) { + if (auto *C = dyn_cast(BV->getOperand(i))) { + const APInt &ShAmt = C->getAPIntValue(); + if (ShAmt.ult(BitWidth)) { + ShiftAmountMin = std::min(ShiftAmountMin, + ShAmt.getZExtValue()); + continue; + } + } + // Don't know anything. + ShiftAmountMin = 0; + break; + } + + Known.Zero.setHighBits(ShiftAmountMin); } break; case ISD::SRA: if (const APInt *ShAmt = getValidShiftAmountConstant(Op)) { computeKnownBits(Op.getOperand(0), Known, DemandedElts, Depth + 1); + unsigned Shift = ShAmt->getZExtValue(); // Sign extend known zero/one bit (else is unknown). - Known.Zero.ashrInPlace(*ShAmt); - Known.One.ashrInPlace(*ShAmt); + Known.Zero.ashrInPlace(Shift); + Known.One.ashrInPlace(Shift); } break; case ISD::SIGN_EXTEND_INREG: { @@ -5821,7 +5843,8 @@ SDValue SelectionDAG::getMemIntrinsicNode(unsigned Opcode, const SDLoc &dl, /// MachinePointerInfo record from it. This is particularly useful because the /// code generator has many cases where it doesn't bother passing in a /// MachinePointerInfo to getLoad or getStore when it has "FI+Cst". -static MachinePointerInfo InferPointerInfo(SelectionDAG &DAG, SDValue Ptr, +static MachinePointerInfo InferPointerInfo(const MachinePointerInfo &Info, + SelectionDAG &DAG, SDValue Ptr, int64_t Offset = 0) { // If this is FI+Offset, we can model it. if (const FrameIndexSDNode *FI = dyn_cast(Ptr)) @@ -5832,7 +5855,7 @@ static MachinePointerInfo InferPointerInfo(SelectionDAG &DAG, SDValue Ptr, if (Ptr.getOpcode() != ISD::ADD || !isa(Ptr.getOperand(1)) || !isa(Ptr.getOperand(0))) - return MachinePointerInfo(); + return Info; int FI = cast(Ptr.getOperand(0))->getIndex(); return MachinePointerInfo::getFixedStack( @@ -5844,14 +5867,15 @@ static MachinePointerInfo InferPointerInfo(SelectionDAG &DAG, SDValue Ptr, /// MachinePointerInfo record from it. This is particularly useful because the /// code generator has many cases where it doesn't bother passing in a /// MachinePointerInfo to getLoad or getStore when it has "FI+Cst". -static MachinePointerInfo InferPointerInfo(SelectionDAG &DAG, SDValue Ptr, +static MachinePointerInfo InferPointerInfo(const MachinePointerInfo &Info, + SelectionDAG &DAG, SDValue Ptr, SDValue OffsetOp) { // If the 'Offset' value isn't a constant, we can't handle this. if (ConstantSDNode *OffsetNode = dyn_cast(OffsetOp)) - return InferPointerInfo(DAG, Ptr, OffsetNode->getSExtValue()); + return InferPointerInfo(Info, DAG, Ptr, OffsetNode->getSExtValue()); if (OffsetOp.isUndef()) - return InferPointerInfo(DAG, Ptr); - return MachinePointerInfo(); + return InferPointerInfo(Info, DAG, Ptr); + return Info; } SDValue SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, @@ -5871,7 +5895,7 @@ SDValue SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, // If we don't have a PtrInfo, infer the trivial frame index case to simplify // clients. if (PtrInfo.V.isNull()) - PtrInfo = InferPointerInfo(*this, Ptr, Offset); + PtrInfo = InferPointerInfo(PtrInfo, *this, Ptr, Offset); MachineFunction &MF = getMachineFunction(); MachineMemOperand *MMO = MF.getMachineMemOperand( @@ -5990,7 +6014,7 @@ SDValue SelectionDAG::getStore(SDValue Chain, const SDLoc &dl, SDValue Val, assert((MMOFlags & MachineMemOperand::MOLoad) == 0); if (PtrInfo.V.isNull()) - PtrInfo = InferPointerInfo(*this, Ptr); + PtrInfo = InferPointerInfo(PtrInfo, *this, Ptr); MachineFunction &MF = getMachineFunction(); MachineMemOperand *MMO = MF.getMachineMemOperand( @@ -6040,7 +6064,7 @@ SDValue SelectionDAG::getTruncStore(SDValue Chain, const SDLoc &dl, SDValue Val, assert((MMOFlags & MachineMemOperand::MOLoad) == 0); if (PtrInfo.V.isNull()) - PtrInfo = InferPointerInfo(*this, Ptr); + PtrInfo = InferPointerInfo(PtrInfo, *this, Ptr); MachineFunction &MF = getMachineFunction(); MachineMemOperand *MMO = MF.getMachineMemOperand( diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp index 16a5bbd8b5567..1c31eca3ec916 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -128,11 +128,11 @@ using namespace llvm; static unsigned LimitFloatPrecision; static cl::opt -LimitFPPrecision("limit-float-precision", - cl::desc("Generate low-precision inline sequences " - "for some float libcalls"), - cl::location(LimitFloatPrecision), - cl::init(0)); + LimitFPPrecision("limit-float-precision", + cl::desc("Generate low-precision inline sequences " + "for some float libcalls"), + cl::location(LimitFloatPrecision), cl::Hidden, + cl::init(0)); static cl::opt SwitchPeelThreshold( "switch-peel-threshold", cl::Hidden, cl::init(66), @@ -1472,7 +1472,9 @@ void SelectionDAGBuilder::visitRet(const ReturnInst &I) { // Leave Outs empty so that LowerReturn won't try to load return // registers the usual way. SmallVector PtrValueVTs; - ComputeValueVTs(TLI, DL, PointerType::getUnqual(F->getReturnType()), + ComputeValueVTs(TLI, DL, + F->getReturnType()->getPointerTo( + DAG.getDataLayout().getAllocaAddrSpace()), PtrValueVTs); SDValue RetPtr = DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(), @@ -1489,10 +1491,10 @@ void SelectionDAGBuilder::visitRet(const ReturnInst &I) { // An aggregate return value cannot wrap around the address space, so // offsets to its parts don't wrap either. SDValue Ptr = DAG.getObjectPtrOffset(getCurSDLoc(), RetPtr, Offsets[i]); - Chains[i] = DAG.getStore(Chain, getCurSDLoc(), - SDValue(RetOp.getNode(), RetOp.getResNo() + i), - // FIXME: better loc info would be nice. - Ptr, MachinePointerInfo()); + Chains[i] = DAG.getStore( + Chain, getCurSDLoc(), SDValue(RetOp.getNode(), RetOp.getResNo() + i), + // FIXME: better loc info would be nice. + Ptr, MachinePointerInfo::getUnknownStack(DAG.getMachineFunction())); } Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), @@ -8590,7 +8592,9 @@ void SelectionDAGISel::LowerArguments(const Function &F) { // Put in an sret pointer parameter before all the other parameters. SmallVector ValueVTs; ComputeValueVTs(*TLI, DAG.getDataLayout(), - PointerType::getUnqual(F.getReturnType()), ValueVTs); + F.getReturnType()->getPointerTo( + DAG.getDataLayout().getAllocaAddrSpace()), + ValueVTs); // NOTE: Assuming that a pointer will never break down to more than one VT // or one register. @@ -8744,7 +8748,9 @@ void SelectionDAGISel::LowerArguments(const Function &F) { // from the sret argument into it. SmallVector ValueVTs; ComputeValueVTs(*TLI, DAG.getDataLayout(), - PointerType::getUnqual(F.getReturnType()), ValueVTs); + F.getReturnType()->getPointerTo( + DAG.getDataLayout().getAllocaAddrSpace()), + ValueVTs); MVT VT = ValueVTs[0].getSimpleVT(); MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT); Optional AssertOp = None; diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index cb37137d547f5..8f47c5b40ba38 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -730,8 +730,9 @@ void SelectionDAGISel::CodeGenAndEmitDAG() { BlockName = (MF->getName() + ":" + FuncInfo->MBB->getBasicBlock()->getName()).str(); } - DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber - << " '" << BlockName << "'\n"; CurDAG->dump()); + DEBUG(dbgs() << "Initial selection DAG: " << printMBBReference(*FuncInfo->MBB) + << " '" << BlockName << "'\n"; + CurDAG->dump()); if (ViewDAGCombine1 && MatchFilterBB) CurDAG->viewGraph("dag-combine1 input for " + BlockName); @@ -743,8 +744,10 @@ void SelectionDAGISel::CodeGenAndEmitDAG() { CurDAG->Combine(BeforeLegalizeTypes, AA, OptLevel); } - DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber - << " '" << BlockName << "'\n"; CurDAG->dump()); + DEBUG(dbgs() << "Optimized lowered selection DAG: " + << printMBBReference(*FuncInfo->MBB) << " '" << BlockName + << "'\n"; + CurDAG->dump()); // Second step, hack on the DAG until it only uses operations and types that // the target supports. @@ -758,8 +761,10 @@ void SelectionDAGISel::CodeGenAndEmitDAG() { Changed = CurDAG->LegalizeTypes(); } - DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber - << " '" << BlockName << "'\n"; CurDAG->dump()); + DEBUG(dbgs() << "Type-legalized selection DAG: " + << printMBBReference(*FuncInfo->MBB) << " '" << BlockName + << "'\n"; + CurDAG->dump()); // Only allow creation of legal node types. CurDAG->NewNodesMustHaveLegalTypes = true; @@ -775,8 +780,10 @@ void SelectionDAGISel::CodeGenAndEmitDAG() { CurDAG->Combine(AfterLegalizeTypes, AA, OptLevel); } - DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber - << " '" << BlockName << "'\n"; CurDAG->dump()); + DEBUG(dbgs() << "Optimized type-legalized selection DAG: " + << printMBBReference(*FuncInfo->MBB) << " '" << BlockName + << "'\n"; + CurDAG->dump()); } { @@ -786,8 +793,10 @@ void SelectionDAGISel::CodeGenAndEmitDAG() { } if (Changed) { - DEBUG(dbgs() << "Vector-legalized selection DAG: BB#" << BlockNumber - << " '" << BlockName << "'\n"; CurDAG->dump()); + DEBUG(dbgs() << "Vector-legalized selection DAG: " + << printMBBReference(*FuncInfo->MBB) << " '" << BlockName + << "'\n"; + CurDAG->dump()); { NamedRegionTimer T("legalize_types2", "Type Legalization 2", GroupName, @@ -795,8 +804,10 @@ void SelectionDAGISel::CodeGenAndEmitDAG() { CurDAG->LegalizeTypes(); } - DEBUG(dbgs() << "Vector/type-legalized selection DAG: BB#" << BlockNumber - << " '" << BlockName << "'\n"; CurDAG->dump()); + DEBUG(dbgs() << "Vector/type-legalized selection DAG: " + << printMBBReference(*FuncInfo->MBB) << " '" << BlockName + << "'\n"; + CurDAG->dump()); if (ViewDAGCombineLT && MatchFilterBB) CurDAG->viewGraph("dag-combine-lv input for " + BlockName); @@ -808,8 +819,10 @@ void SelectionDAGISel::CodeGenAndEmitDAG() { CurDAG->Combine(AfterLegalizeVectorOps, AA, OptLevel); } - DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#" - << BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump()); + DEBUG(dbgs() << "Optimized vector-legalized selection DAG: " + << printMBBReference(*FuncInfo->MBB) << " '" << BlockName + << "'\n"; + CurDAG->dump()); } if (ViewLegalizeDAGs && MatchFilterBB) @@ -821,8 +834,10 @@ void SelectionDAGISel::CodeGenAndEmitDAG() { CurDAG->Legalize(); } - DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber - << " '" << BlockName << "'\n"; CurDAG->dump()); + DEBUG(dbgs() << "Legalized selection DAG: " + << printMBBReference(*FuncInfo->MBB) << " '" << BlockName + << "'\n"; + CurDAG->dump()); if (ViewDAGCombine2 && MatchFilterBB) CurDAG->viewGraph("dag-combine2 input for " + BlockName); @@ -834,8 +849,10 @@ void SelectionDAGISel::CodeGenAndEmitDAG() { CurDAG->Combine(AfterLegalizeDAG, AA, OptLevel); } - DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber - << " '" << BlockName << "'\n"; CurDAG->dump()); + DEBUG(dbgs() << "Optimized legalized selection DAG: " + << printMBBReference(*FuncInfo->MBB) << " '" << BlockName + << "'\n"; + CurDAG->dump()); if (OptLevel != CodeGenOpt::None) ComputeLiveOutVRegInfo(); @@ -851,8 +868,10 @@ void SelectionDAGISel::CodeGenAndEmitDAG() { DoInstructionSelection(); } - DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber - << " '" << BlockName << "'\n"; CurDAG->dump()); + DEBUG(dbgs() << "Selected selection DAG: " + << printMBBReference(*FuncInfo->MBB) << " '" << BlockName + << "'\n"; + CurDAG->dump()); if (ViewSchedDAGs && MatchFilterBB) CurDAG->viewGraph("scheduler input for " + BlockName); @@ -919,9 +938,9 @@ class ISelUpdater : public SelectionDAG::DAGUpdateListener { } // end anonymous namespace void SelectionDAGISel::DoInstructionSelection() { - DEBUG(dbgs() << "===== Instruction selection begins: BB#" - << FuncInfo->MBB->getNumber() - << " '" << FuncInfo->MBB->getName() << "'\n"); + DEBUG(dbgs() << "===== Instruction selection begins: " + << printMBBReference(*FuncInfo->MBB) << " '" + << FuncInfo->MBB->getName() << "'\n"); PreprocessISelDAG(); diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp index e87b3d8db1ec2..1dff66f362780 100644 --- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -3797,7 +3797,7 @@ SDValue TargetLowering::getVectorElementPointer(SelectionDAG &DAG, SDValue Index) const { SDLoc dl(Index); // Make sure the index type is big enough to compute in. - Index = DAG.getZExtOrTrunc(Index, dl, getPointerTy(DAG.getDataLayout())); + Index = DAG.getZExtOrTrunc(Index, dl, VecPtr.getValueType()); EVT EltVT = VecVT.getVectorElementType(); diff --git a/lib/CodeGen/SlotIndexes.cpp b/lib/CodeGen/SlotIndexes.cpp index 25a1c37b145da..184329a659cb9 100644 --- a/lib/CodeGen/SlotIndexes.cpp +++ b/lib/CodeGen/SlotIndexes.cpp @@ -264,7 +264,7 @@ LLVM_DUMP_METHOD void SlotIndexes::dump() const { } for (unsigned i = 0, e = MBBRanges.size(); i != e; ++i) - dbgs() << "BB#" << i << "\t[" << MBBRanges[i].first << ';' + dbgs() << "%bb." << i << "\t[" << MBBRanges[i].first << ';' << MBBRanges[i].second << ")\n"; } #endif diff --git a/lib/CodeGen/SplitKit.cpp b/lib/CodeGen/SplitKit.cpp index 59c5798ab49e6..fc85ea3d16636 100644 --- a/lib/CodeGen/SplitKit.cpp +++ b/lib/CodeGen/SplitKit.cpp @@ -729,7 +729,8 @@ SlotIndex SplitEditor::enterIntvAtEnd(MachineBasicBlock &MBB) { assert(OpenIdx && "openIntv not called before enterIntvAtEnd"); SlotIndex End = LIS.getMBBEndIdx(&MBB); SlotIndex Last = End.getPrevSlot(); - DEBUG(dbgs() << " enterIntvAtEnd BB#" << MBB.getNumber() << ", " << Last); + DEBUG(dbgs() << " enterIntvAtEnd " << printMBBReference(MBB) << ", " + << Last); VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Last); if (!ParentVNI) { DEBUG(dbgs() << ": not live\n"); @@ -808,7 +809,8 @@ SlotIndex SplitEditor::leaveIntvBefore(SlotIndex Idx) { SlotIndex SplitEditor::leaveIntvAtTop(MachineBasicBlock &MBB) { assert(OpenIdx && "openIntv not called before leaveIntvAtTop"); SlotIndex Start = LIS.getMBBStartIdx(&MBB); - DEBUG(dbgs() << " leaveIntvAtTop BB#" << MBB.getNumber() << ", " << Start); + DEBUG(dbgs() << " leaveIntvAtTop " << printMBBReference(MBB) << ", " + << Start); VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Start); if (!ParentVNI) { @@ -906,15 +908,15 @@ SplitEditor::findShallowDominator(MachineBasicBlock *MBB, // MBB isn't in a loop, it doesn't get any better. All dominators have a // higher frequency by definition. if (!Loop) { - DEBUG(dbgs() << "Def in BB#" << DefMBB->getNumber() << " dominates BB#" - << MBB->getNumber() << " at depth 0\n"); + DEBUG(dbgs() << "Def in " << printMBBReference(*DefMBB) << " dominates " + << printMBBReference(*MBB) << " at depth 0\n"); return MBB; } // We'll never be able to exit the DefLoop. if (Loop == DefLoop) { - DEBUG(dbgs() << "Def in BB#" << DefMBB->getNumber() << " dominates BB#" - << MBB->getNumber() << " in the same loop\n"); + DEBUG(dbgs() << "Def in " << printMBBReference(*DefMBB) << " dominates " + << printMBBReference(*MBB) << " in the same loop\n"); return MBB; } @@ -923,8 +925,8 @@ SplitEditor::findShallowDominator(MachineBasicBlock *MBB, if (Depth < BestDepth) { BestMBB = MBB; BestDepth = Depth; - DEBUG(dbgs() << "Def in BB#" << DefMBB->getNumber() << " dominates BB#" - << MBB->getNumber() << " at depth " << Depth << '\n'); + DEBUG(dbgs() << "Def in " << printMBBReference(*DefMBB) << " dominates " + << printMBBReference(*MBB) << " at depth " << Depth << '\n'); } // Leave loop by going to the immediate dominator of the loop header. @@ -1063,7 +1065,7 @@ void SplitEditor::hoistCopies() { DEBUG(dbgs() << "Multi-mapped complement " << VNI->id << '@' << VNI->def << " for parent " << ParentVNI->id << '@' << ParentVNI->def - << " hoist to BB#" << Dom.first->getNumber() << ' ' + << " hoist to " << printMBBReference(*Dom.first) << ' ' << Dom.second << '\n'); } @@ -1173,7 +1175,7 @@ bool SplitEditor::transferValues() { if (Start != BlockStart) { VNInfo *VNI = LI.extendInBlock(BlockStart, std::min(BlockEnd, End)); assert(VNI && "Missing def for complex mapped value"); - DEBUG(dbgs() << ':' << VNI->id << "*BB#" << MBB->getNumber()); + DEBUG(dbgs() << ':' << VNI->id << "*" << printMBBReference(*MBB)); // MBB has its own def. Is it also live-out? if (BlockEnd <= End) LRC.setLiveOutValue(&*MBB, VNI); @@ -1186,7 +1188,7 @@ bool SplitEditor::transferValues() { // Handle the live-in blocks covered by [Start;End). assert(Start <= BlockStart && "Expected live-in block"); while (BlockStart < End) { - DEBUG(dbgs() << ">BB#" << MBB->getNumber()); + DEBUG(dbgs() << ">" << printMBBReference(*MBB)); BlockEnd = LIS.getMBBEndIdx(&*MBB); if (BlockStart == ParentVNI->def) { // This block has the def of a parent PHI, so it isn't live-in. @@ -1329,7 +1331,7 @@ void SplitEditor::rewriteAssigned(bool ExtendRanges) { unsigned RegIdx = RegAssign.lookup(Idx); LiveInterval &LI = LIS.getInterval(Edit->get(RegIdx)); MO.setReg(LI.reg); - DEBUG(dbgs() << " rewr BB#" << MI->getParent()->getNumber() << '\t' + DEBUG(dbgs() << " rewr " << printMBBReference(*MI->getParent()) << '\t' << Idx << ':' << RegIdx << '\t' << *MI); // Extend liveness to Idx if the instruction reads reg. @@ -1375,9 +1377,9 @@ void SplitEditor::rewriteAssigned(bool ExtendRanges) { continue; // The problem here can be that the new register may have been created // for a partially defined original register. For example: - // %vreg827:subreg_hireg = ... + // %0:subreg_hireg = ... // ... - // %vreg828 = COPY %vreg827 + // %1 = COPY %0 if (S.empty()) continue; SubLRC.reset(&VRM.getMachineFunction(), LIS.getSlotIndexes(), &MDT, @@ -1563,9 +1565,9 @@ void SplitEditor::splitLiveThroughBlock(unsigned MBBNum, SlotIndex Start, Stop; std::tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(MBBNum); - DEBUG(dbgs() << "BB#" << MBBNum << " [" << Start << ';' << Stop - << ") intf " << LeaveBefore << '-' << EnterAfter - << ", live-through " << IntvIn << " -> " << IntvOut); + DEBUG(dbgs() << "%bb." << MBBNum << " [" << Start << ';' << Stop << ") intf " + << LeaveBefore << '-' << EnterAfter << ", live-through " + << IntvIn << " -> " << IntvOut); assert((IntvIn || IntvOut) && "Use splitSingleBlock for isolated blocks"); @@ -1665,7 +1667,7 @@ void SplitEditor::splitRegInBlock(const SplitAnalysis::BlockInfo &BI, SlotIndex Start, Stop; std::tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(BI.MBB); - DEBUG(dbgs() << "BB#" << BI.MBB->getNumber() << " [" << Start << ';' << Stop + DEBUG(dbgs() << printMBBReference(*BI.MBB) << " [" << Start << ';' << Stop << "), uses " << BI.FirstInstr << '-' << BI.LastInstr << ", reg-in " << IntvIn << ", leave before " << LeaveBefore << (BI.LiveOut ? ", stack-out" : ", killed in block")); @@ -1757,7 +1759,7 @@ void SplitEditor::splitRegOutBlock(const SplitAnalysis::BlockInfo &BI, SlotIndex Start, Stop; std::tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(BI.MBB); - DEBUG(dbgs() << "BB#" << BI.MBB->getNumber() << " [" << Start << ';' << Stop + DEBUG(dbgs() << printMBBReference(*BI.MBB) << " [" << Start << ';' << Stop << "), uses " << BI.FirstInstr << '-' << BI.LastInstr << ", reg-out " << IntvOut << ", enter after " << EnterAfter << (BI.LiveIn ? ", stack-in" : ", defined in block")); diff --git a/lib/CodeGen/StackColoring.cpp b/lib/CodeGen/StackColoring.cpp index 0a7be1d12fa2f..18bba42907bd6 100644 --- a/lib/CodeGen/StackColoring.cpp +++ b/lib/CodeGen/StackColoring.cpp @@ -739,7 +739,7 @@ unsigned StackColoring::collectMarkers(unsigned NumSlot) { } else { for (auto Slot : slots) { DEBUG(dbgs() << "Found a use of slot #" << Slot); - DEBUG(dbgs() << " at BB#" << MBB->getNumber() << " index "); + DEBUG(dbgs() << " at " << printMBBReference(*MBB) << " index "); DEBUG(Indexes->getInstructionIndex(MI).print(dbgs())); const AllocaInst *Allocation = MFI->getObjectAllocation(Slot); if (Allocation) { diff --git a/lib/CodeGen/StackMaps.cpp b/lib/CodeGen/StackMaps.cpp index 1fa4c2f4d9d29..e66a25bec911c 100644 --- a/lib/CodeGen/StackMaps.cpp +++ b/lib/CodeGen/StackMaps.cpp @@ -41,7 +41,7 @@ using namespace llvm; #define DEBUG_TYPE "stackmaps" static cl::opt StackMapVersion( - "stackmap-version", cl::init(3), + "stackmap-version", cl::init(3), cl::Hidden, cl::desc("Specify the stackmap encoding version (default = 3)")); const char *StackMaps::WSMP = "Stack Maps: "; @@ -193,14 +193,14 @@ void StackMaps::print(raw_ostream &OS) { case Location::Register: OS << "Register "; if (TRI) - OS << TRI->getName(Loc.Reg); + OS << printReg(Loc.Reg, TRI); else OS << Loc.Reg; break; case Location::Direct: OS << "Direct "; if (TRI) - OS << TRI->getName(Loc.Reg); + OS << printReg(Loc.Reg, TRI); else OS << Loc.Reg; if (Loc.Offset) @@ -209,7 +209,7 @@ void StackMaps::print(raw_ostream &OS) { case Location::Indirect: OS << "Indirect "; if (TRI) - OS << TRI->getName(Loc.Reg); + OS << printReg(Loc.Reg, TRI); else OS << Loc.Reg; OS << "+" << Loc.Offset; @@ -233,7 +233,7 @@ void StackMaps::print(raw_ostream &OS) { for (const auto &LO : LiveOuts) { OS << WSMP << "\t\tLO " << Idx << ": "; if (TRI) - OS << TRI->getName(LO.Reg); + OS << printReg(LO.Reg, TRI); else OS << LO.Reg; OS << "\t[encoding: .short " << LO.DwarfRegNum << ", .byte 0, .byte " diff --git a/lib/CodeGen/TailDuplicator.cpp b/lib/CodeGen/TailDuplicator.cpp index 7adf9b037b5ff..63eb6cc651b22 100644 --- a/lib/CodeGen/TailDuplicator.cpp +++ b/lib/CodeGen/TailDuplicator.cpp @@ -111,9 +111,10 @@ static void VerifyPHIs(MachineFunction &MF, bool CheckExtra) { } } if (!Found) { - dbgs() << "Malformed PHI in BB#" << MBB->getNumber() << ": " << *MI; - dbgs() << " missing input from predecessor BB#" - << PredBB->getNumber() << '\n'; + dbgs() << "Malformed PHI in " << printMBBReference(*MBB) << ": " + << *MI; + dbgs() << " missing input from predecessor " + << printMBBReference(*PredBB) << '\n'; llvm_unreachable(nullptr); } } @@ -121,15 +122,16 @@ static void VerifyPHIs(MachineFunction &MF, bool CheckExtra) { for (unsigned i = 1, e = MI->getNumOperands(); i != e; i += 2) { MachineBasicBlock *PHIBB = MI->getOperand(i + 1).getMBB(); if (CheckExtra && !Preds.count(PHIBB)) { - dbgs() << "Warning: malformed PHI in BB#" << MBB->getNumber() << ": " - << *MI; - dbgs() << " extra input from predecessor BB#" << PHIBB->getNumber() - << '\n'; + dbgs() << "Warning: malformed PHI in " << printMBBReference(*MBB) + << ": " << *MI; + dbgs() << " extra input from predecessor " + << printMBBReference(*PHIBB) << '\n'; llvm_unreachable(nullptr); } if (PHIBB->getNumber() < 0) { - dbgs() << "Malformed PHI in BB#" << MBB->getNumber() << ": " << *MI; - dbgs() << " non-existing BB#" << PHIBB->getNumber() << '\n'; + dbgs() << "Malformed PHI in " << printMBBReference(*MBB) << ": " + << *MI; + dbgs() << " non-existing " << printMBBReference(*PHIBB) << '\n'; llvm_unreachable(nullptr); } } @@ -783,7 +785,8 @@ bool TailDuplicator::tailDuplicate(bool IsSimple, MachineBasicBlock *TailBB, MachineBasicBlock *ForcedLayoutPred, SmallVectorImpl &TDBBs, SmallVectorImpl &Copies) { - DEBUG(dbgs() << "\n*** Tail-duplicating BB#" << TailBB->getNumber() << '\n'); + DEBUG(dbgs() << "\n*** Tail-duplicating " << printMBBReference(*TailBB) + << '\n'); DenseSet UsedByPhi; getRegsUsedByPHIs(*TailBB, &UsedByPhi); diff --git a/lib/CodeGen/TargetPassConfig.cpp b/lib/CodeGen/TargetPassConfig.cpp index 3f2a31a69cfa1..121bed5a79cbb 100644 --- a/lib/CodeGen/TargetPassConfig.cpp +++ b/lib/CodeGen/TargetPassConfig.cpp @@ -93,11 +93,11 @@ static cl::opt DisablePartialLibcallInlining("disable-partial-libcall-inli static cl::opt EnableImplicitNullChecks( "enable-implicit-null-checks", cl::desc("Fold null checks into faulting memory operations"), - cl::init(false)); -static cl::opt EnableMergeICmps( - "enable-mergeicmps", - cl::desc("Merge ICmp chains into a single memcmp"), - cl::init(false)); + cl::init(false), cl::Hidden); +static cl::opt + EnableMergeICmps("enable-mergeicmps", + cl::desc("Merge ICmp chains into a single memcmp"), + cl::init(false), cl::Hidden); static cl::opt PrintLSR("print-lsr-output", cl::Hidden, cl::desc("Print LLVM IR produced by the loop-reduce pass")); static cl::opt PrintISelInput("print-isel-input", cl::Hidden, @@ -127,10 +127,9 @@ static cl::opt EnableGlobalISel("global-isel", cl::Hidden, cl::desc("Enable the \"global\" instruction selector")); -static cl::opt -PrintMachineInstrs("print-machineinstrs", cl::ValueOptional, - cl::desc("Print machine instrs"), - cl::value_desc("pass-name"), cl::init("option-unspecified")); +static cl::opt PrintMachineInstrs( + "print-machineinstrs", cl::ValueOptional, cl::desc("Print machine instrs"), + cl::value_desc("pass-name"), cl::init("option-unspecified"), cl::Hidden); static cl::opt EnableGlobalISelAbort( "global-isel-abort", cl::Hidden, @@ -176,22 +175,22 @@ const char *StopBeforeOptName = "stop-before"; static cl::opt StartAfterOpt(StringRef(StartAfterOptName), cl::desc("Resume compilation after a specific pass"), - cl::value_desc("pass-name"), cl::init("")); + cl::value_desc("pass-name"), cl::init(""), cl::Hidden); static cl::opt StartBeforeOpt(StringRef(StartBeforeOptName), cl::desc("Resume compilation before a specific pass"), - cl::value_desc("pass-name"), cl::init("")); + cl::value_desc("pass-name"), cl::init(""), cl::Hidden); static cl::opt StopAfterOpt(StringRef(StopAfterOptName), cl::desc("Stop compilation after a specific pass"), - cl::value_desc("pass-name"), cl::init("")); + cl::value_desc("pass-name"), cl::init(""), cl::Hidden); static cl::opt StopBeforeOpt(StringRef(StopBeforeOptName), cl::desc("Stop compilation before a specific pass"), - cl::value_desc("pass-name"), cl::init("")); + cl::value_desc("pass-name"), cl::init(""), cl::Hidden); /// Allow standard passes to be disabled by command line options. This supports /// simple binary flags that either suppress the pass or do nothing. @@ -767,10 +766,9 @@ bool TargetPassConfig::addISelPasses() { /// -regalloc=... command line option. static FunctionPass *useDefaultRegisterAllocator() { return nullptr; } static cl::opt > -RegAlloc("regalloc", - cl::init(&useDefaultRegisterAllocator), - cl::desc("Register allocator to use")); + RegisterPassParser> + RegAlloc("regalloc", cl::Hidden, cl::init(&useDefaultRegisterAllocator), + cl::desc("Register allocator to use")); /// Add the complete set of target-independent postISel code generator passes. /// diff --git a/lib/CodeGen/TargetRegisterInfo.cpp b/lib/CodeGen/TargetRegisterInfo.cpp index cc5c14856084c..f4e5583cbe7b1 100644 --- a/lib/CodeGen/TargetRegisterInfo.cpp +++ b/lib/CodeGen/TargetRegisterInfo.cpp @@ -93,12 +93,15 @@ Printable printReg(unsigned Reg, const TargetRegisterInfo *TRI, else if (TargetRegisterInfo::isStackSlot(Reg)) OS << "SS#" << TargetRegisterInfo::stackSlot2Index(Reg); else if (TargetRegisterInfo::isVirtualRegister(Reg)) - OS << "%vreg" << TargetRegisterInfo::virtReg2Index(Reg); - else if (TRI && Reg < TRI->getNumRegs()) { + OS << '%' << TargetRegisterInfo::virtReg2Index(Reg); + else if (!TRI) + OS << '%' << "physreg" << Reg; + else if (Reg < TRI->getNumRegs()) { OS << '%'; printLowerCase(TRI->getName(Reg), OS); } else - OS << "%physreg" << Reg; + llvm_unreachable("Register kind is unsupported."); + if (SubIdx) { if (TRI) OS << ':' << TRI->getSubRegIndexName(SubIdx); @@ -134,7 +137,7 @@ Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI) { Printable printVRegOrUnit(unsigned Unit, const TargetRegisterInfo *TRI) { return Printable([Unit, TRI](raw_ostream &OS) { if (TRI && TRI->isVirtualRegister(Unit)) { - OS << "%vreg" << TargetRegisterInfo::virtReg2Index(Unit); + OS << '%' << TargetRegisterInfo::virtReg2Index(Unit); } else { OS << printRegUnit(Unit, TRI); } diff --git a/lib/CodeGen/TwoAddressInstructionPass.cpp b/lib/CodeGen/TwoAddressInstructionPass.cpp index b996850d706f1..28a4375cb28b6 100644 --- a/lib/CodeGen/TwoAddressInstructionPass.cpp +++ b/lib/CodeGen/TwoAddressInstructionPass.cpp @@ -110,6 +110,10 @@ class TwoAddressInstructionPass : public MachineFunctionPass { // Set of already processed instructions in the current block. SmallPtrSet Processed; + // Set of instructions converted to three-address by target and then sunk + // down current basic block. + SmallPtrSet SunkInstrs; + // A map from virtual registers to physical registers which are likely targets // to be coalesced to due to copies from physical registers to virtual // registers. e.g. v1024 = move r0. @@ -756,6 +760,8 @@ TwoAddressInstructionPass::convertInstTo3Addr(MachineBasicBlock::iterator &mi, mi = NewMI; nmi = std::next(mi); } + else + SunkInstrs.insert(NewMI); // Update source and destination register maps. SrcRegMap.erase(RegA); @@ -1674,10 +1680,13 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &Func) { SrcRegMap.clear(); DstRegMap.clear(); Processed.clear(); + SunkInstrs.clear(); for (MachineBasicBlock::iterator mi = MBB->begin(), me = MBB->end(); mi != me; ) { MachineBasicBlock::iterator nmi = std::next(mi); - if (mi->isDebugValue()) { + // Don't revisit an instruction previously converted by target. It may + // contain undef register operands (%noreg), which are not handled. + if (mi->isDebugValue() || SunkInstrs.count(&*mi)) { mi = nmi; continue; } diff --git a/lib/DebugInfo/CodeView/AppendingTypeTableBuilder.cpp b/lib/DebugInfo/CodeView/AppendingTypeTableBuilder.cpp new file mode 100644 index 0000000000000..8828671d9be9d --- /dev/null +++ b/lib/DebugInfo/CodeView/AppendingTypeTableBuilder.cpp @@ -0,0 +1,101 @@ +//===- AppendingTypeTableBuilder.cpp --------------------------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#include "llvm/DebugInfo/CodeView/AppendingTypeTableBuilder.h" +#include "llvm/ADT/ArrayRef.h" +#include "llvm/ADT/DenseSet.h" +#include "llvm/ADT/STLExtras.h" +#include "llvm/DebugInfo/CodeView/CodeView.h" +#include "llvm/DebugInfo/CodeView/ContinuationRecordBuilder.h" +#include "llvm/DebugInfo/CodeView/RecordSerialization.h" +#include "llvm/DebugInfo/CodeView/TypeIndex.h" +#include "llvm/Support/Allocator.h" +#include "llvm/Support/BinaryByteStream.h" +#include "llvm/Support/BinaryStreamWriter.h" +#include "llvm/Support/Endian.h" +#include "llvm/Support/Error.h" +#include +#include +#include +#include + +using namespace llvm; +using namespace llvm::codeview; + +TypeIndex AppendingTypeTableBuilder::nextTypeIndex() const { + return TypeIndex::fromArrayIndex(SeenRecords.size()); +} + +AppendingTypeTableBuilder::AppendingTypeTableBuilder(BumpPtrAllocator &Storage) + : RecordStorage(Storage) {} + +AppendingTypeTableBuilder::~AppendingTypeTableBuilder() = default; + +Optional AppendingTypeTableBuilder::getFirst() { + if (empty()) + return None; + + return TypeIndex(TypeIndex::FirstNonSimpleIndex); +} + +Optional AppendingTypeTableBuilder::getNext(TypeIndex Prev) { + if (++Prev == nextTypeIndex()) + return None; + return Prev; +} + +CVType AppendingTypeTableBuilder::getType(TypeIndex Index) { + CVType Type; + Type.RecordData = SeenRecords[Index.toArrayIndex()]; + const RecordPrefix *P = + reinterpret_cast(Type.RecordData.data()); + Type.Type = static_cast(uint16_t(P->RecordKind)); + return Type; +} + +StringRef AppendingTypeTableBuilder::getTypeName(TypeIndex Index) { + llvm_unreachable("Method not implemented"); +} + +bool AppendingTypeTableBuilder::contains(TypeIndex Index) { + if (Index.isSimple() || Index.isNoneType()) + return false; + + return Index.toArrayIndex() < SeenRecords.size(); +} + +uint32_t AppendingTypeTableBuilder::size() { return SeenRecords.size(); } + +uint32_t AppendingTypeTableBuilder::capacity() { return SeenRecords.size(); } + +ArrayRef> AppendingTypeTableBuilder::records() const { + return SeenRecords; +} + +void AppendingTypeTableBuilder::reset() { SeenRecords.clear(); } + +TypeIndex +AppendingTypeTableBuilder::insertRecordBytes(ArrayRef &Record) { + TypeIndex NewTI = nextTypeIndex(); + uint8_t *Stable = RecordStorage.Allocate(Record.size()); + memcpy(Stable, Record.data(), Record.size()); + Record = ArrayRef(Stable, Record.size()); + SeenRecords.push_back(Record); + return NewTI; +} + +TypeIndex +AppendingTypeTableBuilder::insertRecord(ContinuationRecordBuilder &Builder) { + TypeIndex TI; + auto Fragments = Builder.end(nextTypeIndex()); + assert(!Fragments.empty()); + for (auto C : Fragments) + TI = insertRecordBytes(C.RecordData); + return TI; +} diff --git a/lib/DebugInfo/CodeView/CMakeLists.txt b/lib/DebugInfo/CodeView/CMakeLists.txt index 566ebaeae80a9..7d18c98bdc300 100644 --- a/lib/DebugInfo/CodeView/CMakeLists.txt +++ b/lib/DebugInfo/CodeView/CMakeLists.txt @@ -1,4 +1,5 @@ add_llvm_library(LLVMDebugInfoCodeView + AppendingTypeTableBuilder.cpp CodeViewError.cpp CodeViewRecordIO.cpp ContinuationRecordBuilder.cpp @@ -20,6 +21,7 @@ add_llvm_library(LLVMDebugInfoCodeView Formatters.cpp LazyRandomTypeCollection.cpp Line.cpp + MergingTypeTableBuilder.cpp RecordName.cpp RecordSerialization.cpp SimpleTypeSerializer.cpp @@ -31,7 +33,6 @@ add_llvm_library(LLVMDebugInfoCodeView TypeIndex.cpp TypeIndexDiscovery.cpp TypeRecordMapping.cpp - TypeTableBuilder.cpp TypeStreamMerger.cpp TypeTableCollection.cpp diff --git a/lib/DebugInfo/CodeView/MergingTypeTableBuilder.cpp b/lib/DebugInfo/CodeView/MergingTypeTableBuilder.cpp new file mode 100644 index 0000000000000..514d55aed0b2e --- /dev/null +++ b/lib/DebugInfo/CodeView/MergingTypeTableBuilder.cpp @@ -0,0 +1,154 @@ +//===- MergingTypeTableBuilder.cpp ----------------------------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#include "llvm/DebugInfo/CodeView/MergingTypeTableBuilder.h" +#include "llvm/ADT/ArrayRef.h" +#include "llvm/ADT/DenseSet.h" +#include "llvm/ADT/STLExtras.h" +#include "llvm/DebugInfo/CodeView/CodeView.h" +#include "llvm/DebugInfo/CodeView/ContinuationRecordBuilder.h" +#include "llvm/DebugInfo/CodeView/RecordSerialization.h" +#include "llvm/DebugInfo/CodeView/TypeIndex.h" +#include "llvm/Support/Allocator.h" +#include "llvm/Support/BinaryByteStream.h" +#include "llvm/Support/BinaryStreamWriter.h" +#include "llvm/Support/Endian.h" +#include "llvm/Support/Error.h" +#include +#include +#include +#include + +using namespace llvm; +using namespace llvm::codeview; + +static HashedType Empty{0, {}, TypeIndex::None()}; +static HashedType Tombstone{hash_code(-1), {}, TypeIndex::None()}; + +namespace llvm { + +template <> struct DenseMapInfo { + static inline HashedType getEmptyKey() { return Empty; } + + static inline HashedType getTombstoneKey() { return Tombstone; } + + static unsigned getHashValue(HashedType Val) { return Val.Hash; } + + static bool isEqual(HashedType LHS, HashedType RHS) { + if (RHS.Hash != LHS.Hash) + return false; + return RHS.Data == LHS.Data; + } +}; + +} // end namespace llvm + +TypeIndex MergingTypeTableBuilder::nextTypeIndex() const { + return TypeIndex::fromArrayIndex(SeenRecords.size()); +} + +MergingTypeTableBuilder::MergingTypeTableBuilder(BumpPtrAllocator &Storage) + : RecordStorage(Storage) { + SeenRecords.reserve(4096); + SeenHashes.reserve(4096); +} + +MergingTypeTableBuilder::~MergingTypeTableBuilder() = default; + +Optional MergingTypeTableBuilder::getFirst() { + if (empty()) + return None; + + return TypeIndex(TypeIndex::FirstNonSimpleIndex); +} + +Optional MergingTypeTableBuilder::getNext(TypeIndex Prev) { + if (++Prev == nextTypeIndex()) + return None; + return Prev; +} + +CVType MergingTypeTableBuilder::getType(TypeIndex Index) { + CVType Type; + Type.RecordData = SeenRecords[Index.toArrayIndex()]; + const RecordPrefix *P = + reinterpret_cast(Type.RecordData.data()); + Type.Type = static_cast(uint16_t(P->RecordKind)); + return Type; +} + +StringRef MergingTypeTableBuilder::getTypeName(TypeIndex Index) { + llvm_unreachable("Method not implemented"); +} + +bool MergingTypeTableBuilder::contains(TypeIndex Index) { + if (Index.isSimple() || Index.isNoneType()) + return false; + + return Index.toArrayIndex() < SeenRecords.size(); +} + +uint32_t MergingTypeTableBuilder::size() { return SeenRecords.size(); } + +uint32_t MergingTypeTableBuilder::capacity() { return SeenRecords.size(); } + +ArrayRef> MergingTypeTableBuilder::records() const { + return SeenRecords; +} + +ArrayRef MergingTypeTableBuilder::hashes() const { + return SeenHashes; +} + +void MergingTypeTableBuilder::reset() { + HashedRecords.clear(); + SeenHashes.clear(); + SeenRecords.clear(); +} + +static inline ArrayRef stabilize(BumpPtrAllocator &Alloc, + ArrayRef Data) { + uint8_t *Stable = Alloc.Allocate(Data.size()); + memcpy(Stable, Data.data(), Data.size()); + return makeArrayRef(Stable, Data.size()); +} + +TypeIndex MergingTypeTableBuilder::insertRecordAs(hash_code Hash, + ArrayRef &Record) { + assert(Record.size() < UINT32_MAX && "Record too big"); + assert(Record.size() % 4 == 0 && "Record is not aligned to 4 bytes!"); + + HashedType TempHashedType = {Hash, Record, nextTypeIndex()}; + auto Result = HashedRecords.insert(TempHashedType); + + if (Result.second) { + Result.first->Data = stabilize(RecordStorage, Record); + SeenRecords.push_back(Result.first->Data); + SeenHashes.push_back(Result.first->Hash); + } + + // Update the caller's copy of Record to point a stable copy. + Record = Result.first->Data; + return Result.first->Index; +} + +TypeIndex +MergingTypeTableBuilder::insertRecordBytes(ArrayRef &Record) { + return insertRecordAs(hash_value(Record), Record); +} + +TypeIndex +MergingTypeTableBuilder::insertRecord(ContinuationRecordBuilder &Builder) { + TypeIndex TI; + auto Fragments = Builder.end(nextTypeIndex()); + assert(!Fragments.empty()); + for (auto C : Fragments) + TI = insertRecordBytes(C.RecordData); + return TI; +} diff --git a/lib/DebugInfo/CodeView/TypeStreamMerger.cpp b/lib/DebugInfo/CodeView/TypeStreamMerger.cpp index 465f01aab9da4..5865ed9796944 100644 --- a/lib/DebugInfo/CodeView/TypeStreamMerger.cpp +++ b/lib/DebugInfo/CodeView/TypeStreamMerger.cpp @@ -10,11 +10,11 @@ #include "llvm/DebugInfo/CodeView/TypeStreamMerger.h" #include "llvm/ADT/SmallString.h" #include "llvm/ADT/StringExtras.h" +#include "llvm/DebugInfo/CodeView/MergingTypeTableBuilder.h" #include "llvm/DebugInfo/CodeView/TypeDeserializer.h" #include "llvm/DebugInfo/CodeView/TypeIndex.h" #include "llvm/DebugInfo/CodeView/TypeIndexDiscovery.h" #include "llvm/DebugInfo/CodeView/TypeRecord.h" -#include "llvm/DebugInfo/CodeView/TypeTableBuilder.h" #include "llvm/Support/Error.h" #include "llvm/Support/ScopedPrinter.h" @@ -64,12 +64,14 @@ class TypeStreamMerger { static const TypeIndex Untranslated; - Error mergeTypesAndIds(TypeTableBuilder &DestIds, TypeTableBuilder &DestTypes, + Error mergeTypesAndIds(MergingTypeTableBuilder &DestIds, + MergingTypeTableBuilder &DestTypes, const CVTypeArray &IdsAndTypes); - Error mergeIdRecords(TypeTableBuilder &Dest, + Error mergeIdRecords(MergingTypeTableBuilder &Dest, ArrayRef TypeSourceToDest, const CVTypeArray &Ids); - Error mergeTypeRecords(TypeTableBuilder &Dest, const CVTypeArray &Types); + Error mergeTypeRecords(MergingTypeTableBuilder &Dest, + const CVTypeArray &Types); private: Error doit(const CVTypeArray &Types); @@ -106,8 +108,8 @@ class TypeStreamMerger { TypeIndex CurIndex{TypeIndex::FirstNonSimpleIndex}; - TypeTableBuilder *DestIdStream = nullptr; - TypeTableBuilder *DestTypeStream = nullptr; + MergingTypeTableBuilder *DestIdStream = nullptr; + MergingTypeTableBuilder *DestTypeStream = nullptr; // If we're only mapping id records, this array contains the mapping for // type records. @@ -221,14 +223,14 @@ bool TypeStreamMerger::remapItemIndex(TypeIndex &Idx) { return remapIndex(Idx, IndexMap); } -Error TypeStreamMerger::mergeTypeRecords(TypeTableBuilder &Dest, +Error TypeStreamMerger::mergeTypeRecords(MergingTypeTableBuilder &Dest, const CVTypeArray &Types) { DestTypeStream = &Dest; return doit(Types); } -Error TypeStreamMerger::mergeIdRecords(TypeTableBuilder &Dest, +Error TypeStreamMerger::mergeIdRecords(MergingTypeTableBuilder &Dest, ArrayRef TypeSourceToDest, const CVTypeArray &Ids) { DestIdStream = &Dest; @@ -237,8 +239,8 @@ Error TypeStreamMerger::mergeIdRecords(TypeTableBuilder &Dest, return doit(Ids); } -Error TypeStreamMerger::mergeTypesAndIds(TypeTableBuilder &DestIds, - TypeTableBuilder &DestTypes, +Error TypeStreamMerger::mergeTypesAndIds(MergingTypeTableBuilder &DestIds, + MergingTypeTableBuilder &DestTypes, const CVTypeArray &IdsAndTypes) { DestIdStream = &DestIds; DestTypeStream = &DestTypes; @@ -286,7 +288,7 @@ Error TypeStreamMerger::remapAllTypes(const CVTypeArray &Types) { } Error TypeStreamMerger::remapType(const CVType &Type) { - TypeTableBuilder &Dest = + MergingTypeTableBuilder &Dest = isIdRecord(Type.kind()) ? *DestIdStream : *DestTypeStream; RemappedType R(Type); @@ -329,14 +331,14 @@ bool TypeStreamMerger::remapIndices(RemappedType &Record, return Success; } -Error llvm::codeview::mergeTypeRecords(TypeTableBuilder &Dest, +Error llvm::codeview::mergeTypeRecords(MergingTypeTableBuilder &Dest, SmallVectorImpl &SourceToDest, const CVTypeArray &Types) { TypeStreamMerger M(SourceToDest); return M.mergeTypeRecords(Dest, Types); } -Error llvm::codeview::mergeIdRecords(TypeTableBuilder &Dest, +Error llvm::codeview::mergeIdRecords(MergingTypeTableBuilder &Dest, ArrayRef TypeSourceToDest, SmallVectorImpl &SourceToDest, const CVTypeArray &Ids) { @@ -345,7 +347,7 @@ Error llvm::codeview::mergeIdRecords(TypeTableBuilder &Dest, } Error llvm::codeview::mergeTypeAndIdRecords( - TypeTableBuilder &DestIds, TypeTableBuilder &DestTypes, + MergingTypeTableBuilder &DestIds, MergingTypeTableBuilder &DestTypes, SmallVectorImpl &SourceToDest, const CVTypeArray &IdsAndTypes) { TypeStreamMerger M(SourceToDest); return M.mergeTypesAndIds(DestIds, DestTypes, IdsAndTypes); diff --git a/lib/DebugInfo/CodeView/TypeTableBuilder.cpp b/lib/DebugInfo/CodeView/TypeTableBuilder.cpp deleted file mode 100644 index ad61b0b220bcf..0000000000000 --- a/lib/DebugInfo/CodeView/TypeTableBuilder.cpp +++ /dev/null @@ -1,215 +0,0 @@ -//===- TypeSerialzier.cpp -------------------------------------------------===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// - -#include "llvm/DebugInfo/CodeView/TypeTableBuilder.h" -#include "llvm/ADT/ArrayRef.h" -#include "llvm/ADT/DenseSet.h" -#include "llvm/ADT/STLExtras.h" -#include "llvm/DebugInfo/CodeView/CodeView.h" -#include "llvm/DebugInfo/CodeView/ContinuationRecordBuilder.h" -#include "llvm/DebugInfo/CodeView/RecordSerialization.h" -#include "llvm/DebugInfo/CodeView/TypeIndex.h" -#include "llvm/Support/Allocator.h" -#include "llvm/Support/BinaryByteStream.h" -#include "llvm/Support/BinaryStreamWriter.h" -#include "llvm/Support/Endian.h" -#include "llvm/Support/Error.h" -#include -#include -#include -#include - -using namespace llvm; -using namespace llvm::codeview; - -namespace { - -struct HashedType { - hash_code Hash; - ArrayRef Data; - TypeIndex Index; -}; - -/// Wrapper around a poitner to a HashedType. Hash and equality operations are -/// based on data in the pointee. -struct HashedTypePtr { - HashedTypePtr() = default; - HashedTypePtr(HashedType *Ptr) : Ptr(Ptr) {} - - HashedType *Ptr = nullptr; -}; - -} // end anonymous namespace - -namespace llvm { - -template <> struct DenseMapInfo { - static inline HashedTypePtr getEmptyKey() { return HashedTypePtr(nullptr); } - - static inline HashedTypePtr getTombstoneKey() { - return HashedTypePtr(reinterpret_cast(1)); - } - - static unsigned getHashValue(HashedTypePtr Val) { - assert(Val.Ptr != getEmptyKey().Ptr && Val.Ptr != getTombstoneKey().Ptr); - return Val.Ptr->Hash; - } - - static bool isEqual(HashedTypePtr LHSP, HashedTypePtr RHSP) { - HashedType *LHS = LHSP.Ptr; - HashedType *RHS = RHSP.Ptr; - if (RHS == getEmptyKey().Ptr || RHS == getTombstoneKey().Ptr) - return LHS == RHS; - if (LHS->Hash != RHS->Hash) - return false; - return LHS->Data == RHS->Data; - } -}; - -} // end namespace llvm - -/// Private implementation so that we don't leak our DenseMap instantiations to -/// users. -class llvm::codeview::TypeHasher { -private: - /// Storage for type record provided by the caller. Records will outlive the - /// hasher object, so they should be allocated here. - BumpPtrAllocator &RecordStorage; - - /// Storage for hash keys. These only need to live as long as the hashing - /// operation. - BumpPtrAllocator KeyStorage; - - /// Hash table. We really want a DenseMap, TypeIndex> here, - /// but DenseMap is inefficient when the keys are long (like type records) - /// because it recomputes the hash value of every key when it grows. This - /// value type stores the hash out of line in KeyStorage, so that table - /// entries are small and easy to rehash. - DenseSet HashedRecords; - -public: - TypeHasher(BumpPtrAllocator &RecordStorage) : RecordStorage(RecordStorage) {} - - void reset() { HashedRecords.clear(); } - - /// Takes the bytes of type record, inserts them into the hash table, saves - /// them, and returns a pointer to an identical stable type record along with - /// its type index in the destination stream. - TypeIndex getOrCreateRecord(ArrayRef &Record, TypeIndex TI); -}; - -TypeIndex TypeHasher::getOrCreateRecord(ArrayRef &Record, - TypeIndex TI) { - assert(Record.size() < UINT32_MAX && "Record too big"); - assert(Record.size() % 4 == 0 && "Record is not aligned to 4 bytes!"); - - // Compute the hash up front so we can store it in the key. - HashedType TempHashedType = {hash_value(Record), Record, TI}; - auto Result = HashedRecords.insert(HashedTypePtr(&TempHashedType)); - HashedType *&Hashed = Result.first->Ptr; - - if (Result.second) { - // This was a new type record. We need stable storage for both the key and - // the record. The record should outlive the hashing operation. - Hashed = KeyStorage.Allocate(); - *Hashed = TempHashedType; - - uint8_t *Stable = RecordStorage.Allocate(Record.size()); - memcpy(Stable, Record.data(), Record.size()); - Hashed->Data = makeArrayRef(Stable, Record.size()); - } - - // Update the caller's copy of Record to point a stable copy. - Record = Hashed->Data; - return Hashed->Index; -} - -TypeIndex TypeTableBuilder::nextTypeIndex() const { - return TypeIndex::fromArrayIndex(SeenRecords.size()); -} - -TypeTableBuilder::TypeTableBuilder(BumpPtrAllocator &Storage, bool Hash) - : RecordStorage(Storage) { - if (Hash) - Hasher = llvm::make_unique(Storage); -} - -TypeTableBuilder::~TypeTableBuilder() = default; - -Optional TypeTableBuilder::getFirst() { - if (empty()) - return None; - - return TypeIndex(TypeIndex::FirstNonSimpleIndex); -} - -Optional TypeTableBuilder::getNext(TypeIndex Prev) { - if (++Prev == nextTypeIndex()) - return None; - return Prev; -} - -CVType TypeTableBuilder::getType(TypeIndex Index) { - CVType Type; - Type.RecordData = SeenRecords[Index.toArrayIndex()]; - const RecordPrefix *P = - reinterpret_cast(Type.RecordData.data()); - Type.Type = static_cast(uint16_t(P->RecordKind)); - return Type; -} - -StringRef TypeTableBuilder::getTypeName(TypeIndex Index) { - llvm_unreachable("Method not implemented"); -} - -bool TypeTableBuilder::contains(TypeIndex Index) { - if (Index.isSimple() || Index.isNoneType()) - return false; - - return Index.toArrayIndex() < SeenRecords.size(); -} - -uint32_t TypeTableBuilder::size() { return SeenRecords.size(); } - -uint32_t TypeTableBuilder::capacity() { return SeenRecords.size(); } - -ArrayRef> TypeTableBuilder::records() const { - return SeenRecords; -} - -void TypeTableBuilder::reset() { - if (Hasher) - Hasher->reset(); - SeenRecords.clear(); -} - -TypeIndex TypeTableBuilder::insertRecordBytes(ArrayRef &Record) { - if (Hasher) { - TypeIndex ActualTI = Hasher->getOrCreateRecord(Record, nextTypeIndex()); - if (nextTypeIndex() == ActualTI) - SeenRecords.push_back(Record); - return ActualTI; - } - - TypeIndex NewTI = nextTypeIndex(); - uint8_t *Stable = RecordStorage.Allocate(Record.size()); - memcpy(Stable, Record.data(), Record.size()); - Record = ArrayRef(Stable, Record.size()); - SeenRecords.push_back(Record); - return NewTI; -} - -TypeIndex TypeTableBuilder::insertRecord(ContinuationRecordBuilder &Builder) { - TypeIndex TI; - auto Fragments = Builder.end(nextTypeIndex()); - assert(!Fragments.empty()); - for (auto C : Fragments) - TI = insertRecordBytes(C.RecordData); - return TI; -} diff --git a/lib/DebugInfo/DWARF/DWARFContext.cpp b/lib/DebugInfo/DWARF/DWARFContext.cpp index 5893f223c074a..414959c7a5c60 100644 --- a/lib/DebugInfo/DWARF/DWARFContext.cpp +++ b/lib/DebugInfo/DWARF/DWARFContext.cpp @@ -357,12 +357,16 @@ void DWARFContext::dump( // Verbose dumping is done during parsing and not on the intermediate // representation. OS << "debug_line[" << format("0x%8.8x", Offset) << "]\n"; + unsigned OldOffset = Offset; if (DumpOpts.Verbose) { LineTable.parse(LineData, &Offset, U, &OS); } else { LineTable.parse(LineData, &Offset, U); LineTable.dump(OS); } + // Check for unparseable prologue, to avoid infinite loops. + if (OldOffset == Offset) + break; } } diff --git a/lib/FuzzMutate/IRMutator.cpp b/lib/FuzzMutate/IRMutator.cpp index 6545446a98492..15e7f86d1cdfc 100644 --- a/lib/FuzzMutate/IRMutator.cpp +++ b/lib/FuzzMutate/IRMutator.cpp @@ -105,6 +105,8 @@ void InjectorIRStrategy::mutate(BasicBlock &BB, RandomIRBuilder &IB) { SmallVector Insts; for (auto I = BB.getFirstInsertionPt(), E = BB.end(); I != E; ++I) Insts.push_back(&*I); + if (Insts.size() < 1) + return; // Choose an insertion point for our new instruction. size_t IP = uniform(IB.Rand, 0, Insts.size() - 1); @@ -147,7 +149,9 @@ void InstDeleterIRStrategy::mutate(Function &F, RandomIRBuilder &IB) { for (Instruction &Inst : instructions(F)) if (!Inst.isTerminator()) RS.sample(&Inst, /*Weight=*/1); - assert(!RS.isEmpty() && "No instructions to delete"); + if (RS.isEmpty()) + return; + // Delete the instruction. mutate(*RS.getSelection(), IB); // Clean up any dead code that's left over after removing the instruction. diff --git a/lib/FuzzMutate/Operations.cpp b/lib/FuzzMutate/Operations.cpp index 083d9aa039e19..af2775ebcfb30 100644 --- a/lib/FuzzMutate/Operations.cpp +++ b/lib/FuzzMutate/Operations.cpp @@ -216,8 +216,9 @@ OpDescriptor llvm::fuzzerop::extractValueDescriptor(unsigned Weight) { static SourcePred matchScalarInAggregate() { auto Pred = [](ArrayRef Cur, const Value *V) { - if (isa(Cur[0]->getType())) - return V->getType() == Cur[0]->getType(); + if (auto *ArrayT = dyn_cast(Cur[0]->getType())) + return V->getType() == ArrayT->getElementType(); + auto *STy = cast(Cur[0]->getType()); for (int I = 0, E = STy->getNumElements(); I < E; ++I) if (STy->getTypeAtIndex(I) == V->getType()) @@ -225,8 +226,9 @@ static SourcePred matchScalarInAggregate() { return false; }; auto Make = [](ArrayRef Cur, ArrayRef) { - if (isa(Cur[0]->getType())) - return makeConstantsWithType(Cur[0]->getType()); + if (auto *ArrayT = dyn_cast(Cur[0]->getType())) + return makeConstantsWithType(ArrayT->getElementType()); + std::vector Result; auto *STy = cast(Cur[0]->getType()); for (int I = 0, E = STy->getNumElements(); I < E; ++I) @@ -240,9 +242,9 @@ static SourcePred validInsertValueIndex() { auto Pred = [](ArrayRef Cur, const Value *V) { auto *CTy = cast(Cur[0]->getType()); if (auto *CI = dyn_cast(V)) - if (CI->getBitWidth() == 32) - if (CTy->getTypeAtIndex(CI->getZExtValue()) == V->getType()) - return true; + if (CI->getBitWidth() == 32 && + CTy->getTypeAtIndex(CI->getZExtValue()) == Cur[1]->getType()) + return true; return false; }; auto Make = [](ArrayRef Cur, ArrayRef Ts) { diff --git a/lib/FuzzMutate/RandomIRBuilder.cpp b/lib/FuzzMutate/RandomIRBuilder.cpp index 42e30464b0d49..7dfe4c63e0b18 100644 --- a/lib/FuzzMutate/RandomIRBuilder.cpp +++ b/lib/FuzzMutate/RandomIRBuilder.cpp @@ -45,22 +45,25 @@ Value *RandomIRBuilder::newSource(BasicBlock &BB, ArrayRef Insts, // Generate some constants to choose from. auto RS = makeSampler(Rand); RS.sample(Pred.generate(Srcs, KnownTypes)); - assert(!RS.isEmpty() && "Failed to generate sources"); // If we can find a pointer to load from, use it half the time. Value *Ptr = findPointer(BB, Insts, Srcs, Pred); - if (Ptr) - RS.sample(Ptr, RS.totalWeight()); + if (Ptr) { + // Create load from the chosen pointer + auto IP = BB.getFirstInsertionPt(); + if (auto *I = dyn_cast(Ptr)) + IP = ++I->getIterator(); + auto *NewLoad = new LoadInst(Ptr, "L", &*IP); - Value *Result = RS.getSelection(); - if (Result != Ptr) - return Result; + // Only sample this load if it really matches the descriptor + if (Pred.matches(Srcs, NewLoad)) + RS.sample(NewLoad, RS.totalWeight()); + else + NewLoad->eraseFromParent(); + } - // If we choose the pointer, we need to create a load. - auto IP = BB.getFirstInsertionPt(); - if (auto *I = dyn_cast(Ptr)) - IP = ++I->getIterator(); - return new LoadInst(Ptr, "L", &*IP); + assert(!RS.isEmpty() && "Failed to generate sources"); + return RS.getSelection(); } static bool isCompatibleReplacement(const Instruction *I, const Use &Operand, @@ -73,12 +76,13 @@ static bool isCompatibleReplacement(const Instruction *I, const Use &Operand, case Instruction::ExtractValue: // TODO: We could potentially validate these, but for now just leave indices // alone. - if (Operand.getOperandNo() > 1) + if (Operand.getOperandNo() >= 1) return false; break; case Instruction::InsertValue: case Instruction::InsertElement: - if (Operand.getOperandNo() > 2) + case Instruction::ShuffleVector: + if (Operand.getOperandNo() >= 2) return false; break; default: diff --git a/lib/IR/ConstantFold.cpp b/lib/IR/ConstantFold.cpp index c826f757e6dde..90b10309b58bd 100644 --- a/lib/IR/ConstantFold.cpp +++ b/lib/IR/ConstantFold.cpp @@ -2210,17 +2210,17 @@ Constant *llvm::ConstantFoldGetElementPtr(Type *PointeeTy, Constant *C, SmallVector NewIdxs; Type *Ty = PointeeTy; Type *Prev = C->getType(); - bool Unknown = !isa(Idxs[0]); + bool Unknown = + !isa(Idxs[0]) && !isa(Idxs[0]); for (unsigned i = 1, e = Idxs.size(); i != e; Prev = Ty, Ty = cast(Ty)->getTypeAtIndex(Idxs[i]), ++i) { - auto *CI = dyn_cast(Idxs[i]); - if (!CI) { + if (!isa(Idxs[i]) && !isa(Idxs[i])) { // We don't know if it's in range or not. Unknown = true; continue; } - if (!isa(Idxs[i - 1])) - // FIXME: add the support of cosntant vector index. + if (!isa(Idxs[i - 1]) && !isa(Idxs[i - 1])) + // Skip if the type of the previous index is not supported. continue; if (InRangeIndex && i == *InRangeIndex + 1) { // If an index is marked inrange, we cannot apply this canonicalization to @@ -2238,46 +2238,91 @@ Constant *llvm::ConstantFoldGetElementPtr(Type *PointeeTy, Constant *C, Unknown = true; continue; } - if (isIndexInRangeOfArrayType(STy->getNumElements(), CI)) - // It's in range, skip to the next index. - continue; + if (ConstantInt *CI = dyn_cast(Idxs[i])) { + if (isIndexInRangeOfArrayType(STy->getNumElements(), CI)) + // It's in range, skip to the next index. + continue; + if (CI->getSExtValue() < 0) { + // It's out of range and negative, don't try to factor it. + Unknown = true; + continue; + } + } else { + auto *CV = cast(Idxs[i]); + bool InRange = true; + for (unsigned I = 0, E = CV->getNumElements(); I != E; ++I) { + auto *CI = cast(CV->getElementAsConstant(I)); + InRange &= isIndexInRangeOfArrayType(STy->getNumElements(), CI); + if (CI->getSExtValue() < 0) { + Unknown = true; + break; + } + } + if (InRange || Unknown) + // It's in range, skip to the next index. + // It's out of range and negative, don't try to factor it. + continue; + } if (isa(Prev)) { // It's out of range, but the prior dimension is a struct // so we can't do anything about it. Unknown = true; continue; } - if (CI->getSExtValue() < 0) { - // It's out of range and negative, don't try to factor it. - Unknown = true; - continue; - } // It's out of range, but we can factor it into the prior // dimension. NewIdxs.resize(Idxs.size()); // Determine the number of elements in our sequential type. uint64_t NumElements = STy->getArrayNumElements(); - ConstantInt *Factor = ConstantInt::get(CI->getType(), NumElements); - NewIdxs[i] = ConstantExpr::getSRem(CI, Factor); + // Expand the current index or the previous index to a vector from a scalar + // if necessary. + Constant *CurrIdx = cast(Idxs[i]); + auto *PrevIdx = + NewIdxs[i - 1] ? NewIdxs[i - 1] : cast(Idxs[i - 1]); + bool IsCurrIdxVector = CurrIdx->getType()->isVectorTy(); + bool IsPrevIdxVector = PrevIdx->getType()->isVectorTy(); + bool UseVector = IsCurrIdxVector || IsPrevIdxVector; + + if (!IsCurrIdxVector && IsPrevIdxVector) + CurrIdx = ConstantDataVector::getSplat( + PrevIdx->getType()->getVectorNumElements(), CurrIdx); + + if (!IsPrevIdxVector && IsCurrIdxVector) + PrevIdx = ConstantDataVector::getSplat( + CurrIdx->getType()->getVectorNumElements(), PrevIdx); + + Constant *Factor = + ConstantInt::get(CurrIdx->getType()->getScalarType(), NumElements); + if (UseVector) + Factor = ConstantDataVector::getSplat( + IsPrevIdxVector ? PrevIdx->getType()->getVectorNumElements() + : CurrIdx->getType()->getVectorNumElements(), + Factor); + + NewIdxs[i] = ConstantExpr::getSRem(CurrIdx, Factor); - Constant *PrevIdx = NewIdxs[i-1] ? NewIdxs[i-1] : - cast(Idxs[i - 1]); - Constant *Div = ConstantExpr::getSDiv(CI, Factor); + Constant *Div = ConstantExpr::getSDiv(CurrIdx, Factor); unsigned CommonExtendedWidth = - std::max(PrevIdx->getType()->getIntegerBitWidth(), - Div->getType()->getIntegerBitWidth()); + std::max(PrevIdx->getType()->getScalarSizeInBits(), + Div->getType()->getScalarSizeInBits()); CommonExtendedWidth = std::max(CommonExtendedWidth, 64U); // Before adding, extend both operands to i64 to avoid // overflow trouble. - if (!PrevIdx->getType()->isIntegerTy(CommonExtendedWidth)) - PrevIdx = ConstantExpr::getSExt( - PrevIdx, Type::getIntNTy(Div->getContext(), CommonExtendedWidth)); - if (!Div->getType()->isIntegerTy(CommonExtendedWidth)) - Div = ConstantExpr::getSExt( - Div, Type::getIntNTy(Div->getContext(), CommonExtendedWidth)); + Type *ExtendedTy = Type::getIntNTy(Div->getContext(), CommonExtendedWidth); + if (UseVector) + ExtendedTy = VectorType::get( + ExtendedTy, IsPrevIdxVector + ? PrevIdx->getType()->getVectorNumElements() + : CurrIdx->getType()->getVectorNumElements()); + + if (!PrevIdx->getType()->isIntOrIntVectorTy(CommonExtendedWidth)) + PrevIdx = ConstantExpr::getSExt(PrevIdx, ExtendedTy); + + if (!Div->getType()->isIntOrIntVectorTy(CommonExtendedWidth)) + Div = ConstantExpr::getSExt(Div, ExtendedTy); NewIdxs[i - 1] = ConstantExpr::getAdd(PrevIdx, Div); } diff --git a/lib/IR/DIBuilder.cpp b/lib/IR/DIBuilder.cpp index 837b1ec5857d3..a00c595d01c5c 100644 --- a/lib/IR/DIBuilder.cpp +++ b/lib/IR/DIBuilder.cpp @@ -27,8 +27,8 @@ using namespace llvm::dwarf; cl::opt UseDbgAddr("use-dbg-addr", - llvm::cl::desc("Use llvm.dbg.addr for all local variables"), - cl::init(false)); + llvm::cl::desc("Use llvm.dbg.addr for all local variables"), + cl::init(false), cl::Hidden); DIBuilder::DIBuilder(Module &m, bool AllowUnresolvedNodes) : M(m), VMContext(M.getContext()), CUNode(nullptr), diff --git a/lib/IR/Dominators.cpp b/lib/IR/Dominators.cpp index a5900e49ad00a..a6127a5ef08dc 100644 --- a/lib/IR/Dominators.cpp +++ b/lib/IR/Dominators.cpp @@ -33,9 +33,9 @@ bool llvm::VerifyDomInfo = true; #else bool llvm::VerifyDomInfo = false; #endif -static cl::opt -VerifyDomInfoX("verify-dom-info", cl::location(VerifyDomInfo), - cl::desc("Verify dominator info (time consuming)")); +static cl::opt + VerifyDomInfoX("verify-dom-info", cl::location(VerifyDomInfo), cl::Hidden, + cl::desc("Verify dominator info (time consuming)")); bool BasicBlockEdge::isSingleEdge() const { const TerminatorInst *TI = Start->getTerminator(); diff --git a/lib/IR/IRPrintingPasses.cpp b/lib/IR/IRPrintingPasses.cpp index 4c8afda18b711..3b32814bed5cb 100644 --- a/lib/IR/IRPrintingPasses.cpp +++ b/lib/IR/IRPrintingPasses.cpp @@ -44,8 +44,12 @@ PrintFunctionPass::PrintFunctionPass(raw_ostream &OS, const std::string &Banner) PreservedAnalyses PrintFunctionPass::run(Function &F, FunctionAnalysisManager &) { - if (isFunctionInPrintList(F.getName())) - OS << Banner << static_cast(F); + if (isFunctionInPrintList(F.getName())) { + if (forcePrintModuleIR()) + OS << Banner << " (function: " << F.getName() << ")\n" << *F.getParent(); + else + OS << Banner << static_cast(F); + } return PreservedAnalyses::all(); } diff --git a/lib/IR/LegacyPassManager.cpp b/lib/IR/LegacyPassManager.cpp index 995e1e5703404..8bd9ed6ef0faa 100644 --- a/lib/IR/LegacyPassManager.cpp +++ b/lib/IR/LegacyPassManager.cpp @@ -75,21 +75,25 @@ PrintAfter("print-after", llvm::cl::desc("Print IR after specified passes"), cl::Hidden); +static cl::opt PrintBeforeAll("print-before-all", + llvm::cl::desc("Print IR before each pass"), + cl::init(false), cl::Hidden); +static cl::opt PrintAfterAll("print-after-all", + llvm::cl::desc("Print IR after each pass"), + cl::init(false), cl::Hidden); + static cl::opt -PrintBeforeAll("print-before-all", - llvm::cl::desc("Print IR before each pass"), - cl::init(false)); -static cl::opt -PrintAfterAll("print-after-all", - llvm::cl::desc("Print IR after each pass"), - cl::init(false)); + PrintModuleScope("print-module-scope", + cl::desc("When printing IR for print-[before|after]{-all} " + "always print a module IR"), + cl::init(false)); static cl::list PrintFuncsList("filter-print-funcs", cl::value_desc("function names"), cl::desc("Only print IR for functions whose name " "match this for all print-[before|after][-all] " "options"), - cl::CommaSeparated); + cl::CommaSeparated, cl::Hidden); /// This is a helper to determine whether to print IR before or /// after a pass. @@ -117,6 +121,8 @@ static bool ShouldPrintAfterPass(const PassInfo *PI) { return PrintAfterAll || ShouldPrintBeforeOrAfterPass(PI, PrintAfter); } +bool llvm::forcePrintModuleIR() { return PrintModuleScope; } + bool llvm::isFunctionInPrintList(StringRef FunctionName) { static std::unordered_set PrintFuncNames(PrintFuncsList.begin(), PrintFuncsList.end()); @@ -1729,9 +1735,9 @@ bool PassManager::run(Module &M) { // TimingInfo implementation bool llvm::TimePassesIsEnabled = false; -static cl::opt -EnableTiming("time-passes", cl::location(TimePassesIsEnabled), - cl::desc("Time each pass, printing elapsed time for each on exit")); +static cl::opt EnableTiming( + "time-passes", cl::location(TimePassesIsEnabled), cl::Hidden, + cl::desc("Time each pass, printing elapsed time for each on exit")); // createTheTimeInfo - This method either initializes the TheTimeInfo pointer to // a non-null value (if the -time-passes option is enabled) or it leaves it diff --git a/lib/IR/ValueSymbolTable.cpp b/lib/IR/ValueSymbolTable.cpp index ccdabe0817b4f..0da1990c3a3f8 100644 --- a/lib/IR/ValueSymbolTable.cpp +++ b/lib/IR/ValueSymbolTable.cpp @@ -13,7 +13,9 @@ #include "llvm/IR/ValueSymbolTable.h" #include "llvm/ADT/SmallString.h" +#include "llvm/ADT/Triple.h" #include "llvm/IR/GlobalValue.h" +#include "llvm/IR/Module.h" #include "llvm/IR/Type.h" #include "llvm/IR/Value.h" #include "llvm/Support/Casting.h" @@ -45,8 +47,17 @@ ValueName *ValueSymbolTable::makeUniqueName(Value *V, // Trim any suffix off and append the next number. UniqueName.resize(BaseSize); raw_svector_ostream S(UniqueName); - if (isa(V)) - S << "."; + if (auto *GV = dyn_cast(V)) { + // A dot is appended to mark it as clone during ABI demangling so that + // for example "_Z1fv" and "_Z1fv.1" both demangle to "f()", the second + // one being a clone. + // On NVPTX we cannot use a dot because PTX only allows [A-Za-z0-9_$] for + // identifiers. This breaks ABI demangling but at least ptxas accepts and + // compiles the program. + const Module *M = GV->getParent(); + if (!(M && Triple(M->getTargetTriple()).isNVPTX())) + S << "."; + } S << ++LastUnique; // Try insert the vmap entry with this suffix. diff --git a/lib/MC/MCAsmStreamer.cpp b/lib/MC/MCAsmStreamer.cpp index 44bac8eabdc7a..d1b475f2ca07e 100644 --- a/lib/MC/MCAsmStreamer.cpp +++ b/lib/MC/MCAsmStreamer.cpp @@ -1296,12 +1296,17 @@ void MCAsmStreamer::EmitCFIEndProcImpl(MCDwarfFrameInfo &Frame) { void MCAsmStreamer::EmitRegisterName(int64_t Register) { if (!MAI->useDwarfRegNumForCFI()) { + // User .cfi_* directives can use arbitrary DWARF register numbers, not + // just ones that map to LLVM register numbers and have known names. + // Fall back to using the original number directly if no name is known. const MCRegisterInfo *MRI = getContext().getRegisterInfo(); - unsigned LLVMRegister = MRI->getLLVMRegNum(Register, true); - InstPrinter->printRegName(OS, LLVMRegister); - } else { - OS << Register; + int LLVMRegister = MRI->getLLVMRegNumFromEH(Register); + if (LLVMRegister != -1) { + InstPrinter->printRegName(OS, LLVMRegister); + return; + } } + OS << Register; } void MCAsmStreamer::EmitCFIDefCfa(int64_t Register, int64_t Offset) { diff --git a/lib/MC/MCDwarf.cpp b/lib/MC/MCDwarf.cpp index a36ff4cb90721..748036e8a2577 100644 --- a/lib/MC/MCDwarf.cpp +++ b/lib/MC/MCDwarf.cpp @@ -277,8 +277,13 @@ MCDwarfLineTableHeader::Emit(MCStreamer *MCOS, MCDwarfLineTableParams Params, emitAbsValue(*MCOS, MakeStartMinusEndExpr(*MCOS, *LineStartSym, *LineEndSym, 4), 4); - // Next 2 bytes is the Version, which is Dwarf 2. - MCOS->EmitIntValue(2, 2); + // Next 2 bytes is the Version. + unsigned LineTableVersion = context.getDwarfVersion(); + // FIXME: Right now the compiler doesn't support line table V5. Until it's + // supported keep generating line table V4, when Dwarf Info version V5 is used. + if (LineTableVersion >= 5) + LineTableVersion = 4; + MCOS->EmitIntValue(LineTableVersion, 2); // Create a symbol for the end of the prologue (to be set when we get there). MCSymbol *ProEndSym = context.createTempSymbol(); // Lprologue_end @@ -293,6 +298,11 @@ MCDwarfLineTableHeader::Emit(MCStreamer *MCOS, MCDwarfLineTableParams Params, // Parameters of the state machine, are next. MCOS->EmitIntValue(context.getAsmInfo()->getMinInstAlignment(), 1); + // maximum_operations_per_instruction + // For non-VLIW architectures this field is always 1. + // FIXME: VLIW architectures need to update this field accordingly. + if (context.getDwarfVersion() >= 4) + MCOS->EmitIntValue(1, 1); MCOS->EmitIntValue(DWARF2_LINE_DEFAULT_IS_STMT, 1); MCOS->EmitIntValue(Params.DWARF2LineBase, 1); MCOS->EmitIntValue(Params.DWARF2LineRange, 1); @@ -1057,8 +1067,8 @@ void FrameEmitterImpl::EmitCFIInstruction(const MCCFIInstruction &Instr) { unsigned Reg1 = Instr.getRegister(); unsigned Reg2 = Instr.getRegister2(); if (!IsEH) { - Reg1 = MRI->getDwarfRegNum(MRI->getLLVMRegNum(Reg1, true), false); - Reg2 = MRI->getDwarfRegNum(MRI->getLLVMRegNum(Reg2, true), false); + Reg1 = MRI->getDwarfRegNumFromDwarfEHRegNum(Reg1); + Reg2 = MRI->getDwarfRegNumFromDwarfEHRegNum(Reg2); } Streamer.EmitIntValue(dwarf::DW_CFA_register, 1); Streamer.EmitULEB128IntValue(Reg1); @@ -1094,7 +1104,7 @@ void FrameEmitterImpl::EmitCFIInstruction(const MCCFIInstruction &Instr) { case MCCFIInstruction::OpDefCfa: { unsigned Reg = Instr.getRegister(); if (!IsEH) - Reg = MRI->getDwarfRegNum(MRI->getLLVMRegNum(Reg, true), false); + Reg = MRI->getDwarfRegNumFromDwarfEHRegNum(Reg); Streamer.EmitIntValue(dwarf::DW_CFA_def_cfa, 1); Streamer.EmitULEB128IntValue(Reg); CFAOffset = -Instr.getOffset(); @@ -1105,7 +1115,7 @@ void FrameEmitterImpl::EmitCFIInstruction(const MCCFIInstruction &Instr) { case MCCFIInstruction::OpDefCfaRegister: { unsigned Reg = Instr.getRegister(); if (!IsEH) - Reg = MRI->getDwarfRegNum(MRI->getLLVMRegNum(Reg, true), false); + Reg = MRI->getDwarfRegNumFromDwarfEHRegNum(Reg); Streamer.EmitIntValue(dwarf::DW_CFA_def_cfa_register, 1); Streamer.EmitULEB128IntValue(Reg); @@ -1118,7 +1128,7 @@ void FrameEmitterImpl::EmitCFIInstruction(const MCCFIInstruction &Instr) { unsigned Reg = Instr.getRegister(); if (!IsEH) - Reg = MRI->getDwarfRegNum(MRI->getLLVMRegNum(Reg, true), false); + Reg = MRI->getDwarfRegNumFromDwarfEHRegNum(Reg); int Offset = Instr.getOffset(); if (IsRelative) @@ -1154,7 +1164,7 @@ void FrameEmitterImpl::EmitCFIInstruction(const MCCFIInstruction &Instr) { case MCCFIInstruction::OpRestore: { unsigned Reg = Instr.getRegister(); if (!IsEH) - Reg = MRI->getDwarfRegNum(MRI->getLLVMRegNum(Reg, true), false); + Reg = MRI->getDwarfRegNumFromDwarfEHRegNum(Reg); Streamer.EmitIntValue(dwarf::DW_CFA_restore | Reg, 1); return; } diff --git a/lib/MC/MCObjectFileInfo.cpp b/lib/MC/MCObjectFileInfo.cpp index d8077df146986..ba0146fd9fcac 100644 --- a/lib/MC/MCObjectFileInfo.cpp +++ b/lib/MC/MCObjectFileInfo.cpp @@ -594,6 +594,8 @@ void MCObjectFileInfo::initELFMCObjectFileInfo(const Triple &T, bool Large) { EHFrameSection = Ctx->getELFSection(".eh_frame", EHSectionType, EHSectionFlags); + + StackSizesSection = Ctx->getELFSection(".stack_sizes", ELF::SHT_PROGBITS, 0); } void MCObjectFileInfo::initCOFFMCObjectFileInfo(const Triple &T) { diff --git a/lib/MC/MCRegisterInfo.cpp b/lib/MC/MCRegisterInfo.cpp index 0f76c1838b518..8e47963b44182 100644 --- a/lib/MC/MCRegisterInfo.cpp +++ b/lib/MC/MCRegisterInfo.cpp @@ -88,6 +88,34 @@ int MCRegisterInfo::getLLVMRegNum(unsigned RegNum, bool isEH) const { return I->ToReg; } +int MCRegisterInfo::getLLVMRegNumFromEH(unsigned RegNum) const { + const DwarfLLVMRegPair *M = EHDwarf2LRegs; + unsigned Size = EHDwarf2LRegsSize; + + if (!M) + return -1; + DwarfLLVMRegPair Key = { RegNum, 0 }; + const DwarfLLVMRegPair *I = std::lower_bound(M, M+Size, Key); + if (I == M+Size || I->FromReg != RegNum) + return -1; + return I->ToReg; +} + +int MCRegisterInfo::getDwarfRegNumFromDwarfEHRegNum(unsigned RegNum) const { + // On ELF platforms, DWARF EH register numbers are the same as DWARF + // other register numbers. On Darwin x86, they differ and so need to be + // mapped. The .cfi_* directives accept integer literals as well as + // register names and should generate exactly what the assembly code + // asked for, so there might be DWARF/EH register numbers that don't have + // a corresponding LLVM register number at all. So if we can't map the + // EH register number to an LLVM register number, assume it's just a + // valid DWARF register number as is. + int LRegNum = getLLVMRegNumFromEH(RegNum); + if (LRegNum != -1) + return getDwarfRegNum(LRegNum, false); + return RegNum; +} + int MCRegisterInfo::getSEHRegNum(unsigned RegNum) const { const DenseMap::const_iterator I = L2SEHRegs.find(RegNum); if (I == L2SEHRegs.end()) return (int)RegNum; diff --git a/lib/MC/MCWasmStreamer.cpp b/lib/MC/MCWasmStreamer.cpp index 287b7cf7b23f1..ef2a5621512b5 100644 --- a/lib/MC/MCWasmStreamer.cpp +++ b/lib/MC/MCWasmStreamer.cpp @@ -98,10 +98,13 @@ bool MCWasmStreamer::EmitSymbolAttribute(MCSymbol *S, MCSymbolAttr Attribute) { case MCSA_WeakDefAutoPrivate: case MCSA_Invalid: case MCSA_IndirectSymbol: - case MCSA_Hidden: case MCSA_Protected: return false; + case MCSA_Hidden: + Symbol->setHidden(true); + break; + case MCSA_Weak: case MCSA_WeakReference: Symbol->setWeak(true); diff --git a/lib/MC/WasmObjectWriter.cpp b/lib/MC/WasmObjectWriter.cpp index 6e9088b9d0dd8..42521ac72e2c3 100644 --- a/lib/MC/WasmObjectWriter.cpp +++ b/lib/MC/WasmObjectWriter.cpp @@ -1180,10 +1180,14 @@ void WasmObjectWriter::writeObject(MCAssembler &Asm, << S.isExternal() << " isTemporary=" << S.isTemporary() << " isFunction=" << WS.isFunction() << " isWeak=" << WS.isWeak() + << " isHidden=" << WS.isHidden() << " isVariable=" << WS.isVariable() << "\n"); - if (WS.isWeak()) - SymbolFlags.emplace_back(WS.getName(), wasm::WASM_SYMBOL_BINDING_WEAK); + if (WS.isWeak() || WS.isHidden()) { + uint32_t Flags = (WS.isWeak() ? wasm::WASM_SYMBOL_BINDING_WEAK : 0) | + (WS.isHidden() ? wasm::WASM_SYMBOL_VISIBILITY_HIDDEN : 0); + SymbolFlags.emplace_back(WS.getName(), Flags); + } if (WS.isVariable()) continue; diff --git a/lib/Object/ArchiveWriter.cpp b/lib/Object/ArchiveWriter.cpp index 8448b617b78b3..b3b812daae2ef 100644 --- a/lib/Object/ArchiveWriter.cpp +++ b/lib/Object/ArchiveWriter.cpp @@ -35,6 +35,15 @@ using namespace llvm; +// The SYM64 format is used when an archive's member offsets are larger than +// 32-bits can hold. The need for this shift in format is detected by +// writeArchive. To test this we need to generate a file with a member that has +// an offset larger than 32-bits but this demands a very slow test. To speed +// the test up we use this flag to pretend like the cutoff happens before +// 32-bits and instead happens at some much smaller value. +static cl::opt Sym64Threshold("sym64-threshold", cl::Hidden, + cl::init(32)); + NewArchiveMember::NewArchiveMember(MemoryBufferRef BufRef) : Buf(MemoryBuffer::getMemBuffer(BufRef, false)), MemberName(BufRef.getBufferIdentifier()) {} @@ -484,7 +493,7 @@ Error llvm::writeArchive(StringRef ArcName, // If LastOffset isn't going to fit in a 32-bit varible we need to switch // to 64-bit. Note that the file can be larger than 4GB as long as the last // member starts before the 4GB offset. - if (LastOffset >> 32 != 0) + if (LastOffset >= (1ULL << Sym64Threshold)) Kind = object::Archive::K_GNU64; } diff --git a/lib/Object/WasmObjectFile.cpp b/lib/Object/WasmObjectFile.cpp index 86ce9c2209c26..70ac598b89762 100644 --- a/lib/Object/WasmObjectFile.cpp +++ b/lib/Object/WasmObjectFile.cpp @@ -378,7 +378,7 @@ Error WasmObjectFile::parseLinkingSection(const uint8_t *Ptr, Symbols[SymIndex].Flags = Flags; DEBUG(dbgs() << "Set symbol flags index:" << SymIndex << " name:" - << Symbols[SymIndex].Name << " exptected:" + << Symbols[SymIndex].Name << " expected:" << Symbol << " flags: " << Flags << "\n"); } break; @@ -766,6 +766,8 @@ uint32_t WasmObjectFile::getSymbolFlags(DataRefImpl Symb) const { Result |= SymbolRef::SF_Weak; if (!Sym.isLocal()) Result |= SymbolRef::SF_Global; + if (Sym.isHidden()) + Result |= SymbolRef::SF_Hidden; switch (Sym.Type) { case WasmSymbol::SymbolType::FUNCTION_IMPORT: diff --git a/lib/ObjectYAML/CodeViewYAMLTypes.cpp b/lib/ObjectYAML/CodeViewYAMLTypes.cpp index 84b52b463c479..887328cf5082e 100644 --- a/lib/ObjectYAML/CodeViewYAMLTypes.cpp +++ b/lib/ObjectYAML/CodeViewYAMLTypes.cpp @@ -17,13 +17,13 @@ #include "llvm/ADT/ArrayRef.h" #include "llvm/ADT/StringRef.h" #include "llvm/BinaryFormat/COFF.h" +#include "llvm/DebugInfo/CodeView/AppendingTypeTableBuilder.h" #include "llvm/DebugInfo/CodeView/CVTypeVisitor.h" #include "llvm/DebugInfo/CodeView/CodeView.h" #include "llvm/DebugInfo/CodeView/CodeViewError.h" #include "llvm/DebugInfo/CodeView/ContinuationRecordBuilder.h" #include "llvm/DebugInfo/CodeView/TypeDeserializer.h" #include "llvm/DebugInfo/CodeView/TypeIndex.h" -#include "llvm/DebugInfo/CodeView/TypeTableBuilder.h" #include "llvm/DebugInfo/CodeView/TypeVisitorCallbacks.h" #include "llvm/Support/Allocator.h" #include "llvm/Support/BinaryStreamReader.h" @@ -83,7 +83,7 @@ struct LeafRecordBase { virtual ~LeafRecordBase() = default; virtual void map(yaml::IO &io) = 0; - virtual CVType toCodeViewRecord(TypeTableBuilder &TS) const = 0; + virtual CVType toCodeViewRecord(AppendingTypeTableBuilder &TS) const = 0; virtual Error fromCodeViewRecord(CVType Type) = 0; }; @@ -97,7 +97,7 @@ template struct LeafRecordImpl : public LeafRecordBase { return TypeDeserializer::deserializeAs(Type, Record); } - CVType toCodeViewRecord(TypeTableBuilder &TS) const override { + CVType toCodeViewRecord(AppendingTypeTableBuilder &TS) const override { TS.writeLeafType(Record); return CVType(Kind, TS.records().back()); } @@ -109,7 +109,7 @@ template <> struct LeafRecordImpl : public LeafRecordBase { explicit LeafRecordImpl(TypeLeafKind K) : LeafRecordBase(K) {} void map(yaml::IO &io) override; - CVType toCodeViewRecord(TypeTableBuilder &TS) const override; + CVType toCodeViewRecord(AppendingTypeTableBuilder &TS) const override; Error fromCodeViewRecord(CVType Type) override; std::vector Members; @@ -489,8 +489,8 @@ Error LeafRecordImpl::fromCodeViewRecord(CVType Type) { return visitMemberRecordStream(Type.content(), V); } -CVType -LeafRecordImpl::toCodeViewRecord(TypeTableBuilder &TS) const { +CVType LeafRecordImpl::toCodeViewRecord( + AppendingTypeTableBuilder &TS) const { ContinuationRecordBuilder CRB; CRB.begin(ContinuationRecordKind::FieldList); for (const auto &Member : Members) { @@ -682,7 +682,8 @@ Expected LeafRecord::fromCodeViewRecord(CVType Type) { return make_error(cv_error_code::corrupt_record); } -CVType LeafRecord::toCodeViewRecord(TypeTableBuilder &Serializer) const { +CVType +LeafRecord::toCodeViewRecord(AppendingTypeTableBuilder &Serializer) const { return Leaf->toCodeViewRecord(Serializer); } @@ -782,7 +783,7 @@ llvm::CodeViewYAML::fromDebugT(ArrayRef DebugT) { ArrayRef llvm::CodeViewYAML::toDebugT(ArrayRef Leafs, BumpPtrAllocator &Alloc) { - TypeTableBuilder TS(Alloc, false); + AppendingTypeTableBuilder TS(Alloc); uint32_t Size = sizeof(uint32_t); for (const auto &Leaf : Leafs) { CVType T = Leaf.Leaf->toCodeViewRecord(TS); diff --git a/lib/ProfileData/InstrProf.cpp b/lib/ProfileData/InstrProf.cpp index a732bedc6fa47..8ab5df59f538e 100644 --- a/lib/ProfileData/InstrProf.cpp +++ b/lib/ProfileData/InstrProf.cpp @@ -56,7 +56,7 @@ using namespace llvm; static cl::opt StaticFuncFullModulePrefix( - "static-func-full-module-prefix", cl::init(true), + "static-func-full-module-prefix", cl::init(true), cl::Hidden, cl::desc("Use full module build paths in the profile counter names for " "static functions.")); @@ -69,7 +69,7 @@ static cl::opt StaticFuncFullModulePrefix( // the source directory name not being stripped. A non-zero option value here // can potentially prevent some inter-module indirect-call-promotions. static cl::opt StaticFuncStripDirNamePrefix( - "static-func-strip-dirname-prefix", cl::init(0), + "static-func-strip-dirname-prefix", cl::init(0), cl::Hidden, cl::desc("Strip specified level of directory name from source path in " "the profile counter name for static functions.")); diff --git a/lib/Support/RandomNumberGenerator.cpp b/lib/Support/RandomNumberGenerator.cpp index 8ea02d709df17..47d20159200b1 100644 --- a/lib/Support/RandomNumberGenerator.cpp +++ b/lib/Support/RandomNumberGenerator.cpp @@ -32,8 +32,8 @@ using namespace llvm; // // Do not change to cl::opt since this silently breaks argument parsing. static cl::opt -Seed("rng-seed", cl::value_desc("seed"), - cl::desc("Seed for the random number generator"), cl::init(0)); + Seed("rng-seed", cl::value_desc("seed"), cl::Hidden, + cl::desc("Seed for the random number generator"), cl::init(0)); RandomNumberGenerator::RandomNumberGenerator(StringRef Salt) { DEBUG( diff --git a/lib/Support/Statistic.cpp b/lib/Support/Statistic.cpp index 72ca22806c43c..23718bb0e9c93 100644 --- a/lib/Support/Statistic.cpp +++ b/lib/Support/Statistic.cpp @@ -39,12 +39,14 @@ using namespace llvm; /// -stats - Command line option to cause transformations to emit stats about /// what they did. /// -static cl::opt Stats("stats", - cl::desc("Enable statistics output from program (available with Asserts)")); - +static cl::opt Stats( + "stats", + cl::desc("Enable statistics output from program (available with Asserts)"), + cl::Hidden); static cl::opt StatsAsJSON("stats-json", - cl::desc("Display statistics as json data")); + cl::desc("Display statistics as json data"), + cl::Hidden); static bool Enabled; static bool PrintOnExit; diff --git a/lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp b/lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp index db1fbe069f4d2..2d510a48d1cb2 100644 --- a/lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp +++ b/lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp @@ -538,7 +538,7 @@ bool AArch64A57FPLoadBalancing::colorChain(Chain *G, Color C, DEBUG(dbgs() << "Scavenging (thus coloring) failed!\n"); return false; } - DEBUG(dbgs() << " - Scavenged register: " << TRI->getName(Reg) << "\n"); + DEBUG(dbgs() << " - Scavenged register: " << printReg(Reg, TRI) << "\n"); std::map Substs; for (MachineInstr &I : *G) { @@ -611,8 +611,8 @@ void AArch64A57FPLoadBalancing::scanInstruction( // unit. unsigned DestReg = MI->getOperand(0).getReg(); - DEBUG(dbgs() << "New chain started for register " - << TRI->getName(DestReg) << " at " << *MI); + DEBUG(dbgs() << "New chain started for register " << printReg(DestReg, TRI) + << " at " << *MI); auto G = llvm::make_unique(MI, Idx, getColor(DestReg)); ActiveChains[DestReg] = G.get(); @@ -632,7 +632,7 @@ void AArch64A57FPLoadBalancing::scanInstruction( if (ActiveChains.find(AccumReg) != ActiveChains.end()) { DEBUG(dbgs() << "Chain found for accumulator register " - << TRI->getName(AccumReg) << " in MI " << *MI); + << printReg(AccumReg, TRI) << " in MI " << *MI); // For simplicity we only chain together sequences of MULs/MLAs where the // accumulator register is killed on each instruction. This means we don't @@ -657,7 +657,7 @@ void AArch64A57FPLoadBalancing::scanInstruction( } DEBUG(dbgs() << "Creating new chain for dest register " - << TRI->getName(DestReg) << "\n"); + << printReg(DestReg, TRI) << "\n"); auto G = llvm::make_unique(MI, Idx, getColor(DestReg)); ActiveChains[DestReg] = G.get(); AllChains.push_back(std::move(G)); @@ -685,8 +685,8 @@ maybeKillChain(MachineOperand &MO, unsigned Idx, // If this is a KILL of a current chain, record it. if (MO.isKill() && ActiveChains.find(MO.getReg()) != ActiveChains.end()) { - DEBUG(dbgs() << "Kill seen for chain " << TRI->getName(MO.getReg()) - << "\n"); + DEBUG(dbgs() << "Kill seen for chain " << printReg(MO.getReg(), TRI) + << "\n"); ActiveChains[MO.getReg()]->setKill(MI, Idx, /*Immutable=*/MO.isTied()); } ActiveChains.erase(MO.getReg()); @@ -697,7 +697,7 @@ maybeKillChain(MachineOperand &MO, unsigned Idx, I != E;) { if (MO.clobbersPhysReg(I->first)) { DEBUG(dbgs() << "Kill (regmask) seen for chain " - << TRI->getName(I->first) << "\n"); + << printReg(I->first, TRI) << "\n"); I->second->setKill(MI, Idx, /*Immutable=*/true); ActiveChains.erase(I++); } else diff --git a/lib/Target/AArch64/AArch64CallLowering.cpp b/lib/Target/AArch64/AArch64CallLowering.cpp index 5cc8881d1c16a..838305858ea48 100644 --- a/lib/Target/AArch64/AArch64CallLowering.cpp +++ b/lib/Target/AArch64/AArch64CallLowering.cpp @@ -259,6 +259,8 @@ bool AArch64CallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder, SmallVector SplitArgs; unsigned i = 0; for (auto &Arg : F.args()) { + if (DL.getTypeStoreSize(Arg.getType()) == 0) + continue; ArgInfo OrigArg{VRegs[i], Arg.getType()}; setArgFlags(OrigArg, i + AttributeList::FirstArgIndex, DL, F); bool Split = false; diff --git a/lib/Target/AArch64/AArch64ConditionOptimizer.cpp b/lib/Target/AArch64/AArch64ConditionOptimizer.cpp index d1bcd3dcaec4c..f765825cdee2d 100644 --- a/lib/Target/AArch64/AArch64ConditionOptimizer.cpp +++ b/lib/Target/AArch64/AArch64ConditionOptimizer.cpp @@ -207,7 +207,7 @@ MachineInstr *AArch64ConditionOptimizer::findSuitableCompare( return nullptr; } } - DEBUG(dbgs() << "Flags not defined in BB#" << MBB->getNumber() << '\n'); + DEBUG(dbgs() << "Flags not defined in " << printMBBReference(*MBB) << '\n'); return nullptr; } diff --git a/lib/Target/AArch64/AArch64ConditionalCompares.cpp b/lib/Target/AArch64/AArch64ConditionalCompares.cpp index 668d21d0b162d..f7c97117ba5ed 100644 --- a/lib/Target/AArch64/AArch64ConditionalCompares.cpp +++ b/lib/Target/AArch64/AArch64ConditionalCompares.cpp @@ -369,7 +369,7 @@ MachineInstr *SSACCmpConv::findConvertibleCompare(MachineBasicBlock *MBB) { return nullptr; } } - DEBUG(dbgs() << "Flags not defined in BB#" << MBB->getNumber() << '\n'); + DEBUG(dbgs() << "Flags not defined in " << printMBBReference(*MBB) << '\n'); return nullptr; } @@ -383,7 +383,7 @@ bool SSACCmpConv::canSpeculateInstrs(MachineBasicBlock *MBB, // Reject any live-in physregs. It's probably NZCV/EFLAGS, and very hard to // get right. if (!MBB->livein_empty()) { - DEBUG(dbgs() << "BB#" << MBB->getNumber() << " has live-ins.\n"); + DEBUG(dbgs() << printMBBReference(*MBB) << " has live-ins.\n"); return false; } @@ -396,7 +396,7 @@ bool SSACCmpConv::canSpeculateInstrs(MachineBasicBlock *MBB, continue; if (++InstrCount > BlockInstrLimit && !Stress) { - DEBUG(dbgs() << "BB#" << MBB->getNumber() << " has more than " + DEBUG(dbgs() << printMBBReference(*MBB) << " has more than " << BlockInstrLimit << " instructions.\n"); return false; } @@ -458,8 +458,9 @@ bool SSACCmpConv::canConvert(MachineBasicBlock *MBB) { return false; // The CFG topology checks out. - DEBUG(dbgs() << "\nTriangle: BB#" << Head->getNumber() << " -> BB#" - << CmpBB->getNumber() << " -> BB#" << Tail->getNumber() << '\n'); + DEBUG(dbgs() << "\nTriangle: " << printMBBReference(*Head) << " -> " + << printMBBReference(*CmpBB) << " -> " + << printMBBReference(*Tail) << '\n'); ++NumConsidered; // Tail is allowed to have many predecessors, but we can't handle PHIs yet. @@ -562,8 +563,9 @@ bool SSACCmpConv::canConvert(MachineBasicBlock *MBB) { } void SSACCmpConv::convert(SmallVectorImpl &RemovedBlocks) { - DEBUG(dbgs() << "Merging BB#" << CmpBB->getNumber() << " into BB#" - << Head->getNumber() << ":\n" << *CmpBB); + DEBUG(dbgs() << "Merging " << printMBBReference(*CmpBB) << " into " + << printMBBReference(*Head) << ":\n" + << *CmpBB); // All CmpBB instructions are moved into Head, and CmpBB is deleted. // Update the CFG first. diff --git a/lib/Target/AArch64/AArch64FrameLowering.cpp b/lib/Target/AArch64/AArch64FrameLowering.cpp index 257e6f6e946ec..72330d9b7cb2f 100644 --- a/lib/Target/AArch64/AArch64FrameLowering.cpp +++ b/lib/Target/AArch64/AArch64FrameLowering.cpp @@ -1060,9 +1060,9 @@ bool AArch64FrameLowering::spillCalleeSavedRegisters( StrOpc = RPI.isPaired() ? AArch64::STPXi : AArch64::STRXui; else StrOpc = RPI.isPaired() ? AArch64::STPDi : AArch64::STRDui; - DEBUG(dbgs() << "CSR spill: (" << TRI->getName(Reg1); + DEBUG(dbgs() << "CSR spill: (" << printReg(Reg1, TRI); if (RPI.isPaired()) - dbgs() << ", " << TRI->getName(Reg2); + dbgs() << ", " << printReg(Reg2, TRI); dbgs() << ") -> fi#(" << RPI.FrameIdx; if (RPI.isPaired()) dbgs() << ", " << RPI.FrameIdx+1; @@ -1123,9 +1123,9 @@ bool AArch64FrameLowering::restoreCalleeSavedRegisters( LdrOpc = RPI.isPaired() ? AArch64::LDPXi : AArch64::LDRXui; else LdrOpc = RPI.isPaired() ? AArch64::LDPDi : AArch64::LDRDui; - DEBUG(dbgs() << "CSR restore: (" << TRI->getName(Reg1); + DEBUG(dbgs() << "CSR restore: (" << printReg(Reg1, TRI); if (RPI.isPaired()) - dbgs() << ", " << TRI->getName(Reg2); + dbgs() << ", " << printReg(Reg2, TRI); dbgs() << ") -> fi#(" << RPI.FrameIdx; if (RPI.isPaired()) dbgs() << ", " << RPI.FrameIdx+1; @@ -1234,7 +1234,7 @@ void AArch64FrameLowering::determineCalleeSaves(MachineFunction &MF, if (BigStack) { if (!ExtraCSSpill && UnspilledCSGPR != AArch64::NoRegister) { DEBUG(dbgs() << "Spilling " << printReg(UnspilledCSGPR, RegInfo) - << " to get a scratch register.\n"); + << " to get a scratch register.\n"); SavedRegs.set(UnspilledCSGPR); // MachO's compact unwind format relies on all registers being stored in // pairs, so if we need to spill one extra for BigStack, then we need to diff --git a/lib/Target/AArch64/AArch64ISelLowering.cpp b/lib/Target/AArch64/AArch64ISelLowering.cpp index 589abaa5f7c8a..00c4504464858 100644 --- a/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -3885,9 +3885,6 @@ AArch64TargetLowering::LowerELFGlobalTLSAddress(SDValue Op, TLSModel::Model Model = getTargetMachine().getTLSModel(GA->getGlobal()); - if (DAG.getTarget().Options.EmulatedTLS) - return LowerToTLSEmulatedModel(GA, DAG); - if (!EnableAArch64ELFLocalDynamicTLSGeneration) { if (Model == TLSModel::LocalDynamic) Model = TLSModel::GeneralDynamic; @@ -3973,6 +3970,10 @@ AArch64TargetLowering::LowerELFGlobalTLSAddress(SDValue Op, SDValue AArch64TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const { + const GlobalAddressSDNode *GA = cast(Op); + if (DAG.getTarget().Options.EmulatedTLS) + return LowerToTLSEmulatedModel(GA, DAG); + if (Subtarget->isTargetDarwin()) return LowerDarwinGlobalTLSAddress(Op, DAG); if (Subtarget->isTargetELF()) diff --git a/lib/Target/AArch64/AArch64ISelLowering.h b/lib/Target/AArch64/AArch64ISelLowering.h index 2af40edd86216..28a52fdc32ae8 100644 --- a/lib/Target/AArch64/AArch64ISelLowering.h +++ b/lib/Target/AArch64/AArch64ISelLowering.h @@ -409,6 +409,9 @@ class AArch64TargetLowering : public TargetLowering { bool isIntDivCheap(EVT VT, AttributeList Attr) const override; + // Disable currently because of invalid merge. + bool mergeStoresAfterLegalization() const override { return false; } + bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT, const SelectionDAG &DAG) const override { // Do not merge to float value size (128 bytes) if no implicit diff --git a/lib/Target/AArch64/AArch64InstrAtomics.td b/lib/Target/AArch64/AArch64InstrAtomics.td index 4c61c3510ba5b..153bcf75cbcd0 100644 --- a/lib/Target/AArch64/AArch64InstrAtomics.td +++ b/lib/Target/AArch64/AArch64InstrAtomics.td @@ -30,18 +30,18 @@ def : Pat<(atomic_fence (imm), (imm)), (DMB (i32 0xb))>; // A atomic load operation that actually needs acquire semantics. class acquiring_load - : PatFrag<(ops node:$ptr), (base node:$ptr), [{ - AtomicOrdering Ordering = cast(N)->getOrdering(); - return isAcquireOrStronger(Ordering); -}]>; + : PatFrag<(ops node:$ptr), (base node:$ptr)> { + let IsAtomic = 1; + let IsAtomicOrderingAcquireOrStronger = 1; +} // An atomic load operation that does not need either acquire or release // semantics. class relaxed_load - : PatFrag<(ops node:$ptr), (base node:$ptr), [{ - AtomicOrdering Ordering = cast(N)->getOrdering(); - return !isAcquireOrStronger(Ordering); -}]>; + : PatFrag<(ops node:$ptr), (base node:$ptr)> { + let IsAtomic = 1; + let IsAtomicOrderingAcquireOrStronger = 0; +} // 8-bit loads def : Pat<(acquiring_load GPR64sp:$ptr), (LDARB GPR64sp:$ptr)>; @@ -113,19 +113,17 @@ def : Pat<(relaxed_load // A store operation that actually needs release semantics. class releasing_store - : PatFrag<(ops node:$ptr, node:$val), (base node:$ptr, node:$val), [{ - AtomicOrdering Ordering = cast(N)->getOrdering(); - assert(Ordering != AtomicOrdering::AcquireRelease && - "unexpected store ordering"); - return isReleaseOrStronger(Ordering); -}]>; + : PatFrag<(ops node:$ptr, node:$val), (base node:$ptr, node:$val)> { + let IsAtomic = 1; + let IsAtomicOrderingReleaseOrStronger = 1; +} // An atomic store operation that doesn't actually need to be atomic on AArch64. class relaxed_store - : PatFrag<(ops node:$ptr, node:$val), (base node:$ptr, node:$val), [{ - AtomicOrdering Ordering = cast(N)->getOrdering(); - return !isReleaseOrStronger(Ordering); -}]>; + : PatFrag<(ops node:$ptr, node:$val), (base node:$ptr, node:$val)> { + let IsAtomic = 1; + let IsAtomicOrderingReleaseOrStronger = 0; +} // 8-bit stores def : Pat<(releasing_store GPR64sp:$ptr, GPR32:$val), diff --git a/lib/Target/AArch64/AArch64InstrInfo.cpp b/lib/Target/AArch64/AArch64InstrInfo.cpp index bf5f0f624af14..bc3c0a4a60e04 100644 --- a/lib/Target/AArch64/AArch64InstrInfo.cpp +++ b/lib/Target/AArch64/AArch64InstrInfo.cpp @@ -2801,14 +2801,14 @@ MachineInstr *AArch64InstrInfo::foldMemoryOperandImpl( LiveIntervals *LIS) const { // This is a bit of a hack. Consider this instruction: // - // %vreg0 = COPY %sp; GPR64all:%vreg0 + // %0 = COPY %sp; GPR64all:%0 // // We explicitly chose GPR64all for the virtual register so such a copy might // be eliminated by RegisterCoalescer. However, that may not be possible, and - // %vreg0 may even spill. We can't spill %sp, and since it is in the GPR64all + // %0 may even spill. We can't spill %sp, and since it is in the GPR64all // register class, TargetInstrInfo::foldMemoryOperand() is going to try. // - // To prevent that, we are going to constrain the %vreg0 register class here. + // To prevent that, we are going to constrain the %0 register class here. // // // @@ -2830,7 +2830,7 @@ MachineInstr *AArch64InstrInfo::foldMemoryOperandImpl( // Handle the case where a copy is being spilled or filled but the source // and destination register class don't match. For example: // - // %vreg0 = COPY %xzr; GPR64common:%vreg0 + // %0 = COPY %xzr; GPR64common:%0 // // In this case we can still safely fold away the COPY and generate the // following spill code: @@ -2840,16 +2840,16 @@ MachineInstr *AArch64InstrInfo::foldMemoryOperandImpl( // This also eliminates spilled cross register class COPYs (e.g. between x and // d regs) of the same size. For example: // - // %vreg0 = COPY %vreg1; GPR64:%vreg0, FPR64:%vreg1 + // %0 = COPY %1; GPR64:%0, FPR64:%1 // // will be filled as // - // LDRDui %vreg0, fi<#0> + // LDRDui %0, fi<#0> // // instead of // - // LDRXui %vregTemp, fi<#0> - // %vreg0 = FMOV %vregTemp + // LDRXui %Temp, fi<#0> + // %0 = FMOV %Temp // if (MI.isCopy() && Ops.size() == 1 && // Make sure we're only folding the explicit COPY defs/uses. @@ -2886,7 +2886,7 @@ MachineInstr *AArch64InstrInfo::foldMemoryOperandImpl( // Handle cases like spilling def of: // - // %vreg0:sub_32 = COPY %wzr; GPR64common:%vreg0 + // %0:sub_32 = COPY %wzr; GPR64common:%0 // // where the physical register source can be widened and stored to the full // virtual reg destination stack slot, in this case producing: @@ -2934,12 +2934,12 @@ MachineInstr *AArch64InstrInfo::foldMemoryOperandImpl( // Handle cases like filling use of: // - // %vreg0:sub_32 = COPY %vreg1; GPR64:%vreg0, GPR32:%vreg1 + // %0:sub_32 = COPY %1; GPR64:%0, GPR32:%1 // // where we can load the full virtual reg source stack slot, into the subreg // destination, in this case producing: // - // LDRWui %vreg0:sub_32, + // LDRWui %0:sub_32, // if (IsFill && SrcMO.getSubReg() == 0 && DstMO.isUndef()) { const TargetRegisterClass *FillRC; diff --git a/lib/Target/AArch64/AArch64InstructionSelector.cpp b/lib/Target/AArch64/AArch64InstructionSelector.cpp index c2d3ae31c6243..6999721b6260c 100644 --- a/lib/Target/AArch64/AArch64InstructionSelector.cpp +++ b/lib/Target/AArch64/AArch64InstructionSelector.cpp @@ -889,12 +889,6 @@ bool AArch64InstructionSelector::select(MachineInstr &I, return false; } - auto &MemOp = **I.memoperands_begin(); - if (MemOp.getOrdering() != AtomicOrdering::NotAtomic) { - DEBUG(dbgs() << "Atomic load/store not supported yet\n"); - return false; - } - const unsigned PtrReg = I.getOperand(1).getReg(); #ifndef NDEBUG const RegisterBank &PtrRB = *RBI.getRegBank(PtrReg, MRI, TRI); diff --git a/lib/Target/AArch64/AArch64LegalizerInfo.cpp b/lib/Target/AArch64/AArch64LegalizerInfo.cpp index 54d1109a08f56..6531d5ebe4c0e 100644 --- a/lib/Target/AArch64/AArch64LegalizerInfo.cpp +++ b/lib/Target/AArch64/AArch64LegalizerInfo.cpp @@ -231,6 +231,14 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST) { setAction({MemOp, 1, p0}, Legal); } + for (unsigned MemOp : {G_ATOMIC_LOAD, G_ATOMIC_STORE}) { + for (auto Ty : {s8, s16, s32, s64, p0}) + setAction({MemOp, Ty}, Legal); + + // And everything's fine in addrspace 0. + setAction({MemOp, 1, p0}, Legal); + } + // Constants for (auto Ty : {s32, s64}) { setAction({TargetOpcode::G_CONSTANT, Ty}, Legal); @@ -351,8 +359,10 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST) { setAction({G_VAARG, Ty}, Custom); if (ST.hasLSE()) { - for (auto Ty : {s8, s16, s32, s64}) + for (auto Ty : {s8, s16, s32, s64}) { + setAction({G_ATOMIC_CMPXCHG_WITH_SUCCESS, Ty}, Lower); setAction({G_ATOMIC_CMPXCHG, Ty}, Legal); + } setAction({G_ATOMIC_CMPXCHG, 1, p0}, Legal); for (unsigned Op : @@ -366,6 +376,23 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST) { } } + // Merge/Unmerge + for (unsigned Op : {G_MERGE_VALUES, G_UNMERGE_VALUES}) + for (int Sz : {8, 16, 32, 64, 128, 192, 256, 384, 512}) { + LLT ScalarTy = LLT::scalar(Sz); + setAction({Op, ScalarTy}, Legal); + setAction({Op, 1, ScalarTy}, Legal); + if (Sz < 32) + continue; + for (int EltSize = 8; EltSize <= 64; EltSize *= 2) { + if (EltSize >= Sz) + continue; + LLT VecTy = LLT::vector(Sz / EltSize, EltSize); + setAction({Op, VecTy}, Legal); + setAction({Op, 1, VecTy}, Legal); + } + } + computeTables(); } diff --git a/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp b/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp index ec98980fa0b97..9848083537663 100644 --- a/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp +++ b/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp @@ -12,9 +12,9 @@ // 1. For BBs that are targets of CBZ/CBNZ instructions, we know the value of // the CBZ/CBNZ source register is zero on the taken/not-taken path. For // instance, the copy instruction in the code below can be removed because -// the CBZW jumps to BB#2 when w0 is zero. +// the CBZW jumps to %bb.2 when w0 is zero. // -// BB#1: +// %bb.1: // cbz w0, .LBB0_2 // .LBB0_2: // mov w0, wzr ; <-- redundant @@ -22,11 +22,11 @@ // 2. If the flag setting instruction defines a register other than WZR/XZR, we // can remove a zero copy in some cases. // -// BB#0: +// %bb.0: // subs w0, w1, w2 // str w0, [x1] // b.ne .LBB0_2 -// BB#1: +// %bb.1: // mov w0, wzr ; <-- redundant // str w0, [x2] // .LBB0_2 @@ -35,7 +35,7 @@ // constant (i.e., ADDS[W|X]ri, SUBS[W|X]ri), we can remove a mov immediate // in some cases. // -// BB#0: +// %bb.0: // subs xzr, x0, #1 // b.eq .LBB0_1 // .LBB0_1: diff --git a/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.cpp b/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.cpp index c5da457c38fff..12b5a27b7699a 100644 --- a/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.cpp +++ b/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.cpp @@ -104,6 +104,11 @@ AArch64MCAsmInfoELF::AArch64MCAsmInfoELF(const Triple &T) { AArch64MCAsmInfoCOFF::AArch64MCAsmInfoCOFF() { PrivateGlobalPrefix = ".L"; PrivateLabelPrefix = ".L"; + + Data16bitsDirective = "\t.hword\t"; + Data32bitsDirective = "\t.word\t"; + Data64bitsDirective = "\t.xword\t"; + AlignmentIsInBytes = false; SupportsDebugInformation = true; CodePointerSize = 8; diff --git a/lib/Target/AMDGPU/AMDGPU.td b/lib/Target/AMDGPU/AMDGPU.td index 71d93444bdf3d..3bf5c8885f57b 100644 --- a/lib/Target/AMDGPU/AMDGPU.td +++ b/lib/Target/AMDGPU/AMDGPU.td @@ -19,6 +19,12 @@ def FeatureFP64 : SubtargetFeature<"fp64", "Enable double precision operations" >; +def FeatureFMA : SubtargetFeature<"fmaf", + "FMA", + "true", + "Enable single precision FMA (not as fast as mul+add, but fused)" +>; + def FeatureFastFMAF32 : SubtargetFeature<"fast-fmaf", "FastFMAF32", "true", diff --git a/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp index 79d8de9203111..f4776adb069c9 100644 --- a/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp +++ b/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp @@ -356,9 +356,7 @@ SDNode *AMDGPUDAGToDAGISel::glueCopyToM0(SDNode *N) const { Ops.push_back(N->getOperand(i)); } Ops.push_back(Glue); - CurDAG->MorphNodeTo(N, N->getOpcode(), N->getVTList(), Ops); - - return N; + return CurDAG->MorphNodeTo(N, N->getOpcode(), N->getVTList(), Ops); } static unsigned selectSGPRVectorRegClassID(unsigned NumVectorElts) { @@ -456,7 +454,8 @@ void AMDGPUDAGToDAGISel::Select(SDNode *N) { N = glueCopyToM0(N); switch (Opc) { - default: break; + default: + break; // We are selecting i64 ADD here instead of custom lower it during // DAG legalization, so we can fold some i64 ADDs used for address // calculation into the LOAD and STORE instructions. @@ -703,6 +702,7 @@ bool AMDGPUDAGToDAGISel::SelectADDRIndirect(SDValue Addr, SDValue &Base, return true; } +// FIXME: Should only handle addcarry/subcarry void AMDGPUDAGToDAGISel::SelectADD_SUB_I64(SDNode *N) { SDLoc DL(N); SDValue LHS = N->getOperand(0); @@ -712,8 +712,7 @@ void AMDGPUDAGToDAGISel::SelectADD_SUB_I64(SDNode *N) { bool ConsumeCarry = (Opcode == ISD::ADDE || Opcode == ISD::SUBE); bool ProduceCarry = ConsumeCarry || Opcode == ISD::ADDC || Opcode == ISD::SUBC; - bool IsAdd = - (Opcode == ISD::ADD || Opcode == ISD::ADDC || Opcode == ISD::ADDE); + bool IsAdd = Opcode == ISD::ADD || Opcode == ISD::ADDC || Opcode == ISD::ADDE; SDValue Sub0 = CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32); SDValue Sub1 = CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32); @@ -876,8 +875,12 @@ bool AMDGPUDAGToDAGISel::SelectDS1Addr1Offset(SDValue Addr, SDValue &Base, Zero, Addr.getOperand(1)); if (isDSOffsetLegal(Sub, ByteOffset, 16)) { + // FIXME: Select to VOP3 version for with-carry. + unsigned SubOp = Subtarget->hasAddNoCarry() ? + AMDGPU::V_SUB_U32_e64 : AMDGPU::V_SUB_I32_e32; + MachineSDNode *MachineSub - = CurDAG->getMachineNode(AMDGPU::V_SUB_I32_e32, DL, MVT::i32, + = CurDAG->getMachineNode(SubOp, DL, MVT::i32, Zero, Addr.getOperand(1)); Base = SDValue(MachineSub, 0); @@ -946,8 +949,11 @@ bool AMDGPUDAGToDAGISel::SelectDS64Bit4ByteAligned(SDValue Addr, SDValue &Base, Zero, Addr.getOperand(1)); if (isDSOffsetLegal(Sub, DWordOffset1, 8)) { + unsigned SubOp = Subtarget->hasAddNoCarry() ? + AMDGPU::V_SUB_U32_e64 : AMDGPU::V_SUB_I32_e32; + MachineSDNode *MachineSub - = CurDAG->getMachineNode(AMDGPU::V_SUB_I32_e32, DL, MVT::i32, + = CurDAG->getMachineNode(SubOp, DL, MVT::i32, Zero, Addr.getOperand(1)); Base = SDValue(MachineSub, 0); @@ -2074,15 +2080,19 @@ void AMDGPUDAGToDAGISel::PostprocessISelDAG() { bool IsModified = false; do { IsModified = false; + // Go over all selected nodes and try to fold them a bit more - for (SDNode &Node : CurDAG->allnodes()) { - MachineSDNode *MachineNode = dyn_cast(&Node); + SelectionDAG::allnodes_iterator Position = CurDAG->allnodes_begin(); + while (Position != CurDAG->allnodes_end()) { + SDNode *Node = &*Position++; + MachineSDNode *MachineNode = dyn_cast(Node); if (!MachineNode) continue; SDNode *ResNode = Lowering.PostISelFolding(MachineNode, *CurDAG); - if (ResNode != &Node) { - ReplaceUses(&Node, ResNode); + if (ResNode != Node) { + if (ResNode) + ReplaceUses(Node, ResNode); IsModified = true; } } diff --git a/lib/Target/AMDGPU/AMDGPUInstrInfo.cpp b/lib/Target/AMDGPU/AMDGPUInstrInfo.cpp index 1e23aa8411ada..49447862b608b 100644 --- a/lib/Target/AMDGPU/AMDGPUInstrInfo.cpp +++ b/lib/Target/AMDGPU/AMDGPUInstrInfo.cpp @@ -56,15 +56,59 @@ bool AMDGPUInstrInfo::shouldScheduleLoadsNear(SDNode *Load0, SDNode *Load1, return (NumLoads <= 16 && (Offset1 - Offset0) < 64); } -int AMDGPUInstrInfo::getMaskedMIMGOp(uint16_t Opcode, unsigned Channels) const { - switch (Channels) { - default: return Opcode; - case 1: return AMDGPU::getMaskedMIMGOp(Opcode, AMDGPU::Channels_1); - case 2: return AMDGPU::getMaskedMIMGOp(Opcode, AMDGPU::Channels_2); - case 3: return AMDGPU::getMaskedMIMGOp(Opcode, AMDGPU::Channels_3); +static AMDGPU::Channels indexToChannel(unsigned Channel) { + switch (Channel) { + case 1: + return AMDGPU::Channels_1; + case 2: + return AMDGPU::Channels_2; + case 3: + return AMDGPU::Channels_3; + case 4: + return AMDGPU::Channels_4; + default: + llvm_unreachable("invalid MIMG channel"); } } +// FIXME: Need to handle d16 images correctly. +static unsigned rcToChannels(unsigned RCID) { + switch (RCID) { + case AMDGPU::VGPR_32RegClassID: + return 1; + case AMDGPU::VReg_64RegClassID: + return 2; + case AMDGPU::VReg_96RegClassID: + return 3; + case AMDGPU::VReg_128RegClassID: + return 4; + default: + llvm_unreachable("invalid MIMG register class"); + } +} + +int AMDGPUInstrInfo::getMaskedMIMGOp(unsigned Opc, + unsigned NewChannels) const { + AMDGPU::Channels Channel = indexToChannel(NewChannels); + unsigned OrigChannels = rcToChannels(get(Opc).OpInfo[0].RegClass); + if (NewChannels == OrigChannels) + return Opc; + + switch (OrigChannels) { + case 1: + return AMDGPU::getMaskedMIMGOp1(Opc, Channel); + case 2: + return AMDGPU::getMaskedMIMGOp2(Opc, Channel); + case 3: + return AMDGPU::getMaskedMIMGOp3(Opc, Channel); + case 4: + return AMDGPU::getMaskedMIMGOp4(Opc, Channel); + default: + llvm_unreachable("invalid MIMG channel"); + } +} + + // This must be kept in sync with the SIEncodingFamily class in SIInstrInfo.td enum SIEncodingFamily { SI = 0, diff --git a/lib/Target/AMDGPU/AMDGPUInstrInfo.h b/lib/Target/AMDGPU/AMDGPUInstrInfo.h index f1a42b42f1f1a..4ab0515d5ca48 100644 --- a/lib/Target/AMDGPU/AMDGPUInstrInfo.h +++ b/lib/Target/AMDGPU/AMDGPUInstrInfo.h @@ -50,9 +50,9 @@ class AMDGPUInstrInfo : public AMDGPUGenInstrInfo { /// not exist. If Opcode is not a pseudo instruction, this is identity. int pseudoToMCOpcode(int Opcode) const; - /// \brief Given a MIMG \p Opcode that writes all 4 channels, return the - /// equivalent opcode that writes \p Channels Channels. - int getMaskedMIMGOp(uint16_t Opcode, unsigned Channels) const; + /// \brief Given a MIMG \p MI that writes any number of channels, return the + /// equivalent opcode that writes \p NewChannels Channels. + int getMaskedMIMGOp(unsigned Opc, unsigned NewChannels) const; }; } // End llvm namespace diff --git a/lib/Target/AMDGPU/AMDGPUInstructions.td b/lib/Target/AMDGPU/AMDGPUInstructions.td index c14679701c0bb..31f728b0c22f3 100644 --- a/lib/Target/AMDGPU/AMDGPUInstructions.td +++ b/lib/Target/AMDGPU/AMDGPUInstructions.td @@ -49,6 +49,7 @@ def NoFP16Denormals : Predicate<"!Subtarget->hasFP16Denormals()">; def NoFP32Denormals : Predicate<"!Subtarget->hasFP32Denormals()">; def NoFP64Denormals : Predicate<"!Subtarget->hasFP64Denormals()">; def UnsafeFPMath : Predicate<"TM.Options.UnsafeFPMath">; +def FMA : Predicate<"Subtarget->hasFMA()">; def InstFlag : OperandWithDefaultOps ; def ADDRIndirect : ComplexPattern; diff --git a/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp b/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp index 879f65e122876..5ff82c5d1e003 100644 --- a/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp +++ b/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp @@ -270,8 +270,8 @@ LLVM_DUMP_METHOD void PHILinearize::dump(MachineRegisterInfo *MRI) { dbgs() << "Dest: " << printReg(Element.DestReg, TRI) << " Sources: {"; for (auto &SI : Element.Sources) { - dbgs() << printReg(SI.first, TRI) << "(BB#" - << SI.second->getNumber() << "),"; + dbgs() << printReg(SI.first, TRI) << '(' << printMBBReference(*SI.second) + << "),"; } dbgs() << "}\n"; } @@ -658,7 +658,7 @@ RegionMRT *MRT::buildMRT(MachineFunction &MF, continue; } - DEBUG(dbgs() << "Visiting BB#" << MBB->getNumber() << "\n"); + DEBUG(dbgs() << "Visiting " << printMBBReference(*MBB) << "\n"); MBBMRT *NewMBB = new MBBMRT(MBB); MachineRegion *Region = RegionInfo->getRegionFor(MBB); @@ -705,7 +705,7 @@ void LinearizedRegion::storeLiveOutReg(MachineBasicBlock *MBB, unsigned Reg, // If this is live out of the MBB for (auto &UI : MRI->use_operands(Reg)) { if (UI.getParent()->getParent() != MBB) { - DEBUG(dbgs() << "Add LiveOut (MBB BB#" << MBB->getNumber() + DEBUG(dbgs() << "Add LiveOut (MBB " << printMBBReference(*MBB) << "): " << printReg(Reg, TRI) << "\n"); addLiveOut(Reg); } else { @@ -749,7 +749,8 @@ void LinearizedRegion::storeLiveOuts(MachineBasicBlock *MBB, const MachineRegisterInfo *MRI, const TargetRegisterInfo *TRI, PHILinearize &PHIInfo) { - DEBUG(dbgs() << "-Store Live Outs Begin (BB#" << MBB->getNumber() << ")-\n"); + DEBUG(dbgs() << "-Store Live Outs Begin (" << printMBBReference(*MBB) + << ")-\n"); for (auto &II : *MBB) { for (auto &RI : II.defs()) { storeLiveOutReg(MBB, RI.getReg(), RI.getParent(), MRI, TRI, PHIInfo); @@ -773,8 +774,8 @@ void LinearizedRegion::storeLiveOuts(MachineBasicBlock *MBB, for (int i = 0; i < numPreds; ++i) { if (getPHIPred(PHI, i) == MBB) { unsigned PHIReg = getPHISourceReg(PHI, i); - DEBUG(dbgs() << "Add LiveOut (PhiSource BB#" << MBB->getNumber() - << " -> BB#" << (*SI)->getNumber() + DEBUG(dbgs() << "Add LiveOut (PhiSource " << printMBBReference(*MBB) + << " -> " << printMBBReference(*(*SI)) << "): " << printReg(PHIReg, TRI) << "\n"); addLiveOut(PHIReg); } @@ -1480,8 +1481,8 @@ bool AMDGPUMachineCFGStructurizer::shrinkPHI(MachineInstr &PHI, if (SourceMBB) { MIB.addReg(CombinedSourceReg); MIB.addMBB(SourceMBB); - DEBUG(dbgs() << printReg(CombinedSourceReg, TRI) << ", BB#" - << SourceMBB->getNumber()); + DEBUG(dbgs() << printReg(CombinedSourceReg, TRI) << ", " + << printMBBReference(*SourceMBB)); } for (unsigned i = 0; i < NumInputs; ++i) { @@ -1492,8 +1493,8 @@ bool AMDGPUMachineCFGStructurizer::shrinkPHI(MachineInstr &PHI, MachineBasicBlock *SourcePred = getPHIPred(PHI, i); MIB.addReg(SourceReg); MIB.addMBB(SourcePred); - DEBUG(dbgs() << printReg(SourceReg, TRI) << ", BB#" - << SourcePred->getNumber()); + DEBUG(dbgs() << printReg(SourceReg, TRI) << ", " + << printMBBReference(*SourcePred)); } DEBUG(dbgs() << ")\n"); } @@ -1524,8 +1525,8 @@ void AMDGPUMachineCFGStructurizer::replacePHI( getPHIDestReg(PHI)); MIB.addReg(CombinedSourceReg); MIB.addMBB(LastMerge); - DEBUG(dbgs() << printReg(CombinedSourceReg, TRI) << ", BB#" - << LastMerge->getNumber()); + DEBUG(dbgs() << printReg(CombinedSourceReg, TRI) << ", " + << printMBBReference(*LastMerge)); for (unsigned i = 0; i < NumInputs; ++i) { if (isPHIRegionIndex(PHIRegionIndices, i)) { continue; @@ -1534,8 +1535,8 @@ void AMDGPUMachineCFGStructurizer::replacePHI( MachineBasicBlock *SourcePred = getPHIPred(PHI, i); MIB.addReg(SourceReg); MIB.addMBB(SourcePred); - DEBUG(dbgs() << printReg(SourceReg, TRI) << ", BB#" - << SourcePred->getNumber()); + DEBUG(dbgs() << printReg(SourceReg, TRI) << ", " + << printMBBReference(*SourcePred)); } DEBUG(dbgs() << ")\n"); } else { @@ -1572,8 +1573,8 @@ void AMDGPUMachineCFGStructurizer::replaceEntryPHI( getPHIDestReg(PHI)); MIB.addReg(CombinedSourceReg); MIB.addMBB(IfMBB); - DEBUG(dbgs() << printReg(CombinedSourceReg, TRI) << ", BB#" - << IfMBB->getNumber()); + DEBUG(dbgs() << printReg(CombinedSourceReg, TRI) << ", " + << printMBBReference(*IfMBB)); unsigned NumInputs = getPHINumInputs(PHI); for (unsigned i = 0; i < NumInputs; ++i) { if (isPHIRegionIndex(PHIRegionIndices, i)) { @@ -1583,8 +1584,8 @@ void AMDGPUMachineCFGStructurizer::replaceEntryPHI( MachineBasicBlock *SourcePred = getPHIPred(PHI, i); MIB.addReg(SourceReg); MIB.addMBB(SourcePred); - DEBUG(dbgs() << printReg(SourceReg, TRI) << ", BB#" - << SourcePred->getNumber()); + DEBUG(dbgs() << printReg(SourceReg, TRI) << ", " + << printMBBReference(*SourcePred)); } DEBUG(dbgs() << ")\n"); PHI.eraseFromParent(); @@ -1749,11 +1750,11 @@ void AMDGPUMachineCFGStructurizer::insertMergePHI(MachineBasicBlock *IfBB, if (MergeBB->succ_begin() == MergeBB->succ_end()) { return; } - DEBUG(dbgs() << "Merge PHI (BB#" << MergeBB->getNumber() + DEBUG(dbgs() << "Merge PHI (" << printMBBReference(*MergeBB) << "): " << printReg(DestRegister, TRI) << " = PHI(" - << printReg(IfSourceRegister, TRI) << ", BB#" - << IfBB->getNumber() << printReg(CodeSourceRegister, TRI) - << ", BB#" << CodeBB->getNumber() << ")\n"); + << printReg(IfSourceRegister, TRI) << ", " + << printMBBReference(*IfBB) << printReg(CodeSourceRegister, TRI) + << ", " << printMBBReference(*CodeBB) << ")\n"); const DebugLoc &DL = MergeBB->findDebugLoc(MergeBB->begin()); MachineInstrBuilder MIB = BuildMI(*MergeBB, MergeBB->instr_begin(), DL, TII->get(TargetOpcode::PHI), DestRegister); @@ -1811,8 +1812,8 @@ static void removeExternalCFGEdges(MachineBasicBlock *StartMBB, for (auto SI : Succs) { std::pair Edge = SI; - DEBUG(dbgs() << "Removing edge: BB#" << Edge.first->getNumber() << " -> BB#" - << Edge.second->getNumber() << "\n"); + DEBUG(dbgs() << "Removing edge: " << printMBBReference(*Edge.first) + << " -> " << printMBBReference(*Edge.second) << "\n"); Edge.first->removeSuccessor(Edge.second); } } @@ -1850,8 +1851,8 @@ MachineBasicBlock *AMDGPUMachineCFGStructurizer::createIfBlock( if (!CodeBBEnd->isSuccessor(MergeBB)) CodeBBEnd->addSuccessor(MergeBB); - DEBUG(dbgs() << "Moved MBB#" << CodeBBStart->getNumber() << " through MBB#" - << CodeBBEnd->getNumber() << "\n"); + DEBUG(dbgs() << "Moved " << printMBBReference(*CodeBBStart) << " through " + << printMBBReference(*CodeBBEnd) << "\n"); // If we have a single predecessor we can find a reasonable debug location MachineBasicBlock *SinglePred = @@ -2064,7 +2065,7 @@ void AMDGPUMachineCFGStructurizer::rewriteLiveOutRegs(MachineBasicBlock *IfBB, // is a source block for a definition. SmallVector Sources; if (PHIInfo.findSourcesFromMBB(CodeBB, Sources)) { - DEBUG(dbgs() << "Inserting PHI Live Out from BB#" << CodeBB->getNumber() + DEBUG(dbgs() << "Inserting PHI Live Out from " << printMBBReference(*CodeBB) << "\n"); for (auto SI : Sources) { unsigned DestReg; @@ -2172,16 +2173,17 @@ void AMDGPUMachineCFGStructurizer::createEntryPHI(LinearizedRegion *CurrentRegio CurrentBackedgeReg = NewBackedgeReg; DEBUG(dbgs() << "Inserting backedge PHI: " << printReg(NewBackedgeReg, TRI) << " = PHI(" - << printReg(CurrentBackedgeReg, TRI) << ", BB#" - << getPHIPred(*PHIDefInstr, 0)->getNumber() << ", " + << printReg(CurrentBackedgeReg, TRI) << ", " + << printMBBReference(*getPHIPred(*PHIDefInstr, 0)) + << ", " << printReg(getPHISourceReg(*PHIDefInstr, 1), TRI) - << ", BB#" << (*SRI).second->getNumber()); + << ", " << printMBBReference(*(*SRI).second)); } } else { MIB.addReg(SourceReg); MIB.addMBB((*SRI).second); - DEBUG(dbgs() << printReg(SourceReg, TRI) << ", BB#" - << (*SRI).second->getNumber() << ", "); + DEBUG(dbgs() << printReg(SourceReg, TRI) << ", " + << printMBBReference(*(*SRI).second) << ", "); } } @@ -2189,8 +2191,8 @@ void AMDGPUMachineCFGStructurizer::createEntryPHI(LinearizedRegion *CurrentRegio if (CurrentBackedgeReg != 0) { MIB.addReg(CurrentBackedgeReg); MIB.addMBB(Exit); - DEBUG(dbgs() << printReg(CurrentBackedgeReg, TRI) << ", BB#" - << Exit->getNumber() << ")\n"); + DEBUG(dbgs() << printReg(CurrentBackedgeReg, TRI) << ", " + << printMBBReference(*Exit) << ")\n"); } else { DEBUG(dbgs() << ")\n"); } @@ -2443,11 +2445,12 @@ void AMDGPUMachineCFGStructurizer::splitLoopPHI(MachineInstr &PHI, << " = PHI("); MIB.addReg(PHISource); MIB.addMBB(Entry); - DEBUG(dbgs() << printReg(PHISource, TRI) << ", BB#" << Entry->getNumber()); + DEBUG(dbgs() << printReg(PHISource, TRI) << ", " + << printMBBReference(*Entry)); MIB.addReg(RegionSourceReg); MIB.addMBB(RegionSourceMBB); - DEBUG(dbgs() << " ," << printReg(RegionSourceReg, TRI) << ", BB#" - << RegionSourceMBB->getNumber() << ")\n"); + DEBUG(dbgs() << " ," << printReg(RegionSourceReg, TRI) << ", " + << printMBBReference(*RegionSourceMBB) << ")\n"); } void AMDGPUMachineCFGStructurizer::splitLoopPHIs(MachineBasicBlock *Entry, @@ -2528,9 +2531,9 @@ AMDGPUMachineCFGStructurizer::splitEntry(LinearizedRegion *LRegion) { MachineBasicBlock *EntrySucc = split(Entry->getFirstNonPHI()); MachineBasicBlock *Exit = LRegion->getExit(); - DEBUG(dbgs() << "Split BB#" << Entry->getNumber() << " to BB#" - << Entry->getNumber() << " -> BB#" << EntrySucc->getNumber() - << "\n"); + DEBUG(dbgs() << "Split " << printMBBReference(*Entry) << " to " + << printMBBReference(*Entry) << " -> " + << printMBBReference(*EntrySucc) << "\n"); LRegion->addMBB(EntrySucc); // Make the backedge go to Entry Succ diff --git a/lib/Target/AMDGPU/AMDGPUSubtarget.cpp b/lib/Target/AMDGPU/AMDGPUSubtarget.cpp index 8e5a432e068a3..22d724628376f 100644 --- a/lib/Target/AMDGPU/AMDGPUSubtarget.cpp +++ b/lib/Target/AMDGPU/AMDGPUSubtarget.cpp @@ -48,14 +48,27 @@ AMDGPUSubtarget::initializeSubtargetDependencies(const Triple &TT, // for SI has the unhelpful behavior that it unsets everything else if you // disable it. - SmallString<256> FullFS("+promote-alloca,+fp64-fp16-denormals,+dx10-clamp,+load-store-opt,"); + SmallString<256> FullFS("+promote-alloca,+dx10-clamp,+load-store-opt,"); + if (isAmdHsaOS()) // Turn on FlatForGlobal for HSA. FullFS += "+flat-address-space,+flat-for-global,+unaligned-buffer-access,+trap-handler,"; + // FIXME: I don't think think Evergreen has any useful support for + // denormals, but should be checked. Should we issue a warning somewhere + // if someone tries to enable these? + if (getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) { + FullFS += "+fp64-fp16-denormals,"; + } else { + FullFS += "-fp32-denormals,"; + } + FullFS += FS; ParseSubtargetFeatures(GPU, FullFS); + // We don't support FP64 for EG/NI atm. + assert(!hasFP64() || (getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)); + // Unless +-flat-for-global is specified, turn on FlatForGlobal for all OS-es // on VI and newer hardware to avoid assertion failures due to missing ADDR64 // variants of MUBUF instructions. @@ -63,14 +76,6 @@ AMDGPUSubtarget::initializeSubtargetDependencies(const Triple &TT, FlatForGlobal = true; } - // FIXME: I don't think think Evergreen has any useful support for - // denormals, but should be checked. Should we issue a warning somewhere - // if someone tries to enable these? - if (getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) { - FP64FP16Denormals = false; - FP32Denormals = false; - } - // Set defaults if needed. if (MaxPrivateElementSize == 0) MaxPrivateElementSize = 4; diff --git a/lib/Target/AMDGPU/AMDGPUSubtarget.h b/lib/Target/AMDGPU/AMDGPUSubtarget.h index c1518dd3d4cc0..456bbdb28e4af 100644 --- a/lib/Target/AMDGPU/AMDGPUSubtarget.h +++ b/lib/Target/AMDGPU/AMDGPUSubtarget.h @@ -140,6 +140,7 @@ class AMDGPUSubtarget : public AMDGPUGenSubtargetInfo { // Subtarget statically properties set by tablegen bool FP64; + bool FMA; bool IsGCN; bool GCN3Encoding; bool CIInsts; @@ -261,7 +262,7 @@ class AMDGPUSubtarget : public AMDGPUGenSubtargetInfo { return HasVOP3PInsts; } - bool hasHWFP64() const { + bool hasFP64() const { return FP64; } @@ -348,6 +349,10 @@ class AMDGPUSubtarget : public AMDGPUGenSubtargetInfo { return CaymanISA; } + bool hasFMA() const { + return FMA; + } + TrapHandlerAbi getTrapHandlerAbi() const { return isAmdHsaOS() ? TrapHandlerAbiHsa : TrapHandlerAbiNone; } diff --git a/lib/Target/AMDGPU/GCNIterativeScheduler.cpp b/lib/Target/AMDGPU/GCNIterativeScheduler.cpp index 942063d5f9333..56d639aca5236 100644 --- a/lib/Target/AMDGPU/GCNIterativeScheduler.cpp +++ b/lib/Target/AMDGPU/GCNIterativeScheduler.cpp @@ -63,8 +63,8 @@ static void printRegion(raw_ostream &OS, unsigned MaxInstNum = std::numeric_limits::max()) { auto BB = Begin->getParent(); - OS << BB->getParent()->getName() << ":BB#" << BB->getNumber() - << ' ' << BB->getName() << ":\n"; + OS << BB->getParent()->getName() << ":" << printMBBReference(*BB) << ' ' + << BB->getName() << ":\n"; auto I = Begin; MaxInstNum = std::max(MaxInstNum, 1u); for (; I != End && MaxInstNum; ++I, --MaxInstNum) { diff --git a/lib/Target/AMDGPU/GCNSchedStrategy.cpp b/lib/Target/AMDGPU/GCNSchedStrategy.cpp index 155b400ba022b..38803204d6e7e 100644 --- a/lib/Target/AMDGPU/GCNSchedStrategy.cpp +++ b/lib/Target/AMDGPU/GCNSchedStrategy.cpp @@ -531,9 +531,8 @@ void GCNScheduleDAGMILive::finalizeSchedule() { } DEBUG(dbgs() << "********** MI Scheduling **********\n"); - DEBUG(dbgs() << MF.getName() - << ":BB#" << MBB->getNumber() << " " << MBB->getName() - << "\n From: " << *begin() << " To: "; + DEBUG(dbgs() << MF.getName() << ":" << printMBBReference(*MBB) << " " + << MBB->getName() << "\n From: " << *begin() << " To: "; if (RegionEnd != MBB->end()) dbgs() << *RegionEnd; else dbgs() << "End"; dbgs() << " RegionInstrs: " << NumRegionInstrs << '\n'); diff --git a/lib/Target/AMDGPU/R600ISelLowering.cpp b/lib/Target/AMDGPU/R600ISelLowering.cpp index 0d62c5a32d4dc..66291d0be4e6b 100644 --- a/lib/Target/AMDGPU/R600ISelLowering.cpp +++ b/lib/Target/AMDGPU/R600ISelLowering.cpp @@ -211,6 +211,11 @@ R600TargetLowering::R600TargetLowering(const TargetMachine &TM, setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); + if (!Subtarget->hasFMA()) { + setOperationAction(ISD::FMA, MVT::f32, Expand); + setOperationAction(ISD::FMA, MVT::f64, Expand); + } + setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 }; diff --git a/lib/Target/AMDGPU/R600Instructions.td b/lib/Target/AMDGPU/R600Instructions.td index f422f441af4f7..801e4e61fca6c 100644 --- a/lib/Target/AMDGPU/R600Instructions.td +++ b/lib/Target/AMDGPU/R600Instructions.td @@ -989,7 +989,10 @@ class MULADD_IEEE_Common inst> : R600_3OP < class FMA_Common inst> : R600_3OP < inst, "FMA", [(set f32:$dst, (fma f32:$src0, f32:$src1, f32:$src2))], VecALU ->; +> +{ + let OtherPredicates = [FMA]; +} class CNDE_Common inst> : R600_3OP < inst, "CNDE", diff --git a/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp b/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp index 972e61d376ddc..1bfa837bfb235 100644 --- a/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp +++ b/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp @@ -12,16 +12,16 @@ /// common data and/or have enough undef subreg using swizzle abilities. /// /// For instance let's consider the following pseudo code : -/// vreg5 = REG_SEQ vreg1, sub0, vreg2, sub1, vreg3, sub2, undef, sub3 +/// %5 = REG_SEQ %1, sub0, %2, sub1, %3, sub2, undef, sub3 /// ... -/// vreg7 = REG_SEQ vreg1, sub0, vreg3, sub1, undef, sub2, vreg4, sub3 -/// (swizzable Inst) vreg7, SwizzleMask : sub0, sub1, sub2, sub3 +/// %7 = REG_SEQ %1, sub0, %3, sub1, undef, sub2, %4, sub3 +/// (swizzable Inst) %7, SwizzleMask : sub0, sub1, sub2, sub3 /// /// is turned into : -/// vreg5 = REG_SEQ vreg1, sub0, vreg2, sub1, vreg3, sub2, undef, sub3 +/// %5 = REG_SEQ %1, sub0, %2, sub1, %3, sub2, undef, sub3 /// ... -/// vreg7 = INSERT_SUBREG vreg4, sub3 -/// (swizzable Inst) vreg7, SwizzleMask : sub0, sub2, sub1, sub3 +/// %7 = INSERT_SUBREG %4, sub3 +/// (swizzable Inst) %7, SwizzleMask : sub0, sub2, sub1, sub3 /// /// This allow regalloc to reduce register pressure for vector registers and /// to reduce MOV count. diff --git a/lib/Target/AMDGPU/R600Processors.td b/lib/Target/AMDGPU/R600Processors.td index 8ef1fe191c313..89194dc1bdf6c 100644 --- a/lib/Target/AMDGPU/R600Processors.td +++ b/lib/Target/AMDGPU/R600Processors.td @@ -24,7 +24,7 @@ def : Processor<"rs880", R600_VLIW5_Itin, >; def : Processor<"rv670", R600_VLIW5_Itin, - [FeatureR600, FeatureWavefrontSize64, FeatureVertexCache, FeatureFP64] + [FeatureR600, FeatureWavefrontSize64, FeatureVertexCache] >; //===----------------------------------------------------------------------===// @@ -40,7 +40,7 @@ def : Processor<"rv730", R600_VLIW5_Itin, >; def : Processor<"rv770", R600_VLIW5_Itin, - [FeatureR700, FeatureWavefrontSize64, FeatureVertexCache, FeatureFP64] + [FeatureR700, FeatureWavefrontSize64, FeatureVertexCache] >; //===----------------------------------------------------------------------===// @@ -53,7 +53,7 @@ def : Processor<"cedar", R600_VLIW5_Itin, >; def : Processor<"cypress", R600_VLIW5_Itin, - [FeatureEvergreen, FeatureWavefrontSize64, FeatureVertexCache, FeatureFP64] + [FeatureEvergreen, FeatureWavefrontSize64, FeatureVertexCache, FeatureFMA] >; def : Processor<"juniper", R600_VLIW5_Itin, @@ -82,7 +82,7 @@ def : Processor<"caicos", R600_VLIW5_Itin, >; def : Processor<"cayman", R600_VLIW4_Itin, - [FeatureNorthernIslands, FeatureFP64, FeatureCaymanISA] + [FeatureNorthernIslands, FeatureCaymanISA, FeatureFMA] >; def : Processor<"turks", R600_VLIW5_Itin, diff --git a/lib/Target/AMDGPU/SIFixSGPRCopies.cpp b/lib/Target/AMDGPU/SIFixSGPRCopies.cpp index 34b1f758f7b5c..8b155c2d27800 100644 --- a/lib/Target/AMDGPU/SIFixSGPRCopies.cpp +++ b/lib/Target/AMDGPU/SIFixSGPRCopies.cpp @@ -14,46 +14,46 @@ /// Register Class is the union of and /// /// BB0: -/// %vreg0 = SCALAR_INST -/// %vreg1 = COPY %vreg0 +/// %0 = SCALAR_INST +/// %1 = COPY %0 /// ... /// BRANCH %cond BB1, BB2 /// BB1: -/// %vreg2 = VECTOR_INST -/// %vreg3 = COPY %vreg2 +/// %2 = VECTOR_INST +/// %3 = COPY %2 /// BB2: -/// %vreg4 = PHI %vreg1 , , %vreg3 , -/// %vreg5 = VECTOR_INST %vreg4 +/// %4 = PHI %1 , <%bb.0>, %3 , <%bb.1> +/// %5 = VECTOR_INST %4 /// /// /// The coalescer will begin at BB0 and eliminate its copy, then the resulting /// code will look like this: /// /// BB0: -/// %vreg0 = SCALAR_INST +/// %0 = SCALAR_INST /// ... /// BRANCH %cond BB1, BB2 /// BB1: -/// %vreg2 = VECTOR_INST -/// %vreg3 = COPY %vreg2 +/// %2 = VECTOR_INST +/// %3 = COPY %2 /// BB2: -/// %vreg4 = PHI %vreg0 , , %vreg3 , -/// %vreg5 = VECTOR_INST %vreg4 +/// %4 = PHI %0 , <%bb.0>, %3 , <%bb.1> +/// %5 = VECTOR_INST %4 /// /// Now that the result of the PHI instruction is an SGPR, the register -/// allocator is now forced to constrain the register class of %vreg3 to +/// allocator is now forced to constrain the register class of %3 to /// so we end up with final code like this: /// /// BB0: -/// %vreg0 = SCALAR_INST +/// %0 = SCALAR_INST /// ... /// BRANCH %cond BB1, BB2 /// BB1: -/// %vreg2 = VECTOR_INST -/// %vreg3 = COPY %vreg2 +/// %2 = VECTOR_INST +/// %3 = COPY %2 /// BB2: -/// %vreg4 = PHI %vreg0 , , %vreg3 , -/// %vreg5 = VECTOR_INST %vreg4 +/// %4 = PHI %0 , <%bb.0>, %3 , <%bb.1> +/// %5 = VECTOR_INST %4 /// /// Now this code contains an illegal copy from a VGPR to an SGPR. /// @@ -81,6 +81,7 @@ #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineOperand.h" #include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/CodeGen/MachinePostDominators.h" #include "llvm/CodeGen/TargetRegisterInfo.h" #include "llvm/Pass.h" #include "llvm/Support/CodeGen.h" @@ -109,7 +110,12 @@ namespace { class SIFixSGPRCopies : public MachineFunctionPass { MachineDominatorTree *MDT; - + MachinePostDominatorTree *MPDT; + DenseMap> PDF; + void computePDF(MachineFunction * MF); +#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) + void printPDF(); +#endif public: static char ID; @@ -122,6 +128,8 @@ class SIFixSGPRCopies : public MachineFunctionPass { void getAnalysisUsage(AnalysisUsage &AU) const override { AU.addRequired(); AU.addPreserved(); + AU.addRequired(); + AU.addPreserved(); AU.setPreservesCFG(); MachineFunctionPass::getAnalysisUsage(AU); } @@ -409,12 +417,6 @@ bool searchPredecessors(const MachineBasicBlock *MBB, return false; } -static bool predsHasDivergentTerminator(MachineBasicBlock *MBB, - const TargetRegisterInfo *TRI) { - return searchPredecessors(MBB, nullptr, [TRI](MachineBasicBlock *MBB) { - return hasTerminatorThatModifiesExec(*MBB, *TRI); }); -} - // Checks if there is potential path From instruction To instruction. // If CutOff is specified and it sits in between of that path we ignore // a higher portion of the path and report it is not reachable. @@ -513,8 +515,9 @@ static bool hoistAndMergeSGPRInits(unsigned Reg, if (MDT.dominates(MI1, MI2)) { if (!intereferes(MI2, MI1)) { - DEBUG(dbgs() << "Erasing from BB#" << MI2->getParent()->getNumber() - << " " << *MI2); + DEBUG(dbgs() << "Erasing from " + << printMBBReference(*MI2->getParent()) << " " + << *MI2); MI2->eraseFromParent(); Defs.erase(I2++); Changed = true; @@ -522,8 +525,9 @@ static bool hoistAndMergeSGPRInits(unsigned Reg, } } else if (MDT.dominates(MI2, MI1)) { if (!intereferes(MI1, MI2)) { - DEBUG(dbgs() << "Erasing from BB#" << MI1->getParent()->getNumber() - << " " << *MI1); + DEBUG(dbgs() << "Erasing from " + << printMBBReference(*MI1->getParent()) << " " + << *MI1); MI1->eraseFromParent(); Defs.erase(I1++); Changed = true; @@ -539,10 +543,11 @@ static bool hoistAndMergeSGPRInits(unsigned Reg, MachineBasicBlock::iterator I = MBB->getFirstNonPHI(); if (!intereferes(MI1, I) && !intereferes(MI2, I)) { - DEBUG(dbgs() << "Erasing from BB#" << MI1->getParent()->getNumber() - << " " << *MI1 << "and moving from BB#" - << MI2->getParent()->getNumber() << " to BB#" - << I->getParent()->getNumber() << " " << *MI2); + DEBUG(dbgs() << "Erasing from " + << printMBBReference(*MI1->getParent()) << " " << *MI1 + << "and moving from " + << printMBBReference(*MI2->getParent()) << " to " + << printMBBReference(*I->getParent()) << " " << *MI2); I->getParent()->splice(I, MI2->getParent(), MI2); MI1->eraseFromParent(); Defs.erase(I1++); @@ -562,12 +567,47 @@ static bool hoistAndMergeSGPRInits(unsigned Reg, return Changed; } +void SIFixSGPRCopies::computePDF(MachineFunction *MF) { + MachineFunction::iterator B = MF->begin(); + MachineFunction::iterator E = MF->end(); + for (; B != E; ++B) { + if (B->succ_size() > 1) { + for (auto S : B->successors()) { + MachineDomTreeNode *runner = MPDT->getNode(&*S); + MachineDomTreeNode *sentinel = MPDT->getNode(&*B)->getIDom(); + while (runner && runner != sentinel) { + PDF[runner->getBlock()].insert(&*B); + runner = runner->getIDom(); + } + } + } + } +} + +#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) +void SIFixSGPRCopies::printPDF() { + dbgs() << "\n######## PostDominanceFrontiers set #########\n"; + for (auto &I : PDF) { + dbgs() << "PDF[ " << I.first->getNumber() << "] : "; + for (auto &J : I.second) { + dbgs() << J->getNumber() << ' '; + } + dbgs() << '\n'; + } + dbgs() << "\n##############################################\n"; +} +#endif + bool SIFixSGPRCopies::runOnMachineFunction(MachineFunction &MF) { const SISubtarget &ST = MF.getSubtarget(); MachineRegisterInfo &MRI = MF.getRegInfo(); const SIRegisterInfo *TRI = ST.getRegisterInfo(); const SIInstrInfo *TII = ST.getInstrInfo(); MDT = &getAnalysis(); + MPDT = &getAnalysis(); + PDF.clear(); + computePDF(&MF); + DEBUG(printPDF()); SmallVector Worklist; @@ -621,15 +661,27 @@ bool SIFixSGPRCopies::runOnMachineFunction(MachineFunction &MF) { if (!TRI->isSGPRClass(MRI.getRegClass(Reg))) break; - // We don't need to fix the PHI if the common dominator of the - // two incoming blocks terminates with a uniform branch. + // We don't need to fix the PHI if all the source blocks + // have no divergent control dependecies bool HasVGPROperand = phiHasVGPROperands(MI, MRI, TRI, TII); - if (MI.getNumExplicitOperands() == 5 && !HasVGPROperand) { - MachineBasicBlock *MBB0 = MI.getOperand(2).getMBB(); - MachineBasicBlock *MBB1 = MI.getOperand(4).getMBB(); - - if (!predsHasDivergentTerminator(MBB0, TRI) && - !predsHasDivergentTerminator(MBB1, TRI)) { + if (!HasVGPROperand) { + bool Uniform = true; + MachineBasicBlock * Join = MI.getParent(); + for (auto &O : MI.explicit_operands()) { + if (O.isMBB()) { + MachineBasicBlock * Source = O.getMBB(); + SetVector &SourcePDF = PDF[Source]; + SetVector &JoinPDF = PDF[Join]; + SetVector CDList; + for (auto &I : SourcePDF) { + if (!JoinPDF.count(I) || /* back edge */MDT->dominates(Join, I)) { + if (hasTerminatorThatModifiesExec(*I, *TRI)) + Uniform = false; + } + } + } + } + if (Uniform) { DEBUG(dbgs() << "Not fixing PHI for uniform branch: " << MI << '\n'); break; } diff --git a/lib/Target/AMDGPU/SIFoldOperands.cpp b/lib/Target/AMDGPU/SIFoldOperands.cpp index 2c52e16892cc7..52157408b36a9 100644 --- a/lib/Target/AMDGPU/SIFoldOperands.cpp +++ b/lib/Target/AMDGPU/SIFoldOperands.cpp @@ -290,11 +290,11 @@ void SIFoldOperands::foldOperand( // copy since a subregister use tied to a full register def doesn't really // make sense. e.g. don't fold: // - // %vreg1 = COPY %vreg0:sub1 - // %vreg2 = V_MAC_{F16, F32} %vreg3, %vreg4, %vreg1 + // %1 = COPY %0:sub1 + // %2 = V_MAC_{F16, F32} %3, %4, %1 // // into - // %vreg2 = V_MAC_{F16, F32} %vreg3, %vreg4, %vreg0:sub1 + // %2 = V_MAC_{F16, F32} %3, %4, %0:sub1 if (UseOp.isTied() && OpToFold.getSubReg() != AMDGPU::NoSubRegister) return; } @@ -971,7 +971,7 @@ bool SIFoldOperands::runOnMachineFunction(MachineFunction &MF) { // Prevent folding operands backwards in the function. For example, // the COPY opcode must not be replaced by 1 in this example: // - // %vreg3 = COPY %vgpr0; VGPR_32:%vreg3 + // %3 = COPY %vgpr0; VGPR_32:%3 // ... // %vgpr0 = V_MOV_B32_e32 1, %exec MachineOperand &Dst = MI.getOperand(0); diff --git a/lib/Target/AMDGPU/SIISelLowering.cpp b/lib/Target/AMDGPU/SIISelLowering.cpp index dd8756bfd11a0..18dc0fb430b48 100644 --- a/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/lib/Target/AMDGPU/SIISelLowering.cpp @@ -226,6 +226,14 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM, setOperationAction(ISD::ADDCARRY, MVT::i32, Legal); setOperationAction(ISD::SUBCARRY, MVT::i32, Legal); +#if 0 + setOperationAction(ISD::ADDCARRY, MVT::i64, Legal); + setOperationAction(ISD::SUBCARRY, MVT::i64, Legal); +#endif + + //setOperationAction(ISD::ADDC, MVT::i64, Expand); + //setOperationAction(ISD::SUBC, MVT::i64, Expand); + // We only support LOAD/STORE and vector manipulation ops for vectors // with > 4 elements. for (MVT VT : {MVT::v8i32, MVT::v8f32, MVT::v16i32, MVT::v16f32, @@ -6578,9 +6586,9 @@ static unsigned SubIdx2Lane(unsigned Idx) { } /// \brief Adjust the writemask of MIMG instructions -void SITargetLowering::adjustWritemask(MachineSDNode *&Node, - SelectionDAG &DAG) const { - SDNode *Users[4] = { }; +SDNode *SITargetLowering::adjustWritemask(MachineSDNode *&Node, + SelectionDAG &DAG) const { + SDNode *Users[4] = { nullptr }; unsigned Lane = 0; unsigned DmaskIdx = (Node->getNumOperands() - Node->getNumValues() == 9) ? 2 : 3; unsigned OldDmask = Node->getConstantOperandVal(DmaskIdx); @@ -6597,7 +6605,7 @@ void SITargetLowering::adjustWritemask(MachineSDNode *&Node, // Abort if we can't understand the usage if (!I->isMachineOpcode() || I->getMachineOpcode() != TargetOpcode::EXTRACT_SUBREG) - return; + return Node; // Lane means which subreg of %vgpra_vgprb_vgprc_vgprd is used. // Note that subregs are packed, i.e. Lane==0 is the first bit set @@ -6615,7 +6623,7 @@ void SITargetLowering::adjustWritemask(MachineSDNode *&Node, // Abort if we have more than one user per component if (Users[Lane]) - return; + return Node; Users[Lane] = *I; NewDmask |= 1 << Comp; @@ -6623,25 +6631,41 @@ void SITargetLowering::adjustWritemask(MachineSDNode *&Node, // Abort if there's no change if (NewDmask == OldDmask) - return; + return Node; + + unsigned BitsSet = countPopulation(NewDmask); + + const SIInstrInfo *TII = getSubtarget()->getInstrInfo(); + int NewOpcode = TII->getMaskedMIMGOp(Node->getMachineOpcode(), BitsSet); + assert(NewOpcode != -1 && + NewOpcode != static_cast(Node->getMachineOpcode()) && + "failed to find equivalent MIMG op"); // Adjust the writemask in the node - std::vector Ops; + SmallVector Ops; Ops.insert(Ops.end(), Node->op_begin(), Node->op_begin() + DmaskIdx); Ops.push_back(DAG.getTargetConstant(NewDmask, SDLoc(Node), MVT::i32)); Ops.insert(Ops.end(), Node->op_begin() + DmaskIdx + 1, Node->op_end()); - Node = (MachineSDNode*)DAG.UpdateNodeOperands(Node, Ops); - - // If we only got one lane, replace it with a copy - // (if NewDmask has only one bit set...) - if (NewDmask && (NewDmask & (NewDmask-1)) == 0) { - SDValue RC = DAG.getTargetConstant(AMDGPU::VGPR_32RegClassID, SDLoc(), - MVT::i32); - SDNode *Copy = DAG.getMachineNode(TargetOpcode::COPY_TO_REGCLASS, - SDLoc(), Users[Lane]->getValueType(0), - SDValue(Node, 0), RC); + + MVT SVT = Node->getValueType(0).getVectorElementType().getSimpleVT(); + + auto NewVTList = + DAG.getVTList(BitsSet == 1 ? + SVT : MVT::getVectorVT(SVT, BitsSet == 3 ? 4 : BitsSet), + MVT::Other); + + MachineSDNode *NewNode = DAG.getMachineNode(NewOpcode, SDLoc(Node), + NewVTList, Ops); + // Update chain. + DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), SDValue(NewNode, 1)); + + if (BitsSet == 1) { + assert(Node->hasNUsesOfValue(1, 0)); + SDNode *Copy = DAG.getMachineNode(TargetOpcode::COPY, + SDLoc(Node), Users[Lane]->getValueType(0), + SDValue(NewNode, 0)); DAG.ReplaceAllUsesWith(Users[Lane], Copy); - return; + return nullptr; } // Update the users of the node with the new indices @@ -6651,7 +6675,7 @@ void SITargetLowering::adjustWritemask(MachineSDNode *&Node, continue; SDValue Op = DAG.getTargetConstant(Idx, SDLoc(User), MVT::i32); - DAG.UpdateNodeOperands(User, User->getOperand(0), Op); + DAG.UpdateNodeOperands(User, SDValue(NewNode, 0), Op); switch (Idx) { default: break; @@ -6660,6 +6684,9 @@ void SITargetLowering::adjustWritemask(MachineSDNode *&Node, case AMDGPU::sub2: Idx = AMDGPU::sub3; break; } } + + DAG.RemoveDeadNode(Node); + return nullptr; } static bool isFrameIndexOp(SDValue Op) { @@ -6717,14 +6744,16 @@ SDNode *SITargetLowering::legalizeTargetIndependentNode(SDNode *Node, } /// \brief Fold the instructions after selecting them. +/// Returns null if users were already updated. SDNode *SITargetLowering::PostISelFolding(MachineSDNode *Node, SelectionDAG &DAG) const { const SIInstrInfo *TII = getSubtarget()->getInstrInfo(); unsigned Opcode = Node->getMachineOpcode(); if (TII->isMIMG(Opcode) && !TII->get(Opcode).mayStore() && - !TII->isGather4(Opcode)) - adjustWritemask(Node, DAG); + !TII->isGather4(Opcode)) { + return adjustWritemask(Node, DAG); + } if (Opcode == AMDGPU::INSERT_SUBREG || Opcode == AMDGPU::REG_SEQUENCE) { @@ -6802,31 +6831,6 @@ void SITargetLowering::AdjustInstrPostInstrSelection(MachineInstr &MI, return; } - if (TII->isMIMG(MI)) { - unsigned VReg = MI.getOperand(0).getReg(); - const TargetRegisterClass *RC = MRI.getRegClass(VReg); - // TODO: Need mapping tables to handle other cases (register classes). - if (RC != &AMDGPU::VReg_128RegClass) - return; - - unsigned DmaskIdx = MI.getNumOperands() == 12 ? 3 : 4; - unsigned Writemask = MI.getOperand(DmaskIdx).getImm(); - unsigned BitsSet = 0; - for (unsigned i = 0; i < 4; ++i) - BitsSet += Writemask & (1 << i) ? 1 : 0; - switch (BitsSet) { - default: return; - case 1: RC = &AMDGPU::VGPR_32RegClass; break; - case 2: RC = &AMDGPU::VReg_64RegClass; break; - case 3: RC = &AMDGPU::VReg_96RegClass; break; - } - - unsigned NewOpcode = TII->getMaskedMIMGOp(MI.getOpcode(), BitsSet); - MI.setDesc(TII->get(NewOpcode)); - MRI.setRegClass(VReg, RC); - return; - } - // Replace unused atomics with the no return version. int NoRetAtomicOp = AMDGPU::getAtomicNoRetOp(MI.getOpcode()); if (NoRetAtomicOp != -1) { diff --git a/lib/Target/AMDGPU/SIISelLowering.h b/lib/Target/AMDGPU/SIISelLowering.h index f68f7dc28cdc2..3bf5df8c1af2d 100644 --- a/lib/Target/AMDGPU/SIISelLowering.h +++ b/lib/Target/AMDGPU/SIISelLowering.h @@ -82,7 +82,7 @@ class SITargetLowering final : public AMDGPUTargetLowering { SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; SDValue lowerTRAP(SDValue Op, SelectionDAG &DAG) const; - void adjustWritemask(MachineSDNode *&N, SelectionDAG &DAG) const; + SDNode *adjustWritemask(MachineSDNode *&N, SelectionDAG &DAG) const; SDValue performUCharToFloatCombine(SDNode *N, DAGCombinerInfo &DCI) const; diff --git a/lib/Target/AMDGPU/SIInsertWaitcnts.cpp b/lib/Target/AMDGPU/SIInsertWaitcnts.cpp index 2d41d8965b15d..6bbe5979316da 100644 --- a/lib/Target/AMDGPU/SIInsertWaitcnts.cpp +++ b/lib/Target/AMDGPU/SIInsertWaitcnts.cpp @@ -1269,7 +1269,7 @@ void SIInsertWaitcnts::mergeInputScoreBrackets(MachineBasicBlock &Block) { BlockWaitcntBracketsMap[pred].get(); bool Visited = BlockVisitedSet.find(pred) != BlockVisitedSet.end(); if (!Visited || PredScoreBrackets->getWaitAtBeginning()) { - break; + continue; } for (enum InstCounterType T = VM_CNT; T < NUM_INST_CNTS; T = (enum InstCounterType)(T + 1)) { @@ -1308,7 +1308,7 @@ void SIInsertWaitcnts::mergeInputScoreBrackets(MachineBasicBlock &Block) { BlockWaitcntBracketsMap[Pred].get(); bool Visited = BlockVisitedSet.find(Pred) != BlockVisitedSet.end(); if (!Visited || PredScoreBrackets->getWaitAtBeginning()) { - break; + continue; } int GDSSpan = PredScoreBrackets->getEventUB(GDS_GPR_LOCK) - @@ -1355,7 +1355,7 @@ void SIInsertWaitcnts::mergeInputScoreBrackets(MachineBasicBlock &Block) { // Set the register scoreboard. for (MachineBasicBlock *Pred : Block.predecessors()) { if (BlockVisitedSet.find(Pred) == BlockVisitedSet.end()) { - break; + continue; } BlockWaitcntBrackets *PredScoreBrackets = @@ -1469,7 +1469,7 @@ void SIInsertWaitcnts::mergeInputScoreBrackets(MachineBasicBlock &Block) { // the delayed nature of these operations. for (MachineBasicBlock *Pred : Block.predecessors()) { if (BlockVisitedSet.find(Pred) == BlockVisitedSet.end()) { - break; + continue; } BlockWaitcntBrackets *PredScoreBrackets = diff --git a/lib/Target/AMDGPU/SIInstrInfo.cpp b/lib/Target/AMDGPU/SIInstrInfo.cpp index 8df1c58848ed9..6ec5667cece3b 100644 --- a/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -1057,9 +1057,9 @@ unsigned SIInstrInfo::calculateLDSSpillAddress( .addReg(TIDIGYReg) .addReg(TIDReg); // (NGROUPS.Z * TIDIG.Y + (NGROUPS.X * NGROPUS.Y * TIDIG.X)) + TIDIG.Z - BuildMI(Entry, Insert, DL, get(AMDGPU::V_ADD_I32_e32), TIDReg) - .addReg(TIDReg) - .addReg(TIDIGZReg); + getAddNoCarry(Entry, Insert, DL, TIDReg) + .addReg(TIDReg) + .addReg(TIDIGZReg); } else { // Get the wave id BuildMI(Entry, Insert, DL, get(AMDGPU::V_MBCNT_LO_U32_B32_e64), @@ -1082,9 +1082,9 @@ unsigned SIInstrInfo::calculateLDSSpillAddress( // Add FrameIndex to LDS offset unsigned LDSOffset = MFI->getLDSSize() + (FrameOffset * WorkGroupSize); - BuildMI(MBB, MI, DL, get(AMDGPU::V_ADD_I32_e32), TmpReg) - .addImm(LDSOffset) - .addReg(TIDReg); + getAddNoCarry(MBB, MI, DL, TmpReg) + .addImm(LDSOffset) + .addReg(TIDReg); return TmpReg; } @@ -2687,6 +2687,28 @@ bool SIInstrInfo::verifyInstruction(const MachineInstr &MI, } } } + + const MachineOperand *DstUnused = getNamedOperand(MI, AMDGPU::OpName::dst_unused); + if (DstUnused && DstUnused->isImm() && + DstUnused->getImm() == AMDGPU::SDWA::UNUSED_PRESERVE) { + const MachineOperand &Dst = MI.getOperand(DstIdx); + if (!Dst.isReg() || !Dst.isTied()) { + ErrInfo = "Dst register should have tied register"; + return false; + } + + const MachineOperand &TiedMO = + MI.getOperand(MI.findTiedOperandIdx(DstIdx)); + if (!TiedMO.isReg() || !TiedMO.isImplicit() || !TiedMO.isUse()) { + ErrInfo = + "Dst register should be tied to implicit use of preserved register"; + return false; + } else if (TargetRegisterInfo::isPhysicalRegister(TiedMO.getReg()) && + Dst.getReg() != TiedMO.getReg()) { + ErrInfo = "Dst register should use same physical register as preserved"; + return false; + } + } } // Verify VOP* @@ -2831,7 +2853,7 @@ bool SIInstrInfo::verifyInstruction(const MachineInstr &MI, return true; } -unsigned SIInstrInfo::getVALUOp(const MachineInstr &MI) { +unsigned SIInstrInfo::getVALUOp(const MachineInstr &MI) const { switch (MI.getOpcode()) { default: return AMDGPU::INSTRUCTION_LIST_END; case AMDGPU::REG_SEQUENCE: return AMDGPU::REG_SEQUENCE; @@ -2844,10 +2866,17 @@ unsigned SIInstrInfo::getVALUOp(const MachineInstr &MI) { return MI.getOperand(1).isReg() ? AMDGPU::COPY : AMDGPU::V_MOV_B32_e32; case AMDGPU::S_ADD_I32: - case AMDGPU::S_ADD_U32: return AMDGPU::V_ADD_I32_e32; - case AMDGPU::S_ADDC_U32: return AMDGPU::V_ADDC_U32_e32; + return ST.hasAddNoCarry() ? AMDGPU::V_ADD_U32_e64 : AMDGPU::V_ADD_I32_e32; + case AMDGPU::S_ADDC_U32: + return AMDGPU::V_ADDC_U32_e32; case AMDGPU::S_SUB_I32: - case AMDGPU::S_SUB_U32: return AMDGPU::V_SUB_I32_e32; + return ST.hasAddNoCarry() ? AMDGPU::V_SUB_U32_e64 : AMDGPU::V_SUB_I32_e32; + // FIXME: These are not consistently handled, and selected when the carry is + // used. + case AMDGPU::S_ADD_U32: + return AMDGPU::V_ADD_I32_e32; + case AMDGPU::S_SUB_U32: + return AMDGPU::V_SUB_I32_e32; case AMDGPU::S_SUBB_U32: return AMDGPU::V_SUBB_U32_e32; case AMDGPU::S_MUL_I32: return AMDGPU::V_MUL_LO_I32; case AMDGPU::S_AND_B32: return AMDGPU::V_AND_B32_e64; @@ -2894,10 +2923,6 @@ unsigned SIInstrInfo::getVALUOp(const MachineInstr &MI) { } } -bool SIInstrInfo::isSALUOpSupportedOnVALU(const MachineInstr &MI) const { - return getVALUOp(MI) != AMDGPU::INSTRUCTION_LIST_END; -} - const TargetRegisterClass *SIInstrInfo::getOpRegClass(const MachineInstr &MI, unsigned OpNo) const { const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo(); @@ -3612,6 +3637,14 @@ void SIInstrInfo::moveToVALU(MachineInstr &TopInst) const { splitScalar64BitAddSub(Worklist, Inst); Inst.eraseFromParent(); continue; + case AMDGPU::S_ADD_I32: + case AMDGPU::S_SUB_I32: + // FIXME: The u32 versions currently selected use the carry. + if (moveScalarAddSub(Worklist, Inst)) + continue; + + // Default handling + break; case AMDGPU::S_AND_B64: splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::V_AND_B32_e64); Inst.eraseFromParent(); @@ -3720,6 +3753,14 @@ void SIInstrInfo::moveToVALU(MachineInstr &TopInst) const { auto Add = MRI.getUniqueVRegDef(VAddr->getReg()); unsigned Offset = 0; + // FIXME: This isn't safe because the addressing mode doesn't work + // correctly if vaddr is negative. + // + // FIXME: Handle v_add_u32 and VOP3 form. Also don't rely on immediate + // being in src0. + // + // FIXME: Should probably be done somewhere else, maybe SIFoldOperands. + // // See if we can extract an immediate offset by recognizing one of these: // V_ADD_I32_e32 dst, imm, src1 // V_ADD_I32_e32 dst, (S_MOV_B32 imm), src1 @@ -3728,7 +3769,7 @@ void SIInstrInfo::moveToVALU(MachineInstr &TopInst) const { const MachineOperand *Src = getNamedOperand(*Add, AMDGPU::OpName::src0); - if (Src && Src->isReg()) { + if (Src->isReg()) { auto Mov = MRI.getUniqueVRegDef(Src->getReg()); if (Mov && Mov->getOpcode() == AMDGPU::S_MOV_B32) Src = &Mov->getOperand(1); @@ -3858,6 +3899,41 @@ void SIInstrInfo::moveToVALU(MachineInstr &TopInst) const { } } +// Add/sub require special handling to deal with carry outs. +bool SIInstrInfo::moveScalarAddSub(SetVectorType &Worklist, + MachineInstr &Inst) const { + if (ST.hasAddNoCarry()) { + // Assume there is no user of scc since we don't select this in that case. + // Since scc isn't used, it doesn't really matter if the i32 or u32 variant + // is used. + + MachineBasicBlock &MBB = *Inst.getParent(); + MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); + + unsigned OldDstReg = Inst.getOperand(0).getReg(); + unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); + + unsigned Opc = Inst.getOpcode(); + assert(Opc == AMDGPU::S_ADD_I32 || Opc == AMDGPU::S_SUB_I32); + + unsigned NewOpc = Opc == AMDGPU::S_ADD_I32 ? + AMDGPU::V_ADD_U32_e64 : AMDGPU::V_SUB_U32_e64; + + assert(Inst.getOperand(3).getReg() == AMDGPU::SCC); + Inst.RemoveOperand(3); + + Inst.setDesc(get(NewOpc)); + Inst.addImplicitDefUseOperands(*MBB.getParent()); + MRI.replaceRegWith(OldDstReg, ResultReg); + legalizeOperands(Inst); + + addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist); + return true; + } + + return false; +} + void SIInstrInfo::lowerScalarAbs(SetVectorType &Worklist, MachineInstr &Inst) const { MachineBasicBlock &MBB = *Inst.getParent(); @@ -3870,7 +3946,10 @@ void SIInstrInfo::lowerScalarAbs(SetVectorType &Worklist, unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); - BuildMI(MBB, MII, DL, get(AMDGPU::V_SUB_I32_e32), TmpReg) + unsigned SubOp = ST.hasAddNoCarry() ? + AMDGPU::V_SUB_U32_e32 : AMDGPU::V_SUB_I32_e32; + + BuildMI(MBB, MII, DL, get(SubOp), TmpReg) .addImm(0) .addReg(Src.getReg()); @@ -4707,9 +4786,12 @@ SIInstrInfo::getAddNoCarry(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg) const { - MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); + if (ST.hasAddNoCarry()) + return BuildMI(MBB, I, DL, get(AMDGPU::V_ADD_U32_e64), DestReg); + MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); unsigned UnusedCarry = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass); + MRI.setRegAllocationHint(UnusedCarry, 0, AMDGPU::VCC); return BuildMI(MBB, I, DL, get(AMDGPU::V_ADD_I32_e64), DestReg) .addReg(UnusedCarry, RegState::Define | RegState::Dead); diff --git a/lib/Target/AMDGPU/SIInstrInfo.h b/lib/Target/AMDGPU/SIInstrInfo.h index d7d3918f6bf78..24ee843e6adec 100644 --- a/lib/Target/AMDGPU/SIInstrInfo.h +++ b/lib/Target/AMDGPU/SIInstrInfo.h @@ -76,6 +76,9 @@ class SIInstrInfo final : public AMDGPUInstrInfo { private: void swapOperands(MachineInstr &Inst) const; + bool moveScalarAddSub(SetVectorType &Worklist, + MachineInstr &Inst) const; + void lowerScalarAbs(SetVectorType &Worklist, MachineInstr &Inst) const; @@ -691,9 +694,7 @@ class SIInstrInfo final : public AMDGPUInstrInfo { bool verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const override; - static unsigned getVALUOp(const MachineInstr &MI); - - bool isSALUOpSupportedOnVALU(const MachineInstr &MI) const; + unsigned getVALUOp(const MachineInstr &MI) const; /// \brief Return the correct register class for \p OpNo. For target-specific /// instructions, this will return the register class that has been defined diff --git a/lib/Target/AMDGPU/SIInstrInfo.td b/lib/Target/AMDGPU/SIInstrInfo.td index 1ce27c3789ed2..fc2d35d873aa3 100644 --- a/lib/Target/AMDGPU/SIInstrInfo.td +++ b/lib/Target/AMDGPU/SIInstrInfo.td @@ -1823,7 +1823,31 @@ def getBasicFromSDWAOp : InstrMapping { let ValueCols = [["Default"]]; } -def getMaskedMIMGOp : InstrMapping { +def getMaskedMIMGOp1 : InstrMapping { + let FilterClass = "MIMG_Mask"; + let RowFields = ["Op"]; + let ColFields = ["Channels"]; + let KeyCol = ["1"]; + let ValueCols = [["2"], ["3"], ["4"] ]; +} + +def getMaskedMIMGOp2 : InstrMapping { + let FilterClass = "MIMG_Mask"; + let RowFields = ["Op"]; + let ColFields = ["Channels"]; + let KeyCol = ["2"]; + let ValueCols = [["1"], ["3"], ["4"] ]; +} + +def getMaskedMIMGOp3 : InstrMapping { + let FilterClass = "MIMG_Mask"; + let RowFields = ["Op"]; + let ColFields = ["Channels"]; + let KeyCol = ["3"]; + let ValueCols = [["1"], ["2"], ["4"] ]; +} + +def getMaskedMIMGOp4 : InstrMapping { let FilterClass = "MIMG_Mask"; let RowFields = ["Op"]; let ColFields = ["Channels"]; diff --git a/lib/Target/AMDGPU/SIInstructions.td b/lib/Target/AMDGPU/SIInstructions.td index 76612d0c95578..9740a18b72488 100644 --- a/lib/Target/AMDGPU/SIInstructions.td +++ b/lib/Target/AMDGPU/SIInstructions.td @@ -159,10 +159,14 @@ def S_SUB_U64_PSEUDO : SPseudoInstSI < [(set SReg_64:$vdst, (sub i64:$src0, i64:$src1))] >; -def S_ADDC_U64_PSEUDO : SPseudoInstSI <(outs SReg_64:$vdst, SReg_64:$sdst), - (ins SSrc_b64:$src0, SSrc_b64:$src1)>; -def S_SUBC_U64_PSEUDO : SPseudoInstSI <(outs SReg_64:$vdst, SReg_64:$sdst), - (ins SSrc_b64:$src0, SSrc_b64:$src1)>; +def S_ADD_U64_CO_PSEUDO : SPseudoInstSI < + (outs SReg_64:$vdst, VOPDstS64:$sdst), (ins SSrc_b64:$src0, SSrc_b64:$src1) +>; + +def S_SUB_U64_CO_PSEUDO : SPseudoInstSI < + (outs SReg_64:$vdst, VOPDstS64:$sdst), (ins SSrc_b64:$src0, SSrc_b64:$src1) +>; + } // End usesCustomInserter = 1, Defs = [SCC] let usesCustomInserter = 1, SALU = 1 in { diff --git a/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp b/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp index 840c7fbb8d70d..d9fdb81b8f4d7 100644 --- a/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp +++ b/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp @@ -498,9 +498,12 @@ MachineBasicBlock::iterator SILoadStoreOptimizer::mergeRead2Pair( if (CI.BaseOff) { BaseReg = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass); BaseRegFlags = RegState::Kill; - BuildMI(*MBB, CI.Paired, DL, TII->get(AMDGPU::V_ADD_I32_e32), BaseReg) - .addImm(CI.BaseOff) - .addReg(AddrReg->getReg()); + + unsigned AddOpc = STM->hasAddNoCarry() ? + AMDGPU::V_ADD_U32_e32 : AMDGPU::V_ADD_I32_e32; + BuildMI(*MBB, CI.Paired, DL, TII->get(AddOpc), BaseReg) + .addImm(CI.BaseOff) + .addReg(AddrReg->getReg()); } MachineInstrBuilder Read2 = @@ -581,9 +584,12 @@ MachineBasicBlock::iterator SILoadStoreOptimizer::mergeWrite2Pair( if (CI.BaseOff) { BaseReg = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass); BaseRegFlags = RegState::Kill; - BuildMI(*MBB, CI.Paired, DL, TII->get(AMDGPU::V_ADD_I32_e32), BaseReg) - .addImm(CI.BaseOff) - .addReg(Addr->getReg()); + + unsigned AddOpc = STM->hasAddNoCarry() ? + AMDGPU::V_ADD_U32_e32 : AMDGPU::V_ADD_I32_e32; + BuildMI(*MBB, CI.Paired, DL, TII->get(AddOpc), BaseReg) + .addImm(CI.BaseOff) + .addReg(Addr->getReg()); } MachineInstrBuilder Write2 = diff --git a/lib/Target/AMDGPU/SIMachineScheduler.cpp b/lib/Target/AMDGPU/SIMachineScheduler.cpp index c13148bf0a2b6..3fb39998ff711 100644 --- a/lib/Target/AMDGPU/SIMachineScheduler.cpp +++ b/lib/Target/AMDGPU/SIMachineScheduler.cpp @@ -2050,9 +2050,9 @@ void SIScheduleDAGMI::schedule() placeDebugValues(); DEBUG({ - unsigned BBNum = begin()->getParent()->getNumber(); - dbgs() << "*** Final schedule for BB#" << BBNum << " ***\n"; - dumpSchedule(); - dbgs() << '\n'; - }); + dbgs() << "*** Final schedule for " + << printMBBReference(*begin()->getParent()) << " ***\n"; + dumpSchedule(); + dbgs() << '\n'; + }); } diff --git a/lib/Target/AMDGPU/SIPeepholeSDWA.cpp b/lib/Target/AMDGPU/SIPeepholeSDWA.cpp index 5738077f98904..59bc44bdfa052 100644 --- a/lib/Target/AMDGPU/SIPeepholeSDWA.cpp +++ b/lib/Target/AMDGPU/SIPeepholeSDWA.cpp @@ -10,12 +10,12 @@ /// \file This pass tries to apply several peephole SDWA patterns. /// /// E.g. original: -/// V_LSHRREV_B32_e32 %vreg0, 16, %vreg1 -/// V_ADD_I32_e32 %vreg2, %vreg0, %vreg3 -/// V_LSHLREV_B32_e32 %vreg4, 16, %vreg2 +/// V_LSHRREV_B32_e32 %0, 16, %1 +/// V_ADD_I32_e32 %2, %0, %3 +/// V_LSHLREV_B32_e32 %4, 16, %2 /// /// Replace: -/// V_ADD_I32_sdwa %vreg4, %vreg1, %vreg3 +/// V_ADD_I32_sdwa %4, %1, %3 /// dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD /// //===----------------------------------------------------------------------===// @@ -61,6 +61,7 @@ STATISTIC(NumSDWAInstructionsPeepholed, namespace { class SDWAOperand; +class SDWADstOperand; class SIPeepholeSDWA : public MachineFunctionPass { public: @@ -86,6 +87,7 @@ class SIPeepholeSDWA : public MachineFunctionPass { bool runOnMachineFunction(MachineFunction &MF) override; void matchSDWAOperands(MachineFunction &MF); + std::unique_ptr matchSDWAOperand(MachineInstr &MI); bool isConvertibleToSDWA(const MachineInstr &MI, const SISubtarget &ST) const; bool convertToSDWA(MachineInstr &MI, const SDWAOperandsVector &SDWAOperands); void legalizeScalarOperands(MachineInstr &MI, const SISubtarget &ST) const; @@ -122,6 +124,11 @@ class SDWAOperand { MachineRegisterInfo *getMRI() const { return &getParentInst()->getParent()->getParent()->getRegInfo(); } + +#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) + virtual void print(raw_ostream& OS) const = 0; + void dump() const { print(dbgs()); } +#endif }; using namespace AMDGPU::SDWA; @@ -137,8 +144,8 @@ class SDWASrcOperand : public SDWAOperand { SDWASrcOperand(MachineOperand *TargetOp, MachineOperand *ReplacedOp, SdwaSel SrcSel_ = DWORD, bool Abs_ = false, bool Neg_ = false, bool Sext_ = false) - : SDWAOperand(TargetOp, ReplacedOp), SrcSel(SrcSel_), Abs(Abs_), - Neg(Neg_), Sext(Sext_) {} + : SDWAOperand(TargetOp, ReplacedOp), + SrcSel(SrcSel_), Abs(Abs_), Neg(Neg_), Sext(Sext_) {} MachineInstr *potentialToConvert(const SIInstrInfo *TII) override; bool convertToSDWA(MachineInstr &MI, const SIInstrInfo *TII) override; @@ -150,6 +157,10 @@ class SDWASrcOperand : public SDWAOperand { uint64_t getSrcMods(const SIInstrInfo *TII, const MachineOperand *SrcOp) const; + +#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) + void print(raw_ostream& OS) const override; +#endif }; class SDWADstOperand : public SDWAOperand { @@ -158,15 +169,39 @@ class SDWADstOperand : public SDWAOperand { DstUnused DstUn; public: + SDWADstOperand(MachineOperand *TargetOp, MachineOperand *ReplacedOp, SdwaSel DstSel_ = DWORD, DstUnused DstUn_ = UNUSED_PAD) - : SDWAOperand(TargetOp, ReplacedOp), DstSel(DstSel_), DstUn(DstUn_) {} + : SDWAOperand(TargetOp, ReplacedOp), DstSel(DstSel_), DstUn(DstUn_) {} MachineInstr *potentialToConvert(const SIInstrInfo *TII) override; bool convertToSDWA(MachineInstr &MI, const SIInstrInfo *TII) override; SdwaSel getDstSel() const { return DstSel; } DstUnused getDstUnused() const { return DstUn; } + +#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) + void print(raw_ostream& OS) const override; +#endif +}; + +class SDWADstPreserveOperand : public SDWADstOperand { +private: + MachineOperand *Preserve; + +public: + SDWADstPreserveOperand(MachineOperand *TargetOp, MachineOperand *ReplacedOp, + MachineOperand *PreserveOp, SdwaSel DstSel_ = DWORD) + : SDWADstOperand(TargetOp, ReplacedOp, DstSel_, UNUSED_PRESERVE), + Preserve(PreserveOp) {} + + bool convertToSDWA(MachineInstr &MI, const SIInstrInfo *TII) override; + + MachineOperand *getPreservedOperand() const { return Preserve; } + +#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) + void print(raw_ostream& OS) const override; +#endif }; } // end anonymous namespace @@ -181,7 +216,8 @@ FunctionPass *llvm::createSIPeepholeSDWAPass() { return new SIPeepholeSDWA(); } -#ifndef NDEBUG + +#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) static raw_ostream& operator<<(raw_ostream &OS, const SdwaSel &Sel) { switch(Sel) { case BYTE_0: OS << "BYTE_0"; break; @@ -204,20 +240,33 @@ static raw_ostream& operator<<(raw_ostream &OS, const DstUnused &Un) { return OS; } -static raw_ostream& operator<<(raw_ostream &OS, const SDWASrcOperand &Src) { - OS << "SDWA src: " << *Src.getTargetOperand() - << " src_sel:" << Src.getSrcSel() - << " abs:" << Src.getAbs() << " neg:" << Src.getNeg() - << " sext:" << Src.getSext() << '\n'; +static raw_ostream& operator<<(raw_ostream &OS, const SDWAOperand &Operand) { + Operand.print(OS); return OS; } -static raw_ostream& operator<<(raw_ostream &OS, const SDWADstOperand &Dst) { - OS << "SDWA dst: " << *Dst.getTargetOperand() - << " dst_sel:" << Dst.getDstSel() - << " dst_unused:" << Dst.getDstUnused() << '\n'; - return OS; +LLVM_DUMP_METHOD +void SDWASrcOperand::print(raw_ostream& OS) const { + OS << "SDWA src: " << *getTargetOperand() + << " src_sel:" << getSrcSel() + << " abs:" << getAbs() << " neg:" << getNeg() + << " sext:" << getSext() << '\n'; +} + +LLVM_DUMP_METHOD +void SDWADstOperand::print(raw_ostream& OS) const { + OS << "SDWA dst: " << *getTargetOperand() + << " dst_sel:" << getDstSel() + << " dst_unused:" << getDstUnused() << '\n'; } + +LLVM_DUMP_METHOD +void SDWADstPreserveOperand::print(raw_ostream& OS) const { + OS << "SDWA preserve dst: " << *getTargetOperand() + << " dst_sel:" << getDstSel() + << " preserve:" << *getPreservedOperand() << '\n'; +} + #endif static void copyRegOperand(MachineOperand &To, const MachineOperand &From) { @@ -239,23 +288,43 @@ static bool isSameReg(const MachineOperand &LHS, const MachineOperand &RHS) { LHS.getSubReg() == RHS.getSubReg(); } -static bool isSubregOf(const MachineOperand &SubReg, - const MachineOperand &SuperReg, - const TargetRegisterInfo *TRI) { +static MachineOperand *findSingleRegUse(const MachineOperand *Reg, + const MachineRegisterInfo *MRI) { + if (!Reg->isReg() || !Reg->isDef()) + return nullptr; - if (!SuperReg.isReg() || !SubReg.isReg()) - return false; + MachineOperand *ResMO = nullptr; + for (MachineOperand &UseMO : MRI->use_nodbg_operands(Reg->getReg())) { + // If there exist use of subreg of Reg then return nullptr + if (!isSameReg(UseMO, *Reg)) + return nullptr; - if (isSameReg(SuperReg, SubReg)) - return true; + // Check that there is only one instruction that uses Reg + if (!ResMO) { + ResMO = &UseMO; + } else if (ResMO->getParent() != UseMO.getParent()) { + return nullptr; + } + } - if (SuperReg.getReg() != SubReg.getReg()) - return false; + return ResMO; +} + +static MachineOperand *findSingleRegDef(const MachineOperand *Reg, + const MachineRegisterInfo *MRI) { + if (!Reg->isReg()) + return nullptr; - LaneBitmask SuperMask = TRI->getSubRegIndexLaneMask(SuperReg.getSubReg()); - LaneBitmask SubMask = TRI->getSubRegIndexLaneMask(SubReg.getSubReg()); - SuperMask |= ~SubMask; - return SuperMask.all(); + MachineInstr *DefInstr = MRI->getUniqueVRegDef(Reg->getReg()); + if (!DefInstr) + return nullptr; + + for (auto &DefMO : DefInstr->defs()) { + if (DefMO.isReg() && DefMO.getReg() == Reg->getReg()) + return &DefMO; + } + + llvm_unreachable("invalid reg"); } uint64_t SDWASrcOperand::getSrcMods(const SIInstrInfo *TII, @@ -286,30 +355,11 @@ uint64_t SDWASrcOperand::getSrcMods(const SIInstrInfo *TII, MachineInstr *SDWASrcOperand::potentialToConvert(const SIInstrInfo *TII) { // For SDWA src operand potential instruction is one that use register // defined by parent instruction - MachineRegisterInfo *MRI = getMRI(); - MachineOperand *Replaced = getReplacedOperand(); - assert(Replaced->isReg()); + MachineOperand *PotentialMO = findSingleRegUse(getReplacedOperand(), getMRI()); + if (!PotentialMO) + return nullptr; - MachineInstr *PotentialMI = nullptr; - for (MachineOperand &PotentialMO : MRI->use_operands(Replaced->getReg())) { - // If this is use of another subreg of dst reg then do nothing - if (!isSubregOf(*Replaced, PotentialMO, MRI->getTargetRegisterInfo())) - continue; - - // If there exist use of superreg of dst then we should not combine this - // opernad - if (!isSameReg(PotentialMO, *Replaced)) - return nullptr; - - // Check that PotentialMI is only instruction that uses dst reg - if (PotentialMI == nullptr) { - PotentialMI = PotentialMO.getParent(); - } else if (PotentialMI != PotentialMO.getParent()) { - return nullptr; - } - } - - return PotentialMI; + return PotentialMO->getParent(); } bool SDWASrcOperand::convertToSDWA(MachineInstr &MI, const SIInstrInfo *TII) { @@ -331,7 +381,7 @@ bool SDWASrcOperand::convertToSDWA(MachineInstr &MI, const SIInstrInfo *TII) { if ((MI.getOpcode() == AMDGPU::V_MAC_F16_sdwa || MI.getOpcode() == AMDGPU::V_MAC_F32_sdwa) && - !isSameReg(*Src, *getReplacedOperand())) { + !isSameReg(*Src, *getReplacedOperand())) { // In case of v_mac_f16/32_sdwa this pass can try to apply src operand to // src2. This is not allowed. return false; @@ -351,29 +401,18 @@ MachineInstr *SDWADstOperand::potentialToConvert(const SIInstrInfo *TII) { // that this operand uses MachineRegisterInfo *MRI = getMRI(); MachineInstr *ParentMI = getParentInst(); - MachineOperand *Replaced = getReplacedOperand(); - assert(Replaced->isReg()); - for (MachineOperand &PotentialMO : MRI->def_operands(Replaced->getReg())) { - if (!isSubregOf(*Replaced, PotentialMO, MRI->getTargetRegisterInfo())) - continue; + MachineOperand *PotentialMO = findSingleRegDef(getReplacedOperand(), MRI); + if (!PotentialMO) + return nullptr; - if (!isSameReg(*Replaced, PotentialMO)) + // Check that ParentMI is the only instruction that uses replaced register + for (MachineInstr &UseInst : MRI->use_nodbg_instructions(PotentialMO->getReg())) { + if (&UseInst != ParentMI) return nullptr; - - // Check that ParentMI is the only instruction that uses replaced register - for (MachineOperand &UseMO : MRI->use_operands(PotentialMO.getReg())) { - if (isSubregOf(UseMO, PotentialMO, MRI->getTargetRegisterInfo()) && - UseMO.getParent() != ParentMI) { - return nullptr; - } - } - - // Due to SSA this should be onle def of replaced register, so return it - return PotentialMO.getParent(); } - return nullptr; + return PotentialMO->getParent(); } bool SDWADstOperand::convertToSDWA(MachineInstr &MI, const SIInstrInfo *TII) { @@ -404,13 +443,43 @@ bool SDWADstOperand::convertToSDWA(MachineInstr &MI, const SIInstrInfo *TII) { return true; } +bool SDWADstPreserveOperand::convertToSDWA(MachineInstr &MI, + const SIInstrInfo *TII) { + // MI should be moved right before v_or_b32. + // For this we should clear all kill flags on uses of MI src-operands or else + // we can encounter problem with use of killed operand. + for (MachineOperand &MO : MI.uses()) { + if (!MO.isReg()) + continue; + getMRI()->clearKillFlags(MO.getReg()); + } + + // Move MI before v_or_b32 + auto MBB = MI.getParent(); + MBB->remove(&MI); + MBB->insert(getParentInst(), &MI); + + // Add Implicit use of preserved register + MachineInstrBuilder MIB(*MBB->getParent(), MI); + MIB.addReg(getPreservedOperand()->getReg(), + RegState::ImplicitKill, + getPreservedOperand()->getSubReg()); + + // Tie dst to implicit use + MI.tieOperands(AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vdst), + MI.getNumOperands() - 1); + + // Convert MI as any other SDWADstOperand and remove v_or_b32 + return SDWADstOperand::convertToSDWA(MI, TII); +} + Optional SIPeepholeSDWA::foldToImm(const MachineOperand &Op) const { if (Op.isImm()) { return Op.getImm(); } // If this is not immediate then it can be copy of immediate value, e.g.: - // %vreg1 = S_MOV_B32 255; + // %1 = S_MOV_B32 255; if (Op.isReg()) { for (const MachineOperand &Def : MRI->def_operands(Op.getReg())) { if (!isSameReg(Op, Def)) @@ -431,195 +500,316 @@ Optional SIPeepholeSDWA::foldToImm(const MachineOperand &Op) const { return None; } -void SIPeepholeSDWA::matchSDWAOperands(MachineFunction &MF) { - for (MachineBasicBlock &MBB : MF) { - for (MachineInstr &MI : MBB) { - unsigned Opcode = MI.getOpcode(); - switch (Opcode) { - case AMDGPU::V_LSHRREV_B32_e32: - case AMDGPU::V_ASHRREV_I32_e32: - case AMDGPU::V_LSHLREV_B32_e32: - case AMDGPU::V_LSHRREV_B32_e64: - case AMDGPU::V_ASHRREV_I32_e64: - case AMDGPU::V_LSHLREV_B32_e64: { - // from: v_lshrrev_b32_e32 v1, 16/24, v0 - // to SDWA src:v0 src_sel:WORD_1/BYTE_3 - - // from: v_ashrrev_i32_e32 v1, 16/24, v0 - // to SDWA src:v0 src_sel:WORD_1/BYTE_3 sext:1 - - // from: v_lshlrev_b32_e32 v1, 16/24, v0 - // to SDWA dst:v1 dst_sel:WORD_1/BYTE_3 dst_unused:UNUSED_PAD - MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); - auto Imm = foldToImm(*Src0); - if (!Imm) - break; - - if (*Imm != 16 && *Imm != 24) - break; - - MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); - MachineOperand *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst); - if (TRI->isPhysicalRegister(Src1->getReg()) || - TRI->isPhysicalRegister(Dst->getReg())) - break; - - if (Opcode == AMDGPU::V_LSHLREV_B32_e32 || - Opcode == AMDGPU::V_LSHLREV_B32_e64) { - auto SDWADst = make_unique( - Dst, Src1, *Imm == 16 ? WORD_1 : BYTE_3, UNUSED_PAD); - DEBUG(dbgs() << "Match: " << MI << "To: " << *SDWADst << '\n'); - SDWAOperands[&MI] = std::move(SDWADst); - ++NumSDWAPatternsFound; - } else { - auto SDWASrc = make_unique( - Src1, Dst, *Imm == 16 ? WORD_1 : BYTE_3, false, false, - Opcode != AMDGPU::V_LSHRREV_B32_e32 && - Opcode != AMDGPU::V_LSHRREV_B32_e64); - DEBUG(dbgs() << "Match: " << MI << "To: " << *SDWASrc << '\n'); - SDWAOperands[&MI] = std::move(SDWASrc); - ++NumSDWAPatternsFound; - } - break; - } +std::unique_ptr +SIPeepholeSDWA::matchSDWAOperand(MachineInstr &MI) { + unsigned Opcode = MI.getOpcode(); + switch (Opcode) { + case AMDGPU::V_LSHRREV_B32_e32: + case AMDGPU::V_ASHRREV_I32_e32: + case AMDGPU::V_LSHLREV_B32_e32: + case AMDGPU::V_LSHRREV_B32_e64: + case AMDGPU::V_ASHRREV_I32_e64: + case AMDGPU::V_LSHLREV_B32_e64: { + // from: v_lshrrev_b32_e32 v1, 16/24, v0 + // to SDWA src:v0 src_sel:WORD_1/BYTE_3 + + // from: v_ashrrev_i32_e32 v1, 16/24, v0 + // to SDWA src:v0 src_sel:WORD_1/BYTE_3 sext:1 + + // from: v_lshlrev_b32_e32 v1, 16/24, v0 + // to SDWA dst:v1 dst_sel:WORD_1/BYTE_3 dst_unused:UNUSED_PAD + MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); + auto Imm = foldToImm(*Src0); + if (!Imm) + break; + + if (*Imm != 16 && *Imm != 24) + break; + + MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); + MachineOperand *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst); + if (TRI->isPhysicalRegister(Src1->getReg()) || + TRI->isPhysicalRegister(Dst->getReg())) + break; + + if (Opcode == AMDGPU::V_LSHLREV_B32_e32 || + Opcode == AMDGPU::V_LSHLREV_B32_e64) { + return make_unique( + Dst, Src1, *Imm == 16 ? WORD_1 : BYTE_3, UNUSED_PAD); + } else { + return make_unique( + Src1, Dst, *Imm == 16 ? WORD_1 : BYTE_3, false, false, + Opcode != AMDGPU::V_LSHRREV_B32_e32 && + Opcode != AMDGPU::V_LSHRREV_B32_e64); + } + break; + } - case AMDGPU::V_LSHRREV_B16_e32: - case AMDGPU::V_ASHRREV_I16_e32: - case AMDGPU::V_LSHLREV_B16_e32: - case AMDGPU::V_LSHRREV_B16_e64: - case AMDGPU::V_ASHRREV_I16_e64: - case AMDGPU::V_LSHLREV_B16_e64: { - // from: v_lshrrev_b16_e32 v1, 8, v0 - // to SDWA src:v0 src_sel:BYTE_1 - - // from: v_ashrrev_i16_e32 v1, 8, v0 - // to SDWA src:v0 src_sel:BYTE_1 sext:1 - - // from: v_lshlrev_b16_e32 v1, 8, v0 - // to SDWA dst:v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD - MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); - auto Imm = foldToImm(*Src0); - if (!Imm || *Imm != 8) - break; - - MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); - MachineOperand *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst); - - if (TRI->isPhysicalRegister(Src1->getReg()) || - TRI->isPhysicalRegister(Dst->getReg())) - break; - - if (Opcode == AMDGPU::V_LSHLREV_B16_e32 || - Opcode == AMDGPU::V_LSHLREV_B16_e64) { - auto SDWADst = - make_unique(Dst, Src1, BYTE_1, UNUSED_PAD); - DEBUG(dbgs() << "Match: " << MI << "To: " << *SDWADst << '\n'); - SDWAOperands[&MI] = std::move(SDWADst); - ++NumSDWAPatternsFound; - } else { - auto SDWASrc = make_unique( - Src1, Dst, BYTE_1, false, false, - Opcode != AMDGPU::V_LSHRREV_B16_e32 && - Opcode != AMDGPU::V_LSHRREV_B16_e64); - DEBUG(dbgs() << "Match: " << MI << "To: " << *SDWASrc << '\n'); - SDWAOperands[&MI] = std::move(SDWASrc); - ++NumSDWAPatternsFound; - } - break; - } + case AMDGPU::V_LSHRREV_B16_e32: + case AMDGPU::V_ASHRREV_I16_e32: + case AMDGPU::V_LSHLREV_B16_e32: + case AMDGPU::V_LSHRREV_B16_e64: + case AMDGPU::V_ASHRREV_I16_e64: + case AMDGPU::V_LSHLREV_B16_e64: { + // from: v_lshrrev_b16_e32 v1, 8, v0 + // to SDWA src:v0 src_sel:BYTE_1 + + // from: v_ashrrev_i16_e32 v1, 8, v0 + // to SDWA src:v0 src_sel:BYTE_1 sext:1 + + // from: v_lshlrev_b16_e32 v1, 8, v0 + // to SDWA dst:v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD + MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); + auto Imm = foldToImm(*Src0); + if (!Imm || *Imm != 8) + break; + + MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); + MachineOperand *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst); + + if (TRI->isPhysicalRegister(Src1->getReg()) || + TRI->isPhysicalRegister(Dst->getReg())) + break; + + if (Opcode == AMDGPU::V_LSHLREV_B16_e32 || + Opcode == AMDGPU::V_LSHLREV_B16_e64) { + return make_unique(Dst, Src1, BYTE_1, UNUSED_PAD); + } else { + return make_unique( + Src1, Dst, BYTE_1, false, false, + Opcode != AMDGPU::V_LSHRREV_B16_e32 && + Opcode != AMDGPU::V_LSHRREV_B16_e64); + } + break; + } - case AMDGPU::V_BFE_I32: - case AMDGPU::V_BFE_U32: { - // e.g.: - // from: v_bfe_u32 v1, v0, 8, 8 - // to SDWA src:v0 src_sel:BYTE_1 - - // offset | width | src_sel - // ------------------------ - // 0 | 8 | BYTE_0 - // 0 | 16 | WORD_0 - // 0 | 32 | DWORD ? - // 8 | 8 | BYTE_1 - // 16 | 8 | BYTE_2 - // 16 | 16 | WORD_1 - // 24 | 8 | BYTE_3 - - MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); - auto Offset = foldToImm(*Src1); - if (!Offset) - break; - - MachineOperand *Src2 = TII->getNamedOperand(MI, AMDGPU::OpName::src2); - auto Width = foldToImm(*Src2); - if (!Width) - break; - - SdwaSel SrcSel = DWORD; - - if (*Offset == 0 && *Width == 8) - SrcSel = BYTE_0; - else if (*Offset == 0 && *Width == 16) - SrcSel = WORD_0; - else if (*Offset == 0 && *Width == 32) - SrcSel = DWORD; - else if (*Offset == 8 && *Width == 8) - SrcSel = BYTE_1; - else if (*Offset == 16 && *Width == 8) - SrcSel = BYTE_2; - else if (*Offset == 16 && *Width == 16) - SrcSel = WORD_1; - else if (*Offset == 24 && *Width == 8) - SrcSel = BYTE_3; - else - break; - - MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); - MachineOperand *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst); - - if (TRI->isPhysicalRegister(Src0->getReg()) || - TRI->isPhysicalRegister(Dst->getReg())) - break; - - auto SDWASrc = make_unique( - Src0, Dst, SrcSel, false, false, - Opcode != AMDGPU::V_BFE_U32); - DEBUG(dbgs() << "Match: " << MI << "To: " << *SDWASrc << '\n'); - SDWAOperands[&MI] = std::move(SDWASrc); - ++NumSDWAPatternsFound; + case AMDGPU::V_BFE_I32: + case AMDGPU::V_BFE_U32: { + // e.g.: + // from: v_bfe_u32 v1, v0, 8, 8 + // to SDWA src:v0 src_sel:BYTE_1 + + // offset | width | src_sel + // ------------------------ + // 0 | 8 | BYTE_0 + // 0 | 16 | WORD_0 + // 0 | 32 | DWORD ? + // 8 | 8 | BYTE_1 + // 16 | 8 | BYTE_2 + // 16 | 16 | WORD_1 + // 24 | 8 | BYTE_3 + + MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); + auto Offset = foldToImm(*Src1); + if (!Offset) + break; + + MachineOperand *Src2 = TII->getNamedOperand(MI, AMDGPU::OpName::src2); + auto Width = foldToImm(*Src2); + if (!Width) + break; + + SdwaSel SrcSel = DWORD; + + if (*Offset == 0 && *Width == 8) + SrcSel = BYTE_0; + else if (*Offset == 0 && *Width == 16) + SrcSel = WORD_0; + else if (*Offset == 0 && *Width == 32) + SrcSel = DWORD; + else if (*Offset == 8 && *Width == 8) + SrcSel = BYTE_1; + else if (*Offset == 16 && *Width == 8) + SrcSel = BYTE_2; + else if (*Offset == 16 && *Width == 16) + SrcSel = WORD_1; + else if (*Offset == 24 && *Width == 8) + SrcSel = BYTE_3; + else + break; + + MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); + MachineOperand *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst); + + if (TRI->isPhysicalRegister(Src0->getReg()) || + TRI->isPhysicalRegister(Dst->getReg())) + break; + + return make_unique( + Src0, Dst, SrcSel, false, false, Opcode != AMDGPU::V_BFE_U32); + } + + case AMDGPU::V_AND_B32_e32: + case AMDGPU::V_AND_B32_e64: { + // e.g.: + // from: v_and_b32_e32 v1, 0x0000ffff/0x000000ff, v0 + // to SDWA src:v0 src_sel:WORD_0/BYTE_0 + + MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); + MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); + auto ValSrc = Src1; + auto Imm = foldToImm(*Src0); + + if (!Imm) { + Imm = foldToImm(*Src1); + ValSrc = Src0; + } + + if (!Imm || (*Imm != 0x0000ffff && *Imm != 0x000000ff)) + break; + + MachineOperand *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst); + + if (TRI->isPhysicalRegister(Src1->getReg()) || + TRI->isPhysicalRegister(Dst->getReg())) + break; + + return make_unique( + ValSrc, Dst, *Imm == 0x0000ffff ? WORD_0 : BYTE_0); + } + + case AMDGPU::V_OR_B32_e32: + case AMDGPU::V_OR_B32_e64: { + // Patterns for dst_unused:UNUSED_PRESERVE. + // e.g., from: + // v_add_f16_sdwa v0, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD + // src1_sel:WORD_1 src2_sel:WORD1 + // v_add_f16_e32 v3, v1, v2 + // v_or_b32_e32 v4, v0, v3 + // to SDWA preserve dst:v4 dst_sel:WORD_1 dst_unused:UNUSED_PRESERVE preserve:v3 + + // Check if one of operands of v_or_b32 is SDWA instruction + using CheckRetType = Optional>; + auto CheckOROperandsForSDWA = + [&](const MachineOperand *Op1, const MachineOperand *Op2) -> CheckRetType { + if (!Op1 || !Op1->isReg() || !Op2 || !Op2->isReg()) + return CheckRetType(None); + + MachineOperand *Op1Def = findSingleRegDef(Op1, MRI); + if (!Op1Def) + return CheckRetType(None); + + MachineInstr *Op1Inst = Op1Def->getParent(); + if (!TII->isSDWA(*Op1Inst)) + return CheckRetType(None); + + MachineOperand *Op2Def = findSingleRegDef(Op2, MRI); + if (!Op2Def) + return CheckRetType(None); + + return CheckRetType(std::make_pair(Op1Def, Op2Def)); + }; + + MachineOperand *OrSDWA = TII->getNamedOperand(MI, AMDGPU::OpName::src0); + MachineOperand *OrOther = TII->getNamedOperand(MI, AMDGPU::OpName::src1); + assert(OrSDWA && OrOther); + auto Res = CheckOROperandsForSDWA(OrSDWA, OrOther); + if (!Res) { + OrSDWA = TII->getNamedOperand(MI, AMDGPU::OpName::src1); + OrOther = TII->getNamedOperand(MI, AMDGPU::OpName::src0); + assert(OrSDWA && OrOther); + Res = CheckOROperandsForSDWA(OrSDWA, OrOther); + if (!Res) break; - } - case AMDGPU::V_AND_B32_e32: - case AMDGPU::V_AND_B32_e64: { - // e.g.: - // from: v_and_b32_e32 v1, 0x0000ffff/0x000000ff, v0 - // to SDWA src:v0 src_sel:WORD_0/BYTE_0 - - MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); - MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); - auto ValSrc = Src1; - auto Imm = foldToImm(*Src0); - - if (!Imm) { - Imm = foldToImm(*Src1); - ValSrc = Src0; - } - - if (!Imm || (*Imm != 0x0000ffff && *Imm != 0x000000ff)) - break; - - MachineOperand *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst); - - if (TRI->isPhysicalRegister(Src1->getReg()) || - TRI->isPhysicalRegister(Dst->getReg())) - break; - - auto SDWASrc = make_unique( - ValSrc, Dst, *Imm == 0x0000ffff ? WORD_0 : BYTE_0); - DEBUG(dbgs() << "Match: " << MI << "To: " << *SDWASrc << '\n'); - SDWAOperands[&MI] = std::move(SDWASrc); + } + + MachineOperand *OrSDWADef = Res->first; + MachineOperand *OrOtherDef = Res->second; + assert(OrSDWADef && OrOtherDef); + + MachineInstr *SDWAInst = OrSDWADef->getParent(); + MachineInstr *OtherInst = OrOtherDef->getParent(); + + // Check that OtherInstr is actually bitwise compatible with SDWAInst = their + // destination patterns don't overlap. Compatible instruction can be either + // regular instruction with compatible bitness or SDWA instruction with + // correct dst_sel + // SDWAInst | OtherInst bitness / OtherInst dst_sel + // ----------------------------------------------------- + // DWORD | no / no + // WORD_0 | no / BYTE_2/3, WORD_1 + // WORD_1 | 8/16-bit instructions / BYTE_0/1, WORD_0 + // BYTE_0 | no / BYTE_1/2/3, WORD_1 + // BYTE_1 | 8-bit / BYTE_0/2/3, WORD_1 + // BYTE_2 | 8/16-bit / BYTE_0/1/3. WORD_0 + // BYTE_3 | 8/16/24-bit / BYTE_0/1/2, WORD_0 + // E.g. if SDWAInst is v_add_f16_sdwa dst_sel:WORD_1 then v_add_f16 is OK + // but v_add_f32 is not. + + // TODO: add support for non-SDWA instructions as OtherInst. + // For now this only works with SDWA instructions. For regular instructions + // there is no way to determine if instruction write only 8/16/24-bit out of + // full register size and all registers are at min 32-bit wide. + if (!TII->isSDWA(*OtherInst)) + break; + + SdwaSel DstSel = static_cast( + TII->getNamedImmOperand(*SDWAInst, AMDGPU::OpName::dst_sel));; + SdwaSel OtherDstSel = static_cast( + TII->getNamedImmOperand(*OtherInst, AMDGPU::OpName::dst_sel)); + + bool DstSelAgree = false; + switch (DstSel) { + case WORD_0: DstSelAgree = ((OtherDstSel == BYTE_2) || + (OtherDstSel == BYTE_3) || + (OtherDstSel == WORD_1)); + break; + case WORD_1: DstSelAgree = ((OtherDstSel == BYTE_0) || + (OtherDstSel == BYTE_1) || + (OtherDstSel == WORD_0)); + break; + case BYTE_0: DstSelAgree = ((OtherDstSel == BYTE_1) || + (OtherDstSel == BYTE_2) || + (OtherDstSel == BYTE_3) || + (OtherDstSel == WORD_1)); + break; + case BYTE_1: DstSelAgree = ((OtherDstSel == BYTE_0) || + (OtherDstSel == BYTE_2) || + (OtherDstSel == BYTE_3) || + (OtherDstSel == WORD_1)); + break; + case BYTE_2: DstSelAgree = ((OtherDstSel == BYTE_0) || + (OtherDstSel == BYTE_1) || + (OtherDstSel == BYTE_3) || + (OtherDstSel == WORD_0)); + break; + case BYTE_3: DstSelAgree = ((OtherDstSel == BYTE_0) || + (OtherDstSel == BYTE_1) || + (OtherDstSel == BYTE_2) || + (OtherDstSel == WORD_0)); + break; + default: DstSelAgree = false; + } + + if (!DstSelAgree) + break; + + // Also OtherInst dst_unused should be UNUSED_PAD + DstUnused OtherDstUnused = static_cast( + TII->getNamedImmOperand(*OtherInst, AMDGPU::OpName::dst_unused)); + if (OtherDstUnused != DstUnused::UNUSED_PAD) + break; + + // Create DstPreserveOperand + MachineOperand *OrDst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst); + assert(OrDst && OrDst->isReg()); + + return make_unique( + OrDst, OrSDWADef, OrOtherDef, DstSel); + + } + } + + return std::unique_ptr(nullptr); +} + +void SIPeepholeSDWA::matchSDWAOperands(MachineFunction &MF) { + for (MachineBasicBlock &MBB : MF) { + for (MachineInstr &MI : MBB) { + if (auto Operand = matchSDWAOperand(MI)) { + DEBUG(dbgs() << "Match: " << MI << "To: " << *Operand << '\n'); + SDWAOperands[&MI] = std::move(Operand); ++NumSDWAPatternsFound; - break; - } } } } @@ -627,12 +817,16 @@ void SIPeepholeSDWA::matchSDWAOperands(MachineFunction &MF) { bool SIPeepholeSDWA::isConvertibleToSDWA(const MachineInstr &MI, const SISubtarget &ST) const { + // Check if this is already an SDWA instruction + unsigned Opc = MI.getOpcode(); + if (TII->isSDWA(Opc)) + return true; + // Check if this instruction has opcode that supports SDWA - int Opc = MI.getOpcode(); if (AMDGPU::getSDWAOp(Opc) == -1) Opc = AMDGPU::getVOPe32(Opc); - if (Opc == -1 || AMDGPU::getSDWAOp(Opc) == -1) + if (AMDGPU::getSDWAOp(Opc) == -1) return false; if (!ST.hasSDWAOmod() && TII->hasModifiersSet(MI, AMDGPU::OpName::omod)) @@ -665,9 +859,15 @@ bool SIPeepholeSDWA::isConvertibleToSDWA(const MachineInstr &MI, bool SIPeepholeSDWA::convertToSDWA(MachineInstr &MI, const SDWAOperandsVector &SDWAOperands) { // Convert to sdwa - int SDWAOpcode = AMDGPU::getSDWAOp(MI.getOpcode()); - if (SDWAOpcode == -1) - SDWAOpcode = AMDGPU::getSDWAOp(AMDGPU::getVOPe32(MI.getOpcode())); + int SDWAOpcode; + unsigned Opcode = MI.getOpcode(); + if (TII->isSDWA(Opcode)) { + SDWAOpcode = Opcode; + } else { + SDWAOpcode = AMDGPU::getSDWAOp(Opcode); + if (SDWAOpcode == -1) + SDWAOpcode = AMDGPU::getSDWAOp(AMDGPU::getVOPe32(Opcode)); + } assert(SDWAOpcode != -1); const MCInstrDesc &SDWADesc = TII->get(SDWAOpcode); @@ -743,25 +943,44 @@ bool SIPeepholeSDWA::convertToSDWA(MachineInstr &MI, } } - // Initialize dst_sel if present + // Copy dst_sel if present, initialize otherwise if needed if (AMDGPU::getNamedOperandIdx(SDWAOpcode, AMDGPU::OpName::dst_sel) != -1) { - SDWAInst.addImm(AMDGPU::SDWA::SdwaSel::DWORD); + MachineOperand *DstSel = TII->getNamedOperand(MI, AMDGPU::OpName::dst_sel); + if (DstSel) { + SDWAInst.add(*DstSel); + } else { + SDWAInst.addImm(AMDGPU::SDWA::SdwaSel::DWORD); + } } - // Initialize dst_unused if present + // Copy dst_unused if present, initialize otherwise if needed if (AMDGPU::getNamedOperandIdx(SDWAOpcode, AMDGPU::OpName::dst_unused) != -1) { - SDWAInst.addImm(AMDGPU::SDWA::DstUnused::UNUSED_PAD); + MachineOperand *DstUnused = TII->getNamedOperand(MI, AMDGPU::OpName::dst_unused); + if (DstUnused) { + SDWAInst.add(*DstUnused); + } else { + SDWAInst.addImm(AMDGPU::SDWA::DstUnused::UNUSED_PAD); + } } - // Initialize src0_sel + // Copy src0_sel if present, initialize otherwise assert(AMDGPU::getNamedOperandIdx(SDWAOpcode, AMDGPU::OpName::src0_sel) != -1); - SDWAInst.addImm(AMDGPU::SDWA::SdwaSel::DWORD); - + MachineOperand *Src0Sel = TII->getNamedOperand(MI, AMDGPU::OpName::src0_sel); + if (Src0Sel) { + SDWAInst.add(*Src0Sel); + } else { + SDWAInst.addImm(AMDGPU::SDWA::SdwaSel::DWORD); + } - // Initialize src1_sel if present + // Copy src1_sel if present, initialize otherwise if needed if (Src1) { assert(AMDGPU::getNamedOperandIdx(SDWAOpcode, AMDGPU::OpName::src1_sel) != -1); - SDWAInst.addImm(AMDGPU::SDWA::SdwaSel::DWORD); + MachineOperand *Src1Sel = TII->getNamedOperand(MI, AMDGPU::OpName::src1_sel); + if (Src1Sel) { + SDWAInst.add(*Src1Sel); + } else { + SDWAInst.addImm(AMDGPU::SDWA::SdwaSel::DWORD); + } } // Apply all sdwa operand pattenrs @@ -800,7 +1019,7 @@ bool SIPeepholeSDWA::convertToSDWA(MachineInstr &MI, void SIPeepholeSDWA::legalizeScalarOperands(MachineInstr &MI, const SISubtarget &ST) const { const MCInstrDesc &Desc = TII->get(MI.getOpcode()); unsigned ConstantBusCount = 0; - for (MachineOperand &Op: MI.explicit_uses()) { + for (MachineOperand &Op : MI.explicit_uses()) { if (!Op.isImm() && !(Op.isReg() && !TRI->isVGPR(*MRI, Op.getReg()))) continue; @@ -838,27 +1057,35 @@ bool SIPeepholeSDWA::runOnMachineFunction(MachineFunction &MF) { TII = ST.getInstrInfo(); // Find all SDWA operands in MF. - matchSDWAOperands(MF); + bool Changed = false; + bool Ret = false; + do { + matchSDWAOperands(MF); + + for (const auto &OperandPair : SDWAOperands) { + const auto &Operand = OperandPair.second; + MachineInstr *PotentialMI = Operand->potentialToConvert(TII); + if (PotentialMI && isConvertibleToSDWA(*PotentialMI, ST)) { + PotentialMatches[PotentialMI].push_back(Operand.get()); + } + } - for (const auto &OperandPair : SDWAOperands) { - const auto &Operand = OperandPair.second; - MachineInstr *PotentialMI = Operand->potentialToConvert(TII); - if (PotentialMI && isConvertibleToSDWA(*PotentialMI, ST)) { - PotentialMatches[PotentialMI].push_back(Operand.get()); + for (auto &PotentialPair : PotentialMatches) { + MachineInstr &PotentialMI = *PotentialPair.first; + convertToSDWA(PotentialMI, PotentialPair.second); } - } - for (auto &PotentialPair : PotentialMatches) { - MachineInstr &PotentialMI = *PotentialPair.first; - convertToSDWA(PotentialMI, PotentialPair.second); - } + PotentialMatches.clear(); + SDWAOperands.clear(); + + Changed = !ConvertedInstructions.empty(); - PotentialMatches.clear(); - SDWAOperands.clear(); + if (Changed) + Ret = true; - bool Ret = !ConvertedInstructions.empty(); - while (!ConvertedInstructions.empty()) - legalizeScalarOperands(*ConvertedInstructions.pop_back_val(), ST); + while (!ConvertedInstructions.empty()) + legalizeScalarOperands(*ConvertedInstructions.pop_back_val(), ST); + } while (Changed); return Ret; } diff --git a/lib/Target/AMDGPU/SIRegisterInfo.cpp b/lib/Target/AMDGPU/SIRegisterInfo.cpp index 152b24599e9d3..6dc67d2144a05 100644 --- a/lib/Target/AMDGPU/SIRegisterInfo.cpp +++ b/lib/Target/AMDGPU/SIRegisterInfo.cpp @@ -1071,8 +1071,6 @@ void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI, .addImm(Log2_32(ST.getWavefrontSize())) .addReg(DiffReg); } else { - unsigned CarryOut - = MRI.createVirtualRegister(&AMDGPU::SReg_64_XEXECRegClass); unsigned ScaledReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); @@ -1082,8 +1080,7 @@ void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI, // TODO: Fold if use instruction is another add of a constant. if (AMDGPU::isInlinableLiteral32(Offset, ST.hasInv2PiInlineImm())) { - BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_ADD_I32_e64), ResultReg) - .addReg(CarryOut, RegState::Define | RegState::Dead) + TII->getAddNoCarry(*MBB, MI, DL, ResultReg) .addImm(Offset) .addReg(ScaledReg, RegState::Kill); } else { @@ -1092,13 +1089,10 @@ void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI, BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_MOV_B32), ConstOffsetReg) .addImm(Offset); - BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_ADD_I32_e64), ResultReg) - .addReg(CarryOut, RegState::Define | RegState::Dead) + TII->getAddNoCarry(*MBB, MI, DL, ResultReg) .addReg(ConstOffsetReg, RegState::Kill) .addReg(ScaledReg, RegState::Kill); } - - MRI.setRegAllocationHint(CarryOut, 0, AMDGPU::VCC); } // Don't introduce an extra copy if we're just materializing in a mov. @@ -1347,13 +1341,13 @@ bool SIRegisterInfo::shouldRewriteCopySrc( // class. // // e.g. if we have something like - // vreg0 = ... - // vreg1 = ... - // vreg2 = REG_SEQUENCE vreg0, sub0, vreg1, sub1, vreg2, sub2 - // vreg3 = COPY vreg2, sub0 + // %0 = ... + // %1 = ... + // %2 = REG_SEQUENCE %0, sub0, %1, sub1, %2, sub2 + // %3 = COPY %2, sub0 // // We want to look through the COPY to find: - // => vreg3 = COPY vreg0 + // => %3 = COPY %0 // Plain copy. return getCommonSubClass(DefRC, SrcRC) != nullptr; diff --git a/lib/Target/AMDGPU/SIWholeQuadMode.cpp b/lib/Target/AMDGPU/SIWholeQuadMode.cpp index 1864973310332..c46fd28710613 100644 --- a/lib/Target/AMDGPU/SIWholeQuadMode.cpp +++ b/lib/Target/AMDGPU/SIWholeQuadMode.cpp @@ -224,7 +224,8 @@ FunctionPass *llvm::createSIWholeQuadModePass() { #ifndef NDEBUG LLVM_DUMP_METHOD void SIWholeQuadMode::printInfo() { for (const auto &BII : Blocks) { - dbgs() << "\nBB#" << BII.first->getNumber() << ":\n" + dbgs() << "\n" + << printMBBReference(*BII.first) << ":\n" << " InNeeds = " << PrintState(BII.second.InNeeds) << ", Needs = " << PrintState(BII.second.Needs) << ", OutNeeds = " << PrintState(BII.second.OutNeeds) << "\n\n"; @@ -680,7 +681,7 @@ void SIWholeQuadMode::processBlock(MachineBasicBlock &MBB, unsigned LiveMaskReg, if (!isEntry && BI.Needs == StateWQM && BI.OutNeeds != StateExact) return; - DEBUG(dbgs() << "\nProcessing block BB#" << MBB.getNumber() << ":\n"); + DEBUG(dbgs() << "\nProcessing block " << printMBBReference(MBB) << ":\n"); unsigned SavedWQMReg = 0; unsigned SavedNonWWMReg = 0; diff --git a/lib/Target/ARC/ARCInstrFormats.td b/lib/Target/ARC/ARCInstrFormats.td index 94240e90a601d..bddef6b9500a0 100644 --- a/lib/Target/ARC/ARCInstrFormats.td +++ b/lib/Target/ARC/ARCInstrFormats.td @@ -17,18 +17,23 @@ class Encoding64 { } // Address operands -def immU6 : Operand, PatLeaf<(imm), [{ - return isUInt<6>(N->getSExtValue()); }]> { + +class immU : Operand, PatLeaf<(imm), + "\n return isUInt<"#BSz#">(N->getSExtValue());"> { } -def immS12 : Operand, PatLeaf<(imm), [{ - return isInt<12>(N->getSExtValue()); }]> { - let DecoderMethod = "DecodeS12Operand"; +def immU6 : immU<6>; + +class immS : Operand, PatLeaf<(imm), + "\n return isInt<"#BSz#">(N->getSExtValue());"> { + let DecoderMethod = "DecodeSignedOperand<"#BSz#">"; } -def immS9 : Operand, PatLeaf<(imm), [{ - return isInt<9>(N->getSExtValue()); }]> { - let DecoderMethod = "DecodeS9Operand"; +// e.g. s3 field may encode the signed integers values -1 .. 6 +// using binary codes 111, 000, 001, 010, 011, 100, 101, and 110, respectively +class immC : Operand, PatLeaf<(imm), + "\n return isInt<"#BSz#">(N->getSExtValue());"> { + let DecoderMethod = "DecodeFromCyclicRange<"#BSz#">"; } def MEMii : Operand { @@ -36,7 +41,7 @@ def MEMii : Operand { } def MEMrs9 : Operand { - let MIOperandInfo = (ops GPR32:$B, immS9:$S9); + let MIOperandInfo = (ops GPR32:$B, immS<9>:$S9); let PrintMethod = "printMemOperandRI"; let DecoderMethod = "DecodeMEMrs9"; } @@ -47,6 +52,10 @@ def MEMrlimm : Operand { let DecoderMethod = "DecodeMEMrlimm"; } +def GPR32Reduced : Operand { + let DecoderMethod = "DecodeGBR32ShortRegister"; +} + class InstARC pattern> : Instruction, Encoding64 { @@ -153,7 +162,6 @@ class F32_BR1_BL_COND pat> : let Inst{17} = 0; } - // BRcc targets have limited 9-bit range. These are for compare and branch // in single instruction. Their targets are 2-byte aligned. They also use // a different (3-bit) set of condition codes. @@ -464,6 +472,342 @@ class F32_ST_LIMM zz, dag outs, dag ins, let DecoderMethod = "DecodeStLImmInstruction"; } +// Compact Move/Load. +// |10|9|8|7|6|5|4|3|2|1|0| +// | |h | |i|H | +class F16_COMPACT i, dag outs, dag ins, + string asmstr> : + InstARC<2, outs, ins, asmstr, []> { + + bits<5> h; + + let Inst{15-11} = 0b01000; + let Inst{7-5} = h{2-0}; + let Inst{2} = i; + let Inst{1-0} = h{4-3}; +} + +// Compact Load/Add/Sub. +class F16_LD_ADD_SUB : + InstARC<2, outs, ins, asmstr, []> { + + bits<3> b; + let Inst{15-11} = 0b01001; + let Inst{10-8} = b; +} + +class F16_LD_SUB : + F16_LD_ADD_SUB<(outs GPR32:$a), (ins GPR32:$b, GPR32:$c), + asmstr> { + + bits<3> a; + bits<3> c; + + let Inst{7-5} = c; + let Inst{4} = i; + let Inst{3} = 0; + let Inst{2-0} = a; +} + +class F16_ADD : + F16_LD_ADD_SUB<(outs GPR32:$r), (ins GPR32:$b, immU<6>:$u6), + "add_s\t$r, $b, $u6"> { + + bit r; + bits<6> u6; + + let Inst{7} = r; + let Inst{6-4} = u6{5-3}; + let Inst{3} = 1; + let Inst{2-0} = u6{2-0}; +} + +// Compact Load/Store. +class F16_LD_ST_1 : + InstARC<2, outs, ins, asmstr, []> { + + let Inst{15-11} = 0b01010; +} + +class F16_LD_ST_s11 : + F16_LD_ST_1<(outs), (ins immS<11>:$s11), asmstr> { + + bits<11> s11; + + let Inst{10-5} = s11{10-5}; + let Inst{4} = i; + let Inst{3} = 0; + let Inst{2-0} = s11{4-2}; + let s11{1-0} = 0b00; +} + +class F16_LDI_u7 : + F16_LD_ST_1<(outs GPR32:$b), (ins immU<7>:$u7), + "ldi_s\t$b, [$u7]"> { + + bits<3> b; + bits<7> u7; + + let Inst{10-8} = b; + let Inst{7-4} = u7{6-3}; + let Inst{3} = 1; + let Inst{2-0} = u7{2-0}; +} + +// Indexed Jump or Execute. +class F16_JLI_EI : + InstARC<2, (outs), (ins immU<10>:$u10), + !strconcat(asmstr, "\t$u10"), []> { + + bits<10> u10; + + let Inst{15-11} = 0b01011; + let Inst{10} = i; + let Inst{9-0} = u10; +} + +// Load/Add Register-Register. +class F16_LD_ADD_RR i, string asmstr> : + InstARC<2, (outs GPR32:$a), (ins GPR32:$b, GPR32:$c), + asmstr, []> { + + bits<3> a; + bits<3> b; + bits<3> c; + + let Inst{15-11} = 0b01100; + let Inst{10-8} = b; + let Inst{7-5} = c; + let Inst{4-3} = i; + let Inst{2-0} = a; +} + +// Load/Add GP-Relative. +class F16_GP_LD_ADD i, dag ins, string asmstr> : + InstARC<2, (outs), ins, asmstr, []> { + + let Inst{15-11} = 0b11001; + let Inst{10-9} = i; +} + +// Add/Sub/Shift Register-Immediate. +// |10|9|8|7|6|5|4|3|2|1|0| +// |b |c |i |u | +class F16_ADD_IMM i, string asmstr> : + InstARC<2, (outs GPR32:$c), (ins GPR32:$b, immU<3>:$u3), + !strconcat(asmstr, "\t$c, $b, $u3"), []> { + + bits<3> b; + bits<3> c; + bits<3> u3; + + let Inst{15-11} = 0b01101; + let Inst{10-8} = b; + let Inst{7-5} = c; + let Inst{4-3} = i; + let Inst{2-0} = u3; +} + +// Dual Register Operations. +// |10|9|8|7|6|5|4|3|2|1|0| +// |b/s |h |i |H | +class F16_OP_HREG i, dag outs, dag ins, string asmstr> : + InstARC<2, outs, ins, asmstr, []> { + + bits<3> b_s3; + bits<5> h; + + let Inst{15-11} = 0b01110; + let Inst{10-8} = b_s3; + let Inst{7-5} = h{2-0}; + let Inst{4-2} = i; + let Inst{1-0} = h{4-3}; +} + +class F16_OP_HREG30 i, dag outs, dag ins, string asmstr> : + F16_OP_HREG { + + bits<5> LImmReg = 0b11110; + let Inst{7-5} = LImmReg{2-0}; + let Inst{1-0} = LImmReg{4-3}; +} + +class F16_OP_HREG_LIMM i, dag outs, dag ins, string asmstr> : + F16_OP_HREG30 { + + bits<32> LImm; + let Inst{47-16} = LImm; + let Size = 6; +} + +// General compact DOP format. +class F16_GEN_DOP_BASE i, dag outs, dag ins, string asmstr> : + InstARC<2, outs, ins, asmstr, []> { + + bits<3> b; + bits<3> c; + let Inst{15-11} = 0b01111; + let Inst{10-8} = b; + let Inst{7-5} = c; + let Inst{4-0} = i; +} + +class F16_GEN_DOP i, string asmstr> : + F16_GEN_DOP_BASE; + +class F16_GEN_DOP_NODST i, string asmstr> : + F16_GEN_DOP_BASE; + +class F16_GEN_DOP_SINGLESRC i, string asmstr> : + F16_GEN_DOP_BASE; + +class F16_GEN_SOP_BASE i, dag outs, dag ins, string asmstr> : + F16_GEN_DOP_BASE<0b00000, outs, ins, asmstr> { + + let c = i; +} + +class F16_GEN_SOP i, string asmstr> : + F16_GEN_SOP_BASE; + +class F16_GEN_ZOP i, string asmstr> : + F16_GEN_SOP_BASE<0b111, (outs), (ins), asmstr> { + + let b = i; +} + +// Compact Load/Store with Offset Format. +class F16_LD_ST_OFF opc, dag outs, dag ins, string asmstr> : + InstARC<2, outs, ins, !strconcat(asmstr, "\t$c, [$b, $off]"), []> { + + bits<3> b; + bits<3> c; + let Inst{15-11} = opc; + let Inst{10-8} = b; + let Inst{7-5} = c; +} + +class F16_LD_ST_WORD_OFF opc, dag outs, dag ins, string asmstr> : + F16_LD_ST_OFF { + + bits<7> off; + let Inst{4-0} = off{6-2}; + let off{1-0} = 0b00; +} + +class F16_LD_ST_HALF_OFF opc, dag outs, dag ins, string asmstr> : + F16_LD_ST_OFF { + + bits<6> off; + let Inst{4-0} = off{5-1}; + let off{0} = 0b0; +} + +class F16_LD_ST_BYTE_OFF opc, dag outs, dag ins, string asmstr> : + F16_LD_ST_OFF { + + bits<5> off; + let Inst{4-0} = off; +} + +// Shift/Subtract/Bit Immediate. +// |10|9|8|7|6|5|4|3|2|1|0| +// |b |i |u | +class F16_SH_SUB_BIT i, string asmstr> : + InstARC<2, (outs), (ins GPR32:$b, immU<5>:$u5), asmstr, []> { + + bits<3> b; + bits<5> u5; + + let Inst{15-11} = 0b10111; + let Inst{10-8} = b; + let Inst{7-5} = i; + let Inst{4-0} = u5; +} + +class F16_SH_SUB_BIT_DST i, string asmstr> : + F16_SH_SUB_BIT; + +// 16-bit stack-based operations. +// |10|9|8|7|6|5|4|3|2|1|0| +// |b |i |u | +class F16_SP_OPS i, + dag outs, dag ins, string asmstr> : + InstARC<2, outs, ins, asmstr, []> { + + bits<3> fieldB; + bits<5> fieldU; + + let Inst{15-11} = 0b11000; + let Inst{10-8} = fieldB; + let Inst{7-5} = i; + let Inst{4-0} = fieldU; +} + +class F16_SP_OPS_u7_aligned i, + dag outs, dag ins, string asmstr> : + F16_SP_OPS { + + bits<3> b3; + bits<7> u7; + + let fieldB = b3; + let fieldU = u7{6-2}; + let u7{1-0} = 0b00; +} + +class F16_SP_OPS_bconst b, string asmop> : + F16_SP_OPS_u7_aligned<0b101, + (outs), (ins immU<7>:$u7), + !strconcat(asmop, "\t%sp, %sp, $u7")> { + + let fieldB = b; +} + +class F16_SP_OPS_uconst i, + dag outs, dag ins, string asmop> : + F16_SP_OPS_u7_aligned { + + let fieldU = 0b00001; +} + +class F16_SP_OPS_buconst i, string asmop> : + F16_SP_OPS_u7_aligned { + + let fieldB = 0x000; + let fieldU = 0b10001; +} + +class F16_SP_LD i, string asmop> : F16_SP_OPS_u7_aligned:$u7), + !strconcat(asmop, "\t$b3, [%sp, $u7]")>; + +class F16_SP_ST i, string asmop> : F16_SP_OPS_u7_aligned:$u7), + !strconcat(asmop, "\t$b3, [%sp, $u7]")>; + +// Compact MOV/ADD/CMP Immediate Format. +class F16_OP_IMM opc, dag outs, dag ins, string asmstr> : + InstARC<2, outs, ins, asmstr, []> { + + bits<3> b; + let Inst{15-11} = opc; + let Inst{10-8} = b; +} + +class F16_OP_U7 : + F16_OP_IMM<0b11100, (outs GPR32:$b), (ins immU<7>:$u7), asmstr> { + + bits<7> u7; + let Inst{7} = i; + let Inst{6-0} = u7; +} + // Special types for different instruction operands. def cmovpred : Operand, PredicateOp, ComplexPattern { @@ -481,28 +825,67 @@ def brccond : Operand { let PrintMethod = "printBRCCPredicateOperand"; } -// Branch targets of different offset sizes. -def btarget : Operand { +// Branch/call targets of different offset sizes. +class BCTarget : Operand { let OperandType = "OPERAND_PCREL"; } -def btargetS9 : Operand { - let OperandType = "OPERAND_PCREL"; - let DecoderMethod = "DecodeBranchTargetS9"; +def btarget : BCTarget; + +class BCTargetSigned : BCTarget { + let DecoderMethod = "DecodeBranchTargetS<"#BSz#">"; } -def btargetS21 : Operand { - let OperandType = "OPERAND_PCREL"; - let DecoderMethod = "DecodeBranchTargetS21"; +class BranchTargetS : BCTargetSigned; +def btargetS7 : BranchTargetS<7>; +def btargetS8 : BranchTargetS<8>; +def btargetS9 : BranchTargetS<9>; +def btargetS10 : BranchTargetS<10>; +def btargetS13 : BranchTargetS<13>; +def btargetS21 : BranchTargetS<21>; +def btargetS25 : BranchTargetS<25>; + +class CallTargetS : BCTargetSigned; +def calltargetS25: CallTargetS<25>; + +// Compact Branch on Compare Register with Zero. +class F16_BCC_REG : + InstARC<2, (outs), (ins GPR32:$b, btargetS8:$s8), + !strconcat(asmstr, "\t$b, 0, $s8"), []> { + + bits<3> b; + bits<8> s8; + + let Inst{15-11} = 0b11101; + let Inst{10-8} = b; + let Inst{7} = i; + let Inst{6-0} = s8{7-1}; + let s8{0} = 0b0; } -def btargetS25 : Operand { - let OperandType = "OPERAND_PCREL"; - let DecoderMethod = "DecodeBranchTargetS25"; +// Compact Branch Conditionally Format. +class F16_BCC i, dag ins, string asmstr> : + InstARC<2, (outs), ins, asmstr, []> { + + let Inst{15-11} = 0b11110; + let Inst{10-9} = i; } -def calltargetS25: Operand { - let OperandType = "OPERAND_PCREL"; - let DecoderMethod = "DecodeBranchTargetS25"; +class F16_BCC_s10 i, string asmstr> : + F16_BCC { + + bits<10> s; + let Inst{8-0} = s{9-1}; + let s{0} = 0b0; } +class F16_BCC_s7 i, string asmstr> : + F16_BCC<0b11, (ins btargetS7:$s), + !strconcat(asmstr, "\t$s")> { + + bits<7> s; + let Inst{8-6} = i; + let Inst{5-0} = s{6-1}; + let s{0} = 0b0; +} diff --git a/lib/Target/ARC/ARCInstrInfo.td b/lib/Target/ARC/ARCInstrInfo.td index 79ab42fcef328..e4ad162edee0f 100644 --- a/lib/Target/ARC/ARCInstrInfo.td +++ b/lib/Target/ARC/ARCInstrInfo.td @@ -117,7 +117,7 @@ def STB_FAR : PseudoInstARC<(outs), (ins GPR32:$dst, MEMrlimm:$addr), // multiclass. These classes do not contain Selection DAG patterns. //===----------------------------------------------------------------------===// -// Generic 3 operand binary instructions (i.e., add, r0, r1, r2). +// Generic 3 operand binary instructions (i.e., add r0, r1, r2). multiclass ArcBinaryInst major, bits<6> mincode, string opasm> { // 3 register variant. @@ -140,7 +140,7 @@ multiclass ArcBinaryInst major, bits<6> mincode, // 2 matched-register with signed 12-bit immediate variant (add r0, r0, -1). def _rrs12 : F32_DOP_RS12:$S12), !strconcat(opasm, "\t$B, $in, $S12"), []> { let Constraints = "$B = $in"; } @@ -194,6 +194,9 @@ multiclass MultiPat; defm SUB : ArcBinaryGEN4Inst<0b000010, "sub">; +defm SUB1 : ArcBinaryGEN4Inst<0b010111, "sub1">; +defm SUB2 : ArcBinaryGEN4Inst<0b011000, "sub2">; +defm SUB3 : ArcBinaryGEN4Inst<0b011001, "sub3">; defm OR : ArcBinaryGEN4Inst<0b000101, "or">; defm AND : ArcBinaryGEN4Inst<0b000100, "and">; defm XOR : ArcBinaryGEN4Inst<0b000111, "xor">; @@ -206,6 +209,7 @@ defm ROR : ArcBinaryEXT5Inst<0b000011, "ror">; defm MPY : ArcBinaryGEN4Inst<0b011010, "mpy">; defm MPYM : ArcBinaryGEN4Inst<0b011011, "mpym">; defm MPYMU : ArcBinaryGEN4Inst<0b011100, "mpymu">; +defm SETEQ : ArcBinaryGEN4Inst<0b111000, "seteq">; // Patterns for 3 operand binary instructions. defm : MultiPat; @@ -223,7 +227,6 @@ defm : MultiPat; defm : MultiPat; defm : MultiPat; - // --------------------------------------------------------------------------- // Unary Instruction definitions. // --------------------------------------------------------------------------- @@ -248,9 +251,9 @@ defm : MultiPat; // --------------------------------------------------------------------------- let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { def MOV_rs12 : F32_DOP_RS12<0b00100, 0b001010, 0, - (outs GPR32:$B), (ins immS12:$S12), + (outs GPR32:$B), (ins immS<12>:$S12), "mov\t$B, $S12", - [(set GPR32:$B, immS12:$S12)]>; + [(set GPR32:$B, immS<12>:$S12)]>; } def MOV_rr : F32_DOP_RR<0b00100, 0b001010, 0, @@ -288,96 +291,463 @@ def : Pat<(ARCGAWrapper tjumptable:$addr), // --------------------------------------------------------------------------- // Branch instructions -let isBranch = 1, isTerminator = 1, isBarrier = 1 in { -// Unconditional branch. -def BR : F32_BR0_UCOND_FAR<(outs), (ins btargetS25:$S25), - "b\t$S25", [(br bb:$S25)]>; - -let Uses=[STATUS32] in { -// Conditional branch. -def Bcc : F32_BR0_COND<(outs), (ins btargetS21:$S21, ccond:$cc), - "b$cc\t$S21", []>; -} - -// Compare and branch (limited range). -def BRcc_rr : F32_BR1_BCC<(outs), - (ins btargetS9:$S9, GPR32:$B, GPR32:$C, brccond:$cc), - "br$cc\t$B, $C, $S9", 0, []>; -def BRcc_ru6 : F32_BR1_BCC<(outs), - (ins btargetS9:$S9, GPR32:$B, immU6:$C, brccond:$cc), - "br$cc\t$B, $C, $S9", 1, []>; - -// Pseudo compare and branch. -// After register allocation, this can expand into either a limited range -// Compare and branch (BRcc), or into CMP + Bcc. -// At worst, this expands into 2 4-byte instructions. -def BRcc_rr_p : PseudoInstARC<(outs), - (ins btarget:$T, GPR32:$B, GPR32:$C, ccond:$cc), - "pbr$cc\t$B, $C, $T", - [(ARCbrcc bb:$T, i32:$B, i32:$C, imm32:$cc)]> - { let Size = 8; } - -def BRcc_ru6_p : PseudoInstARC<(outs), - (ins btarget:$T, GPR32:$B, i32imm:$C, ccond:$cc), - "pbr$cc\t$B, $C, $T", - [(ARCbrcc bb:$T, i32:$B, immU6:$C, imm32:$cc)]> - { let Size = 8; } -} +let isBranch = 1, isTerminator = 1 in { + + // Unconditional branch. + let isBarrier = 1 in + def BR : F32_BR0_UCOND_FAR<(outs), (ins btargetS25:$S25), + "b\t$S25", [(br bb:$S25)]>; + + let Uses=[STATUS32] in + // Conditional branch. + def Bcc : F32_BR0_COND<(outs), (ins btargetS21:$S21, ccond:$cc), + "b$cc\t$S21", []>; + + // Compare and branch (limited range). + def BRcc_rr : F32_BR1_BCC<(outs), + (ins btargetS9:$S9, GPR32:$B, GPR32:$C, brccond:$cc), + "br$cc\t$B, $C, $S9", 0, []>; + def BRcc_ru6 : F32_BR1_BCC<(outs), + (ins btargetS9:$S9, GPR32:$B, immU6:$C, brccond:$cc), + "br$cc\t$B, $C, $S9", 1, []>; + + // Pseudo compare and branch. + // After register allocation, this can expand into either a limited range + // Compare and branch (BRcc), or into CMP + Bcc. + // At worst, this expands into 2 4-byte instructions. + def BRcc_rr_p : PseudoInstARC<(outs), + (ins btarget:$T, GPR32:$B, GPR32:$C, ccond:$cc), + "pbr$cc\t$B, $C, $T", + [(ARCbrcc bb:$T, i32:$B, i32:$C, imm32:$cc)]> + { let Size = 8; } + + def BRcc_ru6_p : PseudoInstARC<(outs), + (ins btarget:$T, GPR32:$B, i32imm:$C, ccond:$cc), + "pbr$cc\t$B, $C, $T", + [(ARCbrcc bb:$T, i32:$B, immU6:$C, imm32:$cc)]> + { let Size = 8; } +} // let isBranch, isTerminator // Indirect, unconditional Jump. -let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { +let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in def J : F32_DOP_RR<0b00100, 0b100000, 0, (outs), (ins GPR32:$C), "j\t[$C]", [(brind i32:$C)]>; -} // Call instructions. -let isCall = 1, Defs = [BLINK], Uses = [SP] in { -// Direct unconditional call. -def BL : F32_BR1_BL_UCOND_FAR<(outs), (ins calltargetS25:$S25), - "bl\t$S25", [(ARCBranchLink tglobaladdr:$S25)]>; - -// Indirect unconditional call. -let isIndirectBranch = 1, Defs = [BLINK], Uses = [SP] in { -def JL : F32_DOP_RR<0b00100, 0b100010, 0, (outs), (ins GPR32:$C), - "jl\t[$C]", [(ARCJumpLink i32:$C)]>; -} -} +let isCall = 1, isBarrier = 1, Defs = [BLINK], Uses = [SP] in { + // Direct unconditional call. + def BL : F32_BR1_BL_UCOND_FAR<(outs), (ins calltargetS25:$S25), + "bl\t$S25", [(ARCBranchLink tglobaladdr:$S25)]>; + + // Indirect unconditional call. + let isIndirectBranch = 1 in + def JL : F32_DOP_RR<0b00100, 0b100010, 0, (outs), (ins GPR32:$C), + "jl\t[$C]", [(ARCJumpLink i32:$C)]>; +} // let isCall, isBarrier, Defs, Uses // Pattern to generate BL instruction. def : Pat<(ARCBranchLink texternalsym:$dst), (BL texternalsym:$dst)>; // Return from call. -let isReturn = 1, isTerminator = 1, isBarrier = 1 in { +let isReturn = 1, isTerminator = 1, isBarrier = 1 in // This is a specialized 2-byte instruction that doesn't generalize // to any larger 2-byte class, so go ahead and define it here. def J_S_BLINK : InstARC<2, (outs), (ins), "j_s\t[%blink]", [(ret)]> { let Inst{15-0} = 0b0111111011100000; } -} //---------------------------------------------------------------------------- -// Load/Store instructions. +// Compact stack-based operations. //---------------------------------------------------------------------------- // 2-byte push/pop blink instructions commonly used for prolog/epilog // generation. These 2 instructions are actually specialized 2-byte // format instructions that aren't generalized to a larger 2-byte // class, so we might as well have them here. -let Uses = [BLINK], Defs = [SP] in { -def PUSH_S_BLINK : InstARC<2, (outs), (ins), - "push_s\t%blink", []> { - let Inst{15-0} = 0b1100000011110001; +let Uses = [BLINK], Defs = [SP] in +def PUSH_S_BLINK : F16_SP_OPS_buconst<0b111, "push_s">; + +let Defs = [BLINK, SP] in +def POP_S_BLINK : F16_SP_OPS_buconst<0b110, "pop_s">; + +def PUSH_S_r : F16_SP_OPS_uconst<0b110, + (outs), (ins GPR32Reduced:$b3), "push_s">; +def POP_S_r : F16_SP_OPS_uconst<0b111, + (outs GPR32Reduced:$b3), (ins), "pop_s">; + +def SP_SUB_SP_S : F16_SP_OPS_bconst<0b001, "sub_s">; +def SP_ADD_SP_S : F16_SP_OPS_bconst<0b000, "add_s">; +def SP_ADD_S : F16_SP_OPS_u7_aligned<0b100, + (outs GPR32Reduced:$b3), (ins immU<7>:$u7), + "add_s\t$b3, %sp, $u7">; + +def SP_LD_S : F16_SP_LD<0b000, "ld_s">; +def SP_LDB_S : F16_SP_LD<0b001, "ldb_s">; +def SP_ST_S : F16_SP_ST<0b010, "st_s">; +def SP_STB_S : F16_SP_ST<0b011, "stb_s">; + +def LEAVE_S : F16_SP_OPS<0b110, + (outs), (ins immU<7>:$u7), "leave_s\t$u7"> { + + bits<7> u7; + + let fieldB = u7{6-4}; + let fieldU{4-1} = u7{3-0}; + let fieldU{0} = 0b0; +} + +def ENTER_S : F16_SP_OPS<0b111, + (outs), (ins immU<6>:$u6), "enter_s\t$u6"> { + + bits<6> u6; + + let fieldB{2} = 0; + let fieldB{1-0} = u6{5-4}; + let fieldU{4-1} = u6{3-0}; + let fieldU{0} = 0b0; +} + +//---------------------------------------------------------------------------- +// Compact Move/Load instructions. +//---------------------------------------------------------------------------- +class COMPACT_MOV_S : + F16_COMPACT<0b0, (outs GPR32:$g), (ins GPR32:$h), + "mov_s\t$g, $h"> { + let DecoderMethod = "DecodeMoveHRegInstruction"; +} + +def COMPACT_MOV_S_limm : COMPACT_MOV_S { + bits<32> LImm; + let Inst{47-16} = LImm; + + bits<5> LImmReg = 0b11110; + let Inst{7-5} = LImmReg{2-0}; + let Inst{1-0} = LImmReg{4-3}; + + let Size = 6; +} + +def COMPACT_MOV_S_hreg : COMPACT_MOV_S; + +def COMPACT_LD_S : + F16_COMPACT<0b1, (outs GPR32:$r), (ins GPR32:$h, immU<5>:$u5), + "ld_s\t$r, [$h, $u5]"> { + bits<5> u5; + bits<2> r; + + let Inst{10} = u5{4}; + let Inst{9-8} = r; + let Inst{4-3} = u5{3-2}; + let u5{1-0} = 0b00; +} + +//---------------------------------------------------------------------------- +// Compact Load/Add/Sub. +//---------------------------------------------------------------------------- +def LD_S_AS_rrr : F16_LD_SUB<0b0, "ld_s.as\t$a, [$b, $c]">; +def SUB_S_rrr : F16_LD_SUB<0b1, "sub_s\t$a, $b, $c">; +def ADD_S_rru6 : F16_ADD; + +//---------------------------------------------------------------------------- +// Compact Load/Store. +//---------------------------------------------------------------------------- +def LD_S_s11 : F16_LD_ST_s11<0b0, "ld_s\t%r1, [%gp, $s11]">; +def ST_S_s11 : F16_LD_ST_s11<0b1, "st_s\t%r0, [%gp, $s11]">; +def LDI_S_u7 : F16_LDI_u7; + +//---------------------------------------------------------------------------- +// Indexed Jump or Execute. +//---------------------------------------------------------------------------- +def JLI_S : F16_JLI_EI<0, "jli_s">; +def EI_S : F16_JLI_EI<1, "ei_s">; + +//---------------------------------------------------------------------------- +// Load/Add Register-Register. +//---------------------------------------------------------------------------- +def LD_S_rrr : F16_LD_ADD_RR<0b00, "ld_s\t$a, [$b, $c]">; +def LDB_S_rrr : F16_LD_ADD_RR<0b01, "ldb_s\t$a, [$b, $c]">; +def LDH_S_rrr : F16_LD_ADD_RR<0b10, "ldh_s\t$a, [$b, $c]">; +def ADD_S_rrr : F16_LD_ADD_RR<0b11, "add_s\t$a, $b, $c">; + +//---------------------------------------------------------------------------- +// Load/Add GP-Relative. +//---------------------------------------------------------------------------- +def GP_LD_S : F16_GP_LD_ADD<0b00, (ins immS<11>:$s), + "ld_s\t%r0, [%gp, $s]"> { + + bits<11> s; + let Inst{8-0} = s{10-2}; + let s{1-0} = 0b00; +} + +def GP_LDB_S : F16_GP_LD_ADD<0b01, (ins immS<9>:$s), + "ldb_s\t%r0, [%gp, $s]"> { + + bits<9> s; + let Inst{8-0} = s{8-0}; +} + +def GP_LDH_S : F16_GP_LD_ADD<0b10, (ins immS<10>:$s), + "ldh_s\t%r0, [%gp, $s]"> { + + bits<10> s; + let Inst{8-0} = s{9-1}; + let s{0} = 0b0; +} + +def GP_ADD_S : F16_GP_LD_ADD<0b11, (ins immS<11>:$s), + "add_s\t%r0, %gp, $s"> { + + bits<11> s; + let Inst{8-0} = s{10-2}; + let s{1-0} = 0b00; +} + +//---------------------------------------------------------------------------- +// Load PCL-Relative. +//---------------------------------------------------------------------------- +def PCL_LD : InstARC<2, (outs GPR32:$b), (ins immU<10>:$u10), + "ld_s\t$b, [%pcl, $u10]", []> { + + bits<3> b; + bits<10> u10; + + let Inst{15-11} = 0b11010; + let Inst{10-8} = b; + let Inst{7-0} = u10{9-2}; + let u10{1-0} = 0b00; +} + +let isBranch = 1 in { + //---------------------------------------------------------------------------- + // Branch on Compare Register with Zero. + //---------------------------------------------------------------------------- + def BREQ_S : F16_BCC_REG<0b0, "breq_s">; + def BRNE_S : F16_BCC_REG<0b1, "brne_s">; + + //---------------------------------------------------------------------------- + // Branch Conditionally. + //---------------------------------------------------------------------------- + let isBarrier = 1 in + def B_S : F16_BCC_s10<0b00, "b_s">; + + def BEQ_S : F16_BCC_s10<0b01, "beq_s">; + def BNE_S : F16_BCC_s10<0b10, "bne_s">; + def BGT_S : F16_BCC_s7<0b000, "bgt_s">; + def BGE_S : F16_BCC_s7<0b001, "bge_s">; + def BLT_S : F16_BCC_s7<0b010, "blt_s">; + def BLE_S : F16_BCC_s7<0b011, "ble_s">; + def BHI_S : F16_BCC_s7<0b100, "bhi_s">; + def BHS_S : F16_BCC_s7<0b101, "bhs_s">; + def BLO_S : F16_BCC_s7<0b110, "blo_s">; + def BLS_S : F16_BCC_s7<0b111, "bls_s">; +} // let isBranch + +def BL_S : + InstARC<2, (outs), (ins btargetS13:$s13), "bl_s\t$s13", []> { + + let Inst{15-11} = 0b11111; + + bits<13> s13; + let Inst{10-0} = s13{12-2}; + let s13{1-0} = 0b00; + + let isCall = 1; + let isBarrier = 1; } + +//---------------------------------------------------------------------------- +// Add/Sub/Shift Register-Immediate. +//---------------------------------------------------------------------------- +def ADD_S_ru3 : F16_ADD_IMM<0b00,"add_s">; +def SUB_S_ru3 : F16_ADD_IMM<0b01,"sub_s">; +def ASL_S_ru3 : F16_ADD_IMM<0b10,"asl_s">; +def ASR_S_ru3 : F16_ADD_IMM<0b11,"asr_s">; + +//---------------------------------------------------------------------------- +// Shift/Subtract/Bit Immediate. +//---------------------------------------------------------------------------- +def ASL_S_ru5 : F16_SH_SUB_BIT_DST<0b000,"asl_s">; +def LSR_S_ru5 : F16_SH_SUB_BIT_DST<0b001,"lsr_s">; +def ASR_S_ru5 : F16_SH_SUB_BIT_DST<0b010,"asr_s">; +def SUB_S_ru5 : F16_SH_SUB_BIT_DST<0b011,"sub_s">; +def BSET_S_ru5 : F16_SH_SUB_BIT_DST<0b100,"bset_s">; +def BCLR_S_ru5 : F16_SH_SUB_BIT_DST<0b101,"bclr_s">; +def BMSK_S_ru5 : F16_SH_SUB_BIT_DST<0b110,"bmsk_s">; +def BTST_S_ru5 : F16_SH_SUB_BIT<0b111, "btst_s\t$b, $u5">; + +//---------------------------------------------------------------------------- +// Dual Register Operations. +//---------------------------------------------------------------------------- +def ADD_S_rlimm : + F16_OP_HREG_LIMM<0b000, (outs GPR32:$b_s3), (ins i32imm:$LImm), + !strconcat("add_s", "\t$b_s3, $b_s3, $LImm")>; + +def ADD_S_rr : + F16_OP_HREG<0b000, (outs GPR32:$b_s3), (ins GPR32:$h), + !strconcat("add_s", "\t$b_s3, $b_s3, $h")>; + +def ADD_S_rs3 : + F16_OP_HREG<0b001, (outs GPR32:$h), (ins immC<3>:$b_s3), + !strconcat("add_s", "\t$h, $h, $b_s3")>; + +def ADD_S_limms3 : + F16_OP_HREG_LIMM<0b001, (outs), (ins immC<3>:$b_s3, i32imm:$LImm), + !strconcat("add_s", "\t0, $LImm, $b_s3")>; + +def MOV_S_NE_rlimm : + F16_OP_HREG_LIMM<0b111, (outs GPR32:$b_s3), (ins i32imm:$LImm), + !strconcat("mov_s.ne", "\t$b_s3, $LImm")>; + +def MOV_S_NE_rr : + F16_OP_HREG<0b111,(outs GPR32:$b_s3), (ins GPR32:$h), + !strconcat("mov_s.ne", "\t$b_s3, $h")>; + +def MOV_S_rs3 : + F16_OP_HREG<0b011, (outs GPR32:$h), (ins immC<3>:$b_s3), + !strconcat("mov_s", "\t$h, $b_s3")>; + +def MOV_S_s3 : + F16_OP_HREG30<0b011, (outs), (ins immC<3>:$b_s3), + !strconcat("mov_s", "\t0, $b_s3")>; + +def CMP_S_rlimm : + F16_OP_HREG_LIMM<0b100, (outs GPR32:$b_s3), (ins i32imm:$LImm), + !strconcat("cmp_s", "\t$b_s3, $LImm")>; + +def CMP_S_rr : + F16_OP_HREG<0b100, (outs GPR32:$b_s3), (ins GPR32:$h), + !strconcat("cmp_s", "\t$b_s3, $h")>; + +def CMP_S_rs3 : + F16_OP_HREG<0b101, (outs GPR32:$h), (ins immC<3>:$b_s3), + !strconcat("cmp_s", "\t$h, $b_s3")>; + +def CMP_S_limms3 : + F16_OP_HREG_LIMM<0b101, (outs), (ins immC<3>:$b_s3, i32imm:$LImm), + !strconcat("cmp_s", "\t$LImm, $b_s3")>; + +//---------------------------------------------------------------------------- +// Compact MOV/ADD/CMP Immediate instructions. +//---------------------------------------------------------------------------- +def MOV_S_u8 : + F16_OP_IMM<0b11011, (outs GPR32:$b), (ins immU<8>:$u8), + !strconcat("mov_s", "\t$b, $u8")> { + bits<8> u8; + let Inst{7-0} = u8; } -let Defs = [BLINK, SP] in { -def POP_S_BLINK : InstARC<2, (outs), (ins), - "pop_s\t%blink", []> { - let Inst{15-0} = 0b1100000011010001; +def ADD_S_u7 : + F16_OP_U7<0b0, !strconcat("add_s", "\t$b, $b, $u7")>; + +def CMP_S_u7 : + F16_OP_U7<0b1, !strconcat("cmp_s", "\t$b, $u7")>; + +//---------------------------------------------------------------------------- +// Compact Load/Store instructions with offset. +//---------------------------------------------------------------------------- +def LD_S_OFF : + F16_LD_ST_WORD_OFF<0x10, (outs GPR32:$c), (ins GPR32:$b, immU<7>:$off), + "ld_s">; + +def LDB_S_OFF : + F16_LD_ST_BYTE_OFF<0x11, (outs GPR32:$c), (ins GPR32:$b, immU<5>:$off), + "ldb_s">; + +class F16_LDH_OFF opc, string asmstr> : + F16_LD_ST_HALF_OFF:$off), + asmstr>; + +def LDH_S_OFF : F16_LDH_OFF<0x12, "ldh_s">; +def LDH_S_X_OFF : F16_LDH_OFF<0x13, "ldh_s.x">; + +def ST_S_OFF : + F16_LD_ST_WORD_OFF<0x14, (outs), (ins GPR32:$c, GPR32:$b, immU<7>:$off), + "st_s">; + +def STB_S_OFF : + F16_LD_ST_BYTE_OFF<0x15, (outs), (ins GPR32:$c, GPR32:$b, immU<5>:$off), + "stb_s">; + +def STH_S_OFF : + F16_LD_ST_HALF_OFF<0x16, (outs), (ins GPR32:$c, GPR32:$b, immU<6>:$off), + "sth_s">; + +//---------------------------------------------------------------------------- +// General compact instructions. +//---------------------------------------------------------------------------- +def GEN_SUB_S : F16_GEN_DOP<0x02, "sub_s">; +def GEN_AND_S : F16_GEN_DOP<0x04, "and_s">; +def GEN_OR_S : F16_GEN_DOP<0x05, "or_s">; +def GEN_BIC_S : F16_GEN_DOP<0x06, "bic_s">; +def GEN_XOR_S : F16_GEN_DOP<0x07, "xor_s">; +def GEN_MPYW_S : F16_GEN_DOP<0x09, "mpyw_s">; +def GEN_MPYUW_S : F16_GEN_DOP<0x0a, "mpyuw_s">; +def GEN_TST_S : F16_GEN_DOP_NODST<0x0b, "tst_s">; +def GEN_MPY_S : F16_GEN_DOP<0x0c, "mpy_s">; +def GEN_SEXB_S : F16_GEN_DOP_SINGLESRC<0x0d, "sexb_s">; +def GEN_SEXH_S : F16_GEN_DOP_SINGLESRC<0x0e, "sexh_s">; +def GEN_EXTB_S : F16_GEN_DOP_SINGLESRC<0x0f, "extb_s">; +def GEN_EXTH_S : F16_GEN_DOP_SINGLESRC<0x10, "exth_s">; +def GEN_ABS_S : F16_GEN_DOP_SINGLESRC<0x11, "abs_s">; +def GEN_NOT_S : F16_GEN_DOP_SINGLESRC<0x12, "not_s">; +def GEN_NEG_S : F16_GEN_DOP_SINGLESRC<0x13, "neg_s">; +def GEN_ADD1_S : F16_GEN_DOP<0x14, "add1_s">; +def GEN_ADD2_S : F16_GEN_DOP<0x15, "add2_s">; +def GEN_ADD3_S : F16_GEN_DOP<0x16, "add3_s">; +def GEN_ASL_S : F16_GEN_DOP<0x18, "asl_s">; +def GEN_LSR_S : F16_GEN_DOP<0x19, "lsr_s">; +def GEN_ASR_S : F16_GEN_DOP<0x1a, "asr_s">; +def GEN_AS1L_S : F16_GEN_DOP_SINGLESRC<0x1b, "asl_s">; +def GEN_AS1R_S : F16_GEN_DOP_SINGLESRC<0x1c, "asr_s">; +def GEN_LS1R_S : F16_GEN_DOP_SINGLESRC<0x1d, "lsr_s">; +def GEN_TRAP_S : F16_GEN_DOP_BASE<0x1e, (outs), (ins immU6:$u6), + "trap_s\t$u6"> { + + bits<6> u6; + let b = u6{5-3}; + let c = u6{2-0}; } + +def GEN_BRK_S : F16_GEN_DOP_BASE<0x1f, (outs), (ins), + "brk_s"> { + + let b = 0b111; + let c = 0b111; } +let isBarrier = 1 in { + let isBranch = 1 in { + def GEN_J_S : F16_GEN_SOP<0x0, "j_s\t[$b]">; + def GEN_J_S_D : F16_GEN_SOP<0x1, "j_s.d\t[$b]">; + } // let isBranch + + let isCall = 1 in { + def GEN_JL_S : F16_GEN_SOP<0x2, "jl_s\t[$b]">; + def GEN_JL_S_D : F16_GEN_SOP<0x3, "jl_s.d\t[$b]">; + } // let isCall +} // let isBarrier + +def GEN_SUB_S_NE : F16_GEN_SOP<0x6, "sub_s.ne\t$b, $b, $b">; + +def GEN_NOP_S : F16_GEN_ZOP<0x0, "nop_s">; +def GEN_UNIMP_S : F16_GEN_ZOP<0x1, "unimp_s">; +def GEN_SWI_S : F16_GEN_ZOP<0x2, "swi_s">; + +let isReturn = 1, isTerminator = 1 in { + def GEN_JEQ_S : F16_GEN_ZOP<0x4, "jeq_s\t[%blink]">; + def GEN_JNE_S : F16_GEN_ZOP<0x5, "jne_s\t[%blink]">; + let isBarrier = 1 in { + //def GEN_J_S_BLINK : F16_GEN_ZOP<0x6, "j_s\t[%blink]">; + def GEN_J_S_D_BLINK : F16_GEN_ZOP<0x7, "j_s.d\t[%blink]">; + } // let isBarrier +} // let isReturn, isTerminator + +//---------------------------------------------------------------------------- +// Load/Store instructions. +//---------------------------------------------------------------------------- + // Load instruction variants: // Control bits: x, aa, di, zz // x - sign extend. @@ -412,7 +782,7 @@ multiclass ArcLdInst zz, string asmop> { def _AB_rs9 : F32_LD_RS9<0, 0b10, 0, zz, (outs GPR32:$addrout, GPR32:$A), - (ins GPR32:$B, immS9:$S9), + (ins GPR32:$B, immS<9>:$S9), !strconcat(asmop, ".ab\t$A, [$B,$S9]"), []> { let Constraints = "$addrout = $B"; } } @@ -472,7 +842,7 @@ multiclass ArcStInst zz, string asmop> { !strconcat(asmop, "\t$C, [$addr]"), []>; def _AW_rs9 : F32_ST_RS9<0b01, 0, zz, (outs GPR32:$addrout), - (ins GPR32:$C, GPR32:$B, immS9:$S9), + (ins GPR32:$C, GPR32:$B, immS<9>:$S9), !strconcat(asmop, ".aw\t$C, [$B,$S9]"), []> { let Constraints = "$addrout = $B"; } } diff --git a/lib/Target/ARC/Disassembler/ARCDisassembler.cpp b/lib/Target/ARC/Disassembler/ARCDisassembler.cpp index b49658004f7ad..82199d858c0c6 100644 --- a/lib/Target/ARC/Disassembler/ARCDisassembler.cpp +++ b/lib/Target/ARC/Disassembler/ARCDisassembler.cpp @@ -67,6 +67,15 @@ static bool readInstruction64(ArrayRef Bytes, uint64_t Address, return true; } +static bool readInstruction48(ArrayRef Bytes, uint64_t Address, + uint64_t &Size, uint64_t &Insn) { + Size = 6; + Insn = ((uint64_t)Bytes[0] << 0) | ((uint64_t)Bytes[1] << 8) | + ((uint64_t)Bytes[2] << 32) | ((uint64_t)Bytes[3] << 40) | + ((uint64_t)Bytes[4] << 16) | ((uint64_t)Bytes[5] << 24); + return true; +} + static bool readInstruction16(ArrayRef Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn) { Size = 2; @@ -74,32 +83,33 @@ static bool readInstruction16(ArrayRef Bytes, uint64_t Address, return true; } -static MCDisassembler::DecodeStatus DecodeS12Operand(MCInst &, unsigned, - uint64_t, const void *); - -static MCDisassembler::DecodeStatus DecodeS9Operand(MCInst &, unsigned, - uint64_t, const void *); +template +static DecodeStatus DecodeSignedOperand(MCInst &Inst, unsigned InsnS, + uint64_t Address = 0, + const void *Decoder = nullptr); -static MCDisassembler::DecodeStatus -DecodeBranchTargetS9(MCInst &, unsigned, uint64_t, const void *); +template +static DecodeStatus DecodeFromCyclicRange(MCInst &Inst, unsigned InsnS, + uint64_t Address = 0, + const void *Decoder = nullptr); -static MCDisassembler::DecodeStatus -DecodeBranchTargetS21(MCInst &, unsigned, uint64_t, const void *); +template +static DecodeStatus DecodeBranchTargetS(MCInst &Inst, unsigned InsnS, + uint64_t Address, const void *Decoder); -static MCDisassembler::DecodeStatus -DecodeBranchTargetS25(MCInst &, unsigned, uint64_t, const void *); +static DecodeStatus DecodeMEMrs9(MCInst &, unsigned, uint64_t, const void *); -static MCDisassembler::DecodeStatus DecodeMEMrs9(MCInst &, unsigned, uint64_t, - const void *); +static DecodeStatus DecodeLdLImmInstruction(MCInst &, uint64_t, uint64_t, + const void *); -static MCDisassembler::DecodeStatus -DecodeLdLImmInstruction(MCInst &, uint64_t, uint64_t, const void *); +static DecodeStatus DecodeStLImmInstruction(MCInst &, uint64_t, uint64_t, + const void *); -static MCDisassembler::DecodeStatus -DecodeStLImmInstruction(MCInst &, uint64_t, uint64_t, const void *); +static DecodeStatus DecodeLdRLImmInstruction(MCInst &, uint64_t, uint64_t, + const void *); -static MCDisassembler::DecodeStatus -DecodeLdRLImmInstruction(MCInst &, uint64_t, uint64_t, const void *); +static DecodeStatus DecodeMoveHRegInstruction(MCInst &Inst, uint64_t, uint64_t, + const void *); static const uint16_t GPR32DecoderTable[] = { ARC::R0, ARC::R1, ARC::R2, ARC::R3, ARC::R4, ARC::R5, ARC::R6, @@ -115,11 +125,22 @@ static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, DEBUG(dbgs() << "Not a GPR32 register."); return MCDisassembler::Fail; } + unsigned Reg = GPR32DecoderTable[RegNo]; Inst.addOperand(MCOperand::createReg(Reg)); return MCDisassembler::Success; } +static DecodeStatus DecodeGBR32ShortRegister(MCInst &Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { + // Enumerates registers from ranges [r0-r3],[r12-r15]. + if (RegNo > 3) + RegNo += 8; // 4 for r12, etc... + + return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); +} + #include "ARCGenDisassemblerTables.inc" static unsigned decodeCField(unsigned Insn) { @@ -135,8 +156,8 @@ static unsigned decodeAField(unsigned Insn) { return fieldFromInstruction(Insn, 0, 6); } -static MCDisassembler::DecodeStatus -DecodeMEMrs9(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Dec) { +static DecodeStatus DecodeMEMrs9(MCInst &Inst, unsigned Insn, uint64_t Address, + const void *Dec) { // We have the 9-bit immediate in the low bits, 6-bit register in high bits. unsigned S9 = Insn & 0x1ff; unsigned R = (Insn & (0x7fff & ~0x1ff)) >> 9; @@ -145,49 +166,59 @@ DecodeMEMrs9(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Dec) { return MCDisassembler::Success; } -static MCDisassembler::DecodeStatus DecodeS9Operand(MCInst &Inst, - unsigned InsnS9, - uint64_t Address, - const void *Decoder) { - Inst.addOperand(MCOperand::createImm(SignExtend32<9>(0x1ff & InsnS9))); - return MCDisassembler::Success; +static bool DecodeSymbolicOperand(MCInst &Inst, uint64_t Address, + uint64_t Value, const void *Decoder) { + static const uint64_t atLeast = 2; + // TODO: Try to force emitter to use MCDisassembler* instead of void*. + auto Disassembler = static_cast(Decoder); + return (nullptr != Disassembler && + Disassembler->tryAddingSymbolicOperand(Inst, Value, Address, true, 0, + atLeast)); } -static MCDisassembler::DecodeStatus DecodeS12Operand(MCInst &Inst, - unsigned InsnS12, - uint64_t Address, - const void *Decoder) { - Inst.addOperand(MCOperand::createImm(SignExtend32<12>(0xfff & InsnS12))); - return MCDisassembler::Success; +static void DecodeSymbolicOperandOff(MCInst &Inst, uint64_t Address, + uint64_t Offset, const void *Decoder) { + uint64_t nextAddress = Address + Offset; + + if (!DecodeSymbolicOperand(Inst, Address, nextAddress, Decoder)) + Inst.addOperand(MCOperand::createImm(Offset)); } -static MCDisassembler::DecodeStatus DecodeBranchTargetS9(MCInst &Inst, - unsigned S, - uint64_t Address, - const void *Decoder) { - Inst.addOperand(MCOperand::createImm(SignExtend32<9>(S))); +template +static DecodeStatus DecodeBranchTargetS(MCInst &Inst, unsigned InsnS, + uint64_t Address, const void *Decoder) { + + static_assert(B > 0, "field is empty"); + DecodeSymbolicOperandOff(Inst, Address, SignExtend32(InsnS), Decoder); return MCDisassembler::Success; } -static MCDisassembler::DecodeStatus DecodeBranchTargetS21(MCInst &Inst, - unsigned S, - uint64_t Address, - const void *Decoder) { - Inst.addOperand(MCOperand::createImm(SignExtend32<21>(S))); +template +static DecodeStatus DecodeSignedOperand(MCInst &Inst, unsigned InsnS, + uint64_t /*Address*/, + const void * /*Decoder*/) { + + static_assert(B > 0, "field is empty"); + Inst.addOperand(MCOperand::createImm( + SignExtend32(maskTrailingOnes(B) & InsnS))); return MCDisassembler::Success; } -static MCDisassembler::DecodeStatus DecodeBranchTargetS25(MCInst &Inst, - unsigned S, - uint64_t Address, - const void *Decoder) { - Inst.addOperand(MCOperand::createImm(SignExtend32<25>(S))); +template +static DecodeStatus DecodeFromCyclicRange(MCInst &Inst, unsigned InsnS, + uint64_t /*Address*/, + const void * /*Decoder*/) { + + static_assert(B > 0, "field is empty"); + const unsigned max = (1u << B) - 1; + Inst.addOperand( + MCOperand::createImm(InsnS < max ? static_cast(InsnS) : -1)); return MCDisassembler::Success; } -static MCDisassembler::DecodeStatus -DecodeStLImmInstruction(MCInst &Inst, uint64_t Insn, uint64_t Address, - const void *Decoder) { +static DecodeStatus DecodeStLImmInstruction(MCInst &Inst, uint64_t Insn, + uint64_t Address, + const void *Decoder) { unsigned SrcC, DstB, LImm; DstB = decodeBField(Insn); if (DstB != 62) { @@ -202,9 +233,9 @@ DecodeStLImmInstruction(MCInst &Inst, uint64_t Insn, uint64_t Address, return MCDisassembler::Success; } -static MCDisassembler::DecodeStatus -DecodeLdLImmInstruction(MCInst &Inst, uint64_t Insn, uint64_t Address, - const void *Decoder) { +static DecodeStatus DecodeLdLImmInstruction(MCInst &Inst, uint64_t Insn, + uint64_t Address, + const void *Decoder) { unsigned DstA, SrcB, LImm; DEBUG(dbgs() << "Decoding LdLImm:\n"); SrcB = decodeBField(Insn); @@ -220,9 +251,9 @@ DecodeLdLImmInstruction(MCInst &Inst, uint64_t Insn, uint64_t Address, return MCDisassembler::Success; } -static MCDisassembler::DecodeStatus -DecodeLdRLImmInstruction(MCInst &Inst, uint64_t Insn, uint64_t Address, - const void *Decoder) { +static DecodeStatus DecodeLdRLImmInstruction(MCInst &Inst, uint64_t Insn, + uint64_t Address, + const void *Decoder) { unsigned DstA, SrcB; DEBUG(dbgs() << "Decoding LdRLimm\n"); DstA = decodeAField(Insn); @@ -237,9 +268,37 @@ DecodeLdRLImmInstruction(MCInst &Inst, uint64_t Insn, uint64_t Address, return MCDisassembler::Success; } -MCDisassembler::DecodeStatus ARCDisassembler::getInstruction( - MCInst &Instr, uint64_t &Size, ArrayRef Bytes, uint64_t Address, - raw_ostream &vStream, raw_ostream &cStream) const { +static DecodeStatus DecodeMoveHRegInstruction(MCInst &Inst, uint64_t Insn, + uint64_t Address, + const void *Decoder) { + DEBUG(dbgs() << "Decoding MOV_S h-register\n"); + using Field = decltype(Insn); + Field h = fieldFromInstruction(Insn, 5, 3) | + (fieldFromInstruction(Insn, 0, 2) << 3); + Field g = fieldFromInstruction(Insn, 8, 3) | + (fieldFromInstruction(Insn, 3, 2) << 3); + + auto DecodeRegisterOrImm = [&Inst, Address, Decoder](Field RegNum, + Field Value) { + if (30 == RegNum) { + Inst.addOperand(MCOperand::createImm(Value)); + return MCDisassembler::Success; + } + + return DecodeGPR32RegisterClass(Inst, RegNum, Address, Decoder); + }; + + if (MCDisassembler::Success != DecodeRegisterOrImm(g, 0)) + return MCDisassembler::Fail; + + return DecodeRegisterOrImm(h, Insn >> 16u); +} + +DecodeStatus ARCDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, + ArrayRef Bytes, + uint64_t Address, + raw_ostream &vStream, + raw_ostream &cStream) const { MCDisassembler::DecodeStatus Result; if (Bytes.size() < 2) { Size = 0; @@ -262,9 +321,9 @@ MCDisassembler::DecodeStatus ARCDisassembler::getInstruction( return Fail; Result = decodeInstruction(DecoderTable64, Instr, Insn64, Address, this, STI); - if (Result == MCDisassembler::Success) { + if (Success == Result) { DEBUG(dbgs() << "Successfully decoded 64-bit instruction."); - return MCDisassembler::Success; + return Result; } DEBUG(dbgs() << "Not a 64-bit instruction, falling back to 32-bit."); } @@ -274,15 +333,28 @@ MCDisassembler::DecodeStatus ARCDisassembler::getInstruction( } // Calling the auto-generated decoder function. return decodeInstruction(DecoderTable32, Instr, Insn32, Address, this, STI); - } + } else { + if (Bytes.size() >= 6) { + // Attempt to treat as instr. with limm data. + uint64_t Insn48; + if (!readInstruction48(Bytes, Address, Size, Insn48)) + return Fail; + Result = + decodeInstruction(DecoderTable48, Instr, Insn48, Address, this, STI); + if (Success == Result) { + DEBUG(dbgs() << "Successfully decoded 16-bit instruction with limm."); + return Result; + } + DEBUG(dbgs() << "Not a 16-bit instruction with limm, try without it."); + } - // 16-bit instruction. - uint32_t Insn16; - if (!readInstruction16(Bytes, Address, Size, Insn16)) { - return Fail; + uint32_t Insn16; + if (!readInstruction16(Bytes, Address, Size, Insn16)) + return Fail; + + // Calling the auto-generated decoder function. + return decodeInstruction(DecoderTable16, Instr, Insn16, Address, this, STI); } - // Calling the auto-generated decoder function. - return decodeInstruction(DecoderTable16, Instr, Insn16, Address, this, STI); } static MCDisassembler *createARCDisassembler(const Target &T, diff --git a/lib/Target/ARC/InstPrinter/ARCInstPrinter.cpp b/lib/Target/ARC/InstPrinter/ARCInstPrinter.cpp index d4f1046db1225..4760ac4456d00 100644 --- a/lib/Target/ARC/InstPrinter/ARCInstPrinter.cpp +++ b/lib/Target/ARC/InstPrinter/ARCInstPrinter.cpp @@ -101,6 +101,12 @@ static void printExpr(const MCExpr *Expr, const MCAsmInfo *MAI, int Offset = 0; const MCSymbolRefExpr *SRE; + if (const auto *CE = dyn_cast(Expr)) { + OS << "0x"; + OS.write_hex(CE->getValue()); + return; + } + if (const auto *BE = dyn_cast(Expr)) { SRE = dyn_cast(BE->getLHS()); const auto *CE = dyn_cast(BE->getRHS()); diff --git a/lib/Target/ARM/ARMBaseInstrInfo.cpp b/lib/Target/ARM/ARMBaseInstrInfo.cpp index 6268b9ef2a37d..f9505beea20b5 100644 --- a/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -1650,7 +1650,7 @@ bool ARMBaseInstrInfo::produceSameValue(const MachineInstr &MI0, } for (unsigned i = 3, e = MI0.getNumOperands(); i != e; ++i) { - // %vreg12 = PICLDR %vreg11, 0, pred:14, pred:%noreg + // %12 = PICLDR %11, 0, pred:14, pred:%noreg const MachineOperand &MO0 = MI0.getOperand(i); const MachineOperand &MO1 = MI1.getOperand(i); if (!MO0.isIdenticalTo(MO1)) diff --git a/lib/Target/ARM/ARMBaseInstrInfo.h b/lib/Target/ARM/ARMBaseInstrInfo.h index 2ff4b1100ee24..d375f40d6e147 100644 --- a/lib/Target/ARM/ARMBaseInstrInfo.h +++ b/lib/Target/ARM/ARMBaseInstrInfo.h @@ -47,10 +47,10 @@ class ARMBaseInstrInfo : public ARMGenInstrInfo { /// and \p DefIdx. /// \p [out] InputRegs of the equivalent REG_SEQUENCE. Each element of /// the list is modeled as . - /// E.g., REG_SEQUENCE vreg1:sub1, sub0, vreg2, sub1 would produce + /// E.g., REG_SEQUENCE %1:sub1, sub0, %2, sub1 would produce /// two elements: - /// - vreg1:sub1, sub0 - /// - vreg2<:0>, sub1 + /// - %1:sub1, sub0 + /// - %2<:0>, sub1 /// /// \returns true if it is possible to build such an input sequence /// with the pair \p MI, \p DefIdx. False otherwise. @@ -63,8 +63,8 @@ class ARMBaseInstrInfo : public ARMGenInstrInfo { /// Build the equivalent inputs of a EXTRACT_SUBREG for the given \p MI /// and \p DefIdx. /// \p [out] InputReg of the equivalent EXTRACT_SUBREG. - /// E.g., EXTRACT_SUBREG vreg1:sub1, sub0, sub1 would produce: - /// - vreg1:sub1, sub0 + /// E.g., EXTRACT_SUBREG %1:sub1, sub0, sub1 would produce: + /// - %1:sub1, sub0 /// /// \returns true if it is possible to build such an input sequence /// with the pair \p MI, \p DefIdx. False otherwise. @@ -77,9 +77,9 @@ class ARMBaseInstrInfo : public ARMGenInstrInfo { /// and \p DefIdx. /// \p [out] BaseReg and \p [out] InsertedReg contain /// the equivalent inputs of INSERT_SUBREG. - /// E.g., INSERT_SUBREG vreg0:sub0, vreg1:sub1, sub3 would produce: - /// - BaseReg: vreg0:sub0 - /// - InsertedReg: vreg1:sub1, sub3 + /// E.g., INSERT_SUBREG %0:sub0, %1:sub1, sub3 would produce: + /// - BaseReg: %0:sub0 + /// - InsertedReg: %1:sub1, sub3 /// /// \returns true if it is possible to build such an input sequence /// with the pair \p MI, \p DefIdx. False otherwise. diff --git a/lib/Target/ARM/ARMCallLowering.cpp b/lib/Target/ARM/ARMCallLowering.cpp index 1c2df39d05a12..7338ac8bcb5e8 100644 --- a/lib/Target/ARM/ARMCallLowering.cpp +++ b/lib/Target/ARM/ARMCallLowering.cpp @@ -434,9 +434,12 @@ bool ARMCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder, auto &MBB = MIRBuilder.getMBB(); auto DL = MF.getDataLayout(); - for (auto &Arg : F.args()) + for (auto &Arg : F.args()) { if (!isSupportedType(DL, TLI, Arg.getType())) return false; + if (Arg.hasByValOrInAllocaAttr()) + return false; + } CCAssignFn *AssignFn = TLI.CCAssignFnForCall(F.getCallingConv(), F.isVarArg()); @@ -529,6 +532,9 @@ bool ARMCallLowering::lowerCall(MachineIRBuilder &MIRBuilder, if (!Arg.IsFixed) return false; + if (Arg.Flags.isByVal()) + return false; + SmallVector Regs; splitToValueTypes(Arg, ArgInfos, MF, [&](unsigned Reg, uint64_t Offset) { Regs.push_back(Reg); diff --git a/lib/Target/ARM/ARMConstantIslandPass.cpp b/lib/Target/ARM/ARMConstantIslandPass.cpp index bc781b26b2c43..8baee1ce281d7 100644 --- a/lib/Target/ARM/ARMConstantIslandPass.cpp +++ b/lib/Target/ARM/ARMConstantIslandPass.cpp @@ -326,7 +326,7 @@ LLVM_DUMP_METHOD void ARMConstantIslands::dumpBBs() { DEBUG({ for (unsigned J = 0, E = BBInfo.size(); J !=E; ++J) { const BasicBlockInfo &BBI = BBInfo[J]; - dbgs() << format("%08x BB#%u\t", BBI.Offset, J) + dbgs() << format("%08x %bb.%u\t", BBI.Offset, J) << " kb=" << unsigned(BBI.KnownBits) << " ua=" << unsigned(BBI.Unalign) << " pa=" << unsigned(BBI.PostAlign) @@ -1071,11 +1071,11 @@ bool ARMConstantIslands::isCPEntryInRange(MachineInstr *MI, unsigned UserOffset, const BasicBlockInfo &BBI = BBInfo[Block]; dbgs() << "User of CPE#" << CPEMI->getOperand(0).getImm() << " max delta=" << MaxDisp - << format(" insn address=%#x", UserOffset) - << " in BB#" << Block << ": " + << format(" insn address=%#x", UserOffset) << " in " + << printMBBReference(*MI->getParent()) << ": " << format("%#x-%x\t", BBI.Offset, BBI.postOffset()) << *MI << format("CPE address=%#x offset=%+d: ", CPEOffset, - int(CPEOffset-UserOffset)); + int(CPEOffset - UserOffset)); }); } @@ -1261,7 +1261,7 @@ bool ARMConstantIslands::findAvailableWater(CPUser &U, unsigned UserOffset, // This is the least amount of required padding seen so far. BestGrowth = Growth; WaterIter = IP; - DEBUG(dbgs() << "Found water after BB#" << WaterBB->getNumber() + DEBUG(dbgs() << "Found water after " << printMBBReference(*WaterBB) << " Growth=" << Growth << '\n'); if (CloserWater && WaterBB == U.MI->getParent()) @@ -1305,8 +1305,8 @@ void ARMConstantIslands::createNewWater(unsigned CPUserIndex, unsigned CPEOffset = UserBBI.postOffset(CPELogAlign) + Delta; if (isOffsetInRange(UserOffset, CPEOffset, U)) { - DEBUG(dbgs() << "Split at end of BB#" << UserMBB->getNumber() - << format(", expected CPE offset %#x\n", CPEOffset)); + DEBUG(dbgs() << "Split at end of " << printMBBReference(*UserMBB) + << format(", expected CPE offset %#x\n", CPEOffset)); NewMBB = &*++UserMBB->getIterator(); // Add an unconditional branch from UserMBB to fallthrough block. Record // it for branch lengthening; this new branch will not get out of range, @@ -1578,11 +1578,11 @@ bool ARMConstantIslands::isBBInRange(MachineInstr *MI,MachineBasicBlock *DestBB, unsigned BrOffset = getOffsetOf(MI) + PCAdj; unsigned DestOffset = BBInfo[DestBB->getNumber()].Offset; - DEBUG(dbgs() << "Branch of destination BB#" << DestBB->getNumber() - << " from BB#" << MI->getParent()->getNumber() - << " max delta=" << MaxDisp - << " from " << getOffsetOf(MI) << " to " << DestOffset - << " offset " << int(DestOffset-BrOffset) << "\t" << *MI); + DEBUG(dbgs() << "Branch of destination " << printMBBReference(*DestBB) + << " from " << printMBBReference(*MI->getParent()) + << " max delta=" << MaxDisp << " from " << getOffsetOf(MI) + << " to " << DestOffset << " offset " + << int(DestOffset - BrOffset) << "\t" << *MI); if (BrOffset <= DestOffset) { // Branch before the Dest. @@ -1700,9 +1700,9 @@ ARMConstantIslands::fixupConditionalBr(ImmBranch &Br) { } MachineBasicBlock *NextBB = &*++MBB->getIterator(); - DEBUG(dbgs() << " Insert B to BB#" << DestBB->getNumber() - << " also invert condition and change dest. to BB#" - << NextBB->getNumber() << "\n"); + DEBUG(dbgs() << " Insert B to " << printMBBReference(*DestBB) + << " also invert condition and change dest. to " + << printMBBReference(*NextBB) << "\n"); // Insert a new conditional branch and a new unconditional branch. // Also update the ImmBranch as well as adding a new entry for the new branch. @@ -2212,7 +2212,7 @@ bool ARMConstantIslands::optimizeThumb2JumpTables() { .addReg(IdxReg, getKillRegState(IdxRegKill)) .addJumpTableIndex(JTI, JTOP.getTargetFlags()) .addImm(CPEMI->getOperand(0).getImm()); - DEBUG(dbgs() << "BB#" << MBB->getNumber() << ": " << *NewJTMI); + DEBUG(dbgs() << printMBBReference(*MBB) << ": " << *NewJTMI); unsigned JTOpc = ByteOk ? ARM::JUMPTABLE_TBB : ARM::JUMPTABLE_TBH; CPEMI->setDesc(TII->get(JTOpc)); diff --git a/lib/Target/ARM/ARMConstantPoolValue.cpp b/lib/Target/ARM/ARMConstantPoolValue.cpp index 38ea835fbe2fe..39ae02af513b6 100644 --- a/lib/Target/ARM/ARMConstantPoolValue.cpp +++ b/lib/Target/ARM/ARMConstantPoolValue.cpp @@ -292,6 +292,6 @@ void ARMConstantPoolMBB::addSelectionDAGCSEId(FoldingSetNodeID &ID) { } void ARMConstantPoolMBB::print(raw_ostream &O) const { - O << "BB#" << MBB->getNumber(); + O << printMBBReference(*MBB); ARMConstantPoolValue::print(O); } diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index cee274080b2bf..1726d6bcb3049 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -2282,6 +2282,13 @@ ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee, assert(Subtarget->supportsTailCall()); + // Tail calls to function pointers cannot be optimized for Thumb1 if the args + // to the call take up r0-r3. The reason is that there are no legal registers + // left to hold the pointer to the function to be called. + if (Subtarget->isThumb1Only() && Outs.size() >= 4 && + !isa(Callee.getNode())) + return false; + // Look for obvious safe cases to perform tail call optimization that do not // require ABI changes. This is what gcc calls sibcall. @@ -2956,6 +2963,10 @@ ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA, SDValue ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const { + GlobalAddressSDNode *GA = cast(Op); + if (DAG.getTarget().Options.EmulatedTLS) + return LowerToTLSEmulatedModel(GA, DAG); + if (Subtarget->isTargetDarwin()) return LowerGlobalTLSAddressDarwin(Op, DAG); @@ -2964,10 +2975,6 @@ ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const { // TODO: implement the "local dynamic" model assert(Subtarget->isTargetELF() && "Only ELF implemented here"); - GlobalAddressSDNode *GA = cast(Op); - if (DAG.getTarget().Options.EmulatedTLS) - return LowerToTLSEmulatedModel(GA, DAG); - TLSModel::Model model = getTargetMachine().getTLSModel(GA->getGlobal()); switch (model) { diff --git a/lib/Target/ARM/ARMInstructionSelector.cpp b/lib/Target/ARM/ARMInstructionSelector.cpp index 6bbeae2e11514..b43faf4903a85 100644 --- a/lib/Target/ARM/ARMInstructionSelector.cpp +++ b/lib/Target/ARM/ARMInstructionSelector.cpp @@ -801,12 +801,6 @@ bool ARMInstructionSelector::select(MachineInstr &I, return selectGlobal(MIB, MRI); case G_STORE: case G_LOAD: { - const auto &MemOp = **I.memoperands_begin(); - if (MemOp.getOrdering() != AtomicOrdering::NotAtomic) { - DEBUG(dbgs() << "Atomic load/store not supported yet\n"); - return false; - } - unsigned Reg = I.getOperand(0).getReg(); unsigned RegBank = RBI.getRegBank(Reg, MRI, TRI)->getID(); diff --git a/lib/Target/ARM/ARMLegalizerInfo.cpp b/lib/Target/ARM/ARMLegalizerInfo.cpp index 51eae325c952e..6a541991adb47 100644 --- a/lib/Target/ARM/ARMLegalizerInfo.cpp +++ b/lib/Target/ARM/ARMLegalizerInfo.cpp @@ -177,6 +177,15 @@ ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) { for (auto Ty : {s32, s64}) setAction({Op, Ty}, Libcall); + // Merge/Unmerge + for (const auto &Ty : {s32, s64}) { + setAction({G_MERGE_VALUES, Ty}, Legal); + setAction({G_UNMERGE_VALUES, 1, Ty}, Legal); + } + for (const auto &Ty : {s16, s32}) { + setAction({G_MERGE_VALUES, 1, Ty}, Legal); + setAction({G_UNMERGE_VALUES, Ty}, Legal); + } computeTables(); } diff --git a/lib/Target/BPF/BPFISelDAGToDAG.cpp b/lib/Target/BPF/BPFISelDAGToDAG.cpp index 1c12c23c93128..283359c8b23a0 100644 --- a/lib/Target/BPF/BPFISelDAGToDAG.cpp +++ b/lib/Target/BPF/BPFISelDAGToDAG.cpp @@ -546,8 +546,7 @@ void BPFDAGToDAGISel::PreprocessTrunc(SDNode *Node, if (!RegN || !TargetRegisterInfo::isVirtualRegister(RegN->getReg())) return; unsigned AndOpReg = RegN->getReg(); - DEBUG(dbgs() << "Examine %vreg" << TargetRegisterInfo::virtReg2Index(AndOpReg) - << '\n'); + DEBUG(dbgs() << "Examine " << printReg(AndOpReg) << '\n'); // Examine the PHI insns in the MachineBasicBlock to found out the // definitions of this virtual register. At this stage (DAG2DAG @@ -574,10 +573,10 @@ void BPFDAGToDAGISel::PreprocessTrunc(SDNode *Node, return; } else { // The PHI node looks like: - // %vreg2 = PHI %vreg0, , %vreg1, - // Trace each incoming definition, e.g., (%vreg0, BB#1) and (%vreg1, BB#3) - // The AND operation can be removed if both %vreg0 in BB#1 and %vreg1 in - // BB#3 are defined with with a load matching the MaskN. + // %2 = PHI %0, <%bb.1>, %1, <%bb.3> + // Trace each incoming definition, e.g., (%0, %bb.1) and (%1, %bb.3) + // The AND operation can be removed if both %0 in %bb.1 and %1 in + // %bb.3 are defined with with a load matching the MaskN. DEBUG(dbgs() << "Check PHI Insn: "; MII->dump(); dbgs() << '\n'); unsigned PrevReg = -1; for (unsigned i = 0; i < MII->getNumOperands(); ++i) { diff --git a/lib/Target/Hexagon/BitTracker.cpp b/lib/Target/Hexagon/BitTracker.cpp index 5e20d8ca0fdb5..a8b8999027780 100644 --- a/lib/Target/Hexagon/BitTracker.cpp +++ b/lib/Target/Hexagon/BitTracker.cpp @@ -18,16 +18,16 @@ // A "ref" value is associated with a BitRef structure, which indicates // which virtual register, and which bit in that register is the origin // of the value. For example, given an instruction -// vreg2 = ASL vreg1, 1 -// assuming that nothing is known about bits of vreg1, bit 1 of vreg2 -// will be a "ref" to (vreg1, 0). If there is a subsequent instruction -// vreg3 = ASL vreg2, 2 -// then bit 3 of vreg3 will be a "ref" to (vreg1, 0) as well. +// %2 = ASL %1, 1 +// assuming that nothing is known about bits of %1, bit 1 of %2 +// will be a "ref" to (%1, 0). If there is a subsequent instruction +// %3 = ASL %2, 2 +// then bit 3 of %3 will be a "ref" to (%1, 0) as well. // The "bottom" case means that the bit's value cannot be determined, // and that this virtual register actually defines it. The "bottom" case // is discussed in detail in BitTracker.h. In fact, "bottom" is a "ref -// to self", so for the vreg1 above, the bit 0 of it will be a "ref" to -// (vreg1, 0), bit 1 will be a "ref" to (vreg1, 1), etc. +// to self", so for the %1 above, the bit 0 of it will be a "ref" to +// (%1, 0), bit 1 will be a "ref" to (%1, 1), etc. // // The tracker implements the Wegman-Zadeck algorithm, originally developed // for SSA-based constant propagation. Each register is represented as @@ -75,7 +75,7 @@ using BT = BitTracker; namespace { - // Local trickery to pretty print a register (without the whole "%vreg" + // Local trickery to pretty print a register (without the whole "%number" // business). struct printv { printv(unsigned r) : R(r) {} @@ -767,7 +767,7 @@ bool BT::MachineEvaluator::evaluate(const MachineInstr &MI, void BT::visitPHI(const MachineInstr &PI) { int ThisN = PI.getParent()->getNumber(); if (Trace) - dbgs() << "Visit FI(BB#" << ThisN << "): " << PI; + dbgs() << "Visit FI(" << printMBBReference(*PI.getParent()) << "): " << PI; const MachineOperand &MD = PI.getOperand(0); assert(MD.getSubReg() == 0 && "Unexpected sub-register in definition"); @@ -784,7 +784,8 @@ void BT::visitPHI(const MachineInstr &PI) { const MachineBasicBlock *PB = PI.getOperand(i + 1).getMBB(); int PredN = PB->getNumber(); if (Trace) - dbgs() << " edge BB#" << PredN << "->BB#" << ThisN; + dbgs() << " edge " << printMBBReference(*PB) << "->" + << printMBBReference(*PI.getParent()); if (!EdgeExec.count(CFGEdge(PredN, ThisN))) { if (Trace) dbgs() << " not executable\n"; @@ -809,10 +810,8 @@ void BT::visitPHI(const MachineInstr &PI) { } void BT::visitNonBranch(const MachineInstr &MI) { - if (Trace) { - int ThisN = MI.getParent()->getNumber(); - dbgs() << "Visit MI(BB#" << ThisN << "): " << MI; - } + if (Trace) + dbgs() << "Visit MI(" << printMBBReference(*MI.getParent()) << "): " << MI; if (MI.isDebugValue()) return; assert(!MI.isBranch() && "Unexpected branch instruction"); @@ -897,7 +896,7 @@ void BT::visitBranchesFrom(const MachineInstr &BI) { BTs.clear(); const MachineInstr &MI = *It; if (Trace) - dbgs() << "Visit BR(BB#" << ThisN << "): " << MI; + dbgs() << "Visit BR(" << printMBBReference(B) << "): " << MI; assert(MI.isBranch() && "Expecting branch instruction"); InstrExec.insert(&MI); bool Eval = ME.evaluate(MI, Map, BTs, FallsThrough); @@ -913,7 +912,7 @@ void BT::visitBranchesFrom(const MachineInstr &BI) { if (Trace) { dbgs() << " adding targets:"; for (unsigned i = 0, n = BTs.size(); i < n; ++i) - dbgs() << " BB#" << BTs[i]->getNumber(); + dbgs() << " " << printMBBReference(*BTs[i]); if (FallsThrough) dbgs() << "\n falls through\n"; else diff --git a/lib/Target/Hexagon/HexagonBitSimplify.cpp b/lib/Target/Hexagon/HexagonBitSimplify.cpp index cbf1b0dc040a5..f14beaad339a9 100644 --- a/lib/Target/Hexagon/HexagonBitSimplify.cpp +++ b/lib/Target/Hexagon/HexagonBitSimplify.cpp @@ -895,7 +895,7 @@ bool HexagonBitSimplify::getUsedBits(unsigned Opc, unsigned OpN, } // Calculate the register class that matches Reg:Sub. For example, if -// vreg1 is a double register, then vreg1:isub_hi would match the "int" +// %1 is a double register, then %1:isub_hi would match the "int" // register class. const TargetRegisterClass *HexagonBitSimplify::getFinalVRegClass( const BitTracker::RegisterRef &RR, MachineRegisterInfo &MRI) { @@ -1246,11 +1246,11 @@ bool RedundantInstrElimination::computeUsedBits(unsigned Reg, BitVector &Bits) { // holds the bits for the entire register. To keep track of that, the // argument Begin indicates where in Bits is the lowest-significant bit // of the register used in operand OpN. For example, in instruction: -// vreg1 = S2_lsr_i_r vreg2:isub_hi, 10 +// %1 = S2_lsr_i_r %2:isub_hi, 10 // the operand 1 is a 32-bit register, which happens to be a subregister -// of the 64-bit register vreg2, and that subregister starts at position 32. +// of the 64-bit register %2, and that subregister starts at position 32. // In this case Begin=32, since Bits[32] would be the lowest-significant bit -// of vreg2:isub_hi. +// of %2:isub_hi. bool RedundantInstrElimination::computeUsedBits(const MachineInstr &MI, unsigned OpN, BitVector &Bits, uint16_t Begin) { unsigned Opc = MI.getOpcode(); @@ -1356,11 +1356,11 @@ bool RedundantInstrElimination::processBlock(MachineBasicBlock &B, // This pass can create copies between registers that don't have the // exact same values. Updating the tracker has to involve updating // all dependent cells. Example: - // vreg1 = inst vreg2 ; vreg1 != vreg2, but used bits are equal + // %1 = inst %2 ; %1 != %2, but used bits are equal // - // vreg3 = copy vreg2 ; <- inserted - // ... = vreg3 ; <- replaced from vreg2 - // Indirectly, we can create a "copy" between vreg1 and vreg2 even + // %3 = copy %2 ; <- inserted + // ... = %3 ; <- replaced from %2 + // Indirectly, we can create a "copy" between %1 and %2 even // though their exact values do not match. BT.visit(*CopyI); Changed = true; @@ -2313,10 +2313,10 @@ bool BitSimplification::genBitSplit(MachineInstr *MI, // Check for tstbit simplification opportunity, where the bit being checked // can be tracked back to another register. For example: -// vreg2 = S2_lsr_i_r vreg1, 5 -// vreg3 = S2_tstbit_i vreg2, 0 +// %2 = S2_lsr_i_r %1, 5 +// %3 = S2_tstbit_i %2, 0 // => -// vreg3 = S2_tstbit_i vreg1, 5 +// %3 = S2_tstbit_i %1, 5 bool BitSimplification::simplifyTstbit(MachineInstr *MI, BitTracker::RegisterRef RD, const BitTracker::RegisterCell &RC) { unsigned Opc = MI->getOpcode(); @@ -2977,7 +2977,7 @@ void HexagonLoopRescheduling::moveGroup(InstrGroup &G, MachineBasicBlock &LB, } bool HexagonLoopRescheduling::processLoop(LoopCand &C) { - DEBUG(dbgs() << "Processing loop in BB#" << C.LB->getNumber() << "\n"); + DEBUG(dbgs() << "Processing loop in " << printMBBReference(*C.LB) << "\n"); std::vector Phis; for (auto &I : *C.LB) { if (!I.isPHI()) diff --git a/lib/Target/Hexagon/HexagonBlockRanges.cpp b/lib/Target/Hexagon/HexagonBlockRanges.cpp index 9ca7e5f0a3c4c..1953439fc3e7c 100644 --- a/lib/Target/Hexagon/HexagonBlockRanges.cpp +++ b/lib/Target/Hexagon/HexagonBlockRanges.cpp @@ -368,7 +368,7 @@ void HexagonBlockRanges::computeInitialLiveRanges(InstrIndexMap &IndexMap, } } // Defs and clobbers can overlap, e.g. - // %d0 = COPY %vreg5, %r0, %r1 + // %d0 = COPY %5, %r0, %r1 for (RegisterRef R : Defs) Clobbers.erase(R); diff --git a/lib/Target/Hexagon/HexagonConstPropagation.cpp b/lib/Target/Hexagon/HexagonConstPropagation.cpp index e7c3290d151d3..80db36071db98 100644 --- a/lib/Target/Hexagon/HexagonConstPropagation.cpp +++ b/lib/Target/Hexagon/HexagonConstPropagation.cpp @@ -617,7 +617,7 @@ void MachineConstPropagator::CellMap::print(raw_ostream &os, void MachineConstPropagator::visitPHI(const MachineInstr &PN) { const MachineBasicBlock *MB = PN.getParent(); unsigned MBN = MB->getNumber(); - DEBUG(dbgs() << "Visiting FI(BB#" << MBN << "): " << PN); + DEBUG(dbgs() << "Visiting FI(" << printMBBReference(*MB) << "): " << PN); const MachineOperand &MD = PN.getOperand(0); Register DefR(MD); @@ -642,8 +642,8 @@ void MachineConstPropagator::visitPHI(const MachineInstr &PN) { const MachineBasicBlock *PB = PN.getOperand(i+1).getMBB(); unsigned PBN = PB->getNumber(); if (!EdgeExec.count(CFGEdge(PBN, MBN))) { - DEBUG(dbgs() << " edge BB#" << PBN << "->BB#" << MBN - << " not executable\n"); + DEBUG(dbgs() << " edge " << printMBBReference(*PB) << "->" + << printMBBReference(*MB) << " not executable\n"); continue; } const MachineOperand &SO = PN.getOperand(i); @@ -658,9 +658,8 @@ void MachineConstPropagator::visitPHI(const MachineInstr &PN) { LatticeCell SrcC; bool Eval = MCE.evaluate(UseR, Cells.get(UseR.Reg), SrcC); - DEBUG(dbgs() << " edge from BB#" << PBN << ": " - << printReg(UseR.Reg, &MCE.TRI, UseR.SubReg) - << SrcC << '\n'); + DEBUG(dbgs() << " edge from " << printMBBReference(*PB) << ": " + << printReg(UseR.Reg, &MCE.TRI, UseR.SubReg) << SrcC << '\n'); Changed |= Eval ? DefC.meet(SrcC) : DefC.setBottom(); Cells.update(DefR.Reg, DefC); @@ -672,7 +671,7 @@ void MachineConstPropagator::visitPHI(const MachineInstr &PN) { } void MachineConstPropagator::visitNonBranch(const MachineInstr &MI) { - DEBUG(dbgs() << "Visiting MI(BB#" << MI.getParent()->getNumber() + DEBUG(dbgs() << "Visiting MI(" << printMBBReference(*MI.getParent()) << "): " << MI); CellMap Outputs; bool Eval = MCE.evaluate(MI, Cells, Outputs); @@ -729,8 +728,8 @@ void MachineConstPropagator::visitBranchesFrom(const MachineInstr &BrI) { while (It != End) { const MachineInstr &MI = *It; InstrExec.insert(&MI); - DEBUG(dbgs() << "Visiting " << (EvalOk ? "BR" : "br") << "(BB#" - << MBN << "): " << MI); + DEBUG(dbgs() << "Visiting " << (EvalOk ? "BR" : "br") << "(" + << printMBBReference(B) << "): " << MI); // Do not evaluate subsequent branches if the evaluation of any of the // previous branches failed. Keep iterating over the branches only // to mark them as executable. @@ -772,7 +771,8 @@ void MachineConstPropagator::visitBranchesFrom(const MachineInstr &BrI) { for (const MachineBasicBlock *TB : Targets) { unsigned TBN = TB->getNumber(); - DEBUG(dbgs() << " pushing edge BB#" << MBN << " -> BB#" << TBN << "\n"); + DEBUG(dbgs() << " pushing edge " << printMBBReference(B) << " -> " + << printMBBReference(*TB) << "\n"); FlowQ.push(CFGEdge(MBN, TBN)); } } @@ -870,8 +870,10 @@ void MachineConstPropagator::propagate(MachineFunction &MF) { CFGEdge Edge = FlowQ.front(); FlowQ.pop(); - DEBUG(dbgs() << "Picked edge BB#" << Edge.first << "->BB#" - << Edge.second << '\n'); + DEBUG(dbgs() << "Picked edge " + << printMBBReference(*MF.getBlockNumbered(Edge.first)) << "->" + << printMBBReference(*MF.getBlockNumbered(Edge.second)) + << '\n'); if (Edge.first != EntryNum) if (EdgeExec.count(Edge)) continue; @@ -934,7 +936,8 @@ void MachineConstPropagator::propagate(MachineFunction &MF) { for (const MachineBasicBlock *SB : B.successors()) { unsigned SN = SB->getNumber(); if (!EdgeExec.count(CFGEdge(BN, SN))) - dbgs() << " BB#" << BN << " -> BB#" << SN << '\n'; + dbgs() << " " << printMBBReference(B) << " -> " + << printMBBReference(*SB) << '\n'; } } }); @@ -1974,7 +1977,7 @@ bool HexagonConstEvaluator::evaluate(const MachineInstr &MI, { const MachineOperand &VO = MI.getOperand(1); // The operand of CONST32 can be a blockaddress, e.g. - // %vreg0 = CONST32 + // %0 = CONST32 // Do this check for all instructions for safety. if (!VO.isImm()) return false; @@ -3126,7 +3129,7 @@ bool HexagonConstEvaluator::rewriteHexBranch(MachineInstr &BrI, if (BrI.getOpcode() == Hexagon::J2_jump) return false; - DEBUG(dbgs() << "Rewrite(BB#" << B.getNumber() << "):" << BrI); + DEBUG(dbgs() << "Rewrite(" << printMBBReference(B) << "):" << BrI); bool Rewritten = false; if (NumTargets > 0) { assert(!FallsThru && "This should have been checked before"); diff --git a/lib/Target/Hexagon/HexagonEarlyIfConv.cpp b/lib/Target/Hexagon/HexagonEarlyIfConv.cpp index b2244107ac437..652ea13c414ef 100644 --- a/lib/Target/Hexagon/HexagonEarlyIfConv.cpp +++ b/lib/Target/Hexagon/HexagonEarlyIfConv.cpp @@ -25,39 +25,39 @@ // // Example: // -// %vreg40 = L2_loadrub_io %vreg39, 1 -// %vreg41 = S2_tstbit_i %vreg40, 0 -// J2_jumpt %vreg41, , %pc -// J2_jump , %pc -// Successors according to CFG: BB#4(62) BB#5(62) +// %40 = L2_loadrub_io %39, 1 +// %41 = S2_tstbit_i %40, 0 +// J2_jumpt %41, <%bb.5>, %pc +// J2_jump <%bb.4>, %pc +// Successors according to CFG: %bb.4(62) %bb.5(62) // -// BB#4: derived from LLVM BB %if.then -// Predecessors according to CFG: BB#3 -// %vreg11 = A2_addp %vreg6, %vreg10 -// S2_storerd_io %vreg32, 16, %vreg11 -// Successors according to CFG: BB#5 +// %bb.4: derived from LLVM BB %if.then +// Predecessors according to CFG: %bb.3 +// %11 = A2_addp %6, %10 +// S2_storerd_io %32, 16, %11 +// Successors according to CFG: %bb.5 // -// BB#5: derived from LLVM BB %if.end -// Predecessors according to CFG: BB#3 BB#4 -// %vreg12 = PHI %vreg6, , %vreg11, -// %vreg13 = A2_addp %vreg7, %vreg12 -// %vreg42 = C2_cmpeqi %vreg9, 10 -// J2_jumpf %vreg42, , %pc -// J2_jump , %pc -// Successors according to CFG: BB#6(4) BB#3(124) +// %bb.5: derived from LLVM BB %if.end +// Predecessors according to CFG: %bb.3 %bb.4 +// %12 = PHI %6, <%bb.3>, %11, <%bb.4> +// %13 = A2_addp %7, %12 +// %42 = C2_cmpeqi %9, 10 +// J2_jumpf %42, <%bb.3>, %pc +// J2_jump <%bb.6>, %pc +// Successors according to CFG: %bb.6(4) %bb.3(124) // // would become: // -// %vreg40 = L2_loadrub_io %vreg39, 1 -// %vreg41 = S2_tstbit_i %vreg40, 0 -// spec-> %vreg11 = A2_addp %vreg6, %vreg10 -// pred-> S2_pstorerdf_io %vreg41, %vreg32, 16, %vreg11 -// %vreg46 = PS_pselect %vreg41, %vreg6, %vreg11 -// %vreg13 = A2_addp %vreg7, %vreg46 -// %vreg42 = C2_cmpeqi %vreg9, 10 -// J2_jumpf %vreg42, , %pc -// J2_jump , %pc -// Successors according to CFG: BB#6 BB#3 +// %40 = L2_loadrub_io %39, 1 +// %41 = S2_tstbit_i %40, 0 +// spec-> %11 = A2_addp %6, %10 +// pred-> S2_pstorerdf_io %41, %32, 16, %11 +// %46 = PS_pselect %41, %6, %11 +// %13 = A2_addp %7, %46 +// %42 = C2_cmpeqi %9, 10 +// J2_jumpf %42, <%bb.3>, %pc +// J2_jump <%bb.6>, %pc +// Successors according to CFG: %bb.6 %bb.3 #include "Hexagon.h" #include "HexagonInstrInfo.h" @@ -238,7 +238,7 @@ bool HexagonEarlyIfConversion::isPreheader(const MachineBasicBlock *B) const { bool HexagonEarlyIfConversion::matchFlowPattern(MachineBasicBlock *B, MachineLoop *L, FlowPattern &FP) { - DEBUG(dbgs() << "Checking flow pattern at BB#" << B->getNumber() << "\n"); + DEBUG(dbgs() << "Checking flow pattern at " << printMBBReference(*B) << "\n"); // Interested only in conditional branches, no .new, no new-value, etc. // Check the terminators directly, it's easier than handling all responses diff --git a/lib/Target/Hexagon/HexagonExpandCondsets.cpp b/lib/Target/Hexagon/HexagonExpandCondsets.cpp index 51c3b78437006..78c7c102e7d45 100644 --- a/lib/Target/Hexagon/HexagonExpandCondsets.cpp +++ b/lib/Target/Hexagon/HexagonExpandCondsets.cpp @@ -17,33 +17,33 @@ // // Liveness tracking aside, the main functionality of this pass is divided // into two steps. The first step is to replace an instruction -// vreg0 = C2_mux vreg1, vreg2, vreg3 +// %0 = C2_mux %1, %2, %3 // with a pair of conditional transfers -// vreg0 = A2_tfrt vreg1, vreg2 -// vreg0 = A2_tfrf vreg1, vreg3 +// %0 = A2_tfrt %1, %2 +// %0 = A2_tfrf %1, %3 // It is the intention that the execution of this pass could be terminated // after this step, and the code generated would be functionally correct. // -// If the uses of the source values vreg1 and vreg2 are kills, and their +// If the uses of the source values %1 and %2 are kills, and their // definitions are predicable, then in the second step, the conditional // transfers will then be rewritten as predicated instructions. E.g. -// vreg0 = A2_or vreg1, vreg2 -// vreg3 = A2_tfrt vreg99, vreg0 +// %0 = A2_or %1, %2 +// %3 = A2_tfrt %99, %0 // will be rewritten as -// vreg3 = A2_port vreg99, vreg1, vreg2 +// %3 = A2_port %99, %1, %2 // // This replacement has two variants: "up" and "down". Consider this case: -// vreg0 = A2_or vreg1, vreg2 +// %0 = A2_or %1, %2 // ... [intervening instructions] ... -// vreg3 = A2_tfrt vreg99, vreg0 +// %3 = A2_tfrt %99, %0 // variant "up": -// vreg3 = A2_port vreg99, vreg1, vreg2 -// ... [intervening instructions, vreg0->vreg3] ... +// %3 = A2_port %99, %1, %2 +// ... [intervening instructions, %0->vreg3] ... // [deleted] // variant "down": // [deleted] // ... [intervening instructions] ... -// vreg3 = A2_port vreg99, vreg1, vreg2 +// %3 = A2_port %99, %1, %2 // // Both, one or none of these variants may be valid, and checks are made // to rule out inapplicable variants. @@ -51,13 +51,13 @@ // As an additional optimization, before either of the two steps above is // executed, the pass attempts to coalesce the target register with one of // the source registers, e.g. given an instruction -// vreg3 = C2_mux vreg0, vreg1, vreg2 -// vreg3 will be coalesced with either vreg1 or vreg2. If this succeeds, +// %3 = C2_mux %0, %1, %2 +// %3 will be coalesced with either %1 or %2. If this succeeds, // the instruction would then be (for example) -// vreg3 = C2_mux vreg0, vreg3, vreg2 +// %3 = C2_mux %0, %3, %2 // and, under certain circumstances, this could result in only one predicated // instruction: -// vreg3 = A2_tfrf vreg0, vreg2 +// %3 = A2_tfrf %0, %2 // // Splitting a definition of a register into two predicated transfers @@ -65,18 +65,18 @@ // will see both instructions as actual definitions, and will mark the // first one as dead. The definition is not actually dead, and this // situation will need to be fixed. For example: -// vreg1 = A2_tfrt ... ; marked as dead -// vreg1 = A2_tfrf ... +// %1 = A2_tfrt ... ; marked as dead +// %1 = A2_tfrf ... // // Since any of the individual predicated transfers may end up getting // removed (in case it is an identity copy), some pre-existing def may // be marked as dead after live interval recomputation: -// vreg1 = ... ; marked as dead +// %1 = ... ; marked as dead // ... -// vreg1 = A2_tfrf ... ; if A2_tfrt is removed -// This case happens if vreg1 was used as a source in A2_tfrt, which means +// %1 = A2_tfrf ... ; if A2_tfrt is removed +// This case happens if %1 was used as a source in A2_tfrt, which means // that is it actually live at the A2_tfrf, and so the now dead definition -// of vreg1 will need to be updated to non-dead at some point. +// of %1 will need to be updated to non-dead at some point. // // This issue could be remedied by adding implicit uses to the predicated // transfers, but this will create a problem with subsequent predication, @@ -654,7 +654,7 @@ bool HexagonExpandCondsets::split(MachineInstr &MI, return false; TfrCounter++; } - DEBUG(dbgs() << "\nsplitting BB#" << MI.getParent()->getNumber() << ": " + DEBUG(dbgs() << "\nsplitting " << printMBBReference(*MI.getParent()) << ": " << MI); MachineOperand &MD = MI.getOperand(0); // Definition MachineOperand &MP = MI.getOperand(1); // Predicate register @@ -760,8 +760,8 @@ MachineInstr *HexagonExpandCondsets::getReachingDefForPred(RegisterRef RD, if (RR.Reg != RD.Reg) continue; // If the "Reg" part agrees, there is still the subregister to check. - // If we are looking for vreg1:loreg, we can skip vreg1:hireg, but - // not vreg1 (w/o subregisters). + // If we are looking for %1:loreg, we can skip %1:hireg, but + // not %1 (w/o subregisters). if (RR.Sub == RD.Sub) return MI; if (RR.Sub == 0 || RD.Sub == 0) @@ -1071,7 +1071,7 @@ bool HexagonExpandCondsets::predicateInBlock(MachineBasicBlock &B, bool Done = predicate(*I, (Opc == Hexagon::A2_tfrt), UpdRegs); if (!Done) { // If we didn't predicate I, we may need to remove it in case it is - // an "identity" copy, e.g. vreg1 = A2_tfrt vreg2, vreg1. + // an "identity" copy, e.g. %1 = A2_tfrt %2, %1. if (RegisterRef(I->getOperand(0)) == RegisterRef(I->getOperand(2))) { for (auto &Op : I->operands()) if (Op.isReg()) @@ -1198,18 +1198,18 @@ bool HexagonExpandCondsets::coalesceSegments( MachineOperand &S1 = CI->getOperand(2), &S2 = CI->getOperand(3); bool Done = false; // Consider this case: - // vreg1 = instr1 ... - // vreg2 = instr2 ... - // vreg0 = C2_mux ..., vreg1, vreg2 - // If vreg0 was coalesced with vreg1, we could end up with the following + // %1 = instr1 ... + // %2 = instr2 ... + // %0 = C2_mux ..., %1, %2 + // If %0 was coalesced with %1, we could end up with the following // code: - // vreg0 = instr1 ... - // vreg2 = instr2 ... - // vreg0 = A2_tfrf ..., vreg2 + // %0 = instr1 ... + // %2 = instr2 ... + // %0 = A2_tfrf ..., %2 // which will later become: - // vreg0 = instr1 ... - // vreg0 = instr2_cNotPt ... - // i.e. there will be an unconditional definition (instr1) of vreg0 + // %0 = instr1 ... + // %0 = instr2_cNotPt ... + // i.e. there will be an unconditional definition (instr1) of %0 // followed by a conditional one. The output dependency was there before // and it unavoidable, but if instr1 is predicable, we will no longer be // able to predicate it here. diff --git a/lib/Target/Hexagon/HexagonFrameLowering.cpp b/lib/Target/Hexagon/HexagonFrameLowering.cpp index ebb7add82e161..a6a950ea045ca 100644 --- a/lib/Target/Hexagon/HexagonFrameLowering.cpp +++ b/lib/Target/Hexagon/HexagonFrameLowering.cpp @@ -443,7 +443,7 @@ void HexagonFrameLowering::findShrunkPrologEpilog(MachineFunction &MF, DEBUG({ dbgs() << "Blocks needing SF: {"; for (auto &B : SFBlocks) - dbgs() << " BB#" << B->getNumber(); + dbgs() << " " << printMBBReference(*B); dbgs() << " }\n"; }); // No frame needed? @@ -464,12 +464,16 @@ void HexagonFrameLowering::findShrunkPrologEpilog(MachineFunction &MF, break; } DEBUG({ - dbgs() << "Computed dom block: BB#"; - if (DomB) dbgs() << DomB->getNumber(); - else dbgs() << ""; - dbgs() << ", computed pdom block: BB#"; - if (PDomB) dbgs() << PDomB->getNumber(); - else dbgs() << ""; + dbgs() << "Computed dom block: "; + if (DomB) + dbgs() << printMBBReference(*DomB); + else + dbgs() << ""; + dbgs() << ", computed pdom block: "; + if (PDomB) + dbgs() << printMBBReference(*PDomB); + else + dbgs() << ""; dbgs() << "\n"; }); if (!DomB || !PDomB) @@ -2010,7 +2014,7 @@ void HexagonFrameLowering::optimizeSpillSlots(MachineFunction &MF, auto P = BlockIndexes.insert( std::make_pair(&B, HexagonBlockRanges::InstrIndexMap(B))); auto &IndexMap = P.first->second; - DEBUG(dbgs() << "Index map for BB#" << B.getNumber() << "\n" + DEBUG(dbgs() << "Index map for " << printMBBReference(B) << "\n" << IndexMap << '\n'); for (auto &In : B) { @@ -2129,7 +2133,8 @@ void HexagonFrameLowering::optimizeSpillSlots(MachineFunction &MF, else dbgs() << "\n"; for (auto &R : P.second.Map) - dbgs() << " BB#" << R.first->getNumber() << " { " << R.second << "}\n"; + dbgs() << " " << printMBBReference(*R.first) << " { " << R.second + << "}\n"; } }); @@ -2162,7 +2167,7 @@ void HexagonFrameLowering::optimizeSpillSlots(MachineFunction &MF, auto &FIs = P.second; if (FIs.empty()) continue; - dbgs() << " BB#" << P.first->getNumber() << ": {"; + dbgs() << " " << printMBBReference(*P.first) << ": {"; for (auto I : FIs) { dbgs() << " fi#" << I; if (LoxFIs.count(I)) @@ -2183,7 +2188,7 @@ void HexagonFrameLowering::optimizeSpillSlots(MachineFunction &MF, HexagonBlockRanges::InstrIndexMap &IM = F->second; HexagonBlockRanges::RegToRangeMap LM = HBR.computeLiveMap(IM); HexagonBlockRanges::RegToRangeMap DM = HBR.computeDeadMap(IM, LM); - DEBUG(dbgs() << "BB#" << B.getNumber() << " dead map\n" + DEBUG(dbgs() << printMBBReference(B) << " dead map\n" << HexagonBlockRanges::PrintRangeMap(DM, HRI)); for (auto FI : BlockFIMap[&B]) { diff --git a/lib/Target/Hexagon/HexagonGenInsert.cpp b/lib/Target/Hexagon/HexagonGenInsert.cpp index 09d3e6d4a1548..99f3a2e9e88f6 100644 --- a/lib/Target/Hexagon/HexagonGenInsert.cpp +++ b/lib/Target/Hexagon/HexagonGenInsert.cpp @@ -915,7 +915,7 @@ bool HexagonGenInsert::findRecordInsertForms(unsigned VR, void HexagonGenInsert::collectInBlock(MachineBasicBlock *B, OrderedRegisterList &AVs) { if (isDebug()) - dbgs() << "visiting block BB#" << B->getNumber() << "\n"; + dbgs() << "visiting block " << printMBBReference(*B) << "\n"; // First, check if this block is reachable at all. If not, the bit tracker // will not have any information about registers in it. @@ -1106,10 +1106,10 @@ void HexagonGenInsert::pruneCoveredSets(unsigned VR) { // Now, remove those whose sets of potentially removable registers are // contained in another IF candidate for VR. For example, given these - // candidates for vreg45, - // %vreg45: - // (%vreg44,%vreg41,#9,#8), { %vreg42 } - // (%vreg43,%vreg41,#9,#8), { %vreg42 %vreg44 } + // candidates for %45, + // %45: + // (%44,%41,#9,#8), { %42 } + // (%43,%41,#9,#8), { %42 %44 } // remove the first one, since it is contained in the second one. for (unsigned i = 0, n = LL.size(); i < n; ) { const RegisterSet &RMi = LL[i].second; diff --git a/lib/Target/Hexagon/HexagonHardwareLoops.cpp b/lib/Target/Hexagon/HexagonHardwareLoops.cpp index 56171f2214835..b5fa0689d042d 100644 --- a/lib/Target/Hexagon/HexagonHardwareLoops.cpp +++ b/lib/Target/Hexagon/HexagonHardwareLoops.cpp @@ -1011,7 +1011,7 @@ bool HexagonHardwareLoops::isInvalidLoopOperation(const MachineInstr *MI, bool HexagonHardwareLoops::containsInvalidInstruction(MachineLoop *L, bool IsInnerHWLoop) const { const std::vector &Blocks = L->getBlocks(); - DEBUG(dbgs() << "\nhw_loop head, BB#" << Blocks[0]->getNumber();); + DEBUG(dbgs() << "\nhw_loop head, " << printMBBReference(*Blocks[0])); for (unsigned i = 0, e = Blocks.size(); i != e; ++i) { MachineBasicBlock *MBB = Blocks[i]; for (MachineBasicBlock::iterator @@ -1367,7 +1367,7 @@ bool HexagonHardwareLoops::isLoopFeeder(MachineLoop *L, MachineBasicBlock *A, LoopFeederMap &LoopFeederPhi) const { if (LoopFeederPhi.find(MO->getReg()) == LoopFeederPhi.end()) { const std::vector &Blocks = L->getBlocks(); - DEBUG(dbgs() << "\nhw_loop head, BB#" << Blocks[0]->getNumber();); + DEBUG(dbgs() << "\nhw_loop head, " << printMBBReference(*Blocks[0])); // Ignore all BBs that form Loop. for (unsigned i = 0, e = Blocks.size(); i != e; ++i) { MachineBasicBlock *MBB = Blocks[i]; @@ -1622,8 +1622,8 @@ bool HexagonHardwareLoops::fixupInductionVariable(MachineLoop *L) { RegisterInductionSet IndRegs; // Look for induction patterns: - // vreg1 = PHI ..., [ latch, vreg2 ] - // vreg2 = ADD vreg1, imm + // %1 = PHI ..., [ latch, %2 ] + // %2 = ADD %1, imm using instr_iterator = MachineBasicBlock::instr_iterator; for (instr_iterator I = Header->instr_begin(), E = Header->instr_end(); @@ -1720,7 +1720,7 @@ bool HexagonHardwareLoops::fixupInductionVariable(MachineLoop *L) { MachineOperand &MO = PredDef->getOperand(i); if (MO.isReg()) { // Skip all implicit references. In one case there was: - // %vreg140 = FCMPUGT32_rr %vreg138, %vreg139, %usr + // %140 = FCMPUGT32_rr %138, %139, %usr if (MO.isImplicit()) continue; if (MO.isUse()) { diff --git a/lib/Target/Hexagon/HexagonInstrInfo.cpp b/lib/Target/Hexagon/HexagonInstrInfo.cpp index 4cdfd09c0956c..cb00bc770c09b 100644 --- a/lib/Target/Hexagon/HexagonInstrInfo.cpp +++ b/lib/Target/Hexagon/HexagonInstrInfo.cpp @@ -463,7 +463,7 @@ bool HexagonInstrInfo::analyzeBranch(MachineBasicBlock &MBB, Cond.push_back(LastInst->getOperand(1)); return false; } - DEBUG(dbgs() << "\nCant analyze BB#" << MBB.getNumber() + DEBUG(dbgs() << "\nCant analyze " << printMBBReference(MBB) << " with one jump\n";); // Otherwise, don't know what this is. return true; @@ -511,7 +511,7 @@ bool HexagonInstrInfo::analyzeBranch(MachineBasicBlock &MBB, FBB = LastInst->getOperand(0).getMBB(); return false; } - DEBUG(dbgs() << "\nCant analyze BB#" << MBB.getNumber() + DEBUG(dbgs() << "\nCant analyze " << printMBBReference(MBB) << " with two jumps";); // Otherwise, can't handle this. return true; @@ -521,7 +521,7 @@ unsigned HexagonInstrInfo::removeBranch(MachineBasicBlock &MBB, int *BytesRemoved) const { assert(!BytesRemoved && "code size not handled"); - DEBUG(dbgs() << "\nRemoving branches out of BB#" << MBB.getNumber()); + DEBUG(dbgs() << "\nRemoving branches out of " << printMBBReference(MBB)); MachineBasicBlock::iterator I = MBB.end(); unsigned Count = 0; while (I != MBB.begin()) { @@ -593,7 +593,7 @@ unsigned HexagonInstrInfo::insertBranch(MachineBasicBlock &MBB, // (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset) // (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset) unsigned Flags1 = getUndefRegState(Cond[1].isUndef()); - DEBUG(dbgs() << "\nInserting NVJump for BB#" << MBB.getNumber();); + DEBUG(dbgs() << "\nInserting NVJump for " << printMBBReference(MBB);); if (Cond[2].isReg()) { unsigned Flags2 = getUndefRegState(Cond[2].isUndef()); BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1). @@ -829,9 +829,8 @@ void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB, #ifndef NDEBUG // Show the invalid registers to ease debugging. - dbgs() << "Invalid registers for copy in BB#" << MBB.getNumber() - << ": " << printReg(DestReg, &HRI) - << " = " << printReg(SrcReg, &HRI) << '\n'; + dbgs() << "Invalid registers for copy in " << printMBBReference(MBB) << ": " + << printReg(DestReg, &HRI) << " = " << printReg(SrcReg, &HRI) << '\n'; #endif llvm_unreachable("Unimplemented"); } @@ -4032,8 +4031,9 @@ void HexagonInstrInfo::immediateExtend(MachineInstr &MI) const { bool HexagonInstrInfo::invertAndChangeJumpTarget( MachineInstr &MI, MachineBasicBlock *NewTarget) const { - DEBUG(dbgs() << "\n[invertAndChangeJumpTarget] to BB#" - << NewTarget->getNumber(); MI.dump();); + DEBUG(dbgs() << "\n[invertAndChangeJumpTarget] to " + << printMBBReference(*NewTarget); + MI.dump();); assert(MI.isBranch()); unsigned NewOpcode = getInvertedPredicatedOpcode(MI.getOpcode()); int TargetPos = MI.getNumOperands() - 1; diff --git a/lib/Target/Hexagon/HexagonMachineScheduler.cpp b/lib/Target/Hexagon/HexagonMachineScheduler.cpp index 5daceac6496d3..8765fc9844843 100644 --- a/lib/Target/Hexagon/HexagonMachineScheduler.cpp +++ b/lib/Target/Hexagon/HexagonMachineScheduler.cpp @@ -186,12 +186,10 @@ bool VLIWResourceModel::reserveResources(SUnit *SU) { /// after setting up the current scheduling region. [RegionBegin, RegionEnd) /// only includes instructions that have DAG nodes, not scheduling boundaries. void VLIWMachineScheduler::schedule() { - DEBUG(dbgs() - << "********** MI Converging Scheduling VLIW BB#" << BB->getNumber() - << " " << BB->getName() - << " in_func " << BB->getParent()->getFunction()->getName() - << " at loop depth " << MLI->getLoopDepth(BB) - << " \n"); + DEBUG(dbgs() << "********** MI Converging Scheduling VLIW " + << printMBBReference(*BB) << " " << BB->getName() << " in_func " + << BB->getParent()->getFunction()->getName() << " at loop depth " + << MLI->getLoopDepth(BB) << " \n"); buildDAGWithRegPressure(); @@ -237,8 +235,8 @@ void VLIWMachineScheduler::schedule() { placeDebugValues(); DEBUG({ - unsigned BBNum = begin()->getParent()->getNumber(); - dbgs() << "*** Final schedule for BB#" << BBNum << " ***\n"; + dbgs() << "*** Final schedule for " + << printMBBReference(*begin()->getParent()) << " ***\n"; dumpSchedule(); dbgs() << '\n'; }); diff --git a/lib/Target/Hexagon/HexagonNewValueJump.cpp b/lib/Target/Hexagon/HexagonNewValueJump.cpp index 51cf6bbd8a241..8f177d9a4ee0a 100644 --- a/lib/Target/Hexagon/HexagonNewValueJump.cpp +++ b/lib/Target/Hexagon/HexagonNewValueJump.cpp @@ -139,6 +139,9 @@ static bool canBeFeederToNewValueJump(const HexagonInstrInfo *QII, if (II->isImplicitDef()) return false; + if (QII->isSolo(*II)) + return false; + // Make sure there there is no 'def' or 'use' of any of the uses of // feeder insn between it's definition, this MI and jump, jmpInst // skipping compare, cmpInst. diff --git a/lib/Target/Hexagon/HexagonOptAddrMode.cpp b/lib/Target/Hexagon/HexagonOptAddrMode.cpp index f42b6ed993572..d97ed4812f287 100644 --- a/lib/Target/Hexagon/HexagonOptAddrMode.cpp +++ b/lib/Target/Hexagon/HexagonOptAddrMode.cpp @@ -461,7 +461,7 @@ bool HexagonOptAddrMode::changeAddAsl(NodeAddr AddAslUN, DEBUG(dbgs() << "[InstrNode]: " << Print>(UseIA, *DFG) << "\n"); MachineInstr *UseMI = UseIA.Addr->getCode(); - DEBUG(dbgs() << "[MI getParent()->getNumber() + DEBUG(dbgs() << "[MI <" << printMBBReference(*UseMI->getParent()) << ">]: " << *UseMI << "\n"); const MCInstrDesc &UseMID = UseMI->getDesc(); assert(HII->getAddrMode(*UseMI) == HexagonII::BaseImmOffset); @@ -570,7 +570,7 @@ bool HexagonOptAddrMode::processBlock(NodeAddr BA) { NodeAddr OwnerN = UseN.Addr->getOwner(*DFG); MachineInstr *UseMI = OwnerN.Addr->getCode(); - DEBUG(dbgs() << "\t\t[MI getParent()->getNumber() + DEBUG(dbgs() << "\t\t[MI <" << printMBBReference(*UseMI->getParent()) << ">]: " << *UseMI << "\n"); int UseMOnum = -1; diff --git a/lib/Target/Hexagon/HexagonPeephole.cpp b/lib/Target/Hexagon/HexagonPeephole.cpp index 0ef0e78c5243e..7f82a5c4c4d8f 100644 --- a/lib/Target/Hexagon/HexagonPeephole.cpp +++ b/lib/Target/Hexagon/HexagonPeephole.cpp @@ -8,31 +8,30 @@ // This peephole pass optimizes in the following cases. // 1. Optimizes redundant sign extends for the following case // Transform the following pattern -// %vreg170 = SXTW %vreg166 +// %170 = SXTW %166 // ... -// %vreg176 = COPY %vreg170:isub_lo +// %176 = COPY %170:isub_lo // // Into -// %vreg176 = COPY vreg166 +// %176 = COPY %166 // // 2. Optimizes redundant negation of predicates. -// %vreg15 = CMPGTrr %vreg6, %vreg2 +// %15 = CMPGTrr %6, %2 // ... -// %vreg16 = NOT_p %vreg15 +// %16 = NOT_p %15 // ... -// JMP_c %vreg16, , %pc +// JMP_c %16, <%bb.1>, %pc // // Into -// %vreg15 = CMPGTrr %vreg6, %vreg2; +// %15 = CMPGTrr %6, %2; // ... -// JMP_cNot %vreg15, , %pc; +// JMP_cNot %15, <%bb.1>, %pc; // // Note: The peephole pass makes the instrucstions like -// %vreg170 = SXTW %vreg166 or %vreg16 = NOT_p %vreg15 +// %170 = SXTW %166 or %16 = NOT_p %15 // redundant and relies on some form of dead removal instructions, like // DCE or DIE to actually eliminate them. - //===----------------------------------------------------------------------===// #include "Hexagon.h" @@ -133,7 +132,7 @@ bool HexagonPeephole::runOnMachineFunction(MachineFunction &MF) { NextI = std::next(I); MachineInstr &MI = *I; // Look for sign extends: - // %vreg170 = SXTW %vreg166 + // %170 = SXTW %166 if (!DisableOptSZExt && MI.getOpcode() == Hexagon::A2_sxtw) { assert(MI.getNumOperands() == 2); MachineOperand &Dst = MI.getOperand(0); @@ -144,14 +143,14 @@ bool HexagonPeephole::runOnMachineFunction(MachineFunction &MF) { if (TargetRegisterInfo::isVirtualRegister(DstReg) && TargetRegisterInfo::isVirtualRegister(SrcReg)) { // Map the following: - // %vreg170 = SXTW %vreg166 - // PeepholeMap[170] = vreg166 + // %170 = SXTW %166 + // PeepholeMap[170] = %166 PeepholeMap[DstReg] = SrcReg; } } - // Look for %vreg170 = COMBINE_ir_V4 (0, %vreg169) - // %vreg170:DoublRegs, %vreg169:IntRegs + // Look for %170 = COMBINE_ir_V4 (0, %169) + // %170:DoublRegs, %169:IntRegs if (!DisableOptExtTo64 && MI.getOpcode() == Hexagon::A4_combineir) { assert(MI.getNumOperands() == 3); MachineOperand &Dst = MI.getOperand(0); @@ -165,10 +164,10 @@ bool HexagonPeephole::runOnMachineFunction(MachineFunction &MF) { } // Look for this sequence below - // %vregDoubleReg1 = LSRd_ri %vregDoubleReg0, 32 - // %vregIntReg = COPY %vregDoubleReg1:isub_lo. + // %DoubleReg1 = LSRd_ri %DoubleReg0, 32 + // %IntReg = COPY %DoubleReg1:isub_lo. // and convert into - // %vregIntReg = COPY %vregDoubleReg0:isub_hi. + // %IntReg = COPY %DoubleReg0:isub_hi. if (MI.getOpcode() == Hexagon::S2_lsr_i_p) { assert(MI.getNumOperands() == 3); MachineOperand &Dst = MI.getOperand(0); @@ -193,14 +192,14 @@ bool HexagonPeephole::runOnMachineFunction(MachineFunction &MF) { if (TargetRegisterInfo::isVirtualRegister(DstReg) && TargetRegisterInfo::isVirtualRegister(SrcReg)) { // Map the following: - // %vreg170 = NOT_xx %vreg166 - // PeepholeMap[170] = vreg166 + // %170 = NOT_xx %166 + // PeepholeMap[170] = %166 PeepholeMap[DstReg] = SrcReg; } } // Look for copy: - // %vreg176 = COPY %vreg170:isub_lo + // %176 = COPY %170:isub_lo if (!DisableOptSZExt && MI.isCopy()) { assert(MI.getNumOperands() == 2); MachineOperand &Dst = MI.getOperand(0); diff --git a/lib/Target/Hexagon/HexagonSplitDouble.cpp b/lib/Target/Hexagon/HexagonSplitDouble.cpp index 75d6750322b03..68b5ddd44388c 100644 --- a/lib/Target/Hexagon/HexagonSplitDouble.cpp +++ b/lib/Target/Hexagon/HexagonSplitDouble.cpp @@ -536,7 +536,7 @@ void HexagonSplitDoubleRegs::collectIndRegsForLoop(const MachineLoop *L, Rs.insert(CmpR2); DEBUG({ - dbgs() << "For loop at BB#" << HB->getNumber() << " ind regs: "; + dbgs() << "For loop at " << printMBBReference(*HB) << " ind regs: "; dump_partition(dbgs(), Rs, *TRI); dbgs() << '\n'; }); diff --git a/lib/Target/Hexagon/HexagonStoreWidening.cpp b/lib/Target/Hexagon/HexagonStoreWidening.cpp index d1816cbc7528a..fb3e6a0fb1051 100644 --- a/lib/Target/Hexagon/HexagonStoreWidening.cpp +++ b/lib/Target/Hexagon/HexagonStoreWidening.cpp @@ -9,10 +9,10 @@ // Replace sequences of "narrow" stores to adjacent memory locations with // a fewer "wide" stores that have the same effect. // For example, replace: -// S4_storeirb_io %vreg100, 0, 0 ; store-immediate-byte -// S4_storeirb_io %vreg100, 1, 0 ; store-immediate-byte +// S4_storeirb_io %100, 0, 0 ; store-immediate-byte +// S4_storeirb_io %100, 1, 0 ; store-immediate-byte // with -// S4_storeirh_io %vreg100, 0, 0 ; store-immediate-halfword +// S4_storeirh_io %100, 0, 0 ; store-immediate-halfword // The above is the general idea. The actual cases handled by the code // may be a bit more complex. // The purpose of this pass is to reduce the number of outstanding stores, diff --git a/lib/Target/Hexagon/HexagonSubtarget.cpp b/lib/Target/Hexagon/HexagonSubtarget.cpp index 7eed2898f617f..37f1e455b2373 100644 --- a/lib/Target/Hexagon/HexagonSubtarget.cpp +++ b/lib/Target/Hexagon/HexagonSubtarget.cpp @@ -92,7 +92,7 @@ static cl::opt EnableCheckBankConflict("hexagon-check-bank-conflict", HexagonSubtarget::HexagonSubtarget(const Triple &TT, StringRef CPU, StringRef FS, const TargetMachine &TM) - : HexagonGenSubtargetInfo(TT, CPU, FS), + : HexagonGenSubtargetInfo(TT, CPU, FS), OptLevel(TM.getOptLevel()), CPUString(Hexagon_MC::selectHexagonCPU(TT, CPU)), InstrInfo(initializeSubtargetDependencies(CPU, FS)), RegInfo(getHwMode()), TLInfo(TM, *this), @@ -223,8 +223,8 @@ void HexagonSubtarget::CallMutation::apply(ScheduleDAGInstrs *DAG) { // both the return value and the argument for the next call being in %r0. // Example: // 1: - // 2: %vregX = COPY %r0 - // 3: + // 2: %vreg = COPY %r0 + // 3: // 4: %r0 = ... // 5: // The scheduler would often swap 3 and 4, so an additional register is @@ -234,12 +234,12 @@ void HexagonSubtarget::CallMutation::apply(ScheduleDAGInstrs *DAG) { const MachineInstr *MI = DAG->SUnits[su].getInstr(); if (MI->isCopy() && (MI->readsRegister(Hexagon::R0, &TRI) || MI->readsRegister(Hexagon::V0, &TRI))) { - // %vregX = COPY %r0 + // %vreg = COPY %r0 VRegHoldingRet = MI->getOperand(0).getReg(); RetRegister = MI->getOperand(1).getReg(); LastUseOfRet = nullptr; } else if (VRegHoldingRet && MI->readsVirtualRegister(VRegHoldingRet)) - // + // LastUseOfRet = &DAG->SUnits[su]; else if (LastUseOfRet && MI->definesRegister(RetRegister, &TRI)) // %r0 = ... @@ -294,6 +294,14 @@ void HexagonSubtarget::BankConflictMutation::apply(ScheduleDAGInstrs *DAG) { } } +/// \brief Enable use of alias analysis during code generation (during MI +/// scheduling, DAGCombine, etc.). +bool HexagonSubtarget::useAA() const { + if (OptLevel != CodeGenOpt::None) + return true; + return false; +} + /// \brief Perform target specific adjustments to the latency of a schedule /// dependency. void HexagonSubtarget::adjustSchedDependency(SUnit *Src, SUnit *Dst, diff --git a/lib/Target/Hexagon/HexagonSubtarget.h b/lib/Target/Hexagon/HexagonSubtarget.h index 76892454d8a6c..ea69bd341926c 100644 --- a/lib/Target/Hexagon/HexagonSubtarget.h +++ b/lib/Target/Hexagon/HexagonSubtarget.h @@ -53,6 +53,7 @@ class HexagonSubtarget : public HexagonGenSubtargetInfo { public: Hexagon::ArchEnum HexagonArchVersion; Hexagon::ArchEnum HexagonHVXVersion = Hexagon::ArchEnum::V4; + CodeGenOpt::Level OptLevel; /// True if the target should use Back-Skip-Back scheduling. This is the /// default for V60. bool UseBSBScheduling; @@ -177,6 +178,10 @@ class HexagonSubtarget : public HexagonGenSubtargetInfo { std::vector> &Mutations) const override; + /// \brief Enable use of alias analysis during code generation (during MI + /// scheduling, DAGCombine, etc.). + bool useAA() const override; + /// \brief Perform target specific adjustments to the latency of a schedule /// dependency. void adjustSchedDependency(SUnit *def, SUnit *use, SDep& dep) const override; diff --git a/lib/Target/Hexagon/RDFGraph.cpp b/lib/Target/Hexagon/RDFGraph.cpp index 50ebcd5302c40..8513ebd1c76f1 100644 --- a/lib/Target/Hexagon/RDFGraph.cpp +++ b/lib/Target/Hexagon/RDFGraph.cpp @@ -247,7 +247,7 @@ raw_ostream &operator<< (raw_ostream &OS, if (T != MI.operands_end()) { OS << ' '; if (T->isMBB()) - OS << "BB#" << T->getMBB()->getNumber(); + OS << printMBBReference(*T->getMBB()); else if (T->isGlobal()) OS << T->getGlobal()->getName(); else if (T->isSymbol()) @@ -284,13 +284,13 @@ raw_ostream &operator<< (raw_ostream &OS, auto PrintBBs = [&OS] (std::vector Ns) -> void { unsigned N = Ns.size(); for (int I : Ns) { - OS << "BB#" << I; + OS << "%bb." << I; if (--N) OS << ", "; } }; - OS << Print(P.Obj.Id, P.G) << ": --- BB#" << BB->getNumber() + OS << Print(P.Obj.Id, P.G) << ": --- " << printMBBReference(*BB) << " --- preds(" << NP << "): "; for (MachineBasicBlock *B : BB->predecessors()) Ns.push_back(B->getNumber()); @@ -1123,8 +1123,8 @@ void DataFlowGraph::pushDefs(NodeAddr IA, DefStackMap &DefM) { if (!Defined.insert(RR.Reg).second) { MachineInstr *MI = NodeAddr(IA).Addr->getCode(); dbgs() << "Multiple definitions of register: " - << Print(RR, *this) << " in\n " << *MI - << "in BB#" << MI->getParent()->getNumber() << '\n'; + << Print(RR, *this) << " in\n " << *MI << "in " + << printMBBReference(*MI->getParent()) << '\n'; llvm_unreachable(nullptr); } #endif diff --git a/lib/Target/Hexagon/RDFGraph.h b/lib/Target/Hexagon/RDFGraph.h index 399b401c5ff6e..25c4b67230a5b 100644 --- a/lib/Target/Hexagon/RDFGraph.h +++ b/lib/Target/Hexagon/RDFGraph.h @@ -111,7 +111,7 @@ // // DFG dump:[ // f1: Function foo -// b2: === BB#0 === preds(0), succs(0): +// b2: === %bb.0 === preds(0), succs(0): // p3: phi [d4(,d12,u9):] // p5: phi [d6(,,u10):] // s7: add [d8(,,u13):, u9(d4):, u10(d6):] diff --git a/lib/Target/Hexagon/RDFLiveness.cpp b/lib/Target/Hexagon/RDFLiveness.cpp index 740cd11136b4b..13d9a17419789 100644 --- a/lib/Target/Hexagon/RDFLiveness.cpp +++ b/lib/Target/Hexagon/RDFLiveness.cpp @@ -814,7 +814,7 @@ void Liveness::computeLiveIns() { for (auto I = B.livein_begin(), E = B.livein_end(); I != E; ++I) LV.push_back(RegisterRef(I->PhysReg, I->LaneMask)); std::sort(LV.begin(), LV.end()); - dbgs() << "BB#" << B.getNumber() << "\t rec = {"; + dbgs() << printMBBReference(B) << "\t rec = {"; for (auto I : LV) dbgs() << ' ' << Print(I, DFG); dbgs() << " }\n"; @@ -963,7 +963,7 @@ void Liveness::traverse(MachineBasicBlock *B, RefMap &LiveIn) { } if (Trace) { - dbgs() << "\n-- BB#" << B->getNumber() << ": " << __func__ + dbgs() << "\n-- " << printMBBReference(*B) << ": " << __func__ << " after recursion into: {"; for (auto I : *N) dbgs() << ' ' << I->getBlock()->getNumber(); diff --git a/lib/Target/MSP430/MSP430BranchSelector.cpp b/lib/Target/MSP430/MSP430BranchSelector.cpp index 424b5ae418f7c..87c320aa76aaf 100644 --- a/lib/Target/MSP430/MSP430BranchSelector.cpp +++ b/lib/Target/MSP430/MSP430BranchSelector.cpp @@ -138,15 +138,15 @@ bool MSP430BSel::expandBranches(OffsetVector &BlockOffsets) { continue; } - DEBUG(dbgs() << " Found a branch that needs expanding, BB#" - << DestBB->getNumber() << ", Distance " << BranchDistance - << "\n"); + DEBUG(dbgs() << " Found a branch that needs expanding, " + << printMBBReference(*DestBB) << ", Distance " + << BranchDistance << "\n"); // If JCC is not the last instruction we need to split the MBB. if (MI->getOpcode() == MSP430::JCC && std::next(MI) != EE) { - DEBUG(dbgs() << " Found a basic block that needs to be split, BB#" - << MBB->getNumber() << "\n"); + DEBUG(dbgs() << " Found a basic block that needs to be split, " + << printMBBReference(*MBB) << "\n"); // Create a new basic block. MachineBasicBlock *NewBB = diff --git a/lib/Target/Mips/MipsConstantIslandPass.cpp b/lib/Target/Mips/MipsConstantIslandPass.cpp index 257e8f45a70ea..4dad98b80ed4c 100644 --- a/lib/Target/Mips/MipsConstantIslandPass.cpp +++ b/lib/Target/Mips/MipsConstantIslandPass.cpp @@ -430,7 +430,7 @@ bool MipsConstantIslands::isOffsetInRange LLVM_DUMP_METHOD void MipsConstantIslands::dumpBBs() { for (unsigned J = 0, E = BBInfo.size(); J !=E; ++J) { const BasicBlockInfo &BBI = BBInfo[J]; - dbgs() << format("%08x BB#%u\t", BBI.Offset, J) + dbgs() << format("%08x %bb.%u\t", BBI.Offset, J) << format(" size=%#x\n", BBInfo[J].Size); } } @@ -991,11 +991,11 @@ bool MipsConstantIslands::isCPEntryInRange const BasicBlockInfo &BBI = BBInfo[Block]; dbgs() << "User of CPE#" << CPEMI->getOperand(0).getImm() << " max delta=" << MaxDisp - << format(" insn address=%#x", UserOffset) - << " in BB#" << Block << ": " + << format(" insn address=%#x", UserOffset) << " in " + << printMBBReference(*MI->getParent()) << ": " << format("%#x-%x\t", BBI.Offset, BBI.postOffset()) << *MI << format("CPE address=%#x offset=%+d: ", CPEOffset, - int(CPEOffset-UserOffset)); + int(CPEOffset - UserOffset)); }); } @@ -1197,7 +1197,7 @@ bool MipsConstantIslands::findAvailableWater(CPUser &U, unsigned UserOffset, // This is the least amount of required padding seen so far. BestGrowth = Growth; WaterIter = IP; - DEBUG(dbgs() << "Found water after BB#" << WaterBB->getNumber() + DEBUG(dbgs() << "Found water after " << printMBBReference(*WaterBB) << " Growth=" << Growth << '\n'); // Keep looking unless it is perfect. @@ -1236,8 +1236,8 @@ void MipsConstantIslands::createNewWater(unsigned CPUserIndex, unsigned CPEOffset = UserBBI.postOffset(CPELogAlign) + Delta; if (isOffsetInRange(UserOffset, CPEOffset, U)) { - DEBUG(dbgs() << "Split at end of BB#" << UserMBB->getNumber() - << format(", expected CPE offset %#x\n", CPEOffset)); + DEBUG(dbgs() << "Split at end of " << printMBBReference(*UserMBB) + << format(", expected CPE offset %#x\n", CPEOffset)); NewMBB = &*++UserMBB->getIterator(); // Add an unconditional branch from UserMBB to fallthrough block. Record // it for branch lengthening; this new branch will not get out of range, @@ -1470,11 +1470,11 @@ bool MipsConstantIslands::isBBInRange unsigned BrOffset = getOffsetOf(MI) + PCAdj; unsigned DestOffset = BBInfo[DestBB->getNumber()].Offset; - DEBUG(dbgs() << "Branch of destination BB#" << DestBB->getNumber() - << " from BB#" << MI->getParent()->getNumber() - << " max delta=" << MaxDisp - << " from " << getOffsetOf(MI) << " to " << DestOffset - << " offset " << int(DestOffset-BrOffset) << "\t" << *MI); + DEBUG(dbgs() << "Branch of destination " << printMBBReference(*DestBB) + << " from " << printMBBReference(*MI->getParent()) + << " max delta=" << MaxDisp << " from " << getOffsetOf(MI) + << " to " << DestOffset << " offset " + << int(DestOffset - BrOffset) << "\t" << *MI); if (BrOffset <= DestOffset) { // Branch before the Dest. @@ -1615,9 +1615,9 @@ MipsConstantIslands::fixupConditionalBr(ImmBranch &Br) { } MachineBasicBlock *NextBB = &*++MBB->getIterator(); - DEBUG(dbgs() << " Insert B to BB#" << DestBB->getNumber() - << " also invert condition and change dest. to BB#" - << NextBB->getNumber() << "\n"); + DEBUG(dbgs() << " Insert B to " << printMBBReference(*DestBB) + << " also invert condition and change dest. to " + << printMBBReference(*NextBB) << "\n"); // Insert a new conditional branch and a new unconditional branch. // Also update the ImmBranch as well as adding a new entry for the new branch. diff --git a/lib/Target/NVPTX/NVPTXAssignValidGlobalNames.cpp b/lib/Target/NVPTX/NVPTXAssignValidGlobalNames.cpp index 7d4be8e809cf0..f02c33f9249ac 100644 --- a/lib/Target/NVPTX/NVPTXAssignValidGlobalNames.cpp +++ b/lib/Target/NVPTX/NVPTXAssignValidGlobalNames.cpp @@ -18,6 +18,7 @@ //===----------------------------------------------------------------------===// #include "NVPTX.h" +#include "llvm/IR/Function.h" #include "llvm/IR/GlobalVariable.h" #include "llvm/IR/LegacyPassManager.h" #include "llvm/IR/Module.h" @@ -61,6 +62,11 @@ bool NVPTXAssignValidGlobalNames::runOnModule(Module &M) { } } + // Do the same for local functions. + for (Function &F : M.functions()) + if (F.hasLocalLinkage()) + F.setName(cleanUpName(F.getName())); + return true; } diff --git a/lib/Target/NVPTX/NVPTXPeephole.cpp b/lib/Target/NVPTX/NVPTXPeephole.cpp index 7258e818e728a..f33655a16c233 100644 --- a/lib/Target/NVPTX/NVPTXPeephole.cpp +++ b/lib/Target/NVPTX/NVPTXPeephole.cpp @@ -22,11 +22,11 @@ // This peephole pass optimizes these cases, for example // // It will transform the following pattern -// %vreg0 = LEA_ADDRi64 %VRFrame, 4 -// %vreg1 = cvta_to_local_yes_64 %vreg0 +// %0 = LEA_ADDRi64 %VRFrame, 4 +// %1 = cvta_to_local_yes_64 %0 // // into -// %vreg1 = LEA_ADDRi64 %VRFrameLocal, 4 +// %1 = LEA_ADDRi64 %VRFrameLocal, 4 // // %VRFrameLocal is the virtual register name of %SPL // diff --git a/lib/Target/PowerPC/PPCBranchCoalescing.cpp b/lib/Target/PowerPC/PPCBranchCoalescing.cpp index 2af1913db55b7..cd07897230712 100644 --- a/lib/Target/PowerPC/PPCBranchCoalescing.cpp +++ b/lib/Target/PowerPC/PPCBranchCoalescing.cpp @@ -59,66 +59,66 @@ namespace llvm { /// /// expands to the following machine code: /// -/// BB#0: derived from LLVM BB %entry +/// %bb.0: derived from LLVM BB %entry /// Live Ins: %f1 %f3 %x6 /// -/// %vreg0 = COPY %f1; F8RC:%vreg0 -/// %vreg5 = CMPLWI %vreg4, 0; CRRC:%vreg5 GPRC:%vreg4 -/// %vreg8 = LXSDX %zero8, %vreg7, %rm; -/// mem:LD8[ConstantPool] F8RC:%vreg8 G8RC:%vreg7 -/// BCC 76, %vreg5, ; CRRC:%vreg5 -/// Successors according to CFG: BB#1(?%) BB#2(?%) -/// -/// BB#1: derived from LLVM BB %entry -/// Predecessors according to CFG: BB#0 -/// Successors according to CFG: BB#2(?%) -/// -/// BB#2: derived from LLVM BB %entry -/// Predecessors according to CFG: BB#0 BB#1 -/// %vreg9 = PHI %vreg8, , %vreg0, ; -/// F8RC:%vreg9,%vreg8,%vreg0 +/// %0 = COPY %f1; F8RC:%0 +/// %5 = CMPLWI %4, 0; CRRC:%5 GPRC:%4 +/// %8 = LXSDX %zero8, %7, %rm; +/// mem:LD8[ConstantPool] F8RC:%8 G8RC:%7 +/// BCC 76, %5, <%bb.2>; CRRC:%5 +/// Successors according to CFG: %bb.1(?%) %bb.2(?%) +/// +/// %bb.1: derived from LLVM BB %entry +/// Predecessors according to CFG: %bb.0 +/// Successors according to CFG: %bb.2(?%) +/// +/// %bb.2: derived from LLVM BB %entry +/// Predecessors according to CFG: %bb.0 %bb.1 +/// %9 = PHI %8, <%bb.1>, %0, <%bb.0>; +/// F8RC:%9,%8,%0 /// -/// BCC 76, %vreg5, ; CRRC:%vreg5 -/// Successors according to CFG: BB#3(?%) BB#4(?%) +/// BCC 76, %5, <%bb.4>; CRRC:%5 +/// Successors according to CFG: %bb.3(?%) %bb.4(?%) /// -/// BB#3: derived from LLVM BB %entry -/// Predecessors according to CFG: BB#2 -/// Successors according to CFG: BB#4(?%) +/// %bb.3: derived from LLVM BB %entry +/// Predecessors according to CFG: %bb.2 +/// Successors according to CFG: %bb.4(?%) /// -/// BB#4: derived from LLVM BB %entry -/// Predecessors according to CFG: BB#2 BB#3 -/// %vreg13 = PHI %vreg12, , %vreg2, ; -/// F8RC:%vreg13,%vreg12,%vreg2 +/// %bb.4: derived from LLVM BB %entry +/// Predecessors according to CFG: %bb.2 %bb.3 +/// %13 = PHI %12, <%bb.3>, %2, <%bb.2>; +/// F8RC:%13,%12,%2 /// /// BLR8 %lr8, %rm, %f1 /// /// When this pattern is detected, branch coalescing will try to collapse -/// it by moving code in BB#2 to BB#0 and/or BB#4 and removing BB#3. +/// it by moving code in %bb.2 to %bb.0 and/or %bb.4 and removing %bb.3. /// /// If all conditions are meet, IR should collapse to: /// -/// BB#0: derived from LLVM BB %entry +/// %bb.0: derived from LLVM BB %entry /// Live Ins: %f1 %f3 %x6 /// -/// %vreg0 = COPY %f1; F8RC:%vreg0 -/// %vreg5 = CMPLWI %vreg4, 0; CRRC:%vreg5 GPRC:%vreg4 -/// %vreg8 = LXSDX %zero8, %vreg7, %rm; -/// mem:LD8[ConstantPool] F8RC:%vreg8 G8RC:%vreg7 +/// %0 = COPY %f1; F8RC:%0 +/// %5 = CMPLWI %4, 0; CRRC:%5 GPRC:%4 +/// %8 = LXSDX %zero8, %7, %rm; +/// mem:LD8[ConstantPool] F8RC:%8 G8RC:%7 /// -/// BCC 76, %vreg5, ; CRRC:%vreg5 -/// Successors according to CFG: BB#1(0x2aaaaaaa / 0x80000000 = 33.33%) -/// BB#4(0x55555554 / 0x80000000 = 66.67%) -/// -/// BB#1: derived from LLVM BB %entry -/// Predecessors according to CFG: BB#0 -/// Successors according to CFG: BB#4(0x40000000 / 0x80000000 = 50.00%) -/// -/// BB#4: derived from LLVM BB %entry -/// Predecessors according to CFG: BB#0 BB#1 -/// %vreg9 = PHI %vreg8, , %vreg0, ; -/// F8RC:%vreg9,%vreg8,%vreg0 -/// %vreg13 = PHI %vreg12, , %vreg2, ; -/// F8RC:%vreg13,%vreg12,%vreg2 +/// BCC 76, %5, <%bb.4>; CRRC:%5 +/// Successors according to CFG: %bb.1(0x2aaaaaaa / 0x80000000 = 33.33%) +/// %bb.4(0x55555554 / 0x80000000 = 66.67%) +/// +/// %bb.1: derived from LLVM BB %entry +/// Predecessors according to CFG: %bb.0 +/// Successors according to CFG: %bb.4(0x40000000 / 0x80000000 = 50.00%) +/// +/// %bb.4: derived from LLVM BB %entry +/// Predecessors according to CFG: %bb.0 %bb.1 +/// %9 = PHI %8, <%bb.1>, %0, <%bb.0>; +/// F8RC:%9,%8,%0 +/// %13 = PHI %12, <%bb.1>, %2, <%bb.0>; +/// F8RC:%13,%12,%2 /// /// BLR8 %lr8, %rm, %f1 /// diff --git a/lib/Target/PowerPC/PPCCTRLoops.cpp b/lib/Target/PowerPC/PPCCTRLoops.cpp index 8784a83190292..fc638829378ab 100644 --- a/lib/Target/PowerPC/PPCCTRLoops.cpp +++ b/lib/Target/PowerPC/PPCCTRLoops.cpp @@ -690,12 +690,11 @@ static bool verifyCTRBranch(MachineBasicBlock *MBB, } if (I != BI && clobbersCTR(*I)) { - DEBUG(dbgs() << "BB#" << MBB->getNumber() << " (" << - MBB->getFullName() << ") instruction " << *I << - " clobbers CTR, invalidating " << "BB#" << - BI->getParent()->getNumber() << " (" << - BI->getParent()->getFullName() << ") instruction " << - *BI << "\n"); + DEBUG(dbgs() << printMBBReference(*MBB) << " (" << MBB->getFullName() + << ") instruction " << *I << " clobbers CTR, invalidating " + << printMBBReference(*BI->getParent()) << " (" + << BI->getParent()->getFullName() << ") instruction " << *BI + << "\n"); return false; } @@ -709,10 +708,10 @@ static bool verifyCTRBranch(MachineBasicBlock *MBB, if (CheckPreds) { queue_preds: if (MachineFunction::iterator(MBB) == MBB->getParent()->begin()) { - DEBUG(dbgs() << "Unable to find a MTCTR instruction for BB#" << - BI->getParent()->getNumber() << " (" << - BI->getParent()->getFullName() << ") instruction " << - *BI << "\n"); + DEBUG(dbgs() << "Unable to find a MTCTR instruction for " + << printMBBReference(*BI->getParent()) << " (" + << BI->getParent()->getFullName() << ") instruction " << *BI + << "\n"); return false; } diff --git a/lib/Target/PowerPC/PPCExpandISEL.cpp b/lib/Target/PowerPC/PPCExpandISEL.cpp index 41e3190c3eec7..dfd2b9bfd05c4 100644 --- a/lib/Target/PowerPC/PPCExpandISEL.cpp +++ b/lib/Target/PowerPC/PPCExpandISEL.cpp @@ -171,7 +171,7 @@ bool PPCExpandISEL::collectISELInstructions() { #ifndef NDEBUG void PPCExpandISEL::DumpISELInstructions() const { for (const auto &I : ISELInstructions) { - DEBUG(dbgs() << "BB#" << I.first << ":\n"); + DEBUG(dbgs() << printMBBReference(*MF->getBlockNumbered(I.first)) << ":\n"); for (const auto &VI : I.second) DEBUG(dbgs() << " "; VI->print(dbgs())); } @@ -191,7 +191,11 @@ bool PPCExpandISEL::canMerge(MachineInstr *PrevPushedMI, MachineInstr *MI) { void PPCExpandISEL::expandAndMergeISELs() { for (auto &BlockList : ISELInstructions) { - DEBUG(dbgs() << "Expanding ISEL instructions in BB#" << BlockList.first + + DEBUG(dbgs() << printMBBReference(*MF->getBlockNumbered(BlockList.first)) + << ":\n"); + DEBUG(dbgs() << "Expanding ISEL instructions in " + << printMBBReference(*MF->getBlockNumbered(BlockList.first)) << "\n"); BlockISELList &CurrentISELList = BlockList.second; diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp index 6289765c6b86a..2fff50b3e79d6 100644 --- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp +++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp @@ -69,6 +69,19 @@ using namespace llvm; #define DEBUG_TYPE "ppc-codegen" +STATISTIC(NumSextSetcc, + "Number of (sext(setcc)) nodes expanded into GPR sequence."); +STATISTIC(NumZextSetcc, + "Number of (zext(setcc)) nodes expanded into GPR sequence."); +STATISTIC(SignExtensionsAdded, + "Number of sign extensions for compare inputs added."); +STATISTIC(ZeroExtensionsAdded, + "Number of zero extensions for compare inputs added."); +STATISTIC(NumLogicOpsOnComparison, + "Number of logical ops on i1 values calculated in GPR."); +STATISTIC(OmittedForNonExtendUses, + "Number of compares not eliminated as they have non-extending uses."); + // FIXME: Remove this once the bug has been fixed! cl::opt ANDIGlueBug("expose-ppc-andi-glue-bug", cl::desc("expose the ANDI glue bug on PPC"), cl::Hidden); @@ -88,6 +101,29 @@ static cl::opt EnableBranchHint( cl::desc("Enable static hinting of branches on ppc"), cl::Hidden); +enum ICmpInGPRType { ICGPR_All, ICGPR_None, ICGPR_I32, ICGPR_I64, + ICGPR_NonExtIn, ICGPR_Zext, ICGPR_Sext, ICGPR_ZextI32, + ICGPR_SextI32, ICGPR_ZextI64, ICGPR_SextI64 }; + +static cl::opt CmpInGPR( + "ppc-gpr-icmps", cl::Hidden, cl::init(ICGPR_All), + cl::desc("Specify the types of comparisons to emit GPR-only code for."), + cl::values(clEnumValN(ICGPR_None, "none", "Do not modify integer comparisons."), + clEnumValN(ICGPR_All, "all", "All possible int comparisons in GPRs."), + clEnumValN(ICGPR_I32, "i32", "Only i32 comparisons in GPRs."), + clEnumValN(ICGPR_I64, "i64", "Only i64 comparisons in GPRs."), + clEnumValN(ICGPR_NonExtIn, "nonextin", + "Only comparisons where inputs don't need [sz]ext."), + clEnumValN(ICGPR_Zext, "zext", "Only comparisons with zext result."), + clEnumValN(ICGPR_ZextI32, "zexti32", + "Only i32 comparisons with zext result."), + clEnumValN(ICGPR_ZextI64, "zexti64", + "Only i64 comparisons with zext result."), + clEnumValN(ICGPR_Sext, "sext", "Only comparisons with sext result."), + clEnumValN(ICGPR_SextI32, "sexti32", + "Only i32 comparisons with sext result."), + clEnumValN(ICGPR_SextI64, "sexti64", + "Only i64 comparisons with sext result."))); namespace { //===--------------------------------------------------------------------===// @@ -161,6 +197,7 @@ namespace { bool tryBitfieldInsert(SDNode *N); bool tryBitPermutation(SDNode *N); + bool tryIntCompareInGPR(SDNode *N); /// SelectCC - Select a comparison of the specified values with the /// specified condition code, returning the CR# of the expression. @@ -2064,8 +2101,1203 @@ class BitPermutationSelector { } }; +class IntegerCompareEliminator { + SelectionDAG *CurDAG; + PPCDAGToDAGISel *S; + // Conversion type for interpreting results of a 32-bit instruction as + // a 64-bit value or vice versa. + enum ExtOrTruncConversion { Ext, Trunc }; + + // Modifiers to guide how an ISD::SETCC node's result is to be computed + // in a GPR. + // ZExtOrig - use the original condition code, zero-extend value + // ZExtInvert - invert the condition code, zero-extend value + // SExtOrig - use the original condition code, sign-extend value + // SExtInvert - invert the condition code, sign-extend value + enum SetccInGPROpts { ZExtOrig, ZExtInvert, SExtOrig, SExtInvert }; + + // Comparisons against zero to emit GPR code sequences for. Each of these + // sequences may need to be emitted for two or more equivalent patterns. + // For example (a >= 0) == (a > -1). The direction of the comparison () + // matters as well as the extension type: sext (-1/0), zext (1/0). + // GEZExt - (zext (LHS >= 0)) + // GESExt - (sext (LHS >= 0)) + // LEZExt - (zext (LHS <= 0)) + // LESExt - (sext (LHS <= 0)) + enum ZeroCompare { GEZExt, GESExt, LEZExt, LESExt }; + + SDNode *tryEXTEND(SDNode *N); + SDNode *tryLogicOpOfCompares(SDNode *N); + SDValue computeLogicOpInGPR(SDValue LogicOp); + SDValue signExtendInputIfNeeded(SDValue Input); + SDValue zeroExtendInputIfNeeded(SDValue Input); + SDValue addExtOrTrunc(SDValue NatWidthRes, ExtOrTruncConversion Conv); + SDValue getCompoundZeroComparisonInGPR(SDValue LHS, SDLoc dl, + ZeroCompare CmpTy); + SDValue get32BitZExtCompare(SDValue LHS, SDValue RHS, ISD::CondCode CC, + int64_t RHSValue, SDLoc dl); + SDValue get32BitSExtCompare(SDValue LHS, SDValue RHS, ISD::CondCode CC, + int64_t RHSValue, SDLoc dl); + SDValue get64BitZExtCompare(SDValue LHS, SDValue RHS, ISD::CondCode CC, + int64_t RHSValue, SDLoc dl); + SDValue get64BitSExtCompare(SDValue LHS, SDValue RHS, ISD::CondCode CC, + int64_t RHSValue, SDLoc dl); + SDValue getSETCCInGPR(SDValue Compare, SetccInGPROpts ConvOpts); + +public: + IntegerCompareEliminator(SelectionDAG *DAG, + PPCDAGToDAGISel *Sel) : CurDAG(DAG), S(Sel) { + assert(CurDAG->getTargetLoweringInfo() + .getPointerTy(CurDAG->getDataLayout()).getSizeInBits() == 64 && + "Only expecting to use this on 64 bit targets."); + } + SDNode *Select(SDNode *N) { + if (CmpInGPR == ICGPR_None) + return nullptr; + switch (N->getOpcode()) { + default: break; + case ISD::ZERO_EXTEND: + if (CmpInGPR == ICGPR_Sext || CmpInGPR == ICGPR_SextI32 || + CmpInGPR == ICGPR_SextI64) + return nullptr; + case ISD::SIGN_EXTEND: + if (CmpInGPR == ICGPR_Zext || CmpInGPR == ICGPR_ZextI32 || + CmpInGPR == ICGPR_ZextI64) + return nullptr; + return tryEXTEND(N); + case ISD::AND: + case ISD::OR: + case ISD::XOR: + return tryLogicOpOfCompares(N); + } + return nullptr; + } +}; + +static bool isLogicOp(unsigned Opc) { + return Opc == ISD::AND || Opc == ISD::OR || Opc == ISD::XOR; +} +// The obvious case for wanting to keep the value in a GPR. Namely, the +// result of the comparison is actually needed in a GPR. +SDNode *IntegerCompareEliminator::tryEXTEND(SDNode *N) { + assert((N->getOpcode() == ISD::ZERO_EXTEND || + N->getOpcode() == ISD::SIGN_EXTEND) && + "Expecting a zero/sign extend node!"); + SDValue WideRes; + // If we are zero-extending the result of a logical operation on i1 + // values, we can keep the values in GPRs. + if (isLogicOp(N->getOperand(0).getOpcode()) && + N->getOperand(0).getValueType() == MVT::i1 && + N->getOpcode() == ISD::ZERO_EXTEND) + WideRes = computeLogicOpInGPR(N->getOperand(0)); + else if (N->getOperand(0).getOpcode() != ISD::SETCC) + return nullptr; + else + WideRes = + getSETCCInGPR(N->getOperand(0), + N->getOpcode() == ISD::SIGN_EXTEND ? + SetccInGPROpts::SExtOrig : SetccInGPROpts::ZExtOrig); + + if (!WideRes) + return nullptr; + + SDLoc dl(N); + bool Input32Bit = WideRes.getValueType() == MVT::i32; + bool Output32Bit = N->getValueType(0) == MVT::i32; + + NumSextSetcc += N->getOpcode() == ISD::SIGN_EXTEND ? 1 : 0; + NumZextSetcc += N->getOpcode() == ISD::SIGN_EXTEND ? 0 : 1; + + SDValue ConvOp = WideRes; + if (Input32Bit != Output32Bit) + ConvOp = addExtOrTrunc(WideRes, Input32Bit ? ExtOrTruncConversion::Ext : + ExtOrTruncConversion::Trunc); + return ConvOp.getNode(); +} + +// Attempt to perform logical operations on the results of comparisons while +// keeping the values in GPRs. Without doing so, these would end up being +// lowered to CR-logical operations which suffer from significant latency and +// low ILP. +SDNode *IntegerCompareEliminator::tryLogicOpOfCompares(SDNode *N) { + if (N->getValueType(0) != MVT::i1) + return nullptr; + assert(isLogicOp(N->getOpcode()) && + "Expected a logic operation on setcc results."); + SDValue LoweredLogical = computeLogicOpInGPR(SDValue(N, 0)); + if (!LoweredLogical) + return nullptr; + + SDLoc dl(N); + bool IsBitwiseNegate = LoweredLogical.getMachineOpcode() == PPC::XORI8; + unsigned SubRegToExtract = IsBitwiseNegate ? PPC::sub_eq : PPC::sub_gt; + SDValue CR0Reg = CurDAG->getRegister(PPC::CR0, MVT::i32); + SDValue LHS = LoweredLogical.getOperand(0); + SDValue RHS = LoweredLogical.getOperand(1); + SDValue WideOp; + SDValue OpToConvToRecForm; + + // Look through any 32-bit to 64-bit implicit extend nodes to find the + // opcode that is input to the XORI. + if (IsBitwiseNegate && + LoweredLogical.getOperand(0).getMachineOpcode() == PPC::INSERT_SUBREG) + OpToConvToRecForm = LoweredLogical.getOperand(0).getOperand(1); + else if (IsBitwiseNegate) + // If the input to the XORI isn't an extension, that's what we're after. + OpToConvToRecForm = LoweredLogical.getOperand(0); + else + // If this is not an XORI, it is a reg-reg logical op and we can convert + // it to record-form. + OpToConvToRecForm = LoweredLogical; + + // Get the record-form version of the node we're looking to use to get the + // CR result from. + uint16_t NonRecOpc = OpToConvToRecForm.getMachineOpcode(); + int NewOpc = PPCInstrInfo::getRecordFormOpcode(NonRecOpc); + + // Convert the right node to record-form. This is either the logical we're + // looking at or it is the input node to the negation (if we're looking at + // a bitwise negation). + if (NewOpc != -1 && IsBitwiseNegate) { + // The input to the XORI has a record-form. Use it. + assert(LoweredLogical.getConstantOperandVal(1) == 1 && + "Expected a PPC::XORI8 only for bitwise negation."); + // Emit the record-form instruction. + std::vector Ops; + for (int i = 0, e = OpToConvToRecForm.getNumOperands(); i < e; i++) + Ops.push_back(OpToConvToRecForm.getOperand(i)); + + WideOp = + SDValue(CurDAG->getMachineNode(NewOpc, dl, + OpToConvToRecForm.getValueType(), + MVT::Glue, Ops), 0); + } else { + assert((NewOpc != -1 || !IsBitwiseNegate) && + "No record form available for AND8/OR8/XOR8?"); + WideOp = + SDValue(CurDAG->getMachineNode(NewOpc == -1 ? PPC::ANDIo8 : NewOpc, dl, + MVT::i64, MVT::Glue, LHS, RHS), 0); + } + + // Select this node to a single bit from CR0 set by the record-form node + // just created. For bitwise negation, use the EQ bit which is the equivalent + // of negating the result (i.e. it is a bit set when the result of the + // operation is zero). + SDValue SRIdxVal = + CurDAG->getTargetConstant(SubRegToExtract, dl, MVT::i32); + SDValue CRBit = + SDValue(CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG, dl, + MVT::i1, CR0Reg, SRIdxVal, + WideOp.getValue(1)), 0); + return CRBit.getNode(); +} + +// Lower a logical operation on i1 values into a GPR sequence if possible. +// The result can be kept in a GPR if requested. +// Three types of inputs can be handled: +// - SETCC +// - TRUNCATE +// - Logical operation (AND/OR/XOR) +// There is also a special case that is handled (namely a complement operation +// achieved with xor %a, -1). +SDValue IntegerCompareEliminator::computeLogicOpInGPR(SDValue LogicOp) { + assert(isLogicOp(LogicOp.getOpcode()) && + "Can only handle logic operations here."); + assert(LogicOp.getValueType() == MVT::i1 && + "Can only handle logic operations on i1 values here."); + SDLoc dl(LogicOp); + SDValue LHS, RHS; + + // Special case: xor %a, -1 + bool IsBitwiseNegation = isBitwiseNot(LogicOp); + + // Produces a GPR sequence for each operand of the binary logic operation. + // For SETCC, it produces the respective comparison, for TRUNCATE it truncates + // the value in a GPR and for logic operations, it will recursively produce + // a GPR sequence for the operation. + auto getLogicOperand = [&] (SDValue Operand) -> SDValue { + unsigned OperandOpcode = Operand.getOpcode(); + if (OperandOpcode == ISD::SETCC) + return getSETCCInGPR(Operand, SetccInGPROpts::ZExtOrig); + else if (OperandOpcode == ISD::TRUNCATE) { + SDValue InputOp = Operand.getOperand(0); + EVT InVT = InputOp.getValueType(); + return SDValue(CurDAG->getMachineNode(InVT == MVT::i32 ? PPC::RLDICL_32 : + PPC::RLDICL, dl, InVT, InputOp, + S->getI64Imm(0, dl), + S->getI64Imm(63, dl)), 0); + } else if (isLogicOp(OperandOpcode)) + return computeLogicOpInGPR(Operand); + return SDValue(); + }; + LHS = getLogicOperand(LogicOp.getOperand(0)); + RHS = getLogicOperand(LogicOp.getOperand(1)); + + // If a GPR sequence can't be produced for the LHS we can't proceed. + // Not producing a GPR sequence for the RHS is only a problem if this isn't + // a bitwise negation operation. + if (!LHS || (!RHS && !IsBitwiseNegation)) + return SDValue(); + + NumLogicOpsOnComparison++; + + // We will use the inputs as 64-bit values. + if (LHS.getValueType() == MVT::i32) + LHS = addExtOrTrunc(LHS, ExtOrTruncConversion::Ext); + if (!IsBitwiseNegation && RHS.getValueType() == MVT::i32) + RHS = addExtOrTrunc(RHS, ExtOrTruncConversion::Ext); + + unsigned NewOpc; + switch (LogicOp.getOpcode()) { + default: llvm_unreachable("Unknown logic operation."); + case ISD::AND: NewOpc = PPC::AND8; break; + case ISD::OR: NewOpc = PPC::OR8; break; + case ISD::XOR: NewOpc = PPC::XOR8; break; + } + + if (IsBitwiseNegation) { + RHS = S->getI64Imm(1, dl); + NewOpc = PPC::XORI8; + } + + return SDValue(CurDAG->getMachineNode(NewOpc, dl, MVT::i64, LHS, RHS), 0); + +} + +/// If the value isn't guaranteed to be sign-extended to 64-bits, extend it. +/// Otherwise just reinterpret it as a 64-bit value. +/// Useful when emitting comparison code for 32-bit values without using +/// the compare instruction (which only considers the lower 32-bits). +SDValue IntegerCompareEliminator::signExtendInputIfNeeded(SDValue Input) { + assert(Input.getValueType() == MVT::i32 && + "Can only sign-extend 32-bit values here."); + unsigned Opc = Input.getOpcode(); + + // The value was sign extended and then truncated to 32-bits. No need to + // sign extend it again. + if (Opc == ISD::TRUNCATE && + (Input.getOperand(0).getOpcode() == ISD::AssertSext || + Input.getOperand(0).getOpcode() == ISD::SIGN_EXTEND)) + return addExtOrTrunc(Input, ExtOrTruncConversion::Ext); + + LoadSDNode *InputLoad = dyn_cast(Input); + // The input is a sign-extending load. All ppc sign-extending loads + // sign-extend to the full 64-bits. + if (InputLoad && InputLoad->getExtensionType() == ISD::SEXTLOAD) + return addExtOrTrunc(Input, ExtOrTruncConversion::Ext); + + ConstantSDNode *InputConst = dyn_cast(Input); + // We don't sign-extend constants. + if (InputConst) + return addExtOrTrunc(Input, ExtOrTruncConversion::Ext); + + SDLoc dl(Input); + SignExtensionsAdded++; + return SDValue(CurDAG->getMachineNode(PPC::EXTSW_32_64, dl, + MVT::i64, Input), 0); +} + +/// If the value isn't guaranteed to be zero-extended to 64-bits, extend it. +/// Otherwise just reinterpret it as a 64-bit value. +/// Useful when emitting comparison code for 32-bit values without using +/// the compare instruction (which only considers the lower 32-bits). +SDValue IntegerCompareEliminator::zeroExtendInputIfNeeded(SDValue Input) { + assert(Input.getValueType() == MVT::i32 && + "Can only zero-extend 32-bit values here."); + unsigned Opc = Input.getOpcode(); + + // The only condition under which we can omit the actual extend instruction: + // - The value is a positive constant + // - The value comes from a load that isn't a sign-extending load + // An ISD::TRUNCATE needs to be zero-extended unless it is fed by a zext. + bool IsTruncateOfZExt = Opc == ISD::TRUNCATE && + (Input.getOperand(0).getOpcode() == ISD::AssertZext || + Input.getOperand(0).getOpcode() == ISD::ZERO_EXTEND); + if (IsTruncateOfZExt) + return addExtOrTrunc(Input, ExtOrTruncConversion::Ext); + + ConstantSDNode *InputConst = dyn_cast(Input); + if (InputConst && InputConst->getSExtValue() >= 0) + return addExtOrTrunc(Input, ExtOrTruncConversion::Ext); + + LoadSDNode *InputLoad = dyn_cast(Input); + // The input is a load that doesn't sign-extend (it will be zero-extended). + if (InputLoad && InputLoad->getExtensionType() != ISD::SEXTLOAD) + return addExtOrTrunc(Input, ExtOrTruncConversion::Ext); + + // None of the above, need to zero-extend. + SDLoc dl(Input); + ZeroExtensionsAdded++; + return SDValue(CurDAG->getMachineNode(PPC::RLDICL_32_64, dl, MVT::i64, Input, + S->getI64Imm(0, dl), + S->getI64Imm(32, dl)), 0); +} + +// Handle a 32-bit value in a 64-bit register and vice-versa. These are of +// course not actual zero/sign extensions that will generate machine code, +// they're just a way to reinterpret a 32 bit value in a register as a +// 64 bit value and vice-versa. +SDValue IntegerCompareEliminator::addExtOrTrunc(SDValue NatWidthRes, + ExtOrTruncConversion Conv) { + SDLoc dl(NatWidthRes); + + // For reinterpreting 32-bit values as 64 bit values, we generate + // INSERT_SUBREG IMPLICIT_DEF:i64, , TargetConstant:i32<1> + if (Conv == ExtOrTruncConversion::Ext) { + SDValue ImDef(CurDAG->getMachineNode(PPC::IMPLICIT_DEF, dl, MVT::i64), 0); + SDValue SubRegIdx = + CurDAG->getTargetConstant(PPC::sub_32, dl, MVT::i32); + return SDValue(CurDAG->getMachineNode(PPC::INSERT_SUBREG, dl, MVT::i64, + ImDef, NatWidthRes, SubRegIdx), 0); + } + + assert(Conv == ExtOrTruncConversion::Trunc && + "Unknown convertion between 32 and 64 bit values."); + // For reinterpreting 64-bit values as 32-bit values, we just need to + // EXTRACT_SUBREG (i.e. extract the low word). + SDValue SubRegIdx = + CurDAG->getTargetConstant(PPC::sub_32, dl, MVT::i32); + return SDValue(CurDAG->getMachineNode(PPC::EXTRACT_SUBREG, dl, MVT::i32, + NatWidthRes, SubRegIdx), 0); +} + +// Produce a GPR sequence for compound comparisons (<=, >=) against zero. +// Handle both zero-extensions and sign-extensions. +SDValue +IntegerCompareEliminator::getCompoundZeroComparisonInGPR(SDValue LHS, SDLoc dl, + ZeroCompare CmpTy) { + EVT InVT = LHS.getValueType(); + bool Is32Bit = InVT == MVT::i32; + SDValue ToExtend; + + // Produce the value that needs to be either zero or sign extended. + switch (CmpTy) { + case ZeroCompare::GEZExt: + case ZeroCompare::GESExt: + ToExtend = SDValue(CurDAG->getMachineNode(Is32Bit ? PPC::NOR : PPC::NOR8, + dl, InVT, LHS, LHS), 0); + break; + case ZeroCompare::LEZExt: + case ZeroCompare::LESExt: { + if (Is32Bit) { + // Upper 32 bits cannot be undefined for this sequence. + LHS = signExtendInputIfNeeded(LHS); + SDValue Neg = + SDValue(CurDAG->getMachineNode(PPC::NEG8, dl, MVT::i64, LHS), 0); + ToExtend = + SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, + Neg, S->getI64Imm(1, dl), + S->getI64Imm(63, dl)), 0); + } else { + SDValue Addi = + SDValue(CurDAG->getMachineNode(PPC::ADDI8, dl, MVT::i64, LHS, + S->getI64Imm(~0ULL, dl)), 0); + ToExtend = SDValue(CurDAG->getMachineNode(PPC::OR8, dl, MVT::i64, + Addi, LHS), 0); + } + break; + } + } + + // For 64-bit sequences, the extensions are the same for the GE/LE cases. + if (!Is32Bit && + (CmpTy == ZeroCompare::GEZExt || CmpTy == ZeroCompare::LEZExt)) + return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, + ToExtend, S->getI64Imm(1, dl), + S->getI64Imm(63, dl)), 0); + if (!Is32Bit && + (CmpTy == ZeroCompare::GESExt || CmpTy == ZeroCompare::LESExt)) + return SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, ToExtend, + S->getI64Imm(63, dl)), 0); + + assert(Is32Bit && "Should have handled the 32-bit sequences above."); + // For 32-bit sequences, the extensions differ between GE/LE cases. + switch (CmpTy) { + case ZeroCompare::GEZExt: { + SDValue ShiftOps[] = { ToExtend, S->getI32Imm(1, dl), S->getI32Imm(31, dl), + S->getI32Imm(31, dl) }; + return SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, + ShiftOps), 0); + } + case ZeroCompare::GESExt: + return SDValue(CurDAG->getMachineNode(PPC::SRAWI, dl, MVT::i32, ToExtend, + S->getI32Imm(31, dl)), 0); + case ZeroCompare::LEZExt: + return SDValue(CurDAG->getMachineNode(PPC::XORI8, dl, MVT::i64, ToExtend, + S->getI32Imm(1, dl)), 0); + case ZeroCompare::LESExt: + return SDValue(CurDAG->getMachineNode(PPC::ADDI8, dl, MVT::i64, ToExtend, + S->getI32Imm(-1, dl)), 0); + } + + // The above case covers all the enumerators so it can't have a default clause + // to avoid compiler warnings. + llvm_unreachable("Unknown zero-comparison type."); +} + +/// Produces a zero-extended result of comparing two 32-bit values according to +/// the passed condition code. +SDValue +IntegerCompareEliminator::get32BitZExtCompare(SDValue LHS, SDValue RHS, + ISD::CondCode CC, + int64_t RHSValue, SDLoc dl) { + if (CmpInGPR == ICGPR_I64 || CmpInGPR == ICGPR_SextI64 || + CmpInGPR == ICGPR_ZextI64 || CmpInGPR == ICGPR_Sext) + return SDValue(); + bool IsRHSZero = RHSValue == 0; + bool IsRHSOne = RHSValue == 1; + bool IsRHSNegOne = RHSValue == -1LL; + switch (CC) { + default: return SDValue(); + case ISD::SETEQ: { + // (zext (setcc %a, %b, seteq)) -> (lshr (cntlzw (xor %a, %b)), 5) + // (zext (setcc %a, 0, seteq)) -> (lshr (cntlzw %a), 5) + SDValue Xor = IsRHSZero ? LHS : + SDValue(CurDAG->getMachineNode(PPC::XOR, dl, MVT::i32, LHS, RHS), 0); + SDValue Clz = + SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, Xor), 0); + SDValue ShiftOps[] = { Clz, S->getI32Imm(27, dl), S->getI32Imm(5, dl), + S->getI32Imm(31, dl) }; + return SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, + ShiftOps), 0); + } + case ISD::SETNE: { + // (zext (setcc %a, %b, setne)) -> (xor (lshr (cntlzw (xor %a, %b)), 5), 1) + // (zext (setcc %a, 0, setne)) -> (xor (lshr (cntlzw %a), 5), 1) + SDValue Xor = IsRHSZero ? LHS : + SDValue(CurDAG->getMachineNode(PPC::XOR, dl, MVT::i32, LHS, RHS), 0); + SDValue Clz = + SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, Xor), 0); + SDValue ShiftOps[] = { Clz, S->getI32Imm(27, dl), S->getI32Imm(5, dl), + S->getI32Imm(31, dl) }; + SDValue Shift = + SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, ShiftOps), 0); + return SDValue(CurDAG->getMachineNode(PPC::XORI, dl, MVT::i32, Shift, + S->getI32Imm(1, dl)), 0); + } + case ISD::SETGE: { + // (zext (setcc %a, %b, setge)) -> (xor (lshr (sub %a, %b), 63), 1) + // (zext (setcc %a, 0, setge)) -> (lshr (~ %a), 31) + if(IsRHSZero) + return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::GEZExt); + + // Not a special case (i.e. RHS == 0). Handle (%a >= %b) as (%b <= %a) + // by swapping inputs and falling through. + std::swap(LHS, RHS); + ConstantSDNode *RHSConst = dyn_cast(RHS); + IsRHSZero = RHSConst && RHSConst->isNullValue(); + LLVM_FALLTHROUGH; + } + case ISD::SETLE: { + if (CmpInGPR == ICGPR_NonExtIn) + return SDValue(); + // (zext (setcc %a, %b, setle)) -> (xor (lshr (sub %b, %a), 63), 1) + // (zext (setcc %a, 0, setle)) -> (xor (lshr (- %a), 63), 1) + if(IsRHSZero) { + if (CmpInGPR == ICGPR_NonExtIn) + return SDValue(); + return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::LEZExt); + } + + // The upper 32-bits of the register can't be undefined for this sequence. + LHS = signExtendInputIfNeeded(LHS); + RHS = signExtendInputIfNeeded(RHS); + SDValue Sub = + SDValue(CurDAG->getMachineNode(PPC::SUBF8, dl, MVT::i64, LHS, RHS), 0); + SDValue Shift = + SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, Sub, + S->getI64Imm(1, dl), S->getI64Imm(63, dl)), + 0); + return + SDValue(CurDAG->getMachineNode(PPC::XORI8, dl, + MVT::i64, Shift, S->getI32Imm(1, dl)), 0); + } + case ISD::SETGT: { + // (zext (setcc %a, %b, setgt)) -> (lshr (sub %b, %a), 63) + // (zext (setcc %a, -1, setgt)) -> (lshr (~ %a), 31) + // (zext (setcc %a, 0, setgt)) -> (lshr (- %a), 63) + // Handle SETLT -1 (which is equivalent to SETGE 0). + if (IsRHSNegOne) + return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::GEZExt); + + if (IsRHSZero) { + if (CmpInGPR == ICGPR_NonExtIn) + return SDValue(); + // The upper 32-bits of the register can't be undefined for this sequence. + LHS = signExtendInputIfNeeded(LHS); + RHS = signExtendInputIfNeeded(RHS); + SDValue Neg = + SDValue(CurDAG->getMachineNode(PPC::NEG8, dl, MVT::i64, LHS), 0); + return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, + Neg, S->getI32Imm(1, dl), S->getI32Imm(63, dl)), 0); + } + // Not a special case (i.e. RHS == 0 or RHS == -1). Handle (%a > %b) as + // (%b < %a) by swapping inputs and falling through. + std::swap(LHS, RHS); + ConstantSDNode *RHSConst = dyn_cast(RHS); + IsRHSZero = RHSConst && RHSConst->isNullValue(); + IsRHSOne = RHSConst && RHSConst->getSExtValue() == 1; + LLVM_FALLTHROUGH; + } + case ISD::SETLT: { + // (zext (setcc %a, %b, setlt)) -> (lshr (sub %a, %b), 63) + // (zext (setcc %a, 1, setlt)) -> (xor (lshr (- %a), 63), 1) + // (zext (setcc %a, 0, setlt)) -> (lshr %a, 31) + // Handle SETLT 1 (which is equivalent to SETLE 0). + if (IsRHSOne) { + if (CmpInGPR == ICGPR_NonExtIn) + return SDValue(); + return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::LEZExt); + } + + if (IsRHSZero) { + SDValue ShiftOps[] = { LHS, S->getI32Imm(1, dl), S->getI32Imm(31, dl), + S->getI32Imm(31, dl) }; + return SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, + ShiftOps), 0); + } + + if (CmpInGPR == ICGPR_NonExtIn) + return SDValue(); + // The upper 32-bits of the register can't be undefined for this sequence. + LHS = signExtendInputIfNeeded(LHS); + RHS = signExtendInputIfNeeded(RHS); + SDValue SUBFNode = + SDValue(CurDAG->getMachineNode(PPC::SUBF8, dl, MVT::i64, RHS, LHS), 0); + return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, + SUBFNode, S->getI64Imm(1, dl), + S->getI64Imm(63, dl)), 0); + } + case ISD::SETUGE: + // (zext (setcc %a, %b, setuge)) -> (xor (lshr (sub %b, %a), 63), 1) + // (zext (setcc %a, %b, setule)) -> (xor (lshr (sub %a, %b), 63), 1) + std::swap(LHS, RHS); + LLVM_FALLTHROUGH; + case ISD::SETULE: { + if (CmpInGPR == ICGPR_NonExtIn) + return SDValue(); + // The upper 32-bits of the register can't be undefined for this sequence. + LHS = zeroExtendInputIfNeeded(LHS); + RHS = zeroExtendInputIfNeeded(RHS); + SDValue Subtract = + SDValue(CurDAG->getMachineNode(PPC::SUBF8, dl, MVT::i64, LHS, RHS), 0); + SDValue SrdiNode = + SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, + Subtract, S->getI64Imm(1, dl), + S->getI64Imm(63, dl)), 0); + return SDValue(CurDAG->getMachineNode(PPC::XORI8, dl, MVT::i64, SrdiNode, + S->getI32Imm(1, dl)), 0); + } + case ISD::SETUGT: + // (zext (setcc %a, %b, setugt)) -> (lshr (sub %b, %a), 63) + // (zext (setcc %a, %b, setult)) -> (lshr (sub %a, %b), 63) + std::swap(LHS, RHS); + LLVM_FALLTHROUGH; + case ISD::SETULT: { + if (CmpInGPR == ICGPR_NonExtIn) + return SDValue(); + // The upper 32-bits of the register can't be undefined for this sequence. + LHS = zeroExtendInputIfNeeded(LHS); + RHS = zeroExtendInputIfNeeded(RHS); + SDValue Subtract = + SDValue(CurDAG->getMachineNode(PPC::SUBF8, dl, MVT::i64, RHS, LHS), 0); + return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, + Subtract, S->getI64Imm(1, dl), + S->getI64Imm(63, dl)), 0); + } + } +} + +/// Produces a sign-extended result of comparing two 32-bit values according to +/// the passed condition code. +SDValue +IntegerCompareEliminator::get32BitSExtCompare(SDValue LHS, SDValue RHS, + ISD::CondCode CC, + int64_t RHSValue, SDLoc dl) { + if (CmpInGPR == ICGPR_I64 || CmpInGPR == ICGPR_SextI64 || + CmpInGPR == ICGPR_ZextI64 || CmpInGPR == ICGPR_Zext) + return SDValue(); + bool IsRHSZero = RHSValue == 0; + bool IsRHSOne = RHSValue == 1; + bool IsRHSNegOne = RHSValue == -1LL; + + switch (CC) { + default: return SDValue(); + case ISD::SETEQ: { + // (sext (setcc %a, %b, seteq)) -> + // (ashr (shl (ctlz (xor %a, %b)), 58), 63) + // (sext (setcc %a, 0, seteq)) -> + // (ashr (shl (ctlz %a), 58), 63) + SDValue CountInput = IsRHSZero ? LHS : + SDValue(CurDAG->getMachineNode(PPC::XOR, dl, MVT::i32, LHS, RHS), 0); + SDValue Cntlzw = + SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, CountInput), 0); + SDValue SHLOps[] = { Cntlzw, S->getI32Imm(27, dl), + S->getI32Imm(5, dl), S->getI32Imm(31, dl) }; + SDValue Slwi = + SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, SHLOps), 0); + return SDValue(CurDAG->getMachineNode(PPC::NEG, dl, MVT::i32, Slwi), 0); + } + case ISD::SETNE: { + // Bitwise xor the operands, count leading zeros, shift right by 5 bits and + // flip the bit, finally take 2's complement. + // (sext (setcc %a, %b, setne)) -> + // (neg (xor (lshr (ctlz (xor %a, %b)), 5), 1)) + // Same as above, but the first xor is not needed. + // (sext (setcc %a, 0, setne)) -> + // (neg (xor (lshr (ctlz %a), 5), 1)) + SDValue Xor = IsRHSZero ? LHS : + SDValue(CurDAG->getMachineNode(PPC::XOR, dl, MVT::i32, LHS, RHS), 0); + SDValue Clz = + SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, Xor), 0); + SDValue ShiftOps[] = + { Clz, S->getI32Imm(27, dl), S->getI32Imm(5, dl), S->getI32Imm(31, dl) }; + SDValue Shift = + SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, ShiftOps), 0); + SDValue Xori = + SDValue(CurDAG->getMachineNode(PPC::XORI, dl, MVT::i32, Shift, + S->getI32Imm(1, dl)), 0); + return SDValue(CurDAG->getMachineNode(PPC::NEG, dl, MVT::i32, Xori), 0); + } + case ISD::SETGE: { + // (sext (setcc %a, %b, setge)) -> (add (lshr (sub %a, %b), 63), -1) + // (sext (setcc %a, 0, setge)) -> (ashr (~ %a), 31) + if (IsRHSZero) + return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::GESExt); + + // Not a special case (i.e. RHS == 0). Handle (%a >= %b) as (%b <= %a) + // by swapping inputs and falling through. + std::swap(LHS, RHS); + ConstantSDNode *RHSConst = dyn_cast(RHS); + IsRHSZero = RHSConst && RHSConst->isNullValue(); + LLVM_FALLTHROUGH; + } + case ISD::SETLE: { + if (CmpInGPR == ICGPR_NonExtIn) + return SDValue(); + // (sext (setcc %a, %b, setge)) -> (add (lshr (sub %b, %a), 63), -1) + // (sext (setcc %a, 0, setle)) -> (add (lshr (- %a), 63), -1) + if (IsRHSZero) + return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::LESExt); + + // The upper 32-bits of the register can't be undefined for this sequence. + LHS = signExtendInputIfNeeded(LHS); + RHS = signExtendInputIfNeeded(RHS); + SDValue SUBFNode = + SDValue(CurDAG->getMachineNode(PPC::SUBF8, dl, MVT::i64, MVT::Glue, + LHS, RHS), 0); + SDValue Srdi = + SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, + SUBFNode, S->getI64Imm(1, dl), + S->getI64Imm(63, dl)), 0); + return SDValue(CurDAG->getMachineNode(PPC::ADDI8, dl, MVT::i64, Srdi, + S->getI32Imm(-1, dl)), 0); + } + case ISD::SETGT: { + // (sext (setcc %a, %b, setgt)) -> (ashr (sub %b, %a), 63) + // (sext (setcc %a, -1, setgt)) -> (ashr (~ %a), 31) + // (sext (setcc %a, 0, setgt)) -> (ashr (- %a), 63) + if (IsRHSNegOne) + return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::GESExt); + if (IsRHSZero) { + if (CmpInGPR == ICGPR_NonExtIn) + return SDValue(); + // The upper 32-bits of the register can't be undefined for this sequence. + LHS = signExtendInputIfNeeded(LHS); + RHS = signExtendInputIfNeeded(RHS); + SDValue Neg = + SDValue(CurDAG->getMachineNode(PPC::NEG8, dl, MVT::i64, LHS), 0); + return SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, Neg, + S->getI64Imm(63, dl)), 0); + } + // Not a special case (i.e. RHS == 0 or RHS == -1). Handle (%a > %b) as + // (%b < %a) by swapping inputs and falling through. + std::swap(LHS, RHS); + ConstantSDNode *RHSConst = dyn_cast(RHS); + IsRHSZero = RHSConst && RHSConst->isNullValue(); + IsRHSOne = RHSConst && RHSConst->getSExtValue() == 1; + LLVM_FALLTHROUGH; + } + case ISD::SETLT: { + // (sext (setcc %a, %b, setgt)) -> (ashr (sub %a, %b), 63) + // (sext (setcc %a, 1, setgt)) -> (add (lshr (- %a), 63), -1) + // (sext (setcc %a, 0, setgt)) -> (ashr %a, 31) + if (IsRHSOne) { + if (CmpInGPR == ICGPR_NonExtIn) + return SDValue(); + return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::LESExt); + } + if (IsRHSZero) + return SDValue(CurDAG->getMachineNode(PPC::SRAWI, dl, MVT::i32, LHS, + S->getI32Imm(31, dl)), 0); + + if (CmpInGPR == ICGPR_NonExtIn) + return SDValue(); + // The upper 32-bits of the register can't be undefined for this sequence. + LHS = signExtendInputIfNeeded(LHS); + RHS = signExtendInputIfNeeded(RHS); + SDValue SUBFNode = + SDValue(CurDAG->getMachineNode(PPC::SUBF8, dl, MVT::i64, RHS, LHS), 0); + return SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, + SUBFNode, S->getI64Imm(63, dl)), 0); + } + case ISD::SETUGE: + // (sext (setcc %a, %b, setuge)) -> (add (lshr (sub %a, %b), 63), -1) + // (sext (setcc %a, %b, setule)) -> (add (lshr (sub %b, %a), 63), -1) + std::swap(LHS, RHS); + LLVM_FALLTHROUGH; + case ISD::SETULE: { + if (CmpInGPR == ICGPR_NonExtIn) + return SDValue(); + // The upper 32-bits of the register can't be undefined for this sequence. + LHS = zeroExtendInputIfNeeded(LHS); + RHS = zeroExtendInputIfNeeded(RHS); + SDValue Subtract = + SDValue(CurDAG->getMachineNode(PPC::SUBF8, dl, MVT::i64, LHS, RHS), 0); + SDValue Shift = + SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, Subtract, + S->getI32Imm(1, dl), S->getI32Imm(63,dl)), + 0); + return SDValue(CurDAG->getMachineNode(PPC::ADDI8, dl, MVT::i64, Shift, + S->getI32Imm(-1, dl)), 0); + } + case ISD::SETUGT: + // (sext (setcc %a, %b, setugt)) -> (ashr (sub %b, %a), 63) + // (sext (setcc %a, %b, setugt)) -> (ashr (sub %a, %b), 63) + std::swap(LHS, RHS); + LLVM_FALLTHROUGH; + case ISD::SETULT: { + if (CmpInGPR == ICGPR_NonExtIn) + return SDValue(); + // The upper 32-bits of the register can't be undefined for this sequence. + LHS = zeroExtendInputIfNeeded(LHS); + RHS = zeroExtendInputIfNeeded(RHS); + SDValue Subtract = + SDValue(CurDAG->getMachineNode(PPC::SUBF8, dl, MVT::i64, RHS, LHS), 0); + return SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, + Subtract, S->getI64Imm(63, dl)), 0); + } + } +} + +/// Produces a zero-extended result of comparing two 64-bit values according to +/// the passed condition code. +SDValue +IntegerCompareEliminator::get64BitZExtCompare(SDValue LHS, SDValue RHS, + ISD::CondCode CC, + int64_t RHSValue, SDLoc dl) { + if (CmpInGPR == ICGPR_I32 || CmpInGPR == ICGPR_SextI32 || + CmpInGPR == ICGPR_ZextI32 || CmpInGPR == ICGPR_Sext) + return SDValue(); + bool IsRHSZero = RHSValue == 0; + bool IsRHSOne = RHSValue == 1; + bool IsRHSNegOne = RHSValue == -1LL; + switch (CC) { + default: return SDValue(); + case ISD::SETEQ: { + // (zext (setcc %a, %b, seteq)) -> (lshr (ctlz (xor %a, %b)), 6) + // (zext (setcc %a, 0, seteq)) -> (lshr (ctlz %a), 6) + SDValue Xor = IsRHSZero ? LHS : + SDValue(CurDAG->getMachineNode(PPC::XOR8, dl, MVT::i64, LHS, RHS), 0); + SDValue Clz = + SDValue(CurDAG->getMachineNode(PPC::CNTLZD, dl, MVT::i64, Xor), 0); + return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, Clz, + S->getI64Imm(58, dl), + S->getI64Imm(63, dl)), 0); + } + case ISD::SETNE: { + // {addc.reg, addc.CA} = (addcarry (xor %a, %b), -1) + // (zext (setcc %a, %b, setne)) -> (sube addc.reg, addc.reg, addc.CA) + // {addcz.reg, addcz.CA} = (addcarry %a, -1) + // (zext (setcc %a, 0, setne)) -> (sube addcz.reg, addcz.reg, addcz.CA) + SDValue Xor = IsRHSZero ? LHS : + SDValue(CurDAG->getMachineNode(PPC::XOR8, dl, MVT::i64, LHS, RHS), 0); + SDValue AC = + SDValue(CurDAG->getMachineNode(PPC::ADDIC8, dl, MVT::i64, MVT::Glue, + Xor, S->getI32Imm(~0U, dl)), 0); + return SDValue(CurDAG->getMachineNode(PPC::SUBFE8, dl, MVT::i64, AC, + Xor, AC.getValue(1)), 0); + } + case ISD::SETGE: { + // {subc.reg, subc.CA} = (subcarry %a, %b) + // (zext (setcc %a, %b, setge)) -> + // (adde (lshr %b, 63), (ashr %a, 63), subc.CA) + // (zext (setcc %a, 0, setge)) -> (lshr (~ %a), 63) + if (IsRHSZero) + return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::GEZExt); + std::swap(LHS, RHS); + ConstantSDNode *RHSConst = dyn_cast(RHS); + IsRHSZero = RHSConst && RHSConst->isNullValue(); + LLVM_FALLTHROUGH; + } + case ISD::SETLE: { + // {subc.reg, subc.CA} = (subcarry %b, %a) + // (zext (setcc %a, %b, setge)) -> + // (adde (lshr %a, 63), (ashr %b, 63), subc.CA) + // (zext (setcc %a, 0, setge)) -> (lshr (or %a, (add %a, -1)), 63) + if (IsRHSZero) + return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::LEZExt); + SDValue ShiftL = + SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, LHS, + S->getI64Imm(1, dl), + S->getI64Imm(63, dl)), 0); + SDValue ShiftR = + SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, RHS, + S->getI64Imm(63, dl)), 0); + SDValue SubtractCarry = + SDValue(CurDAG->getMachineNode(PPC::SUBFC8, dl, MVT::i64, MVT::Glue, + LHS, RHS), 1); + return SDValue(CurDAG->getMachineNode(PPC::ADDE8, dl, MVT::i64, MVT::Glue, + ShiftR, ShiftL, SubtractCarry), 0); + } + case ISD::SETGT: { + // {subc.reg, subc.CA} = (subcarry %b, %a) + // (zext (setcc %a, %b, setgt)) -> + // (xor (adde (lshr %a, 63), (ashr %b, 63), subc.CA), 1) + // (zext (setcc %a, 0, setgt)) -> (lshr (nor (add %a, -1), %a), 63) + if (IsRHSNegOne) + return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::GEZExt); + if (IsRHSZero) { + SDValue Addi = + SDValue(CurDAG->getMachineNode(PPC::ADDI8, dl, MVT::i64, LHS, + S->getI64Imm(~0ULL, dl)), 0); + SDValue Nor = + SDValue(CurDAG->getMachineNode(PPC::NOR8, dl, MVT::i64, Addi, LHS), 0); + return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, Nor, + S->getI64Imm(1, dl), + S->getI64Imm(63, dl)), 0); + } + std::swap(LHS, RHS); + ConstantSDNode *RHSConst = dyn_cast(RHS); + IsRHSZero = RHSConst && RHSConst->isNullValue(); + IsRHSOne = RHSConst && RHSConst->getSExtValue() == 1; + LLVM_FALLTHROUGH; + } + case ISD::SETLT: { + // {subc.reg, subc.CA} = (subcarry %a, %b) + // (zext (setcc %a, %b, setlt)) -> + // (xor (adde (lshr %b, 63), (ashr %a, 63), subc.CA), 1) + // (zext (setcc %a, 0, setlt)) -> (lshr %a, 63) + if (IsRHSOne) + return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::LEZExt); + if (IsRHSZero) + return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, LHS, + S->getI64Imm(1, dl), + S->getI64Imm(63, dl)), 0); + SDValue SRADINode = + SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, + LHS, S->getI64Imm(63, dl)), 0); + SDValue SRDINode = + SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, + RHS, S->getI64Imm(1, dl), + S->getI64Imm(63, dl)), 0); + SDValue SUBFC8Carry = + SDValue(CurDAG->getMachineNode(PPC::SUBFC8, dl, MVT::i64, MVT::Glue, + RHS, LHS), 1); + SDValue ADDE8Node = + SDValue(CurDAG->getMachineNode(PPC::ADDE8, dl, MVT::i64, MVT::Glue, + SRDINode, SRADINode, SUBFC8Carry), 0); + return SDValue(CurDAG->getMachineNode(PPC::XORI8, dl, MVT::i64, + ADDE8Node, S->getI64Imm(1, dl)), 0); + } + case ISD::SETUGE: + // {subc.reg, subc.CA} = (subcarry %a, %b) + // (zext (setcc %a, %b, setuge)) -> (add (sube %b, %b, subc.CA), 1) + std::swap(LHS, RHS); + LLVM_FALLTHROUGH; + case ISD::SETULE: { + // {subc.reg, subc.CA} = (subcarry %b, %a) + // (zext (setcc %a, %b, setule)) -> (add (sube %a, %a, subc.CA), 1) + SDValue SUBFC8Carry = + SDValue(CurDAG->getMachineNode(PPC::SUBFC8, dl, MVT::i64, MVT::Glue, + LHS, RHS), 1); + SDValue SUBFE8Node = + SDValue(CurDAG->getMachineNode(PPC::SUBFE8, dl, MVT::i64, MVT::Glue, + LHS, LHS, SUBFC8Carry), 0); + return SDValue(CurDAG->getMachineNode(PPC::ADDI8, dl, MVT::i64, + SUBFE8Node, S->getI64Imm(1, dl)), 0); + } + case ISD::SETUGT: + // {subc.reg, subc.CA} = (subcarry %b, %a) + // (zext (setcc %a, %b, setugt)) -> -(sube %b, %b, subc.CA) + std::swap(LHS, RHS); + LLVM_FALLTHROUGH; + case ISD::SETULT: { + // {subc.reg, subc.CA} = (subcarry %a, %b) + // (zext (setcc %a, %b, setult)) -> -(sube %a, %a, subc.CA) + SDValue SubtractCarry = + SDValue(CurDAG->getMachineNode(PPC::SUBFC8, dl, MVT::i64, MVT::Glue, + RHS, LHS), 1); + SDValue ExtSub = + SDValue(CurDAG->getMachineNode(PPC::SUBFE8, dl, MVT::i64, + LHS, LHS, SubtractCarry), 0); + return SDValue(CurDAG->getMachineNode(PPC::NEG8, dl, MVT::i64, + ExtSub), 0); + } + } +} + +/// Produces a sign-extended result of comparing two 64-bit values according to +/// the passed condition code. +SDValue +IntegerCompareEliminator::get64BitSExtCompare(SDValue LHS, SDValue RHS, + ISD::CondCode CC, + int64_t RHSValue, SDLoc dl) { + if (CmpInGPR == ICGPR_I32 || CmpInGPR == ICGPR_SextI32 || + CmpInGPR == ICGPR_ZextI32 || CmpInGPR == ICGPR_Zext) + return SDValue(); + bool IsRHSZero = RHSValue == 0; + bool IsRHSOne = RHSValue == 1; + bool IsRHSNegOne = RHSValue == -1LL; + switch (CC) { + default: return SDValue(); + case ISD::SETEQ: { + // {addc.reg, addc.CA} = (addcarry (xor %a, %b), -1) + // (sext (setcc %a, %b, seteq)) -> (sube addc.reg, addc.reg, addc.CA) + // {addcz.reg, addcz.CA} = (addcarry %a, -1) + // (sext (setcc %a, 0, seteq)) -> (sube addcz.reg, addcz.reg, addcz.CA) + SDValue AddInput = IsRHSZero ? LHS : + SDValue(CurDAG->getMachineNode(PPC::XOR8, dl, MVT::i64, LHS, RHS), 0); + SDValue Addic = + SDValue(CurDAG->getMachineNode(PPC::ADDIC8, dl, MVT::i64, MVT::Glue, + AddInput, S->getI32Imm(~0U, dl)), 0); + return SDValue(CurDAG->getMachineNode(PPC::SUBFE8, dl, MVT::i64, Addic, + Addic, Addic.getValue(1)), 0); + } + case ISD::SETNE: { + // {subfc.reg, subfc.CA} = (subcarry 0, (xor %a, %b)) + // (sext (setcc %a, %b, setne)) -> (sube subfc.reg, subfc.reg, subfc.CA) + // {subfcz.reg, subfcz.CA} = (subcarry 0, %a) + // (sext (setcc %a, 0, setne)) -> (sube subfcz.reg, subfcz.reg, subfcz.CA) + SDValue Xor = IsRHSZero ? LHS : + SDValue(CurDAG->getMachineNode(PPC::XOR8, dl, MVT::i64, LHS, RHS), 0); + SDValue SC = + SDValue(CurDAG->getMachineNode(PPC::SUBFIC8, dl, MVT::i64, MVT::Glue, + Xor, S->getI32Imm(0, dl)), 0); + return SDValue(CurDAG->getMachineNode(PPC::SUBFE8, dl, MVT::i64, SC, + SC, SC.getValue(1)), 0); + } + case ISD::SETGE: { + // {subc.reg, subc.CA} = (subcarry %a, %b) + // (zext (setcc %a, %b, setge)) -> + // (- (adde (lshr %b, 63), (ashr %a, 63), subc.CA)) + // (zext (setcc %a, 0, setge)) -> (~ (ashr %a, 63)) + if (IsRHSZero) + return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::GESExt); + std::swap(LHS, RHS); + ConstantSDNode *RHSConst = dyn_cast(RHS); + IsRHSZero = RHSConst && RHSConst->isNullValue(); + LLVM_FALLTHROUGH; + } + case ISD::SETLE: { + // {subc.reg, subc.CA} = (subcarry %b, %a) + // (zext (setcc %a, %b, setge)) -> + // (- (adde (lshr %a, 63), (ashr %b, 63), subc.CA)) + // (zext (setcc %a, 0, setge)) -> (ashr (or %a, (add %a, -1)), 63) + if (IsRHSZero) + return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::LESExt); + SDValue ShiftR = + SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, RHS, + S->getI64Imm(63, dl)), 0); + SDValue ShiftL = + SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, LHS, + S->getI64Imm(1, dl), + S->getI64Imm(63, dl)), 0); + SDValue SubtractCarry = + SDValue(CurDAG->getMachineNode(PPC::SUBFC8, dl, MVT::i64, MVT::Glue, + LHS, RHS), 1); + SDValue Adde = + SDValue(CurDAG->getMachineNode(PPC::ADDE8, dl, MVT::i64, MVT::Glue, + ShiftR, ShiftL, SubtractCarry), 0); + return SDValue(CurDAG->getMachineNode(PPC::NEG8, dl, MVT::i64, Adde), 0); + } + case ISD::SETGT: { + // {subc.reg, subc.CA} = (subcarry %b, %a) + // (zext (setcc %a, %b, setgt)) -> + // -(xor (adde (lshr %a, 63), (ashr %b, 63), subc.CA), 1) + // (zext (setcc %a, 0, setgt)) -> (ashr (nor (add %a, -1), %a), 63) + if (IsRHSNegOne) + return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::GESExt); + if (IsRHSZero) { + SDValue Add = + SDValue(CurDAG->getMachineNode(PPC::ADDI8, dl, MVT::i64, LHS, + S->getI64Imm(-1, dl)), 0); + SDValue Nor = + SDValue(CurDAG->getMachineNode(PPC::NOR8, dl, MVT::i64, Add, LHS), 0); + return SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, Nor, + S->getI64Imm(63, dl)), 0); + } + std::swap(LHS, RHS); + ConstantSDNode *RHSConst = dyn_cast(RHS); + IsRHSZero = RHSConst && RHSConst->isNullValue(); + IsRHSOne = RHSConst && RHSConst->getSExtValue() == 1; + LLVM_FALLTHROUGH; + } + case ISD::SETLT: { + // {subc.reg, subc.CA} = (subcarry %a, %b) + // (zext (setcc %a, %b, setlt)) -> + // -(xor (adde (lshr %b, 63), (ashr %a, 63), subc.CA), 1) + // (zext (setcc %a, 0, setlt)) -> (ashr %a, 63) + if (IsRHSOne) + return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::LESExt); + if (IsRHSZero) { + return SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, LHS, + S->getI64Imm(63, dl)), 0); + } + SDValue SRADINode = + SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, + LHS, S->getI64Imm(63, dl)), 0); + SDValue SRDINode = + SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, + RHS, S->getI64Imm(1, dl), + S->getI64Imm(63, dl)), 0); + SDValue SUBFC8Carry = + SDValue(CurDAG->getMachineNode(PPC::SUBFC8, dl, MVT::i64, MVT::Glue, + RHS, LHS), 1); + SDValue ADDE8Node = + SDValue(CurDAG->getMachineNode(PPC::ADDE8, dl, MVT::i64, + SRDINode, SRADINode, SUBFC8Carry), 0); + SDValue XORI8Node = + SDValue(CurDAG->getMachineNode(PPC::XORI8, dl, MVT::i64, + ADDE8Node, S->getI64Imm(1, dl)), 0); + return SDValue(CurDAG->getMachineNode(PPC::NEG8, dl, MVT::i64, + XORI8Node), 0); + } + case ISD::SETUGE: + // {subc.reg, subc.CA} = (subcarry %a, %b) + // (sext (setcc %a, %b, setuge)) -> ~(sube %b, %b, subc.CA) + std::swap(LHS, RHS); + LLVM_FALLTHROUGH; + case ISD::SETULE: { + // {subc.reg, subc.CA} = (subcarry %b, %a) + // (sext (setcc %a, %b, setule)) -> ~(sube %a, %a, subc.CA) + SDValue SubtractCarry = + SDValue(CurDAG->getMachineNode(PPC::SUBFC8, dl, MVT::i64, MVT::Glue, + LHS, RHS), 1); + SDValue ExtSub = + SDValue(CurDAG->getMachineNode(PPC::SUBFE8, dl, MVT::i64, MVT::Glue, LHS, + LHS, SubtractCarry), 0); + return SDValue(CurDAG->getMachineNode(PPC::NOR8, dl, MVT::i64, + ExtSub, ExtSub), 0); + } + case ISD::SETUGT: + // {subc.reg, subc.CA} = (subcarry %b, %a) + // (sext (setcc %a, %b, setugt)) -> (sube %b, %b, subc.CA) + std::swap(LHS, RHS); + LLVM_FALLTHROUGH; + case ISD::SETULT: { + // {subc.reg, subc.CA} = (subcarry %a, %b) + // (sext (setcc %a, %b, setult)) -> (sube %a, %a, subc.CA) + SDValue SubCarry = + SDValue(CurDAG->getMachineNode(PPC::SUBFC8, dl, MVT::i64, MVT::Glue, + RHS, LHS), 1); + return SDValue(CurDAG->getMachineNode(PPC::SUBFE8, dl, MVT::i64, + LHS, LHS, SubCarry), 0); + } + } +} + +/// Do all uses of this SDValue need the result in a GPR? +/// This is meant to be used on values that have type i1 since +/// it is somewhat meaningless to ask if values of other types +/// should be kept in GPR's. +static bool allUsesExtend(SDValue Compare, SelectionDAG *CurDAG) { + assert(Compare.getOpcode() == ISD::SETCC && + "An ISD::SETCC node required here."); + + // For values that have a single use, the caller should obviously already have + // checked if that use is an extending use. We check the other uses here. + if (Compare.hasOneUse()) + return true; + // We want the value in a GPR if it is being extended, used for a select, or + // used in logical operations. + for (auto CompareUse : Compare.getNode()->uses()) + if (CompareUse->getOpcode() != ISD::SIGN_EXTEND && + CompareUse->getOpcode() != ISD::ZERO_EXTEND && + CompareUse->getOpcode() != ISD::SELECT && + !isLogicOp(CompareUse->getOpcode())) { + OmittedForNonExtendUses++; + return false; + } + return true; +} + +/// Returns an equivalent of a SETCC node but with the result the same width as +/// the inputs. This can nalso be used for SELECT_CC if either the true or false +/// values is a power of two while the other is zero. +SDValue IntegerCompareEliminator::getSETCCInGPR(SDValue Compare, + SetccInGPROpts ConvOpts) { + assert((Compare.getOpcode() == ISD::SETCC || + Compare.getOpcode() == ISD::SELECT_CC) && + "An ISD::SETCC node required here."); + + // Don't convert this comparison to a GPR sequence because there are uses + // of the i1 result (i.e. uses that require the result in the CR). + if ((Compare.getOpcode() == ISD::SETCC) && !allUsesExtend(Compare, CurDAG)) + return SDValue(); + + SDValue LHS = Compare.getOperand(0); + SDValue RHS = Compare.getOperand(1); + + // The condition code is operand 2 for SETCC and operand 4 for SELECT_CC. + int CCOpNum = Compare.getOpcode() == ISD::SELECT_CC ? 4 : 2; + ISD::CondCode CC = + cast(Compare.getOperand(CCOpNum))->get(); + EVT InputVT = LHS.getValueType(); + if (InputVT != MVT::i32 && InputVT != MVT::i64) + return SDValue(); + + if (ConvOpts == SetccInGPROpts::ZExtInvert || + ConvOpts == SetccInGPROpts::SExtInvert) + CC = ISD::getSetCCInverse(CC, true); + + bool Inputs32Bit = InputVT == MVT::i32; + + SDLoc dl(Compare); + ConstantSDNode *RHSConst = dyn_cast(RHS); + int64_t RHSValue = RHSConst ? RHSConst->getSExtValue() : INT64_MAX; + bool IsSext = ConvOpts == SetccInGPROpts::SExtOrig || + ConvOpts == SetccInGPROpts::SExtInvert; + + if (IsSext && Inputs32Bit) + return get32BitSExtCompare(LHS, RHS, CC, RHSValue, dl); + else if (Inputs32Bit) + return get32BitZExtCompare(LHS, RHS, CC, RHSValue, dl); + else if (IsSext) + return get64BitSExtCompare(LHS, RHS, CC, RHSValue, dl); + return get64BitZExtCompare(LHS, RHS, CC, RHSValue, dl); +} + } // end anonymous namespace +bool PPCDAGToDAGISel::tryIntCompareInGPR(SDNode *N) { + if (N->getValueType(0) != MVT::i32 && + N->getValueType(0) != MVT::i64) + return false; + + // This optimization will emit code that assumes 64-bit registers + // so we don't want to run it in 32-bit mode. Also don't run it + // on functions that are not to be optimized. + if (TM.getOptLevel() == CodeGenOpt::None || !TM.isPPC64()) + return false; + + switch (N->getOpcode()) { + default: break; + case ISD::ZERO_EXTEND: + case ISD::SIGN_EXTEND: + case ISD::AND: + case ISD::OR: + case ISD::XOR: { + IntegerCompareEliminator ICmpElim(CurDAG, this); + if (SDNode *New = ICmpElim.Select(N)) { + ReplaceNode(N, New); + return true; + } + } + } + return false; +} + bool PPCDAGToDAGISel::tryBitPermutation(SDNode *N) { if (N->getValueType(0) != MVT::i32 && N->getValueType(0) != MVT::i64) @@ -2578,6 +3810,10 @@ void PPCDAGToDAGISel::Select(SDNode *N) { if (tryBitPermutation(N)) return; + // Try to emit integer compares as GPR-only sequences (i.e. no use of CR). + if (tryIntCompareInGPR(N)) + return; + switch (N->getOpcode()) { default: break; diff --git a/lib/Target/PowerPC/PPCInstrInfo.cpp b/lib/Target/PowerPC/PPCInstrInfo.cpp index fd5666347603a..15cc1c7676062 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -2318,7 +2318,7 @@ PPCInstrInfo::isSignOrZeroExtended(const MachineInstr &MI, bool SignExt, // ADJCALLSTACKDOWN 32, %r1, %r1 // BL8_NOP ,... // ADJCALLSTACKUP 32, 0, %r1, %r1 - // %vreg5 = COPY %x3; G8RC:%vreg5 + // %5 = COPY %x3; G8RC:%5 if (SrcReg == PPC::X3) { const MachineBasicBlock *MBB = MI.getParent(); MachineBasicBlock::const_instr_iterator II = diff --git a/lib/Target/PowerPC/PPCMIPeephole.cpp b/lib/Target/PowerPC/PPCMIPeephole.cpp index a8d98133afcfe..c6fcea7c9564d 100644 --- a/lib/Target/PowerPC/PPCMIPeephole.cpp +++ b/lib/Target/PowerPC/PPCMIPeephole.cpp @@ -585,9 +585,9 @@ bool PPCMIPeephole::simplifyCode(void) { // We can eliminate RLDICL (e.g. for zero-extension) // if all bits to clear are already zero in the input. // This code assume following code sequence for zero-extension. - // %vreg6 = COPY %vreg5:sub_32; (optional) - // %vreg8 = IMPLICIT_DEF; - // %vreg7 = INSERT_SUBREG %vreg8, %vreg6, sub_32; + // %6 = COPY %5:sub_32; (optional) + // %8 = IMPLICIT_DEF; + // %7 = INSERT_SUBREG %8, %6, sub_32; if (!EnableZExtElimination) break; if (MI.getOperand(2).getImm() != 0) @@ -685,8 +685,8 @@ bool PPCMIPeephole::simplifyCode(void) { DEBUG(dbgs() << "Optimizing LI to ADDI: "); DEBUG(LiMI->dump()); - // There could be repeated registers in the PHI, e.g: %vreg1 = - // PHI %vreg6, , %vreg8, , %vreg8, ; So if we've + // There could be repeated registers in the PHI, e.g: %1 = + // PHI %6, <%bb.2>, %8, <%bb.3>, %8, <%bb.6>; So if we've // already replaced the def instruction, skip. if (LiMI->getOpcode() == PPC::ADDI || LiMI->getOpcode() == PPC::ADDI8) continue; @@ -1209,8 +1209,9 @@ bool PPCMIPeephole::eliminateRedundantCompare(void) { DEBUG(BI1->dump()); DEBUG(BI2->dump()); if (IsPartiallyRedundant) { - DEBUG(dbgs() << "The following compare is moved into BB#" << - MBBtoMoveCmp->getNumber() << " to handle partial redundancy.\n"); + DEBUG(dbgs() << "The following compare is moved into " + << printMBBReference(*MBBtoMoveCmp) + << " to handle partial redundancy.\n"); DEBUG(CMPI2->dump()); } diff --git a/lib/Target/PowerPC/PPCVSXFMAMutate.cpp b/lib/Target/PowerPC/PPCVSXFMAMutate.cpp index 80b63b1c9dfaa..4d001c0210ddc 100644 --- a/lib/Target/PowerPC/PPCVSXFMAMutate.cpp +++ b/lib/Target/PowerPC/PPCVSXFMAMutate.cpp @@ -90,21 +90,21 @@ namespace { // This pass is run after register coalescing, and so we're looking for // a situation like this: // ... - // %vreg5 = COPY %vreg9; VSLRC:%vreg5,%vreg9 - // %vreg5 = XSMADDADP %vreg5, %vreg17, %vreg16, - // %rm; VSLRC:%vreg5,%vreg17,%vreg16 + // %5 = COPY %9; VSLRC:%5,%9 + // %5 = XSMADDADP %5, %17, %16, + // %rm; VSLRC:%5,%17,%16 // ... - // %vreg9 = XSMADDADP %vreg9, %vreg17, %vreg19, - // %rm; VSLRC:%vreg9,%vreg17,%vreg19 + // %9 = XSMADDADP %9, %17, %19, + // %rm; VSLRC:%9,%17,%19 // ... // Where we can eliminate the copy by changing from the A-type to the // M-type instruction. Specifically, for this example, this means: - // %vreg5 = XSMADDADP %vreg5, %vreg17, %vreg16, - // %rm; VSLRC:%vreg5,%vreg17,%vreg16 + // %5 = XSMADDADP %5, %17, %16, + // %rm; VSLRC:%5,%17,%16 // is replaced by: - // %vreg16 = XSMADDMDP %vreg16, %vreg18, %vreg9, - // %rm; VSLRC:%vreg16,%vreg18,%vreg9 - // and we remove: %vreg5 = COPY %vreg9; VSLRC:%vreg5,%vreg9 + // %16 = XSMADDMDP %16, %18, %9, + // %rm; VSLRC:%16,%18,%9 + // and we remove: %5 = COPY %9; VSLRC:%5,%9 SlotIndex FMAIdx = LIS->getInstructionIndex(MI); @@ -150,13 +150,13 @@ namespace { // walking the MIs we may as well test liveness here. // // FIXME: There is a case that occurs in practice, like this: - // %vreg9 = COPY %f1; VSSRC:%vreg9 + // %9 = COPY %f1; VSSRC:%9 // ... - // %vreg6 = COPY %vreg9; VSSRC:%vreg6,%vreg9 - // %vreg7 = COPY %vreg9; VSSRC:%vreg7,%vreg9 - // %vreg9 = XSMADDASP %vreg9, %vreg1, %vreg4; VSSRC: - // %vreg6 = XSMADDASP %vreg6, %vreg1, %vreg2; VSSRC: - // %vreg7 = XSMADDASP %vreg7, %vreg1, %vreg3; VSSRC: + // %6 = COPY %9; VSSRC:%6,%9 + // %7 = COPY %9; VSSRC:%7,%9 + // %9 = XSMADDASP %9, %1, %4; VSSRC: + // %6 = XSMADDASP %6, %1, %2; VSSRC: + // %7 = XSMADDASP %7, %1, %3; VSSRC: // which prevents an otherwise-profitable transformation. bool OtherUsers = false, KillsAddendSrc = false; for (auto J = std::prev(I), JE = MachineBasicBlock::iterator(AddendMI); @@ -177,11 +177,11 @@ namespace { // The transformation doesn't work well with things like: - // %vreg5 = A-form-op %vreg5, %vreg11, %vreg5; - // unless vreg11 is also a kill, so skip when it is not, + // %5 = A-form-op %5, %11, %5; + // unless %11 is also a kill, so skip when it is not, // and check operand 3 to see it is also a kill to handle the case: - // %vreg5 = A-form-op %vreg5, %vreg5, %vreg11; - // where vreg5 and vreg11 are both kills. This case would be skipped + // %5 = A-form-op %5, %5, %11; + // where %5 and %11 are both kills. This case would be skipped // otherwise. unsigned OldFMAReg = MI.getOperand(0).getReg(); diff --git a/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp b/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp index c51368d6d2af3..0320ecaf85377 100644 --- a/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp +++ b/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp @@ -966,7 +966,7 @@ LLVM_DUMP_METHOD void PPCVSXSwapRemoval::dumpSwapVector() { dbgs() << format("%6d", ID); dbgs() << format("%6d", EC->getLeaderValue(ID)); - dbgs() << format(" BB#%3d", MI->getParent()->getNumber()); + dbgs() << format(" %bb.%3d", MI->getParent()->getNumber()); dbgs() << format(" %14s ", TII->getName(MI->getOpcode()).str().c_str()); if (SwapVector[EntryIdx].IsLoad) diff --git a/lib/Target/PowerPC/README.txt b/lib/Target/PowerPC/README.txt index bc09d5f8a7e8e..b4bf635dc2c75 100644 --- a/lib/Target/PowerPC/README.txt +++ b/lib/Target/PowerPC/README.txt @@ -256,7 +256,7 @@ _clamp0g: cmpwi cr0, r3, 0 li r2, 0 blt cr0, LBB1_2 -; BB#1: ; %entry +; %bb.1: ; %entry mr r2, r3 LBB1_2: ; %entry mr r3, r2 diff --git a/lib/Target/PowerPC/README_ALTIVEC.txt b/lib/Target/PowerPC/README_ALTIVEC.txt index f70ebd82bd5c9..c38e019231611 100644 --- a/lib/Target/PowerPC/README_ALTIVEC.txt +++ b/lib/Target/PowerPC/README_ALTIVEC.txt @@ -233,7 +233,7 @@ declare <16 x i8> @llvm.ppc.altivec.crypto.vpmsumb(<16 x i8>, <16 x i8>) #1 Produces the following code with -mtriple=powerpc64-unknown-linux-gnu: -# BB#0: # %entry +# %bb.0: # %entry addis 3, 2, .LCPI0_0@toc@ha addis 4, 2, .LCPI0_1@toc@ha addi 3, 3, .LCPI0_0@toc@l diff --git a/lib/Target/README.txt b/lib/Target/README.txt index f0fd323bb582b..563aee9e1a780 100644 --- a/lib/Target/README.txt +++ b/lib/Target/README.txt @@ -1778,7 +1778,7 @@ We do get this at the codegen level, so something knows about it, but instcombine should catch it earlier: _foo: ## @foo -## BB#0: ## %entry +## %bb.0: ## %entry movl %edi, %eax sarl $4, %eax ret @@ -2234,13 +2234,13 @@ void foo(funcs f, int which) { which we compile to: foo: # @foo -# BB#0: # %entry +# %bb.0: # %entry pushq %rbp movq %rsp, %rbp testl %esi, %esi movq %rdi, %rax je .LBB0_2 -# BB#1: # %if.then +# %bb.1: # %if.then movl $5, %edi callq *%rax popq %rbp diff --git a/lib/Target/SystemZ/SystemZISelLowering.cpp b/lib/Target/SystemZ/SystemZISelLowering.cpp index d49d7316e682b..ad14e5e34e2ec 100644 --- a/lib/Target/SystemZ/SystemZISelLowering.cpp +++ b/lib/Target/SystemZ/SystemZISelLowering.cpp @@ -1844,11 +1844,14 @@ static void adjustSubwordCmp(SelectionDAG &DAG, const SDLoc &DL, ISD::SEXTLOAD : ISD::ZEXTLOAD); if (C.Op0.getValueType() != MVT::i32 || - Load->getExtensionType() != ExtType) + Load->getExtensionType() != ExtType) { C.Op0 = DAG.getExtLoad(ExtType, SDLoc(Load), MVT::i32, Load->getChain(), Load->getBasePtr(), Load->getPointerInfo(), Load->getMemoryVT(), Load->getAlignment(), Load->getMemOperand()->getFlags()); + // Update the chain uses. + DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), C.Op0.getValue(1)); + } // Make sure that the second operand is an i32 with the right value. if (C.Op1.getValueType() != MVT::i32 || @@ -2940,9 +2943,13 @@ SDValue SystemZTargetLowering::lowerBITCAST(SDValue Op, // but we need this case for bitcasts that are created during lowering // and which are then lowered themselves. if (auto *LoadN = dyn_cast(In)) - if (ISD::isNormalLoad(LoadN)) - return DAG.getLoad(ResVT, DL, LoadN->getChain(), LoadN->getBasePtr(), - LoadN->getMemOperand()); + if (ISD::isNormalLoad(LoadN)) { + SDValue NewLoad = DAG.getLoad(ResVT, DL, LoadN->getChain(), + LoadN->getBasePtr(), LoadN->getMemOperand()); + // Update the chain uses. + DAG.ReplaceAllUsesOfValueWith(SDValue(LoadN, 1), NewLoad.getValue(1)); + return NewLoad; + } if (InVT == MVT::i32 && ResVT == MVT::f32) { SDValue In64; diff --git a/lib/Target/SystemZ/SystemZMachineScheduler.cpp b/lib/Target/SystemZ/SystemZMachineScheduler.cpp index 4b0f925676361..08eb73fc362ea 100644 --- a/lib/Target/SystemZ/SystemZMachineScheduler.cpp +++ b/lib/Target/SystemZ/SystemZMachineScheduler.cpp @@ -74,7 +74,7 @@ advanceTo(MachineBasicBlock::iterator NextBegin) { void SystemZPostRASchedStrategy::enterMBB(MachineBasicBlock *NextMBB) { assert ((SchedStates.find(NextMBB) == SchedStates.end()) && "Entering MBB twice?"); - DEBUG (dbgs() << "+++ Entering MBB#" << NextMBB->getNumber()); + DEBUG(dbgs() << "+++ Entering " << printMBBReference(*NextMBB)); MBB = NextMBB; /// Create a HazardRec for MBB, save it in SchedStates and set HazardRec to @@ -93,8 +93,8 @@ void SystemZPostRASchedStrategy::enterMBB(MachineBasicBlock *NextMBB) { SchedStates.find(SinglePredMBB) == SchedStates.end()) return; - DEBUG (dbgs() << "+++ Continued scheduling from MBB#" - << SinglePredMBB->getNumber() << "\n";); + DEBUG(dbgs() << "+++ Continued scheduling from " + << printMBBReference(*SinglePredMBB) << "\n";); HazardRec->copyState(SchedStates[SinglePredMBB]); @@ -113,7 +113,7 @@ void SystemZPostRASchedStrategy::enterMBB(MachineBasicBlock *NextMBB) { } void SystemZPostRASchedStrategy::leaveMBB() { - DEBUG (dbgs() << "+++ Leaving MBB#" << MBB->getNumber() << "\n";); + DEBUG(dbgs() << "+++ Leaving " << printMBBReference(*MBB) << "\n";); // Advance to first terminator. The successor block will handle terminators // dependent on CFG layout (T/NT branch etc). diff --git a/lib/Target/WebAssembly/WebAssemblyFixFunctionBitcasts.cpp b/lib/Target/WebAssembly/WebAssemblyFixFunctionBitcasts.cpp index 6473a2bfb5957..f1d2c00d16354 100644 --- a/lib/Target/WebAssembly/WebAssemblyFixFunctionBitcasts.cpp +++ b/lib/Target/WebAssembly/WebAssemblyFixFunctionBitcasts.cpp @@ -162,6 +162,11 @@ bool FixFunctionBitcasts::runOnModule(Module &M) { if (!Ty) continue; + // Bitcasted vararg functions occur in Emscripten's implementation of + // EM_ASM, so suppress wrappers for them for now. + if (Ty->isVarArg() || F->isVarArg()) + continue; + auto Pair = Wrappers.insert(std::make_pair(std::make_pair(F, Ty), nullptr)); if (Pair.second) Pair.first->second = CreateWrapper(F, Ty); diff --git a/lib/Target/WebAssembly/WebAssemblyFixIrreducibleControlFlow.cpp b/lib/Target/WebAssembly/WebAssemblyFixIrreducibleControlFlow.cpp index 41f315c2825b6..88daea7e36813 100644 --- a/lib/Target/WebAssembly/WebAssemblyFixIrreducibleControlFlow.cpp +++ b/lib/Target/WebAssembly/WebAssemblyFixIrreducibleControlFlow.cpp @@ -205,8 +205,7 @@ bool WebAssemblyFixIrreducibleControlFlow::VisitLoop(MachineFunction &MF, continue; unsigned Index = MIB.getInstr()->getNumExplicitOperands() - 1; - DEBUG(dbgs() << "MBB#" << MBB->getNumber() << " has index " << Index - << "\n"); + DEBUG(dbgs() << printMBBReference(*MBB) << " has index " << Index << "\n"); Pair.first->second = Index; for (auto Pred : MBB->predecessors()) diff --git a/lib/Target/X86/AsmParser/X86AsmParser.cpp b/lib/Target/X86/AsmParser/X86AsmParser.cpp index 4dc0466344b71..87c65347e334d 100644 --- a/lib/Target/X86/AsmParser/X86AsmParser.cpp +++ b/lib/Target/X86/AsmParser/X86AsmParser.cpp @@ -1098,19 +1098,31 @@ bool X86AsmParser::ParseRegister(unsigned &RegNo, EndLoc = Parser.getTok().getEndLoc(); - // If this is "db[0-7]", match it as an alias - // for dr[0-7]. - if (RegNo == 0 && Tok.getString().size() == 3 && - Tok.getString().startswith("db")) { - switch (Tok.getString()[2]) { - case '0': RegNo = X86::DR0; break; - case '1': RegNo = X86::DR1; break; - case '2': RegNo = X86::DR2; break; - case '3': RegNo = X86::DR3; break; - case '4': RegNo = X86::DR4; break; - case '5': RegNo = X86::DR5; break; - case '6': RegNo = X86::DR6; break; - case '7': RegNo = X86::DR7; break; + // If this is "db[0-15]", match it as an alias + // for dr[0-15]. + if (RegNo == 0 && Tok.getString().startswith("db")) { + if (Tok.getString().size() == 3) { + switch (Tok.getString()[2]) { + case '0': RegNo = X86::DR0; break; + case '1': RegNo = X86::DR1; break; + case '2': RegNo = X86::DR2; break; + case '3': RegNo = X86::DR3; break; + case '4': RegNo = X86::DR4; break; + case '5': RegNo = X86::DR5; break; + case '6': RegNo = X86::DR6; break; + case '7': RegNo = X86::DR7; break; + case '8': RegNo = X86::DR8; break; + case '9': RegNo = X86::DR9; break; + } + } else if (Tok.getString().size() == 4 && Tok.getString()[2] == '1') { + switch (Tok.getString()[3]) { + case '0': RegNo = X86::DR10; break; + case '1': RegNo = X86::DR11; break; + case '2': RegNo = X86::DR12; break; + case '3': RegNo = X86::DR13; break; + case '4': RegNo = X86::DR14; break; + case '5': RegNo = X86::DR15; break; + } } if (RegNo != 0) { diff --git a/lib/Target/X86/MCTargetDesc/X86MCAsmInfo.cpp b/lib/Target/X86/MCTargetDesc/X86MCAsmInfo.cpp index 1538a515f4190..cfd3b9283ce21 100644 --- a/lib/Target/X86/MCTargetDesc/X86MCAsmInfo.cpp +++ b/lib/Target/X86/MCTargetDesc/X86MCAsmInfo.cpp @@ -27,11 +27,11 @@ enum AsmWriterFlavorTy { ATT = 0, Intel = 1 }; -static cl::opt -AsmWriterFlavor("x86-asm-syntax", cl::init(ATT), - cl::desc("Choose style of code to emit from X86 backend:"), - cl::values(clEnumValN(ATT, "att", "Emit AT&T-style assembly"), - clEnumValN(Intel, "intel", "Emit Intel-style assembly"))); +static cl::opt AsmWriterFlavor( + "x86-asm-syntax", cl::init(ATT), cl::Hidden, + cl::desc("Choose style of code to emit from X86 backend:"), + cl::values(clEnumValN(ATT, "att", "Emit AT&T-style assembly"), + clEnumValN(Intel, "intel", "Emit Intel-style assembly"))); static cl::opt MarkedJTDataRegions("mark-data-regions", cl::init(true), diff --git a/lib/Target/X86/README.txt b/lib/Target/X86/README.txt index 799157c926e65..11652af9f1fcb 100644 --- a/lib/Target/X86/README.txt +++ b/lib/Target/X86/README.txt @@ -987,11 +987,11 @@ bb7: ; preds = %entry to: foo: # @foo -# BB#0: # %entry +# %bb.0: # %entry movl 4(%esp), %ecx cmpb $0, 16(%esp) je .LBB0_2 -# BB#1: # %bb +# %bb.1: # %bb movl 8(%esp), %eax addl %ecx, %eax ret @@ -1073,7 +1073,7 @@ declare void @exit(i32) noreturn nounwind This compiles into: _abort_gzip: ## @abort_gzip -## BB#0: ## %entry +## %bb.0: ## %entry subl $12, %esp movb _in_exit.4870.b, %al cmpb $1, %al @@ -1396,7 +1396,7 @@ define i32 @bar(%struct.B* nocapture %a) nounwind readonly optsize { } bar: # @bar -# BB#0: +# %bb.0: movb (%rdi), %al andb $1, %al movzbl %al, %eax @@ -1633,7 +1633,7 @@ In the real code, we get a lot more wrong than this. However, even in this code we generate: _foo: ## @foo -## BB#0: ## %entry +## %bb.0: ## %entry movb (%rsi), %al movb (%rdi), %cl cmpb %al, %cl @@ -1646,12 +1646,12 @@ LBB0_2: ## %if.end movb 1(%rdi), %cl cmpb %al, %cl jne LBB0_1 -## BB#3: ## %if.end38 +## %bb.3: ## %if.end38 movb 2(%rsi), %al movb 2(%rdi), %cl cmpb %al, %cl jne LBB0_1 -## BB#4: ## %if.end60 +## %bb.4: ## %if.end60 movb 3(%rdi), %al cmpb 3(%rsi), %al LBB0_5: ## %if.end60 diff --git a/lib/Target/X86/X86FixupBWInsts.cpp b/lib/Target/X86/X86FixupBWInsts.cpp index ce559323efcba..2e39cb0d79799 100644 --- a/lib/Target/X86/X86FixupBWInsts.cpp +++ b/lib/Target/X86/X86FixupBWInsts.cpp @@ -188,16 +188,17 @@ bool FixupBWInstPass::runOnMachineFunction(MachineFunction &MF) { /// necessary (e.g. due to register coalescing with a "truncate" copy). /// So, it handles pattern like this: /// -/// BB#2: derived from LLVM BB %if.then +/// %bb.2: derived from LLVM BB %if.then /// Live Ins: %rdi -/// Predecessors according to CFG: BB#0 -/// %ax = MOV16rm %rdi, 1, %noreg, 0, %noreg, %eax; mem:LD2[%p] +/// Predecessors according to CFG: %bb.0 +/// %ax = MOV16rm %rdi, 1, %noreg, 0, %noreg, %eax; +/// mem:LD2[%p] /// No %eax -/// Successors according to CFG: BB#3(?%) +/// Successors according to CFG: %bb.3(?%) /// -/// BB#3: derived from LLVM BB %if.end +/// %bb.3: derived from LLVM BB %if.end /// Live Ins: %eax Only %ax is actually live -/// Predecessors according to CFG: BB#2 BB#1 +/// Predecessors according to CFG: %bb.2 %bb.1 /// %ax = KILL %ax, %eax /// RET 0, %ax static bool isLive(const MachineInstr &MI, diff --git a/lib/Target/X86/X86FloatingPoint.cpp b/lib/Target/X86/X86FloatingPoint.cpp index 6db02f0bd05f8..b73a08846e916 100644 --- a/lib/Target/X86/X86FloatingPoint.cpp +++ b/lib/Target/X86/X86FloatingPoint.cpp @@ -499,7 +499,7 @@ bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) { /// setupBlockStack - Use the live bundles to set up our model of the stack /// to match predecessors' live out stack. void FPS::setupBlockStack() { - DEBUG(dbgs() << "\nSetting up live-ins for BB#" << MBB->getNumber() + DEBUG(dbgs() << "\nSetting up live-ins for " << printMBBReference(*MBB) << " derived from " << MBB->getName() << ".\n"); StackTop = 0; // Get the live-in bundle for MBB. @@ -538,7 +538,7 @@ void FPS::finishBlockStack() { if (MBB->succ_empty()) return; - DEBUG(dbgs() << "Setting up live-outs for BB#" << MBB->getNumber() + DEBUG(dbgs() << "Setting up live-outs for " << printMBBReference(*MBB) << " derived from " << MBB->getName() << ".\n"); // Get MBB's live-out bundle. diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 36c284b0bc180..073b4e01377aa 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -399,7 +399,7 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM, setTruncStoreAction(MVT::f80, MVT::f16, Expand); if (Subtarget.hasPOPCNT()) { - setOperationAction(ISD::CTPOP , MVT::i8 , Promote); + setOperationPromotedToType(ISD::CTPOP, MVT::i8, MVT::i32); } else { setOperationAction(ISD::CTPOP , MVT::i8 , Expand); setOperationAction(ISD::CTPOP , MVT::i16 , Expand); @@ -1127,6 +1127,10 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM, } if (HasInt256) { + // Custom legalize 2x32 to get a little better code. + setOperationAction(ISD::MGATHER, MVT::v2f32, Custom); + setOperationAction(ISD::MGATHER, MVT::v2i32, Custom); + for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64, MVT::v4f32, MVT::v8f32, MVT::v2f64, MVT::v4f64 }) setOperationAction(ISD::MGATHER, VT, Custom); @@ -1322,6 +1326,14 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM, setOperationAction(ISD::CTTZ, VT, Custom); } + // NonVLX sub-targets extend 128/256 vectors to use the 512 version. + for (auto VT : { MVT::v2i64, MVT::v4i64 }) { + setOperationAction(ISD::SMAX, VT, Legal); + setOperationAction(ISD::UMAX, VT, Legal); + setOperationAction(ISD::SMIN, VT, Legal); + setOperationAction(ISD::UMIN, VT, Legal); + } + // NonVLX sub-targets extend 128/256 vectors to use the 512 version. for (auto VT : {MVT::v4i32, MVT::v8i32, MVT::v16i32, MVT::v2i64, MVT::v4i64, MVT::v8i64}) { @@ -1360,11 +1372,6 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM, setOperationAction(ISD::CTPOP, VT, Legal); } - // Custom legalize 2x32 to get a little better code. - if (Subtarget.hasVLX()) { - setOperationAction(ISD::MGATHER, MVT::v2f32, Custom); - } - // Custom lower several nodes. for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64, MVT::v4f32, MVT::v8f32, MVT::v2f64, MVT::v4f64 }) @@ -1533,13 +1540,6 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM, setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i1, Custom); setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Custom); setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4i1, Custom); - - for (auto VT : { MVT::v2i64, MVT::v4i64 }) { - setOperationAction(ISD::SMAX, VT, Legal); - setOperationAction(ISD::UMAX, VT, Legal); - setOperationAction(ISD::SMIN, VT, Legal); - setOperationAction(ISD::UMIN, VT, Legal); - } } // We want to custom lower some of our intrinsics. @@ -6950,10 +6950,10 @@ static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec, // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already // lowered this: - // (extract_vector_elt (v8f32 %vreg1), Constant<6>) + // (extract_vector_elt (v8f32 %1), Constant<6>) // to: // (extract_vector_elt (vector_shuffle<2,u,u,u> - // (extract_subvector (v8f32 %vreg0), Constant<4>), + // (extract_subvector (v8f32 %0), Constant<4>), // undef) // Constant<0>) // In this case the vector is the extract_subvector expression and the index @@ -15808,12 +15808,6 @@ SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, SDLoc dl(Op); auto PtrVT = getPointerTy(DAG.getDataLayout()); - // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't - // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform - // the optimization here. - if (DAG.SignBitIsZero(N0)) - return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0); - if (Op.getSimpleValueType().isVector()) return lowerUINT_TO_FP_vec(Op, DAG); @@ -17690,7 +17684,8 @@ static SDValue LowerVSETCC(SDValue Op, const X86Subtarget &Subtarget, // Special case: Use min/max operations for SETULE/SETUGE MVT VET = VT.getVectorElementType(); bool HasMinMax = - (Subtarget.hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32)) || + (Subtarget.hasAVX512() && VET == MVT::i64) || + (Subtarget.hasSSE41() && (VET == MVT::i16 || VET == MVT::i32)) || (Subtarget.hasSSE2() && (VET == MVT::i8)); bool MinMax = false; if (HasMinMax) { @@ -24277,6 +24272,10 @@ static SDValue LowerMGATHER(SDValue Op, const X86Subtarget &Subtarget, unsigned NumElts = VT.getVectorNumElements(); assert(VT.getScalarSizeInBits() >= 32 && "Unsupported gather op"); + // If the index is v2i32, we're being called by type legalization. + if (IndexVT == MVT::v2i32) + return SDValue(); + if (Subtarget.hasAVX512() && !Subtarget.hasVLX() && !VT.is512BitVector() && !Index.getSimpleValueType().is512BitVector()) { // AVX512F supports only 512-bit vectors. Or data or index should @@ -24321,39 +24320,6 @@ static SDValue LowerMGATHER(SDValue Op, const X86Subtarget &Subtarget, SDValue RetOps[] = {Extract, NewGather.getValue(2)}; return DAG.getMergeValues(RetOps, dl); } - if (N->getMemoryVT() == MVT::v2i32) { - // There is a special case when the return type is v2i32 is illegal and - // the type legaizer extended it to v2i64. Without this conversion we end up - // with VPGATHERQQ (reading q-words from the memory) instead of VPGATHERQD. - // In order to avoid this situation, we'll build an X86 specific Gather node - // with index v2i64 and value type v4i32. - assert(VT == MVT::v2i64 && Src0.getValueType() == MVT::v2i64 && - "Unexpected type in masked gather"); - Src0 = - DAG.getVectorShuffle(MVT::v4i32, dl, DAG.getBitcast(MVT::v4i32, Src0), - DAG.getUNDEF(MVT::v4i32), { 0, 2, -1, -1 }); - // The mask should match the destination type. Extending mask with zeroes - // is not necessary since instruction itself reads only two values from - // memory. - SDVTList VTList; - if (Subtarget.hasVLX()) { - Mask = ExtendToType(Mask, MVT::v4i1, DAG, false); - VTList = DAG.getVTList(MVT::v4i32, MVT::v2i1, MVT::Other); - } else { - Mask = - DAG.getVectorShuffle(MVT::v4i32, dl, DAG.getBitcast(MVT::v4i32, Mask), - DAG.getUNDEF(MVT::v4i32), {0, 2, -1, -1}); - VTList = DAG.getVTList(MVT::v4i32, MVT::v4i32, MVT::Other); - } - SDValue Ops[] = { N->getChain(), Src0, Mask, N->getBasePtr(), Index }; - SDValue NewGather = DAG.getTargetMemSDNode( - VTList, Ops, dl, N->getMemoryVT(), N->getMemOperand()); - - SDValue Sext = getExtendInVec(X86ISD::VSEXT, dl, MVT::v2i64, - NewGather.getValue(0), DAG); - SDValue RetOps[] = { Sext, NewGather.getValue(2) }; - return DAG.getMergeValues(RetOps, dl); - } SDValue Ops[] = { N->getChain(), Src0, Mask, N->getBasePtr(), Index }; SDValue NewGather = DAG.getTargetMemSDNode( @@ -24863,7 +24829,7 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N, } case ISD::MGATHER: { EVT VT = N->getValueType(0); - if (VT == MVT::v2f32 && Subtarget.hasVLX()) { + if (VT == MVT::v2f32 && (Subtarget.hasVLX() || !Subtarget.hasAVX512())) { auto *Gather = cast(N); SDValue Index = Gather->getIndex(); if (Index.getValueType() != MVT::v2i64) @@ -24873,15 +24839,74 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N, SDValue Src0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32, Gather->getValue(), DAG.getUNDEF(MVT::v2f32)); + if (!Subtarget.hasVLX()) { + // We need to widen the mask, but the instruction will only use 2 + // of its elements. So we can use undef. + Mask = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4i1, Mask, + DAG.getUNDEF(MVT::v2i1)); + Mask = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, Mask); + } SDValue Ops[] = { Gather->getChain(), Src0, Mask, Gather->getBasePtr(), Index }; SDValue Res = DAG.getTargetMemSDNode( - DAG.getVTList(MVT::v4f32, MVT::v2i1, MVT::Other), Ops, dl, + DAG.getVTList(MVT::v4f32, Mask.getValueType(), MVT::Other), Ops, dl, Gather->getMemoryVT(), Gather->getMemOperand()); Results.push_back(Res); Results.push_back(Res.getValue(2)); return; } + if (VT == MVT::v2i32) { + auto *Gather = cast(N); + SDValue Index = Gather->getIndex(); + SDValue Mask = Gather->getMask(); + assert(Mask.getValueType() == MVT::v2i1 && "Unexpected mask type"); + SDValue Src0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4i32, + Gather->getValue(), + DAG.getUNDEF(MVT::v2i32)); + // If the index is v2i64 we can use it directly. + if (Index.getValueType() == MVT::v2i64 && + (Subtarget.hasVLX() || !Subtarget.hasAVX512())) { + if (!Subtarget.hasVLX()) { + // We need to widen the mask, but the instruction will only use 2 + // of its elements. So we can use undef. + Mask = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4i1, Mask, + DAG.getUNDEF(MVT::v2i1)); + Mask = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, Mask); + } + SDValue Ops[] = { Gather->getChain(), Src0, Mask, Gather->getBasePtr(), + Index }; + SDValue Res = DAG.getTargetMemSDNode( + DAG.getVTList(MVT::v4i32, Mask.getValueType(), MVT::Other), Ops, dl, + Gather->getMemoryVT(), Gather->getMemOperand()); + SDValue Chain = Res.getValue(2); + if (!ExperimentalVectorWideningLegalization) + Res = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i32, Res, + DAG.getIntPtrConstant(0, dl)); + Results.push_back(Res); + Results.push_back(Chain); + return; + } + EVT IndexVT = Index.getValueType(); + EVT NewIndexVT = EVT::getVectorVT(*DAG.getContext(), + IndexVT.getScalarType(), 4); + // Otherwise we need to custom widen everything to avoid promotion. + Index = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewIndexVT, Index, + DAG.getUNDEF(IndexVT)); + Mask = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4i1, Mask, + DAG.getConstant(0, dl, MVT::v2i1)); + SDValue Ops[] = { Gather->getChain(), Src0, Mask, Gather->getBasePtr(), + Index }; + SDValue Res = DAG.getMaskedGather(DAG.getVTList(MVT::v4i32, MVT::Other), + Gather->getMemoryVT(), dl, Ops, + Gather->getMemOperand()); + SDValue Chain = Res.getValue(1); + if (!ExperimentalVectorWideningLegalization) + Res = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i32, Res, + DAG.getIntPtrConstant(0, dl)); + Results.push_back(Res); + Results.push_back(Chain); + return; + } break; } } @@ -35924,7 +35949,8 @@ static SDValue combineSetCC(SDNode *N, SelectionDAG &DAG, } static SDValue combineGatherScatter(SDNode *N, SelectionDAG &DAG, - TargetLowering::DAGCombinerInfo &DCI) { + TargetLowering::DAGCombinerInfo &DCI, + const X86Subtarget &Subtarget) { SDLoc DL(N); // Pre-shrink oversized index elements to avoid triggering scalarization. @@ -35967,11 +35993,26 @@ static SDValue combineGatherScatter(SDNode *N, SelectionDAG &DAG, // the masks is v*i1. So the mask will be truncated anyway. // The SIGN_EXTEND_INREG my be dropped. SDValue Mask = N->getOperand(2); - if (Mask.getOpcode() == ISD::SIGN_EXTEND_INREG) { + if (Subtarget.hasAVX512() && Mask.getOpcode() == ISD::SIGN_EXTEND_INREG) { SmallVector NewOps(N->op_begin(), N->op_end()); NewOps[2] = Mask.getOperand(0); DAG.UpdateNodeOperands(N, NewOps); } + + // With AVX2 we only demand the upper bit of the mask. + if (!Subtarget.hasAVX512()) { + const TargetLowering &TLI = DAG.getTargetLoweringInfo(); + TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), + !DCI.isBeforeLegalizeOps()); + KnownBits Known; + APInt DemandedMask(APInt::getSignMask(Mask.getScalarValueSizeInBits())); + if (TLI.SimplifyDemandedBits(Mask, DemandedMask, Known, TLO)) { + DCI.AddToWorklist(Mask.getNode()); + DCI.CommitTargetLoweringOpt(TLO); + return SDValue(N, 0); + } + } + return SDValue(); } @@ -37078,8 +37119,10 @@ SDValue X86TargetLowering::PerformDAGCombine(SDNode *N, case X86ISD::FMSUBADD_RND: case X86ISD::FMADDSUB: case X86ISD::FMSUBADD: return combineFMADDSUB(N, DAG, Subtarget); + case X86ISD::MGATHER: + case X86ISD::MSCATTER: case ISD::MGATHER: - case ISD::MSCATTER: return combineGatherScatter(N, DAG, DCI); + case ISD::MSCATTER: return combineGatherScatter(N, DAG, DCI, Subtarget); case X86ISD::TESTM: return combineTestM(N, DAG, Subtarget); case X86ISD::PCMPEQ: case X86ISD::PCMPGT: return combineVectorCompare(N, DAG, Subtarget); diff --git a/lib/Target/X86/X86InstrAVX512.td b/lib/Target/X86/X86InstrAVX512.td index 5d97c21587a60..7a4ba0eae733c 100644 --- a/lib/Target/X86/X86InstrAVX512.td +++ b/lib/Target/X86/X86InstrAVX512.td @@ -352,12 +352,13 @@ multiclass AVX512_maskable_in_asm O, Format F, X86VectorVTInfo _, dag Outs, dag Ins, string OpcodeStr, string AttSrcAsm, string IntelSrcAsm, - list Pattern> : + list Pattern, + InstrItinClass itin = NoItinerary> : AVX512_maskable_custom; + "$src0 = $dst", itin>; // Instruction with mask that puts result in mask register, @@ -369,17 +370,18 @@ multiclass AVX512_maskable_custom_cmp O, Format F, string AttSrcAsm, string IntelSrcAsm, list Pattern, list MaskingPattern, + InstrItinClass itin = NoItinerary, bit IsCommutable = 0> { let isCommutable = IsCommutable in def NAME: AVX512; + Pattern, itin>; def NAME#k: AVX512, EVEX_K; + MaskingPattern, itin>, EVEX_K; } multiclass AVX512_maskable_common_cmp O, Format F, X86VectorVTInfo _, @@ -388,27 +390,30 @@ multiclass AVX512_maskable_common_cmp O, Format F, X86VectorVTInfo _, string OpcodeStr, string AttSrcAsm, string IntelSrcAsm, dag RHS, dag MaskingRHS, + InstrItinClass itin = NoItinerary, bit IsCommutable = 0> : AVX512_maskable_custom_cmp; + [(set _.KRC:$dst, MaskingRHS)], itin, IsCommutable>; multiclass AVX512_maskable_cmp O, Format F, X86VectorVTInfo _, dag Outs, dag Ins, string OpcodeStr, string AttSrcAsm, string IntelSrcAsm, - dag RHS, bit IsCommutable = 0> : + dag RHS, InstrItinClass itin = NoItinerary, + bit IsCommutable = 0> : AVX512_maskable_common_cmp; + (and _.KRCWM:$mask, RHS), itin, IsCommutable>; multiclass AVX512_maskable_cmp_alt O, Format F, X86VectorVTInfo _, dag Outs, dag Ins, string OpcodeStr, - string AttSrcAsm, string IntelSrcAsm> : + string AttSrcAsm, string IntelSrcAsm, + InstrItinClass itin = NoItinerary> : AVX512_maskable_custom_cmp; + AttSrcAsm, IntelSrcAsm, [],[], itin>; // This multiclass generates the unconditional/non-masking, the masking and // the zero-masking variant of the vector instruction. In the masking case, the @@ -488,7 +493,8 @@ let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1, multiclass vinsert_for_size_split { + SDPatternOperator vinsert_for_mask, + OpndItins itins> { let hasSideEffects = 0, ExeDomain = To.ExeDomain in { defm rr : AVX512_maskable_split, AVX512AIi8Base, EVEX_4V; - + (iPTR imm)), itins.rr>, + AVX512AIi8Base, EVEX_4V, Sched<[itins.Sched]>; let mayLoad = 1 in defm rm : AVX512_maskable_split, AVX512AIi8Base, EVEX_4V, - EVEX_CD8; + (iPTR imm)), itins.rm>, AVX512AIi8Base, EVEX_4V, + EVEX_CD8, + Sched<[itins.Sched.Folded, ReadAfterLd]>; } } // Passes the same pattern operator for masked and unmasked ops. multiclass vinsert_for_size : - vinsert_for_size_split; + SDPatternOperator vinsert_insert, + OpndItins itins> : + vinsert_for_size_split; multiclass vinsert_for_size_lowering { + ValueType EltVT64, int Opcode256, + OpndItins itins> { let Predicates = [HasVLX] in defm NAME # "32x4Z256" : vinsert_for_size, X86VectorVTInfo< 8, EltVT32, VR256X>, - vinsert128_insert>, EVEX_V256; + vinsert128_insert, itins>, EVEX_V256; defm NAME # "32x4Z" : vinsert_for_size, X86VectorVTInfo<16, EltVT32, VR512>, - vinsert128_insert>, EVEX_V512; + vinsert128_insert, itins>, EVEX_V512; defm NAME # "64x4Z" : vinsert_for_size, X86VectorVTInfo< 8, EltVT64, VR512>, - vinsert256_insert>, VEX_W, EVEX_V512; + vinsert256_insert, itins>, VEX_W, EVEX_V512; // Even with DQI we'd like to only use these instructions for masking. let Predicates = [HasVLX, HasDQI] in defm NAME # "64x2Z256" : vinsert_for_size_split, X86VectorVTInfo< 4, EltVT64, VR256X>, - null_frag, vinsert128_insert>, VEX_W, EVEX_V256; + null_frag, vinsert128_insert, itins>, + VEX_W, EVEX_V256; // Even with DQI we'd like to only use these instructions for masking. let Predicates = [HasDQI] in { defm NAME # "64x2Z" : vinsert_for_size_split, X86VectorVTInfo< 8, EltVT64, VR512>, - null_frag, vinsert128_insert>, VEX_W, EVEX_V512; + null_frag, vinsert128_insert, itins>, + VEX_W, EVEX_V512; defm NAME # "32x8Z" : vinsert_for_size_split, X86VectorVTInfo<16, EltVT32, VR512>, - null_frag, vinsert256_insert>, EVEX_V512; + null_frag, vinsert256_insert, itins>, + EVEX_V512; } } -defm VINSERTF : vinsert_for_type; -defm VINSERTI : vinsert_for_type; +// FIXME: Is there a better scheduler itinerary for VINSERTF/VINSERTI? +let Sched = WriteFShuffle256 in +def AVX512_VINSERTF : OpndItins< + IIC_SSE_SHUFP, IIC_SSE_SHUFP +>; +let Sched = WriteShuffle256 in +def AVX512_VINSERTI : OpndItins< + IIC_SSE_PSHUF_RI, IIC_SSE_PSHUF_MI +>; + +defm VINSERTF : vinsert_for_type; +defm VINSERTI : vinsert_for_type; // Codegen pattern with the alternative types, // Even with AVX512DQ we'll still use these for unmasked operations. @@ -775,7 +797,8 @@ def VINSERTPSZrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst), multiclass vextract_for_size_split { + SDPatternOperator vextract_for_mask, + OpndItins itins> { let hasSideEffects = 0, ExeDomain = To.ExeDomain in { defm rr : AVX512_maskable_split, - AVX512AIi8Base, EVEX; + (vextract_for_mask:$idx (From.VT From.RC:$src1), (iPTR imm)), + itins.rr>, AVX512AIi8Base, EVEX, Sched<[itins.Sched]>; + def mr : AVX512AIi8, EVEX; + addr:$dst)], itins.rm>, EVEX, + Sched<[itins.Sched.Folded, ReadAfterLd]>; let mayStore = 1, hasSideEffects = 0 in def mrk : AVX512AIi8, EVEX_K, EVEX; + [], itins.rm>, EVEX_K, EVEX, + Sched<[itins.Sched.Folded, ReadAfterLd]>; } } // Passes the same pattern operator for masked and unmasked ops. multiclass vextract_for_size : - vextract_for_size_split; + SDPatternOperator vextract_extract, + OpndItins itins> : + vextract_for_size_split; // Codegen pattern for the alternative types multiclass vextract_for_size_lowering { + ValueType EltVT64, int Opcode256, + OpndItins itins> { let Predicates = [HasAVX512] in { defm NAME # "32x4Z" : vextract_for_size, X86VectorVTInfo< 4, EltVT32, VR128X>, - vextract128_extract>, + vextract128_extract, itins>, EVEX_V512, EVEX_CD8<32, CD8VT4>; defm NAME # "64x4Z" : vextract_for_size, X86VectorVTInfo< 4, EltVT64, VR256X>, - vextract256_extract>, + vextract256_extract, itins>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VT4>; } let Predicates = [HasVLX] in defm NAME # "32x4Z256" : vextract_for_size, X86VectorVTInfo< 4, EltVT32, VR128X>, - vextract128_extract>, + vextract128_extract, itins>, EVEX_V256, EVEX_CD8<32, CD8VT4>; // Even with DQI we'd like to only use these instructions for masking. @@ -852,7 +880,7 @@ multiclass vextract_for_type, X86VectorVTInfo< 2, EltVT64, VR128X>, - null_frag, vextract128_extract>, + null_frag, vextract128_extract, itins>, VEX_W, EVEX_V256, EVEX_CD8<64, CD8VT2>; // Even with DQI we'd like to only use these instructions for masking. @@ -860,18 +888,28 @@ multiclass vextract_for_type, X86VectorVTInfo< 2, EltVT64, VR128X>, - null_frag, vextract128_extract>, + null_frag, vextract128_extract, itins>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VT2>; defm NAME # "32x8Z" : vextract_for_size_split, X86VectorVTInfo< 8, EltVT32, VR256X>, - null_frag, vextract256_extract>, + null_frag, vextract256_extract, itins>, EVEX_V512, EVEX_CD8<32, CD8VT8>; } } -defm VEXTRACTF : vextract_for_type; -defm VEXTRACTI : vextract_for_type; +// FIXME: Is there a better scheduler itinerary for VEXTRACTF/VEXTRACTI? +let Sched = WriteFShuffle256 in +def AVX512_VEXTRACTF : OpndItins< + IIC_SSE_SHUFP, IIC_SSE_SHUFP +>; +let Sched = WriteShuffle256 in +def AVX512_VEXTRACTI : OpndItins< + IIC_SSE_PSHUF_RI, IIC_SSE_PSHUF_MI +>; + +defm VEXTRACTF : vextract_for_type; +defm VEXTRACTI : vextract_for_type; // extract_subvector codegen patterns with the alternative types. // Even with AVX512DQ we'll still use these for unmasked operations. @@ -1568,7 +1606,19 @@ defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q", //===----------------------------------------------------------------------===// // -- VPERMI2 - 3 source operands form -- -multiclass avx512_perm_i opc, string OpcodeStr, X86VectorVTInfo _> { + +let Sched = WriteFShuffle256 in +def AVX512_PERM2_F : OpndItins< + IIC_SSE_SHUFP, IIC_SSE_SHUFP +>; + +let Sched = WriteShuffle256 in +def AVX512_PERM2_I : OpndItins< + IIC_SSE_PSHUF_RI, IIC_SSE_PSHUF_MI +>; + +multiclass avx512_perm_i opc, string OpcodeStr, OpndItins itins, + X86VectorVTInfo _> { let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain in { // The index operand in the pattern should really be an integer type. However, // if we do that and it happens to come from a bitcast, then it becomes @@ -1579,17 +1629,18 @@ let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain in { (ins _.RC:$src2, _.RC:$src3), OpcodeStr, "$src3, $src2", "$src2, $src3", (_.VT (X86VPermi2X _.RC:$src1, _.RC:$src2, _.RC:$src3)), - NoItinerary, 1>, EVEX_4V, AVX5128IBase; + itins.rr, 1>, EVEX_4V, AVX5128IBase, Sched<[itins.Sched]>; defm rm: AVX512_maskable_3src, - EVEX_4V, AVX5128IBase; + (_.VT (bitconvert (_.LdFrag addr:$src3))))), itins.rm, 1>, + EVEX_4V, AVX5128IBase, Sched<[itins.Sched.Folded, ReadAfterLd]>; } } -multiclass avx512_perm_i_mb opc, string OpcodeStr, + +multiclass avx512_perm_i_mb opc, string OpcodeStr, OpndItins itins, X86VectorVTInfo _> { let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain in defm rmb: AVX512_maskable_3src opc, string OpcodeStr, !strconcat("$src2, ${src3}", _.BroadcastStr ), (_.VT (X86VPermi2X _.RC:$src1, _.RC:$src2,(_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3))))), - NoItinerary, 1>, AVX5128IBase, EVEX_4V, EVEX_B; + itins.rm, 1>, AVX5128IBase, EVEX_4V, EVEX_B, + Sched<[itins.Sched.Folded, ReadAfterLd]>; } -multiclass avx512_perm_i_sizes opc, string OpcodeStr, +multiclass avx512_perm_i_sizes opc, string OpcodeStr, OpndItins itins, AVX512VLVectorVTInfo VTInfo> { - defm NAME: avx512_perm_i, - avx512_perm_i_mb, EVEX_V512; + defm NAME: avx512_perm_i, + avx512_perm_i_mb, EVEX_V512; let Predicates = [HasVLX] in { - defm NAME#128: avx512_perm_i, - avx512_perm_i_mb, EVEX_V128; - defm NAME#256: avx512_perm_i, - avx512_perm_i_mb, EVEX_V256; + defm NAME#128: avx512_perm_i, + avx512_perm_i_mb, EVEX_V128; + defm NAME#256: avx512_perm_i, + avx512_perm_i_mb, EVEX_V256; } } multiclass avx512_perm_i_sizes_bw opc, string OpcodeStr, - AVX512VLVectorVTInfo VTInfo, - Predicate Prd> { + OpndItins itins, + AVX512VLVectorVTInfo VTInfo, + Predicate Prd> { let Predicates = [Prd] in - defm NAME: avx512_perm_i, EVEX_V512; + defm NAME: avx512_perm_i, EVEX_V512; let Predicates = [Prd, HasVLX] in { - defm NAME#128: avx512_perm_i, EVEX_V128; - defm NAME#256: avx512_perm_i, EVEX_V256; + defm NAME#128: avx512_perm_i, EVEX_V128; + defm NAME#256: avx512_perm_i, EVEX_V256; } } -defm VPERMI2D : avx512_perm_i_sizes<0x76, "vpermi2d", +defm VPERMI2D : avx512_perm_i_sizes<0x76, "vpermi2d", AVX512_PERM2_I, avx512vl_i32_info>, EVEX_CD8<32, CD8VF>; -defm VPERMI2Q : avx512_perm_i_sizes<0x76, "vpermi2q", +defm VPERMI2Q : avx512_perm_i_sizes<0x76, "vpermi2q", AVX512_PERM2_I, avx512vl_i64_info>, VEX_W, EVEX_CD8<64, CD8VF>; -defm VPERMI2W : avx512_perm_i_sizes_bw<0x75, "vpermi2w", +defm VPERMI2W : avx512_perm_i_sizes_bw<0x75, "vpermi2w", AVX512_PERM2_I, avx512vl_i16_info, HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>; -defm VPERMI2B : avx512_perm_i_sizes_bw<0x75, "vpermi2b", +defm VPERMI2B : avx512_perm_i_sizes_bw<0x75, "vpermi2b", AVX512_PERM2_I, avx512vl_i8_info, HasVBMI>, EVEX_CD8<8, CD8VF>; -defm VPERMI2PS : avx512_perm_i_sizes<0x77, "vpermi2ps", +defm VPERMI2PS : avx512_perm_i_sizes<0x77, "vpermi2ps", AVX512_PERM2_F, avx512vl_f32_info>, EVEX_CD8<32, CD8VF>; -defm VPERMI2PD : avx512_perm_i_sizes<0x77, "vpermi2pd", +defm VPERMI2PD : avx512_perm_i_sizes<0x77, "vpermi2pd", AVX512_PERM2_F, avx512vl_f64_info>, VEX_W, EVEX_CD8<64, CD8VF>; // VPERMT2 -multiclass avx512_perm_t opc, string OpcodeStr, +multiclass avx512_perm_t opc, string OpcodeStr, OpndItins itins, X86VectorVTInfo _, X86VectorVTInfo IdxVT> { let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain in { defm rr: AVX512_maskable_3src, EVEX_4V, AVX5128IBase; + itins.rr, 1>, EVEX_4V, AVX5128IBase, Sched<[itins.Sched]>; defm rm: AVX512_maskable_3src, - EVEX_4V, AVX5128IBase; + (bitconvert (_.LdFrag addr:$src3)))), itins.rm, 1>, + EVEX_4V, AVX5128IBase, Sched<[itins.Sched.Folded, ReadAfterLd]>; } } -multiclass avx512_perm_t_mb opc, string OpcodeStr, +multiclass avx512_perm_t_mb opc, string OpcodeStr, OpndItins itins, X86VectorVTInfo _, X86VectorVTInfo IdxVT> { let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain in defm rmb: AVX512_maskable_3src opc, string OpcodeStr, !strconcat("$src2, ${src3}", _.BroadcastStr ), (_.VT (X86VPermt2 _.RC:$src1, IdxVT.RC:$src2,(_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3))))), - NoItinerary, 1>, AVX5128IBase, EVEX_4V, EVEX_B; + itins.rm, 1>, AVX5128IBase, EVEX_4V, EVEX_B, + Sched<[itins.Sched.Folded, ReadAfterLd]>; } -multiclass avx512_perm_t_sizes opc, string OpcodeStr, +multiclass avx512_perm_t_sizes opc, string OpcodeStr, OpndItins itins, AVX512VLVectorVTInfo VTInfo, AVX512VLVectorVTInfo ShuffleMask> { - defm NAME: avx512_perm_t, - avx512_perm_t_mb, EVEX_V512; let Predicates = [HasVLX] in { - defm NAME#128: avx512_perm_t, - avx512_perm_t_mb, EVEX_V128; - defm NAME#256: avx512_perm_t, - avx512_perm_t_mb, EVEX_V256; } } -multiclass avx512_perm_t_sizes_bw opc, string OpcodeStr, +multiclass avx512_perm_t_sizes_bw opc, string OpcodeStr, OpndItins itins, AVX512VLVectorVTInfo VTInfo, AVX512VLVectorVTInfo Idx, Predicate Prd> { let Predicates = [Prd] in - defm NAME: avx512_perm_t, EVEX_V512; let Predicates = [Prd, HasVLX] in { - defm NAME#128: avx512_perm_t, EVEX_V128; - defm NAME#256: avx512_perm_t, EVEX_V256; } } -defm VPERMT2D : avx512_perm_t_sizes<0x7E, "vpermt2d", +defm VPERMT2D : avx512_perm_t_sizes<0x7E, "vpermt2d", AVX512_PERM2_I, avx512vl_i32_info, avx512vl_i32_info>, EVEX_CD8<32, CD8VF>; -defm VPERMT2Q : avx512_perm_t_sizes<0x7E, "vpermt2q", +defm VPERMT2Q : avx512_perm_t_sizes<0x7E, "vpermt2q", AVX512_PERM2_I, avx512vl_i64_info, avx512vl_i64_info>, VEX_W, EVEX_CD8<64, CD8VF>; -defm VPERMT2W : avx512_perm_t_sizes_bw<0x7D, "vpermt2w", +defm VPERMT2W : avx512_perm_t_sizes_bw<0x7D, "vpermt2w", AVX512_PERM2_I, avx512vl_i16_info, avx512vl_i16_info, HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>; -defm VPERMT2B : avx512_perm_t_sizes_bw<0x7D, "vpermt2b", +defm VPERMT2B : avx512_perm_t_sizes_bw<0x7D, "vpermt2b", AVX512_PERM2_I, avx512vl_i8_info, avx512vl_i8_info, HasVBMI>, EVEX_CD8<8, CD8VF>; -defm VPERMT2PS : avx512_perm_t_sizes<0x7F, "vpermt2ps", +defm VPERMT2PS : avx512_perm_t_sizes<0x7F, "vpermt2ps", AVX512_PERM2_F, avx512vl_f32_info, avx512vl_i32_info>, EVEX_CD8<32, CD8VF>; -defm VPERMT2PD : avx512_perm_t_sizes<0x7F, "vpermt2pd", +defm VPERMT2PD : avx512_perm_t_sizes<0x7F, "vpermt2pd", AVX512_PERM2_F, avx512vl_f64_info, avx512vl_i64_info>, VEX_W, EVEX_CD8<64, CD8VF>; //===----------------------------------------------------------------------===// @@ -2219,15 +2273,15 @@ defm VPCMPUQ : avx512_icmp_cc_rmb_vl<0x1E, "uq", X86cmpmu, avx512vl_i64_info, HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>; -multiclass avx512_vcmp_common { - +multiclass avx512_vcmp_common { defm rri : AVX512_maskable_cmp<0xC2, MRMSrcReg, _, (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2,AVXCC:$cc), "vcmp${cc}"#_.Suffix, "$src2, $src1", "$src1, $src2", (X86cmpm (_.VT _.RC:$src1), (_.VT _.RC:$src2), - imm:$cc), 1>; + imm:$cc), itins.rr, 1>, + Sched<[itins.Sched]>; defm rmi : AVX512_maskable_cmp<0xC2, MRMSrcMem, _, (outs _.KRC:$dst),(ins _.RC:$src1, _.MemOp:$src2, AVXCC:$cc), @@ -2235,7 +2289,8 @@ multiclass avx512_vcmp_common { "$src2, $src1", "$src1, $src2", (X86cmpm (_.VT _.RC:$src1), (_.VT (bitconvert (_.LdFrag addr:$src2))), - imm:$cc)>; + imm:$cc), itins.rm>, + Sched<[itins.Sched.Folded, ReadAfterLd]>; defm rmbi : AVX512_maskable_cmp<0xC2, MRMSrcMem, _, (outs _.KRC:$dst), @@ -2245,28 +2300,32 @@ multiclass avx512_vcmp_common { "$src1, ${src2}"##_.BroadcastStr, (X86cmpm (_.VT _.RC:$src1), (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))), - imm:$cc)>,EVEX_B; + imm:$cc), itins.rm>, + EVEX_B, Sched<[itins.Sched.Folded, ReadAfterLd]>; // Accept explicit immediate argument form instead of comparison code. let isAsmParserOnly = 1, hasSideEffects = 0 in { defm rri_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _, (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, u8imm:$cc), "vcmp"#_.Suffix, - "$cc, $src2, $src1", "$src1, $src2, $cc">; + "$cc, $src2, $src1", "$src1, $src2, $cc", itins.rr>, + Sched<[itins.Sched]>; let mayLoad = 1 in { defm rmi_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcMem, _, (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc), "vcmp"#_.Suffix, - "$cc, $src2, $src1", "$src1, $src2, $cc">; + "$cc, $src2, $src1", "$src1, $src2, $cc", itins.rm>, + Sched<[itins.Sched.Folded, ReadAfterLd]>; defm rmbi_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcMem, _, (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$cc), "vcmp"#_.Suffix, "$cc, ${src2}"##_.BroadcastStr##", $src1", - "$src1, ${src2}"##_.BroadcastStr##", $cc">,EVEX_B; + "$src1, ${src2}"##_.BroadcastStr##", $cc", itins.rm>, + EVEX_B, Sched<[itins.Sched.Folded, ReadAfterLd]>; } } @@ -2297,7 +2356,7 @@ multiclass avx512_vcmp_common { imm:$cc)>; } -multiclass avx512_vcmp_sae { +multiclass avx512_vcmp_sae { // comparison code form (VCMP[EQ/LT/LE/...] defm rrib : AVX512_maskable_cmp<0xC2, MRMSrcReg, _, (outs _.KRC:$dst),(ins _.RC:$src1, _.RC:$src2, AVXCC:$cc), @@ -2306,7 +2365,8 @@ multiclass avx512_vcmp_sae { (X86cmpmRnd (_.VT _.RC:$src1), (_.VT _.RC:$src2), imm:$cc, - (i32 FROUND_NO_EXC))>, EVEX_B; + (i32 FROUND_NO_EXC)), itins.rr>, + EVEX_B, Sched<[itins.Sched]>; let isAsmParserOnly = 1, hasSideEffects = 0 in { defm rrib_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _, @@ -2314,25 +2374,26 @@ multiclass avx512_vcmp_sae { (ins _.RC:$src1, _.RC:$src2, u8imm:$cc), "vcmp"#_.Suffix, "$cc, {sae}, $src2, $src1", - "$src1, $src2, {sae}, $cc">, EVEX_B; + "$src1, $src2, {sae}, $cc", itins.rr>, + EVEX_B, Sched<[itins.Sched]>; } } -multiclass avx512_vcmp { +multiclass avx512_vcmp { let Predicates = [HasAVX512] in { - defm Z : avx512_vcmp_common<_.info512>, - avx512_vcmp_sae<_.info512>, EVEX_V512; + defm Z : avx512_vcmp_common, + avx512_vcmp_sae, EVEX_V512; } let Predicates = [HasAVX512,HasVLX] in { - defm Z128 : avx512_vcmp_common<_.info128>, EVEX_V128; - defm Z256 : avx512_vcmp_common<_.info256>, EVEX_V256; + defm Z128 : avx512_vcmp_common, EVEX_V128; + defm Z256 : avx512_vcmp_common, EVEX_V256; } } -defm VCMPPD : avx512_vcmp, +defm VCMPPD : avx512_vcmp, AVX512PDIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W; -defm VCMPPS : avx512_vcmp, +defm VCMPPS : avx512_vcmp, AVX512PSIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>; @@ -2352,34 +2413,39 @@ let Predicates = [HasAVX512] in { //handle fpclass instruction mask = op(reg_scalar,imm) // op(mem_scalar,imm) multiclass avx512_scalar_fpclass opc, string OpcodeStr, SDNode OpNode, - X86VectorVTInfo _, Predicate prd> { + OpndItins itins, X86VectorVTInfo _, + Predicate prd> { let Predicates = [prd], ExeDomain = _.ExeDomain in { def rr : AVX512; + (i32 imm:$src2)))], itins.rr>, + Sched<[itins.Sched]>; def rrk : AVX512, EVEX_K; + (i32 imm:$src2))))], itins.rr>, + EVEX_K, Sched<[itins.Sched]>; def rm : AVX512; + (i32 imm:$src2)))], itins.rm>, + Sched<[itins.Sched.Folded, ReadAfterLd]>; def rmk : AVX512, EVEX_K; + (i32 imm:$src2))))], itins.rm>, + EVEX_K, Sched<[itins.Sched.Folded, ReadAfterLd]>; } } @@ -2387,34 +2453,39 @@ multiclass avx512_scalar_fpclass opc, string OpcodeStr, SDNode OpNode, // fpclass(reg_vec, mem_vec, imm) // fpclass(reg_vec, broadcast(eltVt), imm) multiclass avx512_vector_fpclass opc, string OpcodeStr, SDNode OpNode, - X86VectorVTInfo _, string mem, string broadcast>{ + OpndItins itins, X86VectorVTInfo _, + string mem, string broadcast>{ let ExeDomain = _.ExeDomain in { def rr : AVX512; + (i32 imm:$src2)))], itins.rr>, + Sched<[itins.Sched]>; def rrk : AVX512, EVEX_K; + (i32 imm:$src2))))], itins.rr>, + EVEX_K, Sched<[itins.Sched]>; def rm : AVX512; + (i32 imm:$src2)))], itins.rm>, + Sched<[itins.Sched.Folded, ReadAfterLd]>; def rmk : AVX512, EVEX_K; + (i32 imm:$src2))))], itins.rm>, + EVEX_K, Sched<[itins.Sched.Folded, ReadAfterLd]>; def rmb : AVX512 opc, string OpcodeStr, SDNode OpNode, [(set _.KRC:$dst,(OpNode (_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src1))), - (i32 imm:$src2)))], NoItinerary>,EVEX_B; + (i32 imm:$src2)))], itins.rm>, + EVEX_B, Sched<[itins.Sched.Folded, ReadAfterLd]>; def rmbk : AVX512 opc, string OpcodeStr, SDNode OpNode, [(set _.KRC:$dst,(or _.KRCWM:$mask, (OpNode (_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src1))), - (i32 imm:$src2))))], NoItinerary>, - EVEX_B, EVEX_K; + (i32 imm:$src2))))], itins.rm>, + EVEX_B, EVEX_K, Sched<[itins.Sched.Folded, ReadAfterLd]>; } } -multiclass avx512_vector_fpclass_all opc, SDNode OpNode, Predicate prd, - string broadcast>{ +multiclass avx512_vector_fpclass_all opc, SDNode OpNode, + OpndItins itins, Predicate prd, + string broadcast>{ let Predicates = [prd] in { - defm Z : avx512_vector_fpclass, EVEX_V512; + defm Z : avx512_vector_fpclass, EVEX_V512; } let Predicates = [prd, HasVLX] in { - defm Z128 : avx512_vector_fpclass, EVEX_V128; - defm Z256 : avx512_vector_fpclass, EVEX_V256; + defm Z128 : avx512_vector_fpclass, EVEX_V128; + defm Z256 : avx512_vector_fpclass, EVEX_V256; } } +// FIXME: Is there a better scheduler itinerary for VFPCLASS? multiclass avx512_fp_fpclass_all opcVec, bits<8> opcScalar, SDNode VecOpNode, SDNode ScalarOpNode, Predicate prd>{ defm PS : avx512_vector_fpclass_all, EVEX_CD8<32, CD8VF>; + VecOpNode, SSE_ALU_F32P, prd, "{l}">, + EVEX_CD8<32, CD8VF>; defm PD : avx512_vector_fpclass_all,EVEX_CD8<64, CD8VF> , VEX_W; + VecOpNode, SSE_ALU_F64P, prd, "{q}">, + EVEX_CD8<64, CD8VF> , VEX_W; defm SS : avx512_scalar_fpclass, EVEX_CD8<32, CD8VT1>; + SSE_ALU_F32S, f32x_info, prd>, + EVEX_CD8<32, CD8VT1>; defm SD : avx512_scalar_fpclass, EVEX_CD8<64, CD8VT1>, VEX_W; + SSE_ALU_F64S, f64x_info, prd>, + EVEX_CD8<64, CD8VT1>, VEX_W; } defm VFPCLASS : avx512_fp_fpclass_all<"vfpclass", 0x66, 0x67, X86Vfpclass, @@ -4107,16 +4185,16 @@ multiclass avx512_binop_rm opc, string OpcodeStr, SDNode OpNode, (ins _.RC:$src1, _.RC:$src2), OpcodeStr, "$src2, $src1", "$src1, $src2", (_.VT (OpNode _.RC:$src1, _.RC:$src2)), - itins.rr, IsCommutable>, - AVX512BIBase, EVEX_4V; + itins.rr, IsCommutable>, AVX512BIBase, EVEX_4V, + Sched<[itins.Sched]>; defm rm : AVX512_maskable, - AVX512BIBase, EVEX_4V; + itins.rm>, AVX512BIBase, EVEX_4V, + Sched<[itins.Sched.Folded, ReadAfterLd]>; } multiclass avx512_binop_rmb opc, string OpcodeStr, SDNode OpNode, @@ -4130,8 +4208,8 @@ multiclass avx512_binop_rmb opc, string OpcodeStr, SDNode OpNode, (_.VT (OpNode _.RC:$src1, (X86VBroadcast (_.ScalarLdFrag addr:$src2)))), - itins.rm>, - AVX512BIBase, EVEX_4V, EVEX_B; + itins.rm>, AVX512BIBase, EVEX_4V, EVEX_B, + Sched<[itins.Sched.Folded, ReadAfterLd]>; } multiclass avx512_binop_rm_vl opc, string OpcodeStr, SDNode OpNode, @@ -4236,14 +4314,14 @@ multiclass avx512_binop_rm2 opc, string OpcodeStr, OpndItins itins, (_Src.VT _Src.RC:$src1), (_Src.VT _Src.RC:$src2))), itins.rr, IsCommutable>, - AVX512BIBase, EVEX_4V; + AVX512BIBase, EVEX_4V, Sched<[itins.Sched]>; defm rm : AVX512_maskable, - AVX512BIBase, EVEX_4V; + itins.rm>, AVX512BIBase, EVEX_4V, + Sched<[itins.Sched.Folded, ReadAfterLd]>; defm rmb : AVX512_maskable opc, string OpcodeStr, OpndItins itins, (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1), (bitconvert (_Brdct.VT (X86VBroadcast (_Brdct.ScalarLdFrag addr:$src2)))))), - itins.rm>, - AVX512BIBase, EVEX_4V, EVEX_B; + itins.rm>, AVX512BIBase, EVEX_4V, EVEX_B, + Sched<[itins.Sched.Folded, ReadAfterLd]>; } defm VPADD : avx512_binop_rm_vl_all<0xFC, 0xFD, 0xFE, 0xD4, "vpadd", add, @@ -4450,6 +4528,46 @@ let Predicates = [HasDQI, NoVLX] in { sub_xmm)>; } +// PMULLQ: Use 512bit version to implement 128/256 bit in case NoVLX. +let Predicates = [HasDQI, NoVLX] in { + def : Pat<(v4i64 (mul (v4i64 VR256X:$src1), (v4i64 VR256X:$src2))), + (EXTRACT_SUBREG + (VPMULLQZrr + (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src1, sub_ymm), + (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src2, sub_ymm)), + sub_ymm)>; + + def : Pat<(v2i64 (mul (v2i64 VR128X:$src1), (v2i64 VR128X:$src2))), + (EXTRACT_SUBREG + (VPMULLQZrr + (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR128X:$src1, sub_xmm), + (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR128X:$src2, sub_xmm)), + sub_xmm)>; +} + +multiclass avx512_min_max_lowering { + def : Pat<(v4i64 (OpNode VR256X:$src1, VR256X:$src2)), + (EXTRACT_SUBREG + (Instr + (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src1, sub_ymm), + (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src2, sub_ymm)), + sub_ymm)>; + + def : Pat<(v2i64 (OpNode VR128X:$src1, VR128X:$src2)), + (EXTRACT_SUBREG + (Instr + (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR128X:$src1, sub_xmm), + (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR128X:$src2, sub_xmm)), + sub_xmm)>; +} + +let Predicates = [HasAVX512] in { + defm : avx512_min_max_lowering; + defm : avx512_min_max_lowering; + defm : avx512_min_max_lowering; + defm : avx512_min_max_lowering; +} + //===----------------------------------------------------------------------===// // AVX-512 Logical Instructions //===----------------------------------------------------------------------===// @@ -4549,7 +4667,7 @@ multiclass avx512_fp_scalar opc, string OpcodeStr,X86VectorVTInfo _, "$src2, $src1", "$src1, $src2", (_.VT (VecNode _.RC:$src1, _.RC:$src2, (i32 FROUND_CURRENT))), - itins.rr>; + itins.rr>, Sched<[itins.Sched]>; defm rm_Int : AVX512_maskable_scalar opc, string OpcodeStr,X86VectorVTInfo _, (_.VT (VecNode _.RC:$src1, _.ScalarIntMemCPat:$src2, (i32 FROUND_CURRENT))), - itins.rm>; + itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>; let isCodeGenOnly = 1, Predicates = [HasAVX512] in { def rr : I< opc, MRMSrcReg, (outs _.FRC:$dst), (ins _.FRC:$src1, _.FRC:$src2), OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", [(set _.FRC:$dst, (OpNode _.FRC:$src1, _.FRC:$src2))], - itins.rr> { + itins.rr>, Sched<[itins.Sched]> { let isCommutable = IsCommutable; } def rm : I< opc, MRMSrcMem, (outs _.FRC:$dst), (ins _.FRC:$src1, _.ScalarMemOp:$src2), OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", [(set _.FRC:$dst, (OpNode _.FRC:$src1, - (_.ScalarLdFrag addr:$src2)))], itins.rm>; + (_.ScalarLdFrag addr:$src2)))], itins.rm>, + Sched<[itins.Sched.Folded, ReadAfterLd]>; } } } @@ -4583,7 +4702,7 @@ multiclass avx512_fp_scalar_round opc, string OpcodeStr,X86VectorVTInfo "$rc, $src2, $src1", "$src1, $src2, $rc", (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2), (i32 imm:$rc)), itins.rr, IsCommutable>, - EVEX_B, EVEX_RC; + EVEX_B, EVEX_RC, Sched<[itins.Sched]>; } multiclass avx512_fp_scalar_sae opc, string OpcodeStr,X86VectorVTInfo _, SDNode OpNode, SDNode VecNode, SDNode SaeNode, @@ -4593,35 +4712,36 @@ multiclass avx512_fp_scalar_sae opc, string OpcodeStr,X86VectorVTInfo _, (ins _.RC:$src1, _.RC:$src2), OpcodeStr, "$src2, $src1", "$src1, $src2", (_.VT (VecNode _.RC:$src1, _.RC:$src2)), - itins.rr>; + itins.rr>, Sched<[itins.Sched]>; defm rm_Int : AVX512_maskable_scalar; + itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>; let isCodeGenOnly = 1, Predicates = [HasAVX512] in { def rr : I< opc, MRMSrcReg, (outs _.FRC:$dst), (ins _.FRC:$src1, _.FRC:$src2), OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", [(set _.FRC:$dst, (OpNode _.FRC:$src1, _.FRC:$src2))], - itins.rr> { + itins.rr>, Sched<[itins.Sched]> { let isCommutable = IsCommutable; } def rm : I< opc, MRMSrcMem, (outs _.FRC:$dst), (ins _.FRC:$src1, _.ScalarMemOp:$src2), OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", [(set _.FRC:$dst, (OpNode _.FRC:$src1, - (_.ScalarLdFrag addr:$src2)))], itins.rm>; + (_.ScalarLdFrag addr:$src2)))], itins.rm>, + Sched<[itins.Sched.Folded, ReadAfterLd]>; } defm rrb : AVX512_maskable_scalar, EVEX_B; + (i32 FROUND_NO_EXC))>, EVEX_B, Sched<[itins.Sched]>; } } @@ -4668,14 +4788,15 @@ multiclass avx512_comutable_binop_s opc, string OpcodeStr, (ins _.FRC:$src1, _.FRC:$src2), OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", [(set _.FRC:$dst, (OpNode _.FRC:$src1, _.FRC:$src2))], - itins.rr> { + itins.rr>, Sched<[itins.Sched]> { let isCommutable = 1; } def rm : I< opc, MRMSrcMem, (outs _.FRC:$dst), (ins _.FRC:$src1, _.ScalarMemOp:$src2), OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", [(set _.FRC:$dst, (OpNode _.FRC:$src1, - (_.ScalarLdFrag addr:$src2)))], itins.rm>; + (_.ScalarLdFrag addr:$src2)))], itins.rm>, + Sched<[itins.Sched.Folded, ReadAfterLd]>; } } defm VMINCSSZ : avx512_comutable_binop_s<0x5D, "vminss", f32x_info, X86fminc, @@ -4702,43 +4823,43 @@ multiclass avx512_fp_packed opc, string OpcodeStr, SDPatternOperator OpN (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix, "$src2, $src1", "$src1, $src2", (_.VT (OpNode _.RC:$src1, _.RC:$src2)), itins.rr, - IsCommutable>, EVEX_4V; + IsCommutable>, EVEX_4V, Sched<[itins.Sched]>; let mayLoad = 1 in { defm rm: AVX512_maskable, - EVEX_4V; + EVEX_4V, Sched<[itins.Sched.Folded, ReadAfterLd]>; defm rmb: AVX512_maskable, EVEX_4V, EVEX_B; + itins.rm>, EVEX_4V, EVEX_B, + Sched<[itins.Sched.Folded, ReadAfterLd]>; } } } multiclass avx512_fp_round_packed opc, string OpcodeStr, SDPatternOperator OpNodeRnd, - X86VectorVTInfo _> { + OpndItins itins, X86VectorVTInfo _> { let ExeDomain = _.ExeDomain in defm rb: AVX512_maskable, - EVEX_4V, EVEX_B, EVEX_RC; + (_.VT (OpNodeRnd _.RC:$src1, _.RC:$src2, (i32 imm:$rc))), itins.rr>, + EVEX_4V, EVEX_B, EVEX_RC, Sched<[itins.Sched]>; } - multiclass avx512_fp_sae_packed opc, string OpcodeStr, SDPatternOperator OpNodeRnd, - X86VectorVTInfo _> { + OpndItins itins, X86VectorVTInfo _> { let ExeDomain = _.ExeDomain in defm rb: AVX512_maskable, - EVEX_4V, EVEX_B; + (_.VT (OpNodeRnd _.RC:$src1, _.RC:$src2, (i32 FROUND_NO_EXC))), itins.rr>, + EVEX_4V, EVEX_B, Sched<[itins.Sched]>; } multiclass avx512_fp_binop_p opc, string OpcodeStr, SDPatternOperator OpNode, @@ -4770,36 +4891,38 @@ multiclass avx512_fp_binop_p opc, string OpcodeStr, SDPatternOperator Op } } -multiclass avx512_fp_binop_p_round opc, string OpcodeStr, SDNode OpNodeRnd> { - defm PSZ : avx512_fp_round_packed, +multiclass avx512_fp_binop_p_round opc, string OpcodeStr, SDNode OpNodeRnd, + SizeItins itins> { + defm PSZ : avx512_fp_round_packed, EVEX_V512, PS, EVEX_CD8<32, CD8VF>; - defm PDZ : avx512_fp_round_packed, + defm PDZ : avx512_fp_round_packed, EVEX_V512, PD, VEX_W,EVEX_CD8<64, CD8VF>; } -multiclass avx512_fp_binop_p_sae opc, string OpcodeStr, SDNode OpNodeRnd> { - defm PSZ : avx512_fp_sae_packed, +multiclass avx512_fp_binop_p_sae opc, string OpcodeStr, SDNode OpNodeRnd, + SizeItins itins> { + defm PSZ : avx512_fp_sae_packed, EVEX_V512, PS, EVEX_CD8<32, CD8VF>; - defm PDZ : avx512_fp_sae_packed, + defm PDZ : avx512_fp_sae_packed, EVEX_V512, PD, VEX_W,EVEX_CD8<64, CD8VF>; } defm VADD : avx512_fp_binop_p<0x58, "vadd", fadd, HasAVX512, SSE_ALU_ITINS_P, 1>, - avx512_fp_binop_p_round<0x58, "vadd", X86faddRnd>; + avx512_fp_binop_p_round<0x58, "vadd", X86faddRnd, SSE_ALU_ITINS_P>; defm VMUL : avx512_fp_binop_p<0x59, "vmul", fmul, HasAVX512, SSE_MUL_ITINS_P, 1>, - avx512_fp_binop_p_round<0x59, "vmul", X86fmulRnd>; + avx512_fp_binop_p_round<0x59, "vmul", X86fmulRnd, SSE_MUL_ITINS_P>; defm VSUB : avx512_fp_binop_p<0x5C, "vsub", fsub, HasAVX512, SSE_ALU_ITINS_P>, - avx512_fp_binop_p_round<0x5C, "vsub", X86fsubRnd>; + avx512_fp_binop_p_round<0x5C, "vsub", X86fsubRnd, SSE_ALU_ITINS_P>; defm VDIV : avx512_fp_binop_p<0x5E, "vdiv", fdiv, HasAVX512, SSE_DIV_ITINS_P>, - avx512_fp_binop_p_round<0x5E, "vdiv", X86fdivRnd>; + avx512_fp_binop_p_round<0x5E, "vdiv", X86fdivRnd, SSE_DIV_ITINS_P>; defm VMIN : avx512_fp_binop_p<0x5D, "vmin", X86fmin, HasAVX512, SSE_ALU_ITINS_P, 0>, - avx512_fp_binop_p_sae<0x5D, "vmin", X86fminRnd>; + avx512_fp_binop_p_sae<0x5D, "vmin", X86fminRnd, SSE_ALU_ITINS_P>; defm VMAX : avx512_fp_binop_p<0x5F, "vmax", X86fmax, HasAVX512, SSE_ALU_ITINS_P, 0>, - avx512_fp_binop_p_sae<0x5F, "vmax", X86fmaxRnd>; + avx512_fp_binop_p_sae<0x5F, "vmax", X86fmaxRnd, SSE_ALU_ITINS_P>; let isCodeGenOnly = 1 in { defm VMINC : avx512_fp_binop_p<0x5D, "vmin", X86fminc, HasAVX512, SSE_ALU_ITINS_P, 1>; @@ -4920,64 +5043,69 @@ let Predicates = [HasVLX,HasDQI] in { } multiclass avx512_fp_scalef_p opc, string OpcodeStr, SDNode OpNode, - X86VectorVTInfo _> { + OpndItins itins, X86VectorVTInfo _> { let ExeDomain = _.ExeDomain in { defm rr: AVX512_maskable, EVEX_4V; + (_.VT (OpNode _.RC:$src1, _.RC:$src2, (i32 FROUND_CURRENT))), + itins.rr>, EVEX_4V, Sched<[itins.Sched]>; defm rm: AVX512_maskable, EVEX_4V; + (OpNode _.RC:$src1, (_.LdFrag addr:$src2), (i32 FROUND_CURRENT)), + itins.rm>, EVEX_4V, Sched<[itins.Sched.Folded, ReadAfterLd]>; defm rmb: AVX512_maskable, - EVEX_4V, EVEX_B; + (_.ScalarLdFrag addr:$src2))), + (i32 FROUND_CURRENT)), itins.rm>, + EVEX_4V, EVEX_B, Sched<[itins.Sched.Folded, ReadAfterLd]>; } } multiclass avx512_fp_scalef_scalar opc, string OpcodeStr, SDNode OpNode, - X86VectorVTInfo _> { + OpndItins itins, X86VectorVTInfo _> { let ExeDomain = _.ExeDomain in { defm rr: AVX512_maskable_scalar; + (_.VT (OpNode _.RC:$src1, _.RC:$src2, (i32 FROUND_CURRENT))), itins.rr>, + Sched<[itins.Sched]>; defm rm: AVX512_maskable_scalar; + (i32 FROUND_CURRENT)), itins.rm>, + Sched<[itins.Sched.Folded, ReadAfterLd]>; } } multiclass avx512_fp_scalef_all opc, bits<8> opcScaler, string OpcodeStr, SDNode OpNode, SDNode OpNodeScal> { - defm PSZ : avx512_fp_scalef_p, - avx512_fp_round_packed, + defm PSZ : avx512_fp_scalef_p, + avx512_fp_round_packed, EVEX_V512, EVEX_CD8<32, CD8VF>; - defm PDZ : avx512_fp_scalef_p, - avx512_fp_round_packed, + defm PDZ : avx512_fp_scalef_p, + avx512_fp_round_packed, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>; - defm SSZ128 : avx512_fp_scalef_scalar, + defm SSZ128 : avx512_fp_scalef_scalar, avx512_fp_scalar_round, EVEX_4V,EVEX_CD8<32, CD8VT1>; - defm SDZ128 : avx512_fp_scalef_scalar, + defm SDZ128 : avx512_fp_scalef_scalar, avx512_fp_scalar_round, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W; // Define only if AVX512VL feature is present. let Predicates = [HasVLX] in { - defm PSZ128 : avx512_fp_scalef_p, + defm PSZ128 : avx512_fp_scalef_p, EVEX_V128, EVEX_CD8<32, CD8VF>; - defm PSZ256 : avx512_fp_scalef_p, + defm PSZ256 : avx512_fp_scalef_p, EVEX_V256, EVEX_CD8<32, CD8VF>; - defm PDZ128 : avx512_fp_scalef_p, + defm PDZ128 : avx512_fp_scalef_p, EVEX_V128, VEX_W, EVEX_CD8<64, CD8VF>; - defm PDZ256 : avx512_fp_scalef_p, + defm PDZ256 : avx512_fp_scalef_p, EVEX_V256, VEX_W, EVEX_CD8<64, CD8VF>; } } @@ -4988,34 +5116,35 @@ defm VSCALEF : avx512_fp_scalef_all<0x2C, 0x2D, "vscalef", X86scalef, X86scalefs //===----------------------------------------------------------------------===// multiclass avx512_vptest opc, string OpcodeStr, SDNode OpNode, - X86VectorVTInfo _> { + OpndItins itins, X86VectorVTInfo _> { let ExeDomain = _.ExeDomain in { let isCommutable = 1 in defm rr : AVX512_maskable_cmp, - EVEX_4V; + (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2)), itins.rr>, + EVEX_4V, Sched<[itins.Sched]>; defm rm : AVX512_maskable_cmp, - EVEX_4V, - EVEX_CD8<_.EltSize, CD8VF>; + (_.VT (bitconvert (_.LdFrag addr:$src2)))), itins.rm>, + EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>, + Sched<[itins.Sched.Folded, ReadAfterLd]>; } } multiclass avx512_vptest_mb opc, string OpcodeStr, SDNode OpNode, - X86VectorVTInfo _> { + OpndItins itins, X86VectorVTInfo _> { let ExeDomain = _.ExeDomain in defm rmb : AVX512_maskable_cmp, - EVEX_B, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>; + (_.ScalarLdFrag addr:$src2)))), + itins.rm>, EVEX_B, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>, + Sched<[itins.Sched.Folded, ReadAfterLd]>; } // Use 512bit version to implement 128/256 bit in case NoVLX. @@ -5032,16 +5161,17 @@ multiclass avx512_vptest_lowering opc, string OpcodeStr, SDNode OpNode, - AVX512VLVectorVTInfo _, string Suffix> { + OpndItins itins, AVX512VLVectorVTInfo _, + string Suffix> { let Predicates = [HasAVX512] in - defm Z : avx512_vptest, - avx512_vptest_mb, EVEX_V512; + defm Z : avx512_vptest, + avx512_vptest_mb, EVEX_V512; let Predicates = [HasAVX512, HasVLX] in { - defm Z256 : avx512_vptest, - avx512_vptest_mb, EVEX_V256; - defm Z128 : avx512_vptest, - avx512_vptest_mb, EVEX_V128; + defm Z256 : avx512_vptest, + avx512_vptest_mb, EVEX_V256; + defm Z128 : avx512_vptest, + avx512_vptest_mb, EVEX_V128; } let Predicates = [HasAVX512, NoVLX] in { defm Z256_Alt : avx512_vptest_lowering< OpNode, _.info512, _.info256, Suffix>; @@ -5049,30 +5179,31 @@ multiclass avx512_vptest_dq_sizes opc, string OpcodeStr, SDNode OpNode, } } -multiclass avx512_vptest_dq opc, string OpcodeStr, SDNode OpNode> { - defm D : avx512_vptest_dq_sizes opc, string OpcodeStr, SDNode OpNode, + OpndItins itins> { + defm D : avx512_vptest_dq_sizes; - defm Q : avx512_vptest_dq_sizes, VEX_W; } multiclass avx512_vptest_wb opc, string OpcodeStr, - SDNode OpNode> { + SDNode OpNode, OpndItins itins> { let Predicates = [HasBWI] in { - defm WZ: avx512_vptest, + defm WZ: avx512_vptest, EVEX_V512, VEX_W; - defm BZ: avx512_vptest, + defm BZ: avx512_vptest, EVEX_V512; } let Predicates = [HasVLX, HasBWI] in { - defm WZ256: avx512_vptest, + defm WZ256: avx512_vptest, EVEX_V256, VEX_W; - defm WZ128: avx512_vptest, + defm WZ128: avx512_vptest, EVEX_V128, VEX_W; - defm BZ256: avx512_vptest, + defm BZ256: avx512_vptest, EVEX_V256; - defm BZ128: avx512_vptest, + defm BZ128: avx512_vptest, EVEX_V128; } @@ -5082,151 +5213,165 @@ multiclass avx512_vptest_wb opc, string OpcodeStr, defm WZ256_Alt : avx512_vptest_lowering< OpNode, v32i16_info, v16i16x_info, "W">; defm WZ128_Alt : avx512_vptest_lowering< OpNode, v32i16_info, v8i16x_info, "W">; } - } multiclass avx512_vptest_all_forms opc_wb, bits<8> opc_dq, string OpcodeStr, - SDNode OpNode> : - avx512_vptest_wb , - avx512_vptest_dq; + SDNode OpNode, OpndItins itins> : + avx512_vptest_wb , + avx512_vptest_dq; -defm VPTESTM : avx512_vptest_all_forms<0x26, 0x27, "vptestm", X86testm>, T8PD; -defm VPTESTNM : avx512_vptest_all_forms<0x26, 0x27, "vptestnm", X86testnm>, T8XS; +defm VPTESTM : avx512_vptest_all_forms<0x26, 0x27, "vptestm", X86testm, + SSE_BIT_ITINS_P>, T8PD; +defm VPTESTNM : avx512_vptest_all_forms<0x26, 0x27, "vptestnm", X86testnm, + SSE_BIT_ITINS_P>, T8XS; //===----------------------------------------------------------------------===// // AVX-512 Shift instructions //===----------------------------------------------------------------------===// multiclass avx512_shift_rmi opc, Format ImmFormR, Format ImmFormM, - string OpcodeStr, SDNode OpNode, X86VectorVTInfo _> { + string OpcodeStr, SDNode OpNode, OpndItins itins, + X86VectorVTInfo _> { let ExeDomain = _.ExeDomain in { defm ri : AVX512_maskable; + itins.rr>, Sched<[itins.Sched]>; defm mi : AVX512_maskable; + itins.rm>, Sched<[itins.Sched.Folded]>; } } multiclass avx512_shift_rmbi opc, Format ImmFormM, - string OpcodeStr, SDNode OpNode, X86VectorVTInfo _> { + string OpcodeStr, SDNode OpNode, OpndItins itins, + X86VectorVTInfo _> { let ExeDomain = _.ExeDomain in defm mbi : AVX512_maskable, EVEX_B; + itins.rm>, EVEX_B, Sched<[itins.Sched.Folded, ReadAfterLd]>; } multiclass avx512_shift_rrm opc, string OpcodeStr, SDNode OpNode, - ValueType SrcVT, PatFrag bc_frag, X86VectorVTInfo _> { + OpndItins itins, ValueType SrcVT, PatFrag bc_frag, + X86VectorVTInfo _> { // src2 is always 128-bit let ExeDomain = _.ExeDomain in { defm rr : AVX512_maskable, AVX512BIBase, EVEX_4V; + itins.rr>, AVX512BIBase, EVEX_4V, Sched<[itins.Sched]>; defm rm : AVX512_maskable, AVX512BIBase, - EVEX_4V; + itins.rm>, AVX512BIBase, + EVEX_4V, Sched<[itins.Sched.Folded, ReadAfterLd]>; } } multiclass avx512_shift_sizes opc, string OpcodeStr, SDNode OpNode, - ValueType SrcVT, PatFrag bc_frag, - AVX512VLVectorVTInfo VTInfo, Predicate prd> { + OpndItins itins, ValueType SrcVT, PatFrag bc_frag, + AVX512VLVectorVTInfo VTInfo, Predicate prd> { let Predicates = [prd] in - defm Z : avx512_shift_rrm, EVEX_V512, EVEX_CD8 ; let Predicates = [prd, HasVLX] in { - defm Z256 : avx512_shift_rrm, EVEX_V256, EVEX_CD8; - defm Z128 : avx512_shift_rrm, EVEX_V128, EVEX_CD8; } } multiclass avx512_shift_types opcd, bits<8> opcq, bits<8> opcw, - string OpcodeStr, SDNode OpNode> { - defm D : avx512_shift_sizes; - defm Q : avx512_shift_sizes, VEX_W; - defm W : avx512_shift_sizes; + string OpcodeStr, SDNode OpNode, + OpndItins itins> { + defm D : avx512_shift_sizes; + defm Q : avx512_shift_sizes, VEX_W; + defm W : avx512_shift_sizes; } multiclass avx512_shift_rmi_sizes opc, Format ImmFormR, Format ImmFormM, - string OpcodeStr, SDNode OpNode, - AVX512VLVectorVTInfo VTInfo> { + string OpcodeStr, SDNode OpNode, + OpndItins itins, AVX512VLVectorVTInfo VTInfo> { let Predicates = [HasAVX512] in - defm Z: avx512_shift_rmi, - avx512_shift_rmbi, EVEX_V512; let Predicates = [HasAVX512, HasVLX] in { - defm Z256: avx512_shift_rmi, - avx512_shift_rmbi, EVEX_V256; defm Z128: avx512_shift_rmi, - avx512_shift_rmbi, + avx512_shift_rmbi, EVEX_V128; } } multiclass avx512_shift_rmi_w opcw, Format ImmFormR, Format ImmFormM, - string OpcodeStr, SDNode OpNode> { + string OpcodeStr, SDNode OpNode, + OpndItins itins> { let Predicates = [HasBWI] in defm WZ: avx512_shift_rmi, EVEX_V512, VEX_WIG; + itins, v32i16_info>, EVEX_V512, VEX_WIG; let Predicates = [HasVLX, HasBWI] in { defm WZ256: avx512_shift_rmi, EVEX_V256, VEX_WIG; + itins, v16i16x_info>, EVEX_V256, VEX_WIG; defm WZ128: avx512_shift_rmi, EVEX_V128, VEX_WIG; + itins, v8i16x_info>, EVEX_V128, VEX_WIG; } } multiclass avx512_shift_rmi_dq opcd, bits<8> opcq, Format ImmFormR, Format ImmFormM, - string OpcodeStr, SDNode OpNode> { + string OpcodeStr, SDNode OpNode, OpndItins itins> { defm D: avx512_shift_rmi_sizes, EVEX_CD8<32, CD8VF>; + itins, avx512vl_i32_info>, EVEX_CD8<32, CD8VF>; defm Q: avx512_shift_rmi_sizes, EVEX_CD8<64, CD8VF>, VEX_W; + itins, avx512vl_i64_info>, EVEX_CD8<64, CD8VF>, VEX_W; } -defm VPSRL : avx512_shift_rmi_dq<0x72, 0x73, MRM2r, MRM2m, "vpsrl", X86vsrli>, - avx512_shift_rmi_w<0x71, MRM2r, MRM2m, "vpsrlw", X86vsrli>, AVX512BIi8Base, EVEX_4V; +defm VPSRL : avx512_shift_rmi_dq<0x72, 0x73, MRM2r, MRM2m, "vpsrl", X86vsrli, + SSE_INTSHIFT_P>, + avx512_shift_rmi_w<0x71, MRM2r, MRM2m, "vpsrlw", X86vsrli, + SSE_INTSHIFT_P>, AVX512BIi8Base, EVEX_4V; -defm VPSLL : avx512_shift_rmi_dq<0x72, 0x73, MRM6r, MRM6m, "vpsll", X86vshli>, - avx512_shift_rmi_w<0x71, MRM6r, MRM6m, "vpsllw", X86vshli>, AVX512BIi8Base, EVEX_4V; +defm VPSLL : avx512_shift_rmi_dq<0x72, 0x73, MRM6r, MRM6m, "vpsll", X86vshli, + SSE_INTSHIFT_P>, + avx512_shift_rmi_w<0x71, MRM6r, MRM6m, "vpsllw", X86vshli, + SSE_INTSHIFT_P>, AVX512BIi8Base, EVEX_4V; -defm VPSRA : avx512_shift_rmi_dq<0x72, 0x72, MRM4r, MRM4m, "vpsra", X86vsrai>, - avx512_shift_rmi_w<0x71, MRM4r, MRM4m, "vpsraw", X86vsrai>, AVX512BIi8Base, EVEX_4V; +defm VPSRA : avx512_shift_rmi_dq<0x72, 0x72, MRM4r, MRM4m, "vpsra", X86vsrai, + SSE_INTSHIFT_P>, + avx512_shift_rmi_w<0x71, MRM4r, MRM4m, "vpsraw", X86vsrai, + SSE_INTSHIFT_P>, AVX512BIi8Base, EVEX_4V; -defm VPROR : avx512_shift_rmi_dq<0x72, 0x72, MRM0r, MRM0m, "vpror", X86vrotri>, AVX512BIi8Base, EVEX_4V; -defm VPROL : avx512_shift_rmi_dq<0x72, 0x72, MRM1r, MRM1m, "vprol", X86vrotli>, AVX512BIi8Base, EVEX_4V; +defm VPROR : avx512_shift_rmi_dq<0x72, 0x72, MRM0r, MRM0m, "vpror", X86vrotri, + SSE_INTSHIFT_P>, AVX512BIi8Base, EVEX_4V; +defm VPROL : avx512_shift_rmi_dq<0x72, 0x72, MRM1r, MRM1m, "vprol", X86vrotli, + SSE_INTSHIFT_P>, AVX512BIi8Base, EVEX_4V; -defm VPSLL : avx512_shift_types<0xF2, 0xF3, 0xF1, "vpsll", X86vshl>; -defm VPSRA : avx512_shift_types<0xE2, 0xE2, 0xE1, "vpsra", X86vsra>; -defm VPSRL : avx512_shift_types<0xD2, 0xD3, 0xD1, "vpsrl", X86vsrl>; +defm VPSLL : avx512_shift_types<0xF2, 0xF3, 0xF1, "vpsll", X86vshl, SSE_INTSHIFT_P>; +defm VPSRA : avx512_shift_types<0xE2, 0xE2, 0xE1, "vpsra", X86vsra, SSE_INTSHIFT_P>; +defm VPSRL : avx512_shift_types<0xD2, 0xD3, 0xD1, "vpsrl", X86vsrl, SSE_INTSHIFT_P>; // Use 512bit VPSRA/VPSRAI version to implement v2i64/v4i64 in case NoVLX. let Predicates = [HasAVX512, NoVLX] in { @@ -5259,25 +5404,27 @@ let Predicates = [HasAVX512, NoVLX] in { // Variable Bit Shifts //===-------------------------------------------------------------------===// multiclass avx512_var_shift opc, string OpcodeStr, SDNode OpNode, - X86VectorVTInfo _> { + OpndItins itins, X86VectorVTInfo _> { let ExeDomain = _.ExeDomain in { defm rr : AVX512_maskable, AVX5128IBase, EVEX_4V; + itins.rr>, AVX5128IBase, EVEX_4V, + Sched<[itins.Sched]>; defm rm : AVX512_maskable, AVX5128IBase, EVEX_4V, - EVEX_CD8<_.EltSize, CD8VF>; + itins.rm>, AVX5128IBase, EVEX_4V, + EVEX_CD8<_.EltSize, CD8VF>, + Sched<[itins.Sched.Folded, ReadAfterLd]>; } } multiclass avx512_var_shift_mb opc, string OpcodeStr, SDNode OpNode, - X86VectorVTInfo _> { + OpndItins itins, X86VectorVTInfo _> { let ExeDomain = _.ExeDomain in defm rmb : AVX512_maskable opc, string OpcodeStr, SDNode OpNode, "$src1, ${src2}"##_.BroadcastStr, (_.VT (OpNode _.RC:$src1, (_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src2))))), - SSE_INTSHIFT_ITINS_P.rm>, AVX5128IBase, EVEX_B, - EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>; + itins.rm>, AVX5128IBase, EVEX_B, + EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>, + Sched<[itins.Sched.Folded, ReadAfterLd]>; } multiclass avx512_var_shift_sizes opc, string OpcodeStr, SDNode OpNode, - AVX512VLVectorVTInfo _> { + OpndItins itins, AVX512VLVectorVTInfo _> { let Predicates = [HasAVX512] in - defm Z : avx512_var_shift, - avx512_var_shift_mb, EVEX_V512; + defm Z : avx512_var_shift, + avx512_var_shift_mb, EVEX_V512; let Predicates = [HasAVX512, HasVLX] in { - defm Z256 : avx512_var_shift, - avx512_var_shift_mb, EVEX_V256; - defm Z128 : avx512_var_shift, - avx512_var_shift_mb, EVEX_V128; + defm Z256 : avx512_var_shift, + avx512_var_shift_mb, EVEX_V256; + defm Z128 : avx512_var_shift, + avx512_var_shift_mb, EVEX_V128; } } multiclass avx512_var_shift_types opc, string OpcodeStr, - SDNode OpNode> { - defm D : avx512_var_shift_sizes { + defm D : avx512_var_shift_sizes; - defm Q : avx512_var_shift_sizes, VEX_W; } @@ -5333,30 +5481,30 @@ multiclass avx512_var_shift_lowering opc, string OpcodeStr, - SDNode OpNode> { + SDNode OpNode, OpndItins itins> { let Predicates = [HasBWI] in - defm WZ: avx512_var_shift, + defm WZ: avx512_var_shift, EVEX_V512, VEX_W; let Predicates = [HasVLX, HasBWI] in { - defm WZ256: avx512_var_shift, + defm WZ256: avx512_var_shift, EVEX_V256, VEX_W; - defm WZ128: avx512_var_shift, + defm WZ128: avx512_var_shift, EVEX_V128, VEX_W; } } -defm VPSLLV : avx512_var_shift_types<0x47, "vpsllv", shl>, - avx512_var_shift_w<0x12, "vpsllvw", shl>; +defm VPSLLV : avx512_var_shift_types<0x47, "vpsllv", shl, SSE_INTSHIFT_P>, + avx512_var_shift_w<0x12, "vpsllvw", shl, SSE_INTSHIFT_P>; -defm VPSRAV : avx512_var_shift_types<0x46, "vpsrav", sra>, - avx512_var_shift_w<0x11, "vpsravw", sra>; +defm VPSRAV : avx512_var_shift_types<0x46, "vpsrav", sra, SSE_INTSHIFT_P>, + avx512_var_shift_w<0x11, "vpsravw", sra, SSE_INTSHIFT_P>; -defm VPSRLV : avx512_var_shift_types<0x45, "vpsrlv", srl>, - avx512_var_shift_w<0x10, "vpsrlvw", srl>; +defm VPSRLV : avx512_var_shift_types<0x45, "vpsrlv", srl, SSE_INTSHIFT_P>, + avx512_var_shift_w<0x10, "vpsrlvw", srl, SSE_INTSHIFT_P>; -defm VPRORV : avx512_var_shift_types<0x14, "vprorv", rotr>; -defm VPROLV : avx512_var_shift_types<0x15, "vprolv", rotl>; +defm VPRORV : avx512_var_shift_types<0x14, "vprorv", rotr, SSE_INTSHIFT_P>; +defm VPROLV : avx512_var_shift_types<0x15, "vprolv", rotl, SSE_INTSHIFT_P>; defm : avx512_var_shift_lowering; defm : avx512_var_shift_lowering; @@ -5534,64 +5682,64 @@ let Predicates = [HasAVX512, NoVLX] in { // 1-src variable permutation VPERMW/D/Q //===-------------------------------------------------------------------===// multiclass avx512_vperm_dq_sizes opc, string OpcodeStr, SDNode OpNode, - AVX512VLVectorVTInfo _> { + OpndItins itins, AVX512VLVectorVTInfo _> { let Predicates = [HasAVX512] in - defm Z : avx512_var_shift, - avx512_var_shift_mb, EVEX_V512; + defm Z : avx512_var_shift, + avx512_var_shift_mb, EVEX_V512; let Predicates = [HasAVX512, HasVLX] in - defm Z256 : avx512_var_shift, - avx512_var_shift_mb, EVEX_V256; + defm Z256 : avx512_var_shift, + avx512_var_shift_mb, EVEX_V256; } multiclass avx512_vpermi_dq_sizes opc, Format ImmFormR, Format ImmFormM, string OpcodeStr, SDNode OpNode, - AVX512VLVectorVTInfo VTInfo> { + OpndItins itins, AVX512VLVectorVTInfo VTInfo> { let Predicates = [HasAVX512] in defm Z: avx512_shift_rmi, + itins, VTInfo.info512>, avx512_shift_rmbi, EVEX_V512; + itins, VTInfo.info512>, EVEX_V512; let Predicates = [HasAVX512, HasVLX] in defm Z256: avx512_shift_rmi, + itins, VTInfo.info256>, avx512_shift_rmbi, EVEX_V256; + itins, VTInfo.info256>, EVEX_V256; } multiclass avx512_vperm_bw opc, string OpcodeStr, Predicate prd, SDNode OpNode, - AVX512VLVectorVTInfo _> { + OpndItins itins, AVX512VLVectorVTInfo _> { let Predicates = [prd] in - defm Z: avx512_var_shift, + defm Z: avx512_var_shift, EVEX_V512 ; let Predicates = [HasVLX, prd] in { - defm Z256: avx512_var_shift, + defm Z256: avx512_var_shift, EVEX_V256 ; - defm Z128: avx512_var_shift, + defm Z128: avx512_var_shift, EVEX_V128 ; } } defm VPERMW : avx512_vperm_bw<0x8D, "vpermw", HasBWI, X86VPermv, - avx512vl_i16_info>, VEX_W; + AVX2_PERMV_I, avx512vl_i16_info>, VEX_W; defm VPERMB : avx512_vperm_bw<0x8D, "vpermb", HasVBMI, X86VPermv, - avx512vl_i8_info>; + AVX2_PERMV_I, avx512vl_i8_info>; defm VPERMD : avx512_vperm_dq_sizes<0x36, "vpermd", X86VPermv, - avx512vl_i32_info>; + AVX2_PERMV_I, avx512vl_i32_info>; defm VPERMQ : avx512_vperm_dq_sizes<0x36, "vpermq", X86VPermv, - avx512vl_i64_info>, VEX_W; + AVX2_PERMV_I, avx512vl_i64_info>, VEX_W; defm VPERMPS : avx512_vperm_dq_sizes<0x16, "vpermps", X86VPermv, - avx512vl_f32_info>; + AVX2_PERMV_F, avx512vl_f32_info>; defm VPERMPD : avx512_vperm_dq_sizes<0x16, "vpermpd", X86VPermv, - avx512vl_f64_info>, VEX_W; + AVX2_PERMV_F, avx512vl_f64_info>, VEX_W; defm VPERMQ : avx512_vpermi_dq_sizes<0x00, MRMSrcReg, MRMSrcMem, "vpermq", - X86VPermi, avx512vl_i64_info>, + X86VPermi, AVX2_PERMV_I, avx512vl_i64_info>, EVEX, AVX512AIi8Base, EVEX_CD8<64, CD8VF>, VEX_W; defm VPERMPD : avx512_vpermi_dq_sizes<0x01, MRMSrcReg, MRMSrcMem, "vpermpd", - X86VPermi, avx512vl_f64_info>, + X86VPermi, AVX2_PERMV_F, avx512vl_f64_info>, EVEX, AVX512AIi8Base, EVEX_CD8<64, CD8VF>, VEX_W; //===----------------------------------------------------------------------===// // AVX-512 - VPERMIL @@ -5645,7 +5793,7 @@ multiclass avx512_permil OpcImm, bits<8> OpcVar, AVX512VLVectorVTInfo _, AVX512VLVectorVTInfo Ctrl>{ defm NAME: avx512_permil_vec_common; defm NAME: avx512_shift_rmi_sizes, + X86VPermilpi, AVX_VPERMILV, _>, EVEX, AVX512AIi8Base, EVEX_CD8<_.info128.EltSize, CD8VF>; } @@ -5661,24 +5809,25 @@ defm VPERMILPD : avx512_permil<"vpermilpd", 0x05, 0x0D, avx512vl_f64_info, //===----------------------------------------------------------------------===// defm VPSHUFD : avx512_shift_rmi_sizes<0x70, MRMSrcReg, MRMSrcMem, "vpshufd", - X86PShufd, avx512vl_i32_info>, + X86PShufd, SSE_PSHUF, avx512vl_i32_info>, EVEX, AVX512BIi8Base, EVEX_CD8<32, CD8VF>; defm VPSHUFH : avx512_shift_rmi_w<0x70, MRMSrcReg, MRMSrcMem, "vpshufhw", - X86PShufhw>, EVEX, AVX512XSIi8Base; + X86PShufhw, SSE_PSHUF>, EVEX, AVX512XSIi8Base; defm VPSHUFL : avx512_shift_rmi_w<0x70, MRMSrcReg, MRMSrcMem, "vpshuflw", - X86PShuflw>, EVEX, AVX512XDIi8Base; + X86PShuflw, SSE_PSHUF>, EVEX, AVX512XDIi8Base; -multiclass avx512_pshufb_sizes opc, string OpcodeStr, SDNode OpNode> { +multiclass avx512_pshufb_sizes opc, string OpcodeStr, SDNode OpNode, + OpndItins itins> { let Predicates = [HasBWI] in - defm Z: avx512_var_shift, EVEX_V512; + defm Z: avx512_var_shift, EVEX_V512; let Predicates = [HasVLX, HasBWI] in { - defm Z256: avx512_var_shift, EVEX_V256; - defm Z128: avx512_var_shift, EVEX_V128; + defm Z256: avx512_var_shift, EVEX_V256; + defm Z128: avx512_var_shift, EVEX_V128; } } -defm VPSHUFB: avx512_pshufb_sizes<0x00, "vpshufb", X86pshufb>, VEX_WIG; +defm VPSHUFB: avx512_pshufb_sizes<0x00, "vpshufb", X86pshufb, SSE_PSHUFB>, VEX_WIG; //===----------------------------------------------------------------------===// // Move Low to High and High to Low packed FP Instructions @@ -6615,74 +6764,81 @@ def : Pat<(v2f64 (X86Movsd //===----------------------------------------------------------------------===// multiclass avx512_vcvt_fp opc, string OpcodeStr, X86VectorVTInfo _, - X86VectorVTInfo _Src, SDNode OpNode, + X86VectorVTInfo _Src, SDNode OpNode, OpndItins itins, string Broadcast = _.BroadcastStr, string Alias = "", X86MemOperand MemOp = _Src.MemOp> { defm rr : AVX512_maskable, EVEX; + (_.VT (OpNode (_Src.VT _Src.RC:$src))), itins.rr>, + EVEX, Sched<[itins.Sched]>; defm rm : AVX512_maskable, EVEX; + (bitconvert (_Src.LdFrag addr:$src))))), itins.rm>, + EVEX, Sched<[itins.Sched.Folded]>; defm rmb : AVX512_maskable, EVEX, EVEX_B; + )), itins.rm>, EVEX, EVEX_B, + Sched<[itins.Sched.Folded]>; } // Coversion with SAE - suppress all exceptions multiclass avx512_vcvt_fp_sae opc, string OpcodeStr, X86VectorVTInfo _, - X86VectorVTInfo _Src, SDNode OpNodeRnd> { + X86VectorVTInfo _Src, SDNode OpNodeRnd, + OpndItins itins> { defm rrb : AVX512_maskable, - EVEX, EVEX_B; + (i32 FROUND_NO_EXC))), itins.rr>, + EVEX, EVEX_B, Sched<[itins.Sched]>; } // Conversion with rounding control (RC) multiclass avx512_vcvt_fp_rc opc, string OpcodeStr, X86VectorVTInfo _, - X86VectorVTInfo _Src, SDNode OpNodeRnd> { + X86VectorVTInfo _Src, SDNode OpNodeRnd, + OpndItins itins> { defm rrb : AVX512_maskable, - EVEX, EVEX_B, EVEX_RC; + (_.VT (OpNodeRnd (_Src.VT _Src.RC:$src), (i32 imm:$rc))), + itins.rr>, EVEX, EVEX_B, EVEX_RC, Sched<[itins.Sched]>; } // Extend Float to Double -multiclass avx512_cvtps2pd opc, string OpcodeStr> { +multiclass avx512_cvtps2pd opc, string OpcodeStr, + OpndItins itins> { let Predicates = [HasAVX512] in { - defm Z : avx512_vcvt_fp, + defm Z : avx512_vcvt_fp, avx512_vcvt_fp_sae, EVEX_V512; + X86vfpextRnd, itins>, EVEX_V512; } let Predicates = [HasVLX] in { defm Z128 : avx512_vcvt_fp, EVEX_V128; - defm Z256 : avx512_vcvt_fp, - EVEX_V256; + X86vfpext, itins, "{1to2}", "", f64mem>, EVEX_V128; + defm Z256 : avx512_vcvt_fp, EVEX_V256; } } // Truncate Double to Float -multiclass avx512_cvtpd2ps opc, string OpcodeStr> { +multiclass avx512_cvtpd2ps opc, string OpcodeStr, OpndItins itins> { let Predicates = [HasAVX512] in { - defm Z : avx512_vcvt_fp, + defm Z : avx512_vcvt_fp, avx512_vcvt_fp_rc, EVEX_V512; + X86vfproundRnd, itins>, EVEX_V512; } let Predicates = [HasVLX] in { defm Z128 : avx512_vcvt_fp, EVEX_V128; + X86vfpround, itins, "{1to2}", "{x}">, EVEX_V128; defm Z256 : avx512_vcvt_fp, EVEX_V256; + itins, "{1to4}", "{y}">, EVEX_V256; def : InstAlias(NAME # "Z128rr") VR128X:$dst, VR128X:$src), 0>; @@ -6695,9 +6851,9 @@ multiclass avx512_cvtpd2ps opc, string OpcodeStr> { } } -defm VCVTPD2PS : avx512_cvtpd2ps<0x5A, "vcvtpd2ps">, +defm VCVTPD2PS : avx512_cvtpd2ps<0x5A, "vcvtpd2ps", SSE_CVT_PD2PS>, VEX_W, PD, EVEX_CD8<64, CD8VF>; -defm VCVTPS2PD : avx512_cvtps2pd<0x5A, "vcvtps2pd">, +defm VCVTPS2PD : avx512_cvtps2pd<0x5A, "vcvtps2pd", SSE_CVT_PS2PD>, PS, EVEX_CD8<32, CD8VH>; def : Pat<(v8f64 (extloadv8f32 addr:$src)), @@ -6720,75 +6876,80 @@ let Predicates = [HasVLX] in { // Convert Signed/Unsigned Doubleword to Double multiclass avx512_cvtdq2pd opc, string OpcodeStr, SDNode OpNode, - SDNode OpNode128> { + SDNode OpNode128, OpndItins itins> { // No rounding in this op let Predicates = [HasAVX512] in - defm Z : avx512_vcvt_fp, - EVEX_V512; + defm Z : avx512_vcvt_fp, EVEX_V512; let Predicates = [HasVLX] in { defm Z128 : avx512_vcvt_fp, EVEX_V128; - defm Z256 : avx512_vcvt_fp, - EVEX_V256; + OpNode128, itins, "{1to2}", "", i64mem>, EVEX_V128; + defm Z256 : avx512_vcvt_fp, EVEX_V256; } } // Convert Signed/Unsigned Doubleword to Float multiclass avx512_cvtdq2ps opc, string OpcodeStr, SDNode OpNode, - SDNode OpNodeRnd> { + SDNode OpNodeRnd, OpndItins itins> { let Predicates = [HasAVX512] in - defm Z : avx512_vcvt_fp, + defm Z : avx512_vcvt_fp, avx512_vcvt_fp_rc, EVEX_V512; + OpNodeRnd, itins>, EVEX_V512; let Predicates = [HasVLX] in { - defm Z128 : avx512_vcvt_fp, - EVEX_V128; - defm Z256 : avx512_vcvt_fp, - EVEX_V256; + defm Z128 : avx512_vcvt_fp, EVEX_V128; + defm Z256 : avx512_vcvt_fp, EVEX_V256; } } // Convert Float to Signed/Unsigned Doubleword with truncation -multiclass avx512_cvttps2dq opc, string OpcodeStr, - SDNode OpNode, SDNode OpNodeRnd> { +multiclass avx512_cvttps2dq opc, string OpcodeStr, SDNode OpNode, + SDNode OpNodeRnd, OpndItins itins> { let Predicates = [HasAVX512] in { - defm Z : avx512_vcvt_fp, + defm Z : avx512_vcvt_fp, avx512_vcvt_fp_sae, EVEX_V512; + OpNodeRnd, itins>, EVEX_V512; } let Predicates = [HasVLX] in { - defm Z128 : avx512_vcvt_fp, - EVEX_V128; - defm Z256 : avx512_vcvt_fp, - EVEX_V256; + defm Z128 : avx512_vcvt_fp, EVEX_V128; + defm Z256 : avx512_vcvt_fp, EVEX_V256; } } // Convert Float to Signed/Unsigned Doubleword -multiclass avx512_cvtps2dq opc, string OpcodeStr, - SDNode OpNode, SDNode OpNodeRnd> { +multiclass avx512_cvtps2dq opc, string OpcodeStr, SDNode OpNode, + SDNode OpNodeRnd, OpndItins itins> { let Predicates = [HasAVX512] in { - defm Z : avx512_vcvt_fp, + defm Z : avx512_vcvt_fp, avx512_vcvt_fp_rc, EVEX_V512; + OpNodeRnd, itins>, EVEX_V512; } let Predicates = [HasVLX] in { - defm Z128 : avx512_vcvt_fp, - EVEX_V128; - defm Z256 : avx512_vcvt_fp, - EVEX_V256; + defm Z128 : avx512_vcvt_fp, EVEX_V128; + defm Z256 : avx512_vcvt_fp, EVEX_V256; } } // Convert Double to Signed/Unsigned Doubleword with truncation multiclass avx512_cvttpd2dq opc, string OpcodeStr, SDNode OpNode, - SDNode OpNode128, SDNode OpNodeRnd> { + SDNode OpNode128, SDNode OpNodeRnd, + OpndItins itins> { let Predicates = [HasAVX512] in { - defm Z : avx512_vcvt_fp, + defm Z : avx512_vcvt_fp, avx512_vcvt_fp_sae, EVEX_V512; + OpNodeRnd, itins>, EVEX_V512; } let Predicates = [HasVLX] in { // we need "x"/"y" suffixes in order to distinguish between 128 and 256 @@ -6796,9 +6957,9 @@ multiclass avx512_cvttpd2dq opc, string OpcodeStr, SDNode OpNode, // dest type - 'v4i32x_info'. We also specify the broadcast string explicitly // due to the same reason. defm Z128 : avx512_vcvt_fp, EVEX_V128; + OpNode128, itins, "{1to2}", "{x}">, EVEX_V128; defm Z256 : avx512_vcvt_fp, EVEX_V256; + itins, "{1to4}", "{y}">, EVEX_V256; def : InstAlias(NAME # "Z128rr") VR128X:$dst, VR128X:$src), 0>; @@ -6812,12 +6973,13 @@ multiclass avx512_cvttpd2dq opc, string OpcodeStr, SDNode OpNode, } // Convert Double to Signed/Unsigned Doubleword -multiclass avx512_cvtpd2dq opc, string OpcodeStr, - SDNode OpNode, SDNode OpNodeRnd> { +multiclass avx512_cvtpd2dq opc, string OpcodeStr, SDNode OpNode, + SDNode OpNodeRnd, OpndItins itins> { let Predicates = [HasAVX512] in { - defm Z : avx512_vcvt_fp, + defm Z : avx512_vcvt_fp, avx512_vcvt_fp_rc, EVEX_V512; + OpNodeRnd, itins>, EVEX_V512; } let Predicates = [HasVLX] in { // we need "x"/"y" suffixes in order to distinguish between 128 and 256 @@ -6825,9 +6987,9 @@ multiclass avx512_cvtpd2dq opc, string OpcodeStr, // dest type - 'v4i32x_info'. We also specify the broadcast string explicitly // due to the same reason. defm Z128 : avx512_vcvt_fp, EVEX_V128; + itins, "{1to2}", "{x}">, EVEX_V128; defm Z256 : avx512_vcvt_fp, EVEX_V256; + itins, "{1to4}", "{y}">, EVEX_V256; def : InstAlias(NAME # "Z128rr") VR128X:$dst, VR128X:$src), 0>; @@ -6841,96 +7003,102 @@ multiclass avx512_cvtpd2dq opc, string OpcodeStr, } // Convert Double to Signed/Unsigned Quardword -multiclass avx512_cvtpd2qq opc, string OpcodeStr, - SDNode OpNode, SDNode OpNodeRnd> { +multiclass avx512_cvtpd2qq opc, string OpcodeStr, SDNode OpNode, + SDNode OpNodeRnd, OpndItins itins> { let Predicates = [HasDQI] in { - defm Z : avx512_vcvt_fp, + defm Z : avx512_vcvt_fp, avx512_vcvt_fp_rc, EVEX_V512; + OpNodeRnd,itins>, EVEX_V512; } let Predicates = [HasDQI, HasVLX] in { - defm Z128 : avx512_vcvt_fp, - EVEX_V128; - defm Z256 : avx512_vcvt_fp, - EVEX_V256; + defm Z128 : avx512_vcvt_fp, EVEX_V128; + defm Z256 : avx512_vcvt_fp, EVEX_V256; } } // Convert Double to Signed/Unsigned Quardword with truncation -multiclass avx512_cvttpd2qq opc, string OpcodeStr, - SDNode OpNode, SDNode OpNodeRnd> { +multiclass avx512_cvttpd2qq opc, string OpcodeStr, SDNode OpNode, + SDNode OpNodeRnd, OpndItins itins> { let Predicates = [HasDQI] in { - defm Z : avx512_vcvt_fp, + defm Z : avx512_vcvt_fp, avx512_vcvt_fp_sae, EVEX_V512; + OpNodeRnd, itins>, EVEX_V512; } let Predicates = [HasDQI, HasVLX] in { - defm Z128 : avx512_vcvt_fp, - EVEX_V128; - defm Z256 : avx512_vcvt_fp, - EVEX_V256; + defm Z128 : avx512_vcvt_fp, EVEX_V128; + defm Z256 : avx512_vcvt_fp, EVEX_V256; } } // Convert Signed/Unsigned Quardword to Double -multiclass avx512_cvtqq2pd opc, string OpcodeStr, - SDNode OpNode, SDNode OpNodeRnd> { +multiclass avx512_cvtqq2pd opc, string OpcodeStr, SDNode OpNode, + SDNode OpNodeRnd, OpndItins itins> { let Predicates = [HasDQI] in { - defm Z : avx512_vcvt_fp, + defm Z : avx512_vcvt_fp, avx512_vcvt_fp_rc, EVEX_V512; + OpNodeRnd, itins>, EVEX_V512; } let Predicates = [HasDQI, HasVLX] in { - defm Z128 : avx512_vcvt_fp, - EVEX_V128; - defm Z256 : avx512_vcvt_fp, - EVEX_V256; + defm Z128 : avx512_vcvt_fp, EVEX_V128; + defm Z256 : avx512_vcvt_fp, EVEX_V256; } } // Convert Float to Signed/Unsigned Quardword -multiclass avx512_cvtps2qq opc, string OpcodeStr, - SDNode OpNode, SDNode OpNodeRnd> { +multiclass avx512_cvtps2qq opc, string OpcodeStr, SDNode OpNode, + SDNode OpNodeRnd, OpndItins itins> { let Predicates = [HasDQI] in { - defm Z : avx512_vcvt_fp, + defm Z : avx512_vcvt_fp, avx512_vcvt_fp_rc, EVEX_V512; + OpNodeRnd, itins>, EVEX_V512; } let Predicates = [HasDQI, HasVLX] in { // Explicitly specified broadcast string, since we take only 2 elements // from v4f32x_info source defm Z128 : avx512_vcvt_fp, EVEX_V128; - defm Z256 : avx512_vcvt_fp, - EVEX_V256; + itins, "{1to2}", "", f64mem>, EVEX_V128; + defm Z256 : avx512_vcvt_fp, EVEX_V256; } } // Convert Float to Signed/Unsigned Quardword with truncation multiclass avx512_cvttps2qq opc, string OpcodeStr, SDNode OpNode, - SDNode OpNode128, SDNode OpNodeRnd> { + SDNode OpNode128, SDNode OpNodeRnd, OpndItins itins> { let Predicates = [HasDQI] in { - defm Z : avx512_vcvt_fp, + defm Z : avx512_vcvt_fp, avx512_vcvt_fp_sae, EVEX_V512; + OpNodeRnd, itins>, EVEX_V512; } let Predicates = [HasDQI, HasVLX] in { // Explicitly specified broadcast string, since we take only 2 elements // from v4f32x_info source defm Z128 : avx512_vcvt_fp, EVEX_V128; - defm Z256 : avx512_vcvt_fp, - EVEX_V256; + itins, "{1to2}", "", f64mem>, EVEX_V128; + defm Z256 : avx512_vcvt_fp, EVEX_V256; } } // Convert Signed/Unsigned Quardword to Float multiclass avx512_cvtqq2ps opc, string OpcodeStr, SDNode OpNode, - SDNode OpNode128, SDNode OpNodeRnd> { + SDNode OpNode128, SDNode OpNodeRnd, OpndItins itins> { let Predicates = [HasDQI] in { - defm Z : avx512_vcvt_fp, + defm Z : avx512_vcvt_fp, avx512_vcvt_fp_rc, EVEX_V512; + OpNodeRnd, itins>, EVEX_V512; } let Predicates = [HasDQI, HasVLX] in { // we need "x"/"y" suffixes in order to distinguish between 128 and 256 @@ -6938,9 +7106,9 @@ multiclass avx512_cvtqq2ps opc, string OpcodeStr, SDNode OpNode, // dest type - 'v4i32x_info'. We also specify the broadcast string explicitly // due to the same reason. defm Z128 : avx512_vcvt_fp, EVEX_V128; + itins, "{1to2}", "{x}">, EVEX_V128; defm Z256 : avx512_vcvt_fp, EVEX_V256; + itins, "{1to4}", "{y}">, EVEX_V256; def : InstAlias(NAME # "Z128rr") VR128X:$dst, VR128X:$src), 0>; @@ -6953,89 +7121,100 @@ multiclass avx512_cvtqq2ps opc, string OpcodeStr, SDNode OpNode, } } -defm VCVTDQ2PD : avx512_cvtdq2pd<0xE6, "vcvtdq2pd", sint_to_fp, X86VSintToFP>, - XS, EVEX_CD8<32, CD8VH>; +defm VCVTDQ2PD : avx512_cvtdq2pd<0xE6, "vcvtdq2pd", sint_to_fp, X86VSintToFP, + SSE_CVT_I2PD>, XS, EVEX_CD8<32, CD8VH>; defm VCVTDQ2PS : avx512_cvtdq2ps<0x5B, "vcvtdq2ps", sint_to_fp, - X86VSintToFpRnd>, + X86VSintToFpRnd, SSE_CVT_I2PS>, PS, EVEX_CD8<32, CD8VF>; defm VCVTTPS2DQ : avx512_cvttps2dq<0x5B, "vcvttps2dq", fp_to_sint, - X86cvttp2siRnd>, + X86cvttp2siRnd, SSE_CVT_PS2I>, XS, EVEX_CD8<32, CD8VF>; defm VCVTTPD2DQ : avx512_cvttpd2dq<0xE6, "vcvttpd2dq", fp_to_sint, X86cvttp2si, - X86cvttp2siRnd>, + X86cvttp2siRnd, SSE_CVT_PD2I>, PD, VEX_W, EVEX_CD8<64, CD8VF>; defm VCVTTPS2UDQ : avx512_cvttps2dq<0x78, "vcvttps2udq", fp_to_uint, - X86cvttp2uiRnd>, PS, + X86cvttp2uiRnd, SSE_CVT_PS2I>, PS, EVEX_CD8<32, CD8VF>; defm VCVTTPD2UDQ : avx512_cvttpd2dq<0x78, "vcvttpd2udq", fp_to_uint, - X86cvttp2ui, X86cvttp2uiRnd>, PS, VEX_W, - EVEX_CD8<64, CD8VF>; + X86cvttp2ui, X86cvttp2uiRnd, SSE_CVT_PD2I>, + PS, VEX_W, EVEX_CD8<64, CD8VF>; -defm VCVTUDQ2PD : avx512_cvtdq2pd<0x7A, "vcvtudq2pd", uint_to_fp, X86VUintToFP>, - XS, EVEX_CD8<32, CD8VH>; +defm VCVTUDQ2PD : avx512_cvtdq2pd<0x7A, "vcvtudq2pd", uint_to_fp, + X86VUintToFP, SSE_CVT_I2PD>, XS, + EVEX_CD8<32, CD8VH>; defm VCVTUDQ2PS : avx512_cvtdq2ps<0x7A, "vcvtudq2ps", uint_to_fp, - X86VUintToFpRnd>, XD, + X86VUintToFpRnd, SSE_CVT_I2PS>, XD, EVEX_CD8<32, CD8VF>; defm VCVTPS2DQ : avx512_cvtps2dq<0x5B, "vcvtps2dq", X86cvtp2Int, - X86cvtp2IntRnd>, PD, EVEX_CD8<32, CD8VF>; + X86cvtp2IntRnd, SSE_CVT_PS2I>, PD, + EVEX_CD8<32, CD8VF>; defm VCVTPD2DQ : avx512_cvtpd2dq<0xE6, "vcvtpd2dq", X86cvtp2Int, - X86cvtp2IntRnd>, XD, VEX_W, - EVEX_CD8<64, CD8VF>; + X86cvtp2IntRnd, SSE_CVT_PD2I>, XD, + VEX_W, EVEX_CD8<64, CD8VF>; defm VCVTPS2UDQ : avx512_cvtps2dq<0x79, "vcvtps2udq", X86cvtp2UInt, - X86cvtp2UIntRnd>, + X86cvtp2UIntRnd, SSE_CVT_PS2I>, PS, EVEX_CD8<32, CD8VF>; + defm VCVTPD2UDQ : avx512_cvtpd2dq<0x79, "vcvtpd2udq", X86cvtp2UInt, - X86cvtp2UIntRnd>, VEX_W, + X86cvtp2UIntRnd, SSE_CVT_PD2I>, VEX_W, PS, EVEX_CD8<64, CD8VF>; defm VCVTPD2QQ : avx512_cvtpd2qq<0x7B, "vcvtpd2qq", X86cvtp2Int, - X86cvtp2IntRnd>, VEX_W, + X86cvtp2IntRnd, SSE_CVT_PD2I>, VEX_W, PD, EVEX_CD8<64, CD8VF>; defm VCVTPS2QQ : avx512_cvtps2qq<0x7B, "vcvtps2qq", X86cvtp2Int, - X86cvtp2IntRnd>, PD, EVEX_CD8<32, CD8VH>; + X86cvtp2IntRnd, SSE_CVT_PS2I>, PD, + EVEX_CD8<32, CD8VH>; defm VCVTPD2UQQ : avx512_cvtpd2qq<0x79, "vcvtpd2uqq", X86cvtp2UInt, - X86cvtp2UIntRnd>, VEX_W, + X86cvtp2UIntRnd, SSE_CVT_PD2I>, VEX_W, PD, EVEX_CD8<64, CD8VF>; defm VCVTPS2UQQ : avx512_cvtps2qq<0x79, "vcvtps2uqq", X86cvtp2UInt, - X86cvtp2UIntRnd>, PD, EVEX_CD8<32, CD8VH>; + X86cvtp2UIntRnd, SSE_CVT_PS2I>, PD, + EVEX_CD8<32, CD8VH>; defm VCVTTPD2QQ : avx512_cvttpd2qq<0x7A, "vcvttpd2qq", fp_to_sint, - X86cvttp2siRnd>, VEX_W, + X86cvttp2siRnd, SSE_CVT_PD2I>, VEX_W, PD, EVEX_CD8<64, CD8VF>; defm VCVTTPS2QQ : avx512_cvttps2qq<0x7A, "vcvttps2qq", fp_to_sint, X86cvttp2si, - X86cvttp2siRnd>, PD, EVEX_CD8<32, CD8VH>; + X86cvttp2siRnd, SSE_CVT_PS2I>, PD, + EVEX_CD8<32, CD8VH>; defm VCVTTPD2UQQ : avx512_cvttpd2qq<0x78, "vcvttpd2uqq", fp_to_uint, - X86cvttp2uiRnd>, VEX_W, + X86cvttp2uiRnd, SSE_CVT_PD2I>, VEX_W, PD, EVEX_CD8<64, CD8VF>; defm VCVTTPS2UQQ : avx512_cvttps2qq<0x78, "vcvttps2uqq", fp_to_uint, X86cvttp2ui, - X86cvttp2uiRnd>, PD, EVEX_CD8<32, CD8VH>; + X86cvttp2uiRnd, SSE_CVT_PS2I>, PD, + EVEX_CD8<32, CD8VH>; defm VCVTQQ2PD : avx512_cvtqq2pd<0xE6, "vcvtqq2pd", sint_to_fp, - X86VSintToFpRnd>, VEX_W, XS, EVEX_CD8<64, CD8VF>; + X86VSintToFpRnd, SSE_CVT_I2PD>, VEX_W, XS, + EVEX_CD8<64, CD8VF>; defm VCVTUQQ2PD : avx512_cvtqq2pd<0x7A, "vcvtuqq2pd", uint_to_fp, - X86VUintToFpRnd>, VEX_W, XS, EVEX_CD8<64, CD8VF>; + X86VUintToFpRnd, SSE_CVT_I2PD>, VEX_W, XS, + EVEX_CD8<64, CD8VF>; defm VCVTQQ2PS : avx512_cvtqq2ps<0x5B, "vcvtqq2ps", sint_to_fp, X86VSintToFP, - X86VSintToFpRnd>, VEX_W, PS, EVEX_CD8<64, CD8VF>; + X86VSintToFpRnd, SSE_CVT_I2PS>, VEX_W, PS, + EVEX_CD8<64, CD8VF>; defm VCVTUQQ2PS : avx512_cvtqq2ps<0x7A, "vcvtuqq2ps", uint_to_fp, X86VUintToFP, - X86VUintToFpRnd>, VEX_W, XD, EVEX_CD8<64, CD8VF>; + X86VUintToFpRnd, SSE_CVT_I2PS>, VEX_W, XD, + EVEX_CD8<64, CD8VF>; let Predicates = [HasAVX512, NoVLX] in { def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))), @@ -7195,37 +7374,45 @@ def : Pat<(v4f64 (uint_to_fp (v4i64 VR256X:$src1))), //===----------------------------------------------------------------------===// // Half precision conversion instructions //===----------------------------------------------------------------------===// + multiclass avx512_cvtph2ps { + X86MemOperand x86memop, PatFrag ld_frag, + OpndItins itins> { defm rr : AVX512_maskable<0x13, MRMSrcReg, _dest ,(outs _dest.RC:$dst), (ins _src.RC:$src), "vcvtph2ps", "$src", "$src", - (X86cvtph2ps (_src.VT _src.RC:$src))>, T8PD; + (X86cvtph2ps (_src.VT _src.RC:$src)),itins.rr>, + T8PD, Sched<[itins.Sched]>; defm rm : AVX512_maskable<0x13, MRMSrcMem, _dest, (outs _dest.RC:$dst), (ins x86memop:$src), "vcvtph2ps", "$src", "$src", (X86cvtph2ps (_src.VT (bitconvert - (ld_frag addr:$src))))>, T8PD; + (ld_frag addr:$src)))), itins.rm>, + T8PD, Sched<[itins.Sched.Folded]>; } -multiclass avx512_cvtph2ps_sae { +multiclass avx512_cvtph2ps_sae { defm rb : AVX512_maskable<0x13, MRMSrcReg, _dest, (outs _dest.RC:$dst), (ins _src.RC:$src), "vcvtph2ps", "{sae}, $src", "$src, {sae}", (X86cvtph2psRnd (_src.VT _src.RC:$src), - (i32 FROUND_NO_EXC))>, T8PD, EVEX_B; - + (i32 FROUND_NO_EXC)), itins.rr>, + T8PD, EVEX_B, Sched<[itins.Sched]>; } let Predicates = [HasAVX512] in - defm VCVTPH2PSZ : avx512_cvtph2ps, - avx512_cvtph2ps_sae, + defm VCVTPH2PSZ : avx512_cvtph2ps, + avx512_cvtph2ps_sae, EVEX, EVEX_V512, EVEX_CD8<32, CD8VH>; let Predicates = [HasVLX] in { defm VCVTPH2PSZ256 : avx512_cvtph2ps,EVEX, EVEX_V256, EVEX_CD8<32, CD8VH>; + loadv2i64, SSE_CVT_PH2PS>, EVEX, EVEX_V256, + EVEX_CD8<32, CD8VH>; defm VCVTPH2PSZ128 : avx512_cvtph2ps, EVEX, EVEX_V128, EVEX_CD8<32, CD8VH>; + loadv2i64, SSE_CVT_PH2PS>, EVEX, EVEX_V128, + EVEX_CD8<32, CD8VH>; // Pattern match vcvtph2ps of a scalar i64 load. def : Pat<(v4f32 (X86cvtph2ps (v8i16 (vzmovl_v2i64 addr:$src)))), @@ -7238,41 +7425,48 @@ let Predicates = [HasVLX] in { } multiclass avx512_cvtps2ph { + X86MemOperand x86memop, OpndItins itins> { defm rr : AVX512_maskable<0x1D, MRMDestReg, _dest ,(outs _dest.RC:$dst), (ins _src.RC:$src1, i32u8imm:$src2), "vcvtps2ph", "$src2, $src1", "$src1, $src2", (X86cvtps2ph (_src.VT _src.RC:$src1), (i32 imm:$src2)), - NoItinerary, 0, 0>, AVX512AIi8Base; + itins.rr, 0, 0>, AVX512AIi8Base, Sched<[itins.Sched]>; let hasSideEffects = 0, mayStore = 1 in { def mr : AVX512AIi8<0x1D, MRMDestMem, (outs), (ins x86memop:$dst, _src.RC:$src1, i32u8imm:$src2), "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", - []>; + [], itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>; def mrk : AVX512AIi8<0x1D, MRMDestMem, (outs), (ins x86memop:$dst, _dest.KRCWM:$mask, _src.RC:$src1, i32u8imm:$src2), "vcvtps2ph\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}", - []>, EVEX_K; + [], itins.rm>, EVEX_K, Sched<[itins.Sched.Folded, ReadAfterLd]>; } } -multiclass avx512_cvtps2ph_sae { + +multiclass avx512_cvtps2ph_sae { let hasSideEffects = 0 in defm rb : AVX512_maskable_in_asm<0x1D, MRMDestReg, _dest, (outs _dest.RC:$dst), (ins _src.RC:$src1, i32u8imm:$src2), "vcvtps2ph", "$src2, {sae}, $src1", "$src1, {sae}, $src2", - []>, EVEX_B, AVX512AIi8Base; + [], itins.rr>, EVEX_B, AVX512AIi8Base, Sched<[itins.Sched]>; } + let Predicates = [HasAVX512] in { - defm VCVTPS2PHZ : avx512_cvtps2ph, - avx512_cvtps2ph_sae, - EVEX, EVEX_V512, EVEX_CD8<32, CD8VH>; + defm VCVTPS2PHZ : avx512_cvtps2ph, + avx512_cvtps2ph_sae, EVEX, EVEX_V512, + EVEX_CD8<32, CD8VH>; let Predicates = [HasVLX] in { - defm VCVTPS2PHZ256 : avx512_cvtps2ph, - EVEX, EVEX_V256, EVEX_CD8<32, CD8VH>; - defm VCVTPS2PHZ128 : avx512_cvtps2ph, - EVEX, EVEX_V128, EVEX_CD8<32, CD8VH>; + defm VCVTPS2PHZ256 : avx512_cvtps2ph, EVEX, EVEX_V256, + EVEX_CD8<32, CD8VH>; + defm VCVTPS2PHZ128 : avx512_cvtps2ph, EVEX, EVEX_V128, + EVEX_CD8<32, CD8VH>; } def : Pat<(store (f64 (extractelt @@ -7364,175 +7558,193 @@ let Defs = [EFLAGS], Predicates = [HasAVX512] in { /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd multiclass avx512_fp14_s opc, string OpcodeStr, SDNode OpNode, - X86VectorVTInfo _> { + OpndItins itins, X86VectorVTInfo _> { let Predicates = [HasAVX512], ExeDomain = _.ExeDomain in { defm rr : AVX512_maskable_scalar, EVEX_4V; + (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2)), itins.rr>, + EVEX_4V, Sched<[itins.Sched]>; defm rm : AVX512_maskable_scalar, EVEX_4V; + _.ScalarIntMemCPat:$src2), itins.rm>, EVEX_4V, + Sched<[itins.Sched.Folded, ReadAfterLd]>; } } -defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", X86rcp14s, f32x_info>, +defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", X86rcp14s, SSE_RCPS, f32x_info>, EVEX_CD8<32, CD8VT1>, T8PD, NotMemoryFoldable; -defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", X86rcp14s, f64x_info>, +defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", X86rcp14s, SSE_RCPS, f64x_info>, VEX_W, EVEX_CD8<64, CD8VT1>, T8PD, NotMemoryFoldable; -defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", X86rsqrt14s, f32x_info>, +defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", X86rsqrt14s, SSE_RSQRTSS, f32x_info>, EVEX_CD8<32, CD8VT1>, T8PD, NotMemoryFoldable; -defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", X86rsqrt14s, f64x_info>, +defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", X86rsqrt14s, SSE_RSQRTSS, f64x_info>, VEX_W, EVEX_CD8<64, CD8VT1>, T8PD, NotMemoryFoldable; /// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd multiclass avx512_fp14_p opc, string OpcodeStr, SDNode OpNode, - X86VectorVTInfo _> { + OpndItins itins, X86VectorVTInfo _> { let ExeDomain = _.ExeDomain in { defm r: AVX512_maskable, EVEX, T8PD; + (_.FloatVT (OpNode _.RC:$src)), itins.rr>, EVEX, T8PD, + Sched<[itins.Sched]>; defm m: AVX512_maskable, EVEX, T8PD; + (bitconvert (_.LdFrag addr:$src)))), itins.rm>, EVEX, T8PD, + Sched<[itins.Sched.Folded, ReadAfterLd]>; defm mb: AVX512_maskable, - EVEX, T8PD, EVEX_B; + (X86VBroadcast (_.ScalarLdFrag addr:$src)))), itins.rm>, + EVEX, T8PD, EVEX_B, Sched<[itins.Sched.Folded, ReadAfterLd]>; } } -multiclass avx512_fp14_p_vl_all opc, string OpcodeStr, SDNode OpNode> { - defm PSZ : avx512_fp14_p, - EVEX_V512, EVEX_CD8<32, CD8VF>; - defm PDZ : avx512_fp14_p, - EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>; +multiclass avx512_fp14_p_vl_all opc, string OpcodeStr, SDNode OpNode, + SizeItins itins> { + defm PSZ : avx512_fp14_p, EVEX_V512, EVEX_CD8<32, CD8VF>; + defm PDZ : avx512_fp14_p, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>; // Define only if AVX512VL feature is present. let Predicates = [HasVLX] in { defm PSZ128 : avx512_fp14_p, + OpNode, itins.s, v4f32x_info>, EVEX_V128, EVEX_CD8<32, CD8VF>; defm PSZ256 : avx512_fp14_p, + OpNode, itins.s, v8f32x_info>, EVEX_V256, EVEX_CD8<32, CD8VF>; defm PDZ128 : avx512_fp14_p, + OpNode, itins.d, v2f64x_info>, EVEX_V128, VEX_W, EVEX_CD8<64, CD8VF>; defm PDZ256 : avx512_fp14_p, + OpNode, itins.d, v4f64x_info>, EVEX_V256, VEX_W, EVEX_CD8<64, CD8VF>; } } -defm VRSQRT14 : avx512_fp14_p_vl_all<0x4E, "vrsqrt14", X86rsqrt14>; -defm VRCP14 : avx512_fp14_p_vl_all<0x4C, "vrcp14", X86rcp14>; +defm VRSQRT14 : avx512_fp14_p_vl_all<0x4E, "vrsqrt14", X86rsqrt14, SSE_RSQRT_P>; +defm VRCP14 : avx512_fp14_p_vl_all<0x4C, "vrcp14", X86rcp14, SSE_RCP_P>; /// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd multiclass avx512_fp28_s opc, string OpcodeStr,X86VectorVTInfo _, - SDNode OpNode> { + SDNode OpNode, OpndItins itins> { let ExeDomain = _.ExeDomain in { defm r : AVX512_maskable_scalar; + (i32 FROUND_CURRENT)), itins.rr>, + Sched<[itins.Sched]>; defm rb : AVX512_maskable_scalar, EVEX_B; + (i32 FROUND_NO_EXC)), itins.rm>, EVEX_B, + Sched<[itins.Sched.Folded, ReadAfterLd]>; defm m : AVX512_maskable_scalar; + (i32 FROUND_CURRENT)), itins.rm>, + Sched<[itins.Sched.Folded, ReadAfterLd]>; } } -multiclass avx512_eri_s opc, string OpcodeStr, SDNode OpNode> { - defm SS : avx512_fp28_s, +multiclass avx512_eri_s opc, string OpcodeStr, SDNode OpNode, + SizeItins itins> { + defm SS : avx512_fp28_s, EVEX_CD8<32, CD8VT1>; - defm SD : avx512_fp28_s, + defm SD : avx512_fp28_s, EVEX_CD8<64, CD8VT1>, VEX_W; } let Predicates = [HasERI] in { - defm VRCP28 : avx512_eri_s<0xCB, "vrcp28", X86rcp28s>, T8PD, EVEX_4V; - defm VRSQRT28 : avx512_eri_s<0xCD, "vrsqrt28", X86rsqrt28s>, T8PD, EVEX_4V; + defm VRCP28 : avx512_eri_s<0xCB, "vrcp28", X86rcp28s, SSE_RCP_S>, + T8PD, EVEX_4V; + defm VRSQRT28 : avx512_eri_s<0xCD, "vrsqrt28", X86rsqrt28s, SSE_RSQRT_S>, + T8PD, EVEX_4V; } -defm VGETEXP : avx512_eri_s<0x43, "vgetexp", X86fgetexpRnds>, T8PD, EVEX_4V; +defm VGETEXP : avx512_eri_s<0x43, "vgetexp", X86fgetexpRnds, SSE_ALU_ITINS_S>, + T8PD, EVEX_4V; /// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd multiclass avx512_fp28_p opc, string OpcodeStr, X86VectorVTInfo _, - SDNode OpNode> { + SDNode OpNode, OpndItins itins> { let ExeDomain = _.ExeDomain in { defm r : AVX512_maskable; + (OpNode (_.VT _.RC:$src), (i32 FROUND_CURRENT)), + itins.rr>, Sched<[itins.Sched]>; defm m : AVX512_maskable; + (i32 FROUND_CURRENT)), itins.rm>, + Sched<[itins.Sched.Folded, ReadAfterLd]>; defm mb : AVX512_maskable, EVEX_B; + (i32 FROUND_CURRENT)), itins.rm>, EVEX_B, + Sched<[itins.Sched.Folded, ReadAfterLd]>; } } multiclass avx512_fp28_p_round opc, string OpcodeStr, X86VectorVTInfo _, - SDNode OpNode> { + SDNode OpNode, OpndItins itins> { let ExeDomain = _.ExeDomain in defm rb : AVX512_maskable, EVEX_B; + (OpNode (_.VT _.RC:$src), (i32 FROUND_NO_EXC)), + itins.rr>, EVEX_B, Sched<[itins.Sched]>; } -multiclass avx512_eri opc, string OpcodeStr, SDNode OpNode> { - defm PS : avx512_fp28_p, - avx512_fp28_p_round, +multiclass avx512_eri opc, string OpcodeStr, SDNode OpNode, + SizeItins itins> { + defm PS : avx512_fp28_p, + avx512_fp28_p_round, T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>; - defm PD : avx512_fp28_p, - avx512_fp28_p_round, + defm PD : avx512_fp28_p, + avx512_fp28_p_round, T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>; } multiclass avx512_fp_unaryop_packed opc, string OpcodeStr, - SDNode OpNode> { + SDNode OpNode, SizeItins itins> { // Define only if AVX512VL feature is present. let Predicates = [HasVLX] in { - defm PSZ128 : avx512_fp28_p, + defm PSZ128 : avx512_fp28_p, EVEX_V128, T8PD, EVEX_CD8<32, CD8VF>; - defm PSZ256 : avx512_fp28_p, + defm PSZ256 : avx512_fp28_p, EVEX_V256, T8PD, EVEX_CD8<32, CD8VF>; - defm PDZ128 : avx512_fp28_p, + defm PDZ128 : avx512_fp28_p, EVEX_V128, VEX_W, T8PD, EVEX_CD8<64, CD8VF>; - defm PDZ256 : avx512_fp28_p, + defm PDZ256 : avx512_fp28_p, EVEX_V256, VEX_W, T8PD, EVEX_CD8<64, CD8VF>; } } let Predicates = [HasERI] in { - defm VRSQRT28 : avx512_eri<0xCC, "vrsqrt28", X86rsqrt28>, EVEX; - defm VRCP28 : avx512_eri<0xCA, "vrcp28", X86rcp28>, EVEX; - defm VEXP2 : avx512_eri<0xC8, "vexp2", X86exp2>, EVEX; + defm VRSQRT28 : avx512_eri<0xCC, "vrsqrt28", X86rsqrt28, SSE_RSQRT_P>, EVEX; + defm VRCP28 : avx512_eri<0xCA, "vrcp28", X86rcp28, SSE_RCP_P>, EVEX; + defm VEXP2 : avx512_eri<0xC8, "vexp2", X86exp2, SSE_ALU_ITINS_P>, EVEX; } -defm VGETEXP : avx512_eri<0x42, "vgetexp", X86fgetexpRnd>, - avx512_fp_unaryop_packed<0x42, "vgetexp", X86fgetexpRnd> , EVEX; +defm VGETEXP : avx512_eri<0x42, "vgetexp", X86fgetexpRnd, SSE_ALU_ITINS_P>, + avx512_fp_unaryop_packed<0x42, "vgetexp", X86fgetexpRnd, + SSE_ALU_ITINS_P>, EVEX; multiclass avx512_sqrt_packed_round opc, string OpcodeStr, OpndItins itins, X86VectorVTInfo _>{ @@ -7668,40 +7880,42 @@ defm VSQRT : avx512_sqrt_packed_all<0x51, "vsqrt">, defm VSQRT : avx512_sqrt_scalar_all<0x51, "vsqrt">, VEX_LIG; -multiclass -avx512_rndscale_scalar opc, string OpcodeStr, X86VectorVTInfo _> { - +multiclass avx512_rndscale_scalar opc, string OpcodeStr, + OpndItins itins, X86VectorVTInfo _> { let ExeDomain = _.ExeDomain in { defm r_Int : AVX512_maskable_scalar; + (i32 imm:$src3))), itins.rr>, + Sched<[itins.Sched]>; defm rb_Int : AVX512_maskable_scalar, EVEX_B; + (i32 imm:$src3), (i32 FROUND_NO_EXC))), itins.rr>, EVEX_B, + Sched<[itins.Sched]>; defm m_Int : AVX512_maskable_scalar; + _.ScalarIntMemCPat:$src2, (i32 imm:$src3))), itins.rm>, + Sched<[itins.Sched.Folded, ReadAfterLd]>; let isCodeGenOnly = 1, hasSideEffects = 0 in { def r : I; + [], itins.rr>, Sched<[itins.Sched]>; let mayLoad = 1 in def m : I; + [], itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>; } } @@ -7742,11 +7956,12 @@ avx512_rndscale_scalar opc, string OpcodeStr, X86VectorVTInfo _> { } } -defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", f32x_info>, - AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VT1>; +defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", SSE_ALU_F32S, + f32x_info>, AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VT1>; -defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", f64x_info>, VEX_W, - AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VT1>; +defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", SSE_ALU_F64S, + f64x_info>, VEX_W, AVX512AIi8Base, EVEX_4V, + EVEX_CD8<64, CD8VT1>; //------------------------------------------------- // Integer truncate and extend operations @@ -8467,27 +8682,39 @@ defm VPMOVQ2M : avx512_convert_vector_to_mask<0x39, "vpmovq2m", // AVX-512 - COMPRESS and EXPAND // +// FIXME: Is there a better scheduler itinerary for VPCOMPRESS/VPEXPAND? +let Sched = WriteShuffle256 in { +def AVX512_COMPRESS : OpndItins< + IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM +>; +def AVX512_EXPAND : OpndItins< + IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM +>; +} + multiclass compress_by_vec_width_common opc, X86VectorVTInfo _, - string OpcodeStr> { + string OpcodeStr, OpndItins itins> { defm rr : AVX512_maskable, AVX5128IBase; + (_.VT (X86compress _.RC:$src1)), itins.rr>, AVX5128IBase, + Sched<[itins.Sched]>; let mayStore = 1, hasSideEffects = 0 in def mr : AVX5128I, EVEX_CD8<_.EltSize, CD8VT1>; + []>, EVEX_CD8<_.EltSize, CD8VT1>, + Sched<[itins.Sched.Folded]>; def mrk : AVX5128I, - EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>; + EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>, + Sched<[itins.Sched.Folded]>; } multiclass compress_by_vec_width_lowering { - def : Pat<(X86mCompressingStore addr:$dst, _.KRCWM:$mask, (_.VT _.RC:$src)), (!cast(NAME#_.ZSuffix##mrk) @@ -8495,41 +8722,44 @@ multiclass compress_by_vec_width_lowering { } multiclass compress_by_elt_width opc, string OpcodeStr, + OpndItins itins, AVX512VLVectorVTInfo VTInfo, Predicate Pred = HasAVX512> { let Predicates = [Pred] in - defm Z : compress_by_vec_width_common, + defm Z : compress_by_vec_width_common, compress_by_vec_width_lowering, EVEX_V512; let Predicates = [Pred, HasVLX] in { - defm Z256 : compress_by_vec_width_common, + defm Z256 : compress_by_vec_width_common, compress_by_vec_width_lowering, EVEX_V256; - defm Z128 : compress_by_vec_width_common, + defm Z128 : compress_by_vec_width_common, compress_by_vec_width_lowering, EVEX_V128; } } -defm VPCOMPRESSD : compress_by_elt_width <0x8B, "vpcompressd", avx512vl_i32_info>, - EVEX; -defm VPCOMPRESSQ : compress_by_elt_width <0x8B, "vpcompressq", avx512vl_i64_info>, - EVEX, VEX_W; -defm VCOMPRESSPS : compress_by_elt_width <0x8A, "vcompressps", avx512vl_f32_info>, - EVEX; -defm VCOMPRESSPD : compress_by_elt_width <0x8A, "vcompresspd", avx512vl_f64_info>, - EVEX, VEX_W; +defm VPCOMPRESSD : compress_by_elt_width <0x8B, "vpcompressd", AVX512_COMPRESS, + avx512vl_i32_info>, EVEX; +defm VPCOMPRESSQ : compress_by_elt_width <0x8B, "vpcompressq", AVX512_COMPRESS, + avx512vl_i64_info>, EVEX, VEX_W; +defm VCOMPRESSPS : compress_by_elt_width <0x8A, "vcompressps", AVX512_COMPRESS, + avx512vl_f32_info>, EVEX; +defm VCOMPRESSPD : compress_by_elt_width <0x8A, "vcompresspd", AVX512_COMPRESS, + avx512vl_f64_info>, EVEX, VEX_W; // expand multiclass expand_by_vec_width opc, X86VectorVTInfo _, - string OpcodeStr> { + string OpcodeStr, OpndItins itins> { defm rr : AVX512_maskable, AVX5128IBase; + (_.VT (X86expand _.RC:$src1)), itins.rr>, AVX5128IBase, + Sched<[itins.Sched]>; defm rm : AVX512_maskable, - AVX5128IBase, EVEX_CD8<_.EltSize, CD8VT1>; + (_.LdFrag addr:$src1))))), itins.rm>, + AVX5128IBase, EVEX_CD8<_.EltSize, CD8VT1>, + Sched<[itins.Sched.Folded, ReadAfterLd]>; } multiclass expand_by_vec_width_lowering { @@ -8545,58 +8775,62 @@ multiclass expand_by_vec_width_lowering { } multiclass expand_by_elt_width opc, string OpcodeStr, + OpndItins itins, AVX512VLVectorVTInfo VTInfo, Predicate Pred = HasAVX512> { let Predicates = [Pred] in - defm Z : expand_by_vec_width, + defm Z : expand_by_vec_width, expand_by_vec_width_lowering, EVEX_V512; let Predicates = [Pred, HasVLX] in { - defm Z256 : expand_by_vec_width, + defm Z256 : expand_by_vec_width, expand_by_vec_width_lowering, EVEX_V256; - defm Z128 : expand_by_vec_width, + defm Z128 : expand_by_vec_width, expand_by_vec_width_lowering, EVEX_V128; } } -defm VPEXPANDD : expand_by_elt_width <0x89, "vpexpandd", avx512vl_i32_info>, - EVEX; -defm VPEXPANDQ : expand_by_elt_width <0x89, "vpexpandq", avx512vl_i64_info>, - EVEX, VEX_W; -defm VEXPANDPS : expand_by_elt_width <0x88, "vexpandps", avx512vl_f32_info>, - EVEX; -defm VEXPANDPD : expand_by_elt_width <0x88, "vexpandpd", avx512vl_f64_info>, - EVEX, VEX_W; +defm VPEXPANDD : expand_by_elt_width <0x89, "vpexpandd", AVX512_EXPAND, + avx512vl_i32_info>, EVEX; +defm VPEXPANDQ : expand_by_elt_width <0x89, "vpexpandq", AVX512_EXPAND, + avx512vl_i64_info>, EVEX, VEX_W; +defm VEXPANDPS : expand_by_elt_width <0x88, "vexpandps", AVX512_EXPAND, + avx512vl_f32_info>, EVEX; +defm VEXPANDPD : expand_by_elt_width <0x88, "vexpandpd", AVX512_EXPAND, + avx512vl_f64_info>, EVEX, VEX_W; //handle instruction reg_vec1 = op(reg_vec,imm) // op(mem_vec,imm) // op(broadcast(eltVt),imm) //all instruction created with FROUND_CURRENT multiclass avx512_unary_fp_packed_imm opc, string OpcodeStr, SDNode OpNode, - X86VectorVTInfo _>{ + OpndItins itins, X86VectorVTInfo _> { let ExeDomain = _.ExeDomain in { defm rri : AVX512_maskable; + (i32 imm:$src2)), itins.rr>, Sched<[itins.Sched]>; defm rmi : AVX512_maskable; + (i32 imm:$src2)), itins.rm>, + Sched<[itins.Sched.Folded, ReadAfterLd]>; defm rmbi : AVX512_maskable, EVEX_B; + (i32 imm:$src2)), itins.rm>, EVEX_B, + Sched<[itins.Sched.Folded, ReadAfterLd]>; } } //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm),{sae} multiclass avx512_unary_fp_sae_packed_imm opc, string OpcodeStr, - SDNode OpNode, X86VectorVTInfo _>{ + SDNode OpNode, OpndItins itins, + X86VectorVTInfo _> { let ExeDomain = _.ExeDomain in defm rrib : AVX512_maskable opc, string OpcodeStr, "$src1, {sae}, $src2", (OpNode (_.VT _.RC:$src1), (i32 imm:$src2), - (i32 FROUND_NO_EXC))>, EVEX_B; + (i32 FROUND_NO_EXC)), itins.rr>, + EVEX_B, Sched<[itins.Sched]>; } multiclass avx512_common_unary_fp_sae_packed_imm opc, SDNode OpNode, - SDNode OpNodeRnd, Predicate prd>{ + SDNode OpNodeRnd, OpndItins itins, Predicate prd>{ let Predicates = [prd] in { - defm Z : avx512_unary_fp_packed_imm, - avx512_unary_fp_sae_packed_imm, - EVEX_V512; + defm Z : avx512_unary_fp_packed_imm, + avx512_unary_fp_sae_packed_imm, EVEX_V512; } let Predicates = [prd, HasVLX] in { - defm Z128 : avx512_unary_fp_packed_imm, - EVEX_V128; - defm Z256 : avx512_unary_fp_packed_imm, - EVEX_V256; + defm Z128 : avx512_unary_fp_packed_imm, EVEX_V128; + defm Z256 : avx512_unary_fp_packed_imm, EVEX_V256; } } @@ -8628,27 +8864,30 @@ multiclass avx512_common_unary_fp_sae_packed_imm opc, string OpcodeStr, SDNode OpNode, - X86VectorVTInfo _>{ + OpndItins itins, X86VectorVTInfo _>{ let ExeDomain = _.ExeDomain in { defm rri : AVX512_maskable; + (i32 imm:$src3)), itins.rr>, + Sched<[itins.Sched]>; defm rmi : AVX512_maskable; + (i32 imm:$src3)), itins.rm>, + Sched<[itins.Sched.Folded, ReadAfterLd]>; defm rmbi : AVX512_maskable, EVEX_B; + (i32 imm:$src3)), itins.rm>, EVEX_B, + Sched<[itins.Sched.Folded, ReadAfterLd]>; } } @@ -8697,27 +8936,30 @@ multiclass avx512_3Op_imm8 opc, string OpcodeStr, SDNode OpNode, //handle scalar instruction reg_vec1 = op(reg_vec2,reg_vec3,imm) // op(reg_vec2,mem_scalar,imm) multiclass avx512_fp_scalar_imm opc, string OpcodeStr, SDNode OpNode, - X86VectorVTInfo _> { + OpndItins itins, X86VectorVTInfo _> { let ExeDomain = _.ExeDomain in { defm rri : AVX512_maskable_scalar; + (i32 imm:$src3)), itins.rr>, + Sched<[itins.Sched]>; defm rmi : AVX512_maskable_scalar; + (i32 imm:$src3)), itins.rm>, + Sched<[itins.Sched.Folded, ReadAfterLd]>; } } //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm),{sae} multiclass avx512_fp_sae_packed_imm opc, string OpcodeStr, - SDNode OpNode, X86VectorVTInfo _>{ + SDNode OpNode, OpndItins itins, + X86VectorVTInfo _> { let ExeDomain = _.ExeDomain in defm rrib : AVX512_maskable opc, string OpcodeStr, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2), (i32 imm:$src3), - (i32 FROUND_NO_EXC))>, EVEX_B; + (i32 FROUND_NO_EXC)), itins.rr>, + EVEX_B, Sched<[itins.Sched]>; } + //handle scalar instruction reg_vec1 = op(reg_vec2,reg_vec3,imm),{sae} -multiclass avx512_fp_sae_scalar_imm opc, string OpcodeStr, - SDNode OpNode, X86VectorVTInfo _> { +multiclass avx512_fp_sae_scalar_imm opc, string OpcodeStr, SDNode OpNode, + OpndItins itins, X86VectorVTInfo _> { let ExeDomain = _.ExeDomain in defm NAME#rrib : AVX512_maskable_scalar opc, string OpcodeStr, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2), (i32 imm:$src3), - (i32 FROUND_NO_EXC))>, EVEX_B; + (i32 FROUND_NO_EXC)), itins.rr>, + EVEX_B, Sched<[itins.Sched]>; } multiclass avx512_common_fp_sae_packed_imm opc, SDNode OpNode, - SDNode OpNodeRnd, Predicate prd>{ + SDNode OpNodeRnd, OpndItins itins, Predicate prd>{ let Predicates = [prd] in { - defm Z : avx512_fp_packed_imm, - avx512_fp_sae_packed_imm, + defm Z : avx512_fp_packed_imm, + avx512_fp_sae_packed_imm, EVEX_V512; } let Predicates = [prd, HasVLX] in { - defm Z128 : avx512_fp_packed_imm, + defm Z128 : avx512_fp_packed_imm, EVEX_V128; - defm Z256 : avx512_fp_packed_imm, + defm Z256 : avx512_fp_packed_imm, EVEX_V256; } } @@ -8788,68 +9033,62 @@ multiclass avx512_common_3Op_imm8 opc, SDNode OpNode, - SDNode OpNodeRnd, Predicate prd>{ + SDNode OpNodeRnd, OpndItins itins, Predicate prd>{ let Predicates = [prd] in { - defm Z128 : avx512_fp_scalar_imm, - avx512_fp_sae_scalar_imm; + defm Z128 : avx512_fp_scalar_imm, + avx512_fp_sae_scalar_imm; } } multiclass avx512_common_unary_fp_sae_packed_imm_all opcPs, bits<8> opcPd, SDNode OpNode, - SDNode OpNodeRnd, Predicate prd>{ + SDNode OpNodeRnd, SizeItins itins, Predicate prd>{ defm PS : avx512_common_unary_fp_sae_packed_imm, EVEX_CD8<32, CD8VF>; + opcPs, OpNode, OpNodeRnd, itins.s, prd>, + EVEX_CD8<32, CD8VF>; defm PD : avx512_common_unary_fp_sae_packed_imm, EVEX_CD8<64, CD8VF>, VEX_W; + opcPd, OpNode, OpNodeRnd, itins.d, prd>, + EVEX_CD8<64, CD8VF>, VEX_W; } - defm VREDUCE : avx512_common_unary_fp_sae_packed_imm_all<"vreduce", 0x56, 0x56, - X86VReduce, X86VReduceRnd, HasDQI>, + X86VReduce, X86VReduceRnd, SSE_ALU_ITINS_P, HasDQI>, AVX512AIi8Base, EVEX; defm VRNDSCALE : avx512_common_unary_fp_sae_packed_imm_all<"vrndscale", 0x08, 0x09, - X86VRndScale, X86VRndScaleRnd, HasAVX512>, + X86VRndScale, X86VRndScaleRnd, SSE_ALU_ITINS_P, HasAVX512>, AVX512AIi8Base, EVEX; defm VGETMANT : avx512_common_unary_fp_sae_packed_imm_all<"vgetmant", 0x26, 0x26, - X86VGetMant, X86VGetMantRnd, HasAVX512>, + X86VGetMant, X86VGetMantRnd, SSE_ALU_ITINS_P, HasAVX512>, AVX512AIi8Base, EVEX; - defm VRANGEPD : avx512_common_fp_sae_packed_imm<"vrangepd", avx512vl_f64_info, - 0x50, X86VRange, - X86VRangeRnd, HasDQI>, + 0x50, X86VRange, X86VRangeRnd, + SSE_ALU_F64P, HasDQI>, AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W; defm VRANGEPS : avx512_common_fp_sae_packed_imm<"vrangeps", avx512vl_f32_info, - 0x50, X86VRange, - X86VRangeRnd, HasDQI>, + 0x50, X86VRange, X86VRangeRnd, + SSE_ALU_F32P, HasDQI>, AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>; -defm VRANGESD: avx512_common_fp_sae_scalar_imm<"vrangesd", f64x_info, - 0x51, X86Ranges, X86RangesRnd, - HasDQI>, +defm VRANGESD: avx512_common_fp_sae_scalar_imm<"vrangesd", + f64x_info, 0x51, X86Ranges, X86RangesRnd, SSE_ALU_F64S, HasDQI>, AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W; defm VRANGESS: avx512_common_fp_sae_scalar_imm<"vrangess", f32x_info, - 0x51, X86Ranges, X86RangesRnd, - HasDQI>, + 0x51, X86Ranges, X86RangesRnd, SSE_ALU_F32S, HasDQI>, AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>; defm VREDUCESD: avx512_common_fp_sae_scalar_imm<"vreducesd", f64x_info, - 0x57, X86Reduces, - X86ReducesRnd, HasDQI>, + 0x57, X86Reduces, X86ReducesRnd, SSE_ALU_F64S, HasDQI>, AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W; defm VREDUCESS: avx512_common_fp_sae_scalar_imm<"vreducess", f32x_info, - 0x57, X86Reduces, - X86ReducesRnd, HasDQI>, + 0x57, X86Reduces, X86ReducesRnd, SSE_ALU_F32S, HasDQI>, AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>; defm VGETMANTSD: avx512_common_fp_sae_scalar_imm<"vgetmantsd", f64x_info, - 0x27, X86GetMants, - X86GetMantsRnd, HasAVX512>, + 0x27, X86GetMants, X86GetMantsRnd, SSE_ALU_F64S, HasAVX512>, AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W; defm VGETMANTSS: avx512_common_fp_sae_scalar_imm<"vgetmantss", f32x_info, - 0x27, X86GetMants, - X86GetMantsRnd, HasAVX512>, + 0x27, X86GetMants, X86GetMantsRnd, SSE_ALU_F32S, HasAVX512>, AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>; let Predicates = [HasAVX512] in { @@ -9663,7 +9902,7 @@ def VPTERNLOG312_imm8 : SDNodeXForm; multiclass avx512_ternlog opc, string OpcodeStr, SDNode OpNode, - X86VectorVTInfo _>{ + OpndItins itins, X86VectorVTInfo _>{ let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain in { defm rri : AVX512_maskable_3src opc, string OpcodeStr, SDNode OpNode, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2), (_.VT _.RC:$src3), - (i8 imm:$src4)), NoItinerary, 1, 1>, - AVX512AIi8Base, EVEX_4V; + (i8 imm:$src4)), itins.rr, 1, 1>, + AVX512AIi8Base, EVEX_4V, Sched<[itins.Sched]>; defm rmi : AVX512_maskable_3src, - AVX512AIi8Base, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>; + (i8 imm:$src4)), itins.rm, 1, 0>, + AVX512AIi8Base, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>, + Sched<[itins.Sched.Folded, ReadAfterLd]>; defm rmbi : AVX512_maskable_3src opc, string OpcodeStr, SDNode OpNode, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2), (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src3))), - (i8 imm:$src4)), NoItinerary, 1, 0>, EVEX_B, - AVX512AIi8Base, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>; + (i8 imm:$src4)), itins.rm, 1, 0>, EVEX_B, + AVX512AIi8Base, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>, + Sched<[itins.Sched.Folded, ReadAfterLd]>; }// Constraints = "$src1 = $dst" // Additional patterns for matching passthru operand in other positions. @@ -9828,17 +10069,20 @@ multiclass avx512_ternlog opc, string OpcodeStr, SDNode OpNode, _.RC:$src2, addr:$src3, (VPTERNLOG312_imm8 imm:$src4))>; } -multiclass avx512_common_ternlog{ +multiclass avx512_common_ternlog { let Predicates = [HasAVX512] in - defm Z : avx512_ternlog<0x25, OpcodeStr, X86vpternlog, _.info512>, EVEX_V512; + defm Z : avx512_ternlog<0x25, OpcodeStr, X86vpternlog, itins, _.info512>, EVEX_V512; let Predicates = [HasAVX512, HasVLX] in { - defm Z128 : avx512_ternlog<0x25, OpcodeStr, X86vpternlog, _.info128>, EVEX_V128; - defm Z256 : avx512_ternlog<0x25, OpcodeStr, X86vpternlog, _.info256>, EVEX_V256; + defm Z128 : avx512_ternlog<0x25, OpcodeStr, X86vpternlog, itins, _.info128>, EVEX_V128; + defm Z256 : avx512_ternlog<0x25, OpcodeStr, X86vpternlog, itins, _.info256>, EVEX_V256; } } -defm VPTERNLOGD : avx512_common_ternlog<"vpternlogd", avx512vl_i32_info>; -defm VPTERNLOGQ : avx512_common_ternlog<"vpternlogq", avx512vl_i64_info>, VEX_W; +defm VPTERNLOGD : avx512_common_ternlog<"vpternlogd", SSE_INTALU_ITINS_P, + avx512vl_i32_info>; +defm VPTERNLOGQ : avx512_common_ternlog<"vpternlogq", SSE_INTALU_ITINS_P, + avx512vl_i64_info>, VEX_W; //===----------------------------------------------------------------------===// // AVX-512 - FixupImm @@ -10190,15 +10434,15 @@ defm VPSHLD : VBMI2_shift_imm<0x70, 0x71, "vpshld", X86VShld, SSE_INTMUL_IT defm VPSHRD : VBMI2_shift_imm<0x72, 0x73, "vpshrd", X86VShrd, SSE_INTMUL_ITINS_P>; // Compress -defm VPCOMPRESSB : compress_by_elt_width <0x63, "vpcompressb", avx512vl_i8_info, - HasVBMI2>, EVEX; -defm VPCOMPRESSW : compress_by_elt_width <0x63, "vpcompressw", avx512vl_i16_info, - HasVBMI2>, EVEX, VEX_W; +defm VPCOMPRESSB : compress_by_elt_width<0x63, "vpcompressb", AVX512_COMPRESS, + avx512vl_i8_info, HasVBMI2>, EVEX; +defm VPCOMPRESSW : compress_by_elt_width <0x63, "vpcompressw", AVX512_COMPRESS, + avx512vl_i16_info, HasVBMI2>, EVEX, VEX_W; // Expand -defm VPEXPANDB : expand_by_elt_width <0x62, "vpexpandb", avx512vl_i8_info, - HasVBMI2>, EVEX; -defm VPEXPANDW : expand_by_elt_width <0x62, "vpexpandw", avx512vl_i16_info, - HasVBMI2>, EVEX, VEX_W; +defm VPEXPANDB : expand_by_elt_width <0x62, "vpexpandb", AVX512_EXPAND, + avx512vl_i8_info, HasVBMI2>, EVEX; +defm VPEXPANDW : expand_by_elt_width <0x62, "vpexpandw", AVX512_EXPAND, + avx512vl_i16_info, HasVBMI2>, EVEX, VEX_W; //===----------------------------------------------------------------------===// // VNNI @@ -10256,32 +10500,35 @@ defm VPOPCNTW : avx512_unary_rm_vl<0x54, "vpopcntw", ctpop, SSE_INTALU_ITINS_P, avx512vl_i16_info, HasBITALG>, avx512_unary_lowering, VEX_W; -multiclass VPSHUFBITQMB_rm { +multiclass VPSHUFBITQMB_rm { defm rr : AVX512_maskable_cmp<0x8F, MRMSrcReg, VTI, (outs VTI.KRC:$dst), (ins VTI.RC:$src1, VTI.RC:$src2), "vpshufbitqmb", "$src2, $src1", "$src1, $src2", (X86Vpshufbitqmb (VTI.VT VTI.RC:$src1), - (VTI.VT VTI.RC:$src2))>, EVEX_4V, T8PD; + (VTI.VT VTI.RC:$src2)), itins.rr>, EVEX_4V, T8PD, + Sched<[itins.Sched]>; defm rm : AVX512_maskable_cmp<0x8F, MRMSrcMem, VTI, (outs VTI.KRC:$dst), (ins VTI.RC:$src1, VTI.MemOp:$src2), "vpshufbitqmb", "$src2, $src1", "$src1, $src2", (X86Vpshufbitqmb (VTI.VT VTI.RC:$src1), - (VTI.VT (bitconvert (VTI.LdFrag addr:$src2))))>, - EVEX_4V, EVEX_CD8<8, CD8VF>, T8PD; + (VTI.VT (bitconvert (VTI.LdFrag addr:$src2)))), + itins.rm>, EVEX_4V, EVEX_CD8<8, CD8VF>, T8PD, + Sched<[itins.Sched.Folded, ReadAfterLd]>; } -multiclass VPSHUFBITQMB_common { +multiclass VPSHUFBITQMB_common { let Predicates = [HasBITALG] in - defm Z : VPSHUFBITQMB_rm, EVEX_V512; + defm Z : VPSHUFBITQMB_rm, EVEX_V512; let Predicates = [HasBITALG, HasVLX] in { - defm Z256 : VPSHUFBITQMB_rm, EVEX_V256; - defm Z128 : VPSHUFBITQMB_rm, EVEX_V128; + defm Z256 : VPSHUFBITQMB_rm, EVEX_V256; + defm Z128 : VPSHUFBITQMB_rm, EVEX_V128; } } -defm VPSHUFBITQMB : VPSHUFBITQMB_common; +// FIXME: Is there a better scheduler itinerary for VPSHUFBITQMB? +defm VPSHUFBITQMB : VPSHUFBITQMB_common; //===----------------------------------------------------------------------===// // GFNI diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp index c1414a1baa58f..a5bff06e70b5b 100644 --- a/lib/Target/X86/X86InstrInfo.cpp +++ b/lib/Target/X86/X86InstrInfo.cpp @@ -47,8 +47,9 @@ using namespace llvm; #include "X86GenInstrInfo.inc" static cl::opt -NoFusing("disable-spill-fusing", - cl::desc("Disable fusing of spill code into instructions")); + NoFusing("disable-spill-fusing", + cl::desc("Disable fusing of spill code into instructions"), + cl::Hidden); static cl::opt PrintFailedFusing("print-failed-fuse-candidates", cl::desc("Print instructions that the allocator wants to" diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td index ed05b32f30afd..ea30393242d72 100644 --- a/lib/Target/X86/X86InstrSSE.td +++ b/lib/Target/X86/X86InstrSSE.td @@ -139,6 +139,11 @@ def SSE_INTMUL_ITINS_P : OpndItins< IIC_SSE_INTMUL_P_RR, IIC_SSE_INTMUL_P_RM >; +// FIXME: Merge SSE_INTSHIFT_P + SSE_INTSHIFT_ITINS_P. +def SSE_INTSHIFT_P : OpndItins< + IIC_SSE_INTSH_P_RR, IIC_SSE_INTSH_P_RM +>; + def SSE_INTSHIFT_ITINS_P : ShiftOpndItins< IIC_SSE_INTSH_P_RR, IIC_SSE_INTSH_P_RM, IIC_SSE_INTSH_P_RI >; @@ -1128,35 +1133,73 @@ let Constraints = "$src1 = $dst", AddedComplexity = 20 in { // SSE 1 & 2 - Conversion Instructions //===----------------------------------------------------------------------===// -def SSE_CVT_PD : OpndItins< +let Sched = WriteCvtF2I in { +def SSE_CVT_SS2SI_32 : OpndItins< + IIC_SSE_CVT_SS2SI32_RR, IIC_SSE_CVT_SS2SI32_RM +>; + +let Sched = WriteCvtF2I in +def SSE_CVT_SS2SI_64 : OpndItins< + IIC_SSE_CVT_SS2SI64_RR, IIC_SSE_CVT_SS2SI64_RM +>; + +def SSE_CVT_SD2SI : OpndItins< + IIC_SSE_CVT_SD2SI_RR, IIC_SSE_CVT_SD2SI_RM +>; + +def SSE_CVT_PS2I : OpndItins< + IIC_SSE_CVT_PS_RR, IIC_SSE_CVT_PS_RM +>; + +def SSE_CVT_PD2I : OpndItins< IIC_SSE_CVT_PD_RR, IIC_SSE_CVT_PD_RM >; +} -let Sched = WriteCvtI2F in -def SSE_CVT_PS : OpndItins< +let Sched = WriteCvtI2F in { +def SSE_CVT_SI2SS : OpndItins< + IIC_SSE_CVT_Scalar_RR, IIC_SSE_CVT_Scalar_RM +>; + +def SSE_CVT_SI2SD : OpndItins< + IIC_SSE_CVT_Scalar_RR, IIC_SSE_CVT_Scalar_RM +>; + +def SSE_CVT_I2PS : OpndItins< IIC_SSE_CVT_PS_RR, IIC_SSE_CVT_PS_RM >; -let Sched = WriteCvtI2F in -def SSE_CVT_Scalar : OpndItins< +def SSE_CVT_I2PD : OpndItins< + IIC_SSE_CVT_PD_RR, IIC_SSE_CVT_PD_RM +>; +} + +let Sched = WriteCvtF2F in { +def SSE_CVT_SD2SS : OpndItins< IIC_SSE_CVT_Scalar_RR, IIC_SSE_CVT_Scalar_RM >; -let Sched = WriteCvtF2I in -def SSE_CVT_SS2SI_32 : OpndItins< - IIC_SSE_CVT_SS2SI32_RR, IIC_SSE_CVT_SS2SI32_RM +def SSE_CVT_SS2SD : OpndItins< + IIC_SSE_CVT_Scalar_RR, IIC_SSE_CVT_Scalar_RM >; -let Sched = WriteCvtF2I in -def SSE_CVT_SS2SI_64 : OpndItins< - IIC_SSE_CVT_SS2SI64_RR, IIC_SSE_CVT_SS2SI64_RM +def SSE_CVT_PD2PS : OpndItins< + IIC_SSE_CVT_PD_RR, IIC_SSE_CVT_PD_RM >; -let Sched = WriteCvtF2I in -def SSE_CVT_SD2SI : OpndItins< - IIC_SSE_CVT_SD2SI_RR, IIC_SSE_CVT_SD2SI_RM +def SSE_CVT_PS2PD : OpndItins< + IIC_SSE_CVT_PD_RR, IIC_SSE_CVT_PD_RM +>; + +def SSE_CVT_PH2PS : OpndItins< + IIC_SSE_CVT_PS_RR, IIC_SSE_CVT_PS_RM >; +def SSE_CVT_PS2PH : OpndItins< + IIC_SSE_CVT_PS_RR, IIC_SSE_CVT_PS_RM +>; +} + // FIXME: We probably want to match the rm form only when optimizing for // size, to avoid false depenendecies (see sse_fp_unop_s for details) multiclass sse12_cvt_s opc, RegisterClass SrcRC, RegisterClass DstRC, @@ -1188,16 +1231,16 @@ let hasSideEffects = 0 in { // FIXME: We probably want to match the rm form only when optimizing for // size, to avoid false depenendecies (see sse_fp_unop_s for details) multiclass sse12_vcvt_avx opc, RegisterClass SrcRC, RegisterClass DstRC, - X86MemOperand x86memop, string asm> { + X86MemOperand x86memop, string asm, OpndItins itins> { let hasSideEffects = 0, Predicates = [UseAVX] in { def rr : SI, - Sched<[WriteCvtI2F]>; + !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), [], + itins.rr>, Sched<[itins.Sched]>; let mayLoad = 1 in def rm : SI, - Sched<[WriteCvtI2FLd, ReadAfterLd]>; + Sched<[itins.Sched.Folded, ReadAfterLd]>; } // hasSideEffects = 0 } @@ -1240,14 +1283,14 @@ def : InstAlias<"vcvttsd2si{q}\t{$src, $dst|$dst, $src}", // register, but the same isn't true when only using memory operands, // provide other assembly "l" and "q" forms to address this explicitly // where appropriate to do so. -defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss{l}">, - XS, VEX_4V, VEX_LIG; -defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">, - XS, VEX_4V, VEX_W, VEX_LIG; -defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd{l}">, - XD, VEX_4V, VEX_LIG; -defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">, - XD, VEX_4V, VEX_W, VEX_LIG; +defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss{l}", + SSE_CVT_SI2SS>, XS, VEX_4V, VEX_LIG; +defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}", + SSE_CVT_SI2SS>, XS, VEX_4V, VEX_W, VEX_LIG; +defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd{l}", + SSE_CVT_SI2SD>, XD, VEX_4V, VEX_LIG; +defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}", + SSE_CVT_SI2SD>, XD, VEX_4V, VEX_W, VEX_LIG; let Predicates = [UseAVX] in { def : InstAlias<"vcvtsi2ss\t{$src, $src1, $dst|$dst, $src1, $src}", @@ -1288,16 +1331,16 @@ defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64, SSE_CVT_SD2SI>, XD, REX_W; defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32, "cvtsi2ss{l}\t{$src, $dst|$dst, $src}", - SSE_CVT_Scalar>, XS; + SSE_CVT_SI2SS>, XS; defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64, "cvtsi2ss{q}\t{$src, $dst|$dst, $src}", - SSE_CVT_Scalar>, XS, REX_W; + SSE_CVT_SI2SS>, XS, REX_W; defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32, "cvtsi2sd{l}\t{$src, $dst|$dst, $src}", - SSE_CVT_Scalar>, XD; + SSE_CVT_SI2SD>, XD; defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64, "cvtsi2sd{q}\t{$src, $dst|$dst, $src}", - SSE_CVT_Scalar>, XD, REX_W; + SSE_CVT_SI2SD>, XD, REX_W; def : InstAlias<"cvttss2si{l}\t{$src, $dst|$dst, $src}", (CVTTSS2SIrr GR32:$dst, FR32:$src), 0>; @@ -1376,32 +1419,32 @@ let isCodeGenOnly = 1 in { let Predicates = [UseAVX] in { defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128, int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}", - SSE_CVT_Scalar, 0>, XS, VEX_4V; + SSE_CVT_SI2SS, 0>, XS, VEX_4V; defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128, int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}", - SSE_CVT_Scalar, 0>, XS, VEX_4V, + SSE_CVT_SI2SS, 0>, XS, VEX_4V, VEX_W; defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128, int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}", - SSE_CVT_Scalar, 0>, XD, VEX_4V; + SSE_CVT_SI2SD, 0>, XD, VEX_4V; defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128, int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}", - SSE_CVT_Scalar, 0>, XD, + SSE_CVT_SI2SD, 0>, XD, VEX_4V, VEX_W; } let Constraints = "$src1 = $dst" in { defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128, int_x86_sse_cvtsi2ss, i32mem, loadi32, - "cvtsi2ss{l}", SSE_CVT_Scalar>, XS; + "cvtsi2ss{l}", SSE_CVT_SI2SS>, XS; defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128, int_x86_sse_cvtsi642ss, i64mem, loadi64, - "cvtsi2ss{q}", SSE_CVT_Scalar>, XS, REX_W; + "cvtsi2ss{q}", SSE_CVT_SI2SS>, XS, REX_W; defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128, int_x86_sse2_cvtsi2sd, i32mem, loadi32, - "cvtsi2sd{l}", SSE_CVT_Scalar>, XD; + "cvtsi2sd{l}", SSE_CVT_SI2SD>, XD; defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128, int_x86_sse2_cvtsi642sd, i64mem, loadi64, - "cvtsi2sd{q}", SSE_CVT_Scalar>, XD, REX_W; + "cvtsi2sd{q}", SSE_CVT_SI2SD>, XD, REX_W; } } // isCodeGenOnly = 1 @@ -1456,16 +1499,16 @@ defm CVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64, defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, i128mem, v4f32, v4i32, loadv2i64, "vcvtdq2ps\t{$src, $dst|$dst, $src}", - SSEPackedSingle, SSE_CVT_PS>, + SSEPackedSingle, SSE_CVT_I2PS>, PS, VEX, Requires<[HasAVX, NoVLX]>, VEX_WIG; defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, i256mem, v8f32, v8i32, loadv4i64, "vcvtdq2ps\t{$src, $dst|$dst, $src}", - SSEPackedSingle, SSE_CVT_PS>, + SSEPackedSingle, SSE_CVT_I2PS>, PS, VEX, VEX_L, Requires<[HasAVX, NoVLX]>, VEX_WIG; defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, i128mem, v4f32, v4i32, memopv2i64, "cvtdq2ps\t{$src, $dst|$dst, $src}", - SSEPackedSingle, SSE_CVT_PS>, + SSEPackedSingle, SSE_CVT_I2PS>, PS, Requires<[UseSSE2]>; let Predicates = [UseAVX] in { @@ -3040,6 +3083,14 @@ def SSE_RSQRTSS : OpndItins< >; } +def SSE_RSQRT_P : SizeItins< + SSE_RSQRTPS, SSE_RSQRTPS +>; + +def SSE_RSQRT_S : SizeItins< + SSE_RSQRTSS, SSE_RSQRTSS +>; + let Sched = WriteFRcp in { def SSE_RCPP : OpndItins< IIC_SSE_RCPP_RR, IIC_SSE_RCPP_RM @@ -3050,6 +3101,14 @@ def SSE_RCPS : OpndItins< >; } +def SSE_RCP_P : SizeItins< + SSE_RCPP, SSE_RCPP +>; + +def SSE_RCP_S : SizeItins< + SSE_RCPS, SSE_RCPS +>; + /// sse_fp_unop_s - SSE1 unops in scalar form /// For the non-AVX defs, we need $src1 to be tied to $dst because /// the HW instructions are 2 operand / destructive. @@ -3875,9 +3934,14 @@ defm PCMPGTD : PDI_binop_all<0x66, "pcmpgtd", X86pcmpgt, v4i32, v8i32, // SSE2 - Packed Integer Shuffle Instructions //===---------------------------------------------------------------------===// +let Sched = WriteShuffle in +def SSE_PSHUF : OpndItins< + IIC_SSE_PSHUF_RI, IIC_SSE_PSHUF_MI +>; + let ExeDomain = SSEPackedInt in { multiclass sse2_pshuffle { + SDNode OpNode, OpndItins itins, Predicate prd> { let Predicates = [HasAVX, prd] in { def V#NAME#ri : Ii8<0x70, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, u8imm:$src2), @@ -3885,15 +3949,15 @@ let Predicates = [HasAVX, prd] in { "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), [(set VR128:$dst, (vt128 (OpNode VR128:$src1, (i8 imm:$src2))))], - IIC_SSE_PSHUF_RI>, VEX, Sched<[WriteShuffle]>, VEX_WIG; + itins.rr>, VEX, Sched<[itins.Sched]>, VEX_WIG; def V#NAME#mi : Ii8<0x70, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src1, u8imm:$src2), !strconcat("v", OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), [(set VR128:$dst, (vt128 (OpNode (bitconvert (loadv2i64 addr:$src1)), - (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>, VEX, - Sched<[WriteShuffleLd]>, VEX_WIG; + (i8 imm:$src2))))], itins.rm>, VEX, + Sched<[itins.Sched.Folded]>, VEX_WIG; } let Predicates = [HasAVX2, prd] in { @@ -3903,15 +3967,15 @@ let Predicates = [HasAVX2, prd] in { "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), [(set VR256:$dst, (vt256 (OpNode VR256:$src1, (i8 imm:$src2))))], - IIC_SSE_PSHUF_RI>, VEX, VEX_L, Sched<[WriteShuffle]>, VEX_WIG; + itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>, VEX_WIG; def V#NAME#Ymi : Ii8<0x70, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src1, u8imm:$src2), !strconcat("v", OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), [(set VR256:$dst, (vt256 (OpNode (bitconvert (loadv4i64 addr:$src1)), - (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>, VEX, VEX_L, - Sched<[WriteShuffleLd]>, VEX_WIG; + (i8 imm:$src2))))], itins.rm>, VEX, VEX_L, + Sched<[itins.Sched.Folded]>, VEX_WIG; } let Predicates = [UseSSE2] in { @@ -3921,23 +3985,24 @@ let Predicates = [UseSSE2] in { "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), [(set VR128:$dst, (vt128 (OpNode VR128:$src1, (i8 imm:$src2))))], - IIC_SSE_PSHUF_RI>, Sched<[WriteShuffle]>; + itins.rr>, Sched<[itins.Sched]>; def mi : Ii8<0x70, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src1, u8imm:$src2), !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), [(set VR128:$dst, (vt128 (OpNode (bitconvert (memopv2i64 addr:$src1)), - (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>, - Sched<[WriteShuffleLd, ReadAfterLd]>; + (i8 imm:$src2))))], itins.rm>, + Sched<[itins.Sched.Folded]>; } } } // ExeDomain = SSEPackedInt -defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, v8i32, X86PShufd, NoVLX>, PD; -defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, v16i16, X86PShufhw, +defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, v8i32, X86PShufd, SSE_PSHUF, + NoVLX>, PD; +defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, v16i16, X86PShufhw, SSE_PSHUF, NoVLX_Or_NoBWI>, XS; -defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, v16i16, X86PShuflw, +defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, v16i16, X86PShuflw, SSE_PSHUF, NoVLX_Or_NoBWI>, XD; //===---------------------------------------------------------------------===// @@ -8070,6 +8135,16 @@ let Predicates = [HasAVX1Only] in { // VPERM - Permute instructions // +let Sched = WriteFShuffle256 in +def AVX2_PERMV_F : OpndItins< + IIC_SSE_SHUFP, IIC_SSE_SHUFP +>; + +let Sched = WriteShuffle256 in +def AVX2_PERMV_I : OpndItins< + IIC_SSE_PSHUF_RI, IIC_SSE_PSHUF_MI +>; + multiclass avx2_perm opc, string OpcodeStr, PatFrag mem_frag, ValueType OpVT, X86FoldableSchedWrite Sched, X86MemOperand memOp> { diff --git a/lib/Target/X86/X86InstructionSelector.cpp b/lib/Target/X86/X86InstructionSelector.cpp index 44bbc3f1b3fa9..f6530c4eee2fd 100644 --- a/lib/Target/X86/X86InstructionSelector.cpp +++ b/lib/Target/X86/X86InstructionSelector.cpp @@ -484,11 +484,6 @@ bool X86InstructionSelector::selectLoadStoreOp(MachineInstr &I, const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI); auto &MemOp = **I.memoperands_begin(); - if (MemOp.getOrdering() != AtomicOrdering::NotAtomic) { - DEBUG(dbgs() << "Atomic load/store not supported yet\n"); - return false; - } - unsigned NewOpc = getLoadStoreOp(Ty, RB, Opc, MemOp.getAlignment()); if (NewOpc == Opc) return false; diff --git a/lib/Target/X86/X86LegalizerInfo.cpp b/lib/Target/X86/X86LegalizerInfo.cpp index 4c86373f6f81c..4108a58fa7a50 100644 --- a/lib/Target/X86/X86LegalizerInfo.cpp +++ b/lib/Target/X86/X86LegalizerInfo.cpp @@ -90,6 +90,7 @@ void X86LegalizerInfo::setLegalizerInfo32bit() { const LLT s8 = LLT::scalar(8); const LLT s16 = LLT::scalar(16); const LLT s32 = LLT::scalar(32); + const LLT s64 = LLT::scalar(64); for (auto Ty : {p0, s1, s8, s16, s32}) setAction({G_IMPLICIT_DEF, Ty}, Legal); @@ -140,6 +141,16 @@ void X86LegalizerInfo::setLegalizerInfo32bit() { for (auto Ty : {s8, s16, s32, p0}) setAction({G_ICMP, 1, Ty}, Legal); + + // Merge/Unmerge + for (const auto &Ty : {s16, s32, s64}) { + setAction({G_MERGE_VALUES, Ty}, Legal); + setAction({G_UNMERGE_VALUES, 1, Ty}, Legal); + } + for (const auto &Ty : {s8, s16, s32}) { + setAction({G_MERGE_VALUES, 1, Ty}, Legal); + setAction({G_UNMERGE_VALUES, Ty}, Legal); + } } void X86LegalizerInfo::setLegalizerInfo64bit() { @@ -148,6 +159,7 @@ void X86LegalizerInfo::setLegalizerInfo64bit() { return; const LLT s64 = LLT::scalar(64); + const LLT s128 = LLT::scalar(128); setAction({G_IMPLICIT_DEF, s64}, Legal); @@ -172,6 +184,12 @@ void X86LegalizerInfo::setLegalizerInfo64bit() { // Comparison setAction({G_ICMP, 1, s64}, Legal); + + // Merge/Unmerge + setAction({G_MERGE_VALUES, s128}, Legal); + setAction({G_UNMERGE_VALUES, 1, s128}, Legal); + setAction({G_MERGE_VALUES, 1, s128}, Legal); + setAction({G_UNMERGE_VALUES, s128}, Legal); } void X86LegalizerInfo::setLegalizerInfoSSE1() { @@ -179,6 +197,7 @@ void X86LegalizerInfo::setLegalizerInfoSSE1() { return; const LLT s32 = LLT::scalar(32); + const LLT s64 = LLT::scalar(64); const LLT v4s32 = LLT::vector(4, 32); const LLT v2s64 = LLT::vector(2, 64); @@ -192,6 +211,14 @@ void X86LegalizerInfo::setLegalizerInfoSSE1() { // Constants setAction({TargetOpcode::G_FCONSTANT, s32}, Legal); + + // Merge/Unmerge + for (const auto &Ty : {v4s32, v2s64}) { + setAction({G_MERGE_VALUES, Ty}, Legal); + setAction({G_UNMERGE_VALUES, 1, Ty}, Legal); + } + setAction({G_MERGE_VALUES, 1, s64}, Legal); + setAction({G_UNMERGE_VALUES, s64}, Legal); } void X86LegalizerInfo::setLegalizerInfoSSE2() { @@ -205,6 +232,11 @@ void X86LegalizerInfo::setLegalizerInfoSSE2() { const LLT v4s32 = LLT::vector(4, 32); const LLT v2s64 = LLT::vector(2, 64); + const LLT v32s8 = LLT::vector(32, 8); + const LLT v16s16 = LLT::vector(16, 16); + const LLT v8s32 = LLT::vector(8, 32); + const LLT v4s64 = LLT::vector(4, 64); + for (unsigned BinOp : {G_FADD, G_FSUB, G_FMUL, G_FDIV}) for (auto Ty : {s64, v2s64}) setAction({BinOp, Ty}, Legal); @@ -220,6 +252,17 @@ void X86LegalizerInfo::setLegalizerInfoSSE2() { // Constants setAction({TargetOpcode::G_FCONSTANT, s64}, Legal); + + // Merge/Unmerge + for (const auto &Ty : + {v16s8, v32s8, v8s16, v16s16, v4s32, v8s32, v2s64, v4s64}) { + setAction({G_MERGE_VALUES, Ty}, Legal); + setAction({G_UNMERGE_VALUES, 1, Ty}, Legal); + } + for (const auto &Ty : {v16s8, v8s16, v4s32, v2s64}) { + setAction({G_MERGE_VALUES, 1, Ty}, Legal); + setAction({G_UNMERGE_VALUES, Ty}, Legal); + } } void X86LegalizerInfo::setLegalizerInfoSSE41() { @@ -241,9 +284,13 @@ void X86LegalizerInfo::setLegalizerInfoAVX() { const LLT v2s64 = LLT::vector(2, 64); const LLT v32s8 = LLT::vector(32, 8); + const LLT v64s8 = LLT::vector(64, 8); const LLT v16s16 = LLT::vector(16, 16); + const LLT v32s16 = LLT::vector(32, 16); const LLT v8s32 = LLT::vector(8, 32); + const LLT v16s32 = LLT::vector(16, 32); const LLT v4s64 = LLT::vector(4, 64); + const LLT v8s64 = LLT::vector(8, 64); for (unsigned MemOp : {G_LOAD, G_STORE}) for (auto Ty : {v8s32, v4s64}) @@ -257,6 +304,17 @@ void X86LegalizerInfo::setLegalizerInfoAVX() { setAction({G_INSERT, 1, Ty}, Legal); setAction({G_EXTRACT, Ty}, Legal); } + // Merge/Unmerge + for (const auto &Ty : + {v32s8, v64s8, v16s16, v32s16, v8s32, v16s32, v4s64, v8s64}) { + setAction({G_MERGE_VALUES, Ty}, Legal); + setAction({G_UNMERGE_VALUES, 1, Ty}, Legal); + } + for (const auto &Ty : + {v16s8, v32s8, v8s16, v16s16, v4s32, v8s32, v2s64, v4s64}) { + setAction({G_MERGE_VALUES, 1, Ty}, Legal); + setAction({G_UNMERGE_VALUES, Ty}, Legal); + } } void X86LegalizerInfo::setLegalizerInfoAVX2() { @@ -268,12 +326,27 @@ void X86LegalizerInfo::setLegalizerInfoAVX2() { const LLT v8s32 = LLT::vector(8, 32); const LLT v4s64 = LLT::vector(4, 64); + const LLT v64s8 = LLT::vector(64, 8); + const LLT v32s16 = LLT::vector(32, 16); + const LLT v16s32 = LLT::vector(16, 32); + const LLT v8s64 = LLT::vector(8, 64); + for (unsigned BinOp : {G_ADD, G_SUB}) for (auto Ty : {v32s8, v16s16, v8s32, v4s64}) setAction({BinOp, Ty}, Legal); for (auto Ty : {v16s16, v8s32}) setAction({G_MUL, Ty}, Legal); + + // Merge/Unmerge + for (const auto &Ty : {v64s8, v32s16, v16s32, v8s64}) { + setAction({G_MERGE_VALUES, Ty}, Legal); + setAction({G_UNMERGE_VALUES, 1, Ty}, Legal); + } + for (const auto &Ty : {v32s8, v16s16, v8s32, v4s64}) { + setAction({G_MERGE_VALUES, 1, Ty}, Legal); + setAction({G_UNMERGE_VALUES, Ty}, Legal); + } } void X86LegalizerInfo::setLegalizerInfoAVX512() { diff --git a/lib/Target/X86/X86RegisterInfo.td b/lib/Target/X86/X86RegisterInfo.td index b6eb37d5f0e51..2341e1fb0facf 100644 --- a/lib/Target/X86/X86RegisterInfo.td +++ b/lib/Target/X86/X86RegisterInfo.td @@ -360,7 +360,7 @@ def GR64 : RegisterClass<"X86", [i64], 64, def SEGMENT_REG : RegisterClass<"X86", [i16], 16, (add CS, DS, SS, ES, FS, GS)>; // Debug registers. -def DEBUG_REG : RegisterClass<"X86", [i32], 32, (sequence "DR%u", 0, 7)>; +def DEBUG_REG : RegisterClass<"X86", [i32], 32, (sequence "DR%u", 0, 15)>; // Control registers. def CONTROL_REG : RegisterClass<"X86", [i64], 64, (sequence "CR%u", 0, 15)>; diff --git a/lib/Target/X86/X86Schedule.td b/lib/Target/X86/X86Schedule.td index 16abe81acf07e..c43ae0b17ca02 100644 --- a/lib/Target/X86/X86Schedule.td +++ b/lib/Target/X86/X86Schedule.td @@ -385,8 +385,6 @@ def IIC_SSE_CVT_PD_RR : InstrItinClass; def IIC_SSE_CVT_PD_RM : InstrItinClass; def IIC_SSE_CVT_PS_RR : InstrItinClass; def IIC_SSE_CVT_PS_RM : InstrItinClass; -def IIC_SSE_CVT_PI2PS_RR : InstrItinClass; -def IIC_SSE_CVT_PI2PS_RM : InstrItinClass; def IIC_SSE_CVT_Scalar_RR : InstrItinClass; def IIC_SSE_CVT_Scalar_RM : InstrItinClass; def IIC_SSE_CVT_SS2SI32_RM : InstrItinClass; diff --git a/lib/Transforms/IPO/ThinLTOBitcodeWriter.cpp b/lib/Transforms/IPO/ThinLTOBitcodeWriter.cpp index 7d6d538bc116f..4138606bf0fa6 100644 --- a/lib/Transforms/IPO/ThinLTOBitcodeWriter.cpp +++ b/lib/Transforms/IPO/ThinLTOBitcodeWriter.cpp @@ -40,9 +40,17 @@ void promoteInternals(Module &ExportM, Module &ImportM, StringRef ModuleId, continue; auto Name = ExportGV.getName(); - GlobalValue *ImportGV = ImportM.getNamedValue(Name); - if ((!ImportGV || ImportGV->use_empty()) && !PromoteExtra.count(&ExportGV)) - continue; + GlobalValue *ImportGV = nullptr; + if (!PromoteExtra.count(&ExportGV)) { + ImportGV = ImportM.getNamedValue(Name); + if (!ImportGV) + continue; + ImportGV->removeDeadConstantUsers(); + if (ImportGV->use_empty()) { + ImportGV->eraseFromParent(); + continue; + } + } std::string NewName = (Name + ModuleId).str(); diff --git a/lib/Transforms/Instrumentation/InstrProfiling.cpp b/lib/Transforms/Instrumentation/InstrProfiling.cpp index db8fa89779479..787afc32dfbf2 100644 --- a/lib/Transforms/Instrumentation/InstrProfiling.cpp +++ b/lib/Transforms/Instrumentation/InstrProfiling.cpp @@ -245,6 +245,9 @@ class PGOCounterPromoter { } bool run(int64_t *NumPromoted) { + // Skip 'infinite' loops: + if (ExitBlocks.size() == 0) + return false; unsigned MaxProm = getMaxNumOfPromotionsInLoop(&L); if (MaxProm == 0) return false; diff --git a/lib/Transforms/Instrumentation/MemorySanitizer.cpp b/lib/Transforms/Instrumentation/MemorySanitizer.cpp index 44190a2c312d1..c034a833bed94 100644 --- a/lib/Transforms/Instrumentation/MemorySanitizer.cpp +++ b/lib/Transforms/Instrumentation/MemorySanitizer.cpp @@ -2772,6 +2772,8 @@ struct MemorySanitizerVisitor : public InstVisitor { setOrigin(&I, getCleanOrigin()); return; } + // FIXME: NextInsn is likely in a basic block that has not been visited yet. + // Anything inserted there will be instrumented by MSan later! NextInsn = NormalDest->getFirstInsertionPt(); assert(NextInsn != NormalDest->end() && "Could not find insertion point for retval shadow load"); diff --git a/lib/Transforms/Scalar/LoopPredication.cpp b/lib/Transforms/Scalar/LoopPredication.cpp index 52dea3254e79e..2e4c7b19e476e 100644 --- a/lib/Transforms/Scalar/LoopPredication.cpp +++ b/lib/Transforms/Scalar/LoopPredication.cpp @@ -98,60 +98,79 @@ // Note that we can use anything stronger than M, i.e. any condition which // implies M. // -// For now the transformation is limited to the following case: +// When S = 1 (i.e. forward iterating loop), the transformation is supported +// when: // * The loop has a single latch with the condition of the form: // B(X) = latchStart + X latchLimit, // where is u<, u<=, s<, or s<=. -// * The step of the IV used in the latch condition is 1. // * The guard condition is of the form // G(X) = guardStart + X u< guardLimit // -// For the ult latch comparison case M is: -// forall X . guardStart + X u< guardLimit && latchStart + X -// guardStart + X + 1 u< guardLimit -// -// The only way the antecedent can be true and the consequent can be false is -// if -// X == guardLimit - 1 - guardStart -// (and guardLimit is non-zero, but we won't use this latter fact). -// If X == guardLimit - 1 - guardStart then the second half of the antecedent is -// latchStart + guardLimit - 1 - guardStart u< latchLimit -// and its negation is -// latchStart + guardLimit - 1 - guardStart u>= latchLimit -// -// In other words, if -// latchLimit u<= latchStart + guardLimit - 1 - guardStart -// then: -// (the ranges below are written in ConstantRange notation, where [A, B) is the -// set for (I = A; I != B; I++ /*maywrap*/) yield(I);) -// -// forall X . guardStart + X u< guardLimit && -// latchStart + X u< latchLimit => -// guardStart + X + 1 u< guardLimit -// == forall X . guardStart + X u< guardLimit && -// latchStart + X u< latchStart + guardLimit - 1 - guardStart => -// guardStart + X + 1 u< guardLimit -// == forall X . (guardStart + X) in [0, guardLimit) && -// (latchStart + X) in [0, latchStart + guardLimit - 1 - guardStart) => -// (guardStart + X + 1) in [0, guardLimit) -// == forall X . X in [-guardStart, guardLimit - guardStart) && -// X in [-latchStart, guardLimit - 1 - guardStart) => -// X in [-guardStart - 1, guardLimit - guardStart - 1) -// == true -// -// So the widened condition is: -// guardStart u< guardLimit && -// latchStart + guardLimit - 1 - guardStart u>= latchLimit -// Similarly for ule condition the widened condition is: -// guardStart u< guardLimit && -// latchStart + guardLimit - 1 - guardStart u> latchLimit -// For slt condition the widened condition is: -// guardStart u< guardLimit && -// latchStart + guardLimit - 1 - guardStart s>= latchLimit -// For sle condition the widened condition is: -// guardStart u< guardLimit && -// latchStart + guardLimit - 1 - guardStart s> latchLimit +// For the ult latch comparison case M is: +// forall X . guardStart + X u< guardLimit && latchStart + X +// guardStart + X + 1 u< guardLimit // +// The only way the antecedent can be true and the consequent can be false is +// if +// X == guardLimit - 1 - guardStart +// (and guardLimit is non-zero, but we won't use this latter fact). +// If X == guardLimit - 1 - guardStart then the second half of the antecedent is +// latchStart + guardLimit - 1 - guardStart u< latchLimit +// and its negation is +// latchStart + guardLimit - 1 - guardStart u>= latchLimit +// +// In other words, if +// latchLimit u<= latchStart + guardLimit - 1 - guardStart +// then: +// (the ranges below are written in ConstantRange notation, where [A, B) is the +// set for (I = A; I != B; I++ /*maywrap*/) yield(I);) +// +// forall X . guardStart + X u< guardLimit && +// latchStart + X u< latchLimit => +// guardStart + X + 1 u< guardLimit +// == forall X . guardStart + X u< guardLimit && +// latchStart + X u< latchStart + guardLimit - 1 - guardStart => +// guardStart + X + 1 u< guardLimit +// == forall X . (guardStart + X) in [0, guardLimit) && +// (latchStart + X) in [0, latchStart + guardLimit - 1 - guardStart) => +// (guardStart + X + 1) in [0, guardLimit) +// == forall X . X in [-guardStart, guardLimit - guardStart) && +// X in [-latchStart, guardLimit - 1 - guardStart) => +// X in [-guardStart - 1, guardLimit - guardStart - 1) +// == true +// +// So the widened condition is: +// guardStart u< guardLimit && +// latchStart + guardLimit - 1 - guardStart u>= latchLimit +// Similarly for ule condition the widened condition is: +// guardStart u< guardLimit && +// latchStart + guardLimit - 1 - guardStart u> latchLimit +// For slt condition the widened condition is: +// guardStart u< guardLimit && +// latchStart + guardLimit - 1 - guardStart s>= latchLimit +// For sle condition the widened condition is: +// guardStart u< guardLimit && +// latchStart + guardLimit - 1 - guardStart s> latchLimit +// +// When S = -1 (i.e. reverse iterating loop), the transformation is supported +// when: +// * The loop has a single latch with the condition of the form: +// B(X) = X latchLimit, where is u> or s>. +// * The guard condition is of the form +// G(X) = X - 1 u< guardLimit +// +// For the ugt latch comparison case M is: +// forall X. X-1 u< guardLimit and X u> latchLimit => X-2 u< guardLimit +// +// The only way the antecedent can be true and the consequent can be false is if +// X == 1. +// If X == 1 then the second half of the antecedent is +// 1 u> latchLimit, and its negation is latchLimit u>= 1. +// +// So the widened condition is: +// guardStart u< guardLimit && latchLimit u>= 1. +// Similarly for sgt condition the widened condition is: +// guardStart u< guardLimit && latchLimit s>= 1. //===----------------------------------------------------------------------===// #include "llvm/Transforms/Scalar/LoopPredication.h" @@ -177,6 +196,8 @@ using namespace llvm; static cl::opt EnableIVTruncation("loop-predication-enable-iv-truncation", cl::Hidden, cl::init(true)); +static cl::opt EnableCountDownLoop("loop-predication-enable-count-down-loop", + cl::Hidden, cl::init(true)); namespace { class LoopPredication { /// Represents an induction variable check: @@ -223,7 +244,10 @@ class LoopPredication { LoopICmp RangeCheck, SCEVExpander &Expander, IRBuilder<> &Builder); - + Optional widenICmpRangeCheckDecrementingLoop(LoopICmp LatchCheck, + LoopICmp RangeCheck, + SCEVExpander &Expander, + IRBuilder<> &Builder); bool widenGuardConditions(IntrinsicInst *II, SCEVExpander &Expander); // When the IV type is wider than the range operand type, we can still do loop @@ -360,7 +384,7 @@ LoopPredication::generateLoopLatchCheck(Type *RangeCheckType) { } bool LoopPredication::isSupportedStep(const SCEV* Step) { - return Step->isOne(); + return Step->isOne() || (Step->isAllOnesValue() && EnableCountDownLoop); } bool LoopPredication::CanExpand(const SCEV* S) { @@ -420,6 +444,44 @@ Optional LoopPredication::widenICmpRangeCheckIncrementingLoop( GuardStart, GuardLimit, InsertAt); return Builder.CreateAnd(FirstIterationCheck, LimitCheck); } + +Optional LoopPredication::widenICmpRangeCheckDecrementingLoop( + LoopPredication::LoopICmp LatchCheck, LoopPredication::LoopICmp RangeCheck, + SCEVExpander &Expander, IRBuilder<> &Builder) { + auto *Ty = RangeCheck.IV->getType(); + const SCEV *GuardStart = RangeCheck.IV->getStart(); + const SCEV *GuardLimit = RangeCheck.Limit; + const SCEV *LatchLimit = LatchCheck.Limit; + if (!CanExpand(GuardStart) || !CanExpand(GuardLimit) || + !CanExpand(LatchLimit)) { + DEBUG(dbgs() << "Can't expand limit check!\n"); + return None; + } + // The decrement of the latch check IV should be the same as the + // rangeCheckIV. + auto *PostDecLatchCheckIV = LatchCheck.IV->getPostIncExpr(*SE); + if (RangeCheck.IV != PostDecLatchCheckIV) { + DEBUG(dbgs() << "Not the same. PostDecLatchCheckIV: " + << *PostDecLatchCheckIV + << " and RangeCheckIV: " << *RangeCheck.IV << "\n"); + return None; + } + + // Generate the widened condition for CountDownLoop: + // guardStart u< guardLimit && + // latchLimit 1. + // See the header comment for reasoning of the checks. + Instruction *InsertAt = Preheader->getTerminator(); + auto LimitCheckPred = ICmpInst::isSigned(LatchCheck.Pred) + ? ICmpInst::ICMP_SGE + : ICmpInst::ICMP_UGE; + auto *FirstIterationCheck = expandCheck(Expander, Builder, ICmpInst::ICMP_ULT, + GuardStart, GuardLimit, InsertAt); + auto *LimitCheck = expandCheck(Expander, Builder, LimitCheckPred, LatchLimit, + SE->getOne(Ty), InsertAt); + return Builder.CreateAnd(FirstIterationCheck, LimitCheck); +} + /// If ICI can be widened to a loop invariant condition emits the loop /// invariant condition in the loop preheader and return it, otherwise /// returns None. @@ -467,13 +529,24 @@ Optional LoopPredication::widenICmpRangeCheck(ICmpInst *ICI, } LoopICmp CurrLatchCheck = *CurrLatchCheckOpt; - // At this point the range check step and latch step should have the same - // value and type. - assert(Step == CurrLatchCheck.IV->getStepRecurrence(*SE) && - "Range and latch should have same step recurrence!"); + // At this point, the range and latch step should have the same type, but need + // not have the same value (we support both 1 and -1 steps). + assert(Step->getType() == + CurrLatchCheck.IV->getStepRecurrence(*SE)->getType() && + "Range and latch steps should be of same type!"); + if (Step != CurrLatchCheck.IV->getStepRecurrence(*SE)) { + DEBUG(dbgs() << "Range and latch have different step values!\n"); + return None; + } - return widenICmpRangeCheckIncrementingLoop(CurrLatchCheck, *RangeCheck, - Expander, Builder); + if (Step->isOne()) + return widenICmpRangeCheckIncrementingLoop(CurrLatchCheck, *RangeCheck, + Expander, Builder); + else { + assert(Step->isAllOnesValue() && "Step should be -1!"); + return widenICmpRangeCheckDecrementingLoop(CurrLatchCheck, *RangeCheck, + Expander, Builder); + } } bool LoopPredication::widenGuardConditions(IntrinsicInst *Guard, @@ -580,9 +653,13 @@ Optional LoopPredication::parseLoopLatchICmp() { } auto IsUnsupportedPredicate = [](const SCEV *Step, ICmpInst::Predicate Pred) { - assert(Step->isOne() && "expected Step to be one!"); - return Pred != ICmpInst::ICMP_ULT && Pred != ICmpInst::ICMP_SLT && - Pred != ICmpInst::ICMP_ULE && Pred != ICmpInst::ICMP_SLE; + if (Step->isOne()) { + return Pred != ICmpInst::ICMP_ULT && Pred != ICmpInst::ICMP_SLT && + Pred != ICmpInst::ICMP_ULE && Pred != ICmpInst::ICMP_SLE; + } else { + assert(Step->isAllOnesValue() && "Step should be -1!"); + return Pred != ICmpInst::ICMP_UGT && Pred != ICmpInst::ICMP_SGT; + } }; if (IsUnsupportedPredicate(Step, Result->Pred)) { diff --git a/lib/Transforms/Scalar/MemCpyOptimizer.cpp b/lib/Transforms/Scalar/MemCpyOptimizer.cpp index a4b4330bfedb1..86d7b5e8ddd5b 100644 --- a/lib/Transforms/Scalar/MemCpyOptimizer.cpp +++ b/lib/Transforms/Scalar/MemCpyOptimizer.cpp @@ -1031,9 +1031,22 @@ bool MemCpyOptPass::processMemCpyMemCpyDependence(MemCpyInst *M, // // NOTE: This is conservative, it will stop on any read from the source loc, // not just the defining memcpy. - MemDepResult SourceDep = - MD->getPointerDependencyFrom(MemoryLocation::getForSource(MDep), false, - M->getIterator(), M->getParent()); + MemoryLocation SourceLoc = MemoryLocation::getForSource(MDep); + MemDepResult SourceDep = MD->getPointerDependencyFrom(SourceLoc, false, + M->getIterator(), M->getParent()); + + if (SourceDep.isNonLocal()) { + SmallVector NonLocalDepResults; + MD->getNonLocalPointerDependencyFrom(M, SourceLoc, /*isLoad=*/false, + NonLocalDepResults); + if (NonLocalDepResults.size() == 1) { + SourceDep = NonLocalDepResults[0].getResult(); + assert((!SourceDep.getInst() || + LookupDomTree().dominates(SourceDep.getInst(), M)) && + "when memdep returns exactly one result, it should dominate"); + } + } + if (!SourceDep.isClobber() || SourceDep.getInst() != MDep) return false; @@ -1235,6 +1248,18 @@ bool MemCpyOptPass::processMemCpy(MemCpyInst *M) { MemDepResult SrcDepInfo = MD->getPointerDependencyFrom( SrcLoc, true, M->getIterator(), M->getParent()); + if (SrcDepInfo.isNonLocal()) { + SmallVector NonLocalDepResults; + MD->getNonLocalPointerDependencyFrom(M, SrcLoc, /*isLoad=*/true, + NonLocalDepResults); + if (NonLocalDepResults.size() == 1) { + SrcDepInfo = NonLocalDepResults[0].getResult(); + assert((!SrcDepInfo.getInst() || + LookupDomTree().dominates(SrcDepInfo.getInst(), M)) && + "when memdep returns exactly one result, it should dominate"); + } + } + if (SrcDepInfo.isClobber()) { if (MemCpyInst *MDep = dyn_cast(SrcDepInfo.getInst())) return processMemCpyMemCpyDependence(M, MDep); diff --git a/lib/Transforms/Scalar/SROA.cpp b/lib/Transforms/Scalar/SROA.cpp index bd064978b645d..2e5023398f280 100644 --- a/lib/Transforms/Scalar/SROA.cpp +++ b/lib/Transforms/Scalar/SROA.cpp @@ -30,6 +30,7 @@ #include "llvm/ADT/PointerIntPair.h" #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/SetVector.h" +#include "llvm/ADT/SmallBitVector.h" #include "llvm/ADT/SmallPtrSet.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/Statistic.h" @@ -4047,27 +4048,58 @@ bool SROA::splitAlloca(AllocaInst &AI, AllocaSlices &AS) { // First try to pre-split loads and stores. Changed |= presplitLoadsAndStores(AI, AS); - // Now that we have identified any pre-splitting opportunities, mark any - // splittable (non-whole-alloca) loads and stores as unsplittable. If we fail - // to split these during pre-splitting, we want to force them to be - // rewritten into a partition. + // Now that we have identified any pre-splitting opportunities, + // mark loads and stores unsplittable except for the following case. + // We leave a slice splittable if all other slices are disjoint or fully + // included in the slice, such as whole-alloca loads and stores. + // If we fail to split these during pre-splitting, we want to force them + // to be rewritten into a partition. bool IsSorted = true; - for (Slice &S : AS) { - if (!S.isSplittable()) - continue; - // FIXME: We currently leave whole-alloca splittable loads and stores. This - // used to be the only splittable loads and stores and we need to be - // confident that the above handling of splittable loads and stores is - // completely sufficient before we forcibly disable the remaining handling. - if (S.beginOffset() == 0 && - S.endOffset() >= DL.getTypeAllocSize(AI.getAllocatedType())) - continue; - if (isa(S.getUse()->getUser()) || - isa(S.getUse()->getUser())) { - S.makeUnsplittable(); - IsSorted = false; + + uint64_t AllocaSize = DL.getTypeAllocSize(AI.getAllocatedType()); + const uint64_t MaxBitVectorSize = 1024; + if (AllocaSize <= MaxBitVectorSize) { + // If a byte boundary is included in any load or store, a slice starting or + // ending at the boundary is not splittable. + SmallBitVector SplittableOffset(AllocaSize + 1, true); + for (Slice &S : AS) + for (unsigned O = S.beginOffset() + 1; + O < S.endOffset() && O < AllocaSize; O++) + SplittableOffset.reset(O); + + for (Slice &S : AS) { + if (!S.isSplittable()) + continue; + + if ((S.beginOffset() > AllocaSize || SplittableOffset[S.beginOffset()]) && + (S.endOffset() > AllocaSize || SplittableOffset[S.endOffset()])) + continue; + + if (isa(S.getUse()->getUser()) || + isa(S.getUse()->getUser())) { + S.makeUnsplittable(); + IsSorted = false; + } } } + else { + // We only allow whole-alloca splittable loads and stores + // for a large alloca to avoid creating too large BitVector. + for (Slice &S : AS) { + if (!S.isSplittable()) + continue; + + if (S.beginOffset() == 0 && S.endOffset() >= AllocaSize) + continue; + + if (isa(S.getUse()->getUser()) || + isa(S.getUse()->getUser())) { + S.makeUnsplittable(); + IsSorted = false; + } + } + } + if (!IsSorted) std::sort(AS.begin(), AS.end()); diff --git a/lib/Transforms/Utils/BreakCriticalEdges.cpp b/lib/Transforms/Utils/BreakCriticalEdges.cpp index 417a771cf952d..ec4f1b944bff4 100644 --- a/lib/Transforms/Utils/BreakCriticalEdges.cpp +++ b/lib/Transforms/Utils/BreakCriticalEdges.cpp @@ -16,6 +16,7 @@ //===----------------------------------------------------------------------===// #include "llvm/Transforms/Utils/BreakCriticalEdges.h" +#include "llvm/ADT/SetVector.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/Statistic.h" #include "llvm/Analysis/AliasAnalysis.h" @@ -28,6 +29,8 @@ #include "llvm/Support/ErrorHandling.h" #include "llvm/Transforms/Scalar.h" #include "llvm/Transforms/Utils/BasicBlockUtils.h" +#include "llvm/Transforms/Utils/Cloning.h" +#include "llvm/Transforms/Utils/ValueMapper.h" using namespace llvm; #define DEBUG_TYPE "break-crit-edges" @@ -290,3 +293,139 @@ llvm::SplitCriticalEdge(TerminatorInst *TI, unsigned SuccNum, return NewBB; } + +// Return the unique indirectbr predecessor of a block. This may return null +// even if such a predecessor exists, if it's not useful for splitting. +// If a predecessor is found, OtherPreds will contain all other (non-indirectbr) +// predecessors of BB. +static BasicBlock * +findIBRPredecessor(BasicBlock *BB, SmallVectorImpl &OtherPreds) { + // If the block doesn't have any PHIs, we don't care about it, since there's + // no point in splitting it. + PHINode *PN = dyn_cast(BB->begin()); + if (!PN) + return nullptr; + + // Verify we have exactly one IBR predecessor. + // Conservatively bail out if one of the other predecessors is not a "regular" + // terminator (that is, not a switch or a br). + BasicBlock *IBB = nullptr; + for (unsigned Pred = 0, E = PN->getNumIncomingValues(); Pred != E; ++Pred) { + BasicBlock *PredBB = PN->getIncomingBlock(Pred); + TerminatorInst *PredTerm = PredBB->getTerminator(); + switch (PredTerm->getOpcode()) { + case Instruction::IndirectBr: + if (IBB) + return nullptr; + IBB = PredBB; + break; + case Instruction::Br: + case Instruction::Switch: + OtherPreds.push_back(PredBB); + continue; + default: + return nullptr; + } + } + + return IBB; +} + +bool llvm::SplitIndirectBrCriticalEdges(Function &F) { + // Check whether the function has any indirectbrs, and collect which blocks + // they may jump to. Since most functions don't have indirect branches, + // this lowers the common case's overhead to O(Blocks) instead of O(Edges). + SmallSetVector Targets; + for (auto &BB : F) { + auto *IBI = dyn_cast(BB.getTerminator()); + if (!IBI) + continue; + + for (unsigned Succ = 0, E = IBI->getNumSuccessors(); Succ != E; ++Succ) + Targets.insert(IBI->getSuccessor(Succ)); + } + + if (Targets.empty()) + return false; + + bool Changed = false; + for (BasicBlock *Target : Targets) { + SmallVector OtherPreds; + BasicBlock *IBRPred = findIBRPredecessor(Target, OtherPreds); + // If we did not found an indirectbr, or the indirectbr is the only + // incoming edge, this isn't the kind of edge we're looking for. + if (!IBRPred || OtherPreds.empty()) + continue; + + // Don't even think about ehpads/landingpads. + Instruction *FirstNonPHI = Target->getFirstNonPHI(); + if (FirstNonPHI->isEHPad() || Target->isLandingPad()) + continue; + + BasicBlock *BodyBlock = Target->splitBasicBlock(FirstNonPHI, ".split"); + // It's possible Target was its own successor through an indirectbr. + // In this case, the indirectbr now comes from BodyBlock. + if (IBRPred == Target) + IBRPred = BodyBlock; + + // At this point Target only has PHIs, and BodyBlock has the rest of the + // block's body. Create a copy of Target that will be used by the "direct" + // preds. + ValueToValueMapTy VMap; + BasicBlock *DirectSucc = CloneBasicBlock(Target, VMap, ".clone", &F); + + for (BasicBlock *Pred : OtherPreds) { + // If the target is a loop to itself, then the terminator of the split + // block needs to be updated. + if (Pred == Target) + BodyBlock->getTerminator()->replaceUsesOfWith(Target, DirectSucc); + else + Pred->getTerminator()->replaceUsesOfWith(Target, DirectSucc); + } + + // Ok, now fix up the PHIs. We know the two blocks only have PHIs, and that + // they are clones, so the number of PHIs are the same. + // (a) Remove the edge coming from IBRPred from the "Direct" PHI + // (b) Leave that as the only edge in the "Indirect" PHI. + // (c) Merge the two in the body block. + BasicBlock::iterator Indirect = Target->begin(), + End = Target->getFirstNonPHI()->getIterator(); + BasicBlock::iterator Direct = DirectSucc->begin(); + BasicBlock::iterator MergeInsert = BodyBlock->getFirstInsertionPt(); + + assert(&*End == Target->getTerminator() && + "Block was expected to only contain PHIs"); + + while (Indirect != End) { + PHINode *DirPHI = cast(Direct); + PHINode *IndPHI = cast(Indirect); + + // Now, clean up - the direct block shouldn't get the indirect value, + // and vice versa. + DirPHI->removeIncomingValue(IBRPred); + Direct++; + + // Advance the pointer here, to avoid invalidation issues when the old + // PHI is erased. + Indirect++; + + PHINode *NewIndPHI = PHINode::Create(IndPHI->getType(), 1, "ind", IndPHI); + NewIndPHI->addIncoming(IndPHI->getIncomingValueForBlock(IBRPred), + IBRPred); + + // Create a PHI in the body block, to merge the direct and indirect + // predecessors. + PHINode *MergePHI = + PHINode::Create(IndPHI->getType(), 2, "merge", &*MergeInsert); + MergePHI->addIncoming(NewIndPHI, Target); + MergePHI->addIncoming(DirPHI, DirectSucc); + + IndPHI->replaceAllUsesWith(MergePHI); + IndPHI->eraseFromParent(); + } + + Changed = true; + } + + return Changed; +} diff --git a/lib/Transforms/Utils/BypassSlowDivision.cpp b/lib/Transforms/Utils/BypassSlowDivision.cpp index e9c14c93a9ad7..f711b192f6044 100644 --- a/lib/Transforms/Utils/BypassSlowDivision.cpp +++ b/lib/Transforms/Utils/BypassSlowDivision.cpp @@ -352,11 +352,6 @@ Optional FastDivInsertionTask::insertFastDivAndRem() { Value *Dividend = SlowDivOrRem->getOperand(0); Value *Divisor = SlowDivOrRem->getOperand(1); - if (isa(Divisor)) { - // Keep division by a constant for DAGCombiner. - return None; - } - VisitedSetTy SetL; ValueRange DividendRange = getValueRange(Dividend, SetL); if (DividendRange == VALRNG_LIKELY_LONG) @@ -372,7 +367,9 @@ Optional FastDivInsertionTask::insertFastDivAndRem() { if (DividendShort && DivisorShort) { // If both operands are known to be short then just replace the long - // division with a short one in-place. + // division with a short one in-place. Since we're not introducing control + // flow in this case, narrowing the division is always a win, even if the + // divisor is a constant (and will later get replaced by a multiplication). IRBuilder<> Builder(SlowDivOrRem); Value *TruncDividend = Builder.CreateTrunc(Dividend, BypassType); @@ -382,7 +379,16 @@ Optional FastDivInsertionTask::insertFastDivAndRem() { Value *ExtDiv = Builder.CreateZExt(TruncDiv, getSlowType()); Value *ExtRem = Builder.CreateZExt(TruncRem, getSlowType()); return QuotRemPair(ExtDiv, ExtRem); - } else if (DividendShort && !isSignedOp()) { + } + + if (isa(Divisor)) { + // If the divisor is not a constant, DAGCombiner will convert it to a + // multiplication by a magic constant. It isn't clear if it is worth + // introducing control flow to get a narrower multiply. + return None; + } + + if (DividendShort && !isSignedOp()) { // If the division is unsigned and Dividend is known to be short, then // either // 1) Divisor is less or equal to Dividend, and the result can be computed diff --git a/lib/Transforms/Utils/LCSSA.cpp b/lib/Transforms/Utils/LCSSA.cpp index 089f2b5f3b181..ae0e2bb6c2803 100644 --- a/lib/Transforms/Utils/LCSSA.cpp +++ b/lib/Transforms/Utils/LCSSA.cpp @@ -56,9 +56,10 @@ static bool VerifyLoopLCSSA = true; #else static bool VerifyLoopLCSSA = false; #endif -static cl::opt -VerifyLoopLCSSAFlag("verify-loop-lcssa", cl::location(VerifyLoopLCSSA), - cl::desc("Verify loop lcssa form (time consuming)")); +static cl::opt + VerifyLoopLCSSAFlag("verify-loop-lcssa", cl::location(VerifyLoopLCSSA), + cl::Hidden, + cl::desc("Verify loop lcssa form (time consuming)")); /// Return true if the specified block is in the list. static bool isExitBlock(BasicBlock *BB, diff --git a/lib/Transforms/Utils/SimplifyIndVar.cpp b/lib/Transforms/Utils/SimplifyIndVar.cpp index fce7f8b81bac7..96b51396c9b63 100644 --- a/lib/Transforms/Utils/SimplifyIndVar.cpp +++ b/lib/Transforms/Utils/SimplifyIndVar.cpp @@ -200,13 +200,23 @@ bool SimplifyIndvar::makeIVComparisonInvariant(ICmpInst *ICmp, // TODO: Support multiple entry loops? (We currently bail out of these in // the IndVarSimplify pass) if (auto *BB = L->getLoopPredecessor()) { - Value *Incoming = PN->getIncomingValueForBlock(BB); - const SCEV *IncomingS = SE->getSCEV(Incoming); - CheapExpansions[IncomingS] = Incoming; + const int Idx = PN->getBasicBlockIndex(BB); + if (Idx >= 0) { + Value *Incoming = PN->getIncomingValue(Idx); + const SCEV *IncomingS = SE->getSCEV(Incoming); + CheapExpansions[IncomingS] = Incoming; + } } Value *NewLHS = CheapExpansions[InvariantLHS]; Value *NewRHS = CheapExpansions[InvariantRHS]; + if (!NewLHS) + if (auto *ConstLHS = dyn_cast(InvariantLHS)) + NewLHS = ConstLHS->getValue(); + if (!NewRHS) + if (auto *ConstRHS = dyn_cast(InvariantRHS)) + NewRHS = ConstRHS->getValue(); + if (!NewLHS || !NewRHS) // We could not find an existing value to replace either LHS or RHS. // Generating new instructions has subtler tradeoffs, so avoid doing that diff --git a/lib/Transforms/Utils/SymbolRewriter.cpp b/lib/Transforms/Utils/SymbolRewriter.cpp index 9da862db6a78a..3640541e63cc0 100644 --- a/lib/Transforms/Utils/SymbolRewriter.cpp +++ b/lib/Transforms/Utils/SymbolRewriter.cpp @@ -90,7 +90,8 @@ using namespace SymbolRewriter; static cl::list RewriteMapFiles("rewrite-map-file", cl::desc("Symbol Rewrite Map"), - cl::value_desc("filename")); + cl::value_desc("filename"), + cl::Hidden); static void rewriteComdat(Module &M, GlobalObject *GO, const std::string &Source, diff --git a/test/Assembler/getelementptr_vec_ce.ll b/test/Assembler/getelementptr_vec_ce.ll index 4cf2964a57f7f..67029698bfc52 100644 --- a/test/Assembler/getelementptr_vec_ce.ll +++ b/test/Assembler/getelementptr_vec_ce.ll @@ -3,7 +3,7 @@ @G = global [4 x i32] zeroinitializer ; CHECK-LABEL: @foo -; CHECK: ret <4 x i32*> getelementptr ([4 x i32], [4 x i32]* @G, <4 x i32> zeroinitializer, <4 x i32> ) +; CHECK: ret <4 x i32*> getelementptr inbounds ([4 x i32], [4 x i32]* @G, <4 x i32> zeroinitializer, <4 x i32> ) define <4 x i32*> @foo() { ret <4 x i32*> getelementptr ([4 x i32], [4 x i32]* @G, i32 0, <4 x i32> ) } diff --git a/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll b/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll index dca9d6227308e..afa003c4dd974 100644 --- a/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll +++ b/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll @@ -40,10 +40,10 @@ define [1 x double] @constant() { ret [1 x double] [double 1.0] } - ; The key problem here is that we may fail to create an MBB referenced by a - ; PHI. If so, we cannot complete the G_PHI and mustn't try or bad things - ; happen. -; FALLBACK-WITH-REPORT-ERR: remark: :0:0: cannot select: G_STORE %vreg6, %vreg2; mem:ST4[%addr] GPR:%vreg6,%vreg2 (in function: pending_phis) +; The key problem here is that we may fail to create an MBB referenced by a +; PHI. If so, we cannot complete the G_PHI and mustn't try or bad things +; happen. +; FALLBACK-WITH-REPORT-ERR: remark: :0:0: unable to translate constant: [1 x double] (in function: pending_phis) ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for pending_phis ; FALLBACK-WITH-REPORT-OUT-LABEL: pending_phis: define i32 @pending_phis(i1 %tst, i32 %val, i32* %addr) { @@ -54,7 +54,7 @@ end: ret i32 %res true: - store atomic i32 42, i32* %addr seq_cst, align 4 + %t = extractvalue [1 x double] [double 1.0], 0 br label %end false: @@ -63,7 +63,7 @@ false: } ; General legalizer inability to handle types whose size wasn't a power of 2. -; FALLBACK-WITH-REPORT-ERR: remark: :0:0: unable to legalize instruction: G_STORE %vreg1, %vreg0; mem:ST6[%addr](align=8) (in function: odd_type) +; FALLBACK-WITH-REPORT-ERR: remark: :0:0: unable to legalize instruction: G_STORE %1, %0; mem:ST6[%addr](align=8) (in function: odd_type) ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for odd_type ; FALLBACK-WITH-REPORT-OUT-LABEL: odd_type: define void @odd_type(i42* %addr) { @@ -72,7 +72,7 @@ define void @odd_type(i42* %addr) { ret void } -; FALLBACK-WITH-REPORT-ERR: remark: :0:0: unable to legalize instruction: G_STORE %vreg1, %vreg0; mem:ST28[%addr](align=32) (in function: odd_vector) +; FALLBACK-WITH-REPORT-ERR: remark: :0:0: unable to legalize instruction: G_STORE %1, %0; mem:ST28[%addr](align=32) (in function: odd_vector) ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for odd_vector ; FALLBACK-WITH-REPORT-OUT-LABEL: odd_vector: define void @odd_vector(<7 x i32>* %addr) { @@ -90,16 +90,6 @@ define i128 @sequence_sizes([8 x i8] %in) { ret i128 undef } -; Just to make sure we don't accidentally emit a normal load/store. -; FALLBACK-WITH-REPORT-ERR: remark: :0:0: cannot select: %vreg2(s64) = G_LOAD %vreg0; mem:LD8[%addr] GPR:%vreg2,%vreg0 (in function: atomic_ops) -; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for atomic_ops -; FALLBACK-WITH-REPORT-LABEL: atomic_ops: -define i64 @atomic_ops(i64* %addr) { - store atomic i64 0, i64* %addr unordered, align 8 - %res = load atomic i64, i64* %addr seq_cst, align 8 - ret i64 %res -} - ; Make sure we don't mess up metadata arguments. declare void @llvm.write_register.i64(metadata, i64) @@ -132,14 +122,14 @@ continue: } ; Check that we fallback on invoke translation failures. -; FALLBACK-WITH-REPORT-ERR: remark: :0:0: unable to legalize instruction: %vreg0(s128) = G_FCONSTANT quad 2 +; FALLBACK-WITH-REPORT-ERR: remark: :0:0: unable to legalize instruction: %0(s128) = G_FCONSTANT quad 2 ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for test_quad_dump ; FALLBACK-WITH-REPORT-OUT-LABEL: test_quad_dump: define fp128 @test_quad_dump() { ret fp128 0xL00000000000000004000000000000000 } -; FALLBACK-WITH-REPORT-ERR: remark: :0:0: unable to legalize instruction: %vreg0(p0) = G_EXTRACT_VECTOR_ELT %vreg1, %vreg2; (in function: vector_of_pointers_extractelement) +; FALLBACK-WITH-REPORT-ERR: remark: :0:0: unable to legalize instruction: %0(p0) = G_EXTRACT_VECTOR_ELT %1, %2; (in function: vector_of_pointers_extractelement) ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for vector_of_pointers_extractelement ; FALLBACK-WITH-REPORT-OUT-LABEL: vector_of_pointers_extractelement: @var = global <2 x i16*> zeroinitializer @@ -156,7 +146,7 @@ end: br label %block } -; FALLBACK-WITH-REPORT-ERR: remark: :0:0: unable to legalize instruction: G_STORE %vreg0, %vreg4; mem:ST16[undef] (in function: vector_of_pointers_insertelement) +; FALLBACK-WITH-REPORT-ERR: remark: :0:0: unable to legalize instruction: G_STORE %0, %4; mem:ST16[undef] (in function: vector_of_pointers_insertelement) ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for vector_of_pointers_insertelement ; FALLBACK-WITH-REPORT-OUT-LABEL: vector_of_pointers_insertelement: define void @vector_of_pointers_insertelement() { @@ -172,7 +162,7 @@ end: br label %block } -; FALLBACK-WITH-REPORT-ERR: remark: :0:0: unable to legalize instruction: G_STORE %vreg1, %vreg3; mem:ST12[undef](align=4) (in function: nonpow2_insertvalue_narrowing) +; FALLBACK-WITH-REPORT-ERR: remark: :0:0: unable to legalize instruction: G_STORE %1, %3; mem:ST12[undef](align=4) (in function: nonpow2_insertvalue_narrowing) ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for nonpow2_insertvalue_narrowing ; FALLBACK-WITH-REPORT-OUT-LABEL: nonpow2_insertvalue_narrowing: %struct96 = type { float, float, float } @@ -182,7 +172,7 @@ define void @nonpow2_insertvalue_narrowing(float %a) { ret void } -; FALLBACK-WITH-REPORT-ERR remark: :0:0: unable to legalize instruction: G_STORE %vreg3, %vreg4; mem:ST12[undef](align=16) (in function: nonpow2_add_narrowing) +; FALLBACK-WITH-REPORT-ERR remark: :0:0: unable to legalize instruction: G_STORE %3, %4; mem:ST12[undef](align=16) (in function: nonpow2_add_narrowing) ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for nonpow2_add_narrowing ; FALLBACK-WITH-REPORT-OUT-LABEL: nonpow2_add_narrowing: define void @nonpow2_add_narrowing() { @@ -193,7 +183,7 @@ define void @nonpow2_add_narrowing() { ret void } -; FALLBACK-WITH-REPORT-ERR remark: :0:0: unable to legalize instruction: G_STORE %vreg3, %vreg4; mem:ST12[undef](align=16) (in function: nonpow2_add_narrowing) +; FALLBACK-WITH-REPORT-ERR remark: :0:0: unable to legalize instruction: G_STORE %3, %4; mem:ST12[undef](align=16) (in function: nonpow2_add_narrowing) ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for nonpow2_or_narrowing ; FALLBACK-WITH-REPORT-OUT-LABEL: nonpow2_or_narrowing: define void @nonpow2_or_narrowing() { @@ -204,7 +194,7 @@ define void @nonpow2_or_narrowing() { ret void } -; FALLBACK-WITH-REPORT-ERR remark: :0:0: unable to legalize instruction: G_STORE %vreg0, %vreg1; mem:ST12[undef](align=16) (in function: nonpow2_load_narrowing) +; FALLBACK-WITH-REPORT-ERR remark: :0:0: unable to legalize instruction: G_STORE %0, %1; mem:ST12[undef](align=16) (in function: nonpow2_load_narrowing) ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for nonpow2_load_narrowing ; FALLBACK-WITH-REPORT-OUT-LABEL: nonpow2_load_narrowing: define void @nonpow2_load_narrowing() { @@ -213,7 +203,7 @@ define void @nonpow2_load_narrowing() { ret void } -; FALLBACK-WITH-REPORT-ERR: remark: :0:0: unable to legalize instruction: G_STORE %vreg3, %vreg0; mem:ST12[%c](align=16) (in function: nonpow2_store_narrowing +; FALLBACK-WITH-REPORT-ERR: remark: :0:0: unable to legalize instruction: G_STORE %3, %0; mem:ST12[%c](align=16) (in function: nonpow2_store_narrowing ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for nonpow2_store_narrowing ; FALLBACK-WITH-REPORT-OUT-LABEL: nonpow2_store_narrowing: define void @nonpow2_store_narrowing(i96* %c) { @@ -223,7 +213,7 @@ define void @nonpow2_store_narrowing(i96* %c) { ret void } -; FALLBACK-WITH-REPORT-ERR: remark: :0:0: unable to legalize instruction: G_STORE %vreg0, %vreg1; mem:ST12[undef](align=16) (in function: nonpow2_constant_narrowing) +; FALLBACK-WITH-REPORT-ERR: remark: :0:0: unable to legalize instruction: G_STORE %0, %1; mem:ST12[undef](align=16) (in function: nonpow2_constant_narrowing) ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for nonpow2_constant_narrowing ; FALLBACK-WITH-REPORT-OUT-LABEL: nonpow2_constant_narrowing: define void @nonpow2_constant_narrowing() { @@ -233,8 +223,8 @@ define void @nonpow2_constant_narrowing() { ; Currently can't handle vector lengths that aren't an exact multiple of ; natively supported vector lengths. Test that the fall-back works for those. -; FALLBACK-WITH-REPORT-ERR-G_IMPLICIT_DEF-LEGALIZABLE: (FIXME: this is what is expected once we can legalize non-pow-of-2 G_IMPLICIT_DEF) remark: :0:0: unable to legalize instruction: %vreg1(<7 x s64>) = G_ADD %vreg0, %vreg0; (in function: nonpow2_vector_add_fewerelements -; FALLBACK-WITH-REPORT-ERR: remark: :0:0: unable to legalize instruction: %vreg2(s64) = G_EXTRACT_VECTOR_ELT %vreg1, %vreg3; (in function: nonpow2_vector_add_fewerelements) +; FALLBACK-WITH-REPORT-ERR-G_IMPLICIT_DEF-LEGALIZABLE: (FIXME: this is what is expected once we can legalize non-pow-of-2 G_IMPLICIT_DEF) remark: :0:0: unable to legalize instruction: %1(<7 x s64>) = G_ADD %0, %0; (in function: nonpow2_vector_add_fewerelements +; FALLBACK-WITH-REPORT-ERR: remark: :0:0: unable to legalize instruction: %2(s64) = G_EXTRACT_VECTOR_ELT %1, %3; (in function: nonpow2_vector_add_fewerelements) ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for nonpow2_vector_add_fewerelements ; FALLBACK-WITH-REPORT-OUT-LABEL: nonpow2_vector_add_fewerelements: define void @nonpow2_vector_add_fewerelements() { diff --git a/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll b/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll index 7c67a22e23c8c..62203213a78cf 100644 --- a/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll +++ b/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll @@ -58,19 +58,19 @@ define void @allocai64() { ; CHECK: body: ; ; ABI/constant lowering and IR-level entry basic block. -; CHECK: {{bb.[0-9]+}}.entry: +; CHECK: bb.{{[0-9]+}}.{{[a-zA-Z0-9.]+}}: ; ; Make sure we have one successor and only one. -; CHECK-NEXT: successors: %[[BB2:bb.[0-9]+.bb2]](0x80000000) +; CHECK-NEXT: successors: %[[BB2:bb.[0-9]+]](0x80000000) ; ; Check that we emit the correct branch. ; CHECK: G_BR %[[BB2]] ; ; Check that end contains the return instruction. -; CHECK: [[END:bb.[0-9]+.end]]: +; CHECK: [[END:bb.[0-9]+]].{{[a-zA-Z0-9.]+}}: ; CHECK-NEXT: RET_ReallyLR ; -; CHECK: {{bb.[0-9]+}}.bb2: +; CHECK: bb.{{[0-9]+}}.{{[a-zA-Z0-9.]+}}: ; CHECK-NEXT: successors: %[[END]](0x80000000) ; CHECK: G_BR %[[END]] define void @uncondbr() { @@ -84,11 +84,11 @@ bb2: ; CHECK-LABEL: name: uncondbr_fallthrough ; CHECK: body: -; CHECK: {{bb.[0-9]+}}.entry: -; CHECK-NEXT: successors: %[[END:bb.[0-9]+.end]](0x80000000) +; CHECK: bb.{{[0-9]+}}.{{[a-zA-Z0-9.]+}}: +; CHECK-NEXT: successors: %[[END:bb.[0-9]+]](0x80000000) ; We don't emit a branch here, as we can fallthrough to the successor. ; CHECK-NOT: G_BR -; CHECK: [[END]]: +; CHECK: [[END]].{{[a-zA-Z0-9.]+}}: ; CHECK-NEXT: RET_ReallyLR define void @uncondbr_fallthrough() { entry: @@ -102,10 +102,10 @@ end: ; CHECK: body: ; ; ABI/constant lowering and IR-level entry basic block. -; CHECK: {{bb.[0-9]+}} (%ir-block.{{[0-9]+}}): +; CHECK: bb.{{[0-9]+}} (%ir-block.{{[0-9]+}}): ; Make sure we have two successors -; CHECK-NEXT: successors: %[[TRUE:bb.[0-9]+.true]](0x40000000), -; CHECK: %[[FALSE:bb.[0-9]+.false]](0x40000000) +; CHECK-NEXT: successors: %[[TRUE:bb.[0-9]+]](0x40000000), +; CHECK: %[[FALSE:bb.[0-9]+]](0x40000000) ; ; CHECK: [[ADDR:%.*]]:_(p0) = COPY %x0 ; @@ -115,9 +115,9 @@ end: ; CHECK: G_BR %[[FALSE]] ; ; Check that each successor contains the return instruction. -; CHECK: [[TRUE]]: +; CHECK: [[TRUE]].{{[a-zA-Z0-9.]+}}: ; CHECK-NEXT: RET_ReallyLR -; CHECK: [[FALSE]]: +; CHECK: [[FALSE]].{{[a-zA-Z0-9.]+}}: ; CHECK-NEXT: RET_ReallyLR define void @condbr(i1* %tstaddr) { %tst = load i1, i1* %tstaddr @@ -133,8 +133,8 @@ false: ; CHECK-LABEL: name: switch ; CHECK: body: ; -; CHECK: {{bb.[0-9]+.entry}}: -; CHECK-NEXT: successors: %[[BB_CASE100:bb.[0-9]+.case100]](0x40000000), %[[BB_NOTCASE100_CHECKNEXT:bb.[0-9]+.entry]](0x40000000) +; CHECK: bb.{{[a-zA-Z0-9.]+}}: +; CHECK-NEXT: successors: %[[BB_CASE100:bb.[0-9]+]](0x40000000), %[[BB_NOTCASE100_CHECKNEXT:bb.[0-9]+]](0x40000000) ; CHECK: %0:_(s32) = COPY %w0 ; CHECK: %[[reg100:[0-9]+]]:_(s32) = G_CONSTANT i32 100 ; CHECK: %[[reg200:[0-9]+]]:_(s32) = G_CONSTANT i32 200 @@ -145,31 +145,31 @@ false: ; CHECK: G_BRCOND %[[regicmp100]](s1), %[[BB_CASE100]] ; CHECK: G_BR %[[BB_NOTCASE100_CHECKNEXT]] ; -; CHECK: [[BB_NOTCASE100_CHECKNEXT]]: -; CHECK-NEXT: successors: %[[BB_CASE200:bb.[0-9]+.case200]](0x40000000), %[[BB_NOTCASE200_CHECKNEXT:bb.[0-9]+.entry]](0x40000000) +; CHECK: [[BB_NOTCASE100_CHECKNEXT]].{{[a-zA-Z0-9.]+}}: +; CHECK-NEXT: successors: %[[BB_CASE200:bb.[0-9]+]](0x40000000), %[[BB_NOTCASE200_CHECKNEXT:bb.[0-9]+]](0x40000000) ; CHECK: %[[regicmp200:[0-9]+]]:_(s1) = G_ICMP intpred(eq), %[[reg200]](s32), %0 ; CHECK: G_BRCOND %[[regicmp200]](s1), %[[BB_CASE200]] ; CHECK: G_BR %[[BB_NOTCASE200_CHECKNEXT]] ; -; CHECK: [[BB_NOTCASE200_CHECKNEXT]]: -; CHECK-NEXT: successors: %[[BB_DEFAULT:bb.[0-9]+.default]](0x80000000) +; CHECK: [[BB_NOTCASE200_CHECKNEXT]].{{[a-zA-Z0-9.]+}}: +; CHECK-NEXT: successors: %[[BB_DEFAULT:bb.[0-9]+]](0x80000000) ; CHECK: G_BR %[[BB_DEFAULT]] ; -; CHECK: [[BB_DEFAULT]]: -; CHECK-NEXT: successors: %[[BB_RET:bb.[0-9]+.return]](0x80000000) +; CHECK: [[BB_DEFAULT]].{{[a-zA-Z0-9.]+}}: +; CHECK-NEXT: successors: %[[BB_RET:bb.[0-9]+]](0x80000000) ; CHECK: %[[regretdefault:[0-9]+]]:_(s32) = G_ADD %0, %[[reg0]] ; CHECK: G_BR %[[BB_RET]] ; -; CHECK: [[BB_CASE100]]: -; CHECK-NEXT: successors: %[[BB_RET:bb.[0-9]+.return]](0x80000000) +; CHECK: [[BB_CASE100]].{{[a-zA-Z0-9.]+}}: +; CHECK-NEXT: successors: %[[BB_RET:bb.[0-9]+]](0x80000000) ; CHECK: %[[regretc100:[0-9]+]]:_(s32) = G_ADD %0, %[[reg1]] ; CHECK: G_BR %[[BB_RET]] ; -; CHECK: [[BB_CASE200]]: +; CHECK: [[BB_CASE200]].{{[a-zA-Z0-9.]+}}: ; CHECK-NEXT: successors: %[[BB_RET]](0x80000000) ; CHECK: %[[regretc200:[0-9]+]]:_(s32) = G_ADD %0, %[[reg2]] ; -; CHECK: [[BB_RET]]: +; CHECK: [[BB_RET]].{{[a-zA-Z0-9.]+}}: ; CHECK-NEXT: %[[regret:[0-9]+]]:_(s32) = G_PHI %[[regretdefault]](s32), %[[BB_DEFAULT]], %[[regretc100]](s32), %[[BB_CASE100]] ; CHECK: %w0 = COPY %[[regret]](s32) ; CHECK: RET_ReallyLR implicit %w0 @@ -202,16 +202,16 @@ return: ; %entry block is no longer a predecessor for the phi instruction. We need to ; use the correct lowered MachineBasicBlock instead. ; CHECK-LABEL: name: test_cfg_remap -; CHECK: {{bb.[0-9]+.entry}}: -; CHECK-NEXT: successors: %{{bb.[0-9]+.next}}(0x40000000), %[[NOTCASE1_BLOCK:bb.[0-9]+.entry]](0x40000000) -; CHECK: [[NOTCASE1_BLOCK]]: -; CHECK-NEXT: successors: %{{bb.[0-9]+.other}}(0x40000000), %[[NOTCASE57_BLOCK:bb.[0-9]+.entry]](0x40000000) -; CHECK: [[NOTCASE57_BLOCK]]: -; CHECK-NEXT: successors: %[[PHI_BLOCK:bb.[0-9]+.phi.block]](0x80000000) +; CHECK: bb.{{[0-9]+.[a-zA-Z0-9.]+}}: +; CHECK-NEXT: successors: %{{bb.[0-9]+}}(0x40000000), %[[NOTCASE1_BLOCK:bb.[0-9]+]](0x40000000) +; CHECK: [[NOTCASE1_BLOCK]].{{[a-zA-Z0-9.]+}}: +; CHECK-NEXT: successors: %{{bb.[0-9]+}}(0x40000000), %[[NOTCASE57_BLOCK:bb.[0-9]+]](0x40000000) +; CHECK: [[NOTCASE57_BLOCK]].{{[a-zA-Z0-9.]+}}: +; CHECK-NEXT: successors: %[[PHI_BLOCK:bb.[0-9]+]](0x80000000) ; CHECK: G_BR %[[PHI_BLOCK]] ; -; CHECK: [[PHI_BLOCK]]: -; CHECK-NEXT: G_PHI %{{.*}}(s32), %[[NOTCASE57_BLOCK:bb.[0-9]+.entry]], %{{.*}}(s32), +; CHECK: [[PHI_BLOCK]].{{[a-zA-Z0-9.]+}}: +; CHECK-NEXT: G_PHI %{{.*}}(s32), %[[NOTCASE57_BLOCK:bb.[0-9]+]], %{{.*}}(s32), ; define i32 @test_cfg_remap(i32 %in) { entry: @@ -230,7 +230,7 @@ phi.block: } ; CHECK-LABEL: name: test_cfg_remap_multiple_preds -; CHECK: G_PHI [[ENTRY:%.*]](s32), %bb.{{[0-9]+}}.entry, [[ENTRY]](s32), %bb.{{[0-9]+}}.entry +; CHECK: G_PHI [[ENTRY:%.*]](s32), %bb.{{[0-9]+}}, [[ENTRY]](s32), %bb.{{[0-9]+}} define i32 @test_cfg_remap_multiple_preds(i32 %in) { entry: switch i32 %in, label %odd [i32 1, label %next @@ -256,19 +256,19 @@ phi.block: ; CHECK: body: ; ; ABI/constant lowering and IR-level entry basic block. -; CHECK: {{bb.[0-9]+.entry}}: +; CHECK: bb.{{[0-9]+.[a-zA-Z0-9.]+}}: ; Make sure we have one successor -; CHECK-NEXT: successors: %[[BB_L1:bb.[0-9]+.L1]](0x80000000) +; CHECK-NEXT: successors: %[[BB_L1:bb.[0-9]+]](0x80000000) ; CHECK-NOT: G_BR ; ; Check basic block L1 has 2 successors: BBL1 and BBL2 -; CHECK: [[BB_L1]] (address-taken): +; CHECK: [[BB_L1]].{{[a-zA-Z0-9.]+}} (address-taken): ; CHECK-NEXT: successors: %[[BB_L1]](0x40000000), -; CHECK: %[[BB_L2:bb.[0-9]+.L2]](0x40000000) +; CHECK: %[[BB_L2:bb.[0-9]+]](0x40000000) ; CHECK: G_BRINDIRECT %{{[0-9]+}}(p0) ; ; Check basic block L2 is the return basic block -; CHECK: [[BB_L2]] (address-taken): +; CHECK: [[BB_L2]].{{[a-zA-Z0-9.]+}} (address-taken): ; CHECK-NEXT: RET_ReallyLR @indirectbr.L = internal unnamed_addr constant [3 x i8*] [i8* blockaddress(@indirectbr, %L1), i8* blockaddress(@indirectbr, %L2), i8* null], align 8 @@ -410,11 +410,11 @@ define i64* @trivial_bitcast(i8* %a) { ; CHECK-LABEL: name: trivial_bitcast_with_copy ; CHECK: [[A:%[0-9]+]]:_(p0) = COPY %x0 -; CHECK: G_BR %[[CAST:bb\.[0-9]+.cast]] +; CHECK: G_BR %[[CAST:bb\.[0-9]+]] -; CHECK: [[END:bb\.[0-9]+.end]]: +; CHECK: [[END:bb\.[0-9]+]].{{[a-zA-Z0-9.]+}}: -; CHECK: [[CAST]]: +; CHECK: [[CAST]].{{[a-zA-Z0-9.]+}}: ; CHECK: {{%[0-9]+}}:_(p0) = COPY [[A]] ; CHECK: G_BR %[[END]] define i64* @trivial_bitcast_with_copy(i8* %a) { @@ -512,13 +512,13 @@ define void @intrinsics(i32 %cur, i32 %bits) { } ; CHECK-LABEL: name: test_phi -; CHECK: G_BRCOND {{%.*}}, %[[TRUE:bb\.[0-9]+.true]] -; CHECK: G_BR %[[FALSE:bb\.[0-9]+.false]] +; CHECK: G_BRCOND {{%.*}}, %[[TRUE:bb\.[0-9]+]] +; CHECK: G_BR %[[FALSE:bb\.[0-9]+]] -; CHECK: [[TRUE]]: +; CHECK: [[TRUE]].{{[a-zA-Z0-9.]+}}: ; CHECK: [[RES1:%[0-9]+]]:_(s32) = G_LOAD -; CHECK: [[FALSE]]: +; CHECK: [[FALSE]].{{[a-zA-Z0-9.]+}}: ; CHECK: [[RES2:%[0-9]+]]:_(s32) = G_LOAD ; CHECK: [[RES:%[0-9]+]]:_(s32) = G_PHI [[RES1]](s32), %[[TRUE]], [[RES2]](s32), %[[FALSE]] @@ -554,7 +554,7 @@ define void @unreachable(i32 %a) { ; CHECK: [[IN:%[0-9]+]]:_(s32) = COPY %w0 ; CHECK: [[ONE:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 -; CHECK: {{bb.[0-9]+}}.next: +; CHECK: bb.{{[0-9]+}}.{{[a-zA-Z0-9.]+}}: ; CHECK: [[SUM1:%[0-9]+]]:_(s32) = G_ADD [[IN]], [[ONE]] ; CHECK: [[SUM2:%[0-9]+]]:_(s32) = G_ADD [[IN]], [[ONE]] ; CHECK: [[RES:%[0-9]+]]:_(s32) = G_ADD [[SUM1]], [[SUM2]] @@ -1226,7 +1226,7 @@ define i8* @test_const_placement() { ; CHECK: bb.{{[0-9]+}} (%ir-block.{{[0-9]+}}): ; CHECK: [[VAL_INT:%[0-9]+]]:_(s32) = G_CONSTANT i32 42 ; CHECK: [[VAL:%[0-9]+]]:_(p0) = G_INTTOPTR [[VAL_INT]](s32) -; CHECK: {{bb.[0-9]+}}.next: +; CHECK: bb.{{[0-9]+}}.{{[a-zA-Z0-9.]+}}: br label %next next: @@ -1332,12 +1332,12 @@ define void @test_lifetime_intrin() { define void @test_load_store_atomics(i8* %addr) { ; CHECK-LABEL: name: test_load_store_atomics ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x0 -; CHECK: [[V0:%[0-9]+]]:_(s8) = G_LOAD [[ADDR]](p0) :: (load unordered 1 from %ir.addr) -; CHECK: G_STORE [[V0]](s8), [[ADDR]](p0) :: (store monotonic 1 into %ir.addr) -; CHECK: [[V1:%[0-9]+]]:_(s8) = G_LOAD [[ADDR]](p0) :: (load acquire 1 from %ir.addr) -; CHECK: G_STORE [[V1]](s8), [[ADDR]](p0) :: (store release 1 into %ir.addr) -; CHECK: [[V2:%[0-9]+]]:_(s8) = G_LOAD [[ADDR]](p0) :: (load syncscope("singlethread") seq_cst 1 from %ir.addr) -; CHECK: G_STORE [[V2]](s8), [[ADDR]](p0) :: (store syncscope("singlethread") monotonic 1 into %ir.addr) +; CHECK: [[V0:%[0-9]+]]:_(s8) = G_ATOMIC_LOAD [[ADDR]](p0) :: (load unordered 1 from %ir.addr) +; CHECK: G_ATOMIC_STORE [[V0]](s8), [[ADDR]](p0) :: (store monotonic 1 into %ir.addr) +; CHECK: [[V1:%[0-9]+]]:_(s8) = G_ATOMIC_LOAD [[ADDR]](p0) :: (load acquire 1 from %ir.addr) +; CHECK: G_ATOMIC_STORE [[V1]](s8), [[ADDR]](p0) :: (store release 1 into %ir.addr) +; CHECK: [[V2:%[0-9]+]]:_(s8) = G_ATOMIC_LOAD [[ADDR]](p0) :: (load syncscope("singlethread") seq_cst 1 from %ir.addr) +; CHECK: G_ATOMIC_STORE [[V2]](s8), [[ADDR]](p0) :: (store syncscope("singlethread") monotonic 1 into %ir.addr) %v0 = load atomic i8, i8* %addr unordered, align 1 store atomic i8 %v0, i8* %addr monotonic, align 1 @@ -1636,3 +1636,16 @@ define i32 @test_target_mem_intrinsic(i32* %addr) { } declare i64 @llvm.aarch64.ldxr.p0i32(i32*) nounwind + +%zerosize_type = type {} + +define %zerosize_type @test_empty_load_store(%zerosize_type *%ptr, %zerosize_type %in) noinline optnone { +; CHECK-LABEL: name: test_empty_load_store +; CHECK-NOT: G_STORE +; CHECK-NOT: G_LOAD +; CHECK: RET_ReallyLR +entry: + store %zerosize_type undef, %zerosize_type* undef, align 4 + %val = load %zerosize_type, %zerosize_type* %ptr, align 4 + ret %zerosize_type %in +} diff --git a/test/CodeGen/AArch64/GlobalISel/debug-insts.ll b/test/CodeGen/AArch64/GlobalISel/debug-insts.ll index eb2d2ec4307c6..be510b5f7e3be 100644 --- a/test/CodeGen/AArch64/GlobalISel/debug-insts.ll +++ b/test/CodeGen/AArch64/GlobalISel/debug-insts.ll @@ -6,7 +6,7 @@ ; CHECK: - { id: {{.*}}, name: in.addr, type: default, offset: 0, size: {{.*}}, alignment: {{.*}}, ; CHECK-NEXT: callee-saved-register: '', callee-saved-restored: true, ; CHECK-NEXT: di-variable: '!11', di-expression: '!DIExpression()', -; CHECK: DBG_VALUE debug-use %0(s32), debug-use _, !11, !DIExpression(), debug-location !12 +; CHECK: DBG_VALUE debug-use %0(s32), debug-use %noreg, !11, !DIExpression(), debug-location !12 define void @debug_declare(i32 %in) #0 !dbg !7 { entry: %in.addr = alloca i32, align 4 @@ -17,7 +17,7 @@ entry: } ; CHECK-LABEL: name: debug_declare_vla -; CHECK: DBG_VALUE debug-use %{{[0-9]+}}(p0), debug-use _, !14, !DIExpression(), debug-location !15 +; CHECK: DBG_VALUE debug-use %{{[0-9]+}}(p0), debug-use %noreg, !14, !DIExpression(), debug-location !15 define void @debug_declare_vla(i32 %in) #0 !dbg !13 { entry: %vla.addr = alloca i32, i32 %in @@ -29,16 +29,16 @@ entry: ; CHECK: [[IN:%[0-9]+]]:_(s32) = COPY %w0 define void @debug_value(i32 %in) #0 !dbg !16 { %addr = alloca i32 -; CHECK: DBG_VALUE debug-use [[IN]](s32), debug-use _, !17, !DIExpression(), debug-location !18 +; CHECK: DBG_VALUE debug-use [[IN]](s32), debug-use %noreg, !17, !DIExpression(), debug-location !18 call void @llvm.dbg.value(metadata i32 %in, i64 0, metadata !17, metadata !DIExpression()), !dbg !18 store i32 %in, i32* %addr -; CHECK: DBG_VALUE debug-use %1(p0), debug-use _, !17, !DIExpression(DW_OP_deref), debug-location !18 +; CHECK: DBG_VALUE debug-use %1(p0), debug-use %noreg, !17, !DIExpression(DW_OP_deref), debug-location !18 call void @llvm.dbg.value(metadata i32* %addr, i64 0, metadata !17, metadata !DIExpression(DW_OP_deref)), !dbg !18 ; CHECK: DBG_VALUE 123, 0, !17, !DIExpression(), debug-location !18 call void @llvm.dbg.value(metadata i32 123, i64 0, metadata !17, metadata !DIExpression()), !dbg !18 ; CHECK: DBG_VALUE float 1.000000e+00, 0, !17, !DIExpression(), debug-location !18 call void @llvm.dbg.value(metadata float 1.000000e+00, i64 0, metadata !17, metadata !DIExpression()), !dbg !18 -; CHECK: DBG_VALUE _, 0, !17, !DIExpression(), debug-location !18 +; CHECK: DBG_VALUE %noreg, 0, !17, !DIExpression(), debug-location !18 call void @llvm.dbg.value(metadata i32* null, i64 0, metadata !17, metadata !DIExpression()), !dbg !18 ret void } diff --git a/test/CodeGen/AArch64/GlobalISel/irtranslator-exceptions.ll b/test/CodeGen/AArch64/GlobalISel/irtranslator-exceptions.ll index 0e7fbd32c6fa8..827fdd261082b 100644 --- a/test/CodeGen/AArch64/GlobalISel/irtranslator-exceptions.ll +++ b/test/CodeGen/AArch64/GlobalISel/irtranslator-exceptions.ll @@ -9,7 +9,7 @@ declare i32 @llvm.eh.typeid.for(i8*) ; CHECK-LABEL: name: bar ; CHECK: body: ; CHECK-NEXT: bb.1 (%ir-block.0): -; CHECK: successors: %[[GOOD:bb.[0-9]+.continue]]{{.*}}%[[BAD:bb.[0-9]+.broken]] +; CHECK: successors: %[[GOOD:bb.[0-9]+]]{{.*}}%[[BAD:bb.[0-9]+]] ; CHECK: EH_LABEL ; CHECK: %w0 = COPY ; CHECK: BL @foo, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %w0, implicit-def %w0 @@ -17,7 +17,7 @@ declare i32 @llvm.eh.typeid.for(i8*) ; CHECK: EH_LABEL ; CHECK: G_BR %[[GOOD]] -; CHECK: [[BAD]] (landing-pad): +; CHECK: [[BAD]].{{[a-z]+}} (landing-pad): ; CHECK: EH_LABEL ; CHECK: [[UNDEF:%[0-9]+]]:_(s128) = G_IMPLICIT_DEF ; CHECK: [[PTR:%[0-9]+]]:_(p0) = COPY %x0 @@ -30,7 +30,7 @@ declare i32 @llvm.eh.typeid.for(i8*) ; CHECK: %x0 = COPY [[PTR_RET]] ; CHECK: %w1 = COPY [[SEL_RET]] -; CHECK: [[GOOD]]: +; CHECK: [[GOOD]].{{[a-z]+}}: ; CHECK: [[SEL:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; CHECK: {{%[0-9]+}}:_(s128) = G_INSERT {{%[0-9]+}}, [[SEL]](s32), 64 diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-atomic-load-store.mir b/test/CodeGen/AArch64/GlobalISel/legalize-atomic-load-store.mir new file mode 100644 index 0000000000000..da95f6b302e56 --- /dev/null +++ b/test/CodeGen/AArch64/GlobalISel/legalize-atomic-load-store.mir @@ -0,0 +1,91 @@ +# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s + +--- | + target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" + target triple = "aarch64--" + define void @test_load(i8* %addr) { + entry: + ret void + } + define void @test_store(i8* %addr) { + entry: + ret void + } +... + +--- +name: test_load +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } + - { id: 6, class: _ } +body: | + bb.0.entry: + liveins: %x0, %x1, %x2, %x3 + ; CHECK-LABEL: name: test_load + %0(p0) = COPY %x0 + + ; CHECK: %1:_(s8) = G_ATOMIC_LOAD %0(p0) :: (load unordered 1 from %ir.addr) + %1(s8) = G_ATOMIC_LOAD %0 :: (load unordered 1 from %ir.addr) + %10:_(s32) = G_ANYEXT %1 + %w0 = COPY %10 + + ; CHECK: %2:_(s16) = G_ATOMIC_LOAD %0(p0) :: (load unordered 2 from %ir.addr) + %2(s16) = G_ATOMIC_LOAD %0 :: (load unordered 2 from %ir.addr) + %11:_(s32) = G_ANYEXT %2 + %w0 = COPY %11 + + ; CHECK: %3:_(s32) = G_ATOMIC_LOAD %0(p0) :: (load unordered 4 from %ir.addr) + %3(s32) = G_ATOMIC_LOAD %0 :: (load unordered 4 from %ir.addr) + %w0 = COPY %3 + + ; CHECK: %4:_(s64) = G_ATOMIC_LOAD %0(p0) :: (load unordered 8 from %ir.addr) + %4(s64) = G_ATOMIC_LOAD %0 :: (load unordered 8 from %ir.addr) + %x0 = COPY %4 + + %5(p0) = G_ATOMIC_LOAD %0(p0) :: (load unordered 8 from %ir.addr) + %12:_(s64) = G_PTRTOINT %5 + %x0 = COPY %12 +... + +--- +name: test_store +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } + - { id: 6, class: _ } + - { id: 7, class: _ } +body: | + bb.0.entry: + liveins: %x0, %x1, %x2, %x3 + ; CHECK-LABEL: name: test_store + + %0(p0) = COPY %x0 + %1(s32) = COPY %w1 + + ; CHECK: G_ATOMIC_STORE %2(s8), %0(p0) :: (store unordered 1 into %ir.addr) + %2(s8) = G_TRUNC %1 + G_ATOMIC_STORE %2, %0 :: (store unordered 1 into %ir.addr) + + ; CHECK: G_ATOMIC_STORE %3(s16), %0(p0) :: (store unordered 2 into %ir.addr) + %3(s16) = G_TRUNC %1 + G_ATOMIC_STORE %3, %0 :: (store unordered 2 into %ir.addr) + + ; CHECK: G_ATOMIC_STORE %1(s32), %0(p0) :: (store unordered 4 into %ir.addr) + G_ATOMIC_STORE %1, %0 :: (store unordered 4 into %ir.addr) + + ; CHECK: G_ATOMIC_STORE %4(s64), %0(p0) :: (store unordered 8 into %ir.addr) + %4(s64) = G_PTRTOINT %0(p0) + G_ATOMIC_STORE %4, %0 :: (store unordered 8 into %ir.addr) + + ; CHECK: G_ATOMIC_STORE %0(p0), %0(p0) :: (store unordered 8 into %ir.addr) + G_ATOMIC_STORE %0(p0), %0(p0) :: (store unordered 8 into %ir.addr) +... diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-cmpxchg-with-success.mir b/test/CodeGen/AArch64/GlobalISel/legalize-cmpxchg-with-success.mir new file mode 100644 index 0000000000000..633033670cc9d --- /dev/null +++ b/test/CodeGen/AArch64/GlobalISel/legalize-cmpxchg-with-success.mir @@ -0,0 +1,59 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=aarch64-- -mattr=+lse -run-pass=legalizer -verify-machineinstrs -global-isel %s -o - | FileCheck %s + +--- | + target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" + + define void @cmpxchg_i32(i64* %addr) { ret void } + define void @cmpxchg_i64(i64* %addr) { ret void } +... + +--- +name: cmpxchg_i32 + +body: | + bb.0: + liveins: %x0 + + ; CHECK-LABEL: name: cmpxchg_i32 + ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY %x0 + ; CHECK: [[CMP:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK: [[CST:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK: [[RES:%[0-9]+]]:_(s32) = G_ATOMIC_CMPXCHG [[COPY]](p0), [[CMP]], [[CST]] :: (load store monotonic 8 on %ir.addr) + ; CHECK: [[SRES:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[RES]](s32), [[CMP]] + ; CHECK: [[SRES32:%[0-9]+]]:_(s32) = COPY [[SRES]] + ; CHECK: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[RES]], [[SRES32]] + ; CHECK: %w0 = COPY [[MUL]] + %0:_(p0) = COPY %x0 + %1:_(s32) = G_CONSTANT i32 0 + %2:_(s32) = G_CONSTANT i32 1 + %3:_(s32), %4:_(s1) = G_ATOMIC_CMPXCHG_WITH_SUCCESS %0, %1, %2 :: (load store monotonic 8 on %ir.addr) + %5:_(s32) = G_ANYEXT %4 + %6:_(s32) = G_MUL %3, %5 + %w0 = COPY %6(s32) +... + +--- +name: cmpxchg_i64 + +body: | + bb.0: + liveins: %x0 + + ; CHECK-LABEL: name: cmpxchg_i64 + ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY %x0 + ; CHECK: [[CMP:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK: [[CST:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK: [[RES:%[0-9]+]]:_(s64) = G_ATOMIC_CMPXCHG [[COPY]](p0), [[CMP]], [[CST]] :: (load store monotonic 8 on %ir.addr) + ; CHECK: [[SRES:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[RES]](s64), [[CMP]] + ; CHECK: [[SRES64:%[0-9]+]]:_(s64) = G_ANYEXT [[SRES]] + ; CHECK: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[RES]], [[SRES64]] + ; CHECK: %x0 = COPY [[MUL]] + %0:_(p0) = COPY %x0 + %1:_(s64) = G_CONSTANT i64 0 + %2:_(s64) = G_CONSTANT i64 1 + %3:_(s64), %4:_(s1) = G_ATOMIC_CMPXCHG_WITH_SUCCESS %0, %1, %2 :: (load store monotonic 8 on %ir.addr) + %5:_(s64) = G_ANYEXT %4 + %6:_(s64) = G_MUL %3, %5 + %x0 = COPY %6(s64) +... diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-combines.mir b/test/CodeGen/AArch64/GlobalISel/legalize-combines.mir index 82594b8c476a1..9cf0f8fd0e716 100644 --- a/test/CodeGen/AArch64/GlobalISel/legalize-combines.mir +++ b/test/CodeGen/AArch64/GlobalISel/legalize-combines.mir @@ -8,7 +8,6 @@ define void @test_combines_3() { ret void } define void @test_combines_4() { ret void } define void @test_combines_5() { ret void } - define void @test_combines_6() { ret void } ... --- @@ -90,23 +89,3 @@ body: | %5:_(s32) = G_ADD %3, %4 %w0 = COPY %5 ... - ---- -name: test_combines_6 -body: | - bb.0: - liveins: %w0 - - ; Check that we replace all the uses of a G_EXTRACT. - ; CHECK-LABEL: name: test_combines_6 - ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0 - ; CHECK: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY]], [[COPY]] - ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[MUL]] - %0:_(s32) = COPY %w0 - - %1:_(s32) = G_MERGE_VALUES %0 - %2:_(s32) = G_UNMERGE_VALUES %1 - %3:_(s32) = G_MUL %2, %2 - %4:_(s32) = G_ADD %2, %3 - %w0 = COPY %4 -... diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-exceptions.ll b/test/CodeGen/AArch64/GlobalISel/legalize-exceptions.ll index da40b274aa620..01f955bc1d102 100644 --- a/test/CodeGen/AArch64/GlobalISel/legalize-exceptions.ll +++ b/test/CodeGen/AArch64/GlobalISel/legalize-exceptions.ll @@ -10,9 +10,9 @@ declare void @_Unwind_Resume(i8*) ; CHECK: name: bar ; CHECK: body: ; CHECK-NEXT: bb.1 (%ir-block.0): -; CHECK: successors: %{{bb.[0-9]+.continue.*}}%[[LP:bb.[0-9]+.cleanup]] +; CHECK: successors: %{{bb.[0-9]+.*}}%[[LP:bb.[0-9]+]] -; CHECK: [[LP]] (landing-pad): +; CHECK: [[LP]].{{[a-z]+}} (landing-pad): ; CHECK: EH_LABEL ; CHECK: [[PTR:%[0-9]+]]:_(p0) = COPY %x0 diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-merge-values.mir b/test/CodeGen/AArch64/GlobalISel/legalize-merge-values.mir new file mode 100644 index 0000000000000..e6171380344ec --- /dev/null +++ b/test/CodeGen/AArch64/GlobalISel/legalize-merge-values.mir @@ -0,0 +1,30 @@ +# RUN: llc -O0 -run-pass=legalizer -global-isel -global-isel-abort=0 -pass-remarks-missed='gisel*' %s -o - 2>&1 | FileCheck %s + +--- | + target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" + target triple = "aarch64--" + define void @test_merge_s4() { + ret void + } +... + +--- +name: test_merge_s4 +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } +body: | + bb.0: + %0(s64) = G_CONSTANT i64 0 + %1(s4) = G_TRUNC %0(s64) + ; Previously, LegalizerInfo was assuming all G_MERGE_VALUES and G_UNMERGE_VALUES + ; instructions are legal. Make sure that is no longer happening. + ; CHECK: unable to legalize instruction: {{.*}} G_MERGE_VALUES + %2(s8) = G_MERGE_VALUES %1(s4), %1(s4) + %3(s8) = COPY %2(s8) + %4(s64) = G_ANYEXT %3(s8) + %x0 = COPY %4(s64) +... diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-nonpowerof2eltsvec.mir b/test/CodeGen/AArch64/GlobalISel/legalize-nonpowerof2eltsvec.mir index a586e69c855cb..168e1df02775e 100644 --- a/test/CodeGen/AArch64/GlobalISel/legalize-nonpowerof2eltsvec.mir +++ b/test/CodeGen/AArch64/GlobalISel/legalize-nonpowerof2eltsvec.mir @@ -4,33 +4,31 @@ --- | target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" target triple = "aarch64--" - define void @test_legalize_merge_v3s32() { + define void @test_legalize_merge_v3s64() { ret void } ... --- -name: test_legalize_merge_v3s32 +name: test_legalize_merge_v3s64 registers: - { id: 0, class: _ } - { id: 1, class: _ } - { id: 2, class: _ } - { id: 3, class: _ } + - { id: 4, class: _ } + - { id: 5, class: _ } body: | bb.0: - liveins: %w0, %w1, %w2 - ; CHECK-LABEL: name: test_legalize_merge_v3s32 - ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0 - ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY %w1 - ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY %w2 - ; CHECK: %w0 = COPY [[COPY]](s32) - ; CHECK: %w1 = COPY [[COPY1]](s32) - ; CHECK: %w2 = COPY [[COPY2]](s32) - %0(s32) = COPY %w0 - %1(s32) = COPY %w1 - %2(s32) = COPY %w2 - %3(<3 x s32>) = G_MERGE_VALUES %0(s32), %1(s32), %2(s32) - %4:_(s32), %5:_(s32), %6:_(s32) = G_UNMERGE_VALUES %3 - %w0 = COPY %4 - %w1 = COPY %5 - %w2 = COPY %6 + liveins: %w0 + ; CHECK-LABEL: name: test_legalize_merge_v3s64 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0 + ; CHECK: [[MV:%[0-9]+]]:_(<3 x s64>) = G_MERGE_VALUES [[COPY]](s64), [[COPY]](s64), [[COPY]](s64) + ; CHECK: [[COPY1:%[0-9]+]]:_(<3 x s64>) = COPY [[MV]](<3 x s64>) + ; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64), [[UV2:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY1]](<3 x s64>) + ; CHECK: %x0 = COPY [[UV]](s64) + %0(s64) = COPY %x0 + %1(<3 x s64>) = G_MERGE_VALUES %0(s64), %0(s64), %0(s64) + %2(<3 x s64>) = COPY %1(<3 x s64>) + %3(s64), %4(s64), %5(s64) = G_UNMERGE_VALUES %2(<3 x s64>) + %x0 = COPY %3(s64) ... diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir b/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir index 9c028eb9d95be..a7329916ea83b 100644 --- a/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir +++ b/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir @@ -43,16 +43,16 @@ registers: - { id: 16, class: _ } body: | ; CHECK-LABEL: name: test_simple - ; CHECK: bb.0.entry: - ; CHECK: successors: %bb.1.next(0x80000000) + ; CHECK: bb.0.{{[a-zA-Z0-9]+}}: + ; CHECK: successors: %bb.1(0x80000000) ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0 ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s64) ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) ; CHECK: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[COPY]](s64) ; CHECK: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[INTTOPTR]](p0) ; CHECK: %x0 = COPY [[PTRTOINT]](s64) - ; CHECK: G_BRCOND [[TRUNC]](s1), %bb.1.next - ; CHECK: bb.1.next: + ; CHECK: G_BRCOND [[TRUNC]](s1), %bb.1 + ; CHECK: bb.1.{{[a-zA-Z0-9]+}}: ; CHECK: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) ; CHECK: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) ; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[TRUNC2]], [[TRUNC3]] @@ -95,7 +95,7 @@ body: | %6(s64) = G_PTRTOINT %5 %x0 = COPY %6 - G_BRCOND %1, %bb.1.next + G_BRCOND %1, %bb.1 bb.1.next: diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-unmerge-values.mir b/test/CodeGen/AArch64/GlobalISel/legalize-unmerge-values.mir new file mode 100644 index 0000000000000..85b65e9454862 --- /dev/null +++ b/test/CodeGen/AArch64/GlobalISel/legalize-unmerge-values.mir @@ -0,0 +1,28 @@ +# RUN: llc -O0 -run-pass=legalizer -global-isel -global-isel-abort=0 -pass-remarks-missed='gisel*' %s -o - 2>&1 | FileCheck %s + +--- | + target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" + target triple = "aarch64--" + define void @test_unmerge_s4() { + ret void + } +... + +--- +name: test_unmerge_s4 +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } +body: | + bb.0: + %0(s8) = G_CONSTANT i8 0 + ; Previously, LegalizerInfo was assuming all G_MERGE_VALUES and G_UNMERGE_VALUES + ; instructions are legal. Make sure that is no longer happening. + ; CHECK: unable to legalize instruction: {{.*}} G_UNMERGE_VALUES + %1(s4), %2(s4)= G_UNMERGE_VALUES %0(s8) + %3(s64) = G_ANYEXT %1(s4) + %x0 = COPY %3(s64) + +... diff --git a/test/CodeGen/AArch64/GlobalISel/localizer-in-O0-pipeline.mir b/test/CodeGen/AArch64/GlobalISel/localizer-in-O0-pipeline.mir index 997205bc0ef65..d4ed70fa5316c 100644 --- a/test/CodeGen/AArch64/GlobalISel/localizer-in-O0-pipeline.mir +++ b/test/CodeGen/AArch64/GlobalISel/localizer-in-O0-pipeline.mir @@ -59,19 +59,19 @@ registers: # CHECK: %5:fpr(s32) = G_FCONSTANT float 2.000000e+00 # Second block will get the constant 1.0 when the localizer is enabled. -# CHECK: bb.1.true: +# CHECK: bb.1.{{[a-zA-Z0-9]+}}: # OPT-NOT: G_FCONSTANT # OPTNONE: [[FONE:%[0-9]+]]:fpr(s32) = G_FCONSTANT float 1.000000e+00 -# CHECK: G_BR %bb.3.end +# CHECK: G_BR %bb.3 # Thrid block will get the constant 2.0 when the localizer is enabled. -# CHECK: bb.2.false: +# CHECK: bb.2.{{[a-zA-Z0-9]+}}: # OPT-NOT: G_FCONSTANT # OPTNONE: [[FTWO:%[0-9]+]]:fpr(s32) = G_FCONSTANT float 2.000000e+00 # CHECK: bb.3.end -# OPTNONE: %2:fpr(s32) = PHI [[FONE]](s32), %bb.1.true, [[FTWO]](s32), %bb.2.false -# OPT: %2:fpr(s32) = PHI %4(s32), %bb.1.true, %5(s32), %bb.2.false +# OPTNONE: %2:fpr(s32) = PHI [[FONE]](s32), %bb.1, [[FTWO]](s32), %bb.2 +# OPT: %2:fpr(s32) = PHI %4(s32), %bb.1, %5(s32), %bb.2 # CHECK-NEXT: G_FADD %0, %2 body: | bb.0 (%ir-block.0): @@ -82,16 +82,16 @@ body: | %1(s1) = G_TRUNC %6 %4(s32) = G_FCONSTANT float 1.000000e+00 %5(s32) = G_FCONSTANT float 2.000000e+00 - G_BRCOND %1(s1), %bb.1.true - G_BR %bb.2.false + G_BRCOND %1(s1), %bb.1 + G_BR %bb.2 bb.1.true: - G_BR %bb.3.end + G_BR %bb.3 bb.2.false: bb.3.end: - %2(s32) = PHI %4(s32), %bb.1.true, %5(s32), %bb.2.false + %2(s32) = PHI %4(s32), %bb.1, %5(s32), %bb.2 %3(s32) = G_FADD %0, %2 %s0 = COPY %3(s32) RET_ReallyLR implicit %s0 diff --git a/test/CodeGen/AArch64/GlobalISel/no-regclass.mir b/test/CodeGen/AArch64/GlobalISel/no-regclass.mir index d4d23142ab9c1..8732274fe034e 100644 --- a/test/CodeGen/AArch64/GlobalISel/no-regclass.mir +++ b/test/CodeGen/AArch64/GlobalISel/no-regclass.mir @@ -25,7 +25,7 @@ body: | ; CHECK: [[COPY:%[0-9]+]]:gpr32all = COPY %w0 ; CHECK: %w0 = COPY [[COPY]] %0:gpr(s32) = COPY %w0 - %1:gpr(s32) = G_MERGE_VALUES %0(s32) - %2:gpr(s32) = G_UNMERGE_VALUES %1(s32) + %1:gpr(s64) = G_MERGE_VALUES %0(s32), %0(s32) + %2:gpr(s32), %3:gpr(s32) = G_UNMERGE_VALUES %1(s64) %w0 = COPY %2(s32) ... diff --git a/test/CodeGen/AArch64/GlobalISel/regbankselect-dbg-value.mir b/test/CodeGen/AArch64/GlobalISel/regbankselect-dbg-value.mir index 4282bffdab129..201565c675af7 100644 --- a/test/CodeGen/AArch64/GlobalISel/regbankselect-dbg-value.mir +++ b/test/CodeGen/AArch64/GlobalISel/regbankselect-dbg-value.mir @@ -36,9 +36,9 @@ body: | bb.0: liveins: %w0 %0:_(s32) = COPY %w0 - ; CHECK: DBG_VALUE debug-use %0(s32), debug-use _, !7, !DIExpression(), debug-location !9 - DBG_VALUE debug-use %0(s32), debug-use _, !7, !DIExpression(), debug-location !9 + ; CHECK: DBG_VALUE debug-use %0(s32), debug-use %noreg, !7, !DIExpression(), debug-location !9 + DBG_VALUE debug-use %0(s32), debug-use %noreg, !7, !DIExpression(), debug-location !9 - ; CHECK: DBG_VALUE _, 0, !7, !DIExpression(), debug-location !9 - DBG_VALUE _, 0, !7, !DIExpression(), debug-location !9 + ; CHECK: DBG_VALUE %noreg, 0, !7, !DIExpression(), debug-location !9 + DBG_VALUE %noreg, 0, !7, !DIExpression(), debug-location !9 ... diff --git a/test/CodeGen/AArch64/GlobalISel/select-atomic-load.mir b/test/CodeGen/AArch64/GlobalISel/select-atomic-load.mir new file mode 100644 index 0000000000000..48a8a5187982e --- /dev/null +++ b/test/CodeGen/AArch64/GlobalISel/select-atomic-load.mir @@ -0,0 +1,431 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s + +--- | + target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" + + define void @load_s8_gpr_unordered(i64* %addr) { ret void } + define void @load_s8_gpr_monotonic(i64* %addr) { ret void } + define void @load_s8_gpr_acquire(i64* %addr) { ret void } + define void @load_s8_gpr_release(i64* %addr) { ret void } + define void @load_s8_gpr_acq_rel(i64* %addr) { ret void } + define void @load_s8_gpr_seq_cst(i64* %addr) { ret void } + + define void @load_s32_gpr_unordered(i64* %addr) { ret void } + define void @load_s32_gpr_monotonic(i64* %addr) { ret void } + define void @load_s32_gpr_acquire(i64* %addr) { ret void } + define void @load_s32_gpr_release(i64* %addr) { ret void } + define void @load_s32_gpr_acq_rel(i64* %addr) { ret void } + define void @load_s32_gpr_seq_cst(i64* %addr) { ret void } + + define void @load_s64_gpr_unordered(i64* %addr) { ret void } + define void @load_s64_gpr_monotonic(i64* %addr) { ret void } + define void @load_s64_gpr_acquire(i64* %addr) { ret void } + define void @load_s64_gpr_release(i64* %addr) { ret void } + define void @load_s64_gpr_acq_rel(i64* %addr) { ret void } + define void @load_s64_gpr_seq_cst(i64* %addr) { ret void } +... + +--- +name: load_s8_gpr_unordered +legalized: true +regBankSelected: true + +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } + +body: | + bb.0: + liveins: %x0 + + ; CHECK-LABEL: name: load_s8_gpr_unordered + ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0 + ; CHECK: [[T0:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load release 4 from %ir.addr) + ; CHECK: %x0 = COPY [[T0]] + %0(p0) = COPY %x0 + %1(s8) = G_ATOMIC_LOAD %0 :: (load release 4 from %ir.addr) + %2:gpr(s32) = G_ANYEXT %1 + %x0 = COPY %2(s32) +... + +--- +name: load_s8_gpr_monotonic +legalized: true +regBankSelected: true + +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } + +body: | + bb.0: + liveins: %x0 + + ; CHECK-LABEL: name: load_s8_gpr_monotonic + ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0 + ; CHECK: [[T0:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load release 4 from %ir.addr) + ; CHECK: %x0 = COPY [[T0]] + %0(p0) = COPY %x0 + %1(s8) = G_ATOMIC_LOAD %0 :: (load release 4 from %ir.addr) + %2:gpr(s32) = G_ANYEXT %1 + %x0 = COPY %2(s32) +... + +--- +name: load_s8_gpr_acquire +legalized: true +regBankSelected: true + +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } + +body: | + bb.0: + liveins: %x0 + + ; CHECK-LABEL: name: load_s8_gpr_acquire + ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0 + ; CHECK: [[T0:%[0-9]+]]:gpr32 = LDARB [[COPY]] :: (load acquire 1 from %ir.addr) + ; CHECK: %x0 = COPY [[T0]] + %0(p0) = COPY %x0 + %1(s8) = G_ATOMIC_LOAD %0 :: (load acquire 1 from %ir.addr) + %2:gpr(s32) = G_ANYEXT %1 + %x0 = COPY %2(s32) +... + +--- +name: load_s8_gpr_release +legalized: true +regBankSelected: true + +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } + +body: | + bb.0: + liveins: %x0 + + ; CHECK-LABEL: name: load_s8_gpr_release + ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0 + ; CHECK: [[T0:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load release 1 from %ir.addr) + ; CHECK: %x0 = COPY [[T0]] + %0(p0) = COPY %x0 + %1(s8) = G_ATOMIC_LOAD %0 :: (load release 1 from %ir.addr) + %2:gpr(s32) = G_ANYEXT %1 + %x0 = COPY %2(s32) +... + +--- +name: load_s8_gpr_acq_rel +legalized: true +regBankSelected: true + +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } + +body: | + bb.0: + liveins: %x0 + + ; CHECK-LABEL: name: load_s8_gpr_acq_rel + ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0 + ; CHECK: [[T0:%[0-9]+]]:gpr32 = LDARB [[COPY]] :: (load acq_rel 1 from %ir.addr) + ; CHECK: %x0 = COPY [[T0]] + %0(p0) = COPY %x0 + %1(s8) = G_ATOMIC_LOAD %0 :: (load acq_rel 1 from %ir.addr) + %2:gpr(s32) = G_ANYEXT %1 + %x0 = COPY %2(s32) +... + +--- +name: load_s8_gpr_seq_cst +legalized: true +regBankSelected: true + +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } + +body: | + bb.0: + liveins: %x0 + + ; CHECK-LABEL: name: load_s8_gpr_seq_cst + ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0 + ; CHECK: [[T0:%[0-9]+]]:gpr32 = LDARB [[COPY]] :: (load seq_cst 1 from %ir.addr) + ; CHECK: %x0 = COPY [[T0]] + %0(p0) = COPY %x0 + %1(s8) = G_ATOMIC_LOAD %0 :: (load seq_cst 1 from %ir.addr) + %2:gpr(s32) = G_ANYEXT %1 + %x0 = COPY %2(s32) +... + +--- +name: load_s32_gpr_unordered +legalized: true +regBankSelected: true + +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } + +body: | + bb.0: + liveins: %x0 + + ; CHECK-LABEL: name: load_s32_gpr_unordered + ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0 + ; CHECK: [[T0:%[0-9]+]]:gpr32 = LDRWui [[COPY]], 0 :: (load release 4 from %ir.addr) + ; CHECK: %x0 = COPY [[T0]] + %0(p0) = COPY %x0 + %1(s32) = G_ATOMIC_LOAD %0 :: (load release 4 from %ir.addr) + %x0 = COPY %1(s32) +... + +--- +name: load_s32_gpr_monotonic +legalized: true +regBankSelected: true + +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } + +body: | + bb.0: + liveins: %x0 + + ; CHECK-LABEL: name: load_s32_gpr_monotonic + ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0 + ; CHECK: [[T0:%[0-9]+]]:gpr32 = LDRWui [[COPY]], 0 :: (load release 4 from %ir.addr) + ; CHECK: %x0 = COPY [[T0]] + %0(p0) = COPY %x0 + %1(s32) = G_ATOMIC_LOAD %0 :: (load release 4 from %ir.addr) + %x0 = COPY %1(s32) +... + +--- +name: load_s32_gpr_acquire +legalized: true +regBankSelected: true + +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } + +body: | + bb.0: + liveins: %x0 + + ; CHECK-LABEL: name: load_s32_gpr_acquire + ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0 + ; CHECK: [[T0:%[0-9]+]]:gpr32 = LDARW [[COPY]] :: (load acquire 4 from %ir.addr) + ; CHECK: %x0 = COPY [[T0]] + %0(p0) = COPY %x0 + %1(s32) = G_ATOMIC_LOAD %0 :: (load acquire 4 from %ir.addr) + %x0 = COPY %1(s32) +... + +--- +name: load_s32_gpr_release +legalized: true +regBankSelected: true + +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } + +body: | + bb.0: + liveins: %x0 + + ; CHECK-LABEL: name: load_s32_gpr_release + ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0 + ; CHECK: [[T0:%[0-9]+]]:gpr32 = LDRWui [[COPY]], 0 :: (load release 4 from %ir.addr) + ; CHECK: %x0 = COPY [[T0]] + %0(p0) = COPY %x0 + %1(s32) = G_ATOMIC_LOAD %0 :: (load release 4 from %ir.addr) + %x0 = COPY %1(s32) +... + +--- +name: load_s32_gpr_acq_rel +legalized: true +regBankSelected: true + +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } + +body: | + bb.0: + liveins: %x0 + + ; CHECK-LABEL: name: load_s32_gpr_acq_rel + ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0 + ; CHECK: [[T0:%[0-9]+]]:gpr32 = LDARW [[COPY]] :: (load acq_rel 4 from %ir.addr) + ; CHECK: %x0 = COPY [[T0]] + %0(p0) = COPY %x0 + %1(s32) = G_ATOMIC_LOAD %0 :: (load acq_rel 4 from %ir.addr) + %x0 = COPY %1(s32) +... + +--- +name: load_s32_gpr_seq_cst +legalized: true +regBankSelected: true + +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } + +body: | + bb.0: + liveins: %x0 + + ; CHECK-LABEL: name: load_s32_gpr_seq_cst + ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0 + ; CHECK: [[T0:%[0-9]+]]:gpr32 = LDARW [[COPY]] :: (load seq_cst 4 from %ir.addr) + ; CHECK: %x0 = COPY [[T0]] + %0(p0) = COPY %x0 + %1(s32) = G_ATOMIC_LOAD %0 :: (load seq_cst 4 from %ir.addr) + %x0 = COPY %1(s32) +... + + +--- +name: load_s64_gpr_unordered +legalized: true +regBankSelected: true + +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } + +body: | + bb.0: + liveins: %x0 + + ; CHECK-LABEL: name: load_s64_gpr_unordered + ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0 + ; CHECK: [[LDRXui:%[0-9]+]]:gpr64 = LDRXui [[COPY]], 0 :: (load release 8 from %ir.addr) + ; CHECK: %x0 = COPY [[LDRXui]] + %0(p0) = COPY %x0 + %1(s64) = G_ATOMIC_LOAD %0 :: (load release 8 from %ir.addr) + %x0 = COPY %1(s64) +... + +--- +name: load_s64_gpr_monotonic +legalized: true +regBankSelected: true + +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } + +body: | + bb.0: + liveins: %x0 + + ; CHECK-LABEL: name: load_s64_gpr_monotonic + ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0 + ; CHECK: [[LDRXui:%[0-9]+]]:gpr64 = LDRXui [[COPY]], 0 :: (load release 8 from %ir.addr) + ; CHECK: %x0 = COPY [[LDRXui]] + %0(p0) = COPY %x0 + %1(s64) = G_ATOMIC_LOAD %0 :: (load release 8 from %ir.addr) + %x0 = COPY %1(s64) +... + +--- +name: load_s64_gpr_acquire +legalized: true +regBankSelected: true + +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } + +body: | + bb.0: + liveins: %x0 + + ; CHECK-LABEL: name: load_s64_gpr_acquire + ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0 + ; CHECK: [[LDRXui:%[0-9]+]]:gpr64 = LDARX [[COPY]] :: (load acquire 8 from %ir.addr) + ; CHECK: %x0 = COPY [[LDRXui]] + %0(p0) = COPY %x0 + %1(s64) = G_ATOMIC_LOAD %0 :: (load acquire 8 from %ir.addr) + %x0 = COPY %1(s64) +... + +--- +name: load_s64_gpr_release +legalized: true +regBankSelected: true + +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } + +body: | + bb.0: + liveins: %x0 + + ; CHECK-LABEL: name: load_s64_gpr_release + ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0 + ; CHECK: [[LDRXui:%[0-9]+]]:gpr64 = LDRXui [[COPY]], 0 :: (load release 8 from %ir.addr) + ; CHECK: %x0 = COPY [[LDRXui]] + %0(p0) = COPY %x0 + %1(s64) = G_ATOMIC_LOAD %0 :: (load release 8 from %ir.addr) + %x0 = COPY %1(s64) +... + +--- +name: load_s64_gpr_acq_rel +legalized: true +regBankSelected: true + +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } + +body: | + bb.0: + liveins: %x0 + + ; CHECK-LABEL: name: load_s64_gpr_acq_rel + ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0 + ; CHECK: [[LDRXui:%[0-9]+]]:gpr64 = LDARX [[COPY]] :: (load acq_rel 8 from %ir.addr) + ; CHECK: %x0 = COPY [[LDRXui]] + %0(p0) = COPY %x0 + %1(s64) = G_ATOMIC_LOAD %0 :: (load acq_rel 8 from %ir.addr) + %x0 = COPY %1(s64) +... + +--- +name: load_s64_gpr_seq_cst +legalized: true +regBankSelected: true + +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } + +body: | + bb.0: + liveins: %x0 + + ; CHECK-LABEL: name: load_s64_gpr_seq_cst + ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0 + ; CHECK: [[LDRXui:%[0-9]+]]:gpr64 = LDARX [[COPY]] :: (load seq_cst 8 from %ir.addr) + ; CHECK: %x0 = COPY [[LDRXui]] + %0(p0) = COPY %x0 + %1(s64) = G_ATOMIC_LOAD %0 :: (load seq_cst 8 from %ir.addr) + %x0 = COPY %1(s64) +... + diff --git a/test/CodeGen/AArch64/GlobalISel/select-dbg-value.mir b/test/CodeGen/AArch64/GlobalISel/select-dbg-value.mir index af83be5c075ed..7396ae57f8fd6 100644 --- a/test/CodeGen/AArch64/GlobalISel/select-dbg-value.mir +++ b/test/CodeGen/AArch64/GlobalISel/select-dbg-value.mir @@ -46,11 +46,11 @@ body: | ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0 ; CHECK: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[COPY]], [[COPY]] ; CHECK: %w0 = COPY [[ADDWrr]] - ; CHECK: DBG_VALUE debug-use [[ADDWrr]], debug-use _, !7, !DIExpression(), debug-location !9 + ; CHECK: DBG_VALUE debug-use [[ADDWrr]], debug-use %noreg, !7, !DIExpression(), debug-location !9 %0:gpr(s32) = COPY %w0 %1:gpr(s32) = G_ADD %0, %0 %w0 = COPY %1(s32) - DBG_VALUE debug-use %1(s32), debug-use _, !7, !DIExpression(), debug-location !9 + DBG_VALUE debug-use %1(s32), debug-use %noreg, !7, !DIExpression(), debug-location !9 ... --- @@ -62,7 +62,7 @@ body: | liveins: %w0 ; CHECK-LABEL: name: test_dbg_value_dead ; CHECK-NOT: COPY - ; CHECK: DBG_VALUE debug-use _, debug-use _, !7, !DIExpression(), debug-location !9 + ; CHECK: DBG_VALUE debug-use %noreg, debug-use %noreg, !7, !DIExpression(), debug-location !9 %0:gpr(s32) = COPY %w0 - DBG_VALUE debug-use %0(s32), debug-use _, !7, !DIExpression(), debug-location !9 + DBG_VALUE debug-use %0(s32), debug-use %noreg, !7, !DIExpression(), debug-location !9 ... diff --git a/test/CodeGen/AArch64/GlobalISel/verify-regbankselected.mir b/test/CodeGen/AArch64/GlobalISel/verify-regbankselected.mir index 9a2f7f7e54f8c..7d0c9a37d17b1 100644 --- a/test/CodeGen/AArch64/GlobalISel/verify-regbankselected.mir +++ b/test/CodeGen/AArch64/GlobalISel/verify-regbankselected.mir @@ -9,8 +9,8 @@ ... --- # CHECK: *** Bad machine code: Generic virtual register must have a bank in a RegBankSelected function *** -# CHECK: instruction: %vreg0(s64) = COPY -# CHECK: operand 0: %vreg0 +# CHECK: instruction: %0(s64) = COPY +# CHECK: operand 0: %0 name: test regBankSelected: true registers: diff --git a/test/CodeGen/AArch64/GlobalISel/verify-selected.mir b/test/CodeGen/AArch64/GlobalISel/verify-selected.mir index 2149903d08a79..a182cf5317340 100644 --- a/test/CodeGen/AArch64/GlobalISel/verify-selected.mir +++ b/test/CodeGen/AArch64/GlobalISel/verify-selected.mir @@ -22,11 +22,11 @@ body: | %0 = COPY %x0 ; CHECK: *** Bad machine code: Unexpected generic instruction in a Selected function *** - ; CHECK: instruction: %vreg1 = G_ADD + ; CHECK: instruction: %1 = G_ADD %1 = G_ADD %0, %0 ; CHECK: *** Bad machine code: Generic virtual register invalid in a Selected function *** - ; CHECK: instruction: %vreg2(s64) = COPY - ; CHECK: operand 0: %vreg2 + ; CHECK: instruction: %2(s64) = COPY + ; CHECK: operand 0: %2 %2(s64) = COPY %x0 ... diff --git a/test/CodeGen/AArch64/aarch64-fix-cortex-a53-835769.ll b/test/CodeGen/AArch64/aarch64-fix-cortex-a53-835769.ll index 51c32b409db50..eafb4126807f8 100644 --- a/test/CodeGen/AArch64/aarch64-fix-cortex-a53-835769.ll +++ b/test/CodeGen/AArch64/aarch64-fix-cortex-a53-835769.ll @@ -508,12 +508,12 @@ block1: ; CHECK: ldr ; CHECK-NEXT: nop ; CHECK-NEXT: .Ltmp -; CHECK-NEXT: BB +; CHECK-NEXT: %bb. ; CHECK-NEXT: madd ; CHECK-NOWORKAROUND-LABEL: fall_through ; CHECK-NOWORKAROUND: ldr ; CHECK-NOWORKAROUND-NEXT: .Ltmp -; CHECK-NOWORKAROUND-NEXT: BB +; CHECK-NOWORKAROUND-NEXT: %bb. ; CHECK-NOWORKAROUND-NEXT: madd ; No checks for this, just check it doesn't crash diff --git a/test/CodeGen/AArch64/aarch64-stp-cluster.ll b/test/CodeGen/AArch64/aarch64-stp-cluster.ll index 25cf313b81e7a..c6bdbe4f03221 100644 --- a/test/CodeGen/AArch64/aarch64-stp-cluster.ll +++ b/test/CodeGen/AArch64/aarch64-stp-cluster.ll @@ -2,13 +2,13 @@ ; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a57 -verify-misched -debug-only=machine-scheduler -aarch64-enable-stp-suppress=false -o - 2>&1 > /dev/null | FileCheck %s ; CHECK: ********** MI Scheduling ********** -; CHECK-LABEL: stp_i64_scale:BB#0 +; CHECK-LABEL: stp_i64_scale:%bb.0 ; CHECK:Cluster ld/st SU(4) - SU(3) ; CHECK:Cluster ld/st SU(2) - SU(5) -; CHECK:SU(4): STRXui %vreg1, %vreg0, 1 -; CHECK:SU(3): STRXui %vreg1, %vreg0, 2 -; CHECK:SU(2): STRXui %vreg1, %vreg0, 3 -; CHECK:SU(5): STRXui %vreg1, %vreg0, 4 +; CHECK:SU(4): STRXui %1, %0, 1 +; CHECK:SU(3): STRXui %1, %0, 2 +; CHECK:SU(2): STRXui %1, %0, 3 +; CHECK:SU(5): STRXui %1, %0, 4 define i64 @stp_i64_scale(i64* nocapture %P, i64 %v) { entry: %arrayidx = getelementptr inbounds i64, i64* %P, i64 3 @@ -23,13 +23,13 @@ entry: } ; CHECK: ********** MI Scheduling ********** -; CHECK-LABEL: stp_i32_scale:BB#0 +; CHECK-LABEL: stp_i32_scale:%bb.0 ; CHECK:Cluster ld/st SU(4) - SU(3) ; CHECK:Cluster ld/st SU(2) - SU(5) -; CHECK:SU(4): STRWui %vreg1, %vreg0, 1 -; CHECK:SU(3): STRWui %vreg1, %vreg0, 2 -; CHECK:SU(2): STRWui %vreg1, %vreg0, 3 -; CHECK:SU(5): STRWui %vreg1, %vreg0, 4 +; CHECK:SU(4): STRWui %1, %0, 1 +; CHECK:SU(3): STRWui %1, %0, 2 +; CHECK:SU(2): STRWui %1, %0, 3 +; CHECK:SU(5): STRWui %1, %0, 4 define i32 @stp_i32_scale(i32* nocapture %P, i32 %v) { entry: %arrayidx = getelementptr inbounds i32, i32* %P, i32 3 @@ -44,13 +44,13 @@ entry: } ; CHECK:********** MI Scheduling ********** -; CHECK-LABEL:stp_i64_unscale:BB#0 entry +; CHECK-LABEL:stp_i64_unscale:%bb.0 entry ; CHECK:Cluster ld/st SU(5) - SU(2) ; CHECK:Cluster ld/st SU(4) - SU(3) -; CHECK:SU(5): STURXi %vreg1, %vreg0, -32 -; CHECK:SU(2): STURXi %vreg1, %vreg0, -24 -; CHECK:SU(4): STURXi %vreg1, %vreg0, -16 -; CHECK:SU(3): STURXi %vreg1, %vreg0, -8 +; CHECK:SU(5): STURXi %1, %0, -32 +; CHECK:SU(2): STURXi %1, %0, -24 +; CHECK:SU(4): STURXi %1, %0, -16 +; CHECK:SU(3): STURXi %1, %0, -8 define void @stp_i64_unscale(i64* nocapture %P, i64 %v) #0 { entry: %arrayidx = getelementptr inbounds i64, i64* %P, i64 -3 @@ -65,13 +65,13 @@ entry: } ; CHECK:********** MI Scheduling ********** -; CHECK-LABEL:stp_i32_unscale:BB#0 entry +; CHECK-LABEL:stp_i32_unscale:%bb.0 entry ; CHECK:Cluster ld/st SU(5) - SU(2) ; CHECK:Cluster ld/st SU(4) - SU(3) -; CHECK:SU(5): STURWi %vreg1, %vreg0, -16 -; CHECK:SU(2): STURWi %vreg1, %vreg0, -12 -; CHECK:SU(4): STURWi %vreg1, %vreg0, -8 -; CHECK:SU(3): STURWi %vreg1, %vreg0, -4 +; CHECK:SU(5): STURWi %1, %0, -16 +; CHECK:SU(2): STURWi %1, %0, -12 +; CHECK:SU(4): STURWi %1, %0, -8 +; CHECK:SU(3): STURWi %1, %0, -4 define void @stp_i32_unscale(i32* nocapture %P, i32 %v) #0 { entry: %arrayidx = getelementptr inbounds i32, i32* %P, i32 -3 @@ -86,13 +86,13 @@ entry: } ; CHECK:********** MI Scheduling ********** -; CHECK-LABEL:stp_double:BB#0 +; CHECK-LABEL:stp_double:%bb.0 ; CHECK:Cluster ld/st SU(3) - SU(4) ; CHECK:Cluster ld/st SU(2) - SU(5) -; CHECK:SU(3): STRDui %vreg1, %vreg0, 1 -; CHECK:SU(4): STRDui %vreg1, %vreg0, 2 -; CHECK:SU(2): STRDui %vreg1, %vreg0, 3 -; CHECK:SU(5): STRDui %vreg1, %vreg0, 4 +; CHECK:SU(3): STRDui %1, %0, 1 +; CHECK:SU(4): STRDui %1, %0, 2 +; CHECK:SU(2): STRDui %1, %0, 3 +; CHECK:SU(5): STRDui %1, %0, 4 define void @stp_double(double* nocapture %P, double %v) { entry: %arrayidx = getelementptr inbounds double, double* %P, i64 3 @@ -107,13 +107,13 @@ entry: } ; CHECK:********** MI Scheduling ********** -; CHECK-LABEL:stp_float:BB#0 +; CHECK-LABEL:stp_float:%bb.0 ; CHECK:Cluster ld/st SU(3) - SU(4) ; CHECK:Cluster ld/st SU(2) - SU(5) -; CHECK:SU(3): STRSui %vreg1, %vreg0, 1 -; CHECK:SU(4): STRSui %vreg1, %vreg0, 2 -; CHECK:SU(2): STRSui %vreg1, %vreg0, 3 -; CHECK:SU(5): STRSui %vreg1, %vreg0, 4 +; CHECK:SU(3): STRSui %1, %0, 1 +; CHECK:SU(4): STRSui %1, %0, 2 +; CHECK:SU(2): STRSui %1, %0, 3 +; CHECK:SU(5): STRSui %1, %0, 4 define void @stp_float(float* nocapture %P, float %v) { entry: %arrayidx = getelementptr inbounds float, float* %P, i64 3 @@ -128,12 +128,12 @@ entry: } ; CHECK: ********** MI Scheduling ********** -; CHECK-LABEL: stp_volatile:BB#0 +; CHECK-LABEL: stp_volatile:%bb.0 ; CHECK-NOT: Cluster ld/st -; CHECK:SU(2): STRXui %vreg1, %vreg0, 3; mem:Volatile -; CHECK:SU(3): STRXui %vreg1, %vreg0, 2; mem:Volatile -; CHECK:SU(4): STRXui %vreg1, %vreg0, 1; mem:Volatile -; CHECK:SU(5): STRXui %vreg1, %vreg0, 4; mem:Volatile +; CHECK:SU(2): STRXui %1, %0, 3; mem:Volatile +; CHECK:SU(3): STRXui %1, %0, 2; mem:Volatile +; CHECK:SU(4): STRXui %1, %0, 1; mem:Volatile +; CHECK:SU(5): STRXui %1, %0, 4; mem:Volatile define i64 @stp_volatile(i64* nocapture %P, i64 %v) { entry: %arrayidx = getelementptr inbounds i64, i64* %P, i64 3 diff --git a/test/CodeGen/AArch64/analyze-branch.ll b/test/CodeGen/AArch64/analyze-branch.ll index 932cd75052c15..4f902ef4fc831 100644 --- a/test/CodeGen/AArch64/analyze-branch.ll +++ b/test/CodeGen/AArch64/analyze-branch.ll @@ -18,7 +18,7 @@ define void @test_Bcc_fallthrough_taken(i32 %in) nounwind { ; CHECK: cmp {{w[0-9]+}}, #42 ; CHECK: b.ne [[FALSE:.LBB[0-9]+_[0-9]+]] -; CHECK-NEXT: // BB# +; CHECK-NEXT: // %bb. ; CHECK-NEXT: bl test_true ; CHECK: [[FALSE]]: @@ -41,7 +41,7 @@ define void @test_Bcc_fallthrough_nottaken(i32 %in) nounwind { ; CHECK: cmp {{w[0-9]+}}, #42 ; CHECK: b.eq [[TRUE:.LBB[0-9]+_[0-9]+]] -; CHECK-NEXT: // BB# +; CHECK-NEXT: // %bb. ; CHECK-NEXT: bl test_false ; CHECK: [[TRUE]]: @@ -62,7 +62,7 @@ define void @test_CBZ_fallthrough_taken(i32 %in) nounwind { br i1 %tst, label %true, label %false, !prof !0 ; CHECK: cbnz {{w[0-9]+}}, [[FALSE:.LBB[0-9]+_[0-9]+]] -; CHECK-NEXT: // BB# +; CHECK-NEXT: // %bb. ; CHECK-NEXT: bl test_true ; CHECK: [[FALSE]]: @@ -83,7 +83,7 @@ define void @test_CBZ_fallthrough_nottaken(i64 %in) nounwind { br i1 %tst, label %true, label %false, !prof !1 ; CHECK: cbz {{x[0-9]+}}, [[TRUE:.LBB[0-9]+_[0-9]+]] -; CHECK-NEXT: // BB# +; CHECK-NEXT: // %bb. ; CHECK-NEXT: bl test_false ; CHECK: [[TRUE]]: @@ -104,7 +104,7 @@ define void @test_CBNZ_fallthrough_taken(i32 %in) nounwind { br i1 %tst, label %true, label %false, !prof !0 ; CHECK: cbz {{w[0-9]+}}, [[FALSE:.LBB[0-9]+_[0-9]+]] -; CHECK-NEXT: // BB# +; CHECK-NEXT: // %bb. ; CHECK-NEXT: bl test_true ; CHECK: [[FALSE]]: @@ -125,7 +125,7 @@ define void @test_CBNZ_fallthrough_nottaken(i64 %in) nounwind { br i1 %tst, label %true, label %false, !prof !1 ; CHECK: cbnz {{x[0-9]+}}, [[TRUE:.LBB[0-9]+_[0-9]+]] -; CHECK-NEXT: // BB# +; CHECK-NEXT: // %bb. ; CHECK-NEXT: bl test_false ; CHECK: [[TRUE]]: @@ -147,7 +147,7 @@ define void @test_TBZ_fallthrough_taken(i32 %in) nounwind { br i1 %tst, label %true, label %false, !prof !0 ; CHECK: tbnz {{w[0-9]+}}, #15, [[FALSE:.LBB[0-9]+_[0-9]+]] -; CHECK-NEXT: // BB# +; CHECK-NEXT: // %bb. ; CHECK-NEXT: bl test_true ; CHECK: [[FALSE]]: @@ -169,7 +169,7 @@ define void @test_TBZ_fallthrough_nottaken(i64 %in) nounwind { br i1 %tst, label %true, label %false, !prof !1 ; CHECK: tbz {{[wx][0-9]+}}, #15, [[TRUE:.LBB[0-9]+_[0-9]+]] -; CHECK-NEXT: // BB# +; CHECK-NEXT: // %bb. ; CHECK-NEXT: bl test_false ; CHECK: [[TRUE]]: @@ -192,7 +192,7 @@ define void @test_TBNZ_fallthrough_taken(i32 %in) nounwind { br i1 %tst, label %true, label %false, !prof !0 ; CHECK: tbz {{w[0-9]+}}, #15, [[FALSE:.LBB[0-9]+_[0-9]+]] -; CHECK-NEXT: // BB# +; CHECK-NEXT: // %bb. ; CHECK-NEXT: bl test_true ; CHECK: [[FALSE]]: @@ -214,7 +214,7 @@ define void @test_TBNZ_fallthrough_nottaken(i64 %in) nounwind { br i1 %tst, label %true, label %false, !prof !1 ; CHECK: tbnz {{[wx][0-9]+}}, #15, [[TRUE:.LBB[0-9]+_[0-9]+]] -; CHECK-NEXT: // BB# +; CHECK-NEXT: // %bb. ; CHECK-NEXT: bl test_false ; CHECK: [[TRUE]]: diff --git a/test/CodeGen/AArch64/arm64-ccmp.ll b/test/CodeGen/AArch64/arm64-ccmp.ll index a910585e7f5db..b18e638a3a947 100644 --- a/test/CodeGen/AArch64/arm64-ccmp.ll +++ b/test/CodeGen/AArch64/arm64-ccmp.ll @@ -132,6 +132,7 @@ if.end: ; Floating point compare. ; CHECK: single_fcmp +; CHECK: ; %bb. ; CHECK: cmp ; CHECK-NOT: b. ; CHECK: fccmp {{.*}}, #8, ge @@ -448,7 +449,7 @@ define i32 @select_noccmp3(i32 %v0, i32 %v1, i32 %v2) { ; Test the IR CCs that expand to two cond codes. ; CHECK-LABEL: select_and_olt_one: -; CHECK-LABEL: ; BB#0: +; CHECK-LABEL: ; %bb.0: ; CHECK-NEXT: fcmp d0, d1 ; CHECK-NEXT: fccmp d2, d3, #4, mi ; CHECK-NEXT: fccmp d2, d3, #1, ne @@ -463,7 +464,7 @@ define i32 @select_and_olt_one(double %v0, double %v1, double %v2, double %v3, i } ; CHECK-LABEL: select_and_one_olt: -; CHECK-LABEL: ; BB#0: +; CHECK-LABEL: ; %bb.0: ; CHECK-NEXT: fcmp d0, d1 ; CHECK-NEXT: fccmp d0, d1, #1, ne ; CHECK-NEXT: fccmp d2, d3, #0, vc @@ -478,7 +479,7 @@ define i32 @select_and_one_olt(double %v0, double %v1, double %v2, double %v3, i } ; CHECK-LABEL: select_and_olt_ueq: -; CHECK-LABEL: ; BB#0: +; CHECK-LABEL: ; %bb.0: ; CHECK-NEXT: fcmp d0, d1 ; CHECK-NEXT: fccmp d2, d3, #0, mi ; CHECK-NEXT: fccmp d2, d3, #8, le @@ -493,7 +494,7 @@ define i32 @select_and_olt_ueq(double %v0, double %v1, double %v2, double %v3, i } ; CHECK-LABEL: select_and_ueq_olt: -; CHECK-LABEL: ; BB#0: +; CHECK-LABEL: ; %bb.0: ; CHECK-NEXT: fcmp d0, d1 ; CHECK-NEXT: fccmp d0, d1, #8, le ; CHECK-NEXT: fccmp d2, d3, #0, pl @@ -508,7 +509,7 @@ define i32 @select_and_ueq_olt(double %v0, double %v1, double %v2, double %v3, i } ; CHECK-LABEL: select_or_olt_one: -; CHECK-LABEL: ; BB#0: +; CHECK-LABEL: ; %bb.0: ; CHECK-NEXT: fcmp d0, d1 ; CHECK-NEXT: fccmp d2, d3, #0, pl ; CHECK-NEXT: fccmp d2, d3, #8, le @@ -523,7 +524,7 @@ define i32 @select_or_olt_one(double %v0, double %v1, double %v2, double %v3, i3 } ; CHECK-LABEL: select_or_one_olt: -; CHECK-LABEL: ; BB#0: +; CHECK-LABEL: ; %bb.0: ; CHECK-NEXT: fcmp d0, d1 ; CHECK-NEXT: fccmp d0, d1, #1, ne ; CHECK-NEXT: fccmp d2, d3, #8, vs @@ -538,7 +539,7 @@ define i32 @select_or_one_olt(double %v0, double %v1, double %v2, double %v3, i3 } ; CHECK-LABEL: select_or_olt_ueq: -; CHECK-LABEL: ; BB#0: +; CHECK-LABEL: ; %bb.0: ; CHECK-NEXT: fcmp d0, d1 ; CHECK-NEXT: fccmp d2, d3, #4, pl ; CHECK-NEXT: fccmp d2, d3, #1, ne @@ -553,7 +554,7 @@ define i32 @select_or_olt_ueq(double %v0, double %v1, double %v2, double %v3, i3 } ; CHECK-LABEL: select_or_ueq_olt: -; CHECK-LABEL: ; BB#0: +; CHECK-LABEL: ; %bb.0: ; CHECK-NEXT: fcmp d0, d1 ; CHECK-NEXT: fccmp d0, d1, #8, le ; CHECK-NEXT: fccmp d2, d3, #8, mi @@ -568,7 +569,7 @@ define i32 @select_or_ueq_olt(double %v0, double %v1, double %v2, double %v3, i3 } ; CHECK-LABEL: select_or_olt_ogt_ueq: -; CHECK-LABEL: ; BB#0: +; CHECK-LABEL: ; %bb.0: ; CHECK-NEXT: fcmp d0, d1 ; CHECK-NEXT: fccmp d2, d3, #0, pl ; CHECK-NEXT: fccmp d4, d5, #4, le @@ -586,7 +587,7 @@ define i32 @select_or_olt_ogt_ueq(double %v0, double %v1, double %v2, double %v3 } ; CHECK-LABEL: select_or_olt_ueq_ogt: -; CHECK-LABEL: ; BB#0: +; CHECK-LABEL: ; %bb.0: ; CHECK-NEXT: fcmp d0, d1 ; CHECK-NEXT: fccmp d2, d3, #4, pl ; CHECK-NEXT: fccmp d2, d3, #1, ne @@ -606,7 +607,7 @@ define i32 @select_or_olt_ueq_ogt(double %v0, double %v1, double %v2, double %v3 ; Verify that we correctly promote f16. ; CHECK-LABEL: half_select_and_olt_oge: -; CHECK-LABEL: ; BB#0: +; CHECK-LABEL: ; %bb.0: ; CHECK-DAG: fcvt [[S0:s[0-9]+]], h0 ; CHECK-DAG: fcvt [[S1:s[0-9]+]], h1 ; CHECK-NEXT: fcmp [[S0]], [[S1]] @@ -624,7 +625,7 @@ define i32 @half_select_and_olt_oge(half %v0, half %v1, half %v2, half %v3, i32 } ; CHECK-LABEL: half_select_and_olt_one: -; CHECK-LABEL: ; BB#0: +; CHECK-LABEL: ; %bb.0: ; CHECK-DAG: fcvt [[S0:s[0-9]+]], h0 ; CHECK-DAG: fcvt [[S1:s[0-9]+]], h1 ; CHECK-NEXT: fcmp [[S0]], [[S1]] diff --git a/test/CodeGen/AArch64/arm64-complex-ret.ll b/test/CodeGen/AArch64/arm64-complex-ret.ll index b4a38544ca1a6..250edac553c73 100644 --- a/test/CodeGen/AArch64/arm64-complex-ret.ll +++ b/test/CodeGen/AArch64/arm64-complex-ret.ll @@ -2,7 +2,6 @@ define { i192, i192, i21, i192 } @foo(i192) { ; CHECK-LABEL: foo: -; CHECK-DAG: str xzr, [x8, #16] -; CHECK-DAG: str q0, [x8] +; CHECK: stp xzr, xzr, [x8] ret { i192, i192, i21, i192 } {i192 0, i192 1, i21 2, i192 3} } diff --git a/test/CodeGen/AArch64/arm64-fast-isel-rem.ll b/test/CodeGen/AArch64/arm64-fast-isel-rem.ll index 05aa96997b57b..58f414432ac17 100644 --- a/test/CodeGen/AArch64/arm64-fast-isel-rem.ll +++ b/test/CodeGen/AArch64/arm64-fast-isel-rem.ll @@ -4,9 +4,9 @@ ; CHECK-SSA-LABEL: Machine code for function t1 -; CHECK-SSA: [[QUOTREG:%vreg[0-9]+]] = SDIVWr +; CHECK-SSA: [[QUOTREG:%[0-9]+]] = SDIVWr ; CHECK-SSA-NOT: [[QUOTREG]] = -; CHECK-SSA: {{%vreg[0-9]+}} = MSUBWrrr [[QUOTREG]] +; CHECK-SSA: {{%[0-9]+}} = MSUBWrrr [[QUOTREG]] ; CHECK-SSA-LABEL: Machine code for function t2 diff --git a/test/CodeGen/AArch64/arm64-fp128.ll b/test/CodeGen/AArch64/arm64-fp128.ll index 2ae0da2d89d10..3561d8fcdff9f 100644 --- a/test/CodeGen/AArch64/arm64-fp128.ll +++ b/test/CodeGen/AArch64/arm64-fp128.ll @@ -195,7 +195,7 @@ define i32 @test_br_cc() { iftrue: ret i32 42 -; CHECK-NEXT: BB# +; CHECK-NEXT: %bb. ; CHECK-NEXT: mov w0, #42 ; CHECK: ret iffalse: @@ -211,7 +211,7 @@ define void @test_select(i1 %cond, fp128 %lhs, fp128 %rhs) { store fp128 %val, fp128* @lhs, align 16 ; CHECK: tst w0, #0x1 ; CHECK-NEXT: b.eq [[IFFALSE:.LBB[0-9]+_[0-9]+]] -; CHECK-NEXT: BB# +; CHECK-NEXT: %bb. ; CHECK-NEXT: mov v[[VAL:[0-9]+]].16b, v0.16b ; CHECK-NEXT: [[IFFALSE]]: ; CHECK: str q[[VAL]], [{{x[0-9]+}}, :lo12:lhs] diff --git a/test/CodeGen/AArch64/arm64-icmp-opt.ll b/test/CodeGen/AArch64/arm64-icmp-opt.ll index 12eae0e88fbee..1ed5c5ee135c2 100644 --- a/test/CodeGen/AArch64/arm64-icmp-opt.ll +++ b/test/CodeGen/AArch64/arm64-icmp-opt.ll @@ -7,7 +7,7 @@ define i32 @t1(i64 %a) { ; CHECK-LABEL: t1: -; CHECK: // BB#0: +; CHECK: // %bb.0: ; CHECK-NEXT: lsr x8, x0, #63 ; CHECK-NEXT: eor w0, w8, #0x1 ; CHECK-NEXT: ret diff --git a/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll b/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll index cdbadfe51f0cc..b63e739f577d2 100644 --- a/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll +++ b/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll @@ -6176,7 +6176,7 @@ define <2 x double> @test_v2f64_post_reg_ld1lane(double* %bar, double** %ptr, i6 ; Check for dependencies between the vector and the scalar load. define <4 x float> @test_v4f32_post_reg_ld1lane_dep_vec_on_load(float* %bar, float** %ptr, i64 %inc, <4 x float>* %dep_ptr_1, <4 x float>* %dep_ptr_2, <4 x float> %vec) { ; CHECK-LABEL: test_v4f32_post_reg_ld1lane_dep_vec_on_load: -; CHECK: BB#0: +; CHECK: %bb.0: ; CHECK-NEXT: ldr s[[LD:[0-9]+]], [x0] ; CHECK-NEXT: str q0, [x3] ; CHECK-NEXT: ldr q0, [x4] diff --git a/test/CodeGen/AArch64/arm64-ldp-cluster.ll b/test/CodeGen/AArch64/arm64-ldp-cluster.ll index 64e535ca74990..370db233fcb57 100644 --- a/test/CodeGen/AArch64/arm64-ldp-cluster.ll +++ b/test/CodeGen/AArch64/arm64-ldp-cluster.ll @@ -4,15 +4,15 @@ ; Test ldr clustering. ; CHECK: ********** MI Scheduling ********** -; CHECK-LABEL: ldr_int:BB#0 +; CHECK-LABEL: ldr_int:%bb.0 ; CHECK: Cluster ld/st SU(1) - SU(2) -; CHECK: SU(1): %vreg{{[0-9]+}} = LDRWui -; CHECK: SU(2): %vreg{{[0-9]+}} = LDRWui +; CHECK: SU(1): %{{[0-9]+}} = LDRWui +; CHECK: SU(2): %{{[0-9]+}} = LDRWui ; EXYNOS: ********** MI Scheduling ********** -; EXYNOS-LABEL: ldr_int:BB#0 +; EXYNOS-LABEL: ldr_int:%bb.0 ; EXYNOS: Cluster ld/st SU(1) - SU(2) -; EXYNOS: SU(1): %vreg{{[0-9]+}} = LDRWui -; EXYNOS: SU(2): %vreg{{[0-9]+}} = LDRWui +; EXYNOS: SU(1): %{{[0-9]+}} = LDRWui +; EXYNOS: SU(2): %{{[0-9]+}} = LDRWui define i32 @ldr_int(i32* %a) nounwind { %p1 = getelementptr inbounds i32, i32* %a, i32 1 %tmp1 = load i32, i32* %p1, align 2 @@ -24,15 +24,15 @@ define i32 @ldr_int(i32* %a) nounwind { ; Test ldpsw clustering ; CHECK: ********** MI Scheduling ********** -; CHECK-LABEL: ldp_sext_int:BB#0 +; CHECK-LABEL: ldp_sext_int:%bb.0 ; CHECK: Cluster ld/st SU(1) - SU(2) -; CHECK: SU(1): %vreg{{[0-9]+}} = LDRSWui -; CHECK: SU(2): %vreg{{[0-9]+}} = LDRSWui +; CHECK: SU(1): %{{[0-9]+}} = LDRSWui +; CHECK: SU(2): %{{[0-9]+}} = LDRSWui ; EXYNOS: ********** MI Scheduling ********** -; EXYNOS-LABEL: ldp_sext_int:BB#0 +; EXYNOS-LABEL: ldp_sext_int:%bb.0 ; EXYNOS: Cluster ld/st SU(1) - SU(2) -; EXYNOS: SU(1): %vreg{{[0-9]+}} = LDRSWui -; EXYNOS: SU(2): %vreg{{[0-9]+}} = LDRSWui +; EXYNOS: SU(1): %{{[0-9]+}} = LDRSWui +; EXYNOS: SU(2): %{{[0-9]+}} = LDRSWui define i64 @ldp_sext_int(i32* %p) nounwind { %tmp = load i32, i32* %p, align 4 %add.ptr = getelementptr inbounds i32, i32* %p, i64 1 @@ -45,15 +45,15 @@ define i64 @ldp_sext_int(i32* %p) nounwind { ; Test ldur clustering. ; CHECK: ********** MI Scheduling ********** -; CHECK-LABEL: ldur_int:BB#0 +; CHECK-LABEL: ldur_int:%bb.0 ; CHECK: Cluster ld/st SU(2) - SU(1) -; CHECK: SU(1): %vreg{{[0-9]+}} = LDURWi -; CHECK: SU(2): %vreg{{[0-9]+}} = LDURWi +; CHECK: SU(1): %{{[0-9]+}} = LDURWi +; CHECK: SU(2): %{{[0-9]+}} = LDURWi ; EXYNOS: ********** MI Scheduling ********** -; EXYNOS-LABEL: ldur_int:BB#0 +; EXYNOS-LABEL: ldur_int:%bb.0 ; EXYNOS: Cluster ld/st SU(2) - SU(1) -; EXYNOS: SU(1): %vreg{{[0-9]+}} = LDURWi -; EXYNOS: SU(2): %vreg{{[0-9]+}} = LDURWi +; EXYNOS: SU(1): %{{[0-9]+}} = LDURWi +; EXYNOS: SU(2): %{{[0-9]+}} = LDURWi define i32 @ldur_int(i32* %a) nounwind { %p1 = getelementptr inbounds i32, i32* %a, i32 -1 %tmp1 = load i32, i32* %p1, align 2 @@ -65,15 +65,15 @@ define i32 @ldur_int(i32* %a) nounwind { ; Test sext + zext clustering. ; CHECK: ********** MI Scheduling ********** -; CHECK-LABEL: ldp_half_sext_zext_int:BB#0 +; CHECK-LABEL: ldp_half_sext_zext_int:%bb.0 ; CHECK: Cluster ld/st SU(3) - SU(4) -; CHECK: SU(3): %vreg{{[0-9]+}} = LDRSWui -; CHECK: SU(4): %vreg{{[0-9]+}}:sub_32 = LDRWui +; CHECK: SU(3): %{{[0-9]+}} = LDRSWui +; CHECK: SU(4): %{{[0-9]+}}:sub_32 = LDRWui ; EXYNOS: ********** MI Scheduling ********** -; EXYNOS-LABEL: ldp_half_sext_zext_int:BB#0 +; EXYNOS-LABEL: ldp_half_sext_zext_int:%bb.0 ; EXYNOS: Cluster ld/st SU(3) - SU(4) -; EXYNOS: SU(3): %vreg{{[0-9]+}} = LDRSWui -; EXYNOS: SU(4): %vreg{{[0-9]+}}:sub_32 = LDRWui +; EXYNOS: SU(3): %{{[0-9]+}} = LDRSWui +; EXYNOS: SU(4): %{{[0-9]+}}:sub_32 = LDRWui define i64 @ldp_half_sext_zext_int(i64* %q, i32* %p) nounwind { %tmp0 = load i64, i64* %q, align 4 %tmp = load i32, i32* %p, align 4 @@ -88,15 +88,15 @@ define i64 @ldp_half_sext_zext_int(i64* %q, i32* %p) nounwind { ; Test zext + sext clustering. ; CHECK: ********** MI Scheduling ********** -; CHECK-LABEL: ldp_half_zext_sext_int:BB#0 +; CHECK-LABEL: ldp_half_zext_sext_int:%bb.0 ; CHECK: Cluster ld/st SU(3) - SU(4) -; CHECK: SU(3): %vreg{{[0-9]+}}:sub_32 = LDRWui -; CHECK: SU(4): %vreg{{[0-9]+}} = LDRSWui +; CHECK: SU(3): %{{[0-9]+}}:sub_32 = LDRWui +; CHECK: SU(4): %{{[0-9]+}} = LDRSWui ; EXYNOS: ********** MI Scheduling ********** -; EXYNOS-LABEL: ldp_half_zext_sext_int:BB#0 +; EXYNOS-LABEL: ldp_half_zext_sext_int:%bb.0 ; EXYNOS: Cluster ld/st SU(3) - SU(4) -; EXYNOS: SU(3): %vreg{{[0-9]+}}:sub_32 = LDRWui -; EXYNOS: SU(4): %vreg{{[0-9]+}} = LDRSWui +; EXYNOS: SU(3): %{{[0-9]+}}:sub_32 = LDRWui +; EXYNOS: SU(4): %{{[0-9]+}} = LDRSWui define i64 @ldp_half_zext_sext_int(i64* %q, i32* %p) nounwind { %tmp0 = load i64, i64* %q, align 4 %tmp = load i32, i32* %p, align 4 @@ -111,15 +111,15 @@ define i64 @ldp_half_zext_sext_int(i64* %q, i32* %p) nounwind { ; Verify we don't cluster volatile loads. ; CHECK: ********** MI Scheduling ********** -; CHECK-LABEL: ldr_int_volatile:BB#0 +; CHECK-LABEL: ldr_int_volatile:%bb.0 ; CHECK-NOT: Cluster ld/st -; CHECK: SU(1): %vreg{{[0-9]+}} = LDRWui -; CHECK: SU(2): %vreg{{[0-9]+}} = LDRWui +; CHECK: SU(1): %{{[0-9]+}} = LDRWui +; CHECK: SU(2): %{{[0-9]+}} = LDRWui ; EXYNOS: ********** MI Scheduling ********** -; EXYNOS-LABEL: ldr_int_volatile:BB#0 +; EXYNOS-LABEL: ldr_int_volatile:%bb.0 ; EXYNOS-NOT: Cluster ld/st -; EXYNOS: SU(1): %vreg{{[0-9]+}} = LDRWui -; EXYNOS: SU(2): %vreg{{[0-9]+}} = LDRWui +; EXYNOS: SU(1): %{{[0-9]+}} = LDRWui +; EXYNOS: SU(2): %{{[0-9]+}} = LDRWui define i32 @ldr_int_volatile(i32* %a) nounwind { %p1 = getelementptr inbounds i32, i32* %a, i32 1 %tmp1 = load volatile i32, i32* %p1, align 2 @@ -131,12 +131,12 @@ define i32 @ldr_int_volatile(i32* %a) nounwind { ; Test ldq clustering (no clustering for Exynos). ; CHECK: ********** MI Scheduling ********** -; CHECK-LABEL: ldq_cluster:BB#0 +; CHECK-LABEL: ldq_cluster:%bb.0 ; CHECK: Cluster ld/st SU(1) - SU(3) -; CHECK: SU(1): %vreg{{[0-9]+}} = LDRQui -; CHECK: SU(3): %vreg{{[0-9]+}} = LDRQui +; CHECK: SU(1): %{{[0-9]+}} = LDRQui +; CHECK: SU(3): %{{[0-9]+}} = LDRQui ; EXYNOS: ********** MI Scheduling ********** -; EXYNOS-LABEL: ldq_cluster:BB#0 +; EXYNOS-LABEL: ldq_cluster:%bb.0 ; EXYNOS-NOT: Cluster ld/st define <2 x i64> @ldq_cluster(i64* %p) { %a1 = bitcast i64* %p to <2 x i64>* diff --git a/test/CodeGen/AArch64/arm64-misched-basic-A53.ll b/test/CodeGen/AArch64/arm64-misched-basic-A53.ll index 307d1ec1aa8cc..07df9cb32dbac 100644 --- a/test/CodeGen/AArch64/arm64-misched-basic-A53.ll +++ b/test/CodeGen/AArch64/arm64-misched-basic-A53.ll @@ -8,7 +8,7 @@ ; ; CHECK: ********** MI Scheduling ********** ; CHECK: main -; CHECK: *** Final schedule for BB#2 *** +; CHECK: *** Final schedule for %bb.2 *** ; CHECK: MADDWrrr ; CHECK: ADDWri ; CHECK: ********** INTERVALS ********** @@ -83,8 +83,8 @@ for.end: ; preds = %for.cond ; after it, this test checks to make sure there are more than one. ; ; CHECK: ********** MI Scheduling ********** -; CHECK: neon4xfloat:BB#0 -; CHECK: *** Final schedule for BB#0 *** +; CHECK: neon4xfloat:%bb.0 +; CHECK: *** Final schedule for %bb.0 *** ; CHECK: FDIVv4f32 ; CHECK: FADDv4f32 ; CHECK: FADDv4f32 @@ -130,7 +130,7 @@ declare { <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld2.v16i8.p0i8(i8*) ; are otherwise ready are jammed in the pending queue. ; CHECK: ********** MI Scheduling ********** ; CHECK: testResourceConflict -; CHECK: *** Final schedule for BB#0 *** +; CHECK: *** Final schedule for %bb.0 *** ; CHECK: BRK ; CHECK: ********** INTERVALS ********** define void @testResourceConflict(float* %ptr) { @@ -178,7 +178,7 @@ declare void @llvm.trap() ; Resource contention on LDST. ; CHECK: ********** MI Scheduling ********** ; CHECK: testLdStConflict -; CHECK: *** Final schedule for BB#1 *** +; CHECK: *** Final schedule for %bb.1 *** ; CHECK: LD4Fourv2d ; CHECK: STRQui ; CHECK: ********** INTERVALS ********** diff --git a/test/CodeGen/AArch64/arm64-misched-basic-A57.ll b/test/CodeGen/AArch64/arm64-misched-basic-A57.ll index 82ba18ce72ca5..711d2f7397b01 100644 --- a/test/CodeGen/AArch64/arm64-misched-basic-A57.ll +++ b/test/CodeGen/AArch64/arm64-misched-basic-A57.ll @@ -8,10 +8,10 @@ ; ; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a57 -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s ; CHECK: ********** MI Scheduling ********** -; CHECK: main:BB#2 +; CHECK: main:%bb.2 ; CHECK: LDR ; CHECK: Latency : 4 -; CHECK: *** Final schedule for BB#2 *** +; CHECK: *** Final schedule for %bb.2 *** ; CHECK: LDR ; CHECK: LDR ; CHECK-NOT: LDR diff --git a/test/CodeGen/AArch64/arm64-misched-forwarding-A53.ll b/test/CodeGen/AArch64/arm64-misched-forwarding-A53.ll index ad4feef7280f2..b4e07fe76c111 100644 --- a/test/CodeGen/AArch64/arm64-misched-forwarding-A53.ll +++ b/test/CodeGen/AArch64/arm64-misched-forwarding-A53.ll @@ -6,10 +6,10 @@ ; ; CHECK: ********** MI Scheduling ********** ; CHECK: shiftable -; CHECK: SU(2): %vreg2 = SUBXri %vreg1, 20, 0 +; CHECK: SU(2): %2 = SUBXri %1, 20, 0 ; CHECK: Successors: -; CHECK-NEXT: SU(4): Data Latency=1 Reg=%vreg2 -; CHECK-NEXT: SU(3): Data Latency=2 Reg=%vreg2 +; CHECK-NEXT: SU(4): Data Latency=1 Reg=%2 +; CHECK-NEXT: SU(3): Data Latency=2 Reg=%2 ; CHECK: ********** INTERVALS ********** define i64 @shiftable(i64 %A, i64 %B) { %tmp0 = sub i64 %B, 20 diff --git a/test/CodeGen/AArch64/arm64-misched-memdep-bug.ll b/test/CodeGen/AArch64/arm64-misched-memdep-bug.ll index 1b102e63569d1..8c81cf43e684a 100644 --- a/test/CodeGen/AArch64/arm64-misched-memdep-bug.ll +++ b/test/CodeGen/AArch64/arm64-misched-memdep-bug.ll @@ -4,16 +4,16 @@ ; Test for bug in misched memory dependency calculation. ; ; CHECK: ********** MI Scheduling ********** -; CHECK: misched_bug:BB#0 entry -; CHECK: SU(2): %vreg2 = LDRWui %vreg0, 1; mem:LD4[%ptr1_plus1] GPR32:%vreg2 GPR64common:%vreg0 +; CHECK: misched_bug:%bb.0 entry +; CHECK: SU(2): %2 = LDRWui %0, 1; mem:LD4[%ptr1_plus1] GPR32:%2 GPR64common:%0 ; CHECK: Successors: -; CHECK-NEXT: SU(5): Data Latency=4 Reg=%vreg2 +; CHECK-NEXT: SU(5): Data Latency=4 Reg=%2 ; CHECK-NEXT: SU(4): Ord Latency=0 -; CHECK: SU(3): STRWui %wzr, %vreg0, 0; mem:ST4[%ptr1] GPR64common:%vreg0 +; CHECK: SU(3): STRWui %wzr, %0, 0; mem:ST4[%ptr1] GPR64common:%0 ; CHECK: Successors: ; CHECK: SU(4): Ord Latency=0 -; CHECK: SU(4): STRWui %wzr, %vreg1, 0; mem:ST4[%ptr2] GPR64common:%vreg1 -; CHECK: SU(5): %w0 = COPY %vreg2; GPR32:%vreg2 +; CHECK: SU(4): STRWui %wzr, %1, 0; mem:ST4[%ptr2] GPR64common:%1 +; CHECK: SU(5): %w0 = COPY %2; GPR32:%2 ; CHECK: ** ScheduleDAGMI::schedule picking next node define i32 @misched_bug(i32* %ptr1, i32* %ptr2) { entry: diff --git a/test/CodeGen/AArch64/arm64-narrow-st-merge.ll b/test/CodeGen/AArch64/arm64-narrow-st-merge.ll index b48f3b46cb46b..ec7c227e16999 100644 --- a/test/CodeGen/AArch64/arm64-narrow-st-merge.ll +++ b/test/CodeGen/AArch64/arm64-narrow-st-merge.ll @@ -19,7 +19,7 @@ entry: } ; CHECK-LABEL: Strh_zero_4 -; CHECK: str xzr +; CHECK: stp wzr, wzr ; CHECK-STRICT-LABEL: Strh_zero_4 ; CHECK-STRICT: strh wzr ; CHECK-STRICT: strh wzr @@ -137,7 +137,7 @@ entry: } ; CHECK-LABEL: Sturh_zero_4 -; CHECK: stur xzr +; CHECK: stp wzr, wzr ; CHECK-STRICT-LABEL: Sturh_zero_4 ; CHECK-STRICT: sturh wzr ; CHECK-STRICT: sturh wzr diff --git a/test/CodeGen/AArch64/arm64-spill-remarks-treshold-hotness.ll b/test/CodeGen/AArch64/arm64-spill-remarks-treshold-hotness.ll new file mode 100644 index 0000000000000..fe22296320fc5 --- /dev/null +++ b/test/CodeGen/AArch64/arm64-spill-remarks-treshold-hotness.ll @@ -0,0 +1,60 @@ +; RUN: llc < %s -mtriple=arm64-apple-ios7.0 -aarch64-neon-syntax=apple -pass-remarks-missed=regalloc \ +; RUN: -pass-remarks-with-hotness 2>&1 | FileCheck %s + +; RUN: llc < %s -mtriple=arm64-apple-ios7.0 -aarch64-neon-syntax=apple -pass-remarks-missed=regalloc \ +; RUN: -pass-remarks-with-hotness -pass-remarks-hotness-threshold=1 \ +; RUN: 2>&1 | FileCheck -check-prefix=THRESHOLD %s + +; CHECK: remark: /tmp/kk.c:3:20: 1 spills 1 reloads generated in loop{{$}} +; THRESHOLD-NOT: remark + +define void @fpr128(<4 x float>* %p) nounwind ssp { +entry: + br label %loop, !dbg !8 + +loop: + %i = phi i32 [ 0, %entry], [ %i.2, %end2 ] + br label %loop2, !dbg !9 + +loop2: + %j = phi i32 [ 0, %loop], [ %j.2, %loop2 ] + call void asm sideeffect "; inlineasm", "~{q0},~{q1},~{q2},~{q3},~{q4},~{q5},~{q6},~{q7},~{q8},~{q9},~{q10},~{q11},~{q12},~{q13},~{q14},~{q15},~{q16},~{q17},~{q18},~{q19},~{q20},~{q21},~{q22},~{q23},~{q24},~{q25},~{q26},~{q27},~{q28},~{q29},~{q30},~{q31},~{x0},~{x1},~{x2},~{x3},~{x4},~{x5},~{x6},~{x7},~{x8},~{x9},~{x10},~{x11},~{x12},~{x13},~{x14},~{x15},~{x16},~{x17},~{x18},~{x19},~{x20},~{x21},~{x22},~{x23},~{x24},~{x25},~{x26},~{x27},~{x28},~{fp},~{lr},~{sp},~{memory}"() nounwind + %j.2 = add i32 %j, 1 + %c2 = icmp slt i32 %j.2, 100 + br i1 %c2, label %loop2, label %end2 + +end2: + call void asm sideeffect "; inlineasm", "~{q0},~{q1},~{q2},~{q3},~{q4},~{q5},~{q6},~{q7},~{q8},~{q9},~{q10},~{q11},~{q12},~{q13},~{q14},~{q15},~{q16},~{q17},~{q18},~{q19},~{q20},~{q21},~{q22},~{q23},~{q24},~{q25},~{q26},~{q27},~{q28},~{q29},~{q30},~{q31},~{x0},~{x1},~{x2},~{x3},~{x4},~{x5},~{x6},~{x7},~{x8},~{x9},~{x10},~{x11},~{x12},~{x13},~{x14},~{x15},~{x16},~{x17},~{x18},~{x19},~{x20},~{x21},~{x22},~{x23},~{x24},~{x25},~{x26},~{x27},~{x28},~{fp},~{lr},~{sp},~{memory}"() nounwind + %i.2 = add i32 %i, 1 + %c = icmp slt i32 %i.2, 100 + br i1 %c, label %loop, label %end + +end: + br label %loop3 + +loop3: + %k = phi i32 [ 0, %end], [ %k.2, %loop3 ] + call void asm sideeffect "; inlineasm", "~{q0},~{q1},~{q2},~{q3},~{q4},~{q5},~{q6},~{q7},~{q8},~{q9},~{q10},~{q11},~{q12},~{q13},~{q14},~{q15},~{q16},~{q17},~{q18},~{q19},~{q20},~{q21},~{q22},~{q23},~{q24},~{q25},~{q26},~{q27},~{q28},~{q29},~{q30},~{q31},~{x0},~{x1},~{x2},~{x3},~{x4},~{x5},~{x6},~{x7},~{x8},~{x9},~{x10},~{x11},~{x12},~{x13},~{x14},~{x15},~{x16},~{x17},~{x18},~{x19},~{x20},~{x21},~{x22},~{x23},~{x24},~{x25},~{x26},~{x27},~{x28},~{fp},~{lr},~{sp},~{memory}"() nounwind + %k.2 = add i32 %k, 1 + %c3 = icmp slt i32 %k.2, 100 + br i1 %c3, label %loop3, label %end3, !dbg !10 + +end3: + ret void +} + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!3, !4} +!llvm.ident = !{!5} + +!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 3.9.0 ", isOptimized: true, runtimeVersion: 0, emissionKind: NoDebug, enums: !2) +!1 = !DIFile(filename: "/tmp/kk.c", directory: "/tmp") +!2 = !{} +!3 = !{i32 2, !"Debug Info Version", i32 3} +!4 = !{i32 1, !"PIC Level", i32 2} +!5 = !{!"clang version 3.9.0 "} +!6 = distinct !DISubprogram(name: "success", scope: !1, file: !1, line: 1, type: !7, isLocal: false, isDefinition: true, scopeLine: 1, flags: DIFlagPrototyped, isOptimized: true, unit: !0, variables: !2) +!7 = !DISubroutineType(types: !2) +!8 = !DILocation(line: 1, column: 20, scope: !6) +!9 = !DILocation(line: 2, column: 20, scope: !6) +!10 = !DILocation(line: 3, column: 20, scope: !6) diff --git a/test/CodeGen/AArch64/arm64-variadic-aapcs.ll b/test/CodeGen/AArch64/arm64-variadic-aapcs.ll index a09853a0b406b..c6c7a65e2c194 100644 --- a/test/CodeGen/AArch64/arm64-variadic-aapcs.ll +++ b/test/CodeGen/AArch64/arm64-variadic-aapcs.ll @@ -32,9 +32,11 @@ define void @test_simple(i32 %n, ...) { ; CHECK: add [[VR_TOP:x[0-9]+]], [[VR_TOPTMP]], #128 ; CHECK: str [[VR_TOP]], [x[[VA_LIST]], #16] -; CHECK: mov [[GRVR:x[0-9]+]], #-545460846720 -; CHECK: movk [[GRVR]], #65480 -; CHECK: str [[GRVR]], [x[[VA_LIST]], #24] +; CHECK: mov [[GR_OFFS:w[0-9]+]], #-56 +; CHECK: str [[GR_OFFS]], [x[[VA_LIST]], #24] + +; CHECK: orr [[VR_OFFS:w[0-9]+]], wzr, #0xffffff80 +; CHECK: str [[VR_OFFS]], [x[[VA_LIST]], #28] %addr = bitcast %va_list* @var to i8* call void @llvm.va_start(i8* %addr) @@ -68,9 +70,11 @@ define void @test_fewargs(i32 %n, i32 %n1, i32 %n2, float %m, ...) { ; CHECK: add [[VR_TOP:x[0-9]+]], [[VR_TOPTMP]], #112 ; CHECK: str [[VR_TOP]], [x[[VA_LIST]], #16] -; CHECK: mov [[GRVR_OFFS:x[0-9]+]], #-40 -; CHECK: movk [[GRVR_OFFS]], #65424, lsl #32 -; CHECK: str [[GRVR_OFFS]], [x[[VA_LIST]], #24] +; CHECK: mov [[GR_OFFS:w[0-9]+]], #-40 +; CHECK: str [[GR_OFFS]], [x[[VA_LIST]], #24] + +; CHECK: mov [[VR_OFFS:w[0-9]+]], #-11 +; CHECK: str [[VR_OFFS]], [x[[VA_LIST]], #28] %addr = bitcast %va_list* @var to i8* call void @llvm.va_start(i8* %addr) @@ -109,7 +113,7 @@ declare void @llvm.va_end(i8*) define void @test_va_end() nounwind { ; CHECK-LABEL: test_va_end: -; CHECK-NEXT: BB#0 +; CHECK-NEXT: %bb.0 %addr = bitcast %va_list* @var to i8* call void @llvm.va_end(i8* %addr) diff --git a/test/CodeGen/AArch64/bics.ll b/test/CodeGen/AArch64/bics.ll index 53aa28ad913fd..244aacbc0df39 100644 --- a/test/CodeGen/AArch64/bics.ll +++ b/test/CodeGen/AArch64/bics.ll @@ -2,7 +2,7 @@ define i1 @andn_cmp(i32 %x, i32 %y) { ; CHECK-LABEL: andn_cmp: -; CHECK: // BB#0: +; CHECK: // %bb.0: ; CHECK-NEXT: bics wzr, w1, w0 ; CHECK-NEXT: cset w0, eq ; CHECK-NEXT: ret @@ -15,7 +15,7 @@ define i1 @andn_cmp(i32 %x, i32 %y) { define i1 @and_cmp(i32 %x, i32 %y) { ; CHECK-LABEL: and_cmp: -; CHECK: // BB#0: +; CHECK: // %bb.0: ; CHECK-NEXT: bics wzr, w1, w0 ; CHECK-NEXT: cset w0, eq ; CHECK-NEXT: ret @@ -27,7 +27,7 @@ define i1 @and_cmp(i32 %x, i32 %y) { define i1 @and_cmp_const(i32 %x) { ; CHECK-LABEL: and_cmp_const: -; CHECK: // BB#0: +; CHECK: // %bb.0: ; CHECK-NEXT: mov w8, #43 ; CHECK-NEXT: bics wzr, w8, w0 ; CHECK-NEXT: cset w0, eq diff --git a/test/CodeGen/AArch64/branch-relax-cbz.ll b/test/CodeGen/AArch64/branch-relax-cbz.ll index d13c0f677bcb5..cddecbd9babbe 100644 --- a/test/CodeGen/AArch64/branch-relax-cbz.ll +++ b/test/CodeGen/AArch64/branch-relax-cbz.ll @@ -4,7 +4,7 @@ ; CHECK: cmn x{{[0-9]+}}, #5 ; CHECK-NEXT: b.le [[B2:LBB[0-9]+_[0-9]+]] -; CHECK-NEXT: ; BB#1: ; %b3 +; CHECK-NEXT: ; %bb.1: ; %b3 ; CHECK: ldr [[LOAD:w[0-9]+]] ; CHECK: cbnz [[LOAD]], [[B8:LBB[0-9]+_[0-9]+]] ; CHECK-NEXT: b [[B7:LBB[0-9]+_[0-9]+]] diff --git a/test/CodeGen/AArch64/emutls_generic.ll b/test/CodeGen/AArch64/emutls_generic.ll index 03473cf80ee4f..f205078ed411d 100644 --- a/test/CodeGen/AArch64/emutls_generic.ll +++ b/test/CodeGen/AArch64/emutls_generic.ll @@ -4,6 +4,10 @@ ; RUN: | FileCheck -check-prefix=ARM_64 %s ; RUN: llc < %s -emulated-tls -mtriple=aarch64-linux-android -O3 \ ; RUN: | FileCheck -check-prefix=ARM_64 %s +; RUN: llc < %s -emulated-tls -mtriple=aarch64-windows-gnu -O3 \ +; RUN: | FileCheck -check-prefix=ARM_64 %s +; RUN: llc < %s -emulated-tls -mtriple=aarch64-apple-darwin -O3 \ +; RUN: | FileCheck -check-prefix=DARWIN %s ; Make sure that TLS symbols are emitted in expected order. @@ -46,7 +50,7 @@ entry: ; ARM_64-NEXT: .xword 0 ; ARM_64-NEXT: .xword __emutls_t.external_y ; ARM_64-NOT: __emutls_v.external_x: -; ARM_64: .section .rodata, +; ARM_64: .section .r{{o?}}data, ; ARM_64-LABEL: __emutls_t.external_y: ; ARM_64-NEXT: .byte 7 ; ARM_64: .data{{$}} @@ -57,6 +61,41 @@ entry: ; ARM_64-NEXT: .xword 16 ; ARM_64-NEXT: .xword 0 ; ARM_64-NEXT: .xword __emutls_t.internal_y -; ARM_64: .section .rodata, +; ARM_64: .section .r{{o?}}data, ; ARM_64-LABEL: __emutls_t.internal_y: ; ARM_64-NEXT: .xword 9 + +; DARWIN-LABEL: _get_external_x: +; DARWIN: ___emutls_v.external_x +; DARWIN: ___emutls_get_address +; DARWIN-LABEL: _get_external_y: +; DARWIN: ___emutls_v.external_y +; DARWIN: ___emutls_get_address +; DARWIN-LABEL: _get_internal_y: +; DARWIN: ___emutls_v.internal_y +; DARWIN: ___emutls_get_address +; DARWIN-NOT: ___emutls_t.external_x +; DARWIN-NOT: ___emutls_v.external_x: +; DARWIN: .section __DATA,__data +; DARWIN: .globl ___emutls_v.external_y +; DARWIN: .p2align 3 +; DARWIN-LABEL: ___emutls_v.external_y: +; DARWIN-NEXT: .quad 1 +; DARWIN-NEXT: .quad 2 +; DARWIN-NEXT: .quad 0 +; DARWIN-NEXT: .quad ___emutls_t.external_y +; DARWIN-NOT: ___emutls_v.external_x: +; DARWIN: .section __TEXT,__const +; DARWIN-LABEL: ___emutls_t.external_y: +; DARWIN-NEXT: .byte 7 +; DARWIN: .section __DATA,__data +; DARWIN-NOT: .globl ___emutls_v +; DARWIN: .p2align 3 +; DARWIN-LABEL: ___emutls_v.internal_y: +; DARWIN-NEXT: .quad 8 +; DARWIN-NEXT: .quad 16 +; DARWIN-NEXT: .quad 0 +; DARWIN-NEXT: .quad ___emutls_t.internal_y +; DARWIN: .section __TEXT,__const +; DARWIN-LABEL: ___emutls_t.internal_y: +; DARWIN-NEXT: .quad 9 diff --git a/test/CodeGen/AArch64/fast-isel-assume.ll b/test/CodeGen/AArch64/fast-isel-assume.ll index d39a907407db7..50f510a09b638 100644 --- a/test/CodeGen/AArch64/fast-isel-assume.ll +++ b/test/CodeGen/AArch64/fast-isel-assume.ll @@ -3,7 +3,7 @@ ; Check that we ignore the assume intrinsic. ; CHECK-LABEL: test: -; CHECK: // BB#0: +; CHECK: // %bb.0: ; CHECK-NEXT: ret define void @test(i32 %a) { %tmp0 = icmp slt i32 %a, 0 diff --git a/test/CodeGen/AArch64/fast-isel-atomic.ll b/test/CodeGen/AArch64/fast-isel-atomic.ll index 195b8befc8e18..ec612616ae2a0 100644 --- a/test/CodeGen/AArch64/fast-isel-atomic.ll +++ b/test/CodeGen/AArch64/fast-isel-atomic.ll @@ -5,7 +5,7 @@ ; currently match, so we might as well check both! Feel free to remove SDAG. ; CHECK-LABEL: atomic_store_monotonic_8: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: strb w1, [x0] ; CHECK-NEXT: ret define void @atomic_store_monotonic_8(i8* %p, i8 %val) #0 { @@ -14,7 +14,7 @@ define void @atomic_store_monotonic_8(i8* %p, i8 %val) #0 { } ; CHECK-LABEL: atomic_store_monotonic_8_off: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: strb w1, [x0, #1] ; CHECK-NEXT: ret define void @atomic_store_monotonic_8_off(i8* %p, i8 %val) #0 { @@ -24,7 +24,7 @@ define void @atomic_store_monotonic_8_off(i8* %p, i8 %val) #0 { } ; CHECK-LABEL: atomic_store_monotonic_16: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: strh w1, [x0] ; CHECK-NEXT: ret define void @atomic_store_monotonic_16(i16* %p, i16 %val) #0 { @@ -33,7 +33,7 @@ define void @atomic_store_monotonic_16(i16* %p, i16 %val) #0 { } ; CHECK-LABEL: atomic_store_monotonic_16_off: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: strh w1, [x0, #2] ; CHECK-NEXT: ret define void @atomic_store_monotonic_16_off(i16* %p, i16 %val) #0 { @@ -43,7 +43,7 @@ define void @atomic_store_monotonic_16_off(i16* %p, i16 %val) #0 { } ; CHECK-LABEL: atomic_store_monotonic_32: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: str w1, [x0] ; CHECK-NEXT: ret define void @atomic_store_monotonic_32(i32* %p, i32 %val) #0 { @@ -52,7 +52,7 @@ define void @atomic_store_monotonic_32(i32* %p, i32 %val) #0 { } ; CHECK-LABEL: atomic_store_monotonic_32_off: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: str w1, [x0, #4] ; CHECK-NEXT: ret define void @atomic_store_monotonic_32_off(i32* %p, i32 %val) #0 { @@ -62,7 +62,7 @@ define void @atomic_store_monotonic_32_off(i32* %p, i32 %val) #0 { } ; CHECK-LABEL: atomic_store_monotonic_64: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: str x1, [x0] ; CHECK-NEXT: ret define void @atomic_store_monotonic_64(i64* %p, i64 %val) #0 { @@ -71,7 +71,7 @@ define void @atomic_store_monotonic_64(i64* %p, i64 %val) #0 { } ; CHECK-LABEL: atomic_store_monotonic_64_off: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: str x1, [x0, #8] ; CHECK-NEXT: ret define void @atomic_store_monotonic_64_off(i64* %p, i64 %val) #0 { @@ -81,7 +81,7 @@ define void @atomic_store_monotonic_64_off(i64* %p, i64 %val) #0 { } ; CHECK-LABEL: atomic_store_release_8: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: stlrb w1, [x0] ; CHECK-NEXT: ret define void @atomic_store_release_8(i8* %p, i8 %val) #0 { @@ -90,7 +90,7 @@ define void @atomic_store_release_8(i8* %p, i8 %val) #0 { } ; CHECK-LABEL: atomic_store_release_8_off: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: add x0, x0, #1 ; CHECK-NEXT: stlrb w1, [x0] ; CHECK-NEXT: ret @@ -101,7 +101,7 @@ define void @atomic_store_release_8_off(i8* %p, i8 %val) #0 { } ; CHECK-LABEL: atomic_store_release_16: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: stlrh w1, [x0] ; CHECK-NEXT: ret define void @atomic_store_release_16(i16* %p, i16 %val) #0 { @@ -110,7 +110,7 @@ define void @atomic_store_release_16(i16* %p, i16 %val) #0 { } ; CHECK-LABEL: atomic_store_release_16_off: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: add x0, x0, #2 ; CHECK-NEXT: stlrh w1, [x0] ; CHECK-NEXT: ret @@ -121,7 +121,7 @@ define void @atomic_store_release_16_off(i16* %p, i16 %val) #0 { } ; CHECK-LABEL: atomic_store_release_32: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: stlr w1, [x0] ; CHECK-NEXT: ret define void @atomic_store_release_32(i32* %p, i32 %val) #0 { @@ -130,7 +130,7 @@ define void @atomic_store_release_32(i32* %p, i32 %val) #0 { } ; CHECK-LABEL: atomic_store_release_32_off: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: add x0, x0, #4 ; CHECK-NEXT: stlr w1, [x0] ; CHECK-NEXT: ret @@ -141,7 +141,7 @@ define void @atomic_store_release_32_off(i32* %p, i32 %val) #0 { } ; CHECK-LABEL: atomic_store_release_64: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: stlr x1, [x0] ; CHECK-NEXT: ret define void @atomic_store_release_64(i64* %p, i64 %val) #0 { @@ -150,7 +150,7 @@ define void @atomic_store_release_64(i64* %p, i64 %val) #0 { } ; CHECK-LABEL: atomic_store_release_64_off: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: add x0, x0, #8 ; CHECK-NEXT: stlr x1, [x0] ; CHECK-NEXT: ret @@ -162,7 +162,7 @@ define void @atomic_store_release_64_off(i64* %p, i64 %val) #0 { ; CHECK-LABEL: atomic_store_seq_cst_8: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: stlrb w1, [x0] ; CHECK-NEXT: ret define void @atomic_store_seq_cst_8(i8* %p, i8 %val) #0 { @@ -171,7 +171,7 @@ define void @atomic_store_seq_cst_8(i8* %p, i8 %val) #0 { } ; CHECK-LABEL: atomic_store_seq_cst_8_off: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: add x0, x0, #1 ; CHECK-NEXT: stlrb w1, [x0] ; CHECK-NEXT: ret @@ -182,7 +182,7 @@ define void @atomic_store_seq_cst_8_off(i8* %p, i8 %val) #0 { } ; CHECK-LABEL: atomic_store_seq_cst_16: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: stlrh w1, [x0] ; CHECK-NEXT: ret define void @atomic_store_seq_cst_16(i16* %p, i16 %val) #0 { @@ -191,7 +191,7 @@ define void @atomic_store_seq_cst_16(i16* %p, i16 %val) #0 { } ; CHECK-LABEL: atomic_store_seq_cst_16_off: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: add x0, x0, #2 ; CHECK-NEXT: stlrh w1, [x0] ; CHECK-NEXT: ret @@ -202,7 +202,7 @@ define void @atomic_store_seq_cst_16_off(i16* %p, i16 %val) #0 { } ; CHECK-LABEL: atomic_store_seq_cst_32: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: stlr w1, [x0] ; CHECK-NEXT: ret define void @atomic_store_seq_cst_32(i32* %p, i32 %val) #0 { @@ -211,7 +211,7 @@ define void @atomic_store_seq_cst_32(i32* %p, i32 %val) #0 { } ; CHECK-LABEL: atomic_store_seq_cst_32_off: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: add x0, x0, #4 ; CHECK-NEXT: stlr w1, [x0] ; CHECK-NEXT: ret @@ -222,7 +222,7 @@ define void @atomic_store_seq_cst_32_off(i32* %p, i32 %val) #0 { } ; CHECK-LABEL: atomic_store_seq_cst_64: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: stlr x1, [x0] ; CHECK-NEXT: ret define void @atomic_store_seq_cst_64(i64* %p, i64 %val) #0 { @@ -231,7 +231,7 @@ define void @atomic_store_seq_cst_64(i64* %p, i64 %val) #0 { } ; CHECK-LABEL: atomic_store_seq_cst_64_off: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: add x0, x0, #8 ; CHECK-NEXT: stlr x1, [x0] ; CHECK-NEXT: ret diff --git a/test/CodeGen/AArch64/fast-isel-cmp-vec.ll b/test/CodeGen/AArch64/fast-isel-cmp-vec.ll index 89b368fa19bb8..d5b64c5363e1b 100644 --- a/test/CodeGen/AArch64/fast-isel-cmp-vec.ll +++ b/test/CodeGen/AArch64/fast-isel-cmp-vec.ll @@ -8,9 +8,9 @@ define <2 x i32> @icmp_v2i32(<2 x i32> %a) { ; CHECK-LABEL: icmp_v2i32: -; CHECK: ; BB#0: +; CHECK: ; %bb.0: ; CHECK-NEXT: cmeq.2s [[CMP:v[0-9]+]], v0, #0 -; CHECK-NEXT: ; BB#1: +; CHECK-NEXT: ; %bb.1: ; CHECK-NEXT: movi.2s [[MASK:v[0-9]+]], #1 ; CHECK-NEXT: and.8b v0, [[CMP]], [[MASK]] ; CHECK-NEXT: ret @@ -23,9 +23,9 @@ bb2: define <2 x i32> @icmp_constfold_v2i32(<2 x i32> %a) { ; CHECK-LABEL: icmp_constfold_v2i32: -; CHECK: ; BB#0: +; CHECK: ; %bb.0: ; CHECK-NEXT: movi d[[CMP:[0-9]+]], #0xffffffffffffffff -; CHECK-NEXT: ; BB#1: +; CHECK-NEXT: ; %bb.1: ; CHECK-NEXT: movi.2s [[MASK:v[0-9]+]], #1 ; CHECK-NEXT: and.8b v0, v[[CMP]], [[MASK]] ; CHECK-NEXT: ret @@ -38,10 +38,10 @@ bb2: define <4 x i32> @icmp_v4i32(<4 x i32> %a) { ; CHECK-LABEL: icmp_v4i32: -; CHECK: ; BB#0: +; CHECK: ; %bb.0: ; CHECK-NEXT: cmeq.4s [[CMP:v[0-9]+]], v0, #0 ; CHECK-NEXT: xtn.4h [[CMPV4I16:v[0-9]+]], [[CMP]] -; CHECK-NEXT: ; BB#1: +; CHECK-NEXT: ; %bb.1: ; CHECK-NEXT: movi.4h [[MASK:v[0-9]+]], #1 ; CHECK-NEXT: and.8b [[ZEXT:v[0-9]+]], [[CMPV4I16]], [[MASK]] ; CHECK-NEXT: ushll.4s v0, [[ZEXT]], #0 @@ -55,9 +55,9 @@ bb2: define <4 x i32> @icmp_constfold_v4i32(<4 x i32> %a) { ; CHECK-LABEL: icmp_constfold_v4i32: -; CHECK: ; BB#0: +; CHECK: ; %bb.0: ; CHECK-NEXT: movi d[[CMP:[0-9]+]], #0xffffffffffffffff -; CHECK-NEXT: ; BB#1: +; CHECK-NEXT: ; %bb.1: ; CHECK-NEXT: movi.4h [[MASK:v[0-9]+]], #1 ; CHECK-NEXT: and.8b [[ZEXT:v[0-9]+]], v[[CMP]], [[MASK]] ; CHECK-NEXT: ushll.4s v0, [[ZEXT]], #0 @@ -71,9 +71,9 @@ bb2: define <16 x i8> @icmp_v16i8(<16 x i8> %a) { ; CHECK-LABEL: icmp_v16i8: -; CHECK: ; BB#0: +; CHECK: ; %bb.0: ; CHECK-NEXT: cmeq.16b [[CMP:v[0-9]+]], v0, #0 -; CHECK-NEXT: ; BB#1: +; CHECK-NEXT: ; %bb.1: ; CHECK-NEXT: movi.16b [[MASK:v[0-9]+]], #1 ; CHECK-NEXT: and.16b v0, [[CMP]], [[MASK]] ; CHECK-NEXT: ret @@ -86,9 +86,9 @@ bb2: define <16 x i8> @icmp_constfold_v16i8(<16 x i8> %a) { ; CHECK-LABEL: icmp_constfold_v16i8: -; CHECK: ; BB#0: +; CHECK: ; %bb.0: ; CHECK-NEXT: movi.2d [[CMP:v[0-9]+]], #0xffffffffffffffff -; CHECK-NEXT: ; BB#1: +; CHECK-NEXT: ; %bb.1: ; CHECK-NEXT: movi.16b [[MASK:v[0-9]+]], #1 ; CHECK-NEXT: and.16b v0, [[CMP]], [[MASK]] ; CHECK-NEXT: ret diff --git a/test/CodeGen/AArch64/fast-isel-cmpxchg.ll b/test/CodeGen/AArch64/fast-isel-cmpxchg.ll index 7ef625abab20f..f03955c4dcd3e 100644 --- a/test/CodeGen/AArch64/fast-isel-cmpxchg.ll +++ b/test/CodeGen/AArch64/fast-isel-cmpxchg.ll @@ -6,7 +6,7 @@ ; CHECK-NEXT: ldaxr [[OLD:w[0-9]+]], [x0] ; CHECK-NEXT: cmp [[OLD]], w1 ; CHECK-NEXT: b.ne [[DONE:.LBB[0-9_]+]] -; CHECK-NEXT: // BB#2: +; CHECK-NEXT: // %bb.2: ; CHECK-NEXT: stlxr [[STATUS]], w2, [x0] ; CHECK-NEXT: cbnz [[STATUS]], [[RETRY]] ; CHECK-NEXT: [[DONE]]: @@ -25,14 +25,14 @@ define i32 @cmpxchg_monotonic_32(i32* %p, i32 %cmp, i32 %new, i32* %ps) #0 { } ; CHECK-LABEL: cmpxchg_acq_rel_32_load: -; CHECK: // BB#0: +; CHECK: // %bb.0: ; CHECK: ldr [[NEW:w[0-9]+]], [x2] ; CHECK-NEXT: [[RETRY:.LBB[0-9_]+]]: ; CHECK-NEXT: mov [[STATUS:w[0-9]+]], #0 ; CHECK-NEXT: ldaxr [[OLD:w[0-9]+]], [x0] ; CHECK-NEXT: cmp [[OLD]], w1 ; CHECK-NEXT: b.ne [[DONE:.LBB[0-9_]+]] -; CHECK-NEXT: // BB#2: +; CHECK-NEXT: // %bb.2: ; CHECK-NEXT: stlxr [[STATUS]], [[NEW]], [x0] ; CHECK-NEXT: cbnz [[STATUS]], [[RETRY]] ; CHECK-NEXT: [[DONE]]: @@ -57,7 +57,7 @@ define i32 @cmpxchg_acq_rel_32_load(i32* %p, i32 %cmp, i32* %pnew, i32* %ps) #0 ; CHECK-NEXT: ldaxr [[OLD:x[0-9]+]], [x0] ; CHECK-NEXT: cmp [[OLD]], x1 ; CHECK-NEXT: b.ne [[DONE:.LBB[0-9_]+]] -; CHECK-NEXT: // BB#2: +; CHECK-NEXT: // %bb.2: ; CHECK-NEXT: stlxr [[STATUS]], x2, [x0] ; CHECK-NEXT: cbnz [[STATUS]], [[RETRY]] ; CHECK-NEXT: [[DONE]]: diff --git a/test/CodeGen/AArch64/fcvt-int.ll b/test/CodeGen/AArch64/fcvt-int.ll index e52b601b14542..aeafc127494bd 100644 --- a/test/CodeGen/AArch64/fcvt-int.ll +++ b/test/CodeGen/AArch64/fcvt-int.ll @@ -152,7 +152,7 @@ define double @test_bitcasti64todouble(i64 %in) { define double @bitcast_fabs(double %x) { ; CHECK-LABEL: bitcast_fabs: -; CHECK: ; BB#0: +; CHECK: ; %bb.0: ; CHECK-NEXT: fabs d0, d0 ; CHECK-NEXT: ret ; @@ -164,7 +164,7 @@ define double @bitcast_fabs(double %x) { define float @bitcast_fneg(float %x) { ; CHECK-LABEL: bitcast_fneg: -; CHECK: ; BB#0: +; CHECK: ; %bb.0: ; CHECK-NEXT: fneg s0, s0 ; CHECK-NEXT: ret ; diff --git a/test/CodeGen/AArch64/local_vars.ll b/test/CodeGen/AArch64/local_vars.ll index 6e33ab2d0bebb..a479572d2a310 100644 --- a/test/CodeGen/AArch64/local_vars.ll +++ b/test/CodeGen/AArch64/local_vars.ll @@ -17,7 +17,7 @@ declare void @foo() define void @trivial_func() nounwind { ; CHECK-LABEL: trivial_func: // @trivial_func -; CHECK-NEXT: // BB#0 +; CHECK-NEXT: // %bb.0 ; CHECK-NEXT: ret ret void diff --git a/test/CodeGen/AArch64/machine-outliner-remarks.ll b/test/CodeGen/AArch64/machine-outliner-remarks.ll index 1a237a2403ea5..a5f131b5a0ca7 100644 --- a/test/CodeGen/AArch64/machine-outliner-remarks.ll +++ b/test/CodeGen/AArch64/machine-outliner-remarks.ll @@ -120,4 +120,4 @@ attributes #0 = { noredzone nounwind ssp uwtable "no-frame-pointer-elim"="false" !26 = !DILocation(line: 29, column: 9, scope: !18) !27 = distinct !DISubprogram(name: "bar", scope: !1, file: !1, line: 35, type: !9, isLocal: false, isDefinition: true, scopeLine: 35, flags: DIFlagPrototyped, isOptimized: false, unit: !0, variables: !2) !33 = !DILocation(line: 36, column: 1, scope: !27) -!35 = !DILocation(line: 38, column: 1, scope: !27) \ No newline at end of file +!35 = !DILocation(line: 38, column: 1, scope: !27) diff --git a/test/CodeGen/AArch64/max-jump-table.ll b/test/CodeGen/AArch64/max-jump-table.ll index 070502052fffc..1a7a418b31fb1 100644 --- a/test/CodeGen/AArch64/max-jump-table.ll +++ b/test/CodeGen/AArch64/max-jump-table.ll @@ -77,10 +77,10 @@ entry: ] ; CHECK-LABEL: function jt2: ; CHECK-NEXT: Jump Tables: -; CHECK0-NEXT: jt#0: BB#1 BB#2 BB#3 BB#4 BB#7 BB#7 BB#7 BB#7 BB#7 BB#7 BB#7 BB#7 BB#7 BB#5 BB#6{{$}} -; CHECK4-NEXT: jt#0: BB#1 BB#2 BB#3 BB#4{{$}} -; CHECK8-NEXT: jt#0: BB#1 BB#2 BB#3 BB#4{{$}} -; CHECKM1-NEXT: jt#0: BB#1 BB#2 BB#3 BB#4{{$}} +; CHECK0-NEXT: jt#0: %bb.1 %bb.2 %bb.3 %bb.4 %bb.7 %bb.7 %bb.7 %bb.7 %bb.7 %bb.7 %bb.7 %bb.7 %bb.7 %bb.5 %bb.6{{$}} +; CHECK4-NEXT: jt#0: %bb.1 %bb.2 %bb.3 %bb.4{{$}} +; CHECK8-NEXT: jt#0: %bb.1 %bb.2 %bb.3 %bb.4{{$}} +; CHECKM1-NEXT: jt#0: %bb.1 %bb.2 %bb.3 %bb.4{{$}} ; CHEC-NEXT: Function Live Ins: bb1: tail call void @ext(i32 1) br label %return diff --git a/test/CodeGen/AArch64/neon-bitcast.ll b/test/CodeGen/AArch64/neon-bitcast.ll index 61099d48fdd29..8f67ff83ae129 100644 --- a/test/CodeGen/AArch64/neon-bitcast.ll +++ b/test/CodeGen/AArch64/neon-bitcast.ll @@ -4,7 +4,7 @@ define <1 x i64> @test_v8i8_to_v1i64(<8 x i8> %in) nounwind { ; CHECK: test_v8i8_to_v1i64: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: ret %val = bitcast <8 x i8> %in to <1 x i64> @@ -13,7 +13,7 @@ define <1 x i64> @test_v8i8_to_v1i64(<8 x i8> %in) nounwind { define <2 x i32> @test_v8i8_to_v2i32(<8 x i8> %in) nounwind { ; CHECK: test_v8i8_to_v2i32: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: ret %val = bitcast <8 x i8> %in to <2 x i32> @@ -22,7 +22,7 @@ define <2 x i32> @test_v8i8_to_v2i32(<8 x i8> %in) nounwind { define <2 x float> @test_v8i8_to_v2f32(<8 x i8> %in) nounwind{ ; CHECK: test_v8i8_to_v2f32: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: ret %val = bitcast <8 x i8> %in to <2 x float> @@ -31,7 +31,7 @@ define <2 x float> @test_v8i8_to_v2f32(<8 x i8> %in) nounwind{ define <4 x i16> @test_v8i8_to_v4i16(<8 x i8> %in) nounwind{ ; CHECK: test_v8i8_to_v4i16: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: ret %val = bitcast <8 x i8> %in to <4 x i16> @@ -40,7 +40,7 @@ define <4 x i16> @test_v8i8_to_v4i16(<8 x i8> %in) nounwind{ define <8 x i8> @test_v8i8_to_v8i8(<8 x i8> %in) nounwind{ ; CHECK: test_v8i8_to_v8i8: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: ret %val = bitcast <8 x i8> %in to <8 x i8> @@ -51,7 +51,7 @@ define <8 x i8> @test_v8i8_to_v8i8(<8 x i8> %in) nounwind{ define <1 x i64> @test_v4i16_to_v1i64(<4 x i16> %in) nounwind { ; CHECK: test_v4i16_to_v1i64: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: ret %val = bitcast <4 x i16> %in to <1 x i64> @@ -60,7 +60,7 @@ define <1 x i64> @test_v4i16_to_v1i64(<4 x i16> %in) nounwind { define <2 x i32> @test_v4i16_to_v2i32(<4 x i16> %in) nounwind { ; CHECK: test_v4i16_to_v2i32: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: ret %val = bitcast <4 x i16> %in to <2 x i32> @@ -69,7 +69,7 @@ define <2 x i32> @test_v4i16_to_v2i32(<4 x i16> %in) nounwind { define <2 x float> @test_v4i16_to_v2f32(<4 x i16> %in) nounwind{ ; CHECK: test_v4i16_to_v2f32: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: ret %val = bitcast <4 x i16> %in to <2 x float> @@ -78,7 +78,7 @@ define <2 x float> @test_v4i16_to_v2f32(<4 x i16> %in) nounwind{ define <4 x i16> @test_v4i16_to_v4i16(<4 x i16> %in) nounwind{ ; CHECK: test_v4i16_to_v4i16: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: ret %val = bitcast <4 x i16> %in to <4 x i16> @@ -87,7 +87,7 @@ define <4 x i16> @test_v4i16_to_v4i16(<4 x i16> %in) nounwind{ define <8 x i8> @test_v4i16_to_v8i8(<4 x i16> %in) nounwind{ ; CHECK: test_v4i16_to_v8i8: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: ret %val = bitcast <4 x i16> %in to <8 x i8> @@ -98,7 +98,7 @@ define <8 x i8> @test_v4i16_to_v8i8(<4 x i16> %in) nounwind{ define <1 x i64> @test_v2i32_to_v1i64(<2 x i32> %in) nounwind { ; CHECK: test_v2i32_to_v1i64: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: ret %val = bitcast <2 x i32> %in to <1 x i64> @@ -107,7 +107,7 @@ define <1 x i64> @test_v2i32_to_v1i64(<2 x i32> %in) nounwind { define <2 x i32> @test_v2i32_to_v2i32(<2 x i32> %in) nounwind { ; CHECK: test_v2i32_to_v2i32: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: ret %val = bitcast <2 x i32> %in to <2 x i32> @@ -116,7 +116,7 @@ define <2 x i32> @test_v2i32_to_v2i32(<2 x i32> %in) nounwind { define <2 x float> @test_v2i32_to_v2f32(<2 x i32> %in) nounwind{ ; CHECK: test_v2i32_to_v2f32: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: ret %val = bitcast <2 x i32> %in to <2 x float> @@ -125,7 +125,7 @@ define <2 x float> @test_v2i32_to_v2f32(<2 x i32> %in) nounwind{ define <4 x i16> @test_v2i32_to_v4i16(<2 x i32> %in) nounwind{ ; CHECK: test_v2i32_to_v4i16: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: ret %val = bitcast <2 x i32> %in to <4 x i16> @@ -134,7 +134,7 @@ define <4 x i16> @test_v2i32_to_v4i16(<2 x i32> %in) nounwind{ define <8 x i8> @test_v2i32_to_v8i8(<2 x i32> %in) nounwind{ ; CHECK: test_v2i32_to_v8i8: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: ret %val = bitcast <2 x i32> %in to <8 x i8> @@ -145,7 +145,7 @@ define <8 x i8> @test_v2i32_to_v8i8(<2 x i32> %in) nounwind{ define <1 x i64> @test_v2f32_to_v1i64(<2 x float> %in) nounwind { ; CHECK: test_v2f32_to_v1i64: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: ret %val = bitcast <2 x float> %in to <1 x i64> @@ -154,7 +154,7 @@ define <1 x i64> @test_v2f32_to_v1i64(<2 x float> %in) nounwind { define <2 x i32> @test_v2f32_to_v2i32(<2 x float> %in) nounwind { ; CHECK: test_v2f32_to_v2i32: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: ret %val = bitcast <2 x float> %in to <2 x i32> @@ -163,7 +163,7 @@ define <2 x i32> @test_v2f32_to_v2i32(<2 x float> %in) nounwind { define <2 x float> @test_v2f32_to_v2f32(<2 x float> %in) nounwind{ ; CHECK: test_v2f32_to_v2f32: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: ret %val = bitcast <2 x float> %in to <2 x float> @@ -172,7 +172,7 @@ define <2 x float> @test_v2f32_to_v2f32(<2 x float> %in) nounwind{ define <4 x i16> @test_v2f32_to_v4i16(<2 x float> %in) nounwind{ ; CHECK: test_v2f32_to_v4i16: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: ret %val = bitcast <2 x float> %in to <4 x i16> @@ -181,7 +181,7 @@ define <4 x i16> @test_v2f32_to_v4i16(<2 x float> %in) nounwind{ define <8 x i8> @test_v2f32_to_v8i8(<2 x float> %in) nounwind{ ; CHECK: test_v2f32_to_v8i8: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: ret %val = bitcast <2 x float> %in to <8 x i8> @@ -192,7 +192,7 @@ define <8 x i8> @test_v2f32_to_v8i8(<2 x float> %in) nounwind{ define <1 x i64> @test_v1i64_to_v1i64(<1 x i64> %in) nounwind { ; CHECK: test_v1i64_to_v1i64: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: ret %val = bitcast <1 x i64> %in to <1 x i64> @@ -201,7 +201,7 @@ define <1 x i64> @test_v1i64_to_v1i64(<1 x i64> %in) nounwind { define <2 x i32> @test_v1i64_to_v2i32(<1 x i64> %in) nounwind { ; CHECK: test_v1i64_to_v2i32: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: ret %val = bitcast <1 x i64> %in to <2 x i32> @@ -210,7 +210,7 @@ define <2 x i32> @test_v1i64_to_v2i32(<1 x i64> %in) nounwind { define <2 x float> @test_v1i64_to_v2f32(<1 x i64> %in) nounwind{ ; CHECK: test_v1i64_to_v2f32: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: ret %val = bitcast <1 x i64> %in to <2 x float> @@ -219,7 +219,7 @@ define <2 x float> @test_v1i64_to_v2f32(<1 x i64> %in) nounwind{ define <4 x i16> @test_v1i64_to_v4i16(<1 x i64> %in) nounwind{ ; CHECK: test_v1i64_to_v4i16: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: ret %val = bitcast <1 x i64> %in to <4 x i16> @@ -228,7 +228,7 @@ define <4 x i16> @test_v1i64_to_v4i16(<1 x i64> %in) nounwind{ define <8 x i8> @test_v1i64_to_v8i8(<1 x i64> %in) nounwind{ ; CHECK: test_v1i64_to_v8i8: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: ret %val = bitcast <1 x i64> %in to <8 x i8> @@ -240,7 +240,7 @@ define <8 x i8> @test_v1i64_to_v8i8(<1 x i64> %in) nounwind{ define <2 x double> @test_v16i8_to_v2f64(<16 x i8> %in) nounwind { ; CHECK: test_v16i8_to_v2f64: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: ret %val = bitcast <16 x i8> %in to <2 x double> @@ -249,7 +249,7 @@ define <2 x double> @test_v16i8_to_v2f64(<16 x i8> %in) nounwind { define <2 x i64> @test_v16i8_to_v2i64(<16 x i8> %in) nounwind { ; CHECK: test_v16i8_to_v2i64: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: ret %val = bitcast <16 x i8> %in to <2 x i64> @@ -258,7 +258,7 @@ define <2 x i64> @test_v16i8_to_v2i64(<16 x i8> %in) nounwind { define <4 x i32> @test_v16i8_to_v4i32(<16 x i8> %in) nounwind { ; CHECK: test_v16i8_to_v4i32: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: ret %val = bitcast <16 x i8> %in to <4 x i32> @@ -267,7 +267,7 @@ define <4 x i32> @test_v16i8_to_v4i32(<16 x i8> %in) nounwind { define <4 x float> @test_v16i8_to_v2f32(<16 x i8> %in) nounwind{ ; CHECK: test_v16i8_to_v2f32: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: ret %val = bitcast <16 x i8> %in to <4 x float> @@ -276,7 +276,7 @@ define <4 x float> @test_v16i8_to_v2f32(<16 x i8> %in) nounwind{ define <8 x i16> @test_v16i8_to_v8i16(<16 x i8> %in) nounwind{ ; CHECK: test_v16i8_to_v8i16: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: ret %val = bitcast <16 x i8> %in to <8 x i16> @@ -285,7 +285,7 @@ define <8 x i16> @test_v16i8_to_v8i16(<16 x i8> %in) nounwind{ define <16 x i8> @test_v16i8_to_v16i8(<16 x i8> %in) nounwind{ ; CHECK: test_v16i8_to_v16i8: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: ret %val = bitcast <16 x i8> %in to <16 x i8> @@ -296,7 +296,7 @@ define <16 x i8> @test_v16i8_to_v16i8(<16 x i8> %in) nounwind{ define <2 x double> @test_v8i16_to_v2f64(<8 x i16> %in) nounwind { ; CHECK: test_v8i16_to_v2f64: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: ret %val = bitcast <8 x i16> %in to <2 x double> @@ -305,7 +305,7 @@ define <2 x double> @test_v8i16_to_v2f64(<8 x i16> %in) nounwind { define <2 x i64> @test_v8i16_to_v2i64(<8 x i16> %in) nounwind { ; CHECK: test_v8i16_to_v2i64: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: ret %val = bitcast <8 x i16> %in to <2 x i64> @@ -314,7 +314,7 @@ define <2 x i64> @test_v8i16_to_v2i64(<8 x i16> %in) nounwind { define <4 x i32> @test_v8i16_to_v4i32(<8 x i16> %in) nounwind { ; CHECK: test_v8i16_to_v4i32: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: ret %val = bitcast <8 x i16> %in to <4 x i32> @@ -323,7 +323,7 @@ define <4 x i32> @test_v8i16_to_v4i32(<8 x i16> %in) nounwind { define <4 x float> @test_v8i16_to_v2f32(<8 x i16> %in) nounwind{ ; CHECK: test_v8i16_to_v2f32: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: ret %val = bitcast <8 x i16> %in to <4 x float> @@ -332,7 +332,7 @@ define <4 x float> @test_v8i16_to_v2f32(<8 x i16> %in) nounwind{ define <8 x i16> @test_v8i16_to_v8i16(<8 x i16> %in) nounwind{ ; CHECK: test_v8i16_to_v8i16: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: ret %val = bitcast <8 x i16> %in to <8 x i16> @@ -341,7 +341,7 @@ define <8 x i16> @test_v8i16_to_v8i16(<8 x i16> %in) nounwind{ define <16 x i8> @test_v8i16_to_v16i8(<8 x i16> %in) nounwind{ ; CHECK: test_v8i16_to_v16i8: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: ret %val = bitcast <8 x i16> %in to <16 x i8> @@ -352,7 +352,7 @@ define <16 x i8> @test_v8i16_to_v16i8(<8 x i16> %in) nounwind{ define <2 x double> @test_v4i32_to_v2f64(<4 x i32> %in) nounwind { ; CHECK: test_v4i32_to_v2f64: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: ret %val = bitcast <4 x i32> %in to <2 x double> @@ -361,7 +361,7 @@ define <2 x double> @test_v4i32_to_v2f64(<4 x i32> %in) nounwind { define <2 x i64> @test_v4i32_to_v2i64(<4 x i32> %in) nounwind { ; CHECK: test_v4i32_to_v2i64: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: ret %val = bitcast <4 x i32> %in to <2 x i64> @@ -370,7 +370,7 @@ define <2 x i64> @test_v4i32_to_v2i64(<4 x i32> %in) nounwind { define <4 x i32> @test_v4i32_to_v4i32(<4 x i32> %in) nounwind { ; CHECK: test_v4i32_to_v4i32: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: ret %val = bitcast <4 x i32> %in to <4 x i32> @@ -379,7 +379,7 @@ define <4 x i32> @test_v4i32_to_v4i32(<4 x i32> %in) nounwind { define <4 x float> @test_v4i32_to_v2f32(<4 x i32> %in) nounwind{ ; CHECK: test_v4i32_to_v2f32: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: ret %val = bitcast <4 x i32> %in to <4 x float> @@ -388,7 +388,7 @@ define <4 x float> @test_v4i32_to_v2f32(<4 x i32> %in) nounwind{ define <8 x i16> @test_v4i32_to_v8i16(<4 x i32> %in) nounwind{ ; CHECK: test_v4i32_to_v8i16: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: ret %val = bitcast <4 x i32> %in to <8 x i16> @@ -397,7 +397,7 @@ define <8 x i16> @test_v4i32_to_v8i16(<4 x i32> %in) nounwind{ define <16 x i8> @test_v4i32_to_v16i8(<4 x i32> %in) nounwind{ ; CHECK: test_v4i32_to_v16i8: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: ret %val = bitcast <4 x i32> %in to <16 x i8> @@ -408,7 +408,7 @@ define <16 x i8> @test_v4i32_to_v16i8(<4 x i32> %in) nounwind{ define <2 x double> @test_v4f32_to_v2f64(<4 x float> %in) nounwind { ; CHECK: test_v4f32_to_v2f64: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: ret %val = bitcast <4 x float> %in to <2 x double> @@ -417,7 +417,7 @@ define <2 x double> @test_v4f32_to_v2f64(<4 x float> %in) nounwind { define <2 x i64> @test_v4f32_to_v2i64(<4 x float> %in) nounwind { ; CHECK: test_v4f32_to_v2i64: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: ret %val = bitcast <4 x float> %in to <2 x i64> @@ -426,7 +426,7 @@ define <2 x i64> @test_v4f32_to_v2i64(<4 x float> %in) nounwind { define <4 x i32> @test_v4f32_to_v4i32(<4 x float> %in) nounwind { ; CHECK: test_v4f32_to_v4i32: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: ret %val = bitcast <4 x float> %in to <4 x i32> @@ -435,7 +435,7 @@ define <4 x i32> @test_v4f32_to_v4i32(<4 x float> %in) nounwind { define <4 x float> @test_v4f32_to_v4f32(<4 x float> %in) nounwind{ ; CHECK: test_v4f32_to_v4f32: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: ret %val = bitcast <4 x float> %in to <4 x float> @@ -444,7 +444,7 @@ define <4 x float> @test_v4f32_to_v4f32(<4 x float> %in) nounwind{ define <8 x i16> @test_v4f32_to_v8i16(<4 x float> %in) nounwind{ ; CHECK: test_v4f32_to_v8i16: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: ret %val = bitcast <4 x float> %in to <8 x i16> @@ -453,7 +453,7 @@ define <8 x i16> @test_v4f32_to_v8i16(<4 x float> %in) nounwind{ define <16 x i8> @test_v4f32_to_v16i8(<4 x float> %in) nounwind{ ; CHECK: test_v4f32_to_v16i8: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: ret %val = bitcast <4 x float> %in to <16 x i8> @@ -464,7 +464,7 @@ define <16 x i8> @test_v4f32_to_v16i8(<4 x float> %in) nounwind{ define <2 x double> @test_v2i64_to_v2f64(<2 x i64> %in) nounwind { ; CHECK: test_v2i64_to_v2f64: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: ret %val = bitcast <2 x i64> %in to <2 x double> @@ -473,7 +473,7 @@ define <2 x double> @test_v2i64_to_v2f64(<2 x i64> %in) nounwind { define <2 x i64> @test_v2i64_to_v2i64(<2 x i64> %in) nounwind { ; CHECK: test_v2i64_to_v2i64: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: ret %val = bitcast <2 x i64> %in to <2 x i64> @@ -482,7 +482,7 @@ define <2 x i64> @test_v2i64_to_v2i64(<2 x i64> %in) nounwind { define <4 x i32> @test_v2i64_to_v4i32(<2 x i64> %in) nounwind { ; CHECK: test_v2i64_to_v4i32: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: ret %val = bitcast <2 x i64> %in to <4 x i32> @@ -491,7 +491,7 @@ define <4 x i32> @test_v2i64_to_v4i32(<2 x i64> %in) nounwind { define <4 x float> @test_v2i64_to_v4f32(<2 x i64> %in) nounwind{ ; CHECK: test_v2i64_to_v4f32: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: ret %val = bitcast <2 x i64> %in to <4 x float> @@ -500,7 +500,7 @@ define <4 x float> @test_v2i64_to_v4f32(<2 x i64> %in) nounwind{ define <8 x i16> @test_v2i64_to_v8i16(<2 x i64> %in) nounwind{ ; CHECK: test_v2i64_to_v8i16: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: ret %val = bitcast <2 x i64> %in to <8 x i16> @@ -509,7 +509,7 @@ define <8 x i16> @test_v2i64_to_v8i16(<2 x i64> %in) nounwind{ define <16 x i8> @test_v2i64_to_v16i8(<2 x i64> %in) nounwind{ ; CHECK: test_v2i64_to_v16i8: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: ret %val = bitcast <2 x i64> %in to <16 x i8> @@ -520,7 +520,7 @@ define <16 x i8> @test_v2i64_to_v16i8(<2 x i64> %in) nounwind{ define <2 x double> @test_v2f64_to_v2f64(<2 x double> %in) nounwind { ; CHECK: test_v2f64_to_v2f64: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: ret %val = bitcast <2 x double> %in to <2 x double> @@ -529,7 +529,7 @@ define <2 x double> @test_v2f64_to_v2f64(<2 x double> %in) nounwind { define <2 x i64> @test_v2f64_to_v2i64(<2 x double> %in) nounwind { ; CHECK: test_v2f64_to_v2i64: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: ret %val = bitcast <2 x double> %in to <2 x i64> @@ -538,7 +538,7 @@ define <2 x i64> @test_v2f64_to_v2i64(<2 x double> %in) nounwind { define <4 x i32> @test_v2f64_to_v4i32(<2 x double> %in) nounwind { ; CHECK: test_v2f64_to_v4i32: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: ret %val = bitcast <2 x double> %in to <4 x i32> @@ -547,7 +547,7 @@ define <4 x i32> @test_v2f64_to_v4i32(<2 x double> %in) nounwind { define <4 x float> @test_v2f64_to_v4f32(<2 x double> %in) nounwind{ ; CHECK: test_v2f64_to_v4f32: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: ret %val = bitcast <2 x double> %in to <4 x float> @@ -556,7 +556,7 @@ define <4 x float> @test_v2f64_to_v4f32(<2 x double> %in) nounwind{ define <8 x i16> @test_v2f64_to_v8i16(<2 x double> %in) nounwind{ ; CHECK: test_v2f64_to_v8i16: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: ret %val = bitcast <2 x double> %in to <8 x i16> @@ -565,7 +565,7 @@ define <8 x i16> @test_v2f64_to_v8i16(<2 x double> %in) nounwind{ define <16 x i8> @test_v2f64_to_v16i8(<2 x double> %in) nounwind{ ; CHECK: test_v2f64_to_v16i8: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: ret %val = bitcast <2 x double> %in to <16 x i8> diff --git a/test/CodeGen/AArch64/nest-register.ll b/test/CodeGen/AArch64/nest-register.ll index cc42913e10a6c..b8651714be340 100644 --- a/test/CodeGen/AArch64/nest-register.ll +++ b/test/CodeGen/AArch64/nest-register.ll @@ -5,7 +5,7 @@ define i8* @nest_receiver(i8* nest %arg) nounwind { ; CHECK-LABEL: nest_receiver: -; CHECK-NEXT: // BB#0: +; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: mov x0, x18 ; CHECK-NEXT: ret diff --git a/test/CodeGen/AArch64/recp-fastmath.ll b/test/CodeGen/AArch64/recp-fastmath.ll index 4776931cf0625..9f00621eff6b4 100644 --- a/test/CodeGen/AArch64/recp-fastmath.ll +++ b/test/CodeGen/AArch64/recp-fastmath.ll @@ -5,7 +5,7 @@ define float @frecp0(float %x) #0 { ret float %div ; CHECK-LABEL: frecp0: -; CHECK-NEXT: BB#0 +; CHECK-NEXT: %bb.0 ; CHECK-NEXT: fmov ; CHECK-NEXT: fdiv } @@ -15,7 +15,7 @@ define float @frecp1(float %x) #1 { ret float %div ; CHECK-LABEL: frecp1: -; CHECK-NEXT: BB#0 +; CHECK-NEXT: %bb.0 ; CHECK-NEXT: frecpe [[R:s[0-7]]] ; CHECK-NEXT: frecps {{s[0-7](, s[0-7])?}}, [[R]] ; CHECK: frecps {{s[0-7]}}, {{s[0-7]}}, {{s[0-7]}} @@ -27,7 +27,7 @@ define <2 x float> @f2recp0(<2 x float> %x) #0 { ret <2 x float> %div ; CHECK-LABEL: f2recp0: -; CHECK-NEXT: BB#0 +; CHECK-NEXT: %bb.0 ; CHECK-NEXT: fmov ; CHECK-NEXT: fdiv } @@ -37,7 +37,7 @@ define <2 x float> @f2recp1(<2 x float> %x) #1 { ret <2 x float> %div ; CHECK-LABEL: f2recp1: -; CHECK-NEXT: BB#0 +; CHECK-NEXT: %bb.0 ; CHECK-NEXT: frecpe [[R:v[0-7]\.2s]] ; CHECK-NEXT: frecps {{v[0-7]\.2s(, v[0-7].2s)?}}, [[R]] ; CHECK: frecps {{v[0-7]\.2s}}, {{v[0-7]\.2s}}, {{v[0-7]\.2s}} @@ -49,7 +49,7 @@ define <4 x float> @f4recp0(<4 x float> %x) #0 { ret <4 x float> %div ; CHECK-LABEL: f4recp0: -; CHECK-NEXT: BB#0 +; CHECK-NEXT: %bb.0 ; CHECK-NEXT: fmov ; CHECK-NEXT: fdiv } @@ -59,7 +59,7 @@ define <4 x float> @f4recp1(<4 x float> %x) #1 { ret <4 x float> %div ; CHECK-LABEL: f4recp1: -; CHECK-NEXT: BB#0 +; CHECK-NEXT: %bb.0 ; CHECK-NEXT: frecpe [[R:v[0-7]\.4s]] ; CHECK-NEXT: frecps {{v[0-7]\.4s(, v[0-7].4s)?}}, [[R]] ; CHECK: frecps {{v[0-7]\.4s}}, {{v[0-7]\.4s}}, {{v[0-7]\.4s}} @@ -71,7 +71,7 @@ define <8 x float> @f8recp0(<8 x float> %x) #0 { ret <8 x float> %div ; CHECK-LABEL: f8recp0: -; CHECK-NEXT: BB#0 +; CHECK-NEXT: %bb.0 ; CHECK-NEXT: fmov ; CHECK-NEXT: fdiv ; CHECK-NEXT: fdiv @@ -82,7 +82,7 @@ define <8 x float> @f8recp1(<8 x float> %x) #1 { ret <8 x float> %div ; CHECK-LABEL: f8recp1: -; CHECK-NEXT: BB#0 +; CHECK-NEXT: %bb.0 ; CHECK-NEXT: frecpe [[R:v[0-7]\.4s]] ; CHECK: frecps {{v[0-7]\.4s(, v[0-7].4s)?}}, [[R]] ; CHECK: frecps {{v[0-7]\.4s(, v[0-7].4s)?}}, {{v[0-7]\.4s}} @@ -96,7 +96,7 @@ define double @drecp0(double %x) #0 { ret double %div ; CHECK-LABEL: drecp0: -; CHECK-NEXT: BB#0 +; CHECK-NEXT: %bb.0 ; CHECK-NEXT: fmov ; CHECK-NEXT: fdiv } @@ -106,7 +106,7 @@ define double @drecp1(double %x) #1 { ret double %div ; CHECK-LABEL: drecp1: -; CHECK-NEXT: BB#0 +; CHECK-NEXT: %bb.0 ; CHECK-NEXT: frecpe [[R:d[0-7]]] ; CHECK-NEXT: frecps {{d[0-7](, d[0-7])?}}, [[R]] ; CHECK: frecps {{d[0-7]}}, {{d[0-7]}}, {{d[0-7]}} @@ -119,7 +119,7 @@ define <2 x double> @d2recp0(<2 x double> %x) #0 { ret <2 x double> %div ; CHECK-LABEL: d2recp0: -; CHECK-NEXT: BB#0 +; CHECK-NEXT: %bb.0 ; CHECK-NEXT: fmov ; CHECK-NEXT: fdiv } @@ -129,7 +129,7 @@ define <2 x double> @d2recp1(<2 x double> %x) #1 { ret <2 x double> %div ; CHECK-LABEL: d2recp1: -; CHECK-NEXT: BB#0 +; CHECK-NEXT: %bb.0 ; CHECK-NEXT: frecpe [[R:v[0-7]\.2d]] ; CHECK-NEXT: frecps {{v[0-7]\.2d(, v[0-7].2d)?}}, [[R]] ; CHECK: frecps {{v[0-7]\.2d}}, {{v[0-7]\.2d}}, {{v[0-7]\.2d}} @@ -142,7 +142,7 @@ define <4 x double> @d4recp0(<4 x double> %x) #0 { ret <4 x double> %div ; CHECK-LABEL: d4recp0: -; CHECK-NEXT: BB#0 +; CHECK-NEXT: %bb.0 ; CHECK-NEXT: fmov ; CHECK-NEXT: fdiv ; CHECK-NEXT: fdiv @@ -153,7 +153,7 @@ define <4 x double> @d4recp1(<4 x double> %x) #1 { ret <4 x double> %div ; CHECK-LABEL: d4recp1: -; CHECK-NEXT: BB#0 +; CHECK-NEXT: %bb.0 ; CHECK-NEXT: frecpe [[R:v[0-7]\.2d]] ; CHECK: frecps {{v[0-7]\.2d(, v[0-7].2d)?}}, [[R]] ; CHECK: frecps {{v[0-7]\.2d}}, {{v[0-7]\.2d}}, {{v[0-7]\.2d}} diff --git a/test/CodeGen/AArch64/selectcc-to-shiftand.ll b/test/CodeGen/AArch64/selectcc-to-shiftand.ll index 0d89cdedfa8a1..99190633547c7 100644 --- a/test/CodeGen/AArch64/selectcc-to-shiftand.ll +++ b/test/CodeGen/AArch64/selectcc-to-shiftand.ll @@ -4,7 +4,7 @@ define i32 @neg_sel_constants(i32 %a) { ; CHECK-LABEL: neg_sel_constants: -; CHECK: // BB#0: +; CHECK: // %bb.0: ; CHECK-NEXT: mov w8, #5 ; CHECK-NEXT: and w0, w8, w0, asr #31 ; CHECK-NEXT: ret @@ -18,7 +18,7 @@ define i32 @neg_sel_constants(i32 %a) { define i32 @neg_sel_special_constant(i32 %a) { ; CHECK-LABEL: neg_sel_special_constant: -; CHECK: // BB#0: +; CHECK: // %bb.0: ; CHECK-NEXT: lsr w8, w0, #22 ; CHECK-NEXT: and w0, w8, #0x200 ; CHECK-NEXT: ret @@ -32,7 +32,7 @@ define i32 @neg_sel_special_constant(i32 %a) { define i32 @neg_sel_variable_and_zero(i32 %a, i32 %b) { ; CHECK-LABEL: neg_sel_variable_and_zero: -; CHECK: // BB#0: +; CHECK: // %bb.0: ; CHECK-NEXT: and w0, w1, w0, asr #31 ; CHECK-NEXT: ret ; @@ -45,7 +45,7 @@ define i32 @neg_sel_variable_and_zero(i32 %a, i32 %b) { define i32 @not_pos_sel_same_variable(i32 %a) { ; CHECK-LABEL: not_pos_sel_same_variable: -; CHECK: // BB#0: +; CHECK: // %bb.0: ; CHECK-NEXT: and w0, w0, w0, asr #31 ; CHECK-NEXT: ret ; @@ -60,7 +60,7 @@ define i32 @not_pos_sel_same_variable(i32 %a) { define i32 @pos_sel_constants(i32 %a) { ; CHECK-LABEL: pos_sel_constants: -; CHECK: // BB#0: +; CHECK: // %bb.0: ; CHECK-NEXT: mov w8, #5 ; CHECK-NEXT: bic w0, w8, w0, asr #31 ; CHECK-NEXT: ret @@ -74,7 +74,7 @@ define i32 @pos_sel_constants(i32 %a) { define i32 @pos_sel_special_constant(i32 %a) { ; CHECK-LABEL: pos_sel_special_constant: -; CHECK: // BB#0: +; CHECK: // %bb.0: ; CHECK-NEXT: orr w8, wzr, #0x200 ; CHECK-NEXT: bic w0, w8, w0, lsr #22 ; CHECK-NEXT: ret @@ -88,7 +88,7 @@ define i32 @pos_sel_special_constant(i32 %a) { define i32 @pos_sel_variable_and_zero(i32 %a, i32 %b) { ; CHECK-LABEL: pos_sel_variable_and_zero: -; CHECK: // BB#0: +; CHECK: // %bb.0: ; CHECK-NEXT: bic w0, w1, w0, asr #31 ; CHECK-NEXT: ret ; @@ -101,7 +101,7 @@ define i32 @pos_sel_variable_and_zero(i32 %a, i32 %b) { define i32 @not_neg_sel_same_variable(i32 %a) { ; CHECK-LABEL: not_neg_sel_same_variable: -; CHECK: // BB#0: +; CHECK: // %bb.0: ; CHECK-NEXT: bic w0, w0, w0, asr #31 ; CHECK-NEXT: ret ; @@ -115,7 +115,7 @@ define i32 @not_neg_sel_same_variable(i32 %a) { ; ret = (x-y) > 0 ? x-y : 0 define i32 @PR31175(i32 %x, i32 %y) { ; CHECK-LABEL: PR31175: -; CHECK: // BB#0: +; CHECK: // %bb.0: ; CHECK-NEXT: sub w8, w0, w1 ; CHECK-NEXT: bic w0, w8, w8, asr #31 ; CHECK-NEXT: ret diff --git a/test/CodeGen/AArch64/sibling-call.ll b/test/CodeGen/AArch64/sibling-call.ll index 9a44b43d14e6a..be59f27fa8588 100644 --- a/test/CodeGen/AArch64/sibling-call.ll +++ b/test/CodeGen/AArch64/sibling-call.ll @@ -6,7 +6,7 @@ declare void @callee_stack16([8 x i32], i64, i64) define void @caller_to0_from0() nounwind { ; CHECK-LABEL: caller_to0_from0: -; CHECK-NEXT: // BB +; CHECK-NEXT: // %bb. tail call void @callee_stack0() ret void ; CHECK-NEXT: b callee_stack0 @@ -14,7 +14,7 @@ define void @caller_to0_from0() nounwind { define void @caller_to0_from8([8 x i32], i64) nounwind{ ; CHECK-LABEL: caller_to0_from8: -; CHECK-NEXT: // BB +; CHECK-NEXT: // %bb. tail call void @callee_stack0() ret void diff --git a/test/CodeGen/AArch64/sqrt-fastmath.ll b/test/CodeGen/AArch64/sqrt-fastmath.ll index 4dd0516faf0c6..ade9e3d8df32b 100644 --- a/test/CodeGen/AArch64/sqrt-fastmath.ll +++ b/test/CodeGen/AArch64/sqrt-fastmath.ll @@ -14,11 +14,11 @@ define float @fsqrt(float %a) #0 { ret float %1 ; FAULT-LABEL: fsqrt: -; FAULT-NEXT: BB#0 +; FAULT-NEXT: %bb.0 ; FAULT-NEXT: fsqrt ; CHECK-LABEL: fsqrt: -; CHECK-NEXT: BB#0 +; CHECK-NEXT: %bb.0 ; CHECK-NEXT: frsqrte [[RA:s[0-7]]] ; CHECK-NEXT: fmul [[RB:s[0-7]]], [[RA]], [[RA]] ; CHECK-NEXT: frsqrts {{s[0-7](, s[0-7])?}}, [[RB]] @@ -32,11 +32,11 @@ define <2 x float> @f2sqrt(<2 x float> %a) #0 { ret <2 x float> %1 ; FAULT-LABEL: f2sqrt: -; FAULT-NEXT: BB#0 +; FAULT-NEXT: %bb.0 ; FAULT-NEXT: fsqrt ; CHECK-LABEL: f2sqrt: -; CHECK-NEXT: BB#0 +; CHECK-NEXT: %bb.0 ; CHECK-NEXT: frsqrte [[RA:v[0-7]\.2s]] ; CHECK-NEXT: fmul [[RB:v[0-7]\.2s]], [[RA]], [[RA]] ; CHECK-NEXT: frsqrts {{v[0-7]\.2s(, v[0-7]\.2s)?}}, [[RB]] @@ -50,11 +50,11 @@ define <4 x float> @f4sqrt(<4 x float> %a) #0 { ret <4 x float> %1 ; FAULT-LABEL: f4sqrt: -; FAULT-NEXT: BB#0 +; FAULT-NEXT: %bb.0 ; FAULT-NEXT: fsqrt ; CHECK-LABEL: f4sqrt: -; CHECK-NEXT: BB#0 +; CHECK-NEXT: %bb.0 ; CHECK-NEXT: frsqrte [[RA:v[0-7]\.4s]] ; CHECK-NEXT: fmul [[RB:v[0-7]\.4s]], [[RA]], [[RA]] ; CHECK-NEXT: frsqrts {{v[0-7]\.4s(, v[0-7]\.4s)?}}, [[RB]] @@ -68,12 +68,12 @@ define <8 x float> @f8sqrt(<8 x float> %a) #0 { ret <8 x float> %1 ; FAULT-LABEL: f8sqrt: -; FAULT-NEXT: BB#0 +; FAULT-NEXT: %bb.0 ; FAULT-NEXT: fsqrt ; FAULT-NEXT: fsqrt ; CHECK-LABEL: f8sqrt: -; CHECK-NEXT: BB#0 +; CHECK-NEXT: %bb.0 ; CHECK-NEXT: frsqrte [[RA:v[0-7]\.4s]] ; CHECK-NEXT: fmul [[RB:v[0-7]\.4s]], [[RA]], [[RA]] ; CHECK-NEXT: frsqrts {{v[0-7]\.4s(, v[0-7]\.4s)?}}, [[RB]] @@ -92,11 +92,11 @@ define double @dsqrt(double %a) #0 { ret double %1 ; FAULT-LABEL: dsqrt: -; FAULT-NEXT: BB#0 +; FAULT-NEXT: %bb.0 ; FAULT-NEXT: fsqrt ; CHECK-LABEL: dsqrt: -; CHECK-NEXT: BB#0 +; CHECK-NEXT: %bb.0 ; CHECK-NEXT: frsqrte [[RA:d[0-7]]] ; CHECK-NEXT: fmul [[RB:d[0-7]]], [[RA]], [[RA]] ; CHECK-NEXT: frsqrts {{d[0-7](, d[0-7])?}}, [[RB]] @@ -111,11 +111,11 @@ define <2 x double> @d2sqrt(<2 x double> %a) #0 { ret <2 x double> %1 ; FAULT-LABEL: d2sqrt: -; FAULT-NEXT: BB#0 +; FAULT-NEXT: %bb.0 ; FAULT-NEXT: fsqrt ; CHECK-LABEL: d2sqrt: -; CHECK-NEXT: BB#0 +; CHECK-NEXT: %bb.0 ; CHECK-NEXT: frsqrte [[RA:v[0-7]\.2d]] ; CHECK-NEXT: fmul [[RB:v[0-7]\.2d]], [[RA]], [[RA]] ; CHECK-NEXT: frsqrts {{v[0-7]\.2d(, v[0-7]\.2d)?}}, [[RB]] @@ -130,12 +130,12 @@ define <4 x double> @d4sqrt(<4 x double> %a) #0 { ret <4 x double> %1 ; FAULT-LABEL: d4sqrt: -; FAULT-NEXT: BB#0 +; FAULT-NEXT: %bb.0 ; FAULT-NEXT: fsqrt ; FAULT-NEXT: fsqrt ; CHECK-LABEL: d4sqrt: -; CHECK-NEXT: BB#0 +; CHECK-NEXT: %bb.0 ; CHECK-NEXT: frsqrte [[RA:v[0-7]\.2d]] ; CHECK-NEXT: fmul [[RB:v[0-7]\.2d]], [[RA]], [[RA]] ; CHECK-NEXT: frsqrts {{v[0-7]\.2d(, v[0-7]\.2d)?}}, [[RB]] @@ -158,11 +158,11 @@ define float @frsqrt(float %a) #0 { ret float %2 ; FAULT-LABEL: frsqrt: -; FAULT-NEXT: BB#0 +; FAULT-NEXT: %bb.0 ; FAULT-NEXT: fsqrt ; CHECK-LABEL: frsqrt: -; CHECK-NEXT: BB#0 +; CHECK-NEXT: %bb.0 ; CHECK-NEXT: frsqrte [[RA:s[0-7]]] ; CHECK-NEXT: fmul [[RB:s[0-7]]], [[RA]], [[RA]] ; CHECK-NEXT: frsqrts {{s[0-7](, s[0-7])?}}, [[RB]] @@ -177,11 +177,11 @@ define <2 x float> @f2rsqrt(<2 x float> %a) #0 { ret <2 x float> %2 ; FAULT-LABEL: f2rsqrt: -; FAULT-NEXT: BB#0 +; FAULT-NEXT: %bb.0 ; FAULT-NEXT: fsqrt ; CHECK-LABEL: f2rsqrt: -; CHECK-NEXT: BB#0 +; CHECK-NEXT: %bb.0 ; CHECK-NEXT: frsqrte [[RA:v[0-7]\.2s]] ; CHECK-NEXT: fmul [[RB:v[0-7]\.2s]], [[RA]], [[RA]] ; CHECK-NEXT: frsqrts {{v[0-7]\.2s(, v[0-7]\.2s)?}}, [[RB]] @@ -196,11 +196,11 @@ define <4 x float> @f4rsqrt(<4 x float> %a) #0 { ret <4 x float> %2 ; FAULT-LABEL: f4rsqrt: -; FAULT-NEXT: BB#0 +; FAULT-NEXT: %bb.0 ; FAULT-NEXT: fsqrt ; CHECK-LABEL: f4rsqrt: -; CHECK-NEXT: BB#0 +; CHECK-NEXT: %bb.0 ; CHECK-NEXT: frsqrte [[RA:v[0-7]\.4s]] ; CHECK-NEXT: fmul [[RB:v[0-7]\.4s]], [[RA]], [[RA]] ; CHECK-NEXT: frsqrts {{v[0-7]\.4s(, v[0-7]\.4s)?}}, [[RB]] @@ -215,12 +215,12 @@ define <8 x float> @f8rsqrt(<8 x float> %a) #0 { ret <8 x float> %2 ; FAULT-LABEL: f8rsqrt: -; FAULT-NEXT: BB#0 +; FAULT-NEXT: %bb.0 ; FAULT-NEXT: fsqrt ; FAULT-NEXT: fsqrt ; CHECK-LABEL: f8rsqrt: -; CHECK-NEXT: BB#0 +; CHECK-NEXT: %bb.0 ; CHECK-NEXT: frsqrte [[RA:v[0-7]\.4s]] ; CHECK: fmul [[RB:v[0-7]\.4s]], [[RA]], [[RA]] ; CHECK: frsqrts {{v[0-7]\.4s(, v[0-7]\.4s)?}}, [[RB]] @@ -237,11 +237,11 @@ define double @drsqrt(double %a) #0 { ret double %2 ; FAULT-LABEL: drsqrt: -; FAULT-NEXT: BB#0 +; FAULT-NEXT: %bb.0 ; FAULT-NEXT: fsqrt ; CHECK-LABEL: drsqrt: -; CHECK-NEXT: BB#0 +; CHECK-NEXT: %bb.0 ; CHECK-NEXT: frsqrte [[RA:d[0-7]]] ; CHECK-NEXT: fmul [[RB:d[0-7]]], [[RA]], [[RA]] ; CHECK-NEXT: frsqrts {{d[0-7](, d[0-7])?}}, [[RB]] @@ -257,11 +257,11 @@ define <2 x double> @d2rsqrt(<2 x double> %a) #0 { ret <2 x double> %2 ; FAULT-LABEL: d2rsqrt: -; FAULT-NEXT: BB#0 +; FAULT-NEXT: %bb.0 ; FAULT-NEXT: fsqrt ; CHECK-LABEL: d2rsqrt: -; CHECK-NEXT: BB#0 +; CHECK-NEXT: %bb.0 ; CHECK-NEXT: frsqrte [[RA:v[0-7]\.2d]] ; CHECK-NEXT: fmul [[RB:v[0-7]\.2d]], [[RA]], [[RA]] ; CHECK-NEXT: frsqrts {{v[0-7]\.2d(, v[0-7]\.2d)?}}, [[RB]] @@ -277,12 +277,12 @@ define <4 x double> @d4rsqrt(<4 x double> %a) #0 { ret <4 x double> %2 ; FAULT-LABEL: d4rsqrt: -; FAULT-NEXT: BB#0 +; FAULT-NEXT: %bb.0 ; FAULT-NEXT: fsqrt ; FAULT-NEXT: fsqrt ; CHECK-LABEL: d4rsqrt: -; CHECK-NEXT: BB#0 +; CHECK-NEXT: %bb.0 ; CHECK-NEXT: frsqrte [[RA:v[0-7]\.2d]] ; CHECK: fmul [[RB:v[0-7]\.2d]], [[RA]], [[RA]] ; CHECK: frsqrts {{v[0-7]\.2d(, v[0-7]\.2d)?}}, [[RB]] diff --git a/test/CodeGen/AArch64/tail-call.ll b/test/CodeGen/AArch64/tail-call.ll index fa5d8b943b6b5..ab63413bd3f1a 100644 --- a/test/CodeGen/AArch64/tail-call.ll +++ b/test/CodeGen/AArch64/tail-call.ll @@ -7,7 +7,7 @@ declare extern_weak fastcc void @callee_weak() define fastcc void @caller_to0_from0() nounwind { ; CHECK-LABEL: caller_to0_from0: -; CHECK-NEXT: // BB +; CHECK-NEXT: // %bb. tail call fastcc void @callee_stack0() ret void diff --git a/test/CodeGen/AArch64/tailcall-explicit-sret.ll b/test/CodeGen/AArch64/tailcall-explicit-sret.ll index b60958b5a25df..c157933618962 100644 --- a/test/CodeGen/AArch64/tailcall-explicit-sret.ll +++ b/test/CodeGen/AArch64/tailcall-explicit-sret.ll @@ -35,7 +35,7 @@ define void @test_tailcall_explicit_sret_alloca_unused() #0 { } ; CHECK-LABEL: _test_tailcall_explicit_sret_alloca_dummyusers: -; CHECK: ldr [[PTRLOAD1:q[0-9]+]], [x0] +; CHECK: ldr [[PTRLOAD1:x[0-9]+]], [x0] ; CHECK: str [[PTRLOAD1]], [sp] ; CHECK: mov x8, sp ; CHECK-NEXT: bl _test_explicit_sret @@ -64,8 +64,8 @@ define void @test_tailcall_explicit_sret_gep(i1024* %ptr) #0 { ; CHECK: mov x[[CALLERX8NUM:[0-9]+]], x8 ; CHECK: mov x8, sp ; CHECK-NEXT: bl _test_explicit_sret -; CHECK-NEXT: ldr [[CALLERSRET1:q[0-9]+]], [sp] -; CHECK: str [[CALLERSRET1:q[0-9]+]], [x[[CALLERX8NUM]]] +; CHECK-NEXT: ldr [[CALLERSRET1:x[0-9]+]], [sp] +; CHECK: str [[CALLERSRET1:x[0-9]+]], [x[[CALLERX8NUM]]] ; CHECK: ret define i1024 @test_tailcall_explicit_sret_alloca_returned() #0 { %l = alloca i1024, align 8 @@ -79,8 +79,8 @@ define i1024 @test_tailcall_explicit_sret_alloca_returned() #0 { ; CHECK-DAG: mov [[FPTR:x[0-9]+]], x0 ; CHECK: mov x0, sp ; CHECK-NEXT: blr [[FPTR]] -; CHECK: ldr [[CALLERSRET1:q[0-9]+]], [sp] -; CHECK: str [[CALLERSRET1:q[0-9]+]], [x[[CALLERX8NUM]]] +; CHECK-NEXT: ldr [[CALLERSRET1:x[0-9]+]], [sp] +; CHECK: str [[CALLERSRET1:x[0-9]+]], [x[[CALLERX8NUM]]] ; CHECK: ret define void @test_indirect_tailcall_explicit_sret_nosret_arg(i1024* sret %arg, void (i1024*)* %f) #0 { %l = alloca i1024, align 8 @@ -94,8 +94,8 @@ define void @test_indirect_tailcall_explicit_sret_nosret_arg(i1024* sret %arg, v ; CHECK: mov x[[CALLERX8NUM:[0-9]+]], x8 ; CHECK: mov x8, sp ; CHECK-NEXT: blr x0 -; CHECK: ldr [[CALLERSRET1:q[0-9]+]], [sp] -; CHECK: str [[CALLERSRET1:q[0-9]+]], [x[[CALLERX8NUM]]] +; CHECK-NEXT: ldr [[CALLERSRET1:x[0-9]+]], [sp] +; CHECK: str [[CALLERSRET1:x[0-9]+]], [x[[CALLERX8NUM]]] ; CHECK: ret define void @test_indirect_tailcall_explicit_sret_(i1024* sret %arg, i1024 ()* %f) #0 { %ret = tail call i1024 %f() diff --git a/test/CodeGen/AArch64/tailcall-implicit-sret.ll b/test/CodeGen/AArch64/tailcall-implicit-sret.ll index f449a7e06588a..10c4ba4c31d63 100644 --- a/test/CodeGen/AArch64/tailcall-implicit-sret.ll +++ b/test/CodeGen/AArch64/tailcall-implicit-sret.ll @@ -11,8 +11,8 @@ declare i1024 @test_sret() #0 ; CHECK: mov x[[CALLERX8NUM:[0-9]+]], x8 ; CHECK: mov x8, sp ; CHECK-NEXT: bl _test_sret -; CHECK: ldr [[CALLERSRET1:q[0-9]+]], [sp] -; CHECK: str [[CALLERSRET1:q[0-9]+]], [x[[CALLERX8NUM]]] +; CHECK-NEXT: ldr [[CALLERSRET1:x[0-9]+]], [sp] +; CHECK: str [[CALLERSRET1:x[0-9]+]], [x[[CALLERX8NUM]]] ; CHECK: ret define i1024 @test_call_sret() #0 { %a = call i1024 @test_sret() @@ -23,8 +23,8 @@ define i1024 @test_call_sret() #0 { ; CHECK: mov x[[CALLERX8NUM:[0-9]+]], x8 ; CHECK: mov x8, sp ; CHECK-NEXT: bl _test_sret -; CHECK: ldr [[CALLERSRET1:q[0-9]+]], [sp] -; CHECK: str [[CALLERSRET1:q[0-9]+]], [x[[CALLERX8NUM]]] +; CHECK-NEXT: ldr [[CALLERSRET1:x[0-9]+]], [sp] +; CHECK: str [[CALLERSRET1:x[0-9]+]], [x[[CALLERX8NUM]]] ; CHECK: ret define i1024 @test_tailcall_sret() #0 { %a = tail call i1024 @test_sret() @@ -35,8 +35,8 @@ define i1024 @test_tailcall_sret() #0 { ; CHECK: mov x[[CALLERX8NUM:[0-9]+]], x8 ; CHECK: mov x8, sp ; CHECK-NEXT: blr x0 -; CHECK: ldr [[CALLERSRET1:q[0-9]+]], [sp] -; CHECK: str [[CALLERSRET1:q[0-9]+]], [x[[CALLERX8NUM]]] +; CHECK-NEXT: ldr [[CALLERSRET1:x[0-9]+]], [sp] +; CHECK: str [[CALLERSRET1:x[0-9]+]], [x[[CALLERX8NUM]]] ; CHECK: ret define i1024 @test_indirect_tailcall_sret(i1024 ()* %f) #0 { %a = tail call i1024 %f() diff --git a/test/CodeGen/AArch64/tailcall_misched_graph.ll b/test/CodeGen/AArch64/tailcall_misched_graph.ll index 7e76dac214a14..cb42fcced8dbb 100644 --- a/test/CodeGen/AArch64/tailcall_misched_graph.ll +++ b/test/CodeGen/AArch64/tailcall_misched_graph.ll @@ -26,9 +26,9 @@ declare void @callee2(i8*, i8*, i8*, i8*, i8*, ; CHECK: fi#-2: {{.*}} fixed, at location [SP+8] ; CHECK: fi#-1: {{.*}} fixed, at location [SP] -; CHECK: [[VRA:%vreg.*]] = LDRXui -; CHECK: [[VRB:%vreg.*]] = LDRXui -; CHECK: STRXui %vreg{{.*}}, +; CHECK: [[VRA:%.*]] = LDRXui +; CHECK: [[VRB:%.*]] = LDRXui +; CHECK: STRXui %{{.*}}, ; CHECK: STRXui [[VRB]], ; Make sure that there is an dependence edge between fi#-2 and fi#-4. @@ -40,5 +40,5 @@ declare void @callee2(i8*, i8*, i8*, i8*, i8*, ; CHECK: SU([[DEPSTOREB:.*]]): Ord Latency=0 ; CHECK: SU([[DEPSTOREA:.*]]): Ord Latency=0 -; CHECK: SU([[DEPSTOREA]]): STRXui %vreg{{.*}}, -; CHECK: SU([[DEPSTOREB]]): STRXui %vreg{{.*}}, +; CHECK: SU([[DEPSTOREA]]): STRXui %{{.*}}, +; CHECK: SU([[DEPSTOREB]]): STRXui %{{.*}}, diff --git a/test/CodeGen/AMDGPU/add.ll b/test/CodeGen/AMDGPU/add.ll index 6dcd7c234dc6d..ec3bf6dca57f3 100644 --- a/test/CodeGen/AMDGPU/add.ll +++ b/test/CodeGen/AMDGPU/add.ll @@ -1,14 +1,15 @@ -; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s -; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SIVI,FUNC %s +; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SIVI,FUNC %s +; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9,FUNC %s ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s -;FUNC-LABEL: {{^}}test1: -;EG: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; FUNC-LABEL: {{^}}s_add_i32: +; EG: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;SI: s_add_i32 s[[REG:[0-9]+]], {{s[0-9]+, s[0-9]+}} -;SI: v_mov_b32_e32 v[[REG]], s[[REG]] -;SI: buffer_store_dword v[[REG]], -define amdgpu_kernel void @test1(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { +; GCN: s_add_i32 s[[REG:[0-9]+]], {{s[0-9]+, s[0-9]+}} +; GCN: v_mov_b32_e32 v[[REG]], s[[REG]] +; GCN: buffer_store_dword v[[REG]], +define amdgpu_kernel void @s_add_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 { %b_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1 %a = load i32, i32 addrspace(1)* %in %b = load i32, i32 addrspace(1)* %b_ptr @@ -17,14 +18,13 @@ define amdgpu_kernel void @test1(i32 addrspace(1)* %out, i32 addrspace(1)* %in) ret void } -;FUNC-LABEL: {{^}}test2: -;EG: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;EG: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; FUNC-LABEL: {{^}}s_add_v2i32: +; EG: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; EG: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;SI: s_add_i32 s{{[0-9]+, s[0-9]+, s[0-9]+}} -;SI: s_add_i32 s{{[0-9]+, s[0-9]+, s[0-9]+}} - -define amdgpu_kernel void @test2(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) { +; GCN: s_add_i32 s{{[0-9]+, s[0-9]+, s[0-9]+}} +; GCN: s_add_i32 s{{[0-9]+, s[0-9]+, s[0-9]+}} +define amdgpu_kernel void @s_add_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) { %b_ptr = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %in, i32 1 %a = load <2 x i32>, <2 x i32> addrspace(1)* %in %b = load <2 x i32>, <2 x i32> addrspace(1)* %b_ptr @@ -33,18 +33,17 @@ define amdgpu_kernel void @test2(<2 x i32> addrspace(1)* %out, <2 x i32> addrspa ret void } -;FUNC-LABEL: {{^}}test4: -;EG: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;EG: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;EG: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;EG: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} - -;SI: s_add_i32 s{{[0-9]+, s[0-9]+, s[0-9]+}} -;SI: s_add_i32 s{{[0-9]+, s[0-9]+, s[0-9]+}} -;SI: s_add_i32 s{{[0-9]+, s[0-9]+, s[0-9]+}} -;SI: s_add_i32 s{{[0-9]+, s[0-9]+, s[0-9]+}} - -define amdgpu_kernel void @test4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { +; FUNC-LABEL: {{^}}s_add_v4i32: +; EG: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; EG: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; EG: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; EG: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} + +; GCN: s_add_i32 s{{[0-9]+, s[0-9]+, s[0-9]+}} +; GCN: s_add_i32 s{{[0-9]+, s[0-9]+, s[0-9]+}} +; GCN: s_add_i32 s{{[0-9]+, s[0-9]+, s[0-9]+}} +; GCN: s_add_i32 s{{[0-9]+, s[0-9]+, s[0-9]+}} +define amdgpu_kernel void @s_add_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { %b_ptr = getelementptr <4 x i32>, <4 x i32> addrspace(1)* %in, i32 1 %a = load <4 x i32>, <4 x i32> addrspace(1)* %in %b = load <4 x i32>, <4 x i32> addrspace(1)* %b_ptr @@ -53,7 +52,7 @@ define amdgpu_kernel void @test4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspa ret void } -; FUNC-LABEL: {{^}}test8: +; FUNC-LABEL: {{^}}s_add_v8i32: ; EG: ADD_INT ; EG: ADD_INT ; EG: ADD_INT @@ -63,22 +62,22 @@ define amdgpu_kernel void @test4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspa ; EG: ADD_INT ; EG: ADD_INT -; SI: s_add_i32 -; SI: s_add_i32 -; SI: s_add_i32 -; SI: s_add_i32 -; SI: s_add_i32 -; SI: s_add_i32 -; SI: s_add_i32 -; SI: s_add_i32 -define amdgpu_kernel void @test8(<8 x i32> addrspace(1)* %out, <8 x i32> %a, <8 x i32> %b) { +; GCN: s_add_i32 +; GCN: s_add_i32 +; GCN: s_add_i32 +; GCN: s_add_i32 +; GCN: s_add_i32 +; GCN: s_add_i32 +; GCN: s_add_i32 +; GCN: s_add_i32 +define amdgpu_kernel void @s_add_v8i32(<8 x i32> addrspace(1)* %out, <8 x i32> %a, <8 x i32> %b) { entry: %0 = add <8 x i32> %a, %b store <8 x i32> %0, <8 x i32> addrspace(1)* %out ret void } -; FUNC-LABEL: {{^}}test16: +; FUNC-LABEL: {{^}}s_add_v16i32: ; EG: ADD_INT ; EG: ADD_INT ; EG: ADD_INT @@ -96,32 +95,62 @@ entry: ; EG: ADD_INT ; EG: ADD_INT -; SI: s_add_i32 -; SI: s_add_i32 -; SI: s_add_i32 -; SI: s_add_i32 -; SI: s_add_i32 -; SI: s_add_i32 -; SI: s_add_i32 -; SI: s_add_i32 -; SI: s_add_i32 -; SI: s_add_i32 -; SI: s_add_i32 -; SI: s_add_i32 -; SI: s_add_i32 -; SI: s_add_i32 -; SI: s_add_i32 -; SI: s_add_i32 -define amdgpu_kernel void @test16(<16 x i32> addrspace(1)* %out, <16 x i32> %a, <16 x i32> %b) { +; GCN: s_add_i32 +; GCN: s_add_i32 +; GCN: s_add_i32 +; GCN: s_add_i32 +; GCN: s_add_i32 +; GCN: s_add_i32 +; GCN: s_add_i32 +; GCN: s_add_i32 +; GCN: s_add_i32 +; GCN: s_add_i32 +; GCN: s_add_i32 +; GCN: s_add_i32 +; GCN: s_add_i32 +; GCN: s_add_i32 +; GCN: s_add_i32 +; GCN: s_add_i32 +define amdgpu_kernel void @s_add_v16i32(<16 x i32> addrspace(1)* %out, <16 x i32> %a, <16 x i32> %b) { entry: %0 = add <16 x i32> %a, %b store <16 x i32> %0, <16 x i32> addrspace(1)* %out ret void } +; FUNC-LABEL: {{^}}v_add_i32: +; GCN: {{buffer|flat|global}}_load_dword [[A:v[0-9]+]] +; GCN: {{buffer|flat|global}}_load_dword [[B:v[0-9]+]] +; SIVI: v_add_{{i|u}}32_e32 v{{[0-9]+}}, vcc, [[B]], [[A]] +; GFX9: v_add_u32_e32 v{{[0-9]+}}, [[A]], [[B]] +define amdgpu_kernel void @v_add_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 { + %tid = call i32 @llvm.r600.read.tidig.x() + %gep = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 %tid + %b_ptr = getelementptr i32, i32 addrspace(1)* %gep, i32 1 + %a = load volatile i32, i32 addrspace(1)* %gep + %b = load volatile i32, i32 addrspace(1)* %b_ptr + %result = add i32 %a, %b + store i32 %result, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}v_add_imm_i32: +; GCN: {{buffer|flat|global}}_load_dword [[A:v[0-9]+]] +; SIVI: v_add_{{i|u}}32_e32 v{{[0-9]+}}, vcc, 0x7b, [[A]] +; GFX9: v_add_u32_e32 v{{[0-9]+}}, 0x7b, [[A]] +define amdgpu_kernel void @v_add_imm_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 { + %tid = call i32 @llvm.r600.read.tidig.x() + %gep = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 %tid + %b_ptr = getelementptr i32, i32 addrspace(1)* %gep, i32 1 + %a = load volatile i32, i32 addrspace(1)* %gep + %result = add i32 %a, 123 + store i32 %result, i32 addrspace(1)* %out + ret void +} + ; FUNC-LABEL: {{^}}add64: -; SI: s_add_u32 -; SI: s_addc_u32 +; GCN: s_add_u32 +; GCN: s_addc_u32 ; EG: MEM_RAT_CACHELESS STORE_RAW [[LO:T[0-9]+\.XY]] ; EG-DAG: ADD_INT {{[* ]*}} @@ -131,8 +160,8 @@ entry: ; EG-NOT: SUB define amdgpu_kernel void @add64(i64 addrspace(1)* %out, i64 %a, i64 %b) { entry: - %0 = add i64 %a, %b - store i64 %0, i64 addrspace(1)* %out + %add = add i64 %a, %b + store i64 %add, i64 addrspace(1)* %out ret void } @@ -142,7 +171,7 @@ entry: ; to a VGPR before doing the add. ; FUNC-LABEL: {{^}}add64_sgpr_vgpr: -; SI-NOT: v_addc_u32_e32 s +; GCN-NOT: v_addc_u32_e32 s ; EG: MEM_RAT_CACHELESS STORE_RAW [[LO:T[0-9]+\.XY]] ; EG-DAG: ADD_INT {{[* ]*}} @@ -160,8 +189,8 @@ entry: ; Test i64 add inside a branch. ; FUNC-LABEL: {{^}}add64_in_branch: -; SI: s_add_u32 -; SI: s_addc_u32 +; GCN: s_add_u32 +; GCN: s_addc_u32 ; EG: MEM_RAT_CACHELESS STORE_RAW [[LO:T[0-9]+\.XY]] ; EG-DAG: ADD_INT {{[* ]*}} @@ -187,3 +216,8 @@ endif: store i64 %3, i64 addrspace(1)* %out ret void } + +declare i32 @llvm.r600.read.tidig.x() #1 + +attributes #0 = { nounwind } +attributes #1 = { nounwind readnone speculatable } diff --git a/test/CodeGen/AMDGPU/adjust-writemask-invalid-copy.ll b/test/CodeGen/AMDGPU/adjust-writemask-invalid-copy.ll new file mode 100644 index 0000000000000..d8cf67af7b071 --- /dev/null +++ b/test/CodeGen/AMDGPU/adjust-writemask-invalid-copy.ll @@ -0,0 +1,51 @@ +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s + +; GCN-LABEL: {{^}}adjust_writemask_crash_0: +; GCN: image_get_lod v0, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}} dmask:0x2 +; GCN-NOT: v1 +; GCN-NOT: v0 +; GCN: buffer_store_dword v0 +define amdgpu_ps void @adjust_writemask_crash_0() #0 { +main_body: + %tmp = call <2 x float> @llvm.amdgcn.image.getlod.v2f32.v2f32.v8i32(<2 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 3, i1 false, i1 false, i1 false, i1 false, i1 false) + %tmp1 = bitcast <2 x float> %tmp to <2 x i32> + %tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <4 x i32> + %tmp3 = bitcast <4 x i32> %tmp2 to <4 x float> + %tmp4 = extractelement <4 x float> %tmp3, i32 0 + store volatile float %tmp4, float addrspace(1)* undef + ret void +} + +; GCN-LABEL: {{^}}adjust_writemask_crash_1: +; GCN: image_get_lod v0, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}} dmask:0x1 +; GCN-NOT: v1 +; GCN-NOT: v0 +; GCN: buffer_store_dword v0 +define amdgpu_ps void @adjust_writemask_crash_1() #0 { +main_body: + %tmp = call <2 x float> @llvm.amdgcn.image.getlod.v2f32.v2f32.v8i32(<2 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 3, i1 false, i1 false, i1 false, i1 false, i1 false) + %tmp1 = bitcast <2 x float> %tmp to <2 x i32> + %tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <4 x i32> + %tmp3 = bitcast <4 x i32> %tmp2 to <4 x float> + %tmp4 = extractelement <4 x float> %tmp3, i32 1 + store volatile float %tmp4, float addrspace(1)* undef + ret void +} + +define amdgpu_ps void @adjust_writemask_crash_0_v4() #0 { +main_body: + %tmp = call <4 x float> @llvm.amdgcn.image.getlod.v4f32.v2f32.v8i32(<2 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 5, i1 false, i1 false, i1 false, i1 false, i1 false) + %tmp1 = bitcast <4 x float> %tmp to <4 x i32> + %tmp2 = shufflevector <4 x i32> %tmp1, <4 x i32> undef, <4 x i32> + %tmp3 = bitcast <4 x i32> %tmp2 to <4 x float> + %tmp4 = extractelement <4 x float> %tmp3, i32 0 + store volatile float %tmp4, float addrspace(1)* undef + ret void +} + + +declare <2 x float> @llvm.amdgcn.image.getlod.v2f32.v2f32.v8i32(<2 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1 +declare <4 x float> @llvm.amdgcn.image.getlod.v4f32.v2f32.v8i32(<2 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #1 + +attributes #0 = { nounwind } +attributes #1 = { nounwind readonly } diff --git a/test/CodeGen/AMDGPU/branch-relaxation.ll b/test/CodeGen/AMDGPU/branch-relaxation.ll index 9edf439b5863b..023baf1407e77 100644 --- a/test/CodeGen/AMDGPU/branch-relaxation.ll +++ b/test/CodeGen/AMDGPU/branch-relaxation.ll @@ -24,7 +24,7 @@ declare i32 @llvm.amdgcn.workitem.id.x() #1 ; GCN-NEXT: s_cbranch_scc1 [[BB3:BB[0-9]+_[0-9]+]] -; GCN-NEXT: ; BB#1: ; %bb2 +; GCN-NEXT: ; %bb.1: ; %bb2 ; GCN-NEXT: ;;#ASMSTART ; GCN-NEXT: v_nop_e64 ; GCN-NEXT: v_nop_e64 @@ -275,7 +275,7 @@ bb4: } ; GCN-LABEL: {{^}}uniform_unconditional_min_long_backward_branch: -; GCN-NEXT: ; BB#0: ; %entry +; GCN-NEXT: ; %bb.0: ; %entry ; GCN-NEXT: [[LOOP:BB[0-9]_[0-9]+]]: ; %loop ; GCN-NEXT: ; =>This Inner Loop Header: Depth=1 @@ -311,7 +311,7 @@ loop: ; branch from %bb0 to %bb2 ; GCN-LABEL: {{^}}expand_requires_expand: -; GCN-NEXT: ; BB#0: ; %bb0 +; GCN-NEXT: ; %bb.0: ; %bb0 ; GCN: s_load_dword ; GCN: s_cmp_lt_i32 s{{[0-9]+}}, 0{{$}} ; GCN-NEXT: s_cbranch_scc0 [[BB1:BB[0-9]+_[0-9]+]] @@ -398,7 +398,7 @@ bb3: ; GCN: s_cmp_lg_u32 ; GCN: s_cbranch_scc1 [[ENDIF]] -; GCN-NEXT: ; BB#2: ; %if_uniform +; GCN-NEXT: ; %bb.2: ; %if_uniform ; GCN: buffer_store_dword ; GCN-NEXT: [[ENDIF]]: ; %endif diff --git a/test/CodeGen/AMDGPU/callee-frame-setup.ll b/test/CodeGen/AMDGPU/callee-frame-setup.ll index 9e01267150e53..88d165144f9d9 100644 --- a/test/CodeGen/AMDGPU/callee-frame-setup.ll +++ b/test/CodeGen/AMDGPU/callee-frame-setup.ll @@ -2,7 +2,7 @@ ; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=GFX9 %s ; GCN-LABEL: {{^}}callee_no_stack: -; GCN: ; BB#0: +; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt ; GCN-NEXT: s_setpc_b64 define void @callee_no_stack() #0 { @@ -10,7 +10,7 @@ define void @callee_no_stack() #0 { } ; GCN-LABEL: {{^}}callee_no_stack_no_fp_elim: -; GCN: ; BB#0: +; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt ; GCN-NEXT: s_setpc_b64 define void @callee_no_stack_no_fp_elim() #1 { @@ -20,7 +20,7 @@ define void @callee_no_stack_no_fp_elim() #1 { ; Requires frame pointer for access to local regular object. ; GCN-LABEL: {{^}}callee_with_stack: -; GCN: ; BB#0: +; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt ; GCN-NEXT: s_mov_b32 s5, s32 ; GCN-NEXT: v_mov_b32_e32 v0, 0{{$}} @@ -34,7 +34,7 @@ define void @callee_with_stack() #0 { } ; GCN-LABEL: {{^}}callee_with_stack_and_call: -; GCN: ; BB#0: +; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt ; GCN: s_mov_b32 s5, s32 ; GCN: buffer_store_dword v32, off, s[0:3], s5 offset:8 diff --git a/test/CodeGen/AMDGPU/cf-loop-on-constant.ll b/test/CodeGen/AMDGPU/cf-loop-on-constant.ll index 697f26b83a4df..1e0af2611b022 100644 --- a/test/CodeGen/AMDGPU/cf-loop-on-constant.ll +++ b/test/CodeGen/AMDGPU/cf-loop-on-constant.ll @@ -102,7 +102,7 @@ for.body: ; GCN: s_add_i32 s{{[0-9]+}}, s{{[0-9]+}}, 4 ; GCN: s_cbranch_vccnz [[LOOPBB]] -; GCN-NEXT: ; BB#2 +; GCN-NEXT: ; %bb.2 ; GCN-NEXT: s_endpgm define amdgpu_kernel void @loop_arg_0(float addrspace(3)* %ptr, i32 %n, i1 %cond) nounwind { entry: diff --git a/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll b/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll index 3eef06950a48f..071bcbcf81bfd 100644 --- a/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll +++ b/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll @@ -13,7 +13,7 @@ ; VGPR: workitem_private_segment_byte_size = 12{{$}} -; GCN: {{^}}; BB#0: +; GCN: {{^}}; %bb.0: ; GCN: s_mov_b32 m0, -1 ; GCN: ds_read_b32 [[LOAD0:v[0-9]+]] @@ -89,9 +89,9 @@ endif: } ; GCN-LABEL: {{^}}divergent_loop: -; VGPR: workitem_private_segment_byte_size = 16{{$}} +; VGPR: workitem_private_segment_byte_size = 12{{$}} -; GCN: {{^}}; BB#0: +; GCN: {{^}}; %bb.0: ; GCN: s_mov_b32 m0, -1 ; GCN: ds_read_b32 [[LOAD0:v[0-9]+]] @@ -123,10 +123,9 @@ endif: ; GCN: [[LOOP:BB[0-9]+_[0-9]+]]: ; GCN: buffer_load_dword v[[VAL_LOOP_RELOAD:[0-9]+]], off, s[0:3], s7 offset:4 ; 4-byte Folded Reload ; GCN: v_subrev_i32_e32 [[VAL_LOOP:v[0-9]+]], vcc, v{{[0-9]+}}, v[[VAL_LOOP_RELOAD]] -; GCN: v_cmp_ne_u32_e32 vcc, -; GCN: s_and_b64 vcc, exec, vcc +; GCN: s_cmp_lg_u32 s{{[0-9]+}}, s{{[0-9]+}} ; GCN: buffer_store_dword [[VAL_LOOP]], off, s[0:3], s7 offset:[[VAL_SUB_OFFSET:[0-9]+]] ; 4-byte Folded Spill -; GCN-NEXT: s_cbranch_vccnz [[LOOP]] +; GCN-NEXT: s_cbranch_scc1 [[LOOP]] ; GCN: [[END]]: @@ -168,7 +167,7 @@ end: } ; GCN-LABEL: {{^}}divergent_if_else_endif: -; GCN: {{^}}; BB#0: +; GCN: {{^}}; %bb.0: ; GCN: s_mov_b32 m0, -1 ; GCN: ds_read_b32 [[LOAD0:v[0-9]+]] diff --git a/test/CodeGen/AMDGPU/convergent-inlineasm.ll b/test/CodeGen/AMDGPU/convergent-inlineasm.ll index 0074a41e44cf8..80907bf1c1beb 100644 --- a/test/CodeGen/AMDGPU/convergent-inlineasm.ll +++ b/test/CodeGen/AMDGPU/convergent-inlineasm.ll @@ -2,7 +2,7 @@ declare i32 @llvm.amdgcn.workitem.id.x() #0 ; GCN-LABEL: {{^}}convergent_inlineasm: -; GCN: BB#0: +; GCN: %bb.0: ; GCN: v_cmp_ne_u32_e64 ; GCN: ; mask branch ; GCN: BB{{[0-9]+_[0-9]+}}: diff --git a/test/CodeGen/AMDGPU/ds-combine-large-stride.ll b/test/CodeGen/AMDGPU/ds-combine-large-stride.ll index c63887eaa8916..7dd1f90e91410 100644 --- a/test/CodeGen/AMDGPU/ds-combine-large-stride.ll +++ b/test/CodeGen/AMDGPU/ds-combine-large-stride.ll @@ -1,15 +1,18 @@ -; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s -; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX9 -check-prefix=GCN %s +; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI %s +; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s ; GCN-LABEL: ds_read32_combine_stride_400: ; GCN: s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0 ; GCN: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]] -; GCN-DAG: v_add{{(_co)?}}_u32_e32 [[B1:v[0-9]+]], vcc, 0x320, [[BASE]] -; GCN-DAG: v_add{{(_co)?}}_u32_e32 [[B2:v[0-9]+]], vcc, 0x640, [[BASE]] -; GCN-DAG: v_add{{(_co)?}}_u32_e32 [[B3:v[0-9]+]], vcc, 0x960, [[BASE]] -; GFX9-DAG: v_add{{(_co)?}}_u32_e32 [[B1:v[0-9]+]], vcc, 0x320, [[BASE]] -; GFX9-DAG: v_add{{(_co)?}}_u32_e32 [[B2:v[0-9]+]], vcc, 0x640, [[BASE]] -; GFX9-DAG: v_add{{(_co)?}}_u32_e32 [[B3:v[0-9]+]], vcc, 0x960, [[BASE]] + +; VI-DAG: v_add_u32_e32 [[B1:v[0-9]+]], vcc, 0x320, [[BASE]] +; VI-DAG: v_add_u32_e32 [[B2:v[0-9]+]], vcc, 0x640, [[BASE]] +; VI-DAG: v_add_u32_e32 [[B3:v[0-9]+]], vcc, 0x960, [[BASE]] + +; GFX9-DAG: v_add_u32_e32 [[B1:v[0-9]+]], 0x320, [[BASE]] +; GFX9-DAG: v_add_u32_e32 [[B2:v[0-9]+]], 0x640, [[BASE]] +; GFX9-DAG: v_add_u32_e32 [[B3:v[0-9]+]], 0x960, [[BASE]] + ; GCN-DAG: ds_read2_b32 v[{{[0-9]+:[0-9]+}}], [[BASE]] offset1:100 ; GCN-DAG: ds_read2_b32 v[{{[0-9]+:[0-9]+}}], [[B1]] offset1:100 ; GCN-DAG: ds_read2_b32 v[{{[0-9]+:[0-9]+}}], [[B2]] offset1:100 @@ -46,12 +49,15 @@ bb: ; GCN-LABEL: ds_read32_combine_stride_400_back: ; GCN: s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0 ; GCN: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]] -; GCN-DAG: v_add{{(_co)?}}_u32_e32 [[B1:v[0-9]+]], vcc, 0x320, [[BASE]] -; GCN-DAG: v_add{{(_co)?}}_u32_e32 [[B2:v[0-9]+]], vcc, 0x640, [[BASE]] -; GCN-DAG: v_add{{(_co)?}}_u32_e32 [[B3:v[0-9]+]], vcc, 0x960, [[BASE]] -; GFX9-DAG: v_add{{(_co)?}}_u32_e32 [[B1:v[0-9]+]], vcc, 0x320, [[BASE]] -; GFX9-DAG: v_add{{(_co)?}}_u32_e32 [[B2:v[0-9]+]], vcc, 0x640, [[BASE]] -; GFX9-DAG: v_add{{(_co)?}}_u32_e32 [[B3:v[0-9]+]], vcc, 0x960, [[BASE]] + +; VI-DAG: v_add_u32_e32 [[B1:v[0-9]+]], vcc, 0x320, [[BASE]] +; VI-DAG: v_add_u32_e32 [[B2:v[0-9]+]], vcc, 0x640, [[BASE]] +; VI-DAG: v_add_u32_e32 [[B3:v[0-9]+]], vcc, 0x960, [[BASE]] + +; GFX9-DAG: v_add_u32_e32 [[B1:v[0-9]+]], 0x320, [[BASE]] +; GFX9-DAG: v_add_u32_e32 [[B2:v[0-9]+]], 0x640, [[BASE]] +; GFX9-DAG: v_add_u32_e32 [[B3:v[0-9]+]], 0x960, [[BASE]] + ; GCN-DAG: ds_read2_b32 v[{{[0-9]+:[0-9]+}}], [[BASE]] offset1:100 ; GCN-DAG: ds_read2_b32 v[{{[0-9]+:[0-9]+}}], [[B1]] offset1:100 ; GCN-DAG: ds_read2_b32 v[{{[0-9]+:[0-9]+}}], [[B2]] offset1:100 @@ -124,12 +130,15 @@ bb: ; GCN-LABEL: ds_read32_combine_stride_8192_shifted: ; GCN: s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0 ; GCN: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]] -; GCN-DAG: v_add{{(_co)?}}_u32_e32 [[B1:v[0-9]+]], vcc, 8, [[BASE]] -; GCN-DAG: v_add{{(_co)?}}_u32_e32 [[B2:v[0-9]+]], vcc, 0x4008, [[BASE]] -; GCN-DAG: v_add{{(_co)?}}_u32_e32 [[B3:v[0-9]+]], vcc, 0x8008, [[BASE]] -; GFX9-DAG: v_add{{(_co)?}}_u32_e32 [[B1:v[0-9]+]], vcc, 8, [[BASE]] -; GFX9-DAG: v_add{{(_co)?}}_u32_e32 [[B2:v[0-9]+]], vcc, 0x4008, [[BASE]] -; GFX9-DAG: v_add{{(_co)?}}_u32_e32 [[B3:v[0-9]+]], vcc, 0x8008, [[BASE]] + +; VI-DAG: v_add_u32_e32 [[B1:v[0-9]+]], vcc, 8, [[BASE]] +; VI-DAG: v_add_u32_e32 [[B2:v[0-9]+]], vcc, 0x4008, [[BASE]] +; VI-DAG: v_add_u32_e32 [[B3:v[0-9]+]], vcc, 0x8008, [[BASE]] + +; GFX9-DAG: v_add_u32_e32 [[B1:v[0-9]+]], 8, [[BASE]] +; GFX9-DAG: v_add_u32_e32 [[B2:v[0-9]+]], 0x4008, [[BASE]] +; GFX9-DAG: v_add_u32_e32 [[B3:v[0-9]+]], 0x8008, [[BASE]] + ; GCN-DAG: ds_read2st64_b32 v[{{[0-9]+:[0-9]+}}], [[B1]] offset1:32 ; GCN-DAG: ds_read2st64_b32 v[{{[0-9]+:[0-9]+}}], [[B2]] offset1:32 ; GCN-DAG: ds_read2st64_b32 v[{{[0-9]+:[0-9]+}}], [[B3]] offset1:32 @@ -160,8 +169,10 @@ bb: ; GCN-LABEL: ds_read64_combine_stride_400: ; GCN: s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0 ; GCN: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]] -; GCN-DAG: v_add{{(_co)?}}_u32_e32 [[B1:v[0-9]+]], vcc, 0x960, [[BASE]] -; GFX9-DAG: v_add{{(_co)?}}_u32_e32 [[B1:v[0-9]+]], vcc, 0x960, [[BASE]] + +; VI-DAG: v_add_u32_e32 [[B1:v[0-9]+]], vcc, 0x960, [[BASE]] +; GFX9-DAG: v_add_u32_e32 [[B1:v[0-9]+]], 0x960, [[BASE]] + ; GCN-DAG: ds_read2_b64 v[{{[0-9]+:[0-9]+}}], [[BASE]] offset1:50 ; GCN-DAG: ds_read2_b64 v[{{[0-9]+:[0-9]+}}], [[BASE]] offset0:100 offset1:150 ; GCN-DAG: ds_read2_b64 v[{{[0-9]+:[0-9]+}}], [[BASE]] offset0:200 offset1:250 @@ -198,12 +209,15 @@ bb: ; GCN-LABEL: ds_read64_combine_stride_8192_shifted: ; GCN: s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0 ; GCN: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]] -; GCN-DAG: v_add{{(_co)?}}_u32_e32 [[B1:v[0-9]+]], vcc, 8, [[BASE]] -; GCN-DAG: v_add{{(_co)?}}_u32_e32 [[B2:v[0-9]+]], vcc, 0x4008, [[BASE]] -; GCN-DAG: v_add{{(_co)?}}_u32_e32 [[B3:v[0-9]+]], vcc, 0x8008, [[BASE]] -; GFX9-DAG: v_add{{(_co)?}}_u32_e32 [[B1:v[0-9]+]], vcc, 8, [[BASE]] -; GFX9-DAG: v_add{{(_co)?}}_u32_e32 [[B2:v[0-9]+]], vcc, 0x4008, [[BASE]] -; GFX9-DAG: v_add{{(_co)?}}_u32_e32 [[B3:v[0-9]+]], vcc, 0x8008, [[BASE]] + +; VI-DAG: v_add_u32_e32 [[B1:v[0-9]+]], vcc, 8, [[BASE]] +; VI-DAG: v_add_u32_e32 [[B2:v[0-9]+]], vcc, 0x4008, [[BASE]] +; VI-DAG: v_add_u32_e32 [[B3:v[0-9]+]], vcc, 0x8008, [[BASE]] + +; GFX9-DAG: v_add_u32_e32 [[B1:v[0-9]+]], 8, [[BASE]] +; GFX9-DAG: v_add_u32_e32 [[B2:v[0-9]+]], 0x4008, [[BASE]] +; GFX9-DAG: v_add_u32_e32 [[B3:v[0-9]+]], 0x8008, [[BASE]] + ; GCN-DAG: ds_read2st64_b64 v[{{[0-9]+:[0-9]+}}], [[B1]] offset1:16 ; GCN-DAG: ds_read2st64_b64 v[{{[0-9]+:[0-9]+}}], [[B2]] offset1:16 ; GCN-DAG: ds_read2st64_b64 v[{{[0-9]+:[0-9]+}}], [[B3]] offset1:16 @@ -234,12 +248,15 @@ bb: ; GCN-LABEL: ds_write32_combine_stride_400: ; GCN: s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0 ; GCN: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]] -; GCN-DAG: v_add{{(_co)?}}_u32_e32 [[B1:v[0-9]+]], vcc, 0x320, [[BASE]] -; GCN-DAG: v_add{{(_co)?}}_u32_e32 [[B2:v[0-9]+]], vcc, 0x640, [[BASE]] -; GCN-DAG: v_add{{(_co)?}}_u32_e32 [[B3:v[0-9]+]], vcc, 0x960, [[BASE]] -; GFX9-DAG: v_add{{(_co)?}}_u32_e32 [[B1:v[0-9]+]], vcc, 0x320, [[BASE]] -; GFX9-DAG: v_add{{(_co)?}}_u32_e32 [[B2:v[0-9]+]], vcc, 0x640, [[BASE]] -; GFX9-DAG: v_add{{(_co)?}}_u32_e32 [[B3:v[0-9]+]], vcc, 0x960, [[BASE]] + +; VI-DAG: v_add_u32_e32 [[B1:v[0-9]+]], vcc, 0x320, [[BASE]] +; VI-DAG: v_add_u32_e32 [[B2:v[0-9]+]], vcc, 0x640, [[BASE]] +; VI-DAG: v_add_u32_e32 [[B3:v[0-9]+]], vcc, 0x960, [[BASE]] + +; GFX9-DAG: v_add_u32_e32 [[B1:v[0-9]+]], 0x320, [[BASE]] +; GFX9-DAG: v_add_u32_e32 [[B2:v[0-9]+]], 0x640, [[BASE]] +; GFX9-DAG: v_add_u32_e32 [[B3:v[0-9]+]], 0x960, [[BASE]] + ; GCN-DAG: ds_write2_b32 [[BASE]], v{{[0-9]+}}, v{{[0-9]+}} offset1:100 ; GCN-DAG: ds_write2_b32 [[B1]], v{{[0-9]+}}, v{{[0-9]+}} offset1:100 ; GCN-DAG: ds_write2_b32 [[B2]], v{{[0-9]+}}, v{{[0-9]+}} offset1:100 @@ -267,12 +284,15 @@ bb: ; GCN-LABEL: ds_write32_combine_stride_400_back: ; GCN: s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0 ; GCN: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]] -; GCN-DAG: v_add{{(_co)?}}_u32_e32 [[B1:v[0-9]+]], vcc, 0x320, [[BASE]] -; GCN-DAG: v_add{{(_co)?}}_u32_e32 [[B2:v[0-9]+]], vcc, 0x640, [[BASE]] -; GCN-DAG: v_add{{(_co)?}}_u32_e32 [[B3:v[0-9]+]], vcc, 0x960, [[BASE]] -; GFX9-DAG: v_add{{(_co)?}}_u32_e32 [[B1:v[0-9]+]], vcc, 0x320, [[BASE]] -; GFX9-DAG: v_add{{(_co)?}}_u32_e32 [[B2:v[0-9]+]], vcc, 0x640, [[BASE]] -; GFX9-DAG: v_add{{(_co)?}}_u32_e32 [[B3:v[0-9]+]], vcc, 0x960, [[BASE]] + +; VI-DAG: v_add_u32_e32 [[B1:v[0-9]+]], vcc, 0x320, [[BASE]] +; VI-DAG: v_add_u32_e32 [[B2:v[0-9]+]], vcc, 0x640, [[BASE]] +; VI-DAG: v_add_u32_e32 [[B3:v[0-9]+]], vcc, 0x960, [[BASE]] + +; GFX9-DAG: v_add_u32_e32 [[B1:v[0-9]+]], 0x320, [[BASE]] +; GFX9-DAG: v_add_u32_e32 [[B2:v[0-9]+]], 0x640, [[BASE]] +; GFX9-DAG: v_add_u32_e32 [[B3:v[0-9]+]], 0x960, [[BASE]] + ; GCN-DAG: ds_write2_b32 [[BASE]], v{{[0-9]+}}, v{{[0-9]+}} offset1:100 ; GCN-DAG: ds_write2_b32 [[B1]], v{{[0-9]+}}, v{{[0-9]+}} offset1:100 ; GCN-DAG: ds_write2_b32 [[B2]], v{{[0-9]+}}, v{{[0-9]+}} offset1:100 @@ -327,12 +347,15 @@ bb: ; GCN-LABEL: ds_write32_combine_stride_8192_shifted: ; GCN: s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0 ; GCN: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]] -; GCN-DAG: v_add{{(_co)?}}_u32_e32 [[B1:v[0-9]+]], vcc, 4, [[BASE]] -; GCN-DAG: v_add{{(_co)?}}_u32_e32 [[B2:v[0-9]+]], vcc, 0x4004, [[BASE]] -; GCN-DAG: v_add{{(_co)?}}_u32_e32 [[B3:v[0-9]+]], vcc, 0x8004, [[BASE]] -; GFX9-DAG: v_add{{(_co)?}}_u32_e32 [[B1:v[0-9]+]], vcc, 4, [[BASE]] -; GFX9-DAG: v_add{{(_co)?}}_u32_e32 [[B2:v[0-9]+]], vcc, 0x4004, [[BASE]] -; GFX9-DAG: v_add{{(_co)?}}_u32_e32 [[B3:v[0-9]+]], vcc, 0x8004, [[BASE]] + +; VI-DAG: v_add_u32_e32 [[B1:v[0-9]+]], vcc, 4, [[BASE]] +; VI-DAG: v_add_u32_e32 [[B2:v[0-9]+]], vcc, 0x4004, [[BASE]] +; VI-DAG: v_add_u32_e32 [[B3:v[0-9]+]], vcc, 0x8004, [[BASE]] + +; GFX9-DAG: v_add_u32_e32 [[B1:v[0-9]+]], 4, [[BASE]] +; GFX9-DAG: v_add_u32_e32 [[B2:v[0-9]+]], 0x4004, [[BASE]] +; GFX9-DAG: v_add_u32_e32 [[B3:v[0-9]+]], 0x8004, [[BASE]] + ; GCN-DAG: ds_write2st64_b32 [[B1]], v{{[0-9]+}}, v{{[0-9]+}} offset1:32 ; GCN-DAG: ds_write2st64_b32 [[B2]], v{{[0-9]+}}, v{{[0-9]+}} offset1:32 ; GCN-DAG: ds_write2st64_b32 [[B3]], v{{[0-9]+}}, v{{[0-9]+}} offset1:32 @@ -356,8 +379,10 @@ bb: ; GCN-LABEL: ds_write64_combine_stride_400: ; GCN: s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0 ; GCN: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]] -; GCN-DAG: v_add{{(_co)?}}_u32_e32 [[B1:v[0-9]+]], vcc, 0x960, [[BASE]] -; GFX9-DAG: v_add{{(_co)?}}_u32_e32 [[B1:v[0-9]+]], vcc, 0x960, [[BASE]] + +; VI-DAG: v_add_u32_e32 [[B1:v[0-9]+]], vcc, 0x960, [[BASE]] +; GFX9-DAG: v_add_u32_e32 [[B1:v[0-9]+]], 0x960, [[BASE]] + ; GCN-DAG: ds_write2_b64 [[BASE]], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] offset1:50 ; GCN-DAG: ds_write2_b64 [[BASE]], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] offset0:100 offset1:150 ; GCN-DAG: ds_write2_b64 [[BASE]], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] offset0:200 offset1:250 @@ -385,12 +410,15 @@ bb: ; GCN-LABEL: ds_write64_combine_stride_8192_shifted: ; GCN: s_load_dword [[ARG:s[0-9]+]], s[4:5], 0x0 ; GCN: v_mov_b32_e32 [[BASE:v[0-9]+]], [[ARG]] -; GCN-DAG: v_add{{(_co)?}}_u32_e32 [[B1:v[0-9]+]], vcc, 8, [[BASE]] -; GCN-DAG: v_add{{(_co)?}}_u32_e32 [[B2:v[0-9]+]], vcc, 0x4008, [[BASE]] -; GCN-DAG: v_add{{(_co)?}}_u32_e32 [[B3:v[0-9]+]], vcc, 0x8008, [[BASE]] -; GFX9-DAG: v_add{{(_co)?}}_u32_e32 [[B1:v[0-9]+]], vcc, 8, [[BASE]] -; GFX9-DAG: v_add{{(_co)?}}_u32_e32 [[B2:v[0-9]+]], vcc, 0x4008, [[BASE]] -; GFX9-DAG: v_add{{(_co)?}}_u32_e32 [[B3:v[0-9]+]], vcc, 0x8008, [[BASE]] + +; VI-DAG: v_add_u32_e32 [[B1:v[0-9]+]], vcc, 8, [[BASE]] +; VI-DAG: v_add_u32_e32 [[B2:v[0-9]+]], vcc, 0x4008, [[BASE]] +; VI-DAG: v_add_u32_e32 [[B3:v[0-9]+]], vcc, 0x8008, [[BASE]] + +; GFX9-DAG: v_add_u32_e32 [[B1:v[0-9]+]], 8, [[BASE]] +; GFX9-DAG: v_add_u32_e32 [[B2:v[0-9]+]], 0x4008, [[BASE]] +; GFX9-DAG: v_add_u32_e32 [[B3:v[0-9]+]], 0x8008, [[BASE]] + ; GCN-DAG: ds_write2st64_b64 [[B1]], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] offset1:16 ; GCN-DAG: ds_write2st64_b64 [[B2]], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] offset1:16 ; GCN-DAG: ds_write2st64_b64 [[B3]], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] offset1:16 diff --git a/test/CodeGen/AMDGPU/ds-sub-offset.ll b/test/CodeGen/AMDGPU/ds-sub-offset.ll index d74bd5aa15ac1..05d8dc0b9a045 100644 --- a/test/CodeGen/AMDGPU/ds-sub-offset.ll +++ b/test/CodeGen/AMDGPU/ds-sub-offset.ll @@ -1,4 +1,5 @@ -; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=CI %s +; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CI %s +; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s declare i32 @llvm.amdgcn.workitem.id.x() #0 @@ -6,7 +7,8 @@ declare i32 @llvm.amdgcn.workitem.id.x() #0 ; GCN-LABEL: {{^}}write_ds_sub0_offset0_global: ; GCN: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], 2, v0 -; GCN: v_sub_i32_e32 [[BASEPTR:v[0-9]+]], vcc, 0, [[SHL]] +; CI: v_sub_i32_e32 [[BASEPTR:v[0-9]+]], vcc, 0, [[SHL]] +; GFX9: v_sub_u32_e32 [[BASEPTR:v[0-9]+]], 0, [[SHL]] ; GCN: v_mov_b32_e32 [[VAL:v[0-9]+]], 0x7b ; GCN: ds_write_b32 [[BASEPTR]], [[VAL]] offset:12 define amdgpu_kernel void @write_ds_sub0_offset0_global() #0 { @@ -21,7 +23,8 @@ entry: ; GCN-LABEL: {{^}}add_x_shl_neg_to_sub_max_offset: ; GCN-DAG: v_lshlrev_b32_e32 [[SCALED:v[0-9]+]], 2, v0 -; GCN-DAG: v_sub_i32_e32 [[NEG:v[0-9]+]], vcc, 0, [[SCALED]] +; CI-DAG: v_sub_i32_e32 [[NEG:v[0-9]+]], vcc, 0, [[SCALED]] +; GFX9-DAG: v_sub_u32_e32 [[NEG:v[0-9]+]], 0, [[SCALED]] ; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 13 ; GCN: ds_write_b8 [[NEG]], [[K]] offset:65535 define amdgpu_kernel void @add_x_shl_neg_to_sub_max_offset() #1 { @@ -36,7 +39,8 @@ define amdgpu_kernel void @add_x_shl_neg_to_sub_max_offset() #1 { ; GCN-LABEL: {{^}}add_x_shl_neg_to_sub_max_offset_p1: ; GCN-DAG: v_lshlrev_b32_e32 [[SCALED:v[0-9]+]], 2, v0 -; GCN-DAG: v_sub_i32_e32 [[NEG:v[0-9]+]], vcc, 0x10000, [[SCALED]] +; CI-DAG: v_sub_i32_e32 [[NEG:v[0-9]+]], vcc, 0x10000, [[SCALED]] +; GFX9-DAG: v_sub_u32_e32 [[NEG:v[0-9]+]], 0x10000, [[SCALED]] ; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 13 ; GCN: ds_write_b8 [[NEG]], [[K]]{{$}} define amdgpu_kernel void @add_x_shl_neg_to_sub_max_offset_p1() #1 { @@ -51,7 +55,8 @@ define amdgpu_kernel void @add_x_shl_neg_to_sub_max_offset_p1() #1 { ; GCN-LABEL: {{^}}add_x_shl_neg_to_sub_multi_use: ; GCN-DAG: v_lshlrev_b32_e32 [[SCALED:v[0-9]+]], 2, v0 -; GCN-DAG: v_sub_i32_e32 [[NEG:v[0-9]+]], vcc, 0, [[SCALED]] +; CI-DAG: v_sub_i32_e32 [[NEG:v[0-9]+]], vcc, 0, [[SCALED]] +; GFX9-DAG: v_sub_u32_e32 [[NEG:v[0-9]+]], 0, [[SCALED]] ; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 13 ; GCN-NOT: v_sub ; GCN: ds_write_b32 [[NEG]], [[K]] offset:123{{$}} @@ -73,7 +78,8 @@ define amdgpu_kernel void @add_x_shl_neg_to_sub_multi_use() #1 { ; GCN-LABEL: {{^}}add_x_shl_neg_to_sub_multi_use_same_offset: ; GCN-DAG: v_lshlrev_b32_e32 [[SCALED:v[0-9]+]], 2, v0 -; GCN-DAG: v_sub_i32_e32 [[NEG:v[0-9]+]], vcc, 0, [[SCALED]] +; CI-DAG: v_sub_i32_e32 [[NEG:v[0-9]+]], vcc, 0, [[SCALED]] +; GFX9-DAG: v_sub_u32_e32 [[NEG:v[0-9]+]], 0, [[SCALED]] ; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 13 ; GCN-NOT: v_sub ; GCN: ds_write_b32 [[NEG]], [[K]] offset:123{{$}} @@ -93,7 +99,8 @@ define amdgpu_kernel void @add_x_shl_neg_to_sub_multi_use_same_offset() #1 { ; GCN-LABEL: {{^}}add_x_shl_neg_to_sub_misaligned_i64_max_offset: ; GCN-DAG: v_lshlrev_b32_e32 [[SCALED:v[0-9]+]], 2, v0 -; GCN-DAG: v_sub_i32_e32 [[NEG:v[0-9]+]], vcc, 0, [[SCALED]] +; CI-DAG: v_sub_i32_e32 [[NEG:v[0-9]+]], vcc, 0, [[SCALED]] +; GFX9-DAG: v_sub_u32_e32 [[NEG:v[0-9]+]], 0, [[SCALED]] ; GCN: ds_write2_b32 [[NEG]], {{v[0-9]+}}, {{v[0-9]+}} offset0:254 offset1:255 define amdgpu_kernel void @add_x_shl_neg_to_sub_misaligned_i64_max_offset() #1 { %x.i = call i32 @llvm.amdgcn.workitem.id.x() #0 @@ -107,7 +114,8 @@ define amdgpu_kernel void @add_x_shl_neg_to_sub_misaligned_i64_max_offset() #1 { ; GCN-LABEL: {{^}}add_x_shl_neg_to_sub_misaligned_i64_max_offset_p1: ; GCN-DAG: v_lshlrev_b32_e32 [[SCALED:v[0-9]+]], 2, v0 -; GCN-DAG: v_sub_i32_e32 [[NEG:v[0-9]+]], vcc, 0x3fc, [[SCALED]] +; CI-DAG: v_sub_i32_e32 [[NEG:v[0-9]+]], vcc, 0x3fc, [[SCALED]] +; GFX9-DAG: v_sub_u32_e32 [[NEG:v[0-9]+]], 0x3fc, [[SCALED]] ; GCN: ds_write2_b32 [[NEG]], {{v[0-9]+}}, {{v[0-9]+}} offset1:1{{$}} define amdgpu_kernel void @add_x_shl_neg_to_sub_misaligned_i64_max_offset_p1() #1 { %x.i = call i32 @llvm.amdgcn.workitem.id.x() #0 diff --git a/test/CodeGen/AMDGPU/ds_read2.ll b/test/CodeGen/AMDGPU/ds_read2.ll index 96eb6ec4e7836..131afb0c6aec6 100644 --- a/test/CodeGen/AMDGPU/ds_read2.ll +++ b/test/CodeGen/AMDGPU/ds_read2.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs -mattr=+load-store-opt < %s | FileCheck -strict-whitespace -check-prefixes=GCN,CI %s -; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -mattr=+load-store-opt < %s | FileCheck -strict-whitespace -check-prefixes=GCN,GFX9 %s +; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs -mattr=+load-store-opt < %s | FileCheck -enable-var-scope -strict-whitespace -check-prefixes=GCN,CI %s +; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -mattr=+load-store-opt,+flat-for-global < %s | FileCheck -enable-var-scope -strict-whitespace -check-prefixes=GCN,GFX9 %s ; FIXME: We don't get cases where the address was an SGPR because we ; get a copy to the address register for each one. @@ -617,8 +617,9 @@ declare i32 @llvm.amdgcn.workgroup.id.x() #1 declare i32 @llvm.amdgcn.workgroup.id.y() #1 declare i32 @llvm.amdgcn.workitem.id.x() #1 declare i32 @llvm.amdgcn.workitem.id.y() #1 + declare void @llvm.amdgcn.s.barrier() #2 attributes #0 = { nounwind } -attributes #1 = { nounwind readnone } +attributes #1 = { nounwind readnone speculatable } attributes #2 = { convergent nounwind } diff --git a/test/CodeGen/AMDGPU/ds_read2st64.ll b/test/CodeGen/AMDGPU/ds_read2st64.ll index c7c6b1615d9ba..c09dca4635f91 100644 --- a/test/CodeGen/AMDGPU/ds_read2st64.ll +++ b/test/CodeGen/AMDGPU/ds_read2st64.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs -mattr=+load-store-opt < %s | FileCheck -check-prefixes=GCN,CI %s -; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -mattr=+load-store-opt < %s | FileCheck -check-prefixes=GCN,GFX9 %s +; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs -mattr=+load-store-opt < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CI %s +; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -mattr=+load-store-opt < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s @lds = addrspace(3) global [512 x float] undef, align 4 @lds.f64 = addrspace(3) global [512 x double] undef, align 8 @@ -78,7 +78,7 @@ define amdgpu_kernel void @simple_read2st64_f32_max_offset(float addrspace(1)* % ; GFX9-NOT: m0 ; GCN-NOT: ds_read2st64_b32 -; GCN-DAG: v_add{{(_co)?}}_{{i|u}}32_e32 [[BIGADD:v[0-9]+]], vcc, 0x10000, {{v[0-9]+}} +; GCN-DAG: v_add_{{i|u}}32_e32 [[BIGADD:v[0-9]+]], {{(vcc, )?}}0x10000, {{v[0-9]+}} ; GCN-DAG: ds_read_b32 {{v[0-9]+}}, {{v[0-9]+}} offset:256 ; GCN-DAG: ds_read_b32 {{v[0-9]+}}, [[BIGADD]]{{$}} ; GCN: s_endpgm @@ -234,7 +234,7 @@ define amdgpu_kernel void @simple_read2st64_f64_max_offset(double addrspace(1)* ; GCN-NOT: ds_read2st64_b64 ; GCN-DAG: ds_read_b64 {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}} offset:512 -; GCN-DAG: v_add_{{(co_)?}}{{i|u}}32_e32 [[BIGADD:v[0-9]+]], vcc, 0x10000, {{v[0-9]+}} +; GCN-DAG: v_add_{{i|u}}32_e32 [[BIGADD:v[0-9]+]], {{(vcc, )?}}0x10000, {{v[0-9]+}} ; GCN: ds_read_b64 {{v\[[0-9]+:[0-9]+\]}}, [[BIGADD]] ; GCN: s_endpgm define amdgpu_kernel void @simple_read2st64_f64_over_max_offset(double addrspace(1)* %out, double addrspace(3)* %lds) #0 { diff --git a/test/CodeGen/AMDGPU/ds_write2.ll b/test/CodeGen/AMDGPU/ds_write2.ll index 5f6c13995007b..7cb070c12b65d 100644 --- a/test/CodeGen/AMDGPU/ds_write2.ll +++ b/test/CodeGen/AMDGPU/ds_write2.ll @@ -1,15 +1,14 @@ -; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs -mattr=+load-store-opt < %s | FileCheck -strict-whitespace -check-prefixes=GCN,CI %s -; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -mattr=+load-store-opt < %s | FileCheck -strict-whitespace -check-prefixes=GCN,GFX9 %s +; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs -mattr=+load-store-opt < %s | FileCheck -enable-var-scope -strict-whitespace -check-prefixes=GCN,CI %s +; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -mattr=+load-store-opt,+flat-for-global < %s | FileCheck -enable-var-scope -strict-whitespace -check-prefixes=GCN,GFX9 %s @lds = addrspace(3) global [512 x float] undef, align 4 @lds.f64 = addrspace(3) global [512 x double] undef, align 8 - ; GCN-LABEL: {{^}}simple_write2_one_val_f32: ; CI-DAG: s_mov_b32 m0 ; GFX9-NOT: m0 -; GCN-DAG: {{buffer|global}}_load_dword [[VAL:v[0-9]+]] +; GCN-DAG: {{buffer|flat|global}}_load_dword [[VAL:v[0-9]+]] ; GCN-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}} ; GCN: ds_write2_b32 [[VPTR]], [[VAL]], [[VAL]] offset1:8 ; GCN: s_endpgm @@ -108,6 +107,7 @@ define amdgpu_kernel void @simple_write2_two_val_f32_volatile_1(float addrspace( ; GFX9: global_load_dwordx2 v{{\[}}[[VAL0:[0-9]+]]:{{[0-9]+\]}} ; GFX9: global_load_dwordx2 v{{\[[0-9]+}}:[[VAL1:[0-9]+]]{{\]}} + ; GCN: ds_write2_b32 [[VPTR]], v[[VAL0]], v[[VAL1]] offset1:8 ; GCN: s_endpgm define amdgpu_kernel void @simple_write2_two_val_subreg2_mixed_f32(float addrspace(1)* %C, <2 x float> addrspace(1)* %in) #0 { @@ -502,5 +502,5 @@ declare i32 @llvm.amdgcn.workitem.id.x() #1 declare i32 @llvm.amdgcn.workitem.id.y() #1 attributes #0 = { nounwind } -attributes #1 = { nounwind readnone } +attributes #1 = { nounwind readnone speculatable } attributes #2 = { convergent nounwind } diff --git a/test/CodeGen/AMDGPU/ds_write2st64.ll b/test/CodeGen/AMDGPU/ds_write2st64.ll index 26e12d5017221..54f2500afab4f 100644 --- a/test/CodeGen/AMDGPU/ds_write2st64.ll +++ b/test/CodeGen/AMDGPU/ds_write2st64.ll @@ -63,7 +63,7 @@ define amdgpu_kernel void @simple_write2st64_two_val_f32_2_5(float addrspace(1)* ; GFX9-DAG: global_load_dword [[VAL1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, off offset:4 ; GCN-DAG: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], 2, v{{[0-9]+}} -; GCN: v_add{{(_co)?}}_{{i|u}}32_e32 [[VPTR:v[0-9]+]], vcc, s{{[0-9]+}}, [[SHL]] +; GCN: v_add_{{i|u}}32_e32 [[VPTR:v[0-9]+]], {{(vcc, )?}}s{{[0-9]+}}, [[SHL]] ; GCN: ds_write2st64_b32 [[VPTR]], [[VAL0]], [[VAL1]] offset1:255 ; GCN: s_endpgm define amdgpu_kernel void @simple_write2st64_two_val_max_offset_f32(float addrspace(1)* %C, float addrspace(1)* %in, float addrspace(3)* %lds) #0 { @@ -91,7 +91,7 @@ define amdgpu_kernel void @simple_write2st64_two_val_max_offset_f32(float addrsp ; GFX9-DAG: global_load_dwordx2 [[VAL1:v\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, off offset:8 ; GCN-DAG: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], 3, v{{[0-9]+}} -; GCN: v_add_{{(co_)?}}{{i|u}}32_e32 [[VPTR:v[0-9]+]], vcc, s{{[0-9]+}}, [[SHL]] +; GCN: v_add_{{i|u}}32_e32 [[VPTR:v[0-9]+]], {{(vcc, )?}}s{{[0-9]+}}, [[SHL]] ; GCN: ds_write2st64_b64 [[VPTR]], [[VAL0]], [[VAL1]] offset0:4 offset1:127 ; GCN: s_endpgm define amdgpu_kernel void @simple_write2st64_two_val_max_offset_f64(double addrspace(1)* %C, double addrspace(1)* %in, double addrspace(3)* %lds) #0 { diff --git a/test/CodeGen/AMDGPU/early-if-convert.ll b/test/CodeGen/AMDGPU/early-if-convert.ll index 792f0b1eaef46..d129ca5c140af 100644 --- a/test/CodeGen/AMDGPU/early-if-convert.ll +++ b/test/CodeGen/AMDGPU/early-if-convert.ll @@ -382,7 +382,7 @@ done: } ; GCN-LABEL: {{^}}ifcvt_undef_scc: -; GCN: {{^}}; BB#0: +; GCN: {{^}}; %bb.0: ; GCN-NEXT: s_load_dwordx2 ; GCN-NEXT: s_cselect_b32 s{{[0-9]+}}, 1, 0 define amdgpu_kernel void @ifcvt_undef_scc(i32 %cond, i32 addrspace(1)* %out) { diff --git a/test/CodeGen/AMDGPU/else.ll b/test/CodeGen/AMDGPU/else.ll index 22338e4f50e56..c73ea936e8be4 100644 --- a/test/CodeGen/AMDGPU/else.ll +++ b/test/CodeGen/AMDGPU/else.ll @@ -25,7 +25,7 @@ end: } ; CHECK-LABEL: {{^}}else_execfix_leave_wqm: -; CHECK: ; BB#0: +; CHECK: ; %bb.0: ; CHECK-NEXT: s_mov_b64 [[INIT_EXEC:s\[[0-9]+:[0-9]+\]]], exec ; CHECK: ; %Flow ; CHECK-NEXT: s_or_saveexec_b64 [[DST:s\[[0-9]+:[0-9]+\]]], diff --git a/test/CodeGen/AMDGPU/extload-align.ll b/test/CodeGen/AMDGPU/extload-align.ll index 12cf27b918afc..097ea2f0bc1e8 100644 --- a/test/CodeGen/AMDGPU/extload-align.ll +++ b/test/CodeGen/AMDGPU/extload-align.ll @@ -1,4 +1,5 @@ -; RUN: llc -debug-only=machine-scheduler -march=amdgcn -verify-machineinstrs %s -o - 2>&1| FileCheck -check-prefix=SI-NOHSA -check-prefix=FUNC -check-prefix=DEBUG %s +; RUN: llc -debug-only=machine-scheduler -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs %s -o - 2>&1| FileCheck -check-prefix=SI-NOHSA -check-prefix=FUNC -check-prefix=DEBUG %s +target datalayout = "A5" ; REQUIRES: asserts ; Verify that the extload generated from %eval has the default @@ -6,18 +7,18 @@ ; size and not 4 corresponding to the sign-extended size (i32). ; DEBUG: {{^}}# Machine code for function extload_align: -; DEBUG: mem:LD2[]{{[^(]}} +; DEBUG: mem:LD2[(addrspace=5)]{{[^(]}} ; DEBUG: {{^}}# End machine code for function extload_align. -define amdgpu_kernel void @extload_align(i32* %out, i32 %index) #0 { - %v0 = alloca [4 x i16] - %a1 = getelementptr inbounds [4 x i16], [4 x i16]* %v0, i32 0, i32 0 - %a2 = getelementptr inbounds [4 x i16], [4 x i16]* %v0, i32 0, i32 1 - store i16 0, i16* %a1 - store i16 1, i16* %a2 - %a = getelementptr inbounds [4 x i16], [4 x i16]* %v0, i32 0, i32 %index - %val = load i16, i16* %a +define amdgpu_kernel void @extload_align(i32 addrspace(5)* %out, i32 %index) #0 { + %v0 = alloca [4 x i16], addrspace(5) + %a1 = getelementptr inbounds [4 x i16], [4 x i16] addrspace(5)* %v0, i32 0, i32 0 + %a2 = getelementptr inbounds [4 x i16], [4 x i16] addrspace(5)* %v0, i32 0, i32 1 + store i16 0, i16 addrspace(5)* %a1 + store i16 1, i16 addrspace(5)* %a2 + %a = getelementptr inbounds [4 x i16], [4 x i16] addrspace(5)* %v0, i32 0, i32 %index + %val = load i16, i16 addrspace(5)* %a %eval = sext i16 %val to i32 - store i32 %eval, i32* %out + store i32 %eval, i32 addrspace(5)* %out ret void } diff --git a/test/CodeGen/AMDGPU/extract_vector_elt-f16.ll b/test/CodeGen/AMDGPU/extract_vector_elt-f16.ll index 1f567ae050817..1e19ddf2b0ac6 100644 --- a/test/CodeGen/AMDGPU/extract_vector_elt-f16.ll +++ b/test/CodeGen/AMDGPU/extract_vector_elt-f16.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s -; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s +; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s +; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; GCN-LABEL: {{^}}extract_vector_elt_v2f16: ; GCN: s_load_dword [[VEC:s[0-9]+]] diff --git a/test/CodeGen/AMDGPU/extract_vector_elt-f64.ll b/test/CodeGen/AMDGPU/extract_vector_elt-f64.ll index db5bf0b4e8089..2f13f63fa8882 100644 --- a/test/CodeGen/AMDGPU/extract_vector_elt-f64.ll +++ b/test/CodeGen/AMDGPU/extract_vector_elt-f64.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s -; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; GCN-LABEL: {{^}}extract_vector_elt_v3f64_2: ; GCN: buffer_load_dwordx4 diff --git a/test/CodeGen/AMDGPU/extract_vector_elt-i16.ll b/test/CodeGen/AMDGPU/extract_vector_elt-i16.ll index 4dee500c84295..e1d24d8ff15eb 100644 --- a/test/CodeGen/AMDGPU/extract_vector_elt-i16.ll +++ b/test/CodeGen/AMDGPU/extract_vector_elt-i16.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=SICIVI %s -; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=SICIVI %s -; RUN: llc -march=amdgcn -mcpu=gfx901 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s +; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=SICIVI %s +; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=SICIVI %s +; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx901 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s ; GCN-LABEL: {{^}}extract_vector_elt_v2i16: ; GCN: s_load_dword [[VEC:s[0-9]+]] diff --git a/test/CodeGen/AMDGPU/extract_vector_elt-i64.ll b/test/CodeGen/AMDGPU/extract_vector_elt-i64.ll index a8d127879a32d..99019e2a83e61 100644 --- a/test/CodeGen/AMDGPU/extract_vector_elt-i64.ll +++ b/test/CodeGen/AMDGPU/extract_vector_elt-i64.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s -; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; How the replacement of i64 stores with v2i32 stores resulted in ; breaking other users of the bitcast if they already existed diff --git a/test/CodeGen/AMDGPU/extract_vector_elt-i8.ll b/test/CodeGen/AMDGPU/extract_vector_elt-i8.ll index b7d768fd55254..a5ff0932c6228 100644 --- a/test/CodeGen/AMDGPU/extract_vector_elt-i8.ll +++ b/test/CodeGen/AMDGPU/extract_vector_elt-i8.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s -; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; FUNC-LABEL: {{^}}extract_vector_elt_v1i8: ; GCN: buffer_load_ubyte diff --git a/test/CodeGen/AMDGPU/fabs.f16.ll b/test/CodeGen/AMDGPU/fabs.f16.ll index 3e2b44fe905cc..3bbea5e241cc8 100644 --- a/test/CodeGen/AMDGPU/fabs.f16.ll +++ b/test/CodeGen/AMDGPU/fabs.f16.ll @@ -127,8 +127,7 @@ define amdgpu_kernel void @fabs_free_v2f16(<2 x half> addrspace(1)* %out, i32 %i ; CI: v_mul_f32_e64 v{{[0-9]+}}, |v{{[0-9]+}}|, v{{[0-9]+}} ; CI: v_cvt_f16_f32 -; VI: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, -; VI: v_mul_f16_sdwa v{{[0-9]+}}, |v{{[0-9]+}}|, v{{[0-9]+}} dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; VI: v_mul_f16_sdwa v{{[0-9]+}}, |v{{[0-9]+}}|, v{{[0-9]+}} dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 ; VI: v_mul_f16_e64 v{{[0-9]+}}, |v{{[0-9]+}}|, v{{[0-9]+}} ; GFX9: v_and_b32_e32 [[FABS:v[0-9]+]], 0x7fff7fff, [[VAL]] diff --git a/test/CodeGen/AMDGPU/fadd.ll b/test/CodeGen/AMDGPU/fadd.ll index 621a0de281db5..a2f1f7195f275 100644 --- a/test/CodeGen/AMDGPU/fadd.ll +++ b/test/CodeGen/AMDGPU/fadd.ll @@ -72,4 +72,4 @@ define amdgpu_kernel void @fadd_0_nsz_attr_f32(float addrspace(1)* %out, float % } attributes #0 = { nounwind } -attributes #1 = { nounwind "no-signed-zeros-fp-math"="true" } \ No newline at end of file +attributes #1 = { nounwind "no-signed-zeros-fp-math"="true" } diff --git a/test/CodeGen/AMDGPU/fcanonicalize.f16.ll b/test/CodeGen/AMDGPU/fcanonicalize.f16.ll index 80f802bdce5b0..aef9eb6958391 100644 --- a/test/CodeGen/AMDGPU/fcanonicalize.f16.ll +++ b/test/CodeGen/AMDGPU/fcanonicalize.f16.ll @@ -207,7 +207,7 @@ define amdgpu_kernel void @test_fold_canonicalize_snan3_value_f16(half addrspace } ; GCN-LABEL: {{^}}v_test_canonicalize_var_v2f16: -; VI-DAG: v_max_f16_sdwa [[REG0:v[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}} dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; VI-DAG: v_max_f16_sdwa [[REG0:v[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}} dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 ; VI-DAG: v_max_f16_e32 [[REG1:v[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}} ; VI-NOT: v_and_b32 @@ -246,7 +246,7 @@ define amdgpu_kernel void @v_test_canonicalize_fabs_var_v2f16(<2 x half> addrspa ; GCN-LABEL: {{^}}v_test_canonicalize_fneg_fabs_var_v2f16: ; VI-DAG: v_or_b32_e32 v{{[0-9]+}}, 0x80008000, v{{[0-9]+}} -; VI-DAG: v_max_f16_sdwa [[REG0:v[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}} dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; VI-DAG: v_max_f16_sdwa [[REG0:v[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}} dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 ; VI-DAG: v_max_f16_e32 [[REG1:v[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}} ; VI: v_or_b32 @@ -266,8 +266,7 @@ define amdgpu_kernel void @v_test_canonicalize_fneg_fabs_var_v2f16(<2 x half> ad ; GCN-LABEL: {{^}}v_test_canonicalize_fneg_var_v2f16: ; VI: v_xor_b32_e32 [[FNEG:v[0-9]+]], 0x80008000, v{{[0-9]+}} -; VI: v_lshrrev_b32_e32 [[FNEGHI:v[0-9]+]], 16, [[FNEG]] -; VI-DAG: v_max_f16_sdwa [[REG1:v[0-9]+]], [[FNEG]], [[FNEGHI]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; VI-DAG: v_max_f16_sdwa [[REG1:v[0-9]+]], [[FNEG]], [[FNEG]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 ; VI-DAG: v_max_f16_e32 [[REG0:v[0-9]+]], [[FNEG]], [[FNEG]] ; VI-NOT: 0xffff diff --git a/test/CodeGen/AMDGPU/fence-amdgiz.ll b/test/CodeGen/AMDGPU/fence-amdgiz.ll index 3055f325f3fa9..0dd2a9241b230 100644 --- a/test/CodeGen/AMDGPU/fence-amdgiz.ll +++ b/test/CodeGen/AMDGPU/fence-amdgiz.ll @@ -3,7 +3,7 @@ target datalayout = "e-p:64:64-p1:64:64-p2:64:64-p3:32:32-p4:32:32-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5" ; CHECK-LABEL: atomic_fence -; CHECK: BB#0: +; CHECK: %bb.0: ; CHECK-NOT: ATOMIC_FENCE ; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: buffer_wbinvl1_vol diff --git a/test/CodeGen/AMDGPU/fma.ll b/test/CodeGen/AMDGPU/fma.ll index 952bd1f295444..8e51f82112ff8 100644 --- a/test/CodeGen/AMDGPU/fma.ll +++ b/test/CodeGen/AMDGPU/fma.ll @@ -1,5 +1,12 @@ ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s +; RUN: not llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=cedar -verify-machineinstrs < %s +; RUN: not llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=juniper -verify-machineinstrs < %s +; RUN: not llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=redwood -verify-machineinstrs < %s +; RUN: not llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=sumo -verify-machineinstrs < %s +; RUN: not llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=barts -verify-machineinstrs < %s +; RUN: not llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=caicos -verify-machineinstrs < %s +; RUN: not llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=turks -verify-machineinstrs < %s declare float @llvm.fma.f32(float, float, float) nounwind readnone declare <2 x float> @llvm.fma.v2f32(<2 x float>, <2 x float>, <2 x float>) nounwind readnone diff --git a/test/CodeGen/AMDGPU/fneg.f16.ll b/test/CodeGen/AMDGPU/fneg.f16.ll index a27a0b444ae95..4ec4ac72ba17d 100644 --- a/test/CodeGen/AMDGPU/fneg.f16.ll +++ b/test/CodeGen/AMDGPU/fneg.f16.ll @@ -116,8 +116,7 @@ define amdgpu_kernel void @fneg_free_v2f16(<2 x half> addrspace(1)* %out, i32 %i ; CI: v_mul_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} ; CI: v_cvt_f16_f32 -; VI: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, -; VI: v_mul_f16_sdwa v{{[0-9]+}}, -v{{[0-9]+}}, v{{[0-9]+}} dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; VI: v_mul_f16_sdwa v{{[0-9]+}}, -v{{[0-9]+}}, v{{[0-9]+}} dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 ; VI: v_mul_f16_e64 v{{[0-9]+}}, -v{{[0-9]+}}, v{{[0-9]+}} ; GFX9: v_pk_mul_f16 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} neg_lo:[1,0] neg_hi:[1,0]{{$}} diff --git a/test/CodeGen/AMDGPU/frame-index-elimination.ll b/test/CodeGen/AMDGPU/frame-index-elimination.ll index 9bc46434d59e4..9b75c44eac050 100644 --- a/test/CodeGen/AMDGPU/frame-index-elimination.ll +++ b/test/CodeGen/AMDGPU/frame-index-elimination.ll @@ -1,4 +1,5 @@ -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=kaveri -mattr=-promote-alloca -amdgpu-sroa=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=kaveri -mattr=-promote-alloca -amdgpu-sroa=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CI %s +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=-promote-alloca -amdgpu-sroa=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s ; Test that non-entry function frame indices are expanded properly to ; give an index relative to the scratch wave offset register @@ -7,8 +8,13 @@ ; GCN-LABEL: {{^}}func_mov_fi_i32: ; GCN: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN: s_sub_u32 s6, s5, s4 -; GCN-NEXT: v_lshr_b32_e64 [[SCALED:v[0-9]+]], s6, 6 -; GCN-NEXT: v_add_i32_e64 v0, s[6:7], 4, [[SCALED]] + +; CI-NEXT: v_lshr_b32_e64 [[SCALED:v[0-9]+]], s6, 6 +; CI-NEXT: v_add_i32_e64 v0, s[6:7], 4, [[SCALED]] + +; GFX9-NEXT: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, s6 +; GFX9-NEXT: v_add_u32_e32 v0, 4, [[SCALED]] + ; GCN-NOT: v_mov ; GCN: ds_write_b32 v0, v0 define void @func_mov_fi_i32() #0 { @@ -23,9 +29,16 @@ define void @func_mov_fi_i32() #0 { ; GCN-LABEL: {{^}}func_add_constant_to_fi_i32: ; GCN: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN: s_sub_u32 s6, s5, s4 -; GCN-NEXT: v_lshr_b32_e64 [[SCALED:v[0-9]+]], s6, 6 -; GCN-NEXT: v_add_i32_e64 v0, s[6:7], 4, [[SCALED]] -; GCN-NEXT: v_add_i32_e32 v0, vcc, 4, v0 + +; CI-NEXT: v_lshr_b32_e64 [[SCALED:v[0-9]+]], s6, 6 +; CI-NEXT: v_add_i32_e64 v0, s[6:7], 4, [[SCALED]] +; CI-NEXT: v_add_i32_e32 v0, vcc, 4, v0 + +; GFX9-NEXT: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, s6 +; GFX9-NEXT: v_add_u32_e32 v0, 4, [[SCALED]] +; GFX9-NEXT: v_add_u32_e32 v0, 4, v0 + + ; GCN-NOT: v_mov ; GCN: ds_write_b32 v0, v0 define void @func_add_constant_to_fi_i32() #0 { @@ -40,8 +53,13 @@ define void @func_add_constant_to_fi_i32() #0 { ; GCN-LABEL: {{^}}func_other_fi_user_i32: ; GCN: s_sub_u32 s6, s5, s4 -; GCN-NEXT: v_lshr_b32_e64 [[SCALED:v[0-9]+]], s6, 6 -; GCN-NEXT: v_add_i32_e64 v0, s[6:7], 4, [[SCALED]] + +; CI-NEXT: v_lshr_b32_e64 [[SCALED:v[0-9]+]], s6, 6 +; CI-NEXT: v_add_i32_e64 v0, s[6:7], 4, [[SCALED]] + +; GFX9-NEXT: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, s6 +; GFX9-NEXT: v_add_u32_e32 v0, 4, [[SCALED]] + ; GCN-NEXT: v_mul_lo_i32 v0, v0, 9 ; GCN-NOT: v_mov ; GCN: ds_write_b32 v0, v0 @@ -73,9 +91,15 @@ define void @func_load_private_arg_i32_ptr(i32* %ptr) #0 { ; GCN: s_waitcnt ; GCN-NEXT: s_mov_b32 s5, s32 ; GCN-NEXT: s_sub_u32 [[SUB_OFFSET:s[0-9]+]], s5, s4 -; GCN-NEXT: v_lshr_b32_e64 [[SHIFT:v[0-9]+]], [[SUB_OFFSET]], 6 -; GCN-NEXT: v_add_i32_e64 [[ADD:v[0-9]+]], {{s\[[0-9]+:[0-9]+\]}}, 4, [[SHIFT]] -; GCN-NEXT: v_add_i32_e32 v0, vcc, 4, [[ADD]] + +; CI-NEXT: v_lshr_b32_e64 [[SHIFT:v[0-9]+]], [[SUB_OFFSET]], 6 +; CI-NEXT: v_add_i32_e64 [[ADD:v[0-9]+]], {{s\[[0-9]+:[0-9]+\]}}, 4, [[SHIFT]] +; CI-NEXT: v_add_i32_e32 v0, vcc, 4, [[ADD]] + +; GFX9-NEXT: v_lshrrev_b32_e64 [[SHIFT:v[0-9]+]], 6, [[SUB_OFFSET]] +; GFX9-NEXT: v_add_u32_e32 [[ADD:v[0-9]+]], 4, [[SHIFT]] +; GFX9-NEXT: v_add_u32_e32 v0, 4, [[ADD]] + ; GCN-NOT: v_mov ; GCN: ds_write_b32 v0, v0 define void @void_func_byval_struct_i8_i32_ptr({ i8, i32 }* byval %arg0) #0 { @@ -106,12 +130,21 @@ define void @void_func_byval_struct_i8_i32_ptr_value({ i8, i32 }* byval %arg0) # ; GCN-LABEL: {{^}}void_func_byval_struct_i8_i32_ptr_nonentry_block: ; GCN: s_sub_u32 [[SUB_OFFSET:s[0-9]+]], s5, s4 -; GCN: v_lshr_b32_e64 [[SHIFT:v[0-9]+]], [[SUB_OFFSET]], 6 -; GCN: v_add_i32_e64 [[ADD:v[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 4, [[SHIFT]] + +; CI: v_lshr_b32_e64 [[SHIFT:v[0-9]+]], [[SUB_OFFSET]], 6 +; CI: v_add_i32_e64 [[ADD:v[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 4, [[SHIFT]] + +; GFX9: v_lshrrev_b32_e64 [[SHIFT:v[0-9]+]], 6, [[SUB_OFFSET]] +; GFX9: v_add_u32_e32 [[ADD:v[0-9]+]], 4, [[SHIFT]] + ; GCN: s_and_saveexec_b64 -; GCN: v_add_i32_e32 v0, vcc, 4, [[ADD]] -; GCN: buffer_load_dword v1, v0, s[0:3], s4 offen{{$}} +; CI: v_add_i32_e32 v0, vcc, 4, [[ADD]] +; CI: buffer_load_dword v1, v0, s[0:3], s4 offen{{$}} + +; GFX9: v_add_u32_e32 v0, 4, [[ADD]] +; GFX9: buffer_load_dword v1, v{{[0-9]+}}, s[0:3], s4 offen offset:4{{$}} + ; GCN: ds_write_b32 define void @void_func_byval_struct_i8_i32_ptr_nonentry_block({ i8, i32 }* byval %arg0, i32 %arg2) #0 { %cmp = icmp eq i32 %arg2, 0 @@ -131,9 +164,14 @@ ret: ; Added offset can't be used with VOP3 add ; GCN-LABEL: {{^}}func_other_fi_user_non_inline_imm_offset_i32: ; GCN: s_sub_u32 s6, s5, s4 -; GCN-DAG: v_lshr_b32_e64 [[SCALED:v[0-9]+]], s6, 6 ; GCN-DAG: s_movk_i32 s6, 0x204 -; GCN: v_add_i32_e64 v0, s[6:7], s6, [[SCALED]] + +; CI-DAG: v_lshr_b32_e64 [[SCALED:v[0-9]+]], s6, 6 +; CI: v_add_i32_e64 v0, s[6:7], s6, [[SCALED]] + +; GFX9-DAG: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, s6 +; GFX9: v_add_u32_e32 v0, s6, [[SCALED]] + ; GCN: v_mul_lo_i32 v0, v0, 9 ; GCN: ds_write_b32 v0, v0 define void @func_other_fi_user_non_inline_imm_offset_i32() #0 { @@ -150,9 +188,14 @@ define void @func_other_fi_user_non_inline_imm_offset_i32() #0 { ; GCN-LABEL: {{^}}func_other_fi_user_non_inline_imm_offset_i32_vcc_live: ; GCN: s_sub_u32 [[DIFF:s[0-9]+]], s5, s4 -; GCN-DAG: v_lshr_b32_e64 [[SCALED:v[0-9]+]], [[DIFF]], 6 ; GCN-DAG: s_movk_i32 [[OFFSET:s[0-9]+]], 0x204 -; GCN: v_add_i32_e64 v0, s{{\[[0-9]+:[0-9]+\]}}, [[OFFSET]], [[SCALED]] + +; CI-DAG: v_lshr_b32_e64 [[SCALED:v[0-9]+]], [[DIFF]], 6 +; CI: v_add_i32_e64 v0, s{{\[[0-9]+:[0-9]+\]}}, [[OFFSET]], [[SCALED]] + +; GFX9-DAG: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, [[DIFF]] +; GFX9: v_add_u32_e32 v0, [[OFFSET]], [[SCALED]] + ; GCN: v_mul_lo_i32 v0, v0, 9 ; GCN: ds_write_b32 v0, v0 define void @func_other_fi_user_non_inline_imm_offset_i32_vcc_live() #0 { diff --git a/test/CodeGen/AMDGPU/function-args.ll b/test/CodeGen/AMDGPU/function-args.ll index 7620f0ecddc3d..ca36732540b25 100644 --- a/test/CodeGen/AMDGPU/function-args.ll +++ b/test/CodeGen/AMDGPU/function-args.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=amdgcn -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=CI %s -; RUN: llc -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI %s -; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI %s +; RUN: llc -march=amdgcn -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CI,CIVI %s +; RUN: llc -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI,CIVI,GFX89 %s +; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI,GFX89 %s ; GCN-LABEL: {{^}}void_func_i1: ; GCN: v_and_b32_e32 v0, 1, v0 @@ -24,7 +24,7 @@ define void @void_func_i1_zeroext(i1 zeroext %arg0) #0 { ; GCN-LABEL: {{^}}void_func_i1_signext: ; GCN: s_waitcnt -; GCN-NEXT: v_add{{(_co)?}}_{{i|u}}32_e32 v0, vcc, 12, v0 +; GCN-NEXT: v_add_{{i|u}}32_e32 v0, {{(vcc, )?}}12, v0 ; GCN-NOT: v0 ; GCN: buffer_store_dword v0, off define void @void_func_i1_signext(i1 signext %arg0) #0 { @@ -60,7 +60,7 @@ define void @void_func_i8(i8 %arg0) #0 { ; GCN-LABEL: {{^}}void_func_i8_zeroext: ; GCN-NOT: and_b32 -; GCN: v_add{{(_co)?}}_{{i|u}}32_e32 v0, vcc, 12, v0 +; GCN: v_add_{{i|u}}32_e32 v0, {{(vcc, )?}}12, v0 define void @void_func_i8_zeroext(i8 zeroext %arg0) #0 { %ext = zext i8 %arg0 to i32 %add = add i32 %ext, 12 @@ -70,7 +70,7 @@ define void @void_func_i8_zeroext(i8 zeroext %arg0) #0 { ; GCN-LABEL: {{^}}void_func_i8_signext: ; GCN-NOT: v_bfe_i32 -; GCN: v_add{{(_co)?}}_{{i|u}}32_e32 v0, vcc, 12, v0 +; GCN: v_add_{{i|u}}32_e32 v0, {{(vcc, )?}}12, v0 define void @void_func_i8_signext(i8 signext %arg0) #0 { %ext = sext i8 %arg0 to i32 %add = add i32 %ext, 12 @@ -87,7 +87,7 @@ define void @void_func_i16(i16 %arg0) #0 { ; GCN-LABEL: {{^}}void_func_i16_zeroext: ; GCN-NOT: v0 -; GCN: v_add{{(_co)?}}_{{i|u}}32_e32 v0, vcc, 12, v0 +; GCN: v_add_{{i|u}}32_e32 v0, {{(vcc, )?}}12, v0 define void @void_func_i16_zeroext(i16 zeroext %arg0) #0 { %ext = zext i16 %arg0 to i32 %add = add i32 %ext, 12 @@ -97,7 +97,7 @@ define void @void_func_i16_zeroext(i16 zeroext %arg0) #0 { ; GCN-LABEL: {{^}}void_func_i16_signext: ; GCN-NOT: v0 -; GCN: v_add{{(_co)?}}_{{i|u}}32_e32 v0, vcc, 12, v0 +; GCN: v_add_{{i|u}}32_e32 v0, {{(vcc, )?}}12, v0 define void @void_func_i16_signext(i16 signext %arg0) #0 { %ext = sext i16 %arg0 to i32 %add = add i32 %ext, 12 @@ -582,7 +582,7 @@ define void @void_func_v32i32_i32_i64(<32 x i32> %arg0, i32 %arg1, i64 %arg2) #0 ; GCN: buffer_store_byte [[TRUNC_ARG1_I1]], off ; GCN: buffer_store_byte [[LOAD_ARG2]], off ; GCN: buffer_store_short [[LOAD_ARG3]], off -; VI: buffer_store_short [[LOAD_ARG4]], off +; GFX89 buffer_store_short [[LOAD_ARG4]], off ; CI: buffer_store_short [[CVT_ARG4]], off define void @void_func_v32i32_i1_i8_i16(<32 x i32> %arg0, i1 %arg1, i8 %arg2, i16 %arg3, half %arg4) #0 { diff --git a/test/CodeGen/AMDGPU/function-returns.ll b/test/CodeGen/AMDGPU/function-returns.ll index f5cd2c0cf1eaf..4a24f5e285b9c 100644 --- a/test/CodeGen/AMDGPU/function-returns.ll +++ b/test/CodeGen/AMDGPU/function-returns.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=amdgcn -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CI %s -; RUN: llc -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX89 %s -; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX89,GFX9 %s +; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CI %s +; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX89 %s +; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX89,GFX9 %s ; GCN-LABEL: {{^}}i1_func_void: ; GCN: buffer_load_ubyte v0, off @@ -376,13 +376,13 @@ define {i8, i32} @struct_i8_i32_func_void() #0 { ; GCN: buffer_load_dword [[VAL1:v[0-9]+]] ; GCN: buffer_store_byte [[VAL0]], v0, s[0:3], s4 offen{{$}} ; GCN: buffer_store_dword [[VAL1]], v0, s[0:3], s4 offen offset:4{{$}} -define void @void_func_sret_struct_i8_i32({ i8, i32 }* sret %arg0) #0 { +define void @void_func_sret_struct_i8_i32({ i8, i32 } addrspace(5)* sret %arg0) #0 { %val0 = load volatile i8, i8 addrspace(1)* undef %val1 = load volatile i32, i32 addrspace(1)* undef - %gep0 = getelementptr inbounds { i8, i32 }, { i8, i32 }* %arg0, i32 0, i32 0 - %gep1 = getelementptr inbounds { i8, i32 }, { i8, i32 }* %arg0, i32 0, i32 1 - store i8 %val0, i8* %gep0 - store i32 %val1, i32* %gep1 + %gep0 = getelementptr inbounds { i8, i32 }, { i8, i32 } addrspace(5)* %arg0, i32 0, i32 0 + %gep1 = getelementptr inbounds { i8, i32 }, { i8, i32 } addrspace(5)* %arg0, i32 0, i32 1 + store i8 %val0, i8 addrspace(5)* %gep0 + store i32 %val1, i32 addrspace(5)* %gep1 ret void } diff --git a/test/CodeGen/AMDGPU/i1-copy-implicit-def.ll b/test/CodeGen/AMDGPU/i1-copy-implicit-def.ll index f6bf0b09486e8..37d05c7ac414c 100644 --- a/test/CodeGen/AMDGPU/i1-copy-implicit-def.ll +++ b/test/CodeGen/AMDGPU/i1-copy-implicit-def.ll @@ -3,7 +3,7 @@ ; SILowerI1Copies was not handling IMPLICIT_DEF ; SI-LABEL: {{^}}br_implicit_def: -; SI: BB#0: +; SI: %bb.0: ; SI-NEXT: s_cbranch_scc1 define amdgpu_kernel void @br_implicit_def(i32 addrspace(1)* %out, i32 %arg) #0 { bb: diff --git a/test/CodeGen/AMDGPU/insert_vector_elt.ll b/test/CodeGen/AMDGPU/insert_vector_elt.ll index 463e7ba53ddd9..79e1943f8fb75 100644 --- a/test/CodeGen/AMDGPU/insert_vector_elt.ll +++ b/test/CodeGen/AMDGPU/insert_vector_elt.ll @@ -1,5 +1,5 @@ -; RUN: llc -verify-machineinstrs -march=amdgcn -mcpu=tahiti -mattr=+max-private-element-size-16 < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=GCN-NO-TONGA %s -; RUN: llc -verify-machineinstrs -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -mattr=+max-private-element-size-16 < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=GCN-TONGA %s +; RUN: llc -verify-machineinstrs -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -mattr=+max-private-element-size-16 < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=GCN-NO-TONGA %s +; RUN: llc -verify-machineinstrs -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -mattr=+max-private-element-size-16 < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=GCN-TONGA %s ; FIXME: Broken on evergreen ; FIXME: For some reason the 8 and 16 vectors are being stored as diff --git a/test/CodeGen/AMDGPU/inserted-wait-states.mir b/test/CodeGen/AMDGPU/inserted-wait-states.mir index 16d9070849b97..698f2c3ebc477 100644 --- a/test/CodeGen/AMDGPU/inserted-wait-states.mir +++ b/test/CodeGen/AMDGPU/inserted-wait-states.mir @@ -548,7 +548,7 @@ body: | %flat_scr_lo = S_ADD_U32 %sgpr6, %sgpr9, implicit-def %scc %flat_scr_hi = S_ADDC_U32 %sgpr7, 0, implicit-def %scc, implicit %scc - DBG_VALUE _, 2, !5, !11, debug-location !12 + DBG_VALUE %noreg, 2, !5, !11, debug-location !12 %sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed %sgpr4_sgpr5, 0, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`) dead %sgpr6_sgpr7 = KILL %sgpr4_sgpr5 %sgpr8 = S_MOV_B32 %sgpr5 diff --git a/test/CodeGen/AMDGPU/invert-br-undef-vcc.mir b/test/CodeGen/AMDGPU/invert-br-undef-vcc.mir index 67642282f75b0..61aa39fcc25da 100644 --- a/test/CodeGen/AMDGPU/invert-br-undef-vcc.mir +++ b/test/CodeGen/AMDGPU/invert-br-undef-vcc.mir @@ -26,7 +26,7 @@ ... --- # CHECK-LABEL: name: invert_br_undef_vcc -# CHECK: S_CBRANCH_VCCZ %bb.1.else, implicit undef %vcc +# CHECK: S_CBRANCH_VCCZ %bb.1, implicit undef %vcc name: invert_br_undef_vcc alignment: 0 @@ -58,7 +58,7 @@ body: | %sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed %sgpr0_sgpr1, 11, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`) %sgpr7 = S_MOV_B32 61440 %sgpr6 = S_MOV_B32 -1 - S_CBRANCH_VCCNZ %bb.2.if, implicit undef %vcc + S_CBRANCH_VCCNZ %bb.2, implicit undef %vcc bb.1.else: liveins: %sgpr6, %sgpr7, %sgpr0_sgpr1_sgpr2_sgpr3:0x00000003 @@ -66,7 +66,7 @@ body: | %vgpr0 = V_MOV_B32_e32 100, implicit %exec BUFFER_STORE_DWORD_OFFSET killed %vgpr0, killed %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec :: (volatile store 4 into `i32 addrspace(1)* undef`) %vgpr0 = V_MOV_B32_e32 1, implicit %exec - S_BRANCH %bb.3.done + S_BRANCH %bb.3 bb.2.if: liveins: %sgpr6, %sgpr7, %sgpr0_sgpr1_sgpr2_sgpr3:0x00000003 diff --git a/test/CodeGen/AMDGPU/lds-output-queue.ll b/test/CodeGen/AMDGPU/lds-output-queue.ll index e5df12a1e5a3f..f8fb12eefa620 100644 --- a/test/CodeGen/AMDGPU/lds-output-queue.ll +++ b/test/CodeGen/AMDGPU/lds-output-queue.ll @@ -46,20 +46,20 @@ declare void @llvm.r600.group.barrier() nounwind convergent ; ; The instruction selection phase will generate ISA that looks like this: ; %oqap = LDS_READ_RET -; %vreg0 = MOV %oqap -; %vreg1 = VTX_READ_32 -; %vreg2 = ADD_INT %vreg1, %vreg0 +; %0 = MOV %oqap +; %1 = VTX_READ_32 +; %2 = ADD_INT %1, %0 ; ; The bottom scheduler will schedule the two ALU instructions first: ; ; UNSCHEDULED: ; %oqap = LDS_READ_RET -; %vreg1 = VTX_READ_32 +; %1 = VTX_READ_32 ; ; SCHEDULED: ; -; vreg0 = MOV %oqap -; vreg2 = ADD_INT %vreg1, %vreg2 +; %0 = MOV %oqap +; %2 = ADD_INT %1, %2 ; ; The lack of proper aliasing results in the local memory read (LDS_READ_RET) ; to consider the global memory read (VTX_READ_32) has a chain dependency, so @@ -69,10 +69,10 @@ declare void @llvm.r600.group.barrier() nounwind convergent ; Alu clause: ; %oqap = LDS_READ_RET ; VTX clause: -; %vreg1 = VTX_READ_32 +; %1 = VTX_READ_32 ; Alu clause: -; vreg0 = MOV %oqap -; vreg2 = ADD_INT %vreg1, %vreg2 +; %0 = MOV %oqap +; %2 = ADD_INT %1, %2 ; ; This is an illegal program because the oqap def and use know occur in ; different ALU clauses. diff --git a/test/CodeGen/AMDGPU/liveness.mir b/test/CodeGen/AMDGPU/liveness.mir index 6fd8466492d08..8bb946da9ad27 100644 --- a/test/CodeGen/AMDGPU/liveness.mir +++ b/test/CodeGen/AMDGPU/liveness.mir @@ -6,7 +6,7 @@ # liveranges needed it. # # Should see three distinct value numbers: -# CHECK: %vreg0 [{{.*}}:0)[{{.*}}:1)[{{.*}}:2) 0@{{[0-9]+[Berd]}} 1@{{[0-9]+[Berd]}} 2@{{[0-9]+B-phi}} +# CHECK: %0 [{{.*}}:0)[{{.*}}:1)[{{.*}}:2) 0@{{[0-9]+[Berd]}} 1@{{[0-9]+[Berd]}} 2@{{[0-9]+B-phi}} --- | define amdgpu_kernel void @test0() { ret void } ... diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load.ll index 4f8c619122481..49ca7d405724b 100644 --- a/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load.ll +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load.ll @@ -127,7 +127,7 @@ entry: } ;CHECK-LABEL: {{^}}buffer_load_x1_offen_merged: -;CHECK-NEXT: BB# +;CHECK-NEXT: %bb. ;CHECK-NEXT: buffer_load_dwordx4 v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:4 ;CHECK-NEXT: buffer_load_dwordx2 v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:28 ;CHECK: s_waitcnt @@ -151,7 +151,7 @@ main_body: } ;CHECK-LABEL: {{^}}buffer_load_x1_offen_merged_glc_slc: -;CHECK-NEXT: BB# +;CHECK-NEXT: %bb. ;CHECK-NEXT: buffer_load_dwordx2 v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:4{{$}} ;CHECK-NEXT: buffer_load_dwordx2 v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:12 glc{{$}} ;CHECK-NEXT: buffer_load_dwordx2 v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:28 glc slc{{$}} @@ -176,7 +176,7 @@ main_body: } ;CHECK-LABEL: {{^}}buffer_load_x2_offen_merged: -;CHECK-NEXT: BB# +;CHECK-NEXT: %bb. ;CHECK-NEXT: buffer_load_dwordx4 v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:4 ;CHECK: s_waitcnt define amdgpu_ps void @buffer_load_x2_offen_merged(<4 x i32> inreg %rsrc, i32 %a) { @@ -194,7 +194,7 @@ main_body: } ;CHECK-LABEL: {{^}}buffer_load_x1_offset_merged: -;CHECK-NEXT: BB# +;CHECK-NEXT: %bb. ;CHECK-NEXT: buffer_load_dwordx4 v[{{[0-9]}}:{{[0-9]}}], off, s[0:3], 0 offset:4 ;CHECK-NEXT: buffer_load_dwordx2 v[{{[0-9]}}:{{[0-9]}}], off, s[0:3], 0 offset:28 ;CHECK: s_waitcnt @@ -212,7 +212,7 @@ main_body: } ;CHECK-LABEL: {{^}}buffer_load_x2_offset_merged: -;CHECK-NEXT: BB# +;CHECK-NEXT: %bb. ;CHECK-NEXT: buffer_load_dwordx4 v[{{[0-9]}}:{{[0-9]}}], off, s[0:3], 0 offset:4 ;CHECK: s_waitcnt define amdgpu_ps void @buffer_load_x2_offset_merged(<4 x i32> inreg %rsrc) { diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.wbinvl1.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.wbinvl1.ll index 10bea8ea63b02..69de9555035b9 100644 --- a/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.wbinvl1.ll +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.wbinvl1.ll @@ -4,7 +4,7 @@ declare void @llvm.amdgcn.buffer.wbinvl1() #0 ; GCN-LABEL: {{^}}test_buffer_wbinvl1: -; GCN-NEXT: ; BB#0: +; GCN-NEXT: ; %bb.0: ; SI-NEXT: buffer_wbinvl1 ; encoding: [0x00,0x00,0xc4,0xe1,0x00,0x00,0x00,0x00] ; VI-NEXT: buffer_wbinvl1 ; encoding: [0x00,0x00,0xf8,0xe0,0x00,0x00,0x00,0x00] ; GCN-NEXT: s_endpgm diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.wbinvl1.sc.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.wbinvl1.sc.ll index fe60d16d90f7a..d1c8f37b3d857 100644 --- a/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.wbinvl1.sc.ll +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.wbinvl1.sc.ll @@ -3,7 +3,7 @@ declare void @llvm.amdgcn.buffer.wbinvl1.sc() #0 ; SI-LABEL: {{^}}test_buffer_wbinvl1_sc: -; SI-NEXT: ; BB#0: +; SI-NEXT: ; %bb.0: ; SI-NEXT: buffer_wbinvl1_sc ; encoding: [0x00,0x00,0xc0,0xe1,0x00,0x00,0x00,0x00] ; SI-NEXT: s_endpgm define amdgpu_kernel void @test_buffer_wbinvl1_sc() #0 { diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.wbinvl1.vol.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.wbinvl1.vol.ll index 061c1469ed4d8..4dc938c9b0a28 100644 --- a/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.wbinvl1.vol.ll +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.wbinvl1.vol.ll @@ -4,7 +4,7 @@ declare void @llvm.amdgcn.buffer.wbinvl1.vol() #0 ; GCN-LABEL: {{^}}test_buffer_wbinvl1_vol: -; GCN-NEXT: ; BB#0: +; GCN-NEXT: ; %bb.0: ; CI-NEXT: buffer_wbinvl1_vol ; encoding: [0x00,0x00,0xc0,0xe1,0x00,0x00,0x00,0x00] ; VI-NEXT: buffer_wbinvl1_vol ; encoding: [0x00,0x00,0xfc,0xe0,0x00,0x00,0x00,0x00] ; GCN: s_endpgm diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pkrtz.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pkrtz.ll index 7b1cfa18721df..16d0c2370073a 100644 --- a/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pkrtz.ll +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pkrtz.ll @@ -25,7 +25,7 @@ define amdgpu_kernel void @s_cvt_pkrtz_samereg_v2f16_f32(<2 x half> addrspace(1) ; FIXME: Folds to 0 on gfx9 ; GCN-LABEL: {{^}}s_cvt_pkrtz_undef_undef: -; GCN-NEXT: ; BB#0 +; GCN-NEXT: ; %bb.0 ; SI-NEXT: s_endpgm ; VI-NEXT: s_endpgm ; GFX9: v_mov_b32_e32 v{{[0-9]+}}, 0{{$}} diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.init.exec.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.init.exec.ll index a379f86e200ed..5c4dafa38f535 100644 --- a/test/CodeGen/AMDGPU/llvm.amdgcn.init.exec.ll +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.init.exec.ll @@ -51,7 +51,7 @@ main_body: ; GCN: s_bfm_b64 exec, s1, 0 ; GCN: s_cmp_eq_u32 s1, 64 ; GCN: s_cmov_b64 exec, -1 -; GCN: v_add_co_u32_e32 v0, vcc, s0, v0 +; GCN: v_add_u32_e32 v0, s0, v0 define amdgpu_ps float @reuse_input(i32 inreg %count, i32 %a) { main_body: call void @llvm.amdgcn.init.exec.from.input(i32 %count, i32 19) @@ -65,7 +65,7 @@ main_body: ; GCN: s_bfm_b64 exec, s1, 0 ; GCN: s_cmp_eq_u32 s1, 64 ; GCN: s_cmov_b64 exec, -1 -; GCN: v_add_co_u32_e32 v0, vcc, s0, v0 +; GCN: v_add_u32_e32 v0, s0, v0 define amdgpu_ps float @reuse_input2(i32 inreg %count, i32 %a) { main_body: %s = add i32 %a, %count diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.kill.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.kill.ll index a1ecb7f750c7b..d6b0628956a02 100644 --- a/test/CodeGen/AMDGPU/llvm.amdgcn.kill.ll +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.kill.ll @@ -31,8 +31,8 @@ define amdgpu_ps void @vcc_implicit_def(float %arg13, float %arg14) { } ; SI-LABEL: {{^}}true: -; SI-NEXT: BB# -; SI-NEXT: BB# +; SI-NEXT: %bb. +; SI-NEXT: %bb. ; SI-NEXT: s_endpgm define amdgpu_gs void @true() { call void @llvm.amdgcn.kill(i1 true) diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.inv.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.inv.ll index 224b2ed72e3bd..b7fb96a2d1a59 100644 --- a/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.inv.ll +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.inv.ll @@ -5,7 +5,7 @@ declare void @llvm.amdgcn.s.dcache.inv() #0 declare void @llvm.amdgcn.s.waitcnt(i32) #0 ; GCN-LABEL: {{^}}test_s_dcache_inv: -; GCN-NEXT: ; BB#0: +; GCN-NEXT: ; %bb.0: ; SI-NEXT: s_dcache_inv ; encoding: [0x00,0x00,0xc0,0xc7] ; VI-NEXT: s_dcache_inv ; encoding: [0x00,0x00,0x80,0xc0,0x00,0x00,0x00,0x00] ; GCN-NEXT: s_endpgm @@ -15,7 +15,7 @@ define amdgpu_kernel void @test_s_dcache_inv() #0 { } ; GCN-LABEL: {{^}}test_s_dcache_inv_insert_wait: -; GCN-NEXT: ; BB#0: +; GCN-NEXT: ; %bb.0: ; GCN: s_dcache_inv ; GCN: s_waitcnt lgkmcnt(0) ; encoding define amdgpu_kernel void @test_s_dcache_inv_insert_wait() #0 { diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.inv.vol.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.inv.vol.ll index f96d5db5794ac..e8a363adde734 100644 --- a/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.inv.vol.ll +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.inv.vol.ll @@ -5,7 +5,7 @@ declare void @llvm.amdgcn.s.dcache.inv.vol() #0 declare void @llvm.amdgcn.s.waitcnt(i32) #0 ; GCN-LABEL: {{^}}test_s_dcache_inv_vol: -; GCN-NEXT: ; BB#0: +; GCN-NEXT: ; %bb.0: ; CI-NEXT: s_dcache_inv_vol ; encoding: [0x00,0x00,0x40,0xc7] ; VI-NEXT: s_dcache_inv_vol ; encoding: [0x00,0x00,0x88,0xc0,0x00,0x00,0x00,0x00] ; GCN-NEXT: s_endpgm @@ -15,7 +15,7 @@ define amdgpu_kernel void @test_s_dcache_inv_vol() #0 { } ; GCN-LABEL: {{^}}test_s_dcache_inv_vol_insert_wait: -; GCN-NEXT: ; BB#0: +; GCN-NEXT: ; %bb.0: ; GCN-NEXT: s_dcache_inv_vol ; GCN: s_waitcnt lgkmcnt(0) ; encoding define amdgpu_kernel void @test_s_dcache_inv_vol_insert_wait() #0 { diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.wb.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.wb.ll index 99b6513504395..254a0fae3c3b7 100644 --- a/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.wb.ll +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.wb.ll @@ -4,7 +4,7 @@ declare void @llvm.amdgcn.s.dcache.wb() #0 declare void @llvm.amdgcn.s.waitcnt(i32) #0 ; VI-LABEL: {{^}}test_s_dcache_wb: -; VI-NEXT: ; BB#0: +; VI-NEXT: ; %bb.0: ; VI-NEXT: s_dcache_wb ; encoding: [0x00,0x00,0x84,0xc0,0x00,0x00,0x00,0x00] ; VI-NEXT: s_endpgm define amdgpu_kernel void @test_s_dcache_wb() #0 { @@ -13,7 +13,7 @@ define amdgpu_kernel void @test_s_dcache_wb() #0 { } ; VI-LABEL: {{^}}test_s_dcache_wb_insert_wait: -; VI-NEXT: ; BB#0: +; VI-NEXT: ; %bb.0: ; VI-NEXT: s_dcache_wb ; VI: s_waitcnt lgkmcnt(0) ; encoding define amdgpu_kernel void @test_s_dcache_wb_insert_wait() #0 { diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.wb.vol.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.wb.vol.ll index 844fcecdb48bf..929cd1c5f0bbd 100644 --- a/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.wb.vol.ll +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.wb.vol.ll @@ -4,7 +4,7 @@ declare void @llvm.amdgcn.s.dcache.wb.vol() #0 declare void @llvm.amdgcn.s.waitcnt(i32) #0 ; VI-LABEL: {{^}}test_s_dcache_wb_vol: -; VI-NEXT: ; BB#0: +; VI-NEXT: ; %bb.0: ; VI-NEXT: s_dcache_wb_vol ; encoding: [0x00,0x00,0x8c,0xc0,0x00,0x00,0x00,0x00] ; VI-NEXT: s_endpgm define amdgpu_kernel void @test_s_dcache_wb_vol() #0 { @@ -13,7 +13,7 @@ define amdgpu_kernel void @test_s_dcache_wb_vol() #0 { } ; VI-LABEL: {{^}}test_s_dcache_wb_vol_insert_wait: -; VI-NEXT: ; BB#0: +; VI-NEXT: ; %bb.0: ; VI-NEXT: s_dcache_wb_vol ; VI: s_waitcnt lgkmcnt(0) ; encoding define amdgpu_kernel void @test_s_dcache_wb_vol_insert_wait() #0 { diff --git a/test/CodeGen/AMDGPU/loop_break.ll b/test/CodeGen/AMDGPU/loop_break.ll index 4acd1b2479574..b2641cd4d2e41 100644 --- a/test/CodeGen/AMDGPU/loop_break.ll +++ b/test/CodeGen/AMDGPU/loop_break.ll @@ -31,7 +31,7 @@ ; GCN: s_and_b64 vcc, exec, vcc ; GCN-NEXT: s_cbranch_vccnz [[FLOW:BB[0-9]+_[0-9]+]] -; GCN: ; BB#2: ; %bb4 +; GCN: ; %bb.2: ; %bb4 ; GCN: buffer_load_dword ; GCN: v_cmp_ge_i32_e32 vcc, ; GCN: s_or_b64 [[MASK]], vcc, [[INITMASK]] @@ -41,7 +41,7 @@ ; GCN: s_andn2_b64 exec, exec, [[MASK]] ; GCN-NEXT: s_cbranch_execnz [[LOOP_ENTRY]] -; GCN: ; BB#4: ; %bb9 +; GCN: ; %bb.4: ; %bb9 ; GCN-NEXT: s_endpgm define amdgpu_kernel void @break_loop(i32 %arg) #0 { bb: diff --git a/test/CodeGen/AMDGPU/memory-legalizer-atomic-fence.ll b/test/CodeGen/AMDGPU/memory-legalizer-atomic-fence.ll index a563cfd028311..c8e920a1854aa 100644 --- a/test/CodeGen/AMDGPU/memory-legalizer-atomic-fence.ll +++ b/test/CodeGen/AMDGPU/memory-legalizer-atomic-fence.ll @@ -3,7 +3,7 @@ ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC -check-prefix=GCN -check-prefix=GFX8 %s ; FUNC-LABEL: {{^}}system_acquire -; GCN: BB#0 +; GCN: %bb.0 ; GCN-NOT: ATOMIC_FENCE ; GFX6: s_waitcnt vmcnt(0){{$}} ; GFX6-NEXT: buffer_wbinvl1{{$}} @@ -17,7 +17,7 @@ entry: } ; FUNC-LABEL: {{^}}system_release -; GCN: BB#0 +; GCN: %bb.0 ; GCN-NOT: ATOMIC_FENCE ; GCN: s_waitcnt vmcnt(0){{$}} ; GCN: s_endpgm @@ -28,7 +28,7 @@ entry: } ; FUNC-LABEL: {{^}}system_acq_rel -; GCN: BB#0 +; GCN: %bb.0 ; GCN-NOT: ATOMIC_FENCE ; GCN: s_waitcnt vmcnt(0){{$}} ; GFX6: buffer_wbinvl1{{$}} @@ -41,7 +41,7 @@ entry: } ; FUNC-LABEL: {{^}}system_seq_cst -; GCN: BB#0 +; GCN: %bb.0 ; GCN-NOT: ATOMIC_FENCE ; GCN: s_waitcnt vmcnt(0){{$}} ; GFX6: buffer_wbinvl1{{$}} @@ -54,7 +54,7 @@ entry: } ; FUNC-LABEL: {{^}}singlethread_acquire -; GCN: BB#0 +; GCN: %bb.0 ; GCN-NOT: ATOMIC_FENCE ; GCN: s_endpgm define amdgpu_kernel void @singlethread_acquire() { @@ -64,7 +64,7 @@ entry: } ; FUNC-LABEL: {{^}}singlethread_release -; GCN: BB#0 +; GCN: %bb.0 ; GCN-NOT: ATOMIC_FENCE ; GCN: s_endpgm define amdgpu_kernel void @singlethread_release() { @@ -74,7 +74,7 @@ entry: } ; FUNC-LABEL: {{^}}singlethread_acq_rel -; GCN: BB#0 +; GCN: %bb.0 ; GCN-NOT: ATOMIC_FENCE ; GCN: s_endpgm define amdgpu_kernel void @singlethread_acq_rel() { @@ -84,7 +84,7 @@ entry: } ; FUNC-LABEL: {{^}}singlethread_seq_cst -; GCN: BB#0 +; GCN: %bb.0 ; GCN-NOT: ATOMIC_FENCE ; GCN: s_endpgm define amdgpu_kernel void @singlethread_seq_cst() { @@ -94,7 +94,7 @@ entry: } ; FUNC-LABEL: {{^}}agent_acquire -; GCN: BB#0 +; GCN: %bb.0 ; GCN-NOT: ATOMIC_FENCE ; GFX6: s_waitcnt vmcnt(0){{$}} ; GFX6-NEXT: buffer_wbinvl1{{$}} @@ -108,7 +108,7 @@ entry: } ; FUNC-LABEL: {{^}}agent_release -; GCN: BB#0 +; GCN: %bb.0 ; GCN-NOT: ATOMIC_FENCE ; GCN: s_waitcnt vmcnt(0){{$}} ; GCN: s_endpgm @@ -119,7 +119,7 @@ entry: } ; FUNC-LABEL: {{^}}agent_acq_rel -; GCN: BB#0 +; GCN: %bb.0 ; GCN-NOT: ATOMIC_FENCE ; GCN: s_waitcnt vmcnt(0){{$}} ; GFX6: buffer_wbinvl1{{$}} @@ -132,7 +132,7 @@ entry: } ; FUNC-LABEL: {{^}}agent_seq_cst -; GCN: BB#0 +; GCN: %bb.0 ; GCN-NOT: ATOMIC_FENCE ; GCN: s_waitcnt vmcnt(0){{$}} ; GFX6: buffer_wbinvl1{{$}} @@ -145,7 +145,7 @@ entry: } ; FUNC-LABEL: {{^}}workgroup_acquire -; GCN: BB#0 +; GCN: %bb.0 ; GCN-NOT: ATOMIC_FENCE ; GCN: s_endpgm define amdgpu_kernel void @workgroup_acquire() { @@ -155,7 +155,7 @@ entry: } ; FUNC-LABEL: {{^}}workgroup_release -; GCN: BB#0 +; GCN: %bb.0 ; GCN-NOT: ATOMIC_FENCE ; GCN: s_endpgm define amdgpu_kernel void @workgroup_release() { @@ -165,7 +165,7 @@ entry: } ; FUNC-LABEL: {{^}}workgroup_acq_rel -; GCN: BB#0 +; GCN: %bb.0 ; GCN-NOT: ATOMIC_FENCE ; GCN: s_endpgm define amdgpu_kernel void @workgroup_acq_rel() { @@ -175,7 +175,7 @@ entry: } ; FUNC-LABEL: {{^}}workgroup_seq_cst -; GCN: BB#0 +; GCN: %bb.0 ; GCN-NOT: ATOMIC_FENCE ; GCN: s_endpgm define amdgpu_kernel void @workgroup_seq_cst() { @@ -185,7 +185,7 @@ entry: } ; FUNC-LABEL: {{^}}wavefront_acquire -; GCN: BB#0 +; GCN: %bb.0 ; GCN-NOT: ATOMIC_FENCE ; GCN: s_endpgm define amdgpu_kernel void @wavefront_acquire() { @@ -195,7 +195,7 @@ entry: } ; FUNC-LABEL: {{^}}wavefront_release -; GCN: BB#0 +; GCN: %bb.0 ; GCN-NOT: ATOMIC_FENCE ; GCN: s_endpgm define amdgpu_kernel void @wavefront_release() { @@ -205,7 +205,7 @@ entry: } ; FUNC-LABEL: {{^}}wavefront_acq_rel -; GCN: BB#0 +; GCN: %bb.0 ; GCN-NOT: ATOMIC_FENCE ; GCN: s_endpgm define amdgpu_kernel void @wavefront_acq_rel() { @@ -215,7 +215,7 @@ entry: } ; FUNC-LABEL: {{^}}wavefront_seq_cst -; GCN: BB#0 +; GCN: %bb.0 ; GCN-NOT: ATOMIC_FENCE ; GCN: s_endpgm define amdgpu_kernel void @wavefront_seq_cst() { diff --git a/test/CodeGen/AMDGPU/mubuf-offset-private.ll b/test/CodeGen/AMDGPU/mubuf-offset-private.ll index 5ff56f2ab66da..23bd2e4bc8239 100644 --- a/test/CodeGen/AMDGPU/mubuf-offset-private.ll +++ b/test/CodeGen/AMDGPU/mubuf-offset-private.ll @@ -141,7 +141,7 @@ define amdgpu_kernel void @store_private_offset_i8_max_offset_plus2() #0 { ; SICIVI: v_add_{{i|u}}32_e32 [[ADDR1:v[0-9]+]], vcc, 32, [[ADDR0]] ; SICIVI: buffer_store_dword v{{[0-9]+}}, [[ADDR1]], s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offen{{$}} -; GFX9: v_add_co_u32_e32 [[ADDR:v[0-9]+]], vcc, 4, +; GFX9: v_add_u32_e32 [[ADDR:v[0-9]+]], 4, ; GFX9: buffer_store_dword v{{[0-9]+}}, [[ADDR]], s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offen offset:32 define amdgpu_kernel void @store_private_unknown_bits_vaddr() #0 { %alloca = alloca [16 x i32], align 4 diff --git a/test/CodeGen/AMDGPU/multilevel-break.ll b/test/CodeGen/AMDGPU/multilevel-break.ll index 15de689b953e6..8cc02d497098b 100644 --- a/test/CodeGen/AMDGPU/multilevel-break.ll +++ b/test/CodeGen/AMDGPU/multilevel-break.ll @@ -34,7 +34,7 @@ ; GCN-NEXT: s_andn2_b64 exec, exec, [[OR_BREAK]] ; GCN-NEXT: s_cbranch_execnz [[INNER_LOOP]] -; GCN: ; BB#{{[0-9]+}}: ; %Flow1{{$}} +; GCN: ; %bb.{{[0-9]+}}: ; %Flow1{{$}} ; GCN-NEXT: ; in Loop: Header=[[OUTER_LOOP]] Depth=1 ; Ensure copy is eliminated diff --git a/test/CodeGen/AMDGPU/optimize-if-exec-masking.mir b/test/CodeGen/AMDGPU/optimize-if-exec-masking.mir index b5dc9d9dac841..24e8ed8e29cbf 100644 --- a/test/CodeGen/AMDGPU/optimize-if-exec-masking.mir +++ b/test/CodeGen/AMDGPU/optimize-if-exec-masking.mir @@ -184,8 +184,8 @@ body: | %sgpr2_sgpr3 = S_AND_B64 %sgpr0_sgpr1, killed %vcc, implicit-def %scc %sgpr0_sgpr1 = S_XOR_B64 %sgpr2_sgpr3, killed %sgpr0_sgpr1, implicit-def %scc %exec = S_MOV_B64_term killed %sgpr2_sgpr3 - SI_MASK_BRANCH %bb.2.end, implicit %exec - S_BRANCH %bb.1.if + SI_MASK_BRANCH %bb.2, implicit %exec + S_BRANCH %bb.1 bb.1.if: liveins: %sgpr0_sgpr1 @@ -241,8 +241,8 @@ body: | %vgpr0 = V_MOV_B32_e32 4, implicit %exec %sgpr2_sgpr3 = S_AND_B64 %sgpr0_sgpr1, killed %vcc, implicit-def %scc %exec = S_MOV_B64_term killed %sgpr2_sgpr3 - SI_MASK_BRANCH %bb.2.end, implicit %exec - S_BRANCH %bb.1.if + SI_MASK_BRANCH %bb.2, implicit %exec + S_BRANCH %bb.1 bb.1.if: liveins: %sgpr0_sgpr1 @@ -298,8 +298,8 @@ body: | %vgpr0 = V_MOV_B32_e32 4, implicit %exec %sgpr2_sgpr3 = S_OR_B64 %sgpr0_sgpr1, killed %vcc, implicit-def %scc %exec = S_MOV_B64_term killed %sgpr2_sgpr3 - SI_MASK_BRANCH %bb.2.end, implicit %exec - S_BRANCH %bb.1.if + SI_MASK_BRANCH %bb.2, implicit %exec + S_BRANCH %bb.1 bb.1.if: liveins: %sgpr0_sgpr1 @@ -359,8 +359,8 @@ body: | BUFFER_STORE_DWORD_OFFSET %vgpr0, undef %sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit %exec :: (store 4 into `i32 addrspace(1)* undef`) %sgpr0_sgpr1 = S_XOR_B64 %sgpr2_sgpr3, killed %sgpr0_sgpr1, implicit-def %scc %exec = S_MOV_B64_term killed %sgpr2_sgpr3 - SI_MASK_BRANCH %bb.2.end, implicit %exec - S_BRANCH %bb.1.if + SI_MASK_BRANCH %bb.2, implicit %exec + S_BRANCH %bb.1 bb.1.if: liveins: %sgpr0_sgpr1 @@ -384,7 +384,7 @@ body: | # CHECK: %sgpr0_sgpr1 = S_AND_B64 %sgpr0_sgpr1, killed %vcc, implicit-def %scc # CHECK-NEXT: %sgpr0_sgpr1 = S_XOR_B64 undef %sgpr2_sgpr3, killed %sgpr0_sgpr1, implicit-def %scc # CHECK-NEXT: %exec = COPY %sgpr0_sgpr1 -# CHECK-NEXT: SI_MASK_BRANCH %bb.2.end, implicit %exec +# CHECK-NEXT: SI_MASK_BRANCH %bb.2, implicit %exec name: optimize_if_and_saveexec_xor_wrong_reg alignment: 0 exposesReturnsTwice: false @@ -420,8 +420,8 @@ body: | %sgpr0_sgpr1 = S_AND_B64 %sgpr0_sgpr1, killed %vcc, implicit-def %scc %sgpr0_sgpr1 = S_XOR_B64 undef %sgpr2_sgpr3, killed %sgpr0_sgpr1, implicit-def %scc %exec = S_MOV_B64_term %sgpr0_sgpr1 - SI_MASK_BRANCH %bb.2.end, implicit %exec - S_BRANCH %bb.1.if + SI_MASK_BRANCH %bb.2, implicit %exec + S_BRANCH %bb.1 bb.1.if: liveins: %sgpr0_sgpr1 , %sgpr4_sgpr5_sgpr6_sgpr7 @@ -443,7 +443,7 @@ body: | # CHECK-NEXT: %sgpr2_sgpr3 = S_OR_B64 killed %sgpr2_sgpr3, 1, implicit-def %scc # CHECK-NEXT: %sgpr0_sgpr1 = S_XOR_B64 %sgpr2_sgpr3, killed %sgpr0_sgpr1, implicit-def %scc # CHECK-NEXT: %exec = COPY killed %sgpr2_sgpr3 -# CHECK-NEXT: SI_MASK_BRANCH %bb.2.end, implicit %exec +# CHECK-NEXT: SI_MASK_BRANCH %bb.2, implicit %exec name: optimize_if_and_saveexec_xor_modify_copy_to_exec alignment: 0 @@ -479,8 +479,8 @@ body: | %sgpr2_sgpr3 = S_OR_B64 killed %sgpr2_sgpr3, 1, implicit-def %scc %sgpr0_sgpr1 = S_XOR_B64 %sgpr2_sgpr3, killed %sgpr0_sgpr1, implicit-def %scc %exec = S_MOV_B64_term killed %sgpr2_sgpr3 - SI_MASK_BRANCH %bb.2.end, implicit %exec - S_BRANCH %bb.1.if + SI_MASK_BRANCH %bb.2, implicit %exec + S_BRANCH %bb.1 bb.1.if: liveins: %sgpr0_sgpr1 @@ -540,8 +540,8 @@ body: | %sgpr2_sgpr3 = S_AND_B64 %sgpr0_sgpr1, killed %vcc, implicit-def %scc %sgpr0_sgpr1 = S_XOR_B64 %sgpr2_sgpr3, killed %sgpr0_sgpr1, implicit-def %scc %exec = S_MOV_B64_term %sgpr2_sgpr3 - SI_MASK_BRANCH %bb.2.end, implicit %exec - S_BRANCH %bb.1.if + SI_MASK_BRANCH %bb.2, implicit %exec + S_BRANCH %bb.1 bb.1.if: liveins: %sgpr0_sgpr1, %sgpr2_sgpr3 @@ -565,7 +565,7 @@ body: | # CHECK: %sgpr0_sgpr1 = COPY %exec # CHECK: %sgpr2_sgpr3 = S_LSHR_B64 %sgpr0_sgpr1, killed %vcc_lo, implicit-def %scc # CHECK-NEXT: %exec = COPY killed %sgpr2_sgpr3 -# CHECK-NEXT: SI_MASK_BRANCH %bb.2.end, implicit %exec +# CHECK-NEXT: SI_MASK_BRANCH %bb.2, implicit %exec name: optimize_if_unknown_saveexec alignment: 0 @@ -599,8 +599,8 @@ body: | %vgpr0 = V_MOV_B32_e32 4, implicit %exec %sgpr2_sgpr3 = S_LSHR_B64 %sgpr0_sgpr1, killed %vcc_lo, implicit-def %scc %exec = S_MOV_B64_term killed %sgpr2_sgpr3 - SI_MASK_BRANCH %bb.2.end, implicit %exec - S_BRANCH %bb.1.if + SI_MASK_BRANCH %bb.2, implicit %exec + S_BRANCH %bb.1 bb.1.if: liveins: %sgpr0_sgpr1 @@ -656,8 +656,8 @@ body: | %vgpr0 = V_MOV_B32_e32 4, implicit %exec %sgpr2_sgpr3 = S_ANDN2_B64 %sgpr0_sgpr1, killed %vcc, implicit-def %scc %exec = S_MOV_B64_term killed %sgpr2_sgpr3 - SI_MASK_BRANCH %bb.2.end, implicit %exec - S_BRANCH %bb.1.if + SI_MASK_BRANCH %bb.2, implicit %exec + S_BRANCH %bb.1 bb.1.if: liveins: %sgpr0_sgpr1 @@ -680,7 +680,7 @@ body: | # CHECK-LABEL: name: optimize_if_andn2_saveexec_no_commute{{$}} # CHECK: %sgpr2_sgpr3 = S_ANDN2_B64 killed %vcc, %sgpr0_sgpr1, implicit-def %scc # CHECK-NEXT: %exec = COPY killed %sgpr2_sgpr3 -# CHECK-NEXT: SI_MASK_BRANCH %bb.2.end, implicit %exec +# CHECK-NEXT: SI_MASK_BRANCH %bb.2, implicit %exec name: optimize_if_andn2_saveexec_no_commute alignment: 0 exposesReturnsTwice: false @@ -713,8 +713,8 @@ body: | %vgpr0 = V_MOV_B32_e32 4, implicit %exec %sgpr2_sgpr3 = S_ANDN2_B64 killed %vcc, %sgpr0_sgpr1, implicit-def %scc %exec = S_MOV_B64_term killed %sgpr2_sgpr3 - SI_MASK_BRANCH %bb.2.end, implicit %exec - S_BRANCH %bb.1.if + SI_MASK_BRANCH %bb.2, implicit %exec + S_BRANCH %bb.1 bb.1.if: liveins: %sgpr0_sgpr1 diff --git a/test/CodeGen/AMDGPU/pack.v2f16.ll b/test/CodeGen/AMDGPU/pack.v2f16.ll index 0be7d87df6682..dab2043438ff0 100644 --- a/test/CodeGen/AMDGPU/pack.v2f16.ll +++ b/test/CodeGen/AMDGPU/pack.v2f16.ll @@ -87,7 +87,7 @@ define amdgpu_kernel void @v_pack_v2f16(i32 addrspace(1)* %in0, i32 addrspace(1) ; GFX9: v_and_b32_e32 [[ELT0:v[0-9]+]], 0xffff, [[VAL0]] ; GFX9: v_lshl_or_b32 [[PACKED:v[0-9]+]], [[VAL1]], 16, [[ELT0]] -; GFX9: v_add{{(_co)?}}_{{i|u}}32_e32 v{{[0-9]+}}, vcc, 9, [[PACKED]] +; GFX9: v_add_u32_e32 v{{[0-9]+}}, 9, [[PACKED]] define amdgpu_kernel void @v_pack_v2f16_user(i32 addrspace(1)* %in0, i32 addrspace(1)* %in1) #0 { %tid = call i32 @llvm.amdgcn.workitem.id.x() %tid.ext = sext i32 %tid to i64 diff --git a/test/CodeGen/AMDGPU/pack.v2i16.ll b/test/CodeGen/AMDGPU/pack.v2i16.ll index d211999ada130..233bf24c799d8 100644 --- a/test/CodeGen/AMDGPU/pack.v2i16.ll +++ b/test/CodeGen/AMDGPU/pack.v2i16.ll @@ -81,7 +81,7 @@ define amdgpu_kernel void @v_pack_v2i16(i32 addrspace(1)* %in0, i32 addrspace(1) ; GFX9: v_and_b32_e32 [[MASKED:v[0-9]+]], 0xffff, [[VAL0]] ; GFX9: v_lshl_or_b32 [[PACKED:v[0-9]+]], [[VAL1]], 16, [[MASKED]] -; GFX9: v_add_co_u32_e32 v{{[0-9]+}}, vcc, 9, [[PACKED]] +; GFX9: v_add_u32_e32 v{{[0-9]+}}, 9, [[PACKED]] define amdgpu_kernel void @v_pack_v2i16_user(i32 addrspace(1)* %in0, i32 addrspace(1)* %in1) #0 { %tid = call i32 @llvm.amdgcn.workitem.id.x() %tid.ext = sext i32 %tid to i64 diff --git a/test/CodeGen/AMDGPU/promote-alloca-to-lds-select.ll b/test/CodeGen/AMDGPU/promote-alloca-to-lds-select.ll index 55c2229fb6bdb..ebeed0dd4435b 100644 --- a/test/CodeGen/AMDGPU/promote-alloca-to-lds-select.ll +++ b/test/CodeGen/AMDGPU/promote-alloca-to-lds-select.ll @@ -130,4 +130,4 @@ bb: } attributes #0 = { norecurse nounwind "amdgpu-waves-per-eu"="1,1" } -attributes #1 = { norecurse nounwind } \ No newline at end of file +attributes #1 = { norecurse nounwind } diff --git a/test/CodeGen/AMDGPU/regcoalesce-dbg.mir b/test/CodeGen/AMDGPU/regcoalesce-dbg.mir index c5a9a0ad01abe..69538d8b7382f 100644 --- a/test/CodeGen/AMDGPU/regcoalesce-dbg.mir +++ b/test/CodeGen/AMDGPU/regcoalesce-dbg.mir @@ -63,7 +63,7 @@ body: | %19.sub1 = COPY killed %18 %10 = S_MOV_B32 61440 %11 = S_MOV_B32 0 - DBG_VALUE debug-use %11, debug-use _, !1, !8, debug-location !9 + DBG_VALUE debug-use %11, debug-use %noreg, !1, !8, debug-location !9 undef %12.sub0 = COPY killed %11 %12.sub1 = COPY killed %10 undef %13.sub0_sub1 = COPY killed %4 diff --git a/test/CodeGen/AMDGPU/ret_jump.ll b/test/CodeGen/AMDGPU/ret_jump.ll index 7c2e28108df8a..f87e8cbea4fc2 100644 --- a/test/CodeGen/AMDGPU/ret_jump.ll +++ b/test/CodeGen/AMDGPU/ret_jump.ll @@ -57,7 +57,7 @@ ret.bb: ; preds = %else, %main_body ; GCN-LABEL: {{^}}uniform_br_nontrivial_ret_divergent_br_nontrivial_unreachable: ; GCN: s_cbranch_vccnz [[RET_BB:BB[0-9]+_[0-9]+]] -; GCN: ; BB#{{[0-9]+}}: ; %else +; GCN: ; %bb.{{[0-9]+}}: ; %else ; GCN: s_and_saveexec_b64 [[SAVE_EXEC:s\[[0-9]+:[0-9]+\]]], vcc ; GCN-NEXT: ; mask branch [[FLOW1:BB[0-9]+_[0-9]+]] diff --git a/test/CodeGen/AMDGPU/saddo.ll b/test/CodeGen/AMDGPU/saddo.ll index c92ea657be0fd..0b52821f72cc9 100644 --- a/test/CodeGen/AMDGPU/saddo.ll +++ b/test/CodeGen/AMDGPU/saddo.ll @@ -1,5 +1,6 @@ -; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s -; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs< %s | FileCheck -check-prefixes=GCN,SICIVI,FUNC %s +; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -verify-machineinstrs< %s | FileCheck -check-prefixes=GCN,SICIVI,FUNC %s +; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -verify-machineinstrs< %s | FileCheck -check-prefixes=GCN,GFX9,FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=cypress -verify-machineinstrs< %s declare { i32, i1 } @llvm.sadd.with.overflow.i32(i32, i32) nounwind readnone @@ -49,8 +50,11 @@ define amdgpu_kernel void @s_saddo_i64(i64 addrspace(1)* %out, i1 addrspace(1)* } ; FUNC-LABEL: {{^}}v_saddo_i64: -; SI: v_add_{{[iu]}}32 -; SI: v_addc_u32 +; SICIVI: v_add_{{[iu]}}32_e32 v{{[0-9]+}}, vcc +; SICIVI: v_addc_u32_e32 v{{[0-9]+}}, vcc + +; GFX9: v_add_co_u32_e32 v{{[0-9]+}}, vcc +; GFX9: v_addc_co_u32_e32 v{{[0-9]+}}, vcc define amdgpu_kernel void @v_saddo_i64(i64 addrspace(1)* %out, i1 addrspace(1)* %carryout, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) nounwind { %a = load i64, i64 addrspace(1)* %aptr, align 4 %b = load i64, i64 addrspace(1)* %bptr, align 4 diff --git a/test/CodeGen/AMDGPU/scratch-simple.ll b/test/CodeGen/AMDGPU/scratch-simple.ll index 5e0178072e5e2..a579844dfde66 100644 --- a/test/CodeGen/AMDGPU/scratch-simple.ll +++ b/test/CodeGen/AMDGPU/scratch-simple.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=amdgcn -mcpu=verde -mattr=+vgpr-spilling -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=SI %s -; RUN: llc -march=amdgcn -mcpu=gfx804 -mattr=-flat-for-global -mattr=+vgpr-spilling -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=SI %s -; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -mattr=+vgpr-spilling -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=GFX9 %s +; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=verde -mattr=+vgpr-spilling -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=SI %s +; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx804 -mattr=-flat-for-global -mattr=+vgpr-spilling -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=SI %s +; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx900 -mattr=-flat-for-global -mattr=+vgpr-spilling -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=GFX9 %s ; This used to fail due to a v_add_i32 instruction with an illegal immediate ; operand that was created during Local Stack Slot Allocation. Test case derived diff --git a/test/CodeGen/AMDGPU/sdiv.ll b/test/CodeGen/AMDGPU/sdiv.ll index f75bec411d28b..b79bca54bbdd3 100644 --- a/test/CodeGen/AMDGPU/sdiv.ll +++ b/test/CodeGen/AMDGPU/sdiv.ll @@ -1,5 +1,6 @@ ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; The code generated by sdiv is long and complex and may frequently change. diff --git a/test/CodeGen/AMDGPU/sdwa-peephole-instr.mir b/test/CodeGen/AMDGPU/sdwa-peephole-instr.mir index 77c231c584a24..0d1534e3f4e84 100644 --- a/test/CodeGen/AMDGPU/sdwa-peephole-instr.mir +++ b/test/CodeGen/AMDGPU/sdwa-peephole-instr.mir @@ -148,13 +148,13 @@ body: | # GCN-LABEL: {{^}}name: vop2_instructions -# VI: %{{[0-9]+}}:vgpr_32 = V_AND_B32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 6, 0, 6, 5, implicit %exec +# VI: %{{[0-9]+}}:vgpr_32 = V_AND_B32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 5, 0, 6, 5, implicit %exec # VI: %{{[0-9]+}}:vgpr_32 = V_ADD_F32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 0, 5, 0, 5, 1, implicit %exec # VI: %{{[0-9]+}}:vgpr_32 = V_SUB_F16_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 0, 6, 0, 5, 1, implicit %exec # VI: %{{[0-9]+}}:vgpr_32 = V_MAC_F32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, %{{[0-9]+}}, 0, 0, 6, 0, 6, 1, implicit %exec # VI: %{{[0-9]+}}:vgpr_32 = V_MAC_F16_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, %{{[0-9]+}}, 0, 0, 6, 0, 5, 1, implicit %exec -# GFX9: %{{[0-9]+}}:vgpr_32 = V_AND_B32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 6, 0, 6, 5, implicit %exec +# GFX9: %{{[0-9]+}}:vgpr_32 = V_AND_B32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 5, 0, 6, 5, implicit %exec # GFX9: %{{[0-9]+}}:vgpr_32 = V_ADD_F32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 0, 5, 0, 5, 1, implicit %exec # GFX9: %{{[0-9]+}}:vgpr_32 = V_SUB_F16_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 0, 6, 0, 5, 1, implicit %exec # GFX9: %{{[0-9]+}}:vgpr_32 = V_MAC_F32_e32 %{{[0-9]+}}, %{{[0-9]+}}, %{{[0-9]+}}, implicit %exec diff --git a/test/CodeGen/AMDGPU/sdwa-peephole.ll b/test/CodeGen/AMDGPU/sdwa-peephole.ll index ec7dc1d3d3c3d..8c67d6e742716 100644 --- a/test/CodeGen/AMDGPU/sdwa-peephole.ll +++ b/test/CodeGen/AMDGPU/sdwa-peephole.ll @@ -7,7 +7,8 @@ ; NOSDWA: v_add_u32_e32 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v[[DST]] ; NOSDWA-NOT: v_add_{{(_co)?}}_u32_sdwa -; SDWA: v_add{{(_co)?}}_u32_sdwa v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; VI: v_add_u32_sdwa v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX9: v_add_u32_sdwa v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 define amdgpu_kernel void @add_shr_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { %a = load i32, i32 addrspace(1)* %in, align 4 @@ -22,8 +23,8 @@ define amdgpu_kernel void @add_shr_i32(i32 addrspace(1)* %out, i32 addrspace(1)* ; NOSDWA: v_subrev_u32_e32 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v[[DST]] ; NOSDWA-NOT: v_subrev_{{(_co)?}}_u32_sdwa -; SDWA: v_subrev{{(_co)?}}_u32_sdwa v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 - +; VI: v_subrev_u32_sdwa v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX9: v_sub_u32_sdwa v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD define amdgpu_kernel void @sub_shr_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { %a = load i32, i32 addrspace(1)* %in, align 4 %shr = lshr i32 %a, 16 diff --git a/test/CodeGen/AMDGPU/sdwa-preserve.mir b/test/CodeGen/AMDGPU/sdwa-preserve.mir new file mode 100644 index 0000000000000..99a000cbd39a9 --- /dev/null +++ b/test/CodeGen/AMDGPU/sdwa-preserve.mir @@ -0,0 +1,56 @@ +# RUN: llc -march=amdgcn -mcpu=fiji -start-before=si-peephole-sdwa -verify-machineinstrs -o - %s | FileCheck -check-prefix=SDWA %s +# RUN: llc -march=amdgcn -mcpu=gfx900 -start-before=si-peephole-sdwa -verify-machineinstrs -o - %s | FileCheck -check-prefix=SDWA %s + +# SDWA-LABEL: {{^}}add_f16_u32_preserve + +# SDWA: flat_load_dword [[FIRST:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}] +# SDWA: flat_load_dword [[SECOND:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}] + +# SDWA: v_mul_f32_sdwa [[RES:v[0-9]+]], [[FIRST]], [[SECOND]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:BYTE_3 +# SDWA: v_add_f16_sdwa [[RES:v[0-9]+]], [[FIRST]], [[SECOND]] dst_sel:BYTE_1 dst_unused:UNUSED_PRESERVE src0_sel:WORD_0 src1_sel:WORD_1 + +# SDWA: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], [[RES]] + +--- +name: add_f16_u32_preserve +tracksRegLiveness: true +registers: + - { id: 0, class: vreg_64 } + - { id: 1, class: vreg_64 } + - { id: 2, class: sreg_64 } + - { id: 3, class: vgpr_32 } + - { id: 4, class: vgpr_32 } + - { id: 5, class: vgpr_32 } + - { id: 6, class: vgpr_32 } + - { id: 7, class: vgpr_32 } + - { id: 8, class: vgpr_32 } + - { id: 9, class: vgpr_32 } + - { id: 10, class: vgpr_32 } + - { id: 11, class: vgpr_32 } + - { id: 12, class: vgpr_32 } + - { id: 13, class: vgpr_32 } +body: | + bb.0: + liveins: %vgpr0_vgpr1, %vgpr2_vgpr3, %sgpr30_sgpr31 + + %2 = COPY %sgpr30_sgpr31 + %1 = COPY %vgpr2_vgpr3 + %0 = COPY %vgpr0_vgpr1 + %3 = FLAT_LOAD_DWORD %0, 0, 0, 0, implicit %exec, implicit %flat_scr :: (load 4) + %4 = FLAT_LOAD_DWORD %1, 0, 0, 0, implicit %exec, implicit %flat_scr :: (load 4) + + %5 = V_AND_B32_e32 65535, %3, implicit %exec + %6 = V_LSHRREV_B32_e64 16, %4, implicit %exec + %7 = V_BFE_U32 %3, 8, 8, implicit %exec + %8 = V_LSHRREV_B32_e32 24, %4, implicit %exec + + %9 = V_ADD_F16_e64 0, %5, 0, %6, 0, 0, implicit %exec + %10 = V_LSHLREV_B16_e64 8, %9, implicit %exec + %11 = V_MUL_F32_e64 0, %7, 0, %8, 0, 0, implicit %exec + %12 = V_LSHLREV_B32_e64 16, %11, implicit %exec + + %13 = V_OR_B32_e64 %10, %12, implicit %exec + + FLAT_STORE_DWORD %0, %13, 0, 0, 0, implicit %exec, implicit %flat_scr :: (store 4) + %sgpr30_sgpr31 = COPY %2 + S_SETPC_B64_return %sgpr30_sgpr31 diff --git a/test/CodeGen/AMDGPU/sgpr-control-flow.ll b/test/CodeGen/AMDGPU/sgpr-control-flow.ll index 8e18ab5554e45..575938b5a5cb2 100644 --- a/test/CodeGen/AMDGPU/sgpr-control-flow.ll +++ b/test/CodeGen/AMDGPU/sgpr-control-flow.ll @@ -37,7 +37,7 @@ endif: ; SI: s_cmp_lg_u32 ; SI: s_cbranch_scc0 [[IF:BB[0-9]+_[0-9]+]] -; SI: ; BB#1: ; %else +; SI: ; %bb.1: ; %else ; SI: s_load_dword [[LOAD0:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xe ; SI: s_load_dword [[LOAD1:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xf ; SI-NOT: add diff --git a/test/CodeGen/AMDGPU/si-lower-control-flow-unreachable-block.ll b/test/CodeGen/AMDGPU/si-lower-control-flow-unreachable-block.ll index 7423a4a275388..ce85a66634044 100644 --- a/test/CodeGen/AMDGPU/si-lower-control-flow-unreachable-block.ll +++ b/test/CodeGen/AMDGPU/si-lower-control-flow-unreachable-block.ll @@ -55,7 +55,7 @@ unreachable: ; GCN: s_cmp_lg_u32 ; GCN: s_cbranch_scc0 [[UNREACHABLE:BB[0-9]+_[0-9]+]] -; GCN-NEXT: BB#{{[0-9]+}}: ; %ret +; GCN-NEXT: %bb.{{[0-9]+}}: ; %ret ; GCN-NEXT: s_endpgm ; GCN: [[UNREACHABLE]]: diff --git a/test/CodeGen/AMDGPU/sibling-call.ll b/test/CodeGen/AMDGPU/sibling-call.ll index 344c05f56cf4f..f7e8a1d80e9ba 100644 --- a/test/CodeGen/AMDGPU/sibling-call.ll +++ b/test/CodeGen/AMDGPU/sibling-call.ll @@ -1,11 +1,13 @@ -; RUN: llc -mtriple=amdgcn-amd-amdhsa-amdgiz -mcpu=fiji -mattr=-flat-for-global -enable-ipra=0 -amdgpu-sroa=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI,MESA %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa-amdgiz -mcpu=hawaii -enable-ipra=0 -amdgpu-sroa=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CI,MESA %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa-amdgiz -mcpu=gfx900 -mattr=-flat-for-global -enable-ipra=0 -amdgpu-sroa=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9,VI,MESA %s +; RUN: llc -mtriple=amdgcn-amd-amdhsa-amdgiz -mcpu=fiji -mattr=-flat-for-global -enable-ipra=0 -amdgpu-sroa=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI,CIVI,MESA %s +; RUN: llc -mtriple=amdgcn-amd-amdhsa-amdgiz -mcpu=hawaii -enable-ipra=0 -amdgpu-sroa=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CI,CIVI,MESA %s +; RUN: llc -mtriple=amdgcn-amd-amdhsa-amdgiz -mcpu=gfx900 -mattr=-flat-for-global -enable-ipra=0 -amdgpu-sroa=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9,MESA %s target datalayout = "A5" +; FIXME: Why is this commuted only sometimes? ; GCN-LABEL: {{^}}i32_fastcc_i32_i32: ; GCN: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_add_{{[_coiu]*}}32_e32 v0, vcc, v1, v0 +; CIVI-NEXT: v_add_{{i|u}}32_e32 v0, vcc, v1, v0 +; GFX9-NEXT: v_add_u32_e32 v0, v0, v1 ; GCN-NEXT: s_setpc_b64 define fastcc i32 @i32_fastcc_i32_i32(i32 %arg0, i32 %arg1) #1 { %add0 = add i32 %arg0, %arg1 @@ -14,7 +16,8 @@ define fastcc i32 @i32_fastcc_i32_i32(i32 %arg0, i32 %arg1) #1 { ; GCN-LABEL: {{^}}i32_fastcc_i32_i32_stack_object: ; GCN: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN: v_add_{{[_coiu]*}}32_e32 v0, vcc, v1, v +; CIVI-NEXT: v_add_{{i|u}}32_e32 v0, vcc, v1, v0 +; GFX9-NEXT: v_add_u32_e32 v0, v0, v1 ; GCN: s_mov_b32 s5, s32 ; GCN: buffer_store_dword v{{[0-9]+}}, off, s[0:3], s5 offset:24 ; GCN: s_waitcnt vmcnt(0) @@ -84,7 +87,10 @@ entry: ; GCN-NEXT: s_mov_b32 s5, s32 ; GCN-NEXT: buffer_load_dword v1, off, s[0:3], s5 offset:4 ; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: v_add_{{[_coiu]*}}32_e32 v0, vcc, v1, v0 + +; CIVI-NEXT: v_add_{{i|u}}32_e32 v0, vcc, v1, v0 +; GFX9-NEXT: v_add_u32_e32 v0, v0, v1 + ; GCN-NEXT: s_setpc_b64 s[30:31] define fastcc i32 @i32_fastcc_i32_byval_i32(i32 %arg0, i32 addrspace(5)* byval align 4 %arg1) #1 { %arg1.load = load i32, i32 addrspace(5)* %arg1, align 4 @@ -123,9 +129,16 @@ entry: ; GCN: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-DAG: buffer_load_dword [[LOAD_0:v[0-9]+]], off, s[0:3], s5 offset:4 ; GCN-DAG: buffer_load_dword [[LOAD_1:v[0-9]+]], off, s[0:3], s5 offset:8 -; GCN-DAG: v_add_{{[_coiu]*}}32_e32 v0, vcc, v1, v0 -; GCN: v_add_{{[_coiu]*}}32_e32 v0, vcc, [[LOAD_0]], v0 -; GCN: v_add_{{[_coiu]*}}32_e32 v0, vcc, [[LOAD_1]], v0 + +; CIVI-NEXT: v_add_{{i|u}}32_e32 v0, vcc, v1, v0 +; CIVI: v_add_{{i|u}}32_e32 v0, vcc, [[LOAD_0]], v0 +; CIVI: v_add_{{i|u}}32_e32 v0, vcc, [[LOAD_1]], v0 + + +; GFX9-NEXT: v_add_u32_e32 v0, v0, v1 +; GFX9: v_add_u32_e32 v0, v0, [[LOAD_0]] +; GFX9: v_add_u32_e32 v0, v0, [[LOAD_1]] + ; GCN-NEXT: s_setpc_b64 define fastcc i32 @i32_fastcc_i32_i32_a32i32(i32 %arg0, i32 %arg1, [32 x i32] %large) #1 { %val_firststack = extractvalue [32 x i32] %large, 30 diff --git a/test/CodeGen/AMDGPU/skip-if-dead.ll b/test/CodeGen/AMDGPU/skip-if-dead.ll index ed7e06ee4e243..9ae36b0a06c21 100644 --- a/test/CodeGen/AMDGPU/skip-if-dead.ll +++ b/test/CodeGen/AMDGPU/skip-if-dead.ll @@ -1,7 +1,7 @@ ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s ; CHECK-LABEL: {{^}}test_kill_depth_0_imm_pos: -; CHECK-NEXT: ; BB#0: +; CHECK-NEXT: ; %bb.0: ; CHECK-NEXT: s_endpgm define amdgpu_ps void @test_kill_depth_0_imm_pos() #0 { call void @llvm.AMDGPU.kill(float 0.0) @@ -9,9 +9,9 @@ define amdgpu_ps void @test_kill_depth_0_imm_pos() #0 { } ; CHECK-LABEL: {{^}}test_kill_depth_0_imm_neg: -; CHECK-NEXT: ; BB#0: +; CHECK-NEXT: ; %bb.0: ; CHECK-NEXT: s_mov_b64 exec, 0 -; CHECK-NEXT: ; BB#1: +; CHECK-NEXT: ; %bb.1: ; CHECK-NEXT: s_endpgm define amdgpu_ps void @test_kill_depth_0_imm_neg() #0 { call void @llvm.AMDGPU.kill(float -0.0) @@ -20,11 +20,11 @@ define amdgpu_ps void @test_kill_depth_0_imm_neg() #0 { ; FIXME: Ideally only one would be emitted ; CHECK-LABEL: {{^}}test_kill_depth_0_imm_neg_x2: -; CHECK-NEXT: ; BB#0: +; CHECK-NEXT: ; %bb.0: ; CHECK-NEXT: s_mov_b64 exec, 0 -; CHECK-NEXT: ; BB#1: +; CHECK-NEXT: ; %bb.1: ; CHECK-NEXT: s_mov_b64 exec, 0 -; CHECK-NEXT: ; BB#2: +; CHECK-NEXT: ; %bb.2: ; CHECK-NEXT: s_endpgm define amdgpu_ps void @test_kill_depth_0_imm_neg_x2() #0 { call void @llvm.AMDGPU.kill(float -0.0) @@ -33,9 +33,9 @@ define amdgpu_ps void @test_kill_depth_0_imm_neg_x2() #0 { } ; CHECK-LABEL: {{^}}test_kill_depth_var: -; CHECK-NEXT: ; BB#0: +; CHECK-NEXT: ; %bb.0: ; CHECK-NEXT: v_cmpx_le_f32_e32 vcc, 0, v0 -; CHECK-NEXT: ; BB#1: +; CHECK-NEXT: ; %bb.1: ; CHECK-NEXT: s_endpgm define amdgpu_ps void @test_kill_depth_var(float %x) #0 { call void @llvm.AMDGPU.kill(float %x) @@ -44,11 +44,11 @@ define amdgpu_ps void @test_kill_depth_var(float %x) #0 { ; FIXME: Ideally only one would be emitted ; CHECK-LABEL: {{^}}test_kill_depth_var_x2_same: -; CHECK-NEXT: ; BB#0: +; CHECK-NEXT: ; %bb.0: ; CHECK-NEXT: v_cmpx_le_f32_e32 vcc, 0, v0 -; CHECK-NEXT: ; BB#1: +; CHECK-NEXT: ; %bb.1: ; CHECK-NEXT: v_cmpx_le_f32_e32 vcc, 0, v0 -; CHECK-NEXT: ; BB#2: +; CHECK-NEXT: ; %bb.2: ; CHECK-NEXT: s_endpgm define amdgpu_ps void @test_kill_depth_var_x2_same(float %x) #0 { call void @llvm.AMDGPU.kill(float %x) @@ -57,11 +57,11 @@ define amdgpu_ps void @test_kill_depth_var_x2_same(float %x) #0 { } ; CHECK-LABEL: {{^}}test_kill_depth_var_x2: -; CHECK-NEXT: ; BB#0: +; CHECK-NEXT: ; %bb.0: ; CHECK-NEXT: v_cmpx_le_f32_e32 vcc, 0, v0 -; CHECK-NEXT: ; BB#1: +; CHECK-NEXT: ; %bb.1: ; CHECK-NEXT: v_cmpx_le_f32_e32 vcc, 0, v1 -; CHECK-NEXT: ; BB#2: +; CHECK-NEXT: ; %bb.2: ; CHECK-NEXT: s_endpgm define amdgpu_ps void @test_kill_depth_var_x2(float %x, float %y) #0 { call void @llvm.AMDGPU.kill(float %x) @@ -70,12 +70,12 @@ define amdgpu_ps void @test_kill_depth_var_x2(float %x, float %y) #0 { } ; CHECK-LABEL: {{^}}test_kill_depth_var_x2_instructions: -; CHECK-NEXT: ; BB#0: +; CHECK-NEXT: ; %bb.0: ; CHECK-NEXT: v_cmpx_le_f32_e32 vcc, 0, v0 -; CHECK-NEXT: ; BB#1: +; CHECK-NEXT: ; %bb.1: ; CHECK: v_mov_b32_e64 v7, -1 ; CHECK: v_cmpx_le_f32_e32 vcc, 0, v7 -; CHECK-NEXT: ; BB#2: +; CHECK-NEXT: ; %bb.2: ; CHECK-NEXT: s_endpgm define amdgpu_ps void @test_kill_depth_var_x2_instructions(float %x) #0 { call void @llvm.AMDGPU.kill(float %x) @@ -90,7 +90,7 @@ define amdgpu_ps void @test_kill_depth_var_x2_instructions(float %x) #0 { ; CHECK: s_cmp_lg_u32 s{{[0-9]+}}, 0 ; CHECK: s_cbranch_scc1 [[RETURN_BB:BB[0-9]+_[0-9]+]] -; CHECK-NEXT: ; BB#1: +; CHECK-NEXT: ; %bb.1: ; CHECK: v_mov_b32_e64 v7, -1 ; CHECK: v_nop_e64 ; CHECK: v_nop_e64 @@ -105,7 +105,7 @@ define amdgpu_ps void @test_kill_depth_var_x2_instructions(float %x) #0 { ; CHECK: v_cmpx_le_f32_e32 vcc, 0, v7 ; CHECK-NEXT: s_cbranch_execnz [[SPLIT_BB:BB[0-9]+_[0-9]+]] -; CHECK-NEXT: ; BB#2: +; CHECK-NEXT: ; %bb.2: ; CHECK-NEXT: exp null off, off, off, off done vm ; CHECK-NEXT: s_endpgm @@ -141,7 +141,7 @@ exit: ; CHECK-NEXT: v_mov_b32_e32 v{{[0-9]+}}, 0 ; CHECK-NEXT: s_cbranch_scc1 [[RETURN_BB:BB[0-9]+_[0-9]+]] -; CHECK-NEXT: ; BB#1: ; %bb +; CHECK-NEXT: ; %bb.1: ; %bb ; CHECK: v_mov_b32_e64 v7, -1 ; CHECK: v_nop_e64 ; CHECK: v_nop_e64 @@ -157,7 +157,7 @@ exit: ; CHECK: v_cmpx_le_f32_e32 vcc, 0, v7 ; CHECK-NEXT: s_cbranch_execnz [[SPLIT_BB:BB[0-9]+_[0-9]+]] -; CHECK-NEXT: ; BB#2: +; CHECK-NEXT: ; %bb.2: ; CHECK-NEXT: exp null off, off, off, off done vm ; CHECK-NEXT: s_endpgm @@ -215,7 +215,7 @@ exit: ; CHECK: v_nop_e64 ; CHECK: v_cmpx_le_f32_e32 vcc, 0, v7 -; CHECK-NEXT: ; BB#3: +; CHECK-NEXT: ; %bb.3: ; CHECK: buffer_load_dword [[LOAD:v[0-9]+]] ; CHECK: v_cmp_eq_u32_e32 vcc, 0, [[LOAD]] ; CHECK-NEXT: s_and_b64 vcc, exec, vcc @@ -309,7 +309,7 @@ end: ; CHECK: [[SKIPKILL]]: ; CHECK: v_cmp_nge_f32_e32 vcc -; CHECK-NEXT: BB#3: ; %bb5 +; CHECK-NEXT: %bb.3: ; %bb5 ; CHECK-NEXT: .Lfunc_end{{[0-9]+}} define amdgpu_ps void @no_skip_no_successors(float inreg %arg, float inreg %arg1) #0 { bb: @@ -335,7 +335,7 @@ bb7: ; preds = %bb4 } ; CHECK-LABEL: {{^}}if_after_kill_block: -; CHECK: ; BB#0: +; CHECK: ; %bb.0: ; CHECK: s_and_saveexec_b64 ; CHECK: s_xor_b64 ; CHECK-NEXT: mask branch [[BB4:BB[0-9]+_[0-9]+]] diff --git a/test/CodeGen/AMDGPU/sminmax.ll b/test/CodeGen/AMDGPU/sminmax.ll index 10b85d3a94f91..96a318fef024b 100644 --- a/test/CodeGen/AMDGPU/sminmax.ll +++ b/test/CodeGen/AMDGPU/sminmax.ll @@ -1,6 +1,7 @@ -; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s -; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s -; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s +; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SIVI,FUNC %s +; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SIVI,FUNC %s +; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9,FUNC %s +; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefixes=EG,FUNC %s ; FUNC-LABEL: {{^}}s_abs_i32: ; GCN: s_abs_i32 @@ -17,9 +18,13 @@ define amdgpu_kernel void @s_abs_i32(i32 addrspace(1)* %out, i32 %val) nounwind } ; FUNC-LABEL: {{^}}v_abs_i32: -; GCN: v_sub_{{[iu]}}32_e32 [[NEG:v[0-9]+]], vcc, 0, [[SRC:v[0-9]+]] +; SIVI: v_sub_{{i|u}}32_e32 [[NEG:v[0-9]+]], vcc, 0, [[SRC:v[0-9]+]] +; GFX9: v_sub_u32_e32 [[NEG:v[0-9]+]], 0, [[SRC:v[0-9]+]] + ; GCN: v_max_i32_e32 {{v[0-9]+}}, [[SRC]], [[NEG]] -; GCN: v_add_{{[iu]}}32 + +; SIVI: v_add_{{i|u}}32_e32 v{{[0-9]+}}, vcc +; GFX9: v_add_u32_e32 v{{[0-9]+}}, 2 ; EG: MAX_INT define amdgpu_kernel void @v_abs_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %src) nounwind { @@ -33,7 +38,8 @@ define amdgpu_kernel void @v_abs_i32(i32 addrspace(1)* %out, i32 addrspace(1)* % } ; GCN-LABEL: {{^}}v_abs_i32_repeat_user: -; GCN: v_sub_{{[iu]}}32_e32 [[NEG:v[0-9]+]], vcc, 0, [[SRC:v[0-9]+]] +; SIVI: v_sub_{{i|u}}32_e32 [[NEG:v[0-9]+]], vcc, 0, [[SRC:v[0-9]+]] +; GFX9: v_sub_u32_e32 [[NEG:v[0-9]+]], 0, [[SRC:v[0-9]+]] ; GCN: v_max_i32_e32 [[MAX:v[0-9]+]], [[SRC]], [[NEG]] ; GCN: v_mul_lo_i32 v{{[0-9]+}}, [[MAX]], [[MAX]] define amdgpu_kernel void @v_abs_i32_repeat_user(i32 addrspace(1)* %out, i32 addrspace(1)* %src) nounwind { @@ -68,14 +74,20 @@ define amdgpu_kernel void @s_abs_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> % } ; FUNC-LABEL: {{^}}v_abs_v2i32: -; GCN-DAG: v_sub_{{[iu]}}32_e32 [[NEG0:v[0-9]+]], vcc, 0, [[SRC0:v[0-9]+]] -; GCN-DAG: v_sub_{{[iu]}}32_e32 [[NEG1:v[0-9]+]], vcc, 0, [[SRC1:v[0-9]+]] +; SIVI-DAG: v_sub_{{i|u}}32_e32 [[NEG0:v[0-9]+]], vcc, 0, [[SRC0:v[0-9]+]] +; SIVI-DAG: v_sub_{{i|u}}32_e32 [[NEG1:v[0-9]+]], vcc, 0, [[SRC1:v[0-9]+]] + +; GFX9-DAG: v_sub_u32_e32 [[NEG0:v[0-9]+]], 0, [[SRC0:v[0-9]+]] +; GFX9-DAG: v_sub_u32_e32 [[NEG1:v[0-9]+]], 0, [[SRC1:v[0-9]+]] ; GCN-DAG: v_max_i32_e32 {{v[0-9]+}}, [[SRC0]], [[NEG0]] ; GCN-DAG: v_max_i32_e32 {{v[0-9]+}}, [[SRC1]], [[NEG1]] -; GCN: v_add_{{[iu]}}32 -; GCN: v_add_{{[iu]}}32 +; SIVI: v_add_{{i|u}}32_e32 v{{[0-9]+}}, vcc +; SIVI: v_add_{{i|u}}32_e32 v{{[0-9]+}}, vcc + +; GFX9: v_add_u32_e32 v{{[0-9]+}}, 2, +; GFX9: v_add_u32_e32 v{{[0-9]+}}, 2, ; EG: MAX_INT ; EG: MAX_INT @@ -127,20 +139,31 @@ define amdgpu_kernel void @s_abs_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> % } ; FUNC-LABEL: {{^}}v_abs_v4i32: -; GCN-DAG: v_sub_{{[iu]}}32_e32 [[NEG0:v[0-9]+]], vcc, 0, [[SRC0:v[0-9]+]] -; GCN-DAG: v_sub_{{[iu]}}32_e32 [[NEG1:v[0-9]+]], vcc, 0, [[SRC1:v[0-9]+]] -; GCN-DAG: v_sub_{{[iu]}}32_e32 [[NEG2:v[0-9]+]], vcc, 0, [[SRC2:v[0-9]+]] -; GCN-DAG: v_sub_{{[iu]}}32_e32 [[NEG3:v[0-9]+]], vcc, 0, [[SRC3:v[0-9]+]] + +; SIVI-DAG: v_sub_{{i|u}}32_e32 [[NEG0:v[0-9]+]], vcc, 0, [[SRC0:v[0-9]+]] +; SIVI-DAG: v_sub_{{i|u}}32_e32 [[NEG1:v[0-9]+]], vcc, 0, [[SRC1:v[0-9]+]] +; SIVI-DAG: v_sub_{{i|u}}32_e32 [[NEG2:v[0-9]+]], vcc, 0, [[SRC2:v[0-9]+]] +; SIVI-DAG: v_sub_{{i|u}}32_e32 [[NEG3:v[0-9]+]], vcc, 0, [[SRC3:v[0-9]+]] + +; GFX9-DAG: v_sub_u32_e32 [[NEG0:v[0-9]+]], 0, [[SRC0:v[0-9]+]] +; GFX9-DAG: v_sub_u32_e32 [[NEG1:v[0-9]+]], 0, [[SRC1:v[0-9]+]] +; GFX9-DAG: v_sub_u32_e32 [[NEG2:v[0-9]+]], 0, [[SRC2:v[0-9]+]] +; GFX9-DAG: v_sub_u32_e32 [[NEG3:v[0-9]+]], 0, [[SRC3:v[0-9]+]] ; GCN-DAG: v_max_i32_e32 {{v[0-9]+}}, [[SRC0]], [[NEG0]] ; GCN-DAG: v_max_i32_e32 {{v[0-9]+}}, [[SRC1]], [[NEG1]] ; GCN-DAG: v_max_i32_e32 {{v[0-9]+}}, [[SRC2]], [[NEG2]] ; GCN-DAG: v_max_i32_e32 {{v[0-9]+}}, [[SRC3]], [[NEG3]] -; GCN: v_add_{{[iu]}}32 -; GCN: v_add_{{[iu]}}32 -; GCN: v_add_{{[iu]}}32 -; GCN: v_add_{{[iu]}}32 +; SIVI: v_add_{{i|u}}32_e32 v{{[0-9]+}}, vcc, +; SIVI: v_add_{{i|u}}32_e32 v{{[0-9]+}}, vcc, +; SIVI: v_add_{{i|u}}32_e32 v{{[0-9]+}}, vcc, +; SIVI: v_add_{{i|u}}32_e32 v{{[0-9]+}}, vcc, + +; GFX9: v_add_u32_e32 v{{[0-9]+}}, 2, +; GFX9: v_add_u32_e32 v{{[0-9]+}}, 2, +; GFX9: v_add_u32_e32 v{{[0-9]+}}, 2, +; GFX9: v_add_u32_e32 v{{[0-9]+}}, 2, ; EG: MAX_INT ; EG: MAX_INT @@ -181,8 +204,8 @@ define amdgpu_kernel void @s_min_max_i32(i32 addrspace(1)* %out0, i32 addrspace( } ; FUNC-LABEL: {{^}}v_min_max_i32: -; GCN: {{buffer|flat}}_load_dword [[VAL0:v[0-9]+]] -; GCN: {{buffer|flat}}_load_dword [[VAL1:v[0-9]+]] +; GCN: {{buffer|flat|global}}_load_dword [[VAL0:v[0-9]+]] +; GCN: {{buffer|flat|global}}_load_dword [[VAL1:v[0-9]+]] ; GCN-DAG: v_min_i32_e32 v{{[0-9]+}}, [[VAL0]], [[VAL1]] ; GCN-DAG: v_max_i32_e32 v{{[0-9]+}}, [[VAL0]], [[VAL1]] diff --git a/test/CodeGen/AMDGPU/smrd.ll b/test/CodeGen/AMDGPU/smrd.ll index e6635d113ec10..9fd20fd67b8ce 100644 --- a/test/CodeGen/AMDGPU/smrd.ll +++ b/test/CodeGen/AMDGPU/smrd.ll @@ -193,8 +193,12 @@ main_body: } ; GCN-LABEL: {{^}}smrd_vgpr_offset_imm: -; GCN-NEXT: BB# -; GCN-NEXT: buffer_load_dword v{{[0-9]}}, v0, s[0:3], 0 offen offset:4095 ; +; GCN-NEXT: %bb. + +; SICIVI-NEXT: buffer_load_dword v{{[0-9]}}, v0, s[0:3], 0 offen offset:4095 ; + +; GFX9-NEXT: v_add_u32_e32 [[ADD:v[0-9]+]], 0xfff, v0 +; GFX9-NEXT: buffer_load_dword v{{[0-9]}}, [[ADD]], s[0:3], 0 offen ; define amdgpu_ps float @smrd_vgpr_offset_imm(<4 x i32> inreg %desc, i32 %offset) #0 { main_body: %off = add i32 %offset, 4095 @@ -203,8 +207,8 @@ main_body: } ; GCN-LABEL: {{^}}smrd_vgpr_offset_imm_too_large: -; GCN-NEXT: BB# -; GCN-NEXT: v_add{{(_co)?}}_{{i|u}}32_e32 v0, vcc, 0x1000, v0 +; GCN-NEXT: %bb. +; GCN-NEXT: v_add_{{i|u}}32_e32 v0, {{(vcc, )?}}0x1000, v0 ; GCN-NEXT: buffer_load_dword v{{[0-9]}}, v0, s[0:3], 0 offen ; define amdgpu_ps float @smrd_vgpr_offset_imm_too_large(<4 x i32> inreg %desc, i32 %offset) #0 { main_body: @@ -214,7 +218,7 @@ main_body: } ; GCN-LABEL: {{^}}smrd_imm_merged: -; GCN-NEXT: BB# +; GCN-NEXT: %bb. ; SICI-NEXT: s_buffer_load_dwordx4 s[{{[0-9]}}:{{[0-9]}}], s[0:3], 0x1 ; SICI-NEXT: s_buffer_load_dwordx2 s[{{[0-9]}}:{{[0-9]}}], s[0:3], 0x7 ; VI-NEXT: s_buffer_load_dwordx4 s[{{[0-9]}}:{{[0-9]}}], s[0:3], 0x4 @@ -239,9 +243,17 @@ main_body: } ; GCN-LABEL: {{^}}smrd_vgpr_merged: -; GCN-NEXT: BB# -; GCN-NEXT: buffer_load_dwordx4 v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:4 -; GCN-NEXT: buffer_load_dwordx2 v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:28 +; GCN-NEXT: %bb. + +; SICIVI-NEXT: buffer_load_dwordx4 v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:4 +; SICIVI-NEXT: buffer_load_dwordx2 v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:28 + +; GFX9: buffer_load_dword +; GFX9: buffer_load_dword +; GFX9: buffer_load_dword +; GFX9: buffer_load_dword +; GFX9: buffer_load_dword +; GFX9: buffer_load_dword define amdgpu_ps void @smrd_vgpr_merged(<4 x i32> inreg %desc, i32 %a) #0 { main_body: %a1 = add i32 %a, 4 diff --git a/test/CodeGen/AMDGPU/spill-empty-live-interval.mir b/test/CodeGen/AMDGPU/spill-empty-live-interval.mir index aceac34f286ac..1e9b6b5dd8d2d 100644 --- a/test/CodeGen/AMDGPU/spill-empty-live-interval.mir +++ b/test/CodeGen/AMDGPU/spill-empty-live-interval.mir @@ -2,7 +2,7 @@ # https://bugs.llvm.org/show_bug.cgi?id=33620 --- -# This would assert due to the empty live interval created for %vreg9 +# This would assert due to the empty live interval created for %9 # on the last S_NOP with an undef subreg use. # CHECK-LABEL: name: expecting_non_empty_interval diff --git a/test/CodeGen/AMDGPU/ssubo.ll b/test/CodeGen/AMDGPU/ssubo.ll index d4b22d6055031..fee14b48b44ad 100644 --- a/test/CodeGen/AMDGPU/ssubo.ll +++ b/test/CodeGen/AMDGPU/ssubo.ll @@ -1,5 +1,6 @@ -; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s -; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs< %s | FileCheck -check-prefixes=GCN,SI,FUNC %s +; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -verify-machineinstrs< %s | FileCheck -check-prefixes=GCN,VI,FUNC %s +; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -verify-machineinstrs< %s | FileCheck -check-prefixes=GCN,GFX9,FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=cypress -verify-machineinstrs< %s declare { i32, i1 } @llvm.ssub.with.overflow.i32(i32, i32) nounwind readnone @@ -39,8 +40,8 @@ define amdgpu_kernel void @v_ssubo_i32(i32 addrspace(1)* %out, i1 addrspace(1)* } ; FUNC-LABEL: {{^}}s_ssubo_i64: -; SI: s_sub_u32 -; SI: s_subb_u32 +; GCN: s_sub_u32 +; GCN: s_subb_u32 define amdgpu_kernel void @s_ssubo_i64(i64 addrspace(1)* %out, i1 addrspace(1)* %carryout, i64 %a, i64 %b) nounwind { %ssub = call { i64, i1 } @llvm.ssub.with.overflow.i64(i64 %a, i64 %b) nounwind %val = extractvalue { i64, i1 } %ssub, 0 @@ -51,8 +52,14 @@ define amdgpu_kernel void @s_ssubo_i64(i64 addrspace(1)* %out, i1 addrspace(1)* } ; FUNC-LABEL: {{^}}v_ssubo_i64: -; SI: v_sub_{{[iu]}}32_e32 -; SI: v_subb_u32_e32 +; SI: v_sub_i32_e32 v{{[0-9]+}}, vcc, +; SI: v_subb_u32_e32 v{{[0-9]+}}, vcc, + +; VI: v_sub_u32_e32 v{{[0-9]+}}, vcc, +; VI: v_subb_u32_e32 v{{[0-9]+}}, vcc, + +; GFX9: v_sub_co_u32_e32 v{{[0-9]+}}, vcc, +; GFX9: v_subb_co_u32_e32 v{{[0-9]+}}, vcc, define amdgpu_kernel void @v_ssubo_i64(i64 addrspace(1)* %out, i1 addrspace(1)* %carryout, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) nounwind { %a = load i64, i64 addrspace(1)* %aptr, align 4 %b = load i64, i64 addrspace(1)* %bptr, align 4 diff --git a/test/CodeGen/AMDGPU/sub.ll b/test/CodeGen/AMDGPU/sub.ll index 4c573acdbab5c..908d13eb01789 100644 --- a/test/CodeGen/AMDGPU/sub.ll +++ b/test/CodeGen/AMDGPU/sub.ll @@ -1,13 +1,34 @@ -; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s -; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=redwood -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s - +; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI,FUNC %s +; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI,GFX89,FUNC %s +; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9,GFX89,FUNC %s +; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=redwood -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=EG,FUNC %s declare i32 @llvm.r600.read.tidig.x() readnone +; FUNC-LABEL: {{^}}s_sub_i32: +; GCN: s_load_dword [[A:s[0-9]+]] +; GCN: s_load_dword [[B:s[0-9]+]] +; GCN: s_sub_i32 s{{[0-9]+}}, [[A]], [[B]] +define amdgpu_kernel void @s_sub_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) { + %result = sub i32 %a, %b + store i32 %result, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}s_sub_imm_i32: +; GCN: s_load_dword [[A:s[0-9]+]] +; GCN: s_sub_i32 s{{[0-9]+}}, 0x4d2, [[A]] +define amdgpu_kernel void @s_sub_imm_i32(i32 addrspace(1)* %out, i32 %a) { + %result = sub i32 1234, %a + store i32 %result, i32 addrspace(1)* %out + ret void +} + ; FUNC-LABEL: {{^}}test_sub_i32: ; EG: SUB_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ; SI: v_subrev_i32_e32 v{{[0-9]+, vcc, v[0-9]+, v[0-9]+}} +; GFX9: v_sub_u32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} define amdgpu_kernel void @test_sub_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { %b_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1 %a = load i32, i32 addrspace(1)* %in @@ -17,6 +38,17 @@ define amdgpu_kernel void @test_sub_i32(i32 addrspace(1)* %out, i32 addrspace(1) ret void } +; FUNC-LABEL: {{^}}test_sub_imm_i32: +; EG: SUB_INT + +; SI: v_sub_i32_e32 v{{[0-9]+}}, vcc, 0x7b, v{{[0-9]+}} +; GFX9: v_sub_u32_e32 v{{[0-9]+}}, 0x7b, v{{[0-9]+}} +define amdgpu_kernel void @test_sub_imm_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { + %a = load i32, i32 addrspace(1)* %in + %result = sub i32 123, %a + store i32 %result, i32 addrspace(1)* %out + ret void +} ; FUNC-LABEL: {{^}}test_sub_v2i32: ; EG: SUB_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} @@ -25,6 +57,8 @@ define amdgpu_kernel void @test_sub_i32(i32 addrspace(1)* %out, i32 addrspace(1) ; SI: v_sub_i32_e32 v{{[0-9]+, vcc, v[0-9]+, v[0-9]+}} ; SI: v_sub_i32_e32 v{{[0-9]+, vcc, v[0-9]+, v[0-9]+}} +; GFX9: v_sub_u32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +; GFX9: v_sub_u32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} define amdgpu_kernel void @test_sub_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) { %b_ptr = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %in, i32 1 %a = load <2 x i32>, <2 x i32> addrspace(1) * %in @@ -45,6 +79,10 @@ define amdgpu_kernel void @test_sub_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32 ; SI: v_sub_i32_e32 v{{[0-9]+, vcc, v[0-9]+, v[0-9]+}} ; SI: v_sub_i32_e32 v{{[0-9]+, vcc, v[0-9]+, v[0-9]+}} +; GFX9: v_sub_u32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +; GFX9: v_sub_u32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +; GFX9: v_sub_u32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +; GFX9: v_sub_u32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} define amdgpu_kernel void @test_sub_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { %b_ptr = getelementptr <4 x i32>, <4 x i32> addrspace(1)* %in, i32 1 %a = load <4 x i32>, <4 x i32> addrspace(1) * %in @@ -54,49 +92,58 @@ define amdgpu_kernel void @test_sub_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32 ret void } -; VI: v_sub_i16_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +; FUNC-LABEL: {{^}}test_sub_i16: +; SI: v_subrev_i32_e32 v{{[0-9]+}}, vcc, +; GFX89: v_sub_u16_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} define amdgpu_kernel void @test_sub_i16(i16 addrspace(1)* %out, i16 addrspace(1)* %in) { - %b_ptr = getelementptr i16, i16 addrspace(1)* %in, i16 1 - %a = load i16, i16 addrspace(1)* %in - %b = load i16, i16 addrspace(1)* %b_ptr - %result = sub i16 %a, %b - store i16 %result, i16 addrspace(1)* %out - ret void + %tid = call i32 @llvm.r600.read.tidig.x() + %gep = getelementptr i16, i16 addrspace(1)* %in, i32 %tid + %b_ptr = getelementptr i16, i16 addrspace(1)* %gep, i32 1 + %a = load volatile i16, i16 addrspace(1)* %gep + %b = load volatile i16, i16 addrspace(1)* %b_ptr + %result = sub i16 %a, %b + store i16 %result, i16 addrspace(1)* %out + ret void } ; FUNC-LABEL: {{^}}test_sub_v2i16: +; VI: v_sub_u16_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +; VI: v_sub_u16_sdwa v{{[0-9]+, v[0-9]+, v[0-9]+}} -; VI: v_sub_i16_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -; VI: v_sub_i16_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} - +; GFX9: v_pk_sub_i16 define amdgpu_kernel void @test_sub_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) { - %b_ptr = getelementptr <2 x i16>, <2 x i16> addrspace(1)* %in, i16 1 - %a = load <2 x i16>, <2 x i16> addrspace(1) * %in - %b = load <2 x i16>, <2 x i16> addrspace(1) * %b_ptr - %result = sub <2 x i16> %a, %b - store <2 x i16> %result, <2 x i16> addrspace(1)* %out - ret void + %tid = call i32 @llvm.r600.read.tidig.x() + %gep = getelementptr <2 x i16>, <2 x i16> addrspace(1)* %in, i32 %tid + %b_ptr = getelementptr <2 x i16>, <2 x i16> addrspace(1)* %gep, i16 1 + %a = load <2 x i16>, <2 x i16> addrspace(1)* %gep + %b = load <2 x i16>, <2 x i16> addrspace(1)* %b_ptr + %result = sub <2 x i16> %a, %b + store <2 x i16> %result, <2 x i16> addrspace(1)* %out + ret void } ; FUNC-LABEL: {{^}}test_sub_v4i16: +; VI: v_sub_u16_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +; VI: v_sub_u16_sdwa v{{[0-9]+, v[0-9]+, v[0-9]+}} +; VI: v_sub_u16_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +; VI: v_sub_u16_sdwa v{{[0-9]+, v[0-9]+, v[0-9]+}} -; VI: v_sub_i16_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -; VI: v_sub_i16_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -; VI: v_sub_i16_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -; VI: v_sub_i16_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} - +; GFX9: v_pk_sub_i16 +; GFX9: v_pk_sub_i16 define amdgpu_kernel void @test_sub_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> addrspace(1)* %in) { - %b_ptr = getelementptr <4 x i16>, <4 x i16> addrspace(1)* %in, i16 1 - %a = load <4 x i16>, <4 x i16> addrspace(1) * %in - %b = load <4 x i16>, <4 x i16> addrspace(1) * %b_ptr - %result = sub <4 x i16> %a, %b - store <4 x i16> %result, <4 x i16> addrspace(1)* %out - ret void + %tid = call i32 @llvm.r600.read.tidig.x() + %gep = getelementptr <4 x i16>, <4 x i16> addrspace(1)* %in, i32 %tid + %b_ptr = getelementptr <4 x i16>, <4 x i16> addrspace(1)* %gep, i16 1 + %a = load <4 x i16>, <4 x i16> addrspace(1) * %gep + %b = load <4 x i16>, <4 x i16> addrspace(1) * %b_ptr + %result = sub <4 x i16> %a, %b + store <4 x i16> %result, <4 x i16> addrspace(1)* %out + ret void } ; FUNC-LABEL: {{^}}s_sub_i64: -; SI: s_sub_u32 -; SI: s_subb_u32 +; GCN: s_sub_u32 +; GCN: s_subb_u32 ; EG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+}}.XY ; EG-DAG: SUB_INT {{[* ]*}} @@ -113,6 +160,12 @@ define amdgpu_kernel void @s_sub_i64(i64 addrspace(1)* noalias %out, i64 %a, i64 ; SI: v_sub_i32_e32 ; SI: v_subb_u32_e32 +; VI: v_sub_u32_e32 +; VI: v_subb_u32_e32 + +; GFX9: v_sub_co_u32_e32 +; GFX9: v_subb_co_u32_e32 + ; EG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+}}.XY ; EG-DAG: SUB_INT {{[* ]*}} ; EG-DAG: SUBB_UINT @@ -130,10 +183,20 @@ define amdgpu_kernel void @v_sub_i64(i64 addrspace(1)* noalias %out, i64 addrspa } ; FUNC-LABEL: {{^}}v_test_sub_v2i64: -; SI: v_sub_i32_e32 -; SI: v_subb_u32_e32 -; SI: v_sub_i32_e32 -; SI: v_subb_u32_e32 +; SI: v_sub_i32_e32 v{{[0-9]+}}, vcc, +; SI: v_subb_u32_e32 v{{[0-9]+}}, vcc, +; SI: v_sub_i32_e32 v{{[0-9]+}}, vcc, +; SI: v_subb_u32_e32 v{{[0-9]+}}, vcc, + +; VI: v_sub_u32_e32 v{{[0-9]+}}, vcc, +; VI: v_subb_u32_e32 v{{[0-9]+}}, vcc, +; VI: v_sub_u32_e32 v{{[0-9]+}}, vcc, +; VI: v_subb_u32_e32 v{{[0-9]+}}, vcc, + +; GFX9: v_sub_co_u32_e32 v{{[0-9]+}}, vcc, +; GFX9: v_subb_co_u32_e32 v{{[0-9]+}}, vcc, +; GFX9: v_sub_co_u32_e32 v{{[0-9]+}}, vcc, +; GFX9: v_subb_co_u32_e32 v{{[0-9]+}}, vcc, define amdgpu_kernel void @v_test_sub_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> addrspace(1)* noalias %inA, <2 x i64> addrspace(1)* noalias %inB) { %tid = call i32 @llvm.r600.read.tidig.x() readnone %a_ptr = getelementptr <2 x i64>, <2 x i64> addrspace(1)* %inA, i32 %tid @@ -146,14 +209,32 @@ define amdgpu_kernel void @v_test_sub_v2i64(<2 x i64> addrspace(1)* %out, <2 x i } ; FUNC-LABEL: {{^}}v_test_sub_v4i64: -; SI: v_sub_i32_e32 -; SI: v_subb_u32_e32 -; SI: v_sub_i32_e32 -; SI: v_subb_u32_e32 -; SI: v_sub_i32_e32 -; SI: v_subb_u32_e32 -; SI: v_sub_i32_e32 -; SI: v_subb_u32_e32 +; SI: v_sub_i32_e32 v{{[0-9]+}}, vcc, +; SI: v_subb_u32_e32 v{{[0-9]+}}, vcc, +; SI: v_sub_i32_e32 v{{[0-9]+}}, vcc, +; SI: v_subb_u32_e32 v{{[0-9]+}}, vcc, +; SI: v_sub_i32_e32 v{{[0-9]+}}, vcc, +; SI: v_subb_u32_e32 v{{[0-9]+}}, vcc, +; SI: v_sub_i32_e32 v{{[0-9]+}}, vcc, +; SI: v_subb_u32_e32 v{{[0-9]+}}, vcc, + +; VI: v_sub_u32_e32 v{{[0-9]+}}, vcc, +; VI: v_subb_u32_e32 v{{[0-9]+}}, vcc, +; VI: v_sub_u32_e32 v{{[0-9]+}}, vcc, +; VI: v_subb_u32_e32 v{{[0-9]+}}, vcc, +; VI: v_sub_u32_e32 v{{[0-9]+}}, vcc, +; VI: v_subb_u32_e32 v{{[0-9]+}}, vcc, +; VI: v_sub_u32_e32 v{{[0-9]+}}, vcc, +; VI: v_subb_u32_e32 v{{[0-9]+}}, vcc, + +; GFX9: v_sub_co_u32_e32 v{{[0-9]+}}, vcc, +; GFX9: v_subb_co_u32_e32 v{{[0-9]+}}, vcc, +; GFX9: v_sub_co_u32_e32 v{{[0-9]+}}, vcc, +; GFX9: v_subb_co_u32_e32 v{{[0-9]+}}, vcc, +; GFX9: v_sub_co_u32_e32 v{{[0-9]+}}, vcc, +; GFX9: v_subb_co_u32_e32 v{{[0-9]+}}, vcc, +; GFX9: v_sub_co_u32_e32 v{{[0-9]+}}, vcc, +; GFX9: v_subb_co_u32_e32 v{{[0-9]+}}, vcc, define amdgpu_kernel void @v_test_sub_v4i64(<4 x i64> addrspace(1)* %out, <4 x i64> addrspace(1)* noalias %inA, <4 x i64> addrspace(1)* noalias %inB) { %tid = call i32 @llvm.r600.read.tidig.x() readnone %a_ptr = getelementptr <4 x i64>, <4 x i64> addrspace(1)* %inA, i32 %tid diff --git a/test/CodeGen/AMDGPU/subreg-intervals.mir b/test/CodeGen/AMDGPU/subreg-intervals.mir index 62816da25b2c4..2d353b8138e3f 100644 --- a/test/CodeGen/AMDGPU/subreg-intervals.mir +++ b/test/CodeGen/AMDGPU/subreg-intervals.mir @@ -2,11 +2,11 @@ # REQUIRES: asserts # CHECK: INTERVALS -# CHECK: vreg0 +# CHECK: %0 # CHECK-LABEL: Machine code for function test0: # CHECK: INTERVALS -# CHECK: vreg0 +# CHECK: %0 # CHECK-LABEL: Machine code for function test1: --- | diff --git a/test/CodeGen/AMDGPU/uaddo.ll b/test/CodeGen/AMDGPU/uaddo.ll index 26b47dc75a881..0cb2487dd4ac6 100644 --- a/test/CodeGen/AMDGPU/uaddo.ll +++ b/test/CodeGen/AMDGPU/uaddo.ll @@ -1,6 +1,7 @@ -; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SI,FUNC %s -; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI,FUNC %s -; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefixes=EG,FUNC %s +; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SI,FUNC %s +; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI,FUNC %s +; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9,FUNC %s +; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefixes=EG,FUNC %s ; FUNC-LABEL: {{^}}s_uaddo_i64_zext: ; GCN: s_add_u32 @@ -22,7 +23,10 @@ define amdgpu_kernel void @s_uaddo_i64_zext(i64 addrspace(1)* %out, i64 %a, i64 ; FIXME: Could do scalar ; FUNC-LABEL: {{^}}s_uaddo_i32: -; GCN: v_add_{{[iu]}}32_e32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, v{{[0-9]+}} +; SI: v_add_i32_e32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, v{{[0-9]+}} +; VI: v_add_u32_e32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, v{{[0-9]+}} +; GFX9: v_add_co_u32_e32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, v{{[0-9]+}} + ; GCN: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1, vcc ; EG: ADDC_UINT @@ -37,7 +41,10 @@ define amdgpu_kernel void @s_uaddo_i32(i32 addrspace(1)* %out, i1 addrspace(1)* } ; FUNC-LABEL: {{^}}v_uaddo_i32: -; GCN: v_add_{{[iu]}}32_e32 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}} +; SI: v_add_i32_e32 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}} +; VI: v_add_u32_e32 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}} +; GFX9: v_add_co_u32_e32 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}} + ; GCN: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1, vcc ; EG: ADDC_UINT @@ -58,7 +65,10 @@ define amdgpu_kernel void @v_uaddo_i32(i32 addrspace(1)* %out, i1 addrspace(1)* } ; FUNC-LABEL: {{^}}v_uaddo_i32_novcc: -; GCN: v_add_{{[iu]}}32_e32 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}} +; SI: v_add_i32_e32 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}} +; VI: v_add_u32_e32 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}} +; GFX9: v_add_co_u32_e32 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}} + ; GCN: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1, vcc ; EG: ADDC_UINT @@ -95,8 +105,14 @@ define amdgpu_kernel void @s_uaddo_i64(i64 addrspace(1)* %out, i1 addrspace(1)* } ; FUNC-LABEL: {{^}}v_uaddo_i64: -; GCN: v_add_{{[iu]}}32 -; GCN: v_addc_u32 +; SI: v_add_i32_e32 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}} +; SI: v_addc_u32_e32 v{{[0-9]+}}, vcc, + +; VI: v_add_u32_e32 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}} +; VI: v_addc_u32_e32 v{{[0-9]+}}, vcc, + +; GFX9: v_add_co_u32_e32 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}} +; GFX9: v_addc_co_u32_e32 v{{[0-9]+}}, vcc, ; EG: ADDC_UINT ; EG: ADD_INT @@ -118,6 +134,9 @@ define amdgpu_kernel void @v_uaddo_i64(i64 addrspace(1)* %out, i1 addrspace(1)* ; FUNC-LABEL: {{^}}v_uaddo_i16: ; VI: v_add_u16_e32 ; VI: v_cmp_lt_u16_e32 + +; GFX9: v_add_u16_e32 +; GFX9: v_cmp_lt_u16_e32 define amdgpu_kernel void @v_uaddo_i16(i16 addrspace(1)* %out, i1 addrspace(1)* %carryout, i16 addrspace(1)* %a.ptr, i16 addrspace(1)* %b.ptr) #0 { %tid = call i32 @llvm.amdgcn.workitem.id.x() %tid.ext = sext i32 %tid to i64 diff --git a/test/CodeGen/AMDGPU/udivrem64.ll b/test/CodeGen/AMDGPU/udivrem64.ll index 91c27b09b5fa5..408fd01c29222 100644 --- a/test/CodeGen/AMDGPU/udivrem64.ll +++ b/test/CodeGen/AMDGPU/udivrem64.ll @@ -1,5 +1,6 @@ ;RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck --check-prefix=SI --check-prefix=GCN --check-prefix=FUNC %s ;RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck --check-prefix=VI --check-prefix=GCN --check-prefix=FUNC %s +;RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck --check-prefix=VI --check-prefix=GCN --check-prefix=FUNC %s ;RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck --check-prefix=EG --check-prefix=FUNC %s ;FUNC-LABEL: {{^}}test_udiv: diff --git a/test/CodeGen/AMDGPU/uniform-PHI.ll b/test/CodeGen/AMDGPU/uniform-PHI.ll new file mode 100644 index 0000000000000..3cb86b39a65f2 --- /dev/null +++ b/test/CodeGen/AMDGPU/uniform-PHI.ll @@ -0,0 +1,39 @@ +; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s + +; GCN-LABEL: BB0_2 +; GCN-NOT: v_readfirstlane + + +target triple = "amdgcn--amdhsa" +define amdgpu_kernel void @uniform-PHI(i32 addrspace(1)* nocapture readonly %arg, i32 addrspace(1)* nocapture %arg1, i32 %arg2) { +bb: + %tmp = sext i32 %arg2 to i64 + %tmp3 = tail call i64 @_Z13get_global_idj(i32 0) #2 + %tmp4 = icmp ugt i64 %tmp3, %tmp + %tmp5 = icmp sgt i32 %arg2, 0 + %tmp6 = and i1 %tmp4, %tmp5 + br i1 %tmp6, label %bb7, label %bb17 + +bb7: ; preds = %bb + br label %bb8 + +bb8: ; preds = %bb8, %bb7 + %tmp9 = phi i32 [ %tmp15, %bb8 ], [ 0, %bb7 ] + %tmp10 = phi i32 [ %tmp14, %bb8 ], [ 0, %bb7 ] + %tmp11 = zext i32 %tmp9 to i64 + %tmp12 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 %tmp11 + %tmp13 = load i32, i32 addrspace(1)* %tmp12, align 4 + %tmp14 = add nsw i32 %tmp13, %tmp10 + %tmp15 = add nuw nsw i32 %tmp9, 1 + %tmp16 = icmp eq i32 %tmp15, %arg2 + br i1 %tmp16, label %bb17, label %bb8 + +bb17: ; preds = %bb8, %bb + %tmp18 = phi i32 [ 0, %bb ], [ %tmp14, %bb8 ] + store i32 %tmp18, i32 addrspace(1)* %arg1, align 4 + ret void +} + +declare i64 @_Z13get_global_idj(i32) local_unnamed_addr #1 +attributes #1 = { convergent nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="fiji" "target-features"="+16-bit-insts,+dpp,+fp64-fp16-denormals,+s-memrealtime,-fp32-denormals" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #2 = { convergent nounwind readnone } diff --git a/test/CodeGen/AMDGPU/uniform-cfg.ll b/test/CodeGen/AMDGPU/uniform-cfg.ll index 247b9691aff57..a247d7a343fbc 100644 --- a/test/CodeGen/AMDGPU/uniform-cfg.ll +++ b/test/CodeGen/AMDGPU/uniform-cfg.ll @@ -401,7 +401,7 @@ exit: ; GCN: s_cmp_lt_i32 [[COND]], 1 ; GCN: s_cbranch_scc1 BB[[FNNUM:[0-9]+]]_3 -; GCN: BB#1: +; GCN: %bb.1: ; GCN-NOT: cmp ; GCN: buffer_load_dword ; GCN: buffer_store_dword diff --git a/test/CodeGen/AMDGPU/uniform-loop-inside-nonuniform.ll b/test/CodeGen/AMDGPU/uniform-loop-inside-nonuniform.ll index 82283f39792ee..1bbda66fddb16 100644 --- a/test/CodeGen/AMDGPU/uniform-loop-inside-nonuniform.ll +++ b/test/CodeGen/AMDGPU/uniform-loop-inside-nonuniform.ll @@ -6,11 +6,10 @@ ; CHECK: v_cmp_ne_u32_e32 vcc, 0 ; CHECK: s_and_saveexec_b64 ; CHECK-NEXT: ; mask branch -; CHECK-NEXT: s_cbranch_execz BB{{[0-9]+_[0-9]+}} ; CHECK-NEXT: BB{{[0-9]+_[0-9]+}}: ; %loop_body.preheader ; CHECK: [[LOOP_BODY_LABEL:BB[0-9]+_[0-9]+]]: -; CHECK: s_cbranch_vccz [[LOOP_BODY_LABEL]] +; CHECK: s_cbranch_scc0 [[LOOP_BODY_LABEL]] ; CHECK: s_endpgm define amdgpu_ps void @test1(<8 x i32> inreg %rsrc, <2 x i32> %addr.base, i32 %y, i32 %p) { @@ -35,7 +34,6 @@ out: ; CHECK-LABEL: {{^}}test2: ; CHECK: s_and_saveexec_b64 ; CHECK-NEXT: ; mask branch -; CHECK-NEXT: s_cbranch_execz define amdgpu_kernel void @test2(i32 addrspace(1)* %out, i32 %a, i32 %b) { main_body: %tid = call i32 @llvm.amdgcn.workitem.id.x() #1 diff --git a/test/CodeGen/AMDGPU/usubo.ll b/test/CodeGen/AMDGPU/usubo.ll index 10c0d8640f5d1..eeb19f86f3849 100644 --- a/test/CodeGen/AMDGPU/usubo.ll +++ b/test/CodeGen/AMDGPU/usubo.ll @@ -1,6 +1,7 @@ -; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SI,FUNC %s -; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI,FUNC %s -; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefixes=EG,FUNC %s +; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SI,SICIVI,FUNC %s +; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI,SICIVI,FUNC %s +; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9,FUNC %s +; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefixes=EG,FUNC %s ; FUNC-LABEL: {{^}}s_usubo_i64_zext: ; GCN: s_sub_u32 @@ -22,7 +23,10 @@ define amdgpu_kernel void @s_usubo_i64_zext(i64 addrspace(1)* %out, i64 %a, i64 ; FIXME: Could do scalar ; FUNC-LABEL: {{^}}s_usubo_i32: -; GCN: v_sub_{{[iu]}}32_e32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, v{{[0-9]+}} +; SI: v_sub_i32_e32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, v{{[0-9]+}} +; VI: v_sub_u32_e32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, v{{[0-9]+}} +; GFX9: v_sub_co_u32_e32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, v{{[0-9]+}} + ; GCN: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1, vcc ; EG-DAG: SUBB_UINT @@ -37,7 +41,10 @@ define amdgpu_kernel void @s_usubo_i32(i32 addrspace(1)* %out, i1 addrspace(1)* } ; FUNC-LABEL: {{^}}v_usubo_i32: -; GCN: v_sub_{{[iu]}}32_e32 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}} +; SI: v_sub_i32_e32 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}} +; VI: v_sub_u32_e32 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}} +; GFX9: v_sub_co_u32_e32 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}} + ; GCN: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1, vcc ; EG-DAG: SUBB_UINT @@ -58,7 +65,10 @@ define amdgpu_kernel void @v_usubo_i32(i32 addrspace(1)* %out, i1 addrspace(1)* } ; FUNC-LABEL: {{^}}v_usubo_i32_novcc: -; GCN: v_sub_{{[iu]}}32_e32 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}} +; SI: v_sub_i32_e32 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}} +; VI: v_sub_u32_e32 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}} +; GFX9: v_sub_co_u32_e32 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}} + ; GCN: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1, vcc ; EG-DAG: SUBB_UINT @@ -97,8 +107,13 @@ define amdgpu_kernel void @s_usubo_i64(i64 addrspace(1)* %out, i1 addrspace(1)* } ; FUNC-LABEL: {{^}}v_usubo_i64: -; GCN: v_sub_{{[iu]}}32 -; GCN: v_subb_u32 +; SI: v_sub_i32_e32 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}} +; SI: v_subb_u32 +; VI: v_sub_u32_e32 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}} +; VI: v_subb_u32 + +; GFX9: v_sub_co_u32_e32 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}} +; GFX9: v_subb_co_u32 ; EG-DAG: SUBB_UINT ; EG-DAG: SUB_INT @@ -120,8 +135,15 @@ define amdgpu_kernel void @v_usubo_i64(i64 addrspace(1)* %out, i1 addrspace(1)* } ; FUNC-LABEL: {{^}}v_usubo_i16: +; SI: v_subrev_i32_e32 +; SI: v_and_b32 +; SI: v_cmp_ne_u32_e32 + ; VI: v_sub_u16_e32 ; VI: v_cmp_gt_u16_e32 + +; GFX9: v_sub_u16_e32 +; GFX9: v_cmp_gt_u16_e32 define amdgpu_kernel void @v_usubo_i16(i16 addrspace(1)* %out, i1 addrspace(1)* %carryout, i16 addrspace(1)* %a.ptr, i16 addrspace(1)* %b.ptr) #0 { %tid = call i32 @llvm.amdgcn.workitem.id.x() %tid.ext = sext i32 %tid to i64 diff --git a/test/CodeGen/AMDGPU/valu-i1.ll b/test/CodeGen/AMDGPU/valu-i1.ll index 7162e818d49ff..4a3937e44f36f 100644 --- a/test/CodeGen/AMDGPU/valu-i1.ll +++ b/test/CodeGen/AMDGPU/valu-i1.ll @@ -162,8 +162,8 @@ exit: ; SI: [[LABEL_LOOP:BB[0-9]+_[0-9]+]]: ; SI: buffer_load_dword ; SI-DAG: buffer_store_dword -; SI-DAG: v_cmp_eq_u32_e32 vcc, 0x100 -; SI: s_cbranch_vccz [[LABEL_LOOP]] +; SI-DAG: s_cmpk_eq_i32 s{{[0-9]+}}, 0x100 +; SI: s_cbranch_scc0 [[LABEL_LOOP]] ; SI: [[LABEL_EXIT]]: ; SI: s_endpgm @@ -192,7 +192,7 @@ exit: ; Load loop limit from buffer ; Branch to exit if uniformly not taken -; SI: ; BB#0: +; SI: ; %bb.0: ; SI: buffer_load_dword [[VBOUND:v[0-9]+]] ; SI: v_cmp_lt_i32_e32 vcc ; SI: s_and_saveexec_b64 [[OUTER_CMP_SREG:s\[[0-9]+:[0-9]+\]]], vcc diff --git a/test/CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir b/test/CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir index 54991d3d953cd..ff9826baf48c4 100644 --- a/test/CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir +++ b/test/CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir @@ -48,7 +48,7 @@ # CHECK-LABEL: name: vccz_corrupt_workaround # CHECK: %vcc = V_CMP_EQ_F32 # CHECK-NEXT: %vcc = S_MOV_B64 %vcc -# CHECK-NEXT: S_CBRANCH_VCCZ %bb.2.else, implicit killed %vcc +# CHECK-NEXT: S_CBRANCH_VCCZ %bb.2, implicit killed %vcc name: vccz_corrupt_workaround alignment: 0 @@ -82,7 +82,7 @@ body: | %sgpr7 = S_MOV_B32 61440 %sgpr6 = S_MOV_B32 -1 %vcc = V_CMP_EQ_F32_e64 0, 0, 0, %sgpr2, 0, implicit %exec - S_CBRANCH_VCCZ %bb.1.else, implicit killed %vcc + S_CBRANCH_VCCZ %bb.1, implicit killed %vcc bb.2.if: liveins: %sgpr6, %sgpr7, %sgpr0_sgpr1_sgpr2_sgpr3:0x00000003 @@ -90,7 +90,7 @@ body: | %vgpr0 = V_MOV_B32_e32 9, implicit %exec BUFFER_STORE_DWORD_OFFSET killed %vgpr0, killed %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec :: (volatile store 4 into `i32 addrspace(1)* undef`) %vgpr0 = V_MOV_B32_e32 0, implicit %exec - S_BRANCH %bb.3.done + S_BRANCH %bb.3 bb.1.else: liveins: %sgpr6, %sgpr7, %sgpr0_sgpr1_sgpr2_sgpr3:0x00000003 @@ -111,7 +111,7 @@ body: | --- # CHECK-LABEL: name: vccz_corrupt_undef_vcc # CHECK: S_WAITCNT -# CHECK-NEXT: S_CBRANCH_VCCZ %bb.2.else, implicit undef %vcc +# CHECK-NEXT: S_CBRANCH_VCCZ %bb.2, implicit undef %vcc name: vccz_corrupt_undef_vcc alignment: 0 @@ -143,7 +143,7 @@ body: | %sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed %sgpr0_sgpr1, 11, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`) %sgpr7 = S_MOV_B32 61440 %sgpr6 = S_MOV_B32 -1 - S_CBRANCH_VCCZ %bb.1.else, implicit undef %vcc + S_CBRANCH_VCCZ %bb.1, implicit undef %vcc bb.2.if: liveins: %sgpr6, %sgpr7, %sgpr0_sgpr1_sgpr2_sgpr3:0x00000003 @@ -151,7 +151,7 @@ body: | %vgpr0 = V_MOV_B32_e32 9, implicit %exec BUFFER_STORE_DWORD_OFFSET killed %vgpr0, killed %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec :: (volatile store 4 into `i32 addrspace(1)* undef`) %vgpr0 = V_MOV_B32_e32 0, implicit %exec - S_BRANCH %bb.3.done + S_BRANCH %bb.3 bb.1.else: liveins: %sgpr6, %sgpr7, %sgpr0_sgpr1_sgpr2_sgpr3:0x00000003 diff --git a/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot-compute.ll b/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot-compute.ll index feae5e9f37920..a0242ec958b3f 100644 --- a/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot-compute.ll +++ b/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot-compute.ll @@ -1,8 +1,8 @@ -; RUN: llc -march=amdgcn -mcpu=tahiti -mattr=+vgpr-spilling -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCNMESA -check-prefix=SIMESA %s -; RUN: llc -march=amdgcn -mcpu=fiji -mattr=+vgpr-spilling,-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCNMESA -check-prefix=VIMESA %s -; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=+vgpr-spilling,-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCNMESA -check-prefix=GFX9MESA %s -; RUN: llc -march=amdgcn -mcpu=hawaii -mtriple=amdgcn-unknown-amdhsa -mattr=+vgpr-spilling -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=CIHSA -check-prefix=HSA %s -; RUN: llc -march=amdgcn -mcpu=fiji -mtriple=amdgcn-unknown-amdhsa -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VIHSA -check-prefix=HSA %s +; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -mattr=+vgpr-spilling -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCNMESA -check-prefix=SIMESA %s +; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -mattr=+vgpr-spilling,-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCNMESA -check-prefix=VIMESA %s +; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx900 -mattr=+vgpr-spilling,-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCNMESA -check-prefix=GFX9MESA %s +; RUN: llc -march=amdgcn -mcpu=hawaii -mtriple=amdgcn-unknown-amdhsa-amdgiz -mattr=+vgpr-spilling -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=CIHSA -check-prefix=HSA %s +; RUN: llc -march=amdgcn -mcpu=fiji -mtriple=amdgcn-unknown-amdhsa-amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VIHSA -check-prefix=HSA %s ; This ends up using all 256 registers and requires register ; scavenging which will fail to find an unsued register. diff --git a/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot.ll b/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot.ll index afbd06a00faed..89327fb8f80de 100644 --- a/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot.ll +++ b/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=amdgcn -mcpu=tahiti -mattr=+vgpr-spilling -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s -; RUN: llc -march=amdgcn -mcpu=fiji -mattr=+vgpr-spilling -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s -; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=+vgpr-spilling -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s +; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tahiti -mattr=+vgpr-spilling -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s +; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -mattr=+vgpr-spilling -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s +; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx900 -mattr=+vgpr-spilling -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s ; This ends up using all 255 registers and requires register ; scavenging which will fail to find an unsued register. diff --git a/test/CodeGen/ARM/2011-11-14-EarlyClobber.ll b/test/CodeGen/ARM/2011-11-14-EarlyClobber.ll index 7f4057143a07d..5e71eeb9c3d11 100644 --- a/test/CodeGen/ARM/2011-11-14-EarlyClobber.ll +++ b/test/CodeGen/ARM/2011-11-14-EarlyClobber.ll @@ -5,11 +5,11 @@ target triple = "thumbv7-apple-ios" ; This test calls shrinkToUses with an early-clobber redefined live range during ; spilling. ; -; Shrink: %vreg47,1.158257e-02 = [384r,400e:0)[400e,420r:1) 0@384r 1@400e +; Shrink: %47,1.158257e-02 = [384r,400e:0)[400e,420r:1) 0@384r 1@400e ; ; The early-clobber instruction is an str: ; -; %vreg12 = t2STR_PRE %vreg6, %vreg12, 32, pred:14, pred:%noreg +; %12 = t2STR_PRE %6, %12, 32, pred:14, pred:%noreg ; ; This tests that shrinkToUses handles the EC redef correctly. diff --git a/test/CodeGen/ARM/ARMLoadStoreDBG.mir b/test/CodeGen/ARM/ARMLoadStoreDBG.mir index 1ff3bffd38772..86d09ce7b0977 100644 --- a/test/CodeGen/ARM/ARMLoadStoreDBG.mir +++ b/test/CodeGen/ARM/ARMLoadStoreDBG.mir @@ -120,40 +120,40 @@ body: | bb.0.entry: liveins: %r0, %r1, %r2, %r3, %lr, %r7 - DBG_VALUE debug-use %r0, debug-use _, !18, !27, debug-location !28 - DBG_VALUE debug-use %r1, debug-use _, !19, !27, debug-location !28 - DBG_VALUE debug-use %r2, debug-use _, !20, !27, debug-location !28 - DBG_VALUE debug-use %r3, debug-use _, !21, !27, debug-location !28 - t2CMPri %r3, 4, 14, _, implicit-def %cpsr, debug-location !31 + DBG_VALUE debug-use %r0, debug-use %noreg, !18, !27, debug-location !28 + DBG_VALUE debug-use %r1, debug-use %noreg, !19, !27, debug-location !28 + DBG_VALUE debug-use %r2, debug-use %noreg, !20, !27, debug-location !28 + DBG_VALUE debug-use %r3, debug-use %noreg, !21, !27, debug-location !28 + t2CMPri %r3, 4, 14, %noreg, implicit-def %cpsr, debug-location !31 t2Bcc %bb.2.if.end, 2, killed %cpsr bb.1: liveins: %lr, %r7 - DBG_VALUE debug-use %r1, debug-use _, !19, !27, debug-location !28 - %r0 = t2MOVi -1, 14, _, _ - DBG_VALUE debug-use %r1, debug-use _, !19, !27, debug-location !28 - tBX_RET 14, _, implicit %r0, debug-location !34 + DBG_VALUE debug-use %r1, debug-use %noreg, !19, !27, debug-location !28 + %r0 = t2MOVi -1, 14, %noreg, %noreg + DBG_VALUE debug-use %r1, debug-use %noreg, !19, !27, debug-location !28 + tBX_RET 14, %noreg, implicit %r0, debug-location !34 bb.2.if.end: liveins: %r0, %r2, %r3, %r7, %lr - %sp = frame-setup t2STMDB_UPD %sp, 14, _, killed %r7, killed %lr + %sp = frame-setup t2STMDB_UPD %sp, 14, %noreg, killed %r7, killed %lr frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION offset %lr, -4 frame-setup CFI_INSTRUCTION offset %r7, -8 - DBG_VALUE debug-use %r0, debug-use _, !18, !27, debug-location !28 - DBG_VALUE debug-use %r1, debug-use _, !19, !27, debug-location !28 - DBG_VALUE debug-use %r2, debug-use _, !20, !27, debug-location !28 - DBG_VALUE debug-use %r3, debug-use _, !21, !27, debug-location !28 + DBG_VALUE debug-use %r0, debug-use %noreg, !18, !27, debug-location !28 + DBG_VALUE debug-use %r1, debug-use %noreg, !19, !27, debug-location !28 + DBG_VALUE debug-use %r2, debug-use %noreg, !20, !27, debug-location !28 + DBG_VALUE debug-use %r3, debug-use %noreg, !21, !27, debug-location !28 %r1 = COPY killed %r2, debug-location !32 - DBG_VALUE debug-use %r1, debug-use _, !19, !27, debug-location !28 + DBG_VALUE debug-use %r1, debug-use %noreg, !19, !27, debug-location !28 %r2 = COPY killed %r3, debug-location !32 - tBL 14, _, @g, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit-def %sp, debug-location !32 - %r0 = t2MOVi 0, 14, _, _ - %sp = t2LDMIA_UPD %sp, 14, _, def %r7, def %lr - tBX_RET 14, _, implicit %r0, debug-location !34 + tBL 14, %noreg, @g, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit-def %sp, debug-location !32 + %r0 = t2MOVi 0, 14, %noreg, %noreg + %sp = t2LDMIA_UPD %sp, 14, %noreg, def %r7, def %lr + tBX_RET 14, %noreg, implicit %r0, debug-location !34 # Verify that the DBG_VALUE is ignored. -# CHECK: %sp = t2LDMIA_RET %sp, 14, _, def %r7, def %pc, implicit %r0 +# CHECK: %sp = t2LDMIA_RET %sp, 14, %noreg, def %r7, def %pc, implicit %r0 ... diff --git a/test/CodeGen/ARM/GlobalISel/arm-call-lowering.ll b/test/CodeGen/ARM/GlobalISel/arm-call-lowering.ll index c1dd9276ddd84..ec6ea632591e1 100644 --- a/test/CodeGen/ARM/GlobalISel/arm-call-lowering.ll +++ b/test/CodeGen/ARM/GlobalISel/arm-call-lowering.ll @@ -7,11 +7,11 @@ define arm_aapcscc void @test_indirect_call(void() *%fptr) { ; V5T: %[[FPTR:[0-9]+]]:gpr(p0) = COPY %r0 ; V4T: %[[FPTR:[0-9]+]]:tgpr(p0) = COPY %r0 ; NOV4T: %[[FPTR:[0-9]+]]:tgpr(p0) = COPY %r0 -; CHECK: ADJCALLSTACKDOWN 0, 0, 14, _, implicit-def %sp, implicit %sp +; CHECK: ADJCALLSTACKDOWN 0, 0, 14, %noreg, implicit-def %sp, implicit %sp ; V5T: BLX %[[FPTR]](p0), csr_aapcs, implicit-def %lr, implicit %sp ; V4T: BX_CALL %[[FPTR]](p0), csr_aapcs, implicit-def %lr, implicit %sp ; NOV4T: BMOVPCRX_CALL %[[FPTR]](p0), csr_aapcs, implicit-def %lr, implicit %sp -; CHECK: ADJCALLSTACKUP 0, 0, 14, _, implicit-def %sp, implicit %sp +; CHECK: ADJCALLSTACKUP 0, 0, 14, %noreg, implicit-def %sp, implicit %sp entry: notail call arm_aapcscc void %fptr() ret void @@ -21,9 +21,9 @@ declare arm_aapcscc void @call_target() define arm_aapcscc void @test_direct_call() { ; CHECK-LABEL: name: test_direct_call -; CHECK: ADJCALLSTACKDOWN 0, 0, 14, _, implicit-def %sp, implicit %sp +; CHECK: ADJCALLSTACKDOWN 0, 0, 14, %noreg, implicit-def %sp, implicit %sp ; CHECK: BL @call_target, csr_aapcs, implicit-def %lr, implicit %sp -; CHECK: ADJCALLSTACKUP 0, 0, 14, _, implicit-def %sp, implicit %sp +; CHECK: ADJCALLSTACKUP 0, 0, 14, %noreg, implicit-def %sp, implicit %sp entry: notail call arm_aapcscc void @call_target() ret void diff --git a/test/CodeGen/ARM/GlobalISel/arm-instruction-select-cmp.mir b/test/CodeGen/ARM/GlobalISel/arm-instruction-select-cmp.mir index e2b6f878e6bf2..c8ed142903bbc 100644 --- a/test/CodeGen/ARM/GlobalISel/arm-instruction-select-cmp.mir +++ b/test/CodeGen/ARM/GlobalISel/arm-instruction-select-cmp.mir @@ -69,18 +69,18 @@ body: | ; CHECK-LABEL: name: test_icmp_eq_s32 ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY %r0 ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY %r1 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _ - ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, _, implicit-def %cpsr + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg + ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, %noreg, implicit-def %cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 0, %cpsr - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _ + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg ; CHECK: %r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, _, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 %0(s32) = COPY %r0 %1(s32) = COPY %r1 %2(s1) = G_ICMP intpred(eq), %0(s32), %1 %3(s32) = G_ZEXT %2(s1) %r0 = COPY %3(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_icmp_ne_s32 @@ -99,18 +99,18 @@ body: | ; CHECK-LABEL: name: test_icmp_ne_s32 ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY %r0 ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY %r1 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _ - ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, _, implicit-def %cpsr + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg + ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, %noreg, implicit-def %cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 1, %cpsr - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _ + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg ; CHECK: %r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, _, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 %0(s32) = COPY %r0 %1(s32) = COPY %r1 %2(s1) = G_ICMP intpred(ne), %0(s32), %1 %3(s32) = G_ZEXT %2(s1) %r0 = COPY %3(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_icmp_ugt_s32 @@ -129,18 +129,18 @@ body: | ; CHECK-LABEL: name: test_icmp_ugt_s32 ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY %r0 ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY %r1 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _ - ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, _, implicit-def %cpsr + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg + ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, %noreg, implicit-def %cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 8, %cpsr - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _ + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg ; CHECK: %r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, _, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 %0(s32) = COPY %r0 %1(s32) = COPY %r1 %2(s1) = G_ICMP intpred(ugt), %0(s32), %1 %3(s32) = G_ZEXT %2(s1) %r0 = COPY %3(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_icmp_uge_s32 @@ -159,18 +159,18 @@ body: | ; CHECK-LABEL: name: test_icmp_uge_s32 ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY %r0 ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY %r1 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _ - ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, _, implicit-def %cpsr + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg + ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, %noreg, implicit-def %cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 2, %cpsr - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _ + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg ; CHECK: %r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, _, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 %0(s32) = COPY %r0 %1(s32) = COPY %r1 %2(s1) = G_ICMP intpred(uge), %0(s32), %1 %3(s32) = G_ZEXT %2(s1) %r0 = COPY %3(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_icmp_ult_s32 @@ -189,18 +189,18 @@ body: | ; CHECK-LABEL: name: test_icmp_ult_s32 ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY %r0 ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY %r1 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _ - ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, _, implicit-def %cpsr + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg + ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, %noreg, implicit-def %cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 3, %cpsr - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _ + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg ; CHECK: %r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, _, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 %0(s32) = COPY %r0 %1(s32) = COPY %r1 %2(s1) = G_ICMP intpred(ult), %0(s32), %1 %3(s32) = G_ZEXT %2(s1) %r0 = COPY %3(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_icmp_ule_s32 @@ -219,18 +219,18 @@ body: | ; CHECK-LABEL: name: test_icmp_ule_s32 ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY %r0 ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY %r1 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _ - ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, _, implicit-def %cpsr + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg + ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, %noreg, implicit-def %cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 9, %cpsr - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _ + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg ; CHECK: %r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, _, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 %0(s32) = COPY %r0 %1(s32) = COPY %r1 %2(s1) = G_ICMP intpred(ule), %0(s32), %1 %3(s32) = G_ZEXT %2(s1) %r0 = COPY %3(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_icmp_sgt_s32 @@ -249,18 +249,18 @@ body: | ; CHECK-LABEL: name: test_icmp_sgt_s32 ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY %r0 ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY %r1 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _ - ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, _, implicit-def %cpsr + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg + ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, %noreg, implicit-def %cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 12, %cpsr - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _ + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg ; CHECK: %r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, _, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 %0(s32) = COPY %r0 %1(s32) = COPY %r1 %2(s1) = G_ICMP intpred(sgt), %0(s32), %1 %3(s32) = G_ZEXT %2(s1) %r0 = COPY %3(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_icmp_sge_s32 @@ -279,18 +279,18 @@ body: | ; CHECK-LABEL: name: test_icmp_sge_s32 ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY %r0 ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY %r1 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _ - ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, _, implicit-def %cpsr + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg + ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, %noreg, implicit-def %cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 10, %cpsr - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _ + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg ; CHECK: %r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, _, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 %0(s32) = COPY %r0 %1(s32) = COPY %r1 %2(s1) = G_ICMP intpred(sge), %0(s32), %1 %3(s32) = G_ZEXT %2(s1) %r0 = COPY %3(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_icmp_slt_s32 @@ -309,18 +309,18 @@ body: | ; CHECK-LABEL: name: test_icmp_slt_s32 ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY %r0 ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY %r1 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _ - ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, _, implicit-def %cpsr + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg + ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, %noreg, implicit-def %cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 11, %cpsr - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _ + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg ; CHECK: %r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, _, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 %0(s32) = COPY %r0 %1(s32) = COPY %r1 %2(s1) = G_ICMP intpred(slt), %0(s32), %1 %3(s32) = G_ZEXT %2(s1) %r0 = COPY %3(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_icmp_sle_s32 @@ -339,18 +339,18 @@ body: | ; CHECK-LABEL: name: test_icmp_sle_s32 ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY %r0 ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY %r1 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _ - ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, _, implicit-def %cpsr + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg + ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, %noreg, implicit-def %cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 13, %cpsr - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _ + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg ; CHECK: %r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, _, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 %0(s32) = COPY %r0 %1(s32) = COPY %r1 %2(s1) = G_ICMP intpred(sle), %0(s32), %1 %3(s32) = G_ZEXT %2(s1) %r0 = COPY %3(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_fcmp_true_s32 @@ -367,16 +367,16 @@ body: | liveins: %s0, %s1 ; CHECK-LABEL: name: test_fcmp_true_s32 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 1, 14, _, _ - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVi]], 1, 14, _, _ + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 1, 14, %noreg, %noreg + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVi]], 1, 14, %noreg, %noreg ; CHECK: %r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, _, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 %0(s32) = COPY %s0 %1(s32) = COPY %s1 %2(s1) = G_FCMP floatpred(true), %0(s32), %1 %3(s32) = G_ZEXT %2(s1) %r0 = COPY %3(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_fcmp_false_s32 @@ -393,16 +393,16 @@ body: | liveins: %s0, %s1 ; CHECK-LABEL: name: test_fcmp_false_s32 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _ - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVi]], 1, 14, _, _ + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVi]], 1, 14, %noreg, %noreg ; CHECK: %r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, _, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 %0(s32) = COPY %s0 %1(s32) = COPY %s1 %2(s1) = G_FCMP floatpred(false), %0(s32), %1 %3(s32) = G_ZEXT %2(s1) %r0 = COPY %3(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_fcmp_oeq_s32 @@ -421,19 +421,19 @@ body: | ; CHECK-LABEL: name: test_fcmp_oeq_s32 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _ - ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv - ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg + ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv + ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 0, %cpsr - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _ + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg ; CHECK: %r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, _, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 %0(s32) = COPY %s0 %1(s32) = COPY %s1 %2(s1) = G_FCMP floatpred(oeq), %0(s32), %1 %3(s32) = G_ZEXT %2(s1) %r0 = COPY %3(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_fcmp_ogt_s32 @@ -452,19 +452,19 @@ body: | ; CHECK-LABEL: name: test_fcmp_ogt_s32 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _ - ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv - ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg + ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv + ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 12, %cpsr - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _ + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg ; CHECK: %r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, _, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 %0(s32) = COPY %s0 %1(s32) = COPY %s1 %2(s1) = G_FCMP floatpred(ogt), %0(s32), %1 %3(s32) = G_ZEXT %2(s1) %r0 = COPY %3(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_fcmp_oge_s32 @@ -483,19 +483,19 @@ body: | ; CHECK-LABEL: name: test_fcmp_oge_s32 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _ - ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv - ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg + ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv + ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 10, %cpsr - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _ + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg ; CHECK: %r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, _, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 %0(s32) = COPY %s0 %1(s32) = COPY %s1 %2(s1) = G_FCMP floatpred(oge), %0(s32), %1 %3(s32) = G_ZEXT %2(s1) %r0 = COPY %3(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_fcmp_olt_s32 @@ -514,19 +514,19 @@ body: | ; CHECK-LABEL: name: test_fcmp_olt_s32 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _ - ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv - ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg + ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv + ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 4, %cpsr - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _ + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg ; CHECK: %r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, _, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 %0(s32) = COPY %s0 %1(s32) = COPY %s1 %2(s1) = G_FCMP floatpred(olt), %0(s32), %1 %3(s32) = G_ZEXT %2(s1) %r0 = COPY %3(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_fcmp_ole_s32 @@ -545,19 +545,19 @@ body: | ; CHECK-LABEL: name: test_fcmp_ole_s32 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _ - ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv - ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg + ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv + ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 9, %cpsr - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _ + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg ; CHECK: %r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, _, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 %0(s32) = COPY %s0 %1(s32) = COPY %s1 %2(s1) = G_FCMP floatpred(ole), %0(s32), %1 %3(s32) = G_ZEXT %2(s1) %r0 = COPY %3(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_fcmp_ord_s32 @@ -576,19 +576,19 @@ body: | ; CHECK-LABEL: name: test_fcmp_ord_s32 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _ - ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv - ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg + ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv + ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 7, %cpsr - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _ + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg ; CHECK: %r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, _, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 %0(s32) = COPY %s0 %1(s32) = COPY %s1 %2(s1) = G_FCMP floatpred(ord), %0(s32), %1 %3(s32) = G_ZEXT %2(s1) %r0 = COPY %3(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_fcmp_ugt_s32 @@ -607,19 +607,19 @@ body: | ; CHECK-LABEL: name: test_fcmp_ugt_s32 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _ - ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv - ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg + ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv + ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 8, %cpsr - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _ + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg ; CHECK: %r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, _, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 %0(s32) = COPY %s0 %1(s32) = COPY %s1 %2(s1) = G_FCMP floatpred(ugt), %0(s32), %1 %3(s32) = G_ZEXT %2(s1) %r0 = COPY %3(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_fcmp_uge_s32 @@ -638,19 +638,19 @@ body: | ; CHECK-LABEL: name: test_fcmp_uge_s32 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _ - ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv - ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg + ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv + ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 5, %cpsr - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _ + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg ; CHECK: %r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, _, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 %0(s32) = COPY %s0 %1(s32) = COPY %s1 %2(s1) = G_FCMP floatpred(uge), %0(s32), %1 %3(s32) = G_ZEXT %2(s1) %r0 = COPY %3(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_fcmp_ult_s32 @@ -669,19 +669,19 @@ body: | ; CHECK-LABEL: name: test_fcmp_ult_s32 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _ - ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv - ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg + ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv + ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 11, %cpsr - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _ + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg ; CHECK: %r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, _, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 %0(s32) = COPY %s0 %1(s32) = COPY %s1 %2(s1) = G_FCMP floatpred(ult), %0(s32), %1 %3(s32) = G_ZEXT %2(s1) %r0 = COPY %3(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_fcmp_ule_s32 @@ -700,19 +700,19 @@ body: | ; CHECK-LABEL: name: test_fcmp_ule_s32 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _ - ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv - ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg + ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv + ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 13, %cpsr - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _ + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg ; CHECK: %r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, _, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 %0(s32) = COPY %s0 %1(s32) = COPY %s1 %2(s1) = G_FCMP floatpred(ule), %0(s32), %1 %3(s32) = G_ZEXT %2(s1) %r0 = COPY %3(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_fcmp_une_s32 @@ -731,19 +731,19 @@ body: | ; CHECK-LABEL: name: test_fcmp_une_s32 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _ - ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv - ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg + ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv + ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 1, %cpsr - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _ + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg ; CHECK: %r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, _, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 %0(s32) = COPY %s0 %1(s32) = COPY %s1 %2(s1) = G_FCMP floatpred(une), %0(s32), %1 %3(s32) = G_ZEXT %2(s1) %r0 = COPY %3(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_fcmp_uno_s32 @@ -762,19 +762,19 @@ body: | ; CHECK-LABEL: name: test_fcmp_uno_s32 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _ - ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv - ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg + ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv + ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 6, %cpsr - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _ + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg ; CHECK: %r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, _, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 %0(s32) = COPY %s0 %1(s32) = COPY %s1 %2(s1) = G_FCMP floatpred(uno), %0(s32), %1 %3(s32) = G_ZEXT %2(s1) %r0 = COPY %3(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_fcmp_one_s32 @@ -793,22 +793,22 @@ body: | ; CHECK-LABEL: name: test_fcmp_one_s32 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _ - ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv - ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg + ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv + ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 12, %cpsr - ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv - ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv + ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv + ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv ; CHECK: [[MOVCCi1:%[0-9]+]]:gpr = MOVCCi [[MOVCCi]], 1, 4, %cpsr - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi1]], 1, 14, _, _ + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi1]], 1, 14, %noreg, %noreg ; CHECK: %r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, _, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 %0(s32) = COPY %s0 %1(s32) = COPY %s1 %2(s1) = G_FCMP floatpred(one), %0(s32), %1 %3(s32) = G_ZEXT %2(s1) %r0 = COPY %3(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_fcmp_ueq_s32 @@ -827,22 +827,22 @@ body: | ; CHECK-LABEL: name: test_fcmp_ueq_s32 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _ - ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv - ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg + ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv + ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 0, %cpsr - ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv - ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv + ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv + ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv ; CHECK: [[MOVCCi1:%[0-9]+]]:gpr = MOVCCi [[MOVCCi]], 1, 6, %cpsr - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi1]], 1, 14, _, _ + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi1]], 1, 14, %noreg, %noreg ; CHECK: %r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, _, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 %0(s32) = COPY %s0 %1(s32) = COPY %s1 %2(s1) = G_FCMP floatpred(ueq), %0(s32), %1 %3(s32) = G_ZEXT %2(s1) %r0 = COPY %3(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_fcmp_true_s64 @@ -859,16 +859,16 @@ body: | liveins: %d0, %d1 ; CHECK-LABEL: name: test_fcmp_true_s64 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 1, 14, _, _ - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVi]], 1, 14, _, _ + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 1, 14, %noreg, %noreg + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVi]], 1, 14, %noreg, %noreg ; CHECK: %r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, _, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 %0(s64) = COPY %d0 %1(s64) = COPY %d1 %2(s1) = G_FCMP floatpred(true), %0(s64), %1 %3(s32) = G_ZEXT %2(s1) %r0 = COPY %3(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_fcmp_false_s64 @@ -885,16 +885,16 @@ body: | liveins: %d0, %d1 ; CHECK-LABEL: name: test_fcmp_false_s64 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _ - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVi]], 1, 14, _, _ + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVi]], 1, 14, %noreg, %noreg ; CHECK: %r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, _, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 %0(s64) = COPY %d0 %1(s64) = COPY %d1 %2(s1) = G_FCMP floatpred(false), %0(s64), %1 %3(s32) = G_ZEXT %2(s1) %r0 = COPY %3(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_fcmp_oeq_s64 @@ -913,19 +913,19 @@ body: | ; CHECK-LABEL: name: test_fcmp_oeq_s64 ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _ - ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv - ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg + ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv + ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 0, %cpsr - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _ + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg ; CHECK: %r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, _, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 %0(s64) = COPY %d0 %1(s64) = COPY %d1 %2(s1) = G_FCMP floatpred(oeq), %0(s64), %1 %3(s32) = G_ZEXT %2(s1) %r0 = COPY %3(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_fcmp_ogt_s64 @@ -944,19 +944,19 @@ body: | ; CHECK-LABEL: name: test_fcmp_ogt_s64 ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _ - ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv - ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg + ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv + ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 12, %cpsr - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _ + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg ; CHECK: %r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, _, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 %0(s64) = COPY %d0 %1(s64) = COPY %d1 %2(s1) = G_FCMP floatpred(ogt), %0(s64), %1 %3(s32) = G_ZEXT %2(s1) %r0 = COPY %3(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_fcmp_oge_s64 @@ -975,19 +975,19 @@ body: | ; CHECK-LABEL: name: test_fcmp_oge_s64 ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _ - ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv - ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg + ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv + ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 10, %cpsr - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _ + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg ; CHECK: %r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, _, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 %0(s64) = COPY %d0 %1(s64) = COPY %d1 %2(s1) = G_FCMP floatpred(oge), %0(s64), %1 %3(s32) = G_ZEXT %2(s1) %r0 = COPY %3(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_fcmp_olt_s64 @@ -1006,19 +1006,19 @@ body: | ; CHECK-LABEL: name: test_fcmp_olt_s64 ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _ - ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv - ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg + ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv + ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 4, %cpsr - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _ + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg ; CHECK: %r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, _, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 %0(s64) = COPY %d0 %1(s64) = COPY %d1 %2(s1) = G_FCMP floatpred(olt), %0(s64), %1 %3(s32) = G_ZEXT %2(s1) %r0 = COPY %3(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_fcmp_ole_s64 @@ -1037,19 +1037,19 @@ body: | ; CHECK-LABEL: name: test_fcmp_ole_s64 ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _ - ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv - ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg + ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv + ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 9, %cpsr - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _ + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg ; CHECK: %r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, _, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 %0(s64) = COPY %d0 %1(s64) = COPY %d1 %2(s1) = G_FCMP floatpred(ole), %0(s64), %1 %3(s32) = G_ZEXT %2(s1) %r0 = COPY %3(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_fcmp_ord_s64 @@ -1068,19 +1068,19 @@ body: | ; CHECK-LABEL: name: test_fcmp_ord_s64 ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _ - ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv - ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg + ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv + ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 7, %cpsr - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _ + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg ; CHECK: %r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, _, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 %0(s64) = COPY %d0 %1(s64) = COPY %d1 %2(s1) = G_FCMP floatpred(ord), %0(s64), %1 %3(s32) = G_ZEXT %2(s1) %r0 = COPY %3(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_fcmp_ugt_s64 @@ -1099,19 +1099,19 @@ body: | ; CHECK-LABEL: name: test_fcmp_ugt_s64 ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _ - ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv - ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg + ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv + ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 8, %cpsr - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _ + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg ; CHECK: %r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, _, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 %0(s64) = COPY %d0 %1(s64) = COPY %d1 %2(s1) = G_FCMP floatpred(ugt), %0(s64), %1 %3(s32) = G_ZEXT %2(s1) %r0 = COPY %3(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_fcmp_uge_s64 @@ -1130,19 +1130,19 @@ body: | ; CHECK-LABEL: name: test_fcmp_uge_s64 ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _ - ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv - ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg + ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv + ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 5, %cpsr - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _ + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg ; CHECK: %r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, _, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 %0(s64) = COPY %d0 %1(s64) = COPY %d1 %2(s1) = G_FCMP floatpred(uge), %0(s64), %1 %3(s32) = G_ZEXT %2(s1) %r0 = COPY %3(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_fcmp_ult_s64 @@ -1161,19 +1161,19 @@ body: | ; CHECK-LABEL: name: test_fcmp_ult_s64 ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _ - ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv - ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg + ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv + ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 11, %cpsr - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _ + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg ; CHECK: %r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, _, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 %0(s64) = COPY %d0 %1(s64) = COPY %d1 %2(s1) = G_FCMP floatpred(ult), %0(s64), %1 %3(s32) = G_ZEXT %2(s1) %r0 = COPY %3(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_fcmp_ule_s64 @@ -1192,19 +1192,19 @@ body: | ; CHECK-LABEL: name: test_fcmp_ule_s64 ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _ - ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv - ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg + ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv + ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 13, %cpsr - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _ + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg ; CHECK: %r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, _, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 %0(s64) = COPY %d0 %1(s64) = COPY %d1 %2(s1) = G_FCMP floatpred(ule), %0(s64), %1 %3(s32) = G_ZEXT %2(s1) %r0 = COPY %3(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_fcmp_une_s64 @@ -1223,19 +1223,19 @@ body: | ; CHECK-LABEL: name: test_fcmp_une_s64 ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _ - ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv - ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg + ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv + ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 1, %cpsr - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _ + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg ; CHECK: %r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, _, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 %0(s64) = COPY %d0 %1(s64) = COPY %d1 %2(s1) = G_FCMP floatpred(une), %0(s64), %1 %3(s32) = G_ZEXT %2(s1) %r0 = COPY %3(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_fcmp_uno_s64 @@ -1254,19 +1254,19 @@ body: | ; CHECK-LABEL: name: test_fcmp_uno_s64 ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _ - ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv - ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg + ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv + ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 6, %cpsr - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _ + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg ; CHECK: %r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, _, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 %0(s64) = COPY %d0 %1(s64) = COPY %d1 %2(s1) = G_FCMP floatpred(uno), %0(s64), %1 %3(s32) = G_ZEXT %2(s1) %r0 = COPY %3(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_fcmp_one_s64 @@ -1285,22 +1285,22 @@ body: | ; CHECK-LABEL: name: test_fcmp_one_s64 ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _ - ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv - ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg + ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv + ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 12, %cpsr - ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv - ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv + ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv + ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv ; CHECK: [[MOVCCi1:%[0-9]+]]:gpr = MOVCCi [[MOVCCi]], 1, 4, %cpsr - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi1]], 1, 14, _, _ + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi1]], 1, 14, %noreg, %noreg ; CHECK: %r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, _, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 %0(s64) = COPY %d0 %1(s64) = COPY %d1 %2(s1) = G_FCMP floatpred(one), %0(s64), %1 %3(s32) = G_ZEXT %2(s1) %r0 = COPY %3(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_fcmp_ueq_s64 @@ -1319,20 +1319,20 @@ body: | ; CHECK-LABEL: name: test_fcmp_ueq_s64 ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _ - ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv - ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg + ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv + ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 0, %cpsr - ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv - ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv + ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv + ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv ; CHECK: [[MOVCCi1:%[0-9]+]]:gpr = MOVCCi [[MOVCCi]], 1, 6, %cpsr - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi1]], 1, 14, _, _ + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi1]], 1, 14, %noreg, %noreg ; CHECK: %r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, _, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 %0(s64) = COPY %d0 %1(s64) = COPY %d1 %2(s1) = G_FCMP floatpred(ueq), %0(s64), %1 %3(s32) = G_ZEXT %2(s1) %r0 = COPY %3(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... diff --git a/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir b/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir index d8da96103fba8..cee6a121bf838 100644 --- a/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir +++ b/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir @@ -50,13 +50,13 @@ body: | %3(s32) = G_MUL %0, %1 %4(s32) = G_ADD %3, %2 - ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = MLA [[VREGX]], [[VREGY]], [[VREGZ]], 14, _, _ + ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = MLA [[VREGX]], [[VREGY]], [[VREGZ]], 14, %noreg, %noreg %r0 = COPY %4(s32) ; CHECK: %r0 = COPY [[VREGR]] - BX_RET 14, _, implicit %r0 - ; CHECK: BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 ... --- name: test_mla_commutative @@ -84,13 +84,13 @@ body: | %3(s32) = G_MUL %0, %1 %4(s32) = G_ADD %2, %3 - ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = MLA [[VREGX]], [[VREGY]], [[VREGZ]], 14, _, _ + ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = MLA [[VREGX]], [[VREGY]], [[VREGZ]], 14, %noreg, %noreg %r0 = COPY %4(s32) ; CHECK: %r0 = COPY [[VREGR]] - BX_RET 14, _, implicit %r0 - ; CHECK: BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 ... --- name: test_mla_v5 @@ -118,13 +118,13 @@ body: | %3(s32) = G_MUL %0, %1 %4(s32) = G_ADD %3, %2 - ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = MLAv5 [[VREGX]], [[VREGY]], [[VREGZ]], 14, _, _ + ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = MLAv5 [[VREGX]], [[VREGY]], [[VREGZ]], 14, %noreg, %noreg %r0 = COPY %4(s32) ; CHECK: %r0 = COPY [[VREGR]] - BX_RET 14, _, implicit %r0 - ; CHECK: BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 ... --- name: test_mls @@ -152,13 +152,13 @@ body: | %3(s32) = G_MUL %0, %1 %4(s32) = G_SUB %2, %3 - ; CHECK: [[VREGR:%[0-9]+]]:gpr = MLS [[VREGX]], [[VREGY]], [[VREGZ]], 14, _ + ; CHECK: [[VREGR:%[0-9]+]]:gpr = MLS [[VREGX]], [[VREGY]], [[VREGZ]], 14, %noreg %r0 = COPY %4(s32) ; CHECK: %r0 = COPY [[VREGR]] - BX_RET 14, _, implicit %r0 - ; CHECK: BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 ... --- name: test_no_mls @@ -186,14 +186,14 @@ body: | %3(s32) = G_MUL %0, %1 %4(s32) = G_SUB %2, %3 - ; CHECK: [[VREGM:%[0-9]+]]:gprnopc = MULv5 [[VREGX]], [[VREGY]], 14, _, _ - ; CHECK: [[VREGR:%[0-9]+]]:gpr = SUBrr [[VREGZ]], [[VREGM]], 14, _, _ + ; CHECK: [[VREGM:%[0-9]+]]:gprnopc = MULv5 [[VREGX]], [[VREGY]], 14, %noreg, %noreg + ; CHECK: [[VREGR:%[0-9]+]]:gpr = SUBrr [[VREGZ]], [[VREGM]], 14, %noreg, %noreg %r0 = COPY %4(s32) ; CHECK: %r0 = COPY [[VREGR]] - BX_RET 14, _, implicit %r0 - ; CHECK: BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 ... --- name: test_shifts_to_revsh @@ -238,8 +238,8 @@ body: | %r0 = COPY %9(s32) ; CHECK: %r0 = COPY [[VREGR]] - BX_RET 14, _, implicit %r0 - ; CHECK: BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 ... --- name: test_shifts_to_revsh_commutative @@ -284,8 +284,8 @@ body: | %r0 = COPY %9(s32) ; CHECK: %r0 = COPY [[VREGR]] - BX_RET 14, _, implicit %r0 - ; CHECK: BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 ... --- name: test_shifts_no_revsh_features @@ -329,7 +329,7 @@ body: | %r0 = COPY %9(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_shifts_no_revsh_constants @@ -373,7 +373,7 @@ body: | %r0 = COPY %9(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_bicrr @@ -400,13 +400,13 @@ body: | %2(s32) = G_CONSTANT i32 -1 %3(s32) = G_XOR %1, %2 %4(s32) = G_AND %0, %3 - ; CHECK: [[VREGR:%[0-9]+]]:gpr = BICrr [[VREGX]], [[VREGY]], 14, _, _ + ; CHECK: [[VREGR:%[0-9]+]]:gpr = BICrr [[VREGX]], [[VREGY]], 14, %noreg, %noreg %r0 = COPY %4(s32) ; CHECK: %r0 = COPY [[VREGR]] - BX_RET 14, _, implicit %r0 - ; CHECK: BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 ... --- name: test_bicrr_commutative @@ -433,13 +433,13 @@ body: | %2(s32) = G_CONSTANT i32 -1 %3(s32) = G_XOR %1, %2 %4(s32) = G_AND %3, %0 - ; CHECK: [[VREGR:%[0-9]+]]:gpr = BICrr [[VREGX]], [[VREGY]], 14, _, _ + ; CHECK: [[VREGR:%[0-9]+]]:gpr = BICrr [[VREGX]], [[VREGY]], 14, %noreg, %noreg %r0 = COPY %4(s32) ; CHECK: %r0 = COPY [[VREGR]] - BX_RET 14, _, implicit %r0 - ; CHECK: BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 ... --- name: test_bicri @@ -471,13 +471,13 @@ body: | %2(s32) = G_CONSTANT i32 -1 %3(s32) = G_XOR %1, %2 %4(s32) = G_AND %0, %3 - ; CHECK: [[VREGR:%[0-9]+]]:gpr = BICri [[VREGX]], 192, 14, _, _ + ; CHECK: [[VREGR:%[0-9]+]]:gpr = BICri [[VREGX]], 192, 14, %noreg, %noreg %r0 = COPY %4(s32) ; CHECK: %r0 = COPY [[VREGR]] - BX_RET 14, _, implicit %r0 - ; CHECK: BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 ... --- name: test_bicri_commutative_xor @@ -504,13 +504,13 @@ body: | %2(s32) = G_CONSTANT i32 -1 %3(s32) = G_XOR %2, %1 %4(s32) = G_AND %0, %3 - ; CHECK: [[VREGR:%[0-9]+]]:gpr = BICri [[VREGX]], 192, 14, _, _ + ; CHECK: [[VREGR:%[0-9]+]]:gpr = BICri [[VREGX]], 192, 14, %noreg, %noreg %r0 = COPY %4(s32) ; CHECK: %r0 = COPY [[VREGR]] - BX_RET 14, _, implicit %r0 - ; CHECK: BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 ... --- name: test_bicri_commutative_and @@ -537,13 +537,13 @@ body: | %2(s32) = G_CONSTANT i32 -1 %3(s32) = G_XOR %1, %2 %4(s32) = G_AND %3, %0 - ; CHECK: [[VREGR:%[0-9]+]]:gpr = BICri [[VREGX]], 192, 14, _, _ + ; CHECK: [[VREGR:%[0-9]+]]:gpr = BICri [[VREGX]], 192, 14, %noreg, %noreg %r0 = COPY %4(s32) ; CHECK: %r0 = COPY [[VREGR]] - BX_RET 14, _, implicit %r0 - ; CHECK: BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 ... --- name: test_bicri_commutative_both @@ -570,11 +570,11 @@ body: | %2(s32) = G_CONSTANT i32 -1 %3(s32) = G_XOR %2, %1 %4(s32) = G_AND %3, %0 - ; CHECK: [[VREGR:%[0-9]+]]:gpr = BICri [[VREGX]], 192, 14, _, _ + ; CHECK: [[VREGR:%[0-9]+]]:gpr = BICri [[VREGX]], 192, 14, %noreg, %noreg %r0 = COPY %4(s32) ; CHECK: %r0 = COPY [[VREGR]] - BX_RET 14, _, implicit %r0 - ; CHECK: BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 ... diff --git a/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir b/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir index 64773e7ebb12e..7c2666e3680fa 100644 --- a/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir +++ b/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir @@ -81,13 +81,13 @@ body: | ; CHECK: [[VREGTRUNC:%[0-9]+]]:gpr = COPY [[VREG]] %2(s32) = G_ZEXT %1(s1) - ; CHECK: [[VREGEXT:%[0-9]+]]:gpr = ANDri [[VREGTRUNC]], 1, 14, _, _ + ; CHECK: [[VREGEXT:%[0-9]+]]:gpr = ANDri [[VREGTRUNC]], 1, 14, %noreg, %noreg %r0 = COPY %2(s32) ; CHECK: %r0 = COPY [[VREGEXT]] - BX_RET 14, _, implicit %r0 - ; CHECK: BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 ... --- name: test_trunc_and_sext_s1 @@ -111,14 +111,14 @@ body: | ; CHECK: [[VREGTRUNC:%[0-9]+]]:gpr = COPY [[VREG]] %2(s32) = G_SEXT %1(s1) - ; CHECK: [[VREGAND:%[0-9]+]]:gpr = ANDri [[VREGTRUNC]], 1, 14, _, _ - ; CHECK: [[VREGEXT:%[0-9]+]]:gpr = RSBri [[VREGAND]], 0, 14, _, _ + ; CHECK: [[VREGAND:%[0-9]+]]:gpr = ANDri [[VREGTRUNC]], 1, 14, %noreg, %noreg + ; CHECK: [[VREGEXT:%[0-9]+]]:gpr = RSBri [[VREGAND]], 0, 14, %noreg, %noreg %r0 = COPY %2(s32) ; CHECK: %r0 = COPY [[VREGEXT]] - BX_RET 14, _, implicit %r0 - ; CHECK: BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 ... --- name: test_trunc_and_sext_s8 @@ -142,13 +142,13 @@ body: | ; CHECK: [[VREGTRUNC:%[0-9]+]]:gprnopc = COPY [[VREG]] %2(s32) = G_SEXT %1(s8) - ; CHECK: [[VREGEXT:%[0-9]+]]:gprnopc = SXTB [[VREGTRUNC]], 0, 14, _ + ; CHECK: [[VREGEXT:%[0-9]+]]:gprnopc = SXTB [[VREGTRUNC]], 0, 14, %noreg %r0 = COPY %2(s32) ; CHECK: %r0 = COPY [[VREGEXT]] - BX_RET 14, _, implicit %r0 - ; CHECK: BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 ... --- name: test_trunc_and_zext_s16 @@ -172,13 +172,13 @@ body: | ; CHECK: [[VREGTRUNC:%[0-9]+]]:gprnopc = COPY [[VREG]] %2(s32) = G_ZEXT %1(s16) - ; CHECK: [[VREGEXT:%[0-9]+]]:gprnopc = UXTH [[VREGTRUNC]], 0, 14, _ + ; CHECK: [[VREGEXT:%[0-9]+]]:gprnopc = UXTH [[VREGTRUNC]], 0, 14, %noreg %r0 = COPY %2(s32) ; CHECK: %r0 = COPY [[VREGEXT]] - BX_RET 14, _, implicit %r0 - ; CHECK: BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 ... --- name: test_trunc_and_anyext_s8 @@ -207,8 +207,8 @@ body: | %r0 = COPY %2(s32) ; CHECK: %r0 = COPY [[VREGEXT]] - BX_RET 14, _, implicit %r0 - ; CHECK: BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 ... --- name: test_trunc_and_anyext_s16 @@ -237,8 +237,8 @@ body: | %r0 = COPY %2(s32) ; CHECK: %r0 = COPY [[VREGEXT]] - BX_RET 14, _, implicit %r0 - ; CHECK: BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 ... --- name: test_add_s32 @@ -262,13 +262,13 @@ body: | ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1 %2(s32) = G_ADD %0, %1 - ; CHECK: [[VREGSUM:%[0-9]+]]:gpr = ADDrr [[VREGX]], [[VREGY]], 14, _, _ + ; CHECK: [[VREGSUM:%[0-9]+]]:gpr = ADDrr [[VREGX]], [[VREGY]], 14, %noreg, %noreg %r0 = COPY %2(s32) ; CHECK: %r0 = COPY [[VREGSUM]] - BX_RET 14, _, implicit %r0 - ; CHECK: BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 ... --- name: test_add_fold_imm_s32 @@ -290,13 +290,13 @@ body: | %1(s32) = G_CONSTANT i32 255 %2(s32) = G_ADD %0, %1 - ; CHECK: [[VREGSUM:%[0-9]+]]:gpr = ADDri [[VREGX]], 255, 14, _, _ + ; CHECK: [[VREGSUM:%[0-9]+]]:gpr = ADDri [[VREGX]], 255, 14, %noreg, %noreg %r0 = COPY %2(s32) ; CHECK: %r0 = COPY [[VREGSUM]] - BX_RET 14, _, implicit %r0 - ; CHECK: BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 ... --- name: test_add_no_fold_imm_s32 @@ -317,16 +317,16 @@ body: | ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0 %1(s32) = G_CONSTANT i32 65535 - ; CHECK: [[VREGY:%[0-9]+]]:gpr = MOVi16 65535, 14, _ + ; CHECK: [[VREGY:%[0-9]+]]:gpr = MOVi16 65535, 14, %noreg %2(s32) = G_ADD %0, %1 - ; CHECK: [[VREGSUM:%[0-9]+]]:gpr = ADDrr [[VREGX]], [[VREGY]], 14, _, _ + ; CHECK: [[VREGSUM:%[0-9]+]]:gpr = ADDrr [[VREGX]], [[VREGY]], 14, %noreg, %noreg %r0 = COPY %2(s32) ; CHECK: %r0 = COPY [[VREGSUM]] - BX_RET 14, _, implicit %r0 - ; CHECK: BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 ... --- name: test_fadd_s32 @@ -350,13 +350,13 @@ body: | ; CHECK: [[VREGY:%[0-9]+]]:spr = COPY %s1 %2(s32) = G_FADD %0, %1 - ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VADDS [[VREGX]], [[VREGY]], 14, _ + ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VADDS [[VREGX]], [[VREGY]], 14, %noreg %s0 = COPY %2(s32) ; CHECK: %s0 = COPY [[VREGSUM]] - BX_RET 14, _, implicit %s0 - ; CHECK: BX_RET 14, _, implicit %s0 + BX_RET 14, %noreg, implicit %s0 + ; CHECK: BX_RET 14, %noreg, implicit %s0 ... --- name: test_fadd_s64 @@ -380,13 +380,13 @@ body: | ; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY %d1 %2(s64) = G_FADD %0, %1 - ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VADDD [[VREGX]], [[VREGY]], 14, _ + ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VADDD [[VREGX]], [[VREGY]], 14, %noreg %d0 = COPY %2(s64) ; CHECK: %d0 = COPY [[VREGSUM]] - BX_RET 14, _, implicit %d0 - ; CHECK: BX_RET 14, _, implicit %d0 + BX_RET 14, %noreg, implicit %d0 + ; CHECK: BX_RET 14, %noreg, implicit %d0 ... --- name: test_fsub_s32 @@ -410,13 +410,13 @@ body: | ; CHECK: [[VREGY:%[0-9]+]]:spr = COPY %s1 %2(s32) = G_FSUB %0, %1 - ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VSUBS [[VREGX]], [[VREGY]], 14, _ + ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VSUBS [[VREGX]], [[VREGY]], 14, %noreg %s0 = COPY %2(s32) ; CHECK: %s0 = COPY [[VREGSUM]] - BX_RET 14, _, implicit %s0 - ; CHECK: BX_RET 14, _, implicit %s0 + BX_RET 14, %noreg, implicit %s0 + ; CHECK: BX_RET 14, %noreg, implicit %s0 ... --- name: test_fsub_s64 @@ -440,13 +440,13 @@ body: | ; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY %d1 %2(s64) = G_FSUB %0, %1 - ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VSUBD [[VREGX]], [[VREGY]], 14, _ + ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VSUBD [[VREGX]], [[VREGY]], 14, %noreg %d0 = COPY %2(s64) ; CHECK: %d0 = COPY [[VREGSUM]] - BX_RET 14, _, implicit %d0 - ; CHECK: BX_RET 14, _, implicit %d0 + BX_RET 14, %noreg, implicit %d0 + ; CHECK: BX_RET 14, %noreg, implicit %d0 ... --- name: test_fmul_s32 @@ -470,13 +470,13 @@ body: | ; CHECK: [[VREGY:%[0-9]+]]:spr = COPY %s1 %2(s32) = G_FMUL %0, %1 - ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VMULS [[VREGX]], [[VREGY]], 14, _ + ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VMULS [[VREGX]], [[VREGY]], 14, %noreg %s0 = COPY %2(s32) ; CHECK: %s0 = COPY [[VREGSUM]] - BX_RET 14, _, implicit %s0 - ; CHECK: BX_RET 14, _, implicit %s0 + BX_RET 14, %noreg, implicit %s0 + ; CHECK: BX_RET 14, %noreg, implicit %s0 ... --- name: test_fmul_s64 @@ -500,13 +500,13 @@ body: | ; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY %d1 %2(s64) = G_FMUL %0, %1 - ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VMULD [[VREGX]], [[VREGY]], 14, _ + ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VMULD [[VREGX]], [[VREGY]], 14, %noreg %d0 = COPY %2(s64) ; CHECK: %d0 = COPY [[VREGSUM]] - BX_RET 14, _, implicit %d0 - ; CHECK: BX_RET 14, _, implicit %d0 + BX_RET 14, %noreg, implicit %d0 + ; CHECK: BX_RET 14, %noreg, implicit %d0 ... --- name: test_fdiv_s32 @@ -530,13 +530,13 @@ body: | ; CHECK: [[VREGY:%[0-9]+]]:spr = COPY %s1 %2(s32) = G_FDIV %0, %1 - ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VDIVS [[VREGX]], [[VREGY]], 14, _ + ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VDIVS [[VREGX]], [[VREGY]], 14, %noreg %s0 = COPY %2(s32) ; CHECK: %s0 = COPY [[VREGSUM]] - BX_RET 14, _, implicit %s0 - ; CHECK: BX_RET 14, _, implicit %s0 + BX_RET 14, %noreg, implicit %s0 + ; CHECK: BX_RET 14, %noreg, implicit %s0 ... --- name: test_fdiv_s64 @@ -560,13 +560,13 @@ body: | ; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY %d1 %2(s64) = G_FDIV %0, %1 - ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VDIVD [[VREGX]], [[VREGY]], 14, _ + ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VDIVD [[VREGX]], [[VREGY]], 14, %noreg %d0 = COPY %2(s64) ; CHECK: %d0 = COPY [[VREGSUM]] - BX_RET 14, _, implicit %d0 - ; CHECK: BX_RET 14, _, implicit %d0 + BX_RET 14, %noreg, implicit %d0 + ; CHECK: BX_RET 14, %noreg, implicit %d0 ... --- name: test_sub_s32 @@ -590,13 +590,13 @@ body: | ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1 %2(s32) = G_SUB %0, %1 - ; CHECK: [[VREGRES:%[0-9]+]]:gpr = SUBrr [[VREGX]], [[VREGY]], 14, _, _ + ; CHECK: [[VREGRES:%[0-9]+]]:gpr = SUBrr [[VREGX]], [[VREGY]], 14, %noreg, %noreg %r0 = COPY %2(s32) ; CHECK: %r0 = COPY [[VREGRES]] - BX_RET 14, _, implicit %r0 - ; CHECK: BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 ... --- name: test_sub_imm_s32 @@ -618,13 +618,13 @@ body: | %1(s32) = G_CONSTANT i32 17 %2(s32) = G_SUB %0, %1 - ; CHECK: [[VREGRES:%[0-9]+]]:gpr = SUBri [[VREGX]], 17, 14, _, _ + ; CHECK: [[VREGRES:%[0-9]+]]:gpr = SUBri [[VREGX]], 17, 14, %noreg, %noreg %r0 = COPY %2(s32) ; CHECK: %r0 = COPY [[VREGRES]] - BX_RET 14, _, implicit %r0 - ; CHECK: BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 ... --- name: test_sub_rev_imm_s32 @@ -646,13 +646,13 @@ body: | %1(s32) = G_CONSTANT i32 17 %2(s32) = G_SUB %1, %0 - ; CHECK: [[VREGRES:%[0-9]+]]:gpr = RSBri [[VREGX]], 17, 14, _, _ + ; CHECK: [[VREGRES:%[0-9]+]]:gpr = RSBri [[VREGX]], 17, 14, %noreg, %noreg %r0 = COPY %2(s32) ; CHECK: %r0 = COPY [[VREGRES]] - BX_RET 14, _, implicit %r0 - ; CHECK: BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 ... --- name: test_mul_s32 @@ -676,13 +676,13 @@ body: | ; CHECK: [[VREGY:%[0-9]+]]:gprnopc = COPY %r1 %2(s32) = G_MUL %0, %1 - ; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = MUL [[VREGX]], [[VREGY]], 14, _, _ + ; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = MUL [[VREGX]], [[VREGY]], 14, %noreg, %noreg %r0 = COPY %2(s32) ; CHECK: %r0 = COPY [[VREGRES]] - BX_RET 14, _, implicit %r0 - ; CHECK: BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 ... --- name: test_mulv5_s32 @@ -706,13 +706,13 @@ body: | ; CHECK: [[VREGY:%[0-9]+]]:gprnopc = COPY %r1 %2(s32) = G_MUL %0, %1 - ; CHECK: early-clobber [[VREGRES:%[0-9]+]]:gprnopc = MULv5 [[VREGX]], [[VREGY]], 14, _, _ + ; CHECK: early-clobber [[VREGRES:%[0-9]+]]:gprnopc = MULv5 [[VREGX]], [[VREGY]], 14, %noreg, %noreg %r0 = COPY %2(s32) ; CHECK: %r0 = COPY [[VREGRES]] - BX_RET 14, _, implicit %r0 - ; CHECK: BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 ... --- name: test_sdiv_s32 @@ -736,13 +736,13 @@ body: | ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1 %2(s32) = G_SDIV %0, %1 - ; CHECK: [[VREGRES:%[0-9]+]]:gpr = SDIV [[VREGX]], [[VREGY]], 14, _ + ; CHECK: [[VREGRES:%[0-9]+]]:gpr = SDIV [[VREGX]], [[VREGY]], 14, %noreg %r0 = COPY %2(s32) ; CHECK: %r0 = COPY [[VREGRES]] - BX_RET 14, _, implicit %r0 - ; CHECK: BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 ... --- name: test_udiv_s32 @@ -766,13 +766,13 @@ body: | ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1 %2(s32) = G_UDIV %0, %1 - ; CHECK: [[VREGRES:%[0-9]+]]:gpr = UDIV [[VREGX]], [[VREGY]], 14, _ + ; CHECK: [[VREGRES:%[0-9]+]]:gpr = UDIV [[VREGX]], [[VREGY]], 14, %noreg %r0 = COPY %2(s32) ; CHECK: %r0 = COPY [[VREGRES]] - BX_RET 14, _, implicit %r0 - ; CHECK: BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 ... --- name: test_lshr_s32 @@ -796,13 +796,13 @@ body: | ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1 %2(s32) = G_LSHR %0, %1 - ; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = MOVsr [[VREGX]], [[VREGY]], 3, 14, _, _ + ; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = MOVsr [[VREGX]], [[VREGY]], 3, 14, %noreg, %noreg %r0 = COPY %2(s32) ; CHECK: %r0 = COPY [[VREGRES]] - BX_RET 14, _, implicit %r0 - ; CHECK: BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 ... --- name: test_ashr_s32 @@ -826,13 +826,13 @@ body: | ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1 %2(s32) = G_ASHR %0, %1 - ; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = MOVsr [[VREGX]], [[VREGY]], 1, 14, _, _ + ; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = MOVsr [[VREGX]], [[VREGY]], 1, 14, %noreg, %noreg %r0 = COPY %2(s32) ; CHECK: %r0 = COPY [[VREGRES]] - BX_RET 14, _, implicit %r0 - ; CHECK: BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 ... --- name: test_shl_s32 @@ -856,13 +856,13 @@ body: | ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1 %2(s32) = G_SHL %0, %1 - ; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = MOVsr [[VREGX]], [[VREGY]], 2, 14, _, _ + ; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = MOVsr [[VREGX]], [[VREGY]], 2, 14, %noreg, %noreg %r0 = COPY %2(s32) ; CHECK: %r0 = COPY [[VREGRES]] - BX_RET 14, _, implicit %r0 - ; CHECK: BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 ... --- name: test_load_from_stack @@ -888,19 +888,19 @@ body: | liveins: %r0, %r1, %r2, %r3 %0(p0) = G_FRAME_INDEX %fixed-stack.2 - ; CHECK: [[FI32VREG:%[0-9]+]]:gpr = ADDri %fixed-stack.[[FI32]], 0, 14, _, _ + ; CHECK: [[FI32VREG:%[0-9]+]]:gpr = ADDri %fixed-stack.[[FI32]], 0, 14, %noreg, %noreg %1(s32) = G_LOAD %0(p0) :: (load 4) - ; CHECK: [[LD32VREG:%[0-9]+]]:gpr = LDRi12 [[FI32VREG]], 0, 14, _ + ; CHECK: [[LD32VREG:%[0-9]+]]:gpr = LDRi12 [[FI32VREG]], 0, 14, %noreg %r0 = COPY %1 ; CHECK: %r0 = COPY [[LD32VREG]] %2(p0) = G_FRAME_INDEX %fixed-stack.0 - ; CHECK: [[FI1VREG:%[0-9]+]]:gpr = ADDri %fixed-stack.[[FI1]], 0, 14, _, _ + ; CHECK: [[FI1VREG:%[0-9]+]]:gpr = ADDri %fixed-stack.[[FI1]], 0, 14, %noreg, %noreg %3(s1) = G_LOAD %2(p0) :: (load 1) - ; CHECK: [[LD1VREG:%[0-9]+]]:gprnopc = LDRBi12 [[FI1VREG]], 0, 14, _ + ; CHECK: [[LD1VREG:%[0-9]+]]:gprnopc = LDRBi12 [[FI1VREG]], 0, 14, %noreg %4(s32) = G_ANYEXT %3(s1) ; CHECK: [[RES:%[0-9]+]]:gpr = COPY [[LD1VREG]] @@ -908,8 +908,8 @@ body: | %r0 = COPY %4 ; CHECK: %r0 = COPY [[RES]] - BX_RET 14, _ - ; CHECK: BX_RET 14, _ + BX_RET 14, %noreg + ; CHECK: BX_RET 14, %noreg ... --- name: test_load_f32 @@ -929,13 +929,13 @@ body: | ; CHECK: %[[P:[0-9]+]]:gpr = COPY %r0 %1(s32) = G_LOAD %0(p0) :: (load 4) - ; CHECK: %[[V:[0-9]+]]:spr = VLDRS %[[P]], 0, 14, _ + ; CHECK: %[[V:[0-9]+]]:spr = VLDRS %[[P]], 0, 14, %noreg %s0 = COPY %1 ; CHECK: %s0 = COPY %[[V]] - BX_RET 14, _, implicit %s0 - ; CHECK: BX_RET 14, _, implicit %s0 + BX_RET 14, %noreg, implicit %s0 + ; CHECK: BX_RET 14, %noreg, implicit %s0 ... --- name: test_load_f64 @@ -955,13 +955,13 @@ body: | ; CHECK: %[[P:[0-9]+]]:gpr = COPY %r0 %1(s64) = G_LOAD %0(p0) :: (load 8) - ; CHECK: %[[V:[0-9]+]]:dpr = VLDRD %[[P]], 0, 14, _ + ; CHECK: %[[V:[0-9]+]]:dpr = VLDRD %[[P]], 0, 14, %noreg %d0 = COPY %1 ; CHECK: %d0 = COPY %[[V]] - BX_RET 14, _, implicit %d0 - ; CHECK: BX_RET 14, _, implicit %d0 + BX_RET 14, %noreg, implicit %d0 + ; CHECK: BX_RET 14, %noreg, implicit %d0 ... --- name: test_stores @@ -995,21 +995,21 @@ body: | %2(s16) = G_TRUNC %3(s32) G_STORE %1(s8), %0(p0) :: (store 1) - ; CHECK: STRBi12 %[[I8]], %[[P]], 0, 14, _ + ; CHECK: STRBi12 %[[I8]], %[[P]], 0, 14, %noreg G_STORE %2(s16), %0(p0) :: (store 2) - ; CHECK: STRH %[[I16]], %[[P]], _, 0, 14, _ + ; CHECK: STRH %[[I16]], %[[P]], %noreg, 0, 14, %noreg G_STORE %3(s32), %0(p0) :: (store 4) - ; CHECK: STRi12 %[[I32]], %[[P]], 0, 14, _ + ; CHECK: STRi12 %[[I32]], %[[P]], 0, 14, %noreg G_STORE %4(s32), %0(p0) :: (store 4) - ; CHECK: VSTRS %[[F32]], %[[P]], 0, 14, _ + ; CHECK: VSTRS %[[F32]], %[[P]], 0, 14, %noreg G_STORE %5(s64), %0(p0) :: (store 8) - ; CHECK: VSTRD %[[F64]], %[[P]], 0, 14, _ + ; CHECK: VSTRD %[[F64]], %[[P]], 0, 14, %noreg - BX_RET 14, _ + BX_RET 14, %noreg ... --- name: test_gep @@ -1033,10 +1033,10 @@ body: | ; CHECK: %[[OFF:[0-9]+]]:gpr = COPY %r1 %2(p0) = G_GEP %0, %1(s32) - ; CHECK: %[[GEP:[0-9]+]]:gpr = ADDrr %[[PTR]], %[[OFF]], 14, _, _ + ; CHECK: %[[GEP:[0-9]+]]:gpr = ADDrr %[[PTR]], %[[OFF]], 14, %noreg, %noreg %r0 = COPY %2(p0) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_constant_imm @@ -1050,10 +1050,10 @@ registers: body: | bb.0: %0(s32) = G_CONSTANT 42 - ; CHECK: %[[C:[0-9]+]]:gpr = MOVi 42, 14, _, _ + ; CHECK: %[[C:[0-9]+]]:gpr = MOVi 42, 14, %noreg, %noreg %r0 = COPY %0(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_constant_cimm @@ -1069,10 +1069,10 @@ body: | ; Adding a type on G_CONSTANT changes its operand from an Imm into a CImm. ; We still want to see the same thing in the output though. %0(s32) = G_CONSTANT i32 42 - ; CHECK: %[[C:[0-9]+]]:gpr = MOVi 42, 14, _, _ + ; CHECK: %[[C:[0-9]+]]:gpr = MOVi 42, 14, %noreg, %noreg %r0 = COPY %0(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_select_s32 @@ -1100,14 +1100,14 @@ body: | ; CHECK: [[VREGC:%[0-9]+]]:gpr = COPY [[VREGY]] %3(s32) = G_SELECT %2(s1), %0, %1 - ; CHECK: CMPri [[VREGC]], 0, 14, _, implicit-def %cpsr + ; CHECK: CMPri [[VREGC]], 0, 14, %noreg, implicit-def %cpsr ; CHECK: [[RES:%[0-9]+]]:gpr = MOVCCr [[VREGX]], [[VREGY]], 0, %cpsr %r0 = COPY %3(s32) ; CHECK: %r0 = COPY [[RES]] - BX_RET 14, _, implicit %r0 - ; CHECK: BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 ... --- name: test_select_ptr @@ -1139,14 +1139,14 @@ body: | ; CHECK: [[VREGD:%[0-9]+]]:gpr = COPY [[VREGC]] %4(p0) = G_SELECT %3(s1), %0, %1 - ; CHECK: CMPri [[VREGD]], 0, 14, _, implicit-def %cpsr + ; CHECK: CMPri [[VREGD]], 0, 14, %noreg, implicit-def %cpsr ; CHECK: [[RES:%[0-9]+]]:gpr = MOVCCr [[VREGX]], [[VREGY]], 0, %cpsr %r0 = COPY %4(p0) ; CHECK: %r0 = COPY [[RES]] - BX_RET 14, _, implicit %r0 - ; CHECK: BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 ... --- name: test_br @@ -1170,7 +1170,7 @@ body: | ; CHECK: [[COND:%[0-9]+]]:gpr = COPY [[COND32]] G_BRCOND %1(s1), %bb.1 - ; CHECK: TSTri [[COND]], 1, 14, _, implicit-def %cpsr + ; CHECK: TSTri [[COND]], 1, 14, %noreg, implicit-def %cpsr ; CHECK: Bcc %bb.1, 1, %cpsr G_BR %bb.2 ; CHECK: B %bb.2 @@ -1185,8 +1185,8 @@ body: | bb.2: ; CHECK: bb.2 - BX_RET 14, _ - ; CHECK: BX_RET 14, _ + BX_RET 14, %noreg + ; CHECK: BX_RET 14, %noreg ... --- name: test_soft_fp_double @@ -1223,6 +1223,6 @@ body: | %r1 = COPY %4 ; CHECK: %r1 = COPY [[OUT2]] - BX_RET 14, _, implicit %r0, implicit %r1 - ; CHECK: BX_RET 14, _, implicit %r0, implicit %r1 + BX_RET 14, %noreg, implicit %r0, implicit %r1 + ; CHECK: BX_RET 14, %noreg, implicit %r0, implicit %r1 ... diff --git a/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll b/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll index 0994455916edc..194c627043702 100644 --- a/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll +++ b/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll @@ -3,7 +3,7 @@ define void @test_void_return() { ; CHECK-LABEL: name: test_void_return -; CHECK: BX_RET 14, _ +; CHECK: BX_RET 14, %noreg entry: ret void } @@ -18,7 +18,7 @@ define signext i1 @test_add_i1(i1 %x, i1 %y) { ; CHECK: [[SUM:%[0-9]+]]:_(s1) = G_ADD [[VREGX]], [[VREGY]] ; CHECK: [[EXT:%[0-9]+]]:_(s32) = G_SEXT [[SUM]] ; CHECK: %r0 = COPY [[EXT]](s32) -; CHECK: BX_RET 14, _, implicit %r0 +; CHECK: BX_RET 14, %noreg, implicit %r0 entry: %sum = add i1 %x, %y ret i1 %sum @@ -34,7 +34,7 @@ define i8 @test_add_i8(i8 %x, i8 %y) { ; CHECK: [[SUM:%[0-9]+]]:_(s8) = G_ADD [[VREGX]], [[VREGY]] ; CHECK: [[SUM_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SUM]] ; CHECK: %r0 = COPY [[SUM_EXT]](s32) -; CHECK: BX_RET 14, _, implicit %r0 +; CHECK: BX_RET 14, %noreg, implicit %r0 entry: %sum = add i8 %x, %y ret i8 %sum @@ -50,7 +50,7 @@ define i8 @test_sub_i8(i8 %x, i8 %y) { ; CHECK: [[RES:%[0-9]+]]:_(s8) = G_SUB [[VREGX]], [[VREGY]] ; CHECK: [[RES_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[RES]] ; CHECK: %r0 = COPY [[RES_EXT]](s32) -; CHECK: BX_RET 14, _, implicit %r0 +; CHECK: BX_RET 14, %noreg, implicit %r0 entry: %res = sub i8 %x, %y ret i8 %res @@ -63,7 +63,7 @@ define signext i8 @test_return_sext_i8(i8 %x) { ; CHECK: [[VREG:%[0-9]+]]:_(s8) = G_TRUNC [[VREGR0]] ; CHECK: [[VREGEXT:%[0-9]+]]:_(s32) = G_SEXT [[VREG]] ; CHECK: %r0 = COPY [[VREGEXT]](s32) -; CHECK: BX_RET 14, _, implicit %r0 +; CHECK: BX_RET 14, %noreg, implicit %r0 entry: ret i8 %x } @@ -78,7 +78,7 @@ define i16 @test_add_i16(i16 %x, i16 %y) { ; CHECK: [[SUM:%[0-9]+]]:_(s16) = G_ADD [[VREGX]], [[VREGY]] ; CHECK: [[SUM_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SUM]] ; CHECK: %r0 = COPY [[SUM_EXT]](s32) -; CHECK: BX_RET 14, _, implicit %r0 +; CHECK: BX_RET 14, %noreg, implicit %r0 entry: %sum = add i16 %x, %y ret i16 %sum @@ -94,7 +94,7 @@ define i16 @test_sub_i16(i16 %x, i16 %y) { ; CHECK: [[RES:%[0-9]+]]:_(s16) = G_SUB [[VREGX]], [[VREGY]] ; CHECK: [[RES_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[RES]] ; CHECK: %r0 = COPY [[RES_EXT]](s32) -; CHECK: BX_RET 14, _, implicit %r0 +; CHECK: BX_RET 14, %noreg, implicit %r0 entry: %res = sub i16 %x, %y ret i16 %res @@ -107,7 +107,7 @@ define zeroext i16 @test_return_zext_i16(i16 %x) { ; CHECK: [[VREG:%[0-9]+]]:_(s16) = G_TRUNC [[VREGR0]] ; CHECK: [[VREGEXT:%[0-9]+]]:_(s32) = G_ZEXT [[VREG]] ; CHECK: %r0 = COPY [[VREGEXT]](s32) -; CHECK: BX_RET 14, _, implicit %r0 +; CHECK: BX_RET 14, %noreg, implicit %r0 entry: ret i16 %x } @@ -119,7 +119,7 @@ define i32 @test_add_i32(i32 %x, i32 %y) { ; CHECK-DAG: [[VREGY:%[0-9]+]]:_(s32) = COPY %r1 ; CHECK: [[SUM:%[0-9]+]]:_(s32) = G_ADD [[VREGX]], [[VREGY]] ; CHECK: %r0 = COPY [[SUM]](s32) -; CHECK: BX_RET 14, _, implicit %r0 +; CHECK: BX_RET 14, %noreg, implicit %r0 entry: %sum = add i32 %x, %y ret i32 %sum @@ -132,7 +132,7 @@ define i32 @test_sub_i32(i32 %x, i32 %y) { ; CHECK-DAG: [[VREGY:%[0-9]+]]:_(s32) = COPY %r1 ; CHECK: [[RES:%[0-9]+]]:_(s32) = G_SUB [[VREGX]], [[VREGY]] ; CHECK: %r0 = COPY [[RES]](s32) -; CHECK: BX_RET 14, _, implicit %r0 +; CHECK: BX_RET 14, %noreg, implicit %r0 entry: %res = sub i32 %x, %y ret i32 %res @@ -149,7 +149,7 @@ define i32 @test_stack_args(i32 %p0, i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5 ; CHECK: [[VREGP5:%[0-9]+]]:_(s32) = G_LOAD [[FIP5]]{{.*}}load 4 ; CHECK: [[SUM:%[0-9]+]]:_(s32) = G_ADD [[VREGP2]], [[VREGP5]] ; CHECK: %r0 = COPY [[SUM]] -; CHECK: BX_RET 14, _, implicit %r0 +; CHECK: BX_RET 14, %noreg, implicit %r0 entry: %sum = add i32 %p2, %p5 ret i32 %sum @@ -170,7 +170,7 @@ define i16 @test_stack_args_signext(i32 %p0, i16 %p1, i8 %p2, i1 %p3, ; CHECK: [[SUM:%[0-9]+]]:_(s16) = G_ADD [[VREGP1]], [[VREGP5]] ; CHECK: [[SUM_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SUM]] ; CHECK: %r0 = COPY [[SUM_EXT]](s32) -; CHECK: BX_RET 14, _, implicit %r0 +; CHECK: BX_RET 14, %noreg, implicit %r0 entry: %sum = add i16 %p1, %p5 ret i16 %sum @@ -191,7 +191,7 @@ define i8 @test_stack_args_zeroext(i32 %p0, i16 %p1, i8 %p2, i1 %p3, ; CHECK: [[SUM:%[0-9]+]]:_(s8) = G_ADD [[VREGP2]], [[VREGP4]] ; CHECK: [[SUM_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SUM]] ; CHECK: %r0 = COPY [[SUM_EXT]](s32) -; CHECK: BX_RET 14, _, implicit %r0 +; CHECK: BX_RET 14, %noreg, implicit %r0 entry: %sum = add i8 %p2, %p4 ret i8 %sum @@ -211,7 +211,7 @@ define i8 @test_stack_args_noext(i32 %p0, i16 %p1, i8 %p2, i1 %p3, ; CHECK: [[SUM:%[0-9]+]]:_(s8) = G_ADD [[VREGP2]], [[VREGP4]] ; CHECK: [[SUM_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SUM]] ; CHECK: %r0 = COPY [[SUM_EXT]](s32) -; CHECK: BX_RET 14, _, implicit %r0 +; CHECK: BX_RET 14, %noreg, implicit %r0 entry: %sum = add i8 %p2, %p4 ret i8 %sum @@ -229,7 +229,7 @@ define zeroext i16 @test_stack_args_extend_the_extended(i32 %p0, i16 %p1, i8 %p2 ; CHECK: [[VREGP5:%[0-9]+]]:_(s16) = G_TRUNC [[VREGP5SEXT]] ; CHECK: [[VREGP5ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[VREGP5]] ; CHECK: %r0 = COPY [[VREGP5ZEXT]] -; CHECK: BX_RET 14, _, implicit %r0 +; CHECK: BX_RET 14, %noreg, implicit %r0 entry: ret i16 %p5 } @@ -251,7 +251,7 @@ define i32* @test_ptr_ret(i32** %p) { ; CHECK: [[VREGP:%[0-9]+]]:_(p0) = COPY %r0 ; CHECK: [[VREGV:%[0-9]+]]:_(p0) = G_LOAD [[VREGP]](p0){{.*}}load 4 ; CHECK: %r0 = COPY [[VREGV]] -; CHECK: BX_RET 14, _, implicit %r0 +; CHECK: BX_RET 14, %noreg, implicit %r0 entry: %v = load i32*, i32** %p ret i32* %v @@ -266,7 +266,7 @@ define i32 @test_ptr_arg_on_stack(i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32* %p) { ; CHECK: [[VREGP:%[0-9]+]]:_(p0) = G_LOAD [[FIP]](p0){{.*}}load 4 ; CHECK: [[VREGV:%[0-9]+]]:_(s32) = G_LOAD [[VREGP]](p0){{.*}}load 4 ; CHECK: %r0 = COPY [[VREGV]] -; CHECK: BX_RET 14, _, implicit %r0 +; CHECK: BX_RET 14, %noreg, implicit %r0 entry: %v = load i32, i32* %p ret i32 %v @@ -284,7 +284,7 @@ define arm_aapcscc float @test_float_aapcscc(float %p0, float %p1, float %p2, ; CHECK: [[VREGP5:%[0-9]+]]:_(s32) = G_LOAD [[FIP5]](p0){{.*}}load 4 ; CHECK: [[VREGV:%[0-9]+]]:_(s32) = G_FADD [[VREGP1]], [[VREGP5]] ; CHECK: %r0 = COPY [[VREGV]] -; CHECK: BX_RET 14, _, implicit %r0 +; CHECK: BX_RET 14, %noreg, implicit %r0 entry: %v = fadd float %p1, %p5 ret float %v @@ -313,7 +313,7 @@ define arm_aapcs_vfpcc float @test_float_vfpcc(float %p0, float %p1, float %p2, ; CHECK: [[VREGQ1:%[0-9]+]]:_(s32) = G_LOAD [[FIQ1]](p0){{.*}}load 4 ; CHECK: [[VREGV:%[0-9]+]]:_(s32) = G_FADD [[VREGP1]], [[VREGQ1]] ; CHECK: %s0 = COPY [[VREGV]] -; CHECK: BX_RET 14, _, implicit %s0 +; CHECK: BX_RET 14, %noreg, implicit %s0 entry: %v = fadd float %p1, %q1 ret float %v @@ -334,7 +334,7 @@ define arm_aapcs_vfpcc double @test_double_vfpcc(double %p0, double %p1, double ; CHECK: [[VREGQ1:%[0-9]+]]:_(s64) = G_LOAD [[FIQ1]](p0){{.*}}load 8 ; CHECK: [[VREGV:%[0-9]+]]:_(s64) = G_FADD [[VREGP1]], [[VREGQ1]] ; CHECK: %d0 = COPY [[VREGV]] -; CHECK: BX_RET 14, _, implicit %d0 +; CHECK: BX_RET 14, %noreg, implicit %d0 entry: %v = fadd double %p1, %q1 ret double %v @@ -360,7 +360,7 @@ define arm_aapcscc double @test_double_aapcscc(double %p0, double %p1, double %p ; BIG: [[VREGVHI:%[0-9]+]]:_(s32), [[VREGVLO:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[VREGV]](s64) ; CHECK-DAG: %r0 = COPY [[VREGVLO]] ; CHECK-DAG: %r1 = COPY [[VREGVHI]] -; CHECK: BX_RET 14, _, implicit %r0, implicit %r1 +; CHECK: BX_RET 14, %noreg, implicit %r0, implicit %r1 entry: %v = fadd double %p1, %p5 ret double %v @@ -382,7 +382,7 @@ define arm_aapcs_vfpcc double @test_double_gap_vfpcc(double %p0, float %filler, ; CHECK: [[VREGQ1:%[0-9]+]]:_(s64) = G_LOAD [[FIQ1]](p0){{.*}}load 8 ; CHECK: [[VREGV:%[0-9]+]]:_(s64) = G_FADD [[VREGP1]], [[VREGQ1]] ; CHECK: %d0 = COPY [[VREGV]] -; CHECK: BX_RET 14, _, implicit %d0 +; CHECK: BX_RET 14, %noreg, implicit %d0 entry: %v = fadd double %p1, %q1 ret double %v @@ -405,7 +405,7 @@ define arm_aapcscc double @test_double_gap_aapcscc(float %filler, double %p0, ; BIG: [[VREGVHI:%[0-9]+]]:_(s32), [[VREGVLO:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[VREGV]](s64) ; CHECK-DAG: %r0 = COPY [[VREGVLO]] ; CHECK-DAG: %r1 = COPY [[VREGVHI]] -; CHECK: BX_RET 14, _, implicit %r0, implicit %r1 +; CHECK: BX_RET 14, %noreg, implicit %r0, implicit %r1 entry: %v = fadd double %p0, %p1 ret double %v @@ -428,7 +428,7 @@ define arm_aapcscc double @test_double_gap2_aapcscc(double %p0, float %filler, ; BIG: [[VREGVHI:%[0-9]+]]:_(s32), [[VREGVLO:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[VREGV]](s64) ; CHECK-DAG: %r0 = COPY [[VREGVLO]] ; CHECK-DAG: %r1 = COPY [[VREGVHI]] -; CHECK: BX_RET 14, _, implicit %r0, implicit %r1 +; CHECK: BX_RET 14, %noreg, implicit %r0, implicit %r1 entry: %v = fadd double %p0, %p1 ret double %v diff --git a/test/CodeGen/ARM/GlobalISel/arm-isel.ll b/test/CodeGen/ARM/GlobalISel/arm-isel.ll index 579101e2d2af2..7162815a7f70a 100644 --- a/test/CodeGen/ARM/GlobalISel/arm-isel.ll +++ b/test/CodeGen/ARM/GlobalISel/arm-isel.ll @@ -35,7 +35,7 @@ entry: define zeroext i8 @test_ext_i8(i8 %x) { ; CHECK-LABEL: test_ext_i8: -; CHECK: and r0, r0, #255 +; CHECK: uxtb r0, r0 ; CHECK: bx lr entry: diff --git a/test/CodeGen/ARM/GlobalISel/arm-legalize-divmod.mir b/test/CodeGen/ARM/GlobalISel/arm-legalize-divmod.mir index 6596036ab6937..35afaaadd9419 100644 --- a/test/CodeGen/ARM/GlobalISel/arm-legalize-divmod.mir +++ b/test/CodeGen/ARM/GlobalISel/arm-legalize-divmod.mir @@ -55,7 +55,7 @@ body: | %2(s32) = G_SDIV %0, %1 ; CHECK: %r0 = COPY [[R]] %r0 = COPY %2(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_udiv_i32 @@ -91,7 +91,7 @@ body: | %2(s32) = G_UDIV %0, %1 ; CHECK: %r0 = COPY [[R]] %r0 = COPY %2(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_sdiv_i16 @@ -145,7 +145,7 @@ body: | ; CHECK: %r0 = COPY [[R]] %5(s32) = G_SEXT %4(s16) %r0 = COPY %5(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_udiv_i16 @@ -197,7 +197,7 @@ body: | ; CHECK: %r0 = COPY [[R]] %5(s32) = G_ZEXT %4(s16) %r0 = COPY %5(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_sdiv_i8 @@ -251,7 +251,7 @@ body: | ; CHECK: %r0 = COPY [[R]] %5(s32) = G_SEXT %4(s8) %r0 = COPY %5(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_udiv_i8 @@ -303,7 +303,7 @@ body: | ; CHECK: %r0 = COPY [[R]] %5(s32) = G_ZEXT %4(s8) %r0 = COPY %5(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_srem_i32 @@ -341,7 +341,7 @@ body: | %2(s32) = G_SREM %0, %1 ; CHECK: %r0 = COPY [[R]] %r0 = COPY %2(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_urem_i32 @@ -379,7 +379,7 @@ body: | %2(s32) = G_UREM %0, %1 ; CHECK: %r0 = COPY [[R]] %r0 = COPY %2(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_srem_i16 @@ -435,7 +435,7 @@ body: | ; CHECK: %r0 = COPY [[R]] %5(s32) = G_SEXT %4(s16) %r0 = COPY %5(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_urem_i16 @@ -489,7 +489,7 @@ body: | ; CHECK: %r0 = COPY [[R]] %5(s32) = G_ZEXT %4(s16) %r0 = COPY %5(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_srem_i8 @@ -545,7 +545,7 @@ body: | ; CHECK: %r0 = COPY [[R]] %5(s32) = G_SEXT %4(s8) %r0 = COPY %5(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_urem_i8 @@ -599,5 +599,5 @@ body: | ; CHECK: %r0 = COPY [[R]] %5(s32) = G_ZEXT %4(s8) %r0 = COPY %5(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... diff --git a/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir b/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir index cd02da286d2a1..4f48581fdf348 100644 --- a/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir +++ b/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir @@ -93,7 +93,7 @@ body: | %2(s32) = G_FREM %0, %1 ; CHECK: %r0 = COPY [[R]] %r0 = COPY %2(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_frem_double @@ -151,7 +151,7 @@ body: | %7(s32), %8(s32) = G_UNMERGE_VALUES %6(s64) %r0 = COPY %7(s32) %r1 = COPY %8(s32) - BX_RET 14, _, implicit %r0, implicit %r1 + BX_RET 14, %noreg, implicit %r0, implicit %r1 ... --- name: test_fpow_float @@ -188,7 +188,7 @@ body: | %2(s32) = G_FPOW %0, %1 ; CHECK: %r0 = COPY [[R]] %r0 = COPY %2(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_fpow_double @@ -246,7 +246,7 @@ body: | %7(s32), %8(s32) = G_UNMERGE_VALUES %6(s64) %r0 = COPY %7(s32) %r1 = COPY %8(s32) - BX_RET 14, _, implicit %r0, implicit %r1 + BX_RET 14, %noreg, implicit %r0, implicit %r1 ... --- name: test_fadd_float @@ -281,7 +281,7 @@ body: | %2(s32) = G_FADD %0, %1 ; CHECK: %r0 = COPY [[R]] %r0 = COPY %2(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_fadd_double @@ -333,7 +333,7 @@ body: | %7(s32),%8(s32) = G_UNMERGE_VALUES %6(s64) %r0 = COPY %7(s32) %r1 = COPY %8(s32) - BX_RET 14, _, implicit %r0, implicit %r1 + BX_RET 14, %noreg, implicit %r0, implicit %r1 ... --- name: test_fsub_float @@ -368,7 +368,7 @@ body: | %2(s32) = G_FSUB %0, %1 ; CHECK: %r0 = COPY [[R]] %r0 = COPY %2(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_fsub_double @@ -420,7 +420,7 @@ body: | %7(s32),%8(s32) = G_UNMERGE_VALUES %6(s64) %r0 = COPY %7(s32) %r1 = COPY %8(s32) - BX_RET 14, _, implicit %r0, implicit %r1 + BX_RET 14, %noreg, implicit %r0, implicit %r1 ... --- name: test_fmul_float @@ -455,7 +455,7 @@ body: | %2(s32) = G_FMUL %0, %1 ; CHECK: %r0 = COPY [[R]] %r0 = COPY %2(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_fmul_double @@ -507,7 +507,7 @@ body: | %7(s32),%8(s32) = G_UNMERGE_VALUES %6(s64) %r0 = COPY %7(s32) %r1 = COPY %8(s32) - BX_RET 14, _, implicit %r0, implicit %r1 + BX_RET 14, %noreg, implicit %r0, implicit %r1 ... --- name: test_fdiv_float @@ -542,7 +542,7 @@ body: | %2(s32) = G_FDIV %0, %1 ; CHECK: %r0 = COPY [[R]] %r0 = COPY %2(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_fdiv_double @@ -594,7 +594,7 @@ body: | %7(s32),%8(s32) = G_UNMERGE_VALUES %6(s64) %r0 = COPY %7(s32) %r1 = COPY %8(s32) - BX_RET 14, _, implicit %r0, implicit %r1 + BX_RET 14, %noreg, implicit %r0, implicit %r1 ... --- name: test_fcmp_true_s32 @@ -618,7 +618,7 @@ body: | %2(s1) = G_FCMP floatpred(true), %0(s32), %1 %3(s32) = G_ZEXT %2(s1) %r0 = COPY %3(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ; HARD-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0 ; HARD-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1 ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(true), [[X]](s32), [[Y]] @@ -655,7 +655,7 @@ body: | %2(s1) = G_FCMP floatpred(false), %0(s32), %1 %3(s32) = G_ZEXT %2(s1) %r0 = COPY %3(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ; HARD-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0 ; HARD-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1 ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(false), [[X]](s32), [[Y]] @@ -714,7 +714,7 @@ body: | %3(s32) = G_ZEXT %2(s1) %r0 = COPY %3(s32) ; CHECK: %r0 = COPY [[REXT]] - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_fcmp_ogt_s32 @@ -760,7 +760,7 @@ body: | %3(s32) = G_ZEXT %2(s1) %r0 = COPY %3(s32) ; CHECK: %r0 = COPY [[REXT]] - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_fcmp_oge_s32 @@ -806,7 +806,7 @@ body: | %3(s32) = G_ZEXT %2(s1) %r0 = COPY %3(s32) ; CHECK: %r0 = COPY [[REXT]] - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_fcmp_olt_s32 @@ -852,7 +852,7 @@ body: | %3(s32) = G_ZEXT %2(s1) %r0 = COPY %3(s32) ; CHECK: %r0 = COPY [[REXT]] - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_fcmp_ole_s32 @@ -898,7 +898,7 @@ body: | %3(s32) = G_ZEXT %2(s1) %r0 = COPY %3(s32) ; CHECK: %r0 = COPY [[REXT]] - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_fcmp_ord_s32 @@ -938,7 +938,7 @@ body: | ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) %r0 = COPY %3(s32) ; CHECK: %r0 = COPY [[REXT]] - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_fcmp_ugt_s32 @@ -979,7 +979,7 @@ body: | ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) %r0 = COPY %3(s32) ; CHECK: %r0 = COPY [[REXT]] - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_fcmp_uge_s32 @@ -1020,7 +1020,7 @@ body: | ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) %r0 = COPY %3(s32) ; CHECK: %r0 = COPY [[REXT]] - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_fcmp_ult_s32 @@ -1061,7 +1061,7 @@ body: | ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) %r0 = COPY %3(s32) ; CHECK: %r0 = COPY [[REXT]] - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_fcmp_ule_s32 @@ -1102,7 +1102,7 @@ body: | ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) %r0 = COPY %3(s32) ; CHECK: %r0 = COPY [[REXT]] - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_fcmp_une_s32 @@ -1143,7 +1143,7 @@ body: | ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) %r0 = COPY %3(s32) ; CHECK: %r0 = COPY [[REXT]] - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_fcmp_uno_s32 @@ -1189,7 +1189,7 @@ body: | %3(s32) = G_ZEXT %2(s1) %r0 = COPY %3(s32) ; CHECK: %r0 = COPY [[REXT]] - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_fcmp_one_s32 @@ -1249,7 +1249,7 @@ body: | %3(s32) = G_ZEXT %2(s1) %r0 = COPY %3(s32) ; CHECK: %r0 = COPY [[REXT]] - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_fcmp_ueq_s32 @@ -1309,7 +1309,7 @@ body: | %3(s32) = G_ZEXT %2(s1) %r0 = COPY %3(s32) ; CHECK: %r0 = COPY [[REXT]] - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_fcmp_true_s64 @@ -1358,7 +1358,7 @@ body: | %7(s32) = G_ZEXT %6(s1) %r0 = COPY %7(s32) ; CHECK: %r0 = COPY [[REXT]] - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_fcmp_false_s64 @@ -1408,7 +1408,7 @@ body: | %7(s32) = G_ZEXT %6(s1) %r0 = COPY %7(s32) ; CHECK: %r0 = COPY [[REXT]] - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_fcmp_oeq_s64 @@ -1468,7 +1468,7 @@ body: | %7(s32) = G_ZEXT %6(s1) %r0 = COPY %7(s32) ; CHECK: %r0 = COPY [[REXT]] - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_fcmp_ogt_s64 @@ -1528,7 +1528,7 @@ body: | %7(s32) = G_ZEXT %6(s1) %r0 = COPY %7(s32) ; CHECK: %r0 = COPY [[REXT]] - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_fcmp_oge_s64 @@ -1588,7 +1588,7 @@ body: | %7(s32) = G_ZEXT %6(s1) %r0 = COPY %7(s32) ; CHECK: %r0 = COPY [[REXT]] - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_fcmp_olt_s64 @@ -1648,7 +1648,7 @@ body: | %7(s32) = G_ZEXT %6(s1) %r0 = COPY %7(s32) ; CHECK: %r0 = COPY [[REXT]] - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_fcmp_ole_s64 @@ -1708,7 +1708,7 @@ body: | %7(s32) = G_ZEXT %6(s1) %r0 = COPY %7(s32) ; CHECK: %r0 = COPY [[REXT]] - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_fcmp_ord_s64 @@ -1762,7 +1762,7 @@ body: | ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) %r0 = COPY %7(s32) ; CHECK: %r0 = COPY [[REXT]] - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_fcmp_ugt_s64 @@ -1817,7 +1817,7 @@ body: | ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) %r0 = COPY %7(s32) ; CHECK: %r0 = COPY [[REXT]] - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_fcmp_uge_s64 @@ -1872,7 +1872,7 @@ body: | ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) %r0 = COPY %7(s32) ; CHECK: %r0 = COPY [[REXT]] - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_fcmp_ult_s64 @@ -1927,7 +1927,7 @@ body: | ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) %r0 = COPY %7(s32) ; CHECK: %r0 = COPY [[REXT]] - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_fcmp_ule_s64 @@ -1982,7 +1982,7 @@ body: | ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) %r0 = COPY %7(s32) ; CHECK: %r0 = COPY [[REXT]] - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_fcmp_une_s64 @@ -2037,7 +2037,7 @@ body: | ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) %r0 = COPY %7(s32) ; CHECK: %r0 = COPY [[REXT]] - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_fcmp_uno_s64 @@ -2097,7 +2097,7 @@ body: | %7(s32) = G_ZEXT %6(s1) %r0 = COPY %7(s32) ; CHECK: %r0 = COPY [[REXT]] - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_fcmp_one_s64 @@ -2173,7 +2173,7 @@ body: | %7(s32) = G_ZEXT %6(s1) %r0 = COPY %7(s32) ; CHECK: %r0 = COPY [[REXT]] - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_fcmp_ueq_s64 @@ -2249,5 +2249,5 @@ body: | %7(s32) = G_ZEXT %6(s1) %r0 = COPY %7(s32) ; CHECK: %r0 = COPY [[REXT]] - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... diff --git a/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir b/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir index 816c042a6d5b1..e3e206cf76e9b 100644 --- a/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir +++ b/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir @@ -74,7 +74,7 @@ body: | ; G_SEXT with s8 is legal, so we should find it unchanged in the output ; CHECK: {{%[0-9]+}}:_(s32) = G_SEXT {{%[0-9]+}} %r0 = COPY %2(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_zext_s16 @@ -98,7 +98,7 @@ body: | ; G_ZEXT with s16 is legal, so we should find it unchanged in the output ; CHECK: {{%[0-9]+}}:_(s32) = G_ZEXT {{%[0-9]+}} %r0 = COPY %2(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_add_s8 @@ -130,7 +130,7 @@ body: | ; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_ADD {{%[0-9]+, %[0-9]+}} %5(s32) = G_SEXT %4(s8) %r0 = COPY %5(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_add_s16 @@ -162,7 +162,7 @@ body: | ; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_ADD {{%[0-9]+, %[0-9]+}} %5(s32) = G_SEXT %4(s16) %r0 = COPY %5(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_add_s32 @@ -186,7 +186,7 @@ body: | ; G_ADD with s32 is legal, so we should find it unchanged in the output ; CHECK: {{%[0-9]+}}:_(s32) = G_ADD {{%[0-9]+, %[0-9]+}} %r0 = COPY %2(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- @@ -219,7 +219,7 @@ body: | ; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_SUB {{%[0-9]+, %[0-9]+}} %5(s32) = G_SEXT %4(s8) %r0 = COPY %5(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_sub_s16 @@ -251,7 +251,7 @@ body: | ; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_SUB {{%[0-9]+, %[0-9]+}} %5(s32) = G_SEXT %4(s16) %r0 = COPY %5(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_sub_s32 @@ -275,7 +275,7 @@ body: | ; G_SUB with s32 is legal, so we should find it unchanged in the output ; CHECK: {{%[0-9]+}}:_(s32) = G_SUB {{%[0-9]+, %[0-9]+}} %r0 = COPY %2(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- @@ -308,7 +308,7 @@ body: | ; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_MUL {{%[0-9]+, %[0-9]+}} %5(s32) = G_SEXT %4(s8) %r0 = COPY %5(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_mul_s16 @@ -340,7 +340,7 @@ body: | ; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_MUL {{%[0-9]+, %[0-9]+}} %5(s32) = G_SEXT %4(s16) %r0 = COPY %5(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_mul_s32 @@ -364,7 +364,7 @@ body: | ; G_MUL with s32 is legal, so we should find it unchanged in the output ; CHECK: {{%[0-9]+}}:_(s32) = G_MUL {{%[0-9]+, %[0-9]+}} %r0 = COPY %2(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- @@ -397,7 +397,7 @@ body: | ; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_AND {{%[0-9]+, %[0-9]+}} %5(s32) = G_SEXT %4(s8) %r0 = COPY %5(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_and_s16 @@ -429,7 +429,7 @@ body: | ; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_AND {{%[0-9]+, %[0-9]+}} %5(s32) = G_SEXT %4(s16) %r0 = COPY %5(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_and_s32 @@ -453,7 +453,7 @@ body: | ; G_AND with s32 is legal, so we should find it unchanged in the output ; CHECK: {{%[0-9]+}}:_(s32) = G_AND {{%[0-9]+, %[0-9]+}} %r0 = COPY %2(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- @@ -486,7 +486,7 @@ body: | ; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_OR {{%[0-9]+, %[0-9]+}} %5(s32) = G_SEXT %4(s8) %r0 = COPY %5(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_or_s16 @@ -518,7 +518,7 @@ body: | ; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_OR {{%[0-9]+, %[0-9]+}} %5(s32) = G_SEXT %4(s16) %r0 = COPY %5(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_or_s32 @@ -542,7 +542,7 @@ body: | ; G_OR with s32 is legal, so we should find it unchanged in the output ; CHECK: {{%[0-9]+}}:_(s32) = G_OR {{%[0-9]+, %[0-9]+}} %r0 = COPY %2(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- @@ -575,7 +575,7 @@ body: | ; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_XOR {{%[0-9]+, %[0-9]+}} %5(s32) = G_SEXT %4(s8) %r0 = COPY %5(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_xor_s16 @@ -607,7 +607,7 @@ body: | ; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_XOR {{%[0-9]+, %[0-9]+}} %5(s32) = G_SEXT %4(s16) %r0 = COPY %5(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_xor_s32 @@ -631,7 +631,7 @@ body: | ; G_XOR with s32 is legal, so we should find it unchanged in the output ; CHECK: {{%[0-9]+}}:_(s32) = G_XOR {{%[0-9]+, %[0-9]+}} %r0 = COPY %2(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- @@ -656,7 +656,7 @@ body: | ; G_LSHR with s32 is legal, so we should find it unchanged in the output ; CHECK: {{%[0-9]+}}:_(s32) = G_LSHR {{%[0-9]+, %[0-9]+}} %r0 = COPY %2(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- @@ -681,7 +681,7 @@ body: | ; G_ASHR with s32 is legal, so we should find it unchanged in the output ; CHECK: {{%[0-9]+}}:_(s32) = G_ASHR {{%[0-9]+, %[0-9]+}} %r0 = COPY %2(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- @@ -706,7 +706,7 @@ body: | ; G_SHL with s32 is legal, so we should find it unchanged in the output ; CHECK: {{%[0-9]+}}:_(s32) = G_SHL {{%[0-9]+, %[0-9]+}} %r0 = COPY %2(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- @@ -737,7 +737,7 @@ body: | %0(p0) = G_FRAME_INDEX %fixed-stack.2 %1(s32) = G_LOAD %0(p0) :: (load 4) %r0 = COPY %1(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_legal_loads_stores @@ -785,7 +785,7 @@ body: | G_STORE %5(s1), %0(p0) :: (store 1) %6(p0) = G_LOAD %0(p0) :: (load 4) G_STORE %6(p0), %0(p0) :: (store 4) - BX_RET 14, _ + BX_RET 14, %noreg ... --- name: test_gep @@ -810,7 +810,7 @@ body: | %2(p0) = G_GEP %0, %1(s32) %r0 = COPY %2(p0) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_constants @@ -857,7 +857,7 @@ body: | ; CHECK-NOT: G_CONSTANT i1 %r0 = COPY %0(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_icmp_s8 @@ -888,7 +888,7 @@ body: | ; CHECK-NOT: {{%[0-9]+}}:_(s1) = G_ICMP intpred(ne), {{%[0-9]+}}(s8), {{%[0-9]+}} %5(s32) = G_ZEXT %4(s1) %r0 = COPY %5(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_icmp_s16 @@ -919,7 +919,7 @@ body: | ; CHECK-NOT: {{%[0-9]+}}:_(s1) = G_ICMP intpred(slt), {{%[0-9]+}}(s16), {{%[0-9]+}} %5(s32) = G_ZEXT %4(s1) %r0 = COPY %5(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_icmp_s32 @@ -945,7 +945,7 @@ body: | ; CHECK: {{%[0-9]+}}:_(s1) = G_ICMP intpred(eq), {{%[0-9]+}}(s32), {{%[0-9]+}} %3(s32) = G_ZEXT %2(s1) %r0 = COPY %3(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_select_s32 @@ -971,7 +971,7 @@ body: | ; G_SELECT with s32 is legal, so we should find it unchanged in the output ; CHECK: {{%[0-9]+}}:_(s32) = G_SELECT {{%[0-9]+}}(s1), {{%[0-9]+}}, {{%[0-9]+}} %r0 = COPY %3(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_select_ptr @@ -997,7 +997,7 @@ body: | ; G_SELECT with p0 is legal, so we should find it unchanged in the output ; CHECK: {{%[0-9]+}}:_(p0) = G_SELECT {{%[0-9]+}}(s1), {{%[0-9]+}}, {{%[0-9]+}} %r0 = COPY %3(p0) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_brcond @@ -1026,11 +1026,11 @@ body: | bb.1: %r0 = COPY %1(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 bb.2: %r0 = COPY %0(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- @@ -1053,6 +1053,6 @@ body: | ; G_GLOBAL_VALUE is legal, so we should find it unchanged in the output ; CHECK: {{%[0-9]+}}:_(p0) = G_GLOBAL_VALUE @a_global %r0 = COPY %1(p0) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... diff --git a/test/CodeGen/ARM/GlobalISel/arm-param-lowering.ll b/test/CodeGen/ARM/GlobalISel/arm-param-lowering.ll index 92c4e2905d88a..fd48428739892 100644 --- a/test/CodeGen/ARM/GlobalISel/arm-param-lowering.ll +++ b/test/CodeGen/ARM/GlobalISel/arm-param-lowering.ll @@ -7,14 +7,14 @@ define arm_aapcscc i32* @test_call_simple_reg_params(i32 *%a, i32 %b) { ; CHECK-LABEL: name: test_call_simple_reg_params ; CHECK-DAG: [[AVREG:%[0-9]+]]:_(p0) = COPY %r0 ; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s32) = COPY %r1 -; CHECK: ADJCALLSTACKDOWN 0, 0, 14, _, implicit-def %sp, implicit %sp +; CHECK: ADJCALLSTACKDOWN 0, 0, 14, %noreg, implicit-def %sp, implicit %sp ; CHECK-DAG: %r0 = COPY [[BVREG]] ; CHECK-DAG: %r1 = COPY [[AVREG]] ; CHECK: BL @simple_reg_params_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit-def %r0 ; CHECK: [[RVREG:%[0-9]+]]:_(p0) = COPY %r0 -; CHECK: ADJCALLSTACKUP 0, 0, 14, _, implicit-def %sp, implicit %sp +; CHECK: ADJCALLSTACKUP 0, 0, 14, %noreg, implicit-def %sp, implicit %sp ; CHECK: %r0 = COPY [[RVREG]] -; CHECK: BX_RET 14, _, implicit %r0 +; CHECK: BX_RET 14, %noreg, implicit %r0 entry: %r = notail call arm_aapcscc i32 *@simple_reg_params_target(i32 %b, i32 *%a) ret i32 *%r @@ -26,7 +26,7 @@ define arm_aapcscc i32* @test_call_simple_stack_params(i32 *%a, i32 %b) { ; CHECK-LABEL: name: test_call_simple_stack_params ; CHECK-DAG: [[AVREG:%[0-9]+]]:_(p0) = COPY %r0 ; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s32) = COPY %r1 -; CHECK: ADJCALLSTACKDOWN 8, 0, 14, _, implicit-def %sp, implicit %sp +; CHECK: ADJCALLSTACKDOWN 8, 0, 14, %noreg, implicit-def %sp, implicit %sp ; CHECK-DAG: %r0 = COPY [[BVREG]] ; CHECK-DAG: %r1 = COPY [[AVREG]] ; CHECK-DAG: %r2 = COPY [[BVREG]] @@ -41,9 +41,9 @@ define arm_aapcscc i32* @test_call_simple_stack_params(i32 *%a, i32 %b) { ; CHECK: G_STORE [[AVREG]](p0), [[FI2]](p0){{.*}}store 4 ; CHECK: BL @simple_stack_params_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 ; CHECK: [[RVREG:%[0-9]+]]:_(p0) = COPY %r0 -; CHECK: ADJCALLSTACKUP 8, 0, 14, _, implicit-def %sp, implicit %sp +; CHECK: ADJCALLSTACKUP 8, 0, 14, %noreg, implicit-def %sp, implicit %sp ; CHECK: %r0 = COPY [[RVREG]] -; CHECK: BX_RET 14, _, implicit %r0 +; CHECK: BX_RET 14, %noreg, implicit %r0 entry: %r = notail call arm_aapcscc i32 *@simple_stack_params_target(i32 %b, i32 *%a, i32 %b, i32 *%a, i32 %b, i32 *%a) ret i32 *%r @@ -59,7 +59,7 @@ define arm_aapcscc signext i16 @test_call_ext_params(i8 %a, i16 %b, i1 %c) { ; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s16) = G_TRUNC [[R1VREG]] ; CHECK-DAG: [[R2VREG:%[0-9]+]]:_(s32) = COPY %r2 ; CHECK-DAG: [[CVREG:%[0-9]+]]:_(s1) = G_TRUNC [[R2VREG]] -; CHECK: ADJCALLSTACKDOWN 20, 0, 14, _, implicit-def %sp, implicit %sp +; CHECK: ADJCALLSTACKDOWN 20, 0, 14, %noreg, implicit-def %sp, implicit %sp ; CHECK: [[SEXTA:%[0-9]+]]:_(s32) = G_SEXT [[AVREG]](s8) ; CHECK: %r0 = COPY [[SEXTA]] ; CHECK: [[ZEXTA:%[0-9]+]]:_(s32) = G_ZEXT [[AVREG]](s8) @@ -96,10 +96,10 @@ define arm_aapcscc signext i16 @test_call_ext_params(i8 %a, i16 %b, i1 %c) { ; CHECK: BL @ext_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 ; CHECK: [[R0VREG:%[0-9]+]]:_(s32) = COPY %r0 ; CHECK: [[RVREG:%[0-9]+]]:_(s16) = G_TRUNC [[R0VREG]] -; CHECK: ADJCALLSTACKUP 20, 0, 14, _, implicit-def %sp, implicit %sp +; CHECK: ADJCALLSTACKUP 20, 0, 14, %noreg, implicit-def %sp, implicit %sp ; CHECK: [[RExtVREG:%[0-9]+]]:_(s32) = G_SEXT [[RVREG]] ; CHECK: %r0 = COPY [[RExtVREG]] -; CHECK: BX_RET 14, _, implicit %r0 +; CHECK: BX_RET 14, %noreg, implicit %r0 entry: %r = notail call arm_aapcscc signext i16 @ext_target(i8 signext %a, i8 zeroext %a, i16 signext %b, i16 zeroext %b, i8 signext %a, i8 zeroext %a, i16 signext %b, i16 zeroext %b, i1 zeroext %c) ret i16 %r @@ -111,14 +111,14 @@ define arm_aapcs_vfpcc double @test_call_vfpcc_fp_params(double %a, float %b) { ; CHECK-LABEL: name: test_call_vfpcc_fp_params ; CHECK-DAG: [[AVREG:%[0-9]+]]:_(s64) = COPY %d0 ; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s32) = COPY %s2 -; CHECK: ADJCALLSTACKDOWN 0, 0, 14, _, implicit-def %sp, implicit %sp +; CHECK: ADJCALLSTACKDOWN 0, 0, 14, %noreg, implicit-def %sp, implicit %sp ; CHECK-DAG: %s0 = COPY [[BVREG]] ; CHECK-DAG: %d1 = COPY [[AVREG]] ; CHECK: BL @vfpcc_fp_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %s0, implicit %d1, implicit-def %d0 ; CHECK: [[RVREG:%[0-9]+]]:_(s64) = COPY %d0 -; CHECK: ADJCALLSTACKUP 0, 0, 14, _, implicit-def %sp, implicit %sp +; CHECK: ADJCALLSTACKUP 0, 0, 14, %noreg, implicit-def %sp, implicit %sp ; CHECK: %d0 = COPY [[RVREG]] -; CHECK: BX_RET 14, _, implicit %d0 +; CHECK: BX_RET 14, %noreg, implicit %d0 entry: %r = notail call arm_aapcs_vfpcc double @vfpcc_fp_target(float %b, double %a) ret double %r @@ -133,7 +133,7 @@ define arm_aapcscc double @test_call_aapcs_fp_params(double %a, float %b) { ; LITTLE-DAG: [[AVREG:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[A1]](s32), [[A2]](s32) ; BIG-DAG: [[AVREG:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[A2]](s32), [[A1]](s32) ; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s32) = COPY %r2 -; CHECK: ADJCALLSTACKDOWN 16, 0, 14, _, implicit-def %sp, implicit %sp +; CHECK: ADJCALLSTACKDOWN 16, 0, 14, %noreg, implicit-def %sp, implicit %sp ; CHECK-DAG: %r0 = COPY [[BVREG]] ; CHECK-DAG: [[A1:%[0-9]+]]:_(s32), [[A2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AVREG]](s64) ; LITTLE-DAG: %r2 = COPY [[A1]] @@ -153,13 +153,13 @@ define arm_aapcscc double @test_call_aapcs_fp_params(double %a, float %b) { ; CHECK-DAG: [[R2:%[0-9]+]]:_(s32) = COPY %r1 ; LITTLE: [[RVREG:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[R1]](s32), [[R2]](s32) ; BIG: [[RVREG:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[R2]](s32), [[R1]](s32) -; CHECK: ADJCALLSTACKUP 16, 0, 14, _, implicit-def %sp, implicit %sp +; CHECK: ADJCALLSTACKUP 16, 0, 14, %noreg, implicit-def %sp, implicit %sp ; CHECK: [[R1:%[0-9]+]]:_(s32), [[R2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[RVREG]](s64) ; LITTLE-DAG: %r0 = COPY [[R1]] ; LITTLE-DAG: %r1 = COPY [[R2]] ; BIG-DAG: %r0 = COPY [[R2]] ; BIG-DAG: %r1 = COPY [[R1]] -; CHECK: BX_RET 14, _, implicit %r0, implicit %r1 +; CHECK: BX_RET 14, %noreg, implicit %r0, implicit %r1 entry: %r = notail call arm_aapcscc double @aapcscc_fp_target(float %b, double %a, float %b, double %a) ret double %r @@ -170,13 +170,13 @@ declare arm_aapcscc float @different_call_conv_target(float) define arm_aapcs_vfpcc float @test_call_different_call_conv(float %x) { ; CHECK-LABEL: name: test_call_different_call_conv ; CHECK: [[X:%[0-9]+]]:_(s32) = COPY %s0 -; CHECK: ADJCALLSTACKDOWN 0, 0, 14, _, implicit-def %sp, implicit %sp +; CHECK: ADJCALLSTACKDOWN 0, 0, 14, %noreg, implicit-def %sp, implicit %sp ; CHECK: %r0 = COPY [[X]] ; CHECK: BL @different_call_conv_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit-def %r0 ; CHECK: [[R:%[0-9]+]]:_(s32) = COPY %r0 -; CHECK: ADJCALLSTACKUP 0, 0, 14, _, implicit-def %sp, implicit %sp +; CHECK: ADJCALLSTACKUP 0, 0, 14, %noreg, implicit-def %sp, implicit %sp ; CHECK: %s0 = COPY [[R]] -; CHECK: BX_RET 14, _, implicit %s0 +; CHECK: BX_RET 14, %noreg, implicit %s0 entry: %r = notail call arm_aapcscc float @different_call_conv_target(float %x) ret float %r @@ -190,7 +190,7 @@ define arm_aapcscc [3 x i32] @test_tiny_int_arrays([2 x i32] %arr) { ; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY %r0 ; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY %r1 ; CHECK: [[ARG_ARR:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32) -; CHECK: ADJCALLSTACKDOWN 0, 0, 14, _, implicit-def %sp, implicit %sp +; CHECK: ADJCALLSTACKDOWN 0, 0, 14, %noreg, implicit-def %sp, implicit %sp ; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ARG_ARR]](s64) ; CHECK: %r0 = COPY [[R0]] ; CHECK: %r1 = COPY [[R1]] @@ -199,7 +199,7 @@ define arm_aapcscc [3 x i32] @test_tiny_int_arrays([2 x i32] %arr) { ; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY %r1 ; CHECK: [[R2:%[0-9]+]]:_(s32) = COPY %r2 ; CHECK: [[RES_ARR:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32), [[R2]](s32) -; CHECK: ADJCALLSTACKUP 0, 0, 14, _, implicit-def %sp, implicit %sp +; CHECK: ADJCALLSTACKUP 0, 0, 14, %noreg, implicit-def %sp, implicit %sp ; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32), [[R2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[RES_ARR]](s96) ; FIXME: This doesn't seem correct with regard to the AAPCS docs (which say ; that composite types larger than 4 bytes should be passed through memory), @@ -207,7 +207,7 @@ define arm_aapcscc [3 x i32] @test_tiny_int_arrays([2 x i32] %arr) { ; CHECK: %r0 = COPY [[R0]] ; CHECK: %r1 = COPY [[R1]] ; CHECK: %r2 = COPY [[R2]] -; CHECK: BX_RET 14, _, implicit %r0, implicit %r1, implicit %r2 +; CHECK: BX_RET 14, %noreg, implicit %r0, implicit %r1, implicit %r2 entry: %r = notail call arm_aapcscc [3 x i32] @tiny_int_arrays_target([2 x i32] %arr) ret [3 x i32] %r @@ -224,7 +224,7 @@ define arm_aapcscc void @test_multiple_int_arrays([2 x i32] %arr0, [2 x i32] %ar ; CHECK: [[R3:%[0-9]+]]:_(s32) = COPY %r3 ; CHECK: [[ARG_ARR0:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32) ; CHECK: [[ARG_ARR1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[R2]](s32), [[R3]](s32) -; CHECK: ADJCALLSTACKDOWN 0, 0, 14, _, implicit-def %sp, implicit %sp +; CHECK: ADJCALLSTACKDOWN 0, 0, 14, %noreg, implicit-def %sp, implicit %sp ; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ARG_ARR0]](s64) ; CHECK: [[R2:%[0-9]+]]:_(s32), [[R3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ARG_ARR1]](s64) ; CHECK: %r0 = COPY [[R0]] @@ -232,8 +232,8 @@ define arm_aapcscc void @test_multiple_int_arrays([2 x i32] %arr0, [2 x i32] %ar ; CHECK: %r2 = COPY [[R2]] ; CHECK: %r3 = COPY [[R3]] ; CHECK: BL @multiple_int_arrays_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit %r3 -; CHECK: ADJCALLSTACKUP 0, 0, 14, _, implicit-def %sp, implicit %sp -; CHECK: BX_RET 14, _ +; CHECK: ADJCALLSTACKUP 0, 0, 14, %noreg, implicit-def %sp, implicit %sp +; CHECK: BX_RET 14, %noreg entry: notail call arm_aapcscc void @multiple_int_arrays_target([2 x i32] %arr0, [2 x i32] %arr1) ret void @@ -258,7 +258,7 @@ define arm_aapcscc void @test_large_int_arrays([20 x i32] %arr) { ; CHECK: [[LAST_STACK_ELEMENT_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[LAST_STACK_ID]] ; CHECK: [[LAST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_LOAD [[LAST_STACK_ELEMENT_FI]]{{.*}}load 4 from %fixed-stack.[[LAST_STACK_ID]] ; CHECK: [[ARG_ARR:%[0-9]+]]:_(s640) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32), [[R2]](s32), [[R3]](s32), [[FIRST_STACK_ELEMENT]](s32), {{.*}}, [[LAST_STACK_ELEMENT]](s32) -; CHECK: ADJCALLSTACKDOWN 64, 0, 14, _, implicit-def %sp, implicit %sp +; CHECK: ADJCALLSTACKDOWN 64, 0, 14, %noreg, implicit-def %sp, implicit %sp ; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32), [[R2:%[0-9]+]]:_(s32), [[R3:%[0-9]+]]:_(s32), [[FIRST_STACK_ELEMENT:%[0-9]+]]:_(s32), {{.*}}, [[LAST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ARG_ARR]](s640) ; CHECK: %r0 = COPY [[R0]] ; CHECK: %r1 = COPY [[R1]] @@ -275,8 +275,8 @@ define arm_aapcscc void @test_large_int_arrays([20 x i32] %arr) { ; CHECK: [[LAST_STACK_ARG_ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[OFF_LAST_ELEMENT]](s32) ; CHECK: G_STORE [[LAST_STACK_ELEMENT]](s32), [[LAST_STACK_ARG_ADDR]]{{.*}}store 4 ; CHECK: BL @large_int_arrays_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit %r3 -; CHECK: ADJCALLSTACKUP 64, 0, 14, _, implicit-def %sp, implicit %sp -; CHECK: BX_RET 14, _ +; CHECK: ADJCALLSTACKUP 64, 0, 14, %noreg, implicit-def %sp, implicit %sp +; CHECK: BX_RET 14, %noreg entry: notail call arm_aapcscc void @large_int_arrays_target([20 x i32] %arr) ret void @@ -300,7 +300,7 @@ define arm_aapcscc [2 x float] @test_fp_arrays_aapcs([3 x double] %arr) { ; CHECK: [[ARR2_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[ARR2_ID]] ; CHECK: [[ARR2:%[0-9]+]]:_(s64) = G_LOAD [[ARR2_FI]]{{.*}}load 8 from %fixed-stack.[[ARR2_ID]] ; CHECK: [[ARR_MERGED:%[0-9]+]]:_(s192) = G_MERGE_VALUES [[ARR0]](s64), [[ARR1]](s64), [[ARR2]](s64) -; CHECK: ADJCALLSTACKDOWN 8, 0, 14, _, implicit-def %sp, implicit %sp +; CHECK: ADJCALLSTACKDOWN 8, 0, 14, %noreg, implicit-def %sp, implicit %sp ; CHECK: [[ARR0:%[0-9]+]]:_(s64), [[ARR1:%[0-9]+]]:_(s64), [[ARR2:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[ARR_MERGED]](s192) ; CHECK: [[ARR0_0:%[0-9]+]]:_(s32), [[ARR0_1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ARR0]](s64) ; LITTLE: %r0 = COPY [[ARR0_0]](s32) @@ -320,11 +320,11 @@ define arm_aapcscc [2 x float] @test_fp_arrays_aapcs([3 x double] %arr) { ; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY %r0 ; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY %r1 ; CHECK: [[R_MERGED:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32) -; CHECK: ADJCALLSTACKUP 8, 0, 14, _, implicit-def %sp, implicit %sp +; CHECK: ADJCALLSTACKUP 8, 0, 14, %noreg, implicit-def %sp, implicit %sp ; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[R_MERGED]](s64) ; CHECK: %r0 = COPY [[R0]] ; CHECK: %r1 = COPY [[R1]] -; CHECK: BX_RET 14, _, implicit %r0, implicit %r1 +; CHECK: BX_RET 14, %noreg, implicit %r0, implicit %r1 entry: %r = notail call arm_aapcscc [2 x float] @fp_arrays_aapcs_target([3 x double] %arr) ret [2 x float] %r @@ -357,7 +357,7 @@ define arm_aapcs_vfpcc [4 x float] @test_fp_arrays_aapcs_vfp([3 x double] %x, [3 ; CHECK: [[X_ARR:%[0-9]+]]:_(s192) = G_MERGE_VALUES [[X0]](s64), [[X1]](s64), [[X2]](s64) ; CHECK: [[Y_ARR:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32), [[Y2]](s32) ; CHECK: [[Z_ARR:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[Z0]](s64), [[Z1]](s64), [[Z2]](s64), [[Z3]](s64) -; CHECK: ADJCALLSTACKDOWN 32, 0, 14, _, implicit-def %sp, implicit %sp +; CHECK: ADJCALLSTACKDOWN 32, 0, 14, %noreg, implicit-def %sp, implicit %sp ; CHECK: [[X0:%[0-9]+]]:_(s64), [[X1:%[0-9]+]]:_(s64), [[X2:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[X_ARR]](s192) ; CHECK: [[Y0:%[0-9]+]]:_(s32), [[Y1:%[0-9]+]]:_(s32), [[Y2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[Y_ARR]](s96) ; CHECK: [[Z0:%[0-9]+]]:_(s64), [[Z1:%[0-9]+]]:_(s64), [[Z2:%[0-9]+]]:_(s64), [[Z3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[Z_ARR]](s256) @@ -389,13 +389,13 @@ define arm_aapcs_vfpcc [4 x float] @test_fp_arrays_aapcs_vfp([3 x double] %x, [3 ; CHECK: [[R2:%[0-9]+]]:_(s32) = COPY %s2 ; CHECK: [[R3:%[0-9]+]]:_(s32) = COPY %s3 ; CHECK: [[R_MERGED:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32), [[R2]](s32), [[R3]](s32) -; CHECK: ADJCALLSTACKUP 32, 0, 14, _, implicit-def %sp, implicit %sp +; CHECK: ADJCALLSTACKUP 32, 0, 14, %noreg, implicit-def %sp, implicit %sp ; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32), [[R2:%[0-9]+]]:_(s32), [[R3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[R_MERGED]](s128) ; CHECK: %s0 = COPY [[R0]] ; CHECK: %s1 = COPY [[R1]] ; CHECK: %s2 = COPY [[R2]] ; CHECK: %s3 = COPY [[R3]] -; CHECK: BX_RET 14, _, implicit %s0, implicit %s1, implicit %s2, implicit %s3 +; CHECK: BX_RET 14, %noreg, implicit %s0, implicit %s1, implicit %s2, implicit %s3 entry: %r = notail call arm_aapcs_vfpcc [4 x float] @fp_arrays_aapcs_vfp_target([3 x double] %x, [3 x float] %y, [4 x double] %z) ret [4 x float] %r @@ -420,7 +420,7 @@ define arm_aapcscc [2 x i32*] @test_tough_arrays([6 x [4 x i32]] %arr) { ; CHECK: [[LAST_STACK_ELEMENT_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[LAST_STACK_ID]] ; CHECK: [[LAST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_LOAD [[LAST_STACK_ELEMENT_FI]]{{.*}}load 4 from %fixed-stack.[[LAST_STACK_ID]] ; CHECK: [[ARG_ARR:%[0-9]+]]:_(s768) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32), [[R2]](s32), [[R3]](s32), [[FIRST_STACK_ELEMENT]](s32), {{.*}}, [[LAST_STACK_ELEMENT]](s32) -; CHECK: ADJCALLSTACKDOWN 80, 0, 14, _, implicit-def %sp, implicit %sp +; CHECK: ADJCALLSTACKDOWN 80, 0, 14, %noreg, implicit-def %sp, implicit %sp ; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32), [[R2:%[0-9]+]]:_(s32), [[R3:%[0-9]+]]:_(s32), [[FIRST_STACK_ELEMENT:%[0-9]+]]:_(s32), {{.*}}, [[LAST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ARG_ARR]](s768) ; CHECK: %r0 = COPY [[R0]] ; CHECK: %r1 = COPY [[R1]] @@ -440,11 +440,11 @@ define arm_aapcscc [2 x i32*] @test_tough_arrays([6 x [4 x i32]] %arr) { ; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY %r0 ; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY %r1 ; CHECK: [[RES_ARR:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32) -; CHECK: ADJCALLSTACKUP 80, 0, 14, _, implicit-def %sp, implicit %sp +; CHECK: ADJCALLSTACKUP 80, 0, 14, %noreg, implicit-def %sp, implicit %sp ; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[RES_ARR]](s64) ; CHECK: %r0 = COPY [[R0]] ; CHECK: %r1 = COPY [[R1]] -; CHECK: BX_RET 14, _, implicit %r0, implicit %r1 +; CHECK: BX_RET 14, %noreg, implicit %r0, implicit %r1 entry: %r = notail call arm_aapcscc [2 x i32*] @tough_arrays_target([6 x [4 x i32]] %arr) ret [2 x i32*] %r @@ -458,7 +458,7 @@ define arm_aapcscc {i32, i32} @test_structs({i32, i32} %x) { ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0 ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1 ; CHECK: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32) -; CHECK: ADJCALLSTACKDOWN 0, 0, 14, _, implicit-def %sp, implicit %sp +; CHECK: ADJCALLSTACKDOWN 0, 0, 14, %noreg, implicit-def %sp, implicit %sp ; CHECK: [[X0:%[0-9]+]]:_(s32), [[X1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[X]](s64) ; CHECK-DAG: %r0 = COPY [[X0]](s32) ; CHECK-DAG: %r1 = COPY [[X1]](s32) @@ -466,11 +466,11 @@ define arm_aapcscc {i32, i32} @test_structs({i32, i32} %x) { ; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY %r0 ; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY %r1 ; CHECK: [[R:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32) -; CHECK: ADJCALLSTACKUP 0, 0, 14, _, implicit-def %sp, implicit %sp +; CHECK: ADJCALLSTACKUP 0, 0, 14, %noreg, implicit-def %sp, implicit %sp ; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[R]](s64) ; CHECK: %r0 = COPY [[R0]](s32) ; CHECK: %r1 = COPY [[R1]](s32) -; CHECK: BX_RET 14, _, implicit %r0, implicit %r1 +; CHECK: BX_RET 14, %noreg, implicit %r0, implicit %r1 %r = notail call arm_aapcscc {i32, i32} @structs_target({i32, i32} %x) ret {i32, i32} %r } diff --git a/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir b/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir index 986f4a5ae4898..044740e33a2d7 100644 --- a/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir +++ b/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir @@ -80,7 +80,7 @@ body: | %1(s32) = COPY %r1 %2(s32) = G_ADD %0, %1 %r0 = COPY %2(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- @@ -106,7 +106,7 @@ body: | %1(s32) = COPY %r1 %2(s32) = G_SUB %0, %1 %r0 = COPY %2(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- @@ -132,7 +132,7 @@ body: | %1(s32) = COPY %r1 %2(s32) = G_MUL %0, %1 %r0 = COPY %2(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- @@ -158,7 +158,7 @@ body: | %1(s32) = COPY %r1 %2(s32) = G_SDIV %0, %1 %r0 = COPY %2(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- @@ -184,7 +184,7 @@ body: | %1(s32) = COPY %r1 %2(s32) = G_UDIV %0, %1 %r0 = COPY %2(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- @@ -210,7 +210,7 @@ body: | %1(s32) = COPY %r1 %2(s32) = G_AND %0, %1 %r0 = COPY %2(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- @@ -236,7 +236,7 @@ body: | %1(s32) = COPY %r1 %2(s32) = G_OR %0, %1 %r0 = COPY %2(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- @@ -262,7 +262,7 @@ body: | %1(s32) = COPY %r1 %2(s32) = G_XOR %0, %1 %r0 = COPY %2(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- @@ -288,7 +288,7 @@ body: | %1(s32) = COPY %r1 %2(s32) = G_LSHR %0, %1 %r0 = COPY %2(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- @@ -314,7 +314,7 @@ body: | %1(s32) = COPY %r1 %2(s32) = G_ASHR %0, %1 %r0 = COPY %2(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- @@ -340,7 +340,7 @@ body: | %1(s32) = COPY %r1 %2(s32) = G_SHL %0, %1 %r0 = COPY %2(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- @@ -376,7 +376,7 @@ body: | %3(s8) = G_LOAD %0 :: (load 1) %4(s1) = G_LOAD %0 :: (load 1) %5(p0) = G_LOAD %0 :: (load 4) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- @@ -418,7 +418,7 @@ body: | G_STORE %5(p0), %0 :: (store 4) %6(s64) = COPY %d6 G_STORE %6(s64), %0 :: (store 8) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- @@ -451,7 +451,7 @@ body: | %4(p0) = G_GEP %2, %3(s32) G_STORE %1(s32), %4(p0) :: (store 4) - BX_RET 14, _ + BX_RET 14, %noreg ... --- @@ -477,7 +477,7 @@ body: | %1(s32) = COPY %r1 %2(p0) = G_GEP %0, %1(s32) %r0 = COPY %2(p0) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_constants @@ -493,7 +493,7 @@ body: | bb.0: %0(s32) = G_CONSTANT 42 %r0 = COPY %0(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_globals @@ -509,7 +509,7 @@ body: | bb.0: %0(p0) = G_GLOBAL_VALUE @a_global %r0 = COPY %0(p0) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_anyext_s8_32 @@ -533,7 +533,7 @@ body: | %1(s8) = G_TRUNC %0(s32) %2(s32) = G_ANYEXT %1(s8) %r0 = COPY %2(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_anyext_s16_32 @@ -557,7 +557,7 @@ body: | %1(s16) = G_TRUNC %0(s32) %2(s32) = G_ANYEXT %1(s16) %r0 = COPY %2(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- name: test_trunc_s32_16 @@ -581,7 +581,7 @@ body: | %2(p0) = COPY %r1 %1(s16) = G_TRUNC %0(s32) G_STORE %1(s16), %2 :: (store 2) - BX_RET 14, _ + BX_RET 14, %noreg ... --- name: test_icmp_eq_s32 @@ -609,7 +609,7 @@ body: | %2(s1) = G_ICMP intpred(eq), %0(s32), %1 %3(s32) = G_ZEXT %2(s1) %r0 = COPY %3(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- @@ -638,7 +638,7 @@ body: | %2(s1) = G_FCMP floatpred(one), %0(s32), %1 %3(s32) = G_ZEXT %2(s1) %r0 = COPY %3(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- @@ -667,7 +667,7 @@ body: | %2(s1) = G_FCMP floatpred(ugt), %0(s64), %1 %3(s32) = G_ZEXT %2(s1) %r0 = COPY %3(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- @@ -699,7 +699,7 @@ body: | %3(s1) = G_TRUNC %2(s32) %4(s32) = G_SELECT %3(s1), %0, %1 %r0 = COPY %4(s32) - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... --- @@ -727,10 +727,10 @@ body: | G_BR %bb.2 bb.1: - BX_RET 14, _ + BX_RET 14, %noreg bb.2: - BX_RET 14, _ + BX_RET 14, %noreg ... --- @@ -756,7 +756,7 @@ body: | %1(s32) = COPY %s1 %2(s32) = G_FADD %0, %1 %s0 = COPY %2(s32) - BX_RET 14, _, implicit %s0 + BX_RET 14, %noreg, implicit %s0 ... --- @@ -782,7 +782,7 @@ body: | %1(s64) = COPY %d1 %2(s64) = G_FADD %0, %1 %d0 = COPY %2(s64) - BX_RET 14, _, implicit %d0 + BX_RET 14, %noreg, implicit %d0 ... --- @@ -808,7 +808,7 @@ body: | %1(s32) = COPY %s1 %2(s32) = G_FSUB %0, %1 %s0 = COPY %2(s32) - BX_RET 14, _, implicit %s0 + BX_RET 14, %noreg, implicit %s0 ... --- @@ -834,7 +834,7 @@ body: | %1(s64) = COPY %d1 %2(s64) = G_FSUB %0, %1 %d0 = COPY %2(s64) - BX_RET 14, _, implicit %d0 + BX_RET 14, %noreg, implicit %d0 ... --- @@ -860,7 +860,7 @@ body: | %1(s32) = COPY %s1 %2(s32) = G_FMUL %0, %1 %s0 = COPY %2(s32) - BX_RET 14, _, implicit %s0 + BX_RET 14, %noreg, implicit %s0 ... --- @@ -886,7 +886,7 @@ body: | %1(s64) = COPY %d1 %2(s64) = G_FMUL %0, %1 %d0 = COPY %2(s64) - BX_RET 14, _, implicit %d0 + BX_RET 14, %noreg, implicit %d0 ... --- @@ -912,7 +912,7 @@ body: | %1(s32) = COPY %s1 %2(s32) = G_FDIV %0, %1 %s0 = COPY %2(s32) - BX_RET 14, _, implicit %s0 + BX_RET 14, %noreg, implicit %s0 ... --- @@ -938,7 +938,7 @@ body: | %1(s64) = COPY %d1 %2(s64) = G_FDIV %0, %1 %d0 = COPY %2(s64) - BX_RET 14, _, implicit %d0 + BX_RET 14, %noreg, implicit %d0 ... --- @@ -970,6 +970,6 @@ body: | %3(s32), %4(s32) = G_UNMERGE_VALUES %2(s64) %r0 = COPY %3(s32) %r1 = COPY %4(s32) - BX_RET 14, _, implicit %r0, implicit %r1 + BX_RET 14, %noreg, implicit %r0, implicit %r1 ... diff --git a/test/CodeGen/ARM/GlobalISel/arm-select-globals-pic.mir b/test/CodeGen/ARM/GlobalISel/arm-select-globals-pic.mir index 448a7f86e8895..99697983192f6 100644 --- a/test/CodeGen/ARM/GlobalISel/arm-select-globals-pic.mir +++ b/test/CodeGen/ARM/GlobalISel/arm-select-globals-pic.mir @@ -33,13 +33,13 @@ body: | ; ELF: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel {{.*}}@internal_global %1(s32) = G_LOAD %0(p0) :: (load 4 from @internal_global) - ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, _ :: (load 4 from @internal_global) + ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, %noreg :: (load 4 from @internal_global) %r0 = COPY %1(s32) ; CHECK: %r0 = COPY [[V]] - BX_RET 14, _, implicit %r0 - ; CHECK: BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 ... --- name: test_external_global @@ -59,13 +59,13 @@ body: | ; ELF: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel_ldr target-flags() @external_global :: (load 4 from got) %1(s32) = G_LOAD %0(p0) :: (load 4 from @external_global) - ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, _ :: (load 4 from @external_global) + ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, %noreg :: (load 4 from @external_global) %r0 = COPY %1(s32) ; CHECK: %r0 = COPY [[V]] - BX_RET 14, _, implicit %r0 - ; CHECK: BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 ... --- name: test_internal_constant @@ -85,13 +85,13 @@ body: | ; ELF: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel {{.*}}@internal_constant %1(s32) = G_LOAD %0(p0) :: (load 4 from @internal_constant) - ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, _ :: (load 4 from @internal_constant) + ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, %noreg :: (load 4 from @internal_constant) %r0 = COPY %1(s32) ; CHECK: %r0 = COPY [[V]] - BX_RET 14, _, implicit %r0 - ; CHECK: BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 ... --- name: test_external_constant @@ -111,11 +111,11 @@ body: | ; ELF: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel_ldr target-flags() @external_constant :: (load 4 from got) %1(s32) = G_LOAD %0(p0) :: (load 4 from @external_constant) - ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, _ :: (load 4 from @external_constant) + ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, %noreg :: (load 4 from @external_constant) %r0 = COPY %1(s32) ; CHECK: %r0 = COPY [[V]] - BX_RET 14, _, implicit %r0 - ; CHECK: BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 ... diff --git a/test/CodeGen/ARM/GlobalISel/arm-select-globals-ropi-rwpi.mir b/test/CodeGen/ARM/GlobalISel/arm-select-globals-ropi-rwpi.mir index e80700317e004..dc48dee00c884 100644 --- a/test/CodeGen/ARM/GlobalISel/arm-select-globals-ropi-rwpi.mir +++ b/test/CodeGen/ARM/GlobalISel/arm-select-globals-ropi-rwpi.mir @@ -37,19 +37,19 @@ body: | bb.0: %0(p0) = G_GLOBAL_VALUE @internal_global ; RW-DEFAULT-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @internal_global - ; RW-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, _ :: (load 4 from constant-pool) + ; RW-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, %noreg :: (load 4 from constant-pool) ; RWPI-MOVT: [[OFF:%[0-9]+]]:gpr = MOVi32imm {{.*}} @internal_global - ; RWPI-NOMOVT: [[OFF:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, _ :: (load 4 from constant-pool) - ; RWPI: [[G:%[0-9]+]]:gpr = ADDrr %r9, [[OFF]], 14, _, _ + ; RWPI-NOMOVT: [[OFF:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, %noreg :: (load 4 from constant-pool) + ; RWPI: [[G:%[0-9]+]]:gpr = ADDrr %r9, [[OFF]], 14, %noreg, %noreg %1(s32) = G_LOAD %0(p0) :: (load 4 from @internal_global) - ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, _ :: (load 4 from @internal_global) + ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, %noreg :: (load 4 from @internal_global) %r0 = COPY %1(s32) ; CHECK: %r0 = COPY [[V]] - BX_RET 14, _, implicit %r0 - ; CHECK: BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 ... --- name: test_external_global @@ -71,19 +71,19 @@ body: | bb.0: %0(p0) = G_GLOBAL_VALUE @external_global ; RW-DEFAULT-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @external_global - ; RW-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, _ :: (load 4 from constant-pool) + ; RW-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, %noreg :: (load 4 from constant-pool) ; RWPI-MOVT: [[OFF:%[0-9]+]]:gpr = MOVi32imm {{.*}} @external_global - ; RWPI-NOMOVT: [[OFF:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, _ :: (load 4 from constant-pool) - ; RWPI: [[G:%[0-9]+]]:gpr = ADDrr %r9, [[OFF]], 14, _, _ + ; RWPI-NOMOVT: [[OFF:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, %noreg :: (load 4 from constant-pool) + ; RWPI: [[G:%[0-9]+]]:gpr = ADDrr %r9, [[OFF]], 14, %noreg, %noreg %1(s32) = G_LOAD %0(p0) :: (load 4 from @external_global) - ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, _ :: (load 4 from @external_global) + ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, %noreg :: (load 4 from @external_global) %r0 = COPY %1(s32) ; CHECK: %r0 = COPY [[V]] - BX_RET 14, _, implicit %r0 - ; CHECK: BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 ... --- name: test_internal_constant @@ -104,16 +104,16 @@ body: | ; ROPI-MOVT: [[G:%[0-9]+]]:gpr = MOV_ga_pcrel @internal_constant ; ROPI-NOMOVT: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel @internal_constant ; RO-DEFAULT-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @internal_constant - ; RO-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, _ :: (load 4 from constant-pool) + ; RO-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, %noreg :: (load 4 from constant-pool) %1(s32) = G_LOAD %0(p0) :: (load 4 from @internal_constant) - ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, _ :: (load 4 from @internal_constant) + ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, %noreg :: (load 4 from @internal_constant) %r0 = COPY %1(s32) ; CHECK: %r0 = COPY [[V]] - BX_RET 14, _, implicit %r0 - ; CHECK: BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 ... --- name: test_external_constant @@ -134,14 +134,14 @@ body: | ; ROPI-MOVT: [[G:%[0-9]+]]:gpr = MOV_ga_pcrel @external_constant ; ROPI-NOMOVT: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel @external_constant ; RO-DEFAULT-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @external_constant - ; RO-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, _ :: (load 4 from constant-pool) + ; RO-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, %noreg :: (load 4 from constant-pool) %1(s32) = G_LOAD %0(p0) :: (load 4 from @external_constant) - ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, _ :: (load 4 from @external_constant) + ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, %noreg :: (load 4 from @external_constant) %r0 = COPY %1(s32) ; CHECK: %r0 = COPY [[V]] - BX_RET 14, _, implicit %r0 - ; CHECK: BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 ... diff --git a/test/CodeGen/ARM/GlobalISel/arm-select-globals-static.mir b/test/CodeGen/ARM/GlobalISel/arm-select-globals-static.mir index 034b88296dc12..cd03d42e4a54e 100644 --- a/test/CodeGen/ARM/GlobalISel/arm-select-globals-static.mir +++ b/test/CodeGen/ARM/GlobalISel/arm-select-globals-static.mir @@ -26,18 +26,18 @@ body: | bb.0: %0(p0) = G_GLOBAL_VALUE @internal_global ; ELF-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @internal_global - ; ELF-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, _ :: (load 4 from constant-pool) + ; ELF-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, %noreg :: (load 4 from constant-pool) ; DARWIN-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @internal_global ; DARWIN-NOMOVT: [[G:%[0-9]+]]:gpr = LDRLIT_ga_abs @internal_global %1(s32) = G_LOAD %0(p0) :: (load 4 from @internal_global) - ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, _ + ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, %noreg %r0 = COPY %1(s32) ; CHECK: %r0 = COPY [[V]] - BX_RET 14, _, implicit %r0 - ; CHECK: BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 ... --- name: test_external_global @@ -56,16 +56,16 @@ body: | bb.0: %0(p0) = G_GLOBAL_VALUE @external_global ; ELF-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @external_global - ; ELF-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, _ :: (load 4 from constant-pool) + ; ELF-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, %noreg :: (load 4 from constant-pool) ; DARWIN-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @external_global ; DARWIN-NOMOVT: [[G:%[0-9]+]]:gpr = LDRLIT_ga_abs @external_global %1(s32) = G_LOAD %0(p0) :: (load 4 from @external_global) - ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, _ + ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, %noreg %r0 = COPY %1(s32) ; CHECK: %r0 = COPY [[V]] - BX_RET 14, _, implicit %r0 - ; CHECK: BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 + ; CHECK: BX_RET 14, %noreg, implicit %r0 ... diff --git a/test/CodeGen/ARM/GlobalISel/arm-unsupported.ll b/test/CodeGen/ARM/GlobalISel/arm-unsupported.ll index bdba535639056..f9d41d9a38f02 100644 --- a/test/CodeGen/ARM/GlobalISel/arm-unsupported.ll +++ b/test/CodeGen/ARM/GlobalISel/arm-unsupported.ll @@ -113,4 +113,19 @@ define i32 @test_thread_local_global() { ret i32 %v } +%byval.class = type { i32 } + +define void @test_byval_arg(%byval.class* byval %x) { +; CHECK: remark: {{.*}} unable to lower arguments: void (%byval.class*)* +; CHECK-LABEL: warning: Instruction selection used fallback path for test_byval + ret void +} + +define void @test_byval_param(%byval.class* %x) { +; CHECK: remark: {{.*}} unable to translate instruction: call +; CHECK-LABEL: warning: Instruction selection used fallback path for test_byval_param + call void @test_byval_arg(%byval.class* byval %x) + ret void +} + attributes #0 = { "target-features"="+thumb-mode" } diff --git a/test/CodeGen/ARM/Windows/dbzchk.ll b/test/CodeGen/ARM/Windows/dbzchk.ll index aea37992de4e6..18e6e52805792 100644 --- a/test/CodeGen/ARM/Windows/dbzchk.ll +++ b/test/CodeGen/ARM/Windows/dbzchk.ll @@ -32,13 +32,13 @@ return: ret i32 %2 } -; CHECK-DIV-DAG: BB#0 -; CHECK-DIV-DAG: Successors according to CFG: BB#1({{.*}}) BB#2 -; CHECK-DIV-DAG: BB#1 -; CHECK-DIV-DAG: Successors according to CFG: BB#3 -; CHECK-DIV-DAG: BB#2 -; CHECK-DIV-DAG: Successors according to CFG: BB#3 -; CHECK-DIV-DAG: BB#3 +; CHECK-DIV-DAG: %bb.0 +; CHECK-DIV-DAG: Successors according to CFG: %bb.1({{.*}}) %bb.2 +; CHECK-DIV-DAG: %bb.1 +; CHECK-DIV-DAG: Successors according to CFG: %bb.3 +; CHECK-DIV-DAG: %bb.2 +; CHECK-DIV-DAG: Successors according to CFG: %bb.3 +; CHECK-DIV-DAG: %bb.3 ; RUN: llc -mtriple thumbv7--windows-itanium -print-machineinstrs=expand-isel-pseudos -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck %s -check-prefix CHECK-MOD @@ -66,13 +66,13 @@ return: ret i32 %retval.0 } -; CHECK-MOD-DAG: BB#0 -; CHECK-MOD-DAG: Successors according to CFG: BB#2({{.*}}) BB#1 -; CHECK-MOD-DAG: BB#1 -; CHECK-MOD-DAG: Successors according to CFG: BB#3 -; CHECK-MOD-DAG: BB#3 -; CHECK-MOD-DAG: Successors according to CFG: BB#2 -; CHECK-MOD-DAG: BB#2 +; CHECK-MOD-DAG: %bb.0 +; CHECK-MOD-DAG: Successors according to CFG: %bb.2({{.*}}) %bb.1 +; CHECK-MOD-DAG: %bb.1 +; CHECK-MOD-DAG: Successors according to CFG: %bb.3 +; CHECK-MOD-DAG: %bb.3 +; CHECK-MOD-DAG: Successors according to CFG: %bb.2 +; CHECK-MOD-DAG: %bb.2 ; RUN: llc -mtriple thumbv7--windows-itanium -print-machineinstrs=expand-isel-pseudos -verify-machineinstrs -filetype asm -o /dev/null %s 2>&1 | FileCheck %s -check-prefix CHECK-CFG ; RUN: llc -mtriple thumbv7--windows-itanium -verify-machineinstrs -filetype asm -o - %s | FileCheck %s -check-prefix CHECK-CFG-ASM @@ -111,23 +111,23 @@ if.end: attributes #0 = { optsize } -; CHECK-CFG-DAG: BB#0 -; CHECK-CFG-DAG: t2Bcc -; CHECK-CFG-DAG: t2B +; CHECK-CFG-DAG: %bb.0 +; CHECK-CFG-DAG: t2Bcc %bb.2 +; CHECK-CFG-DAG: t2B %bb.1 -; CHECK-CFG-DAG: BB#1 -; CHECK-CFG-DAG: t2B +; CHECK-CFG-DAG: %bb.1 +; CHECK-CFG-DAG: t2B %bb.3 -; CHECK-CFG-DAG: BB#2 -; CHECK-CFG-DAG: tCMPi8 %vreg{{[0-9]}}, 0 -; CHECK-CFG-DAG: t2Bcc +; CHECK-CFG-DAG: %bb.2 +; CHECK-CFG-DAG: tCMPi8 %{{[0-9]}}, 0 +; CHECK-CFG-DAG: t2Bcc %bb.5 -; CHECK-CFG-DAG: BB#4 +; CHECK-CFG-DAG: %bb.4 -; CHECK-CFG-DAG: BB#3 +; CHECK-CFG-DAG: %bb.3 ; CHECK-CFG-DAG: tBX_RET -; CHECK-CFG-DAG: BB#5 +; CHECK-CFG-DAG: %bb.5 ; CHECK-CFG-DAG: t__brkdiv0 ; CHECK-CFG-ASM-LABEL: h: diff --git a/test/CodeGen/ARM/a15-SD-dep.ll b/test/CodeGen/ARM/a15-SD-dep.ll index 5e5ca4b873f38..625c40eb41629 100644 --- a/test/CodeGen/ARM/a15-SD-dep.ll +++ b/test/CodeGen/ARM/a15-SD-dep.ll @@ -114,4 +114,4 @@ sw.bb1: ; preds = %entry, %sw.bb sw.epilog: ; preds = %entry, %sw.bb1 ret void -} \ No newline at end of file +} diff --git a/test/CodeGen/ARM/and-load-combine.ll b/test/CodeGen/ARM/and-load-combine.ll new file mode 100644 index 0000000000000..6f0c12359597c --- /dev/null +++ b/test/CodeGen/ARM/and-load-combine.ll @@ -0,0 +1,966 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=armv7 %s -o - | FileCheck %s --check-prefix=ARM +; RUN: llc -mtriple=armv7eb %s -o - | FileCheck %s --check-prefix=ARMEB +; RUN: llc -mtriple=armv6m %s -o - | FileCheck %s --check-prefix=THUMB1 +; RUN: llc -mtriple=thumbv8m.main %s -o - | FileCheck %s --check-prefix=THUMB2 + +define arm_aapcscc zeroext i1 @cmp_xor8_short_short(i16* nocapture readonly %a, +; ARM-LABEL: cmp_xor8_short_short: +; ARM: @ %bb.0: @ %entry +; ARM-NEXT: ldrh r0, [r0] +; ARM-NEXT: ldrh r1, [r1] +; ARM-NEXT: eor r1, r1, r0 +; ARM-NEXT: mov r0, #0 +; ARM-NEXT: tst r1, #255 +; ARM-NEXT: movweq r0, #1 +; ARM-NEXT: bx lr +; +; ARMEB-LABEL: cmp_xor8_short_short: +; ARMEB: @ %bb.0: @ %entry +; ARMEB-NEXT: ldrh r0, [r0] +; ARMEB-NEXT: ldrh r1, [r1] +; ARMEB-NEXT: eor r1, r1, r0 +; ARMEB-NEXT: mov r0, #0 +; ARMEB-NEXT: tst r1, #255 +; ARMEB-NEXT: movweq r0, #1 +; ARMEB-NEXT: bx lr +; +; THUMB1-LABEL: cmp_xor8_short_short: +; THUMB1: @ %bb.0: @ %entry +; THUMB1-NEXT: ldrh r0, [r0] +; THUMB1-NEXT: ldrh r2, [r1] +; THUMB1-NEXT: eors r2, r0 +; THUMB1-NEXT: movs r0, #1 +; THUMB1-NEXT: movs r1, #0 +; THUMB1-NEXT: lsls r2, r2, #24 +; THUMB1-NEXT: beq .LBB0_2 +; THUMB1-NEXT: @ %bb.1: @ %entry +; THUMB1-NEXT: mov r0, r1 +; THUMB1-NEXT: .LBB0_2: @ %entry +; THUMB1-NEXT: bx lr +; +; THUMB2-LABEL: cmp_xor8_short_short: +; THUMB2: @ %bb.0: @ %entry +; THUMB2-NEXT: ldrh r0, [r0] +; THUMB2-NEXT: ldrh r1, [r1] +; THUMB2-NEXT: eors r0, r1 +; THUMB2-NEXT: lsls r0, r0, #24 +; THUMB2-NEXT: mov.w r0, #0 +; THUMB2-NEXT: it eq +; THUMB2-NEXT: moveq r0, #1 +; THUMB2-NEXT: bx lr + i16* nocapture readonly %b) { +entry: + %0 = load i16, i16* %a, align 2 + %1 = load i16, i16* %b, align 2 + %xor2 = xor i16 %1, %0 + %2 = and i16 %xor2, 255 + %cmp = icmp eq i16 %2, 0 + ret i1 %cmp +} + +define arm_aapcscc zeroext i1 @cmp_xor8_short_int(i16* nocapture readonly %a, +; ARM-LABEL: cmp_xor8_short_int: +; ARM: @ %bb.0: @ %entry +; ARM-NEXT: ldrh r0, [r0] +; ARM-NEXT: ldr r1, [r1] +; ARM-NEXT: eor r1, r1, r0 +; ARM-NEXT: mov r0, #0 +; ARM-NEXT: tst r1, #255 +; ARM-NEXT: movweq r0, #1 +; ARM-NEXT: bx lr +; +; ARMEB-LABEL: cmp_xor8_short_int: +; ARMEB: @ %bb.0: @ %entry +; ARMEB-NEXT: ldrh r0, [r0] +; ARMEB-NEXT: ldr r1, [r1] +; ARMEB-NEXT: eor r1, r1, r0 +; ARMEB-NEXT: mov r0, #0 +; ARMEB-NEXT: tst r1, #255 +; ARMEB-NEXT: movweq r0, #1 +; ARMEB-NEXT: bx lr +; +; THUMB1-LABEL: cmp_xor8_short_int: +; THUMB1: @ %bb.0: @ %entry +; THUMB1-NEXT: ldrh r0, [r0] +; THUMB1-NEXT: ldr r2, [r1] +; THUMB1-NEXT: eors r2, r0 +; THUMB1-NEXT: movs r0, #1 +; THUMB1-NEXT: movs r1, #0 +; THUMB1-NEXT: lsls r2, r2, #24 +; THUMB1-NEXT: beq .LBB1_2 +; THUMB1-NEXT: @ %bb.1: @ %entry +; THUMB1-NEXT: mov r0, r1 +; THUMB1-NEXT: .LBB1_2: @ %entry +; THUMB1-NEXT: bx lr +; +; THUMB2-LABEL: cmp_xor8_short_int: +; THUMB2: @ %bb.0: @ %entry +; THUMB2-NEXT: ldrh r0, [r0] +; THUMB2-NEXT: ldr r1, [r1] +; THUMB2-NEXT: eors r0, r1 +; THUMB2-NEXT: lsls r0, r0, #24 +; THUMB2-NEXT: mov.w r0, #0 +; THUMB2-NEXT: it eq +; THUMB2-NEXT: moveq r0, #1 +; THUMB2-NEXT: bx lr + i32* nocapture readonly %b) { +entry: + %0 = load i16, i16* %a, align 2 + %conv = zext i16 %0 to i32 + %1 = load i32, i32* %b, align 4 + %xor = xor i32 %1, %conv + %and = and i32 %xor, 255 + %cmp = icmp eq i32 %and, 0 + ret i1 %cmp +} + +define arm_aapcscc zeroext i1 @cmp_xor8_int_int(i32* nocapture readonly %a, +; ARM-LABEL: cmp_xor8_int_int: +; ARM: @ %bb.0: @ %entry +; ARM-NEXT: ldr r0, [r0] +; ARM-NEXT: ldr r1, [r1] +; ARM-NEXT: eor r1, r1, r0 +; ARM-NEXT: mov r0, #0 +; ARM-NEXT: tst r1, #255 +; ARM-NEXT: movweq r0, #1 +; ARM-NEXT: bx lr +; +; ARMEB-LABEL: cmp_xor8_int_int: +; ARMEB: @ %bb.0: @ %entry +; ARMEB-NEXT: ldr r0, [r0] +; ARMEB-NEXT: ldr r1, [r1] +; ARMEB-NEXT: eor r1, r1, r0 +; ARMEB-NEXT: mov r0, #0 +; ARMEB-NEXT: tst r1, #255 +; ARMEB-NEXT: movweq r0, #1 +; ARMEB-NEXT: bx lr +; +; THUMB1-LABEL: cmp_xor8_int_int: +; THUMB1: @ %bb.0: @ %entry +; THUMB1-NEXT: ldr r0, [r0] +; THUMB1-NEXT: ldr r2, [r1] +; THUMB1-NEXT: eors r2, r0 +; THUMB1-NEXT: movs r0, #1 +; THUMB1-NEXT: movs r1, #0 +; THUMB1-NEXT: lsls r2, r2, #24 +; THUMB1-NEXT: beq .LBB2_2 +; THUMB1-NEXT: @ %bb.1: @ %entry +; THUMB1-NEXT: mov r0, r1 +; THUMB1-NEXT: .LBB2_2: @ %entry +; THUMB1-NEXT: bx lr +; +; THUMB2-LABEL: cmp_xor8_int_int: +; THUMB2: @ %bb.0: @ %entry +; THUMB2-NEXT: ldr r0, [r0] +; THUMB2-NEXT: ldr r1, [r1] +; THUMB2-NEXT: eors r0, r1 +; THUMB2-NEXT: lsls r0, r0, #24 +; THUMB2-NEXT: mov.w r0, #0 +; THUMB2-NEXT: it eq +; THUMB2-NEXT: moveq r0, #1 +; THUMB2-NEXT: bx lr + i32* nocapture readonly %b) { +entry: + %0 = load i32, i32* %a, align 4 + %1 = load i32, i32* %b, align 4 + %xor = xor i32 %1, %0 + %and = and i32 %xor, 255 + %cmp = icmp eq i32 %and, 0 + ret i1 %cmp +} + +define arm_aapcscc zeroext i1 @cmp_xor16(i32* nocapture readonly %a, +; ARM-LABEL: cmp_xor16: +; ARM: @ %bb.0: @ %entry +; ARM-NEXT: ldr r0, [r0] +; ARM-NEXT: movw r2, #65535 +; ARM-NEXT: ldr r1, [r1] +; ARM-NEXT: eor r1, r1, r0 +; ARM-NEXT: mov r0, #0 +; ARM-NEXT: tst r1, r2 +; ARM-NEXT: movweq r0, #1 +; ARM-NEXT: bx lr +; +; ARMEB-LABEL: cmp_xor16: +; ARMEB: @ %bb.0: @ %entry +; ARMEB-NEXT: ldr r0, [r0] +; ARMEB-NEXT: movw r2, #65535 +; ARMEB-NEXT: ldr r1, [r1] +; ARMEB-NEXT: eor r1, r1, r0 +; ARMEB-NEXT: mov r0, #0 +; ARMEB-NEXT: tst r1, r2 +; ARMEB-NEXT: movweq r0, #1 +; ARMEB-NEXT: bx lr +; +; THUMB1-LABEL: cmp_xor16: +; THUMB1: @ %bb.0: @ %entry +; THUMB1-NEXT: ldr r0, [r0] +; THUMB1-NEXT: ldr r2, [r1] +; THUMB1-NEXT: eors r2, r0 +; THUMB1-NEXT: movs r0, #1 +; THUMB1-NEXT: movs r1, #0 +; THUMB1-NEXT: lsls r2, r2, #16 +; THUMB1-NEXT: beq .LBB3_2 +; THUMB1-NEXT: @ %bb.1: @ %entry +; THUMB1-NEXT: mov r0, r1 +; THUMB1-NEXT: .LBB3_2: @ %entry +; THUMB1-NEXT: bx lr +; +; THUMB2-LABEL: cmp_xor16: +; THUMB2: @ %bb.0: @ %entry +; THUMB2-NEXT: ldr r0, [r0] +; THUMB2-NEXT: ldr r1, [r1] +; THUMB2-NEXT: eors r0, r1 +; THUMB2-NEXT: lsls r0, r0, #16 +; THUMB2-NEXT: mov.w r0, #0 +; THUMB2-NEXT: it eq +; THUMB2-NEXT: moveq r0, #1 +; THUMB2-NEXT: bx lr + i32* nocapture readonly %b) { +entry: + %0 = load i32, i32* %a, align 4 + %1 = load i32, i32* %b, align 4 + %xor = xor i32 %1, %0 + %and = and i32 %xor, 65535 + %cmp = icmp eq i32 %and, 0 + ret i1 %cmp +} + +define arm_aapcscc zeroext i1 @cmp_or8_short_short(i16* nocapture readonly %a, +; ARM-LABEL: cmp_or8_short_short: +; ARM: @ %bb.0: @ %entry +; ARM-NEXT: ldrh r0, [r0] +; ARM-NEXT: ldrh r1, [r1] +; ARM-NEXT: orr r1, r1, r0 +; ARM-NEXT: mov r0, #0 +; ARM-NEXT: tst r1, #255 +; ARM-NEXT: movweq r0, #1 +; ARM-NEXT: bx lr +; +; ARMEB-LABEL: cmp_or8_short_short: +; ARMEB: @ %bb.0: @ %entry +; ARMEB-NEXT: ldrh r0, [r0] +; ARMEB-NEXT: ldrh r1, [r1] +; ARMEB-NEXT: orr r1, r1, r0 +; ARMEB-NEXT: mov r0, #0 +; ARMEB-NEXT: tst r1, #255 +; ARMEB-NEXT: movweq r0, #1 +; ARMEB-NEXT: bx lr +; +; THUMB1-LABEL: cmp_or8_short_short: +; THUMB1: @ %bb.0: @ %entry +; THUMB1-NEXT: ldrh r0, [r0] +; THUMB1-NEXT: ldrh r2, [r1] +; THUMB1-NEXT: orrs r2, r0 +; THUMB1-NEXT: movs r0, #1 +; THUMB1-NEXT: movs r1, #0 +; THUMB1-NEXT: lsls r2, r2, #24 +; THUMB1-NEXT: beq .LBB4_2 +; THUMB1-NEXT: @ %bb.1: @ %entry +; THUMB1-NEXT: mov r0, r1 +; THUMB1-NEXT: .LBB4_2: @ %entry +; THUMB1-NEXT: bx lr +; +; THUMB2-LABEL: cmp_or8_short_short: +; THUMB2: @ %bb.0: @ %entry +; THUMB2-NEXT: ldrh r0, [r0] +; THUMB2-NEXT: ldrh r1, [r1] +; THUMB2-NEXT: orrs r0, r1 +; THUMB2-NEXT: lsls r0, r0, #24 +; THUMB2-NEXT: mov.w r0, #0 +; THUMB2-NEXT: it eq +; THUMB2-NEXT: moveq r0, #1 +; THUMB2-NEXT: bx lr + i16* nocapture readonly %b) { +entry: + %0 = load i16, i16* %a, align 2 + %1 = load i16, i16* %b, align 2 + %or2 = or i16 %1, %0 + %2 = and i16 %or2, 255 + %cmp = icmp eq i16 %2, 0 + ret i1 %cmp +} + +define arm_aapcscc zeroext i1 @cmp_or8_short_int(i16* nocapture readonly %a, +; ARM-LABEL: cmp_or8_short_int: +; ARM: @ %bb.0: @ %entry +; ARM-NEXT: ldrh r0, [r0] +; ARM-NEXT: ldr r1, [r1] +; ARM-NEXT: orr r1, r1, r0 +; ARM-NEXT: mov r0, #0 +; ARM-NEXT: tst r1, #255 +; ARM-NEXT: movweq r0, #1 +; ARM-NEXT: bx lr +; +; ARMEB-LABEL: cmp_or8_short_int: +; ARMEB: @ %bb.0: @ %entry +; ARMEB-NEXT: ldrh r0, [r0] +; ARMEB-NEXT: ldr r1, [r1] +; ARMEB-NEXT: orr r1, r1, r0 +; ARMEB-NEXT: mov r0, #0 +; ARMEB-NEXT: tst r1, #255 +; ARMEB-NEXT: movweq r0, #1 +; ARMEB-NEXT: bx lr +; +; THUMB1-LABEL: cmp_or8_short_int: +; THUMB1: @ %bb.0: @ %entry +; THUMB1-NEXT: ldrh r0, [r0] +; THUMB1-NEXT: ldr r2, [r1] +; THUMB1-NEXT: orrs r2, r0 +; THUMB1-NEXT: movs r0, #1 +; THUMB1-NEXT: movs r1, #0 +; THUMB1-NEXT: lsls r2, r2, #24 +; THUMB1-NEXT: beq .LBB5_2 +; THUMB1-NEXT: @ %bb.1: @ %entry +; THUMB1-NEXT: mov r0, r1 +; THUMB1-NEXT: .LBB5_2: @ %entry +; THUMB1-NEXT: bx lr +; +; THUMB2-LABEL: cmp_or8_short_int: +; THUMB2: @ %bb.0: @ %entry +; THUMB2-NEXT: ldrh r0, [r0] +; THUMB2-NEXT: ldr r1, [r1] +; THUMB2-NEXT: orrs r0, r1 +; THUMB2-NEXT: lsls r0, r0, #24 +; THUMB2-NEXT: mov.w r0, #0 +; THUMB2-NEXT: it eq +; THUMB2-NEXT: moveq r0, #1 +; THUMB2-NEXT: bx lr + i32* nocapture readonly %b) { +entry: + %0 = load i16, i16* %a, align 2 + %conv = zext i16 %0 to i32 + %1 = load i32, i32* %b, align 4 + %or = or i32 %1, %conv + %and = and i32 %or, 255 + %cmp = icmp eq i32 %and, 0 + ret i1 %cmp +} + +define arm_aapcscc zeroext i1 @cmp_or8_int_int(i32* nocapture readonly %a, +; ARM-LABEL: cmp_or8_int_int: +; ARM: @ %bb.0: @ %entry +; ARM-NEXT: ldr r0, [r0] +; ARM-NEXT: ldr r1, [r1] +; ARM-NEXT: orr r1, r1, r0 +; ARM-NEXT: mov r0, #0 +; ARM-NEXT: tst r1, #255 +; ARM-NEXT: movweq r0, #1 +; ARM-NEXT: bx lr +; +; ARMEB-LABEL: cmp_or8_int_int: +; ARMEB: @ %bb.0: @ %entry +; ARMEB-NEXT: ldr r0, [r0] +; ARMEB-NEXT: ldr r1, [r1] +; ARMEB-NEXT: orr r1, r1, r0 +; ARMEB-NEXT: mov r0, #0 +; ARMEB-NEXT: tst r1, #255 +; ARMEB-NEXT: movweq r0, #1 +; ARMEB-NEXT: bx lr +; +; THUMB1-LABEL: cmp_or8_int_int: +; THUMB1: @ %bb.0: @ %entry +; THUMB1-NEXT: ldr r0, [r0] +; THUMB1-NEXT: ldr r2, [r1] +; THUMB1-NEXT: orrs r2, r0 +; THUMB1-NEXT: movs r0, #1 +; THUMB1-NEXT: movs r1, #0 +; THUMB1-NEXT: lsls r2, r2, #24 +; THUMB1-NEXT: beq .LBB6_2 +; THUMB1-NEXT: @ %bb.1: @ %entry +; THUMB1-NEXT: mov r0, r1 +; THUMB1-NEXT: .LBB6_2: @ %entry +; THUMB1-NEXT: bx lr +; +; THUMB2-LABEL: cmp_or8_int_int: +; THUMB2: @ %bb.0: @ %entry +; THUMB2-NEXT: ldr r0, [r0] +; THUMB2-NEXT: ldr r1, [r1] +; THUMB2-NEXT: orrs r0, r1 +; THUMB2-NEXT: lsls r0, r0, #24 +; THUMB2-NEXT: mov.w r0, #0 +; THUMB2-NEXT: it eq +; THUMB2-NEXT: moveq r0, #1 +; THUMB2-NEXT: bx lr + i32* nocapture readonly %b) { +entry: + %0 = load i32, i32* %a, align 4 + %1 = load i32, i32* %b, align 4 + %or = or i32 %1, %0 + %and = and i32 %or, 255 + %cmp = icmp eq i32 %and, 0 + ret i1 %cmp +} + +define arm_aapcscc zeroext i1 @cmp_or16(i32* nocapture readonly %a, +; ARM-LABEL: cmp_or16: +; ARM: @ %bb.0: @ %entry +; ARM-NEXT: ldr r0, [r0] +; ARM-NEXT: movw r2, #65535 +; ARM-NEXT: ldr r1, [r1] +; ARM-NEXT: orr r1, r1, r0 +; ARM-NEXT: mov r0, #0 +; ARM-NEXT: tst r1, r2 +; ARM-NEXT: movweq r0, #1 +; ARM-NEXT: bx lr +; +; ARMEB-LABEL: cmp_or16: +; ARMEB: @ %bb.0: @ %entry +; ARMEB-NEXT: ldr r0, [r0] +; ARMEB-NEXT: movw r2, #65535 +; ARMEB-NEXT: ldr r1, [r1] +; ARMEB-NEXT: orr r1, r1, r0 +; ARMEB-NEXT: mov r0, #0 +; ARMEB-NEXT: tst r1, r2 +; ARMEB-NEXT: movweq r0, #1 +; ARMEB-NEXT: bx lr +; +; THUMB1-LABEL: cmp_or16: +; THUMB1: @ %bb.0: @ %entry +; THUMB1-NEXT: ldr r0, [r0] +; THUMB1-NEXT: ldr r2, [r1] +; THUMB1-NEXT: orrs r2, r0 +; THUMB1-NEXT: movs r0, #1 +; THUMB1-NEXT: movs r1, #0 +; THUMB1-NEXT: lsls r2, r2, #16 +; THUMB1-NEXT: beq .LBB7_2 +; THUMB1-NEXT: @ %bb.1: @ %entry +; THUMB1-NEXT: mov r0, r1 +; THUMB1-NEXT: .LBB7_2: @ %entry +; THUMB1-NEXT: bx lr +; +; THUMB2-LABEL: cmp_or16: +; THUMB2: @ %bb.0: @ %entry +; THUMB2-NEXT: ldr r0, [r0] +; THUMB2-NEXT: ldr r1, [r1] +; THUMB2-NEXT: orrs r0, r1 +; THUMB2-NEXT: lsls r0, r0, #16 +; THUMB2-NEXT: mov.w r0, #0 +; THUMB2-NEXT: it eq +; THUMB2-NEXT: moveq r0, #1 +; THUMB2-NEXT: bx lr + i32* nocapture readonly %b) { +entry: + %0 = load i32, i32* %a, align 4 + %1 = load i32, i32* %b, align 4 + %or = or i32 %1, %0 + %and = and i32 %or, 65535 + %cmp = icmp eq i32 %and, 0 + ret i1 %cmp +} + +define arm_aapcscc zeroext i1 @cmp_and8_short_short(i16* nocapture readonly %a, +; ARM-LABEL: cmp_and8_short_short: +; ARM: @ %bb.0: @ %entry +; ARM-NEXT: ldrh r1, [r1] +; ARM-NEXT: ldrh r0, [r0] +; ARM-NEXT: and r1, r0, r1 +; ARM-NEXT: mov r0, #0 +; ARM-NEXT: tst r1, #255 +; ARM-NEXT: movweq r0, #1 +; ARM-NEXT: bx lr +; +; ARMEB-LABEL: cmp_and8_short_short: +; ARMEB: @ %bb.0: @ %entry +; ARMEB-NEXT: ldrh r1, [r1] +; ARMEB-NEXT: ldrh r0, [r0] +; ARMEB-NEXT: and r1, r0, r1 +; ARMEB-NEXT: mov r0, #0 +; ARMEB-NEXT: tst r1, #255 +; ARMEB-NEXT: movweq r0, #1 +; ARMEB-NEXT: bx lr +; +; THUMB1-LABEL: cmp_and8_short_short: +; THUMB1: @ %bb.0: @ %entry +; THUMB1-NEXT: ldrh r1, [r1] +; THUMB1-NEXT: ldrh r2, [r0] +; THUMB1-NEXT: ands r2, r1 +; THUMB1-NEXT: movs r0, #1 +; THUMB1-NEXT: movs r1, #0 +; THUMB1-NEXT: lsls r2, r2, #24 +; THUMB1-NEXT: beq .LBB8_2 +; THUMB1-NEXT: @ %bb.1: @ %entry +; THUMB1-NEXT: mov r0, r1 +; THUMB1-NEXT: .LBB8_2: @ %entry +; THUMB1-NEXT: bx lr +; +; THUMB2-LABEL: cmp_and8_short_short: +; THUMB2: @ %bb.0: @ %entry +; THUMB2-NEXT: ldrh r1, [r1] +; THUMB2-NEXT: ldrh r0, [r0] +; THUMB2-NEXT: ands r0, r1 +; THUMB2-NEXT: lsls r0, r0, #24 +; THUMB2-NEXT: mov.w r0, #0 +; THUMB2-NEXT: it eq +; THUMB2-NEXT: moveq r0, #1 +; THUMB2-NEXT: bx lr + i16* nocapture readonly %b) { +entry: + %0 = load i16, i16* %a, align 2 + %1 = load i16, i16* %b, align 2 + %and3 = and i16 %0, 255 + %2 = and i16 %and3, %1 + %cmp = icmp eq i16 %2, 0 + ret i1 %cmp +} + +define arm_aapcscc zeroext i1 @cmp_and8_short_int(i16* nocapture readonly %a, +; ARM-LABEL: cmp_and8_short_int: +; ARM: @ %bb.0: @ %entry +; ARM-NEXT: ldrh r0, [r0] +; ARM-NEXT: ldr r1, [r1] +; ARM-NEXT: and r1, r1, r0 +; ARM-NEXT: mov r0, #0 +; ARM-NEXT: tst r1, #255 +; ARM-NEXT: movweq r0, #1 +; ARM-NEXT: bx lr +; +; ARMEB-LABEL: cmp_and8_short_int: +; ARMEB: @ %bb.0: @ %entry +; ARMEB-NEXT: ldrh r0, [r0] +; ARMEB-NEXT: ldr r1, [r1] +; ARMEB-NEXT: and r1, r1, r0 +; ARMEB-NEXT: mov r0, #0 +; ARMEB-NEXT: tst r1, #255 +; ARMEB-NEXT: movweq r0, #1 +; ARMEB-NEXT: bx lr +; +; THUMB1-LABEL: cmp_and8_short_int: +; THUMB1: @ %bb.0: @ %entry +; THUMB1-NEXT: ldrh r0, [r0] +; THUMB1-NEXT: ldr r2, [r1] +; THUMB1-NEXT: ands r2, r0 +; THUMB1-NEXT: movs r0, #1 +; THUMB1-NEXT: movs r1, #0 +; THUMB1-NEXT: lsls r2, r2, #24 +; THUMB1-NEXT: beq .LBB9_2 +; THUMB1-NEXT: @ %bb.1: @ %entry +; THUMB1-NEXT: mov r0, r1 +; THUMB1-NEXT: .LBB9_2: @ %entry +; THUMB1-NEXT: bx lr +; +; THUMB2-LABEL: cmp_and8_short_int: +; THUMB2: @ %bb.0: @ %entry +; THUMB2-NEXT: ldrh r0, [r0] +; THUMB2-NEXT: ldr r1, [r1] +; THUMB2-NEXT: ands r0, r1 +; THUMB2-NEXT: lsls r0, r0, #24 +; THUMB2-NEXT: mov.w r0, #0 +; THUMB2-NEXT: it eq +; THUMB2-NEXT: moveq r0, #1 +; THUMB2-NEXT: bx lr + i32* nocapture readonly %b) { +entry: + %0 = load i16, i16* %a, align 2 + %1 = load i32, i32* %b, align 4 + %2 = and i16 %0, 255 + %and = zext i16 %2 to i32 + %and1 = and i32 %1, %and + %cmp = icmp eq i32 %and1, 0 + ret i1 %cmp +} + +define arm_aapcscc zeroext i1 @cmp_and8_int_int(i32* nocapture readonly %a, +; ARM-LABEL: cmp_and8_int_int: +; ARM: @ %bb.0: @ %entry +; ARM-NEXT: ldr r1, [r1] +; ARM-NEXT: ldr r0, [r0] +; ARM-NEXT: and r1, r0, r1 +; ARM-NEXT: mov r0, #0 +; ARM-NEXT: tst r1, #255 +; ARM-NEXT: movweq r0, #1 +; ARM-NEXT: bx lr +; +; ARMEB-LABEL: cmp_and8_int_int: +; ARMEB: @ %bb.0: @ %entry +; ARMEB-NEXT: ldr r1, [r1] +; ARMEB-NEXT: ldr r0, [r0] +; ARMEB-NEXT: and r1, r0, r1 +; ARMEB-NEXT: mov r0, #0 +; ARMEB-NEXT: tst r1, #255 +; ARMEB-NEXT: movweq r0, #1 +; ARMEB-NEXT: bx lr +; +; THUMB1-LABEL: cmp_and8_int_int: +; THUMB1: @ %bb.0: @ %entry +; THUMB1-NEXT: ldr r1, [r1] +; THUMB1-NEXT: ldr r2, [r0] +; THUMB1-NEXT: ands r2, r1 +; THUMB1-NEXT: movs r0, #1 +; THUMB1-NEXT: movs r1, #0 +; THUMB1-NEXT: lsls r2, r2, #24 +; THUMB1-NEXT: beq .LBB10_2 +; THUMB1-NEXT: @ %bb.1: @ %entry +; THUMB1-NEXT: mov r0, r1 +; THUMB1-NEXT: .LBB10_2: @ %entry +; THUMB1-NEXT: bx lr +; +; THUMB2-LABEL: cmp_and8_int_int: +; THUMB2: @ %bb.0: @ %entry +; THUMB2-NEXT: ldr r1, [r1] +; THUMB2-NEXT: ldr r0, [r0] +; THUMB2-NEXT: ands r0, r1 +; THUMB2-NEXT: lsls r0, r0, #24 +; THUMB2-NEXT: mov.w r0, #0 +; THUMB2-NEXT: it eq +; THUMB2-NEXT: moveq r0, #1 +; THUMB2-NEXT: bx lr + i32* nocapture readonly %b) { +entry: + %0 = load i32, i32* %a, align 4 + %1 = load i32, i32* %b, align 4 + %and = and i32 %0, 255 + %and1 = and i32 %and, %1 + %cmp = icmp eq i32 %and1, 0 + ret i1 %cmp +} + +define arm_aapcscc zeroext i1 @cmp_and16(i32* nocapture readonly %a, +; ARM-LABEL: cmp_and16: +; ARM: @ %bb.0: @ %entry +; ARM-NEXT: ldr r1, [r1] +; ARM-NEXT: movw r2, #65535 +; ARM-NEXT: ldr r0, [r0] +; ARM-NEXT: and r1, r0, r1 +; ARM-NEXT: mov r0, #0 +; ARM-NEXT: tst r1, r2 +; ARM-NEXT: movweq r0, #1 +; ARM-NEXT: bx lr +; +; ARMEB-LABEL: cmp_and16: +; ARMEB: @ %bb.0: @ %entry +; ARMEB-NEXT: ldr r1, [r1] +; ARMEB-NEXT: movw r2, #65535 +; ARMEB-NEXT: ldr r0, [r0] +; ARMEB-NEXT: and r1, r0, r1 +; ARMEB-NEXT: mov r0, #0 +; ARMEB-NEXT: tst r1, r2 +; ARMEB-NEXT: movweq r0, #1 +; ARMEB-NEXT: bx lr +; +; THUMB1-LABEL: cmp_and16: +; THUMB1: @ %bb.0: @ %entry +; THUMB1-NEXT: ldr r1, [r1] +; THUMB1-NEXT: ldr r2, [r0] +; THUMB1-NEXT: ands r2, r1 +; THUMB1-NEXT: movs r0, #1 +; THUMB1-NEXT: movs r1, #0 +; THUMB1-NEXT: lsls r2, r2, #16 +; THUMB1-NEXT: beq .LBB11_2 +; THUMB1-NEXT: @ %bb.1: @ %entry +; THUMB1-NEXT: mov r0, r1 +; THUMB1-NEXT: .LBB11_2: @ %entry +; THUMB1-NEXT: bx lr +; +; THUMB2-LABEL: cmp_and16: +; THUMB2: @ %bb.0: @ %entry +; THUMB2-NEXT: ldr r1, [r1] +; THUMB2-NEXT: ldr r0, [r0] +; THUMB2-NEXT: ands r0, r1 +; THUMB2-NEXT: lsls r0, r0, #16 +; THUMB2-NEXT: mov.w r0, #0 +; THUMB2-NEXT: it eq +; THUMB2-NEXT: moveq r0, #1 +; THUMB2-NEXT: bx lr + i32* nocapture readonly %b) { +entry: + %0 = load i32, i32* %a, align 4 + %1 = load i32, i32* %b, align 4 + %and = and i32 %0, 65535 + %and1 = and i32 %and, %1 + %cmp = icmp eq i32 %and1, 0 + ret i1 %cmp +} + +define arm_aapcscc i32 @add_and16(i32* nocapture readonly %a, i32 %y, i32 %z) { +; ARM-LABEL: add_and16: +; ARM: @ %bb.0: @ %entry +; ARM-NEXT: ldr r0, [r0] +; ARM-NEXT: add r1, r1, r2 +; ARM-NEXT: orr r0, r0, r1 +; ARM-NEXT: uxth r0, r0 +; ARM-NEXT: bx lr +; +; ARMEB-LABEL: add_and16: +; ARMEB: @ %bb.0: @ %entry +; ARMEB-NEXT: ldr r0, [r0] +; ARMEB-NEXT: add r1, r1, r2 +; ARMEB-NEXT: orr r0, r0, r1 +; ARMEB-NEXT: uxth r0, r0 +; ARMEB-NEXT: bx lr +; +; THUMB1-LABEL: add_and16: +; THUMB1: @ %bb.0: @ %entry +; THUMB1-NEXT: adds r1, r1, r2 +; THUMB1-NEXT: ldr r0, [r0] +; THUMB1-NEXT: orrs r0, r1 +; THUMB1-NEXT: uxth r0, r0 +; THUMB1-NEXT: bx lr +; +; THUMB2-LABEL: add_and16: +; THUMB2: @ %bb.0: @ %entry +; THUMB2-NEXT: ldr r0, [r0] +; THUMB2-NEXT: add r1, r2 +; THUMB2-NEXT: orrs r0, r1 +; THUMB2-NEXT: uxth r0, r0 +; THUMB2-NEXT: bx lr +entry: + %x = load i32, i32* %a, align 4 + %add = add i32 %y, %z + %or = or i32 %x, %add + %and = and i32 %or, 65535 + ret i32 %and +} + +define arm_aapcscc i32 @test1(i32* %a, i32* %b, i32 %x, i32 %y) { +; ARM-LABEL: test1: +; ARM: @ %bb.0: @ %entry +; ARM-NEXT: mul r2, r2, r3 +; ARM-NEXT: ldr r1, [r1] +; ARM-NEXT: ldr r0, [r0] +; ARM-NEXT: eor r0, r0, r1 +; ARM-NEXT: orr r0, r0, r2 +; ARM-NEXT: uxth r0, r0 +; ARM-NEXT: bx lr +; +; ARMEB-LABEL: test1: +; ARMEB: @ %bb.0: @ %entry +; ARMEB-NEXT: mul r2, r2, r3 +; ARMEB-NEXT: ldr r1, [r1] +; ARMEB-NEXT: ldr r0, [r0] +; ARMEB-NEXT: eor r0, r0, r1 +; ARMEB-NEXT: orr r0, r0, r2 +; ARMEB-NEXT: uxth r0, r0 +; ARMEB-NEXT: bx lr +; +; THUMB1-LABEL: test1: +; THUMB1: @ %bb.0: @ %entry +; THUMB1-NEXT: muls r2, r3, r2 +; THUMB1-NEXT: ldr r1, [r1] +; THUMB1-NEXT: ldr r0, [r0] +; THUMB1-NEXT: eors r0, r1 +; THUMB1-NEXT: orrs r0, r2 +; THUMB1-NEXT: uxth r0, r0 +; THUMB1-NEXT: bx lr +; +; THUMB2-LABEL: test1: +; THUMB2: @ %bb.0: @ %entry +; THUMB2-NEXT: muls r2, r3, r2 +; THUMB2-NEXT: ldr r1, [r1] +; THUMB2-NEXT: ldr r0, [r0] +; THUMB2-NEXT: eors r0, r1 +; THUMB2-NEXT: orrs r0, r2 +; THUMB2-NEXT: uxth r0, r0 +; THUMB2-NEXT: bx lr +entry: + %0 = load i32, i32* %a, align 4 + %1 = load i32, i32* %b, align 4 + %mul = mul i32 %x, %y + %xor = xor i32 %0, %1 + %or = or i32 %xor, %mul + %and = and i32 %or, 65535 + ret i32 %and +} + +define arm_aapcscc i32 @test2(i32* %a, i32* %b, i32 %x, i32 %y) { +; ARM-LABEL: test2: +; ARM: @ %bb.0: @ %entry +; ARM-NEXT: ldr r1, [r1] +; ARM-NEXT: ldr r0, [r0] +; ARM-NEXT: mul r1, r2, r1 +; ARM-NEXT: eor r0, r0, r3 +; ARM-NEXT: orr r0, r0, r1 +; ARM-NEXT: uxth r0, r0 +; ARM-NEXT: bx lr +; +; ARMEB-LABEL: test2: +; ARMEB: @ %bb.0: @ %entry +; ARMEB-NEXT: ldr r1, [r1] +; ARMEB-NEXT: ldr r0, [r0] +; ARMEB-NEXT: mul r1, r2, r1 +; ARMEB-NEXT: eor r0, r0, r3 +; ARMEB-NEXT: orr r0, r0, r1 +; ARMEB-NEXT: uxth r0, r0 +; ARMEB-NEXT: bx lr +; +; THUMB1-LABEL: test2: +; THUMB1: @ %bb.0: @ %entry +; THUMB1-NEXT: ldr r1, [r1] +; THUMB1-NEXT: muls r1, r2, r1 +; THUMB1-NEXT: ldr r0, [r0] +; THUMB1-NEXT: eors r0, r3 +; THUMB1-NEXT: orrs r0, r1 +; THUMB1-NEXT: uxth r0, r0 +; THUMB1-NEXT: bx lr +; +; THUMB2-LABEL: test2: +; THUMB2: @ %bb.0: @ %entry +; THUMB2-NEXT: ldr r1, [r1] +; THUMB2-NEXT: ldr r0, [r0] +; THUMB2-NEXT: muls r1, r2, r1 +; THUMB2-NEXT: eors r0, r3 +; THUMB2-NEXT: orrs r0, r1 +; THUMB2-NEXT: uxth r0, r0 +; THUMB2-NEXT: bx lr +entry: + %0 = load i32, i32* %a, align 4 + %1 = load i32, i32* %b, align 4 + %mul = mul i32 %x, %1 + %xor = xor i32 %0, %y + %or = or i32 %xor, %mul + %and = and i32 %or, 65535 + ret i32 %and +} + +define arm_aapcscc i32 @test3(i32* %a, i32* %b, i32 %x, i16* %y) { +; ARM-LABEL: test3: +; ARM: @ %bb.0: @ %entry +; ARM-NEXT: ldr r0, [r0] +; ARM-NEXT: mul r1, r2, r0 +; ARM-NEXT: ldrh r2, [r3] +; ARM-NEXT: eor r0, r0, r2 +; ARM-NEXT: orr r0, r0, r1 +; ARM-NEXT: uxth r0, r0 +; ARM-NEXT: bx lr +; +; ARMEB-LABEL: test3: +; ARMEB: @ %bb.0: @ %entry +; ARMEB-NEXT: ldr r0, [r0] +; ARMEB-NEXT: mul r1, r2, r0 +; ARMEB-NEXT: ldrh r2, [r3] +; ARMEB-NEXT: eor r0, r0, r2 +; ARMEB-NEXT: orr r0, r0, r1 +; ARMEB-NEXT: uxth r0, r0 +; ARMEB-NEXT: bx lr +; +; THUMB1-LABEL: test3: +; THUMB1: @ %bb.0: @ %entry +; THUMB1-NEXT: ldr r0, [r0] +; THUMB1-NEXT: muls r2, r0, r2 +; THUMB1-NEXT: ldrh r1, [r3] +; THUMB1-NEXT: eors r1, r0 +; THUMB1-NEXT: orrs r1, r2 +; THUMB1-NEXT: uxth r0, r1 +; THUMB1-NEXT: bx lr +; +; THUMB2-LABEL: test3: +; THUMB2: @ %bb.0: @ %entry +; THUMB2-NEXT: ldr r0, [r0] +; THUMB2-NEXT: mul r1, r2, r0 +; THUMB2-NEXT: ldrh r2, [r3] +; THUMB2-NEXT: eors r0, r2 +; THUMB2-NEXT: orrs r0, r1 +; THUMB2-NEXT: uxth r0, r0 +; THUMB2-NEXT: bx lr +entry: + %0 = load i32, i32* %a, align 4 + %1 = load i16, i16* %y, align 4 + %2 = zext i16 %1 to i32 + %mul = mul i32 %x, %0 + %xor = xor i32 %0, %2 + %or = or i32 %xor, %mul + %and = and i32 %or, 65535 + ret i32 %and +} + +define arm_aapcscc i32 @test4(i32* %a, i32* %b, i32 %x, i32 %y) { +; ARM-LABEL: test4: +; ARM: @ %bb.0: @ %entry +; ARM-NEXT: mul r2, r2, r3 +; ARM-NEXT: ldr r1, [r1] +; ARM-NEXT: ldr r0, [r0] +; ARM-NEXT: eor r0, r0, r1 +; ARM-NEXT: orr r0, r0, r2 +; ARM-NEXT: uxth r0, r0 +; ARM-NEXT: bx lr +; +; ARMEB-LABEL: test4: +; ARMEB: @ %bb.0: @ %entry +; ARMEB-NEXT: mul r2, r2, r3 +; ARMEB-NEXT: ldr r1, [r1] +; ARMEB-NEXT: ldr r0, [r0] +; ARMEB-NEXT: eor r0, r0, r1 +; ARMEB-NEXT: orr r0, r0, r2 +; ARMEB-NEXT: uxth r0, r0 +; ARMEB-NEXT: bx lr +; +; THUMB1-LABEL: test4: +; THUMB1: @ %bb.0: @ %entry +; THUMB1-NEXT: muls r2, r3, r2 +; THUMB1-NEXT: ldr r1, [r1] +; THUMB1-NEXT: ldr r0, [r0] +; THUMB1-NEXT: eors r0, r1 +; THUMB1-NEXT: orrs r0, r2 +; THUMB1-NEXT: uxth r0, r0 +; THUMB1-NEXT: bx lr +; +; THUMB2-LABEL: test4: +; THUMB2: @ %bb.0: @ %entry +; THUMB2-NEXT: muls r2, r3, r2 +; THUMB2-NEXT: ldr r1, [r1] +; THUMB2-NEXT: ldr r0, [r0] +; THUMB2-NEXT: eors r0, r1 +; THUMB2-NEXT: orrs r0, r2 +; THUMB2-NEXT: uxth r0, r0 +; THUMB2-NEXT: bx lr +entry: + %0 = load i32, i32* %a, align 4 + %1 = load i32, i32* %b, align 4 + %mul = mul i32 %x, %y + %xor = xor i32 %0, %1 + %or = or i32 %xor, %mul + %and = and i32 %or, 65535 + ret i32 %and +} + +define arm_aapcscc i32 @test5(i32* %a, i32* %b, i32 %x, i16 zeroext %y) { +; ARM-LABEL: test5: +; ARM: @ %bb.0: @ %entry +; ARM-NEXT: ldr r1, [r1] +; ARM-NEXT: ldr r0, [r0] +; ARM-NEXT: mul r1, r2, r1 +; ARM-NEXT: eor r0, r0, r3 +; ARM-NEXT: orr r0, r0, r1 +; ARM-NEXT: uxth r0, r0 +; ARM-NEXT: bx lr +; +; ARMEB-LABEL: test5: +; ARMEB: @ %bb.0: @ %entry +; ARMEB-NEXT: ldr r1, [r1] +; ARMEB-NEXT: ldr r0, [r0] +; ARMEB-NEXT: mul r1, r2, r1 +; ARMEB-NEXT: eor r0, r0, r3 +; ARMEB-NEXT: orr r0, r0, r1 +; ARMEB-NEXT: uxth r0, r0 +; ARMEB-NEXT: bx lr +; +; THUMB1-LABEL: test5: +; THUMB1: @ %bb.0: @ %entry +; THUMB1-NEXT: ldr r1, [r1] +; THUMB1-NEXT: muls r1, r2, r1 +; THUMB1-NEXT: ldr r0, [r0] +; THUMB1-NEXT: eors r0, r3 +; THUMB1-NEXT: orrs r0, r1 +; THUMB1-NEXT: uxth r0, r0 +; THUMB1-NEXT: bx lr +; +; THUMB2-LABEL: test5: +; THUMB2: @ %bb.0: @ %entry +; THUMB2-NEXT: ldr r1, [r1] +; THUMB2-NEXT: ldr r0, [r0] +; THUMB2-NEXT: muls r1, r2, r1 +; THUMB2-NEXT: eors r0, r3 +; THUMB2-NEXT: orrs r0, r1 +; THUMB2-NEXT: uxth r0, r0 +; THUMB2-NEXT: bx lr +entry: + %0 = load i32, i32* %a, align 4 + %1 = load i32, i32* %b, align 4 + %mul = mul i32 %x, %1 + %ext = zext i16 %y to i32 + %xor = xor i32 %0, %ext + %or = or i32 %xor, %mul + %and = and i32 %or, 65535 + ret i32 %and +} diff --git a/test/CodeGen/ARM/arm-and-tst-peephole.ll b/test/CodeGen/ARM/arm-and-tst-peephole.ll index a24808004ef16..c6ca6a624b116 100644 --- a/test/CodeGen/ARM/arm-and-tst-peephole.ll +++ b/test/CodeGen/ARM/arm-and-tst-peephole.ll @@ -142,27 +142,27 @@ return: ; preds = %bb2, %bb, %entry define i32 @test_tst_assessment(i32 %a, i32 %b) { ; ARM-LABEL: test_tst_assessment: -; ARM: @ BB#0: +; ARM: @ %bb.0: ; ARM-NEXT: and r0, r0, #1 ; ARM-NEXT: tst r1, #1 ; ARM-NEXT: subne r0, r0, #1 ; ARM-NEXT: mov pc, lr ; ; THUMB-LABEL: test_tst_assessment: -; THUMB: @ BB#0: +; THUMB: @ %bb.0: ; THUMB-NEXT: movs r2, r0 ; THUMB-NEXT: movs r0, #1 ; THUMB-NEXT: ands r0, r2 ; THUMB-NEXT: subs r2, r0, #1 ; THUMB-NEXT: lsls r1, r1, #31 ; THUMB-NEXT: beq .LBB2_2 -; THUMB-NEXT: @ BB#1: +; THUMB-NEXT: @ %bb.1: ; THUMB-NEXT: movs r0, r2 ; THUMB-NEXT: .LBB2_2: ; THUMB-NEXT: bx lr ; ; T2-LABEL: test_tst_assessment: -; T2: @ BB#0: +; T2: @ %bb.0: ; T2-NEXT: lsls r1, r1, #31 ; T2-NEXT: and r0, r0, #1 ; T2-NEXT: it ne @@ -170,7 +170,7 @@ define i32 @test_tst_assessment(i32 %a, i32 %b) { ; T2-NEXT: bx lr ; ; V8-LABEL: test_tst_assessment: -; V8: @ BB#0: +; V8: @ %bb.0: ; V8-NEXT: and r0, r0, #1 ; V8-NEXT: lsls r1, r1, #31 ; V8-NEXT: it ne diff --git a/test/CodeGen/ARM/atomic-ops-v8.ll b/test/CodeGen/ARM/atomic-ops-v8.ll index d1575ed12e4e1..192ed8f8db7e3 100644 --- a/test/CodeGen/ARM/atomic-ops-v8.ll +++ b/test/CodeGen/ARM/atomic-ops-v8.ll @@ -1046,7 +1046,7 @@ define i8 @test_atomic_cmpxchg_i8(i8 zeroext %wanted, i8 zeroext %new) nounwind ; CHECK-ARM-NEXT: cmp r[[OLD]], r0 ; CHECK-THUMB-NEXT: cmp r[[OLD]], r[[WANTED]] ; CHECK-NEXT: bne .LBB{{[0-9]+}}_4 -; CHECK-NEXT: BB#2: +; CHECK-NEXT: %bb.2: ; As above, r1 is a reasonable guess. ; CHECK: strexb [[STATUS:r[0-9]+]], r1, [r[[ADDR]]] ; CHECK-NEXT: cmp [[STATUS]], #0 @@ -1080,7 +1080,7 @@ define i16 @test_atomic_cmpxchg_i16(i16 zeroext %wanted, i16 zeroext %new) nounw ; CHECK-ARM-NEXT: cmp r[[OLD]], r0 ; CHECK-THUMB-NEXT: cmp r[[OLD]], r[[WANTED]] ; CHECK-NEXT: bne .LBB{{[0-9]+}}_4 -; CHECK-NEXT: BB#2: +; CHECK-NEXT: %bb.2: ; As above, r1 is a reasonable guess. ; CHECK: stlexh [[STATUS:r[0-9]+]], r1, [r[[ADDR]]] ; CHECK-NEXT: cmp [[STATUS]], #0 @@ -1113,7 +1113,7 @@ define void @test_atomic_cmpxchg_i32(i32 %wanted, i32 %new) nounwind { ; function there. ; CHECK-NEXT: cmp r[[OLD]], r0 ; CHECK-NEXT: bne .LBB{{[0-9]+}}_4 -; CHECK-NEXT: BB#2: +; CHECK-NEXT: %bb.2: ; As above, r1 is a reasonable guess. ; CHECK: stlex [[STATUS:r[0-9]+]], r1, [r[[ADDR]]] ; CHECK-NEXT: cmp [[STATUS]], #0 @@ -1152,7 +1152,7 @@ define void @test_atomic_cmpxchg_i64(i64 %wanted, i64 %new) nounwind { ; CHECK-ARM-BE: orrs{{(\.w)?}} {{r[0-9]+}}, [[MISMATCH_HI]], [[MISMATCH_LO]] ; CHECK-THUMB-BE: orrs{{(\.w)?}} {{(r[0-9]+, )?}}[[MISMATCH_LO]], [[MISMATCH_HI]] ; CHECK-NEXT: bne .LBB{{[0-9]+}}_4 -; CHECK-NEXT: BB#2: +; CHECK-NEXT: %bb.2: ; As above, r2, r3 is a reasonable guess. ; CHECK: strexd [[STATUS:r[0-9]+]], r2, r3, [r[[ADDR]]] ; CHECK-NEXT: cmp [[STATUS]], #0 diff --git a/test/CodeGen/ARM/bool-ext-inc.ll b/test/CodeGen/ARM/bool-ext-inc.ll index ca9c9ab079db0..00a7fcdee3caa 100644 --- a/test/CodeGen/ARM/bool-ext-inc.ll +++ b/test/CodeGen/ARM/bool-ext-inc.ll @@ -3,7 +3,7 @@ define i32 @sext_inc(i1 zeroext %x) { ; CHECK-LABEL: sext_inc: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: eor r0, r0, #1 ; CHECK-NEXT: mov pc, lr %ext = sext i1 %x to i32 @@ -13,7 +13,7 @@ define i32 @sext_inc(i1 zeroext %x) { define <4 x i32> @sext_inc_vec(<4 x i1> %x) { ; CHECK-LABEL: sext_inc_vec: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vmov.i16 d16, #0x1 ; CHECK-NEXT: vmov d17, r0, r1 ; CHECK-NEXT: veor d16, d17, d16 @@ -30,7 +30,7 @@ define <4 x i32> @sext_inc_vec(<4 x i1> %x) { define <4 x i32> @cmpgt_sext_inc_vec(<4 x i32> %x, <4 x i32> %y) { ; CHECK-LABEL: cmpgt_sext_inc_vec: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vmov d17, r2, r3 ; CHECK-NEXT: vmov d16, r0, r1 ; CHECK-NEXT: mov r0, sp @@ -49,7 +49,7 @@ define <4 x i32> @cmpgt_sext_inc_vec(<4 x i32> %x, <4 x i32> %y) { define <4 x i32> @cmpne_sext_inc_vec(<4 x i32> %x, <4 x i32> %y) { ; CHECK-LABEL: cmpne_sext_inc_vec: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vmov d17, r2, r3 ; CHECK-NEXT: mov r12, sp ; CHECK-NEXT: vld1.64 {d18, d19}, [r12] diff --git a/test/CodeGen/ARM/cmp1-peephole-thumb.mir b/test/CodeGen/ARM/cmp1-peephole-thumb.mir index 3e87ced0ee57d..62675b4a77c8b 100644 --- a/test/CodeGen/ARM/cmp1-peephole-thumb.mir +++ b/test/CodeGen/ARM/cmp1-peephole-thumb.mir @@ -49,9 +49,9 @@ frameInfo: hasVAStart: false hasMustTailInVarArgFunc: false -# CHECK: tMOVi8 1, 14, _ -# CHECK: tMOVi8 0, 14, _ -# CHECK: tMUL %1, %0, 14, _ +# CHECK: tMOVi8 1, 14, %noreg +# CHECK: tMOVi8 0, 14, %noreg +# CHECK: tMUL %1, %0, 14, %noreg # CHECK-NOT: tCMPi8 body: | bb.0.entry: @@ -59,10 +59,10 @@ body: | %1 = COPY %r1 %0 = COPY %r0 - %2, %cpsr = tMUL %1, %0, 14, _ - %3, %cpsr = tMOVi8 1, 14, _ - %4, %cpsr = tMOVi8 0, 14, _ - tCMPi8 killed %2, 0, 14, _, implicit-def %cpsr + %2, %cpsr = tMUL %1, %0, 14, %noreg + %3, %cpsr = tMOVi8 1, 14, %noreg + %4, %cpsr = tMOVi8 0, 14, %noreg + tCMPi8 killed %2, 0, 14, %noreg, implicit-def %cpsr tBcc %bb.2.entry, 0, %cpsr bb.1.entry: @@ -70,6 +70,6 @@ body: | bb.2.entry: %5 = PHI %4, %bb.1.entry, %3, %bb.0.entry %r0 = COPY %5 - tBX_RET 14, _, implicit %r0 + tBX_RET 14, %noreg, implicit %r0 ... diff --git a/test/CodeGen/ARM/cmp2-peephole-thumb.mir b/test/CodeGen/ARM/cmp2-peephole-thumb.mir index a31086d2113eb..12569b53fde13 100644 --- a/test/CodeGen/ARM/cmp2-peephole-thumb.mir +++ b/test/CodeGen/ARM/cmp2-peephole-thumb.mir @@ -80,24 +80,24 @@ body: | %1 = COPY %r1 %0 = COPY %r0 - %2, %cpsr = tMUL %0, %1, 14, _ - tSTRspi %2, %stack.1.mul, 0, 14, _ :: (store 4 into %ir.mul) - tCMPi8 %2, 0, 14, _, implicit-def %cpsr + %2, %cpsr = tMUL %0, %1, 14, %noreg + tSTRspi %2, %stack.1.mul, 0, 14, %noreg :: (store 4 into %ir.mul) + tCMPi8 %2, 0, 14, %noreg, implicit-def %cpsr tBcc %bb.2.if.end, 12, %cpsr - tB %bb.1.if.then, 14, _ + tB %bb.1.if.then, 14, %noreg bb.1.if.then: - %4, %cpsr = tMOVi8 42, 14, _ - tSTRspi killed %4, %stack.0.retval, 0, 14, _ :: (store 4 into %ir.retval) - tB %bb.3.return, 14, _ + %4, %cpsr = tMOVi8 42, 14, %noreg + tSTRspi killed %4, %stack.0.retval, 0, 14, %noreg :: (store 4 into %ir.retval) + tB %bb.3.return, 14, %noreg bb.2.if.end: - %3, %cpsr = tMOVi8 1, 14, _ - tSTRspi killed %3, %stack.0.retval, 0, 14, _ :: (store 4 into %ir.retval) + %3, %cpsr = tMOVi8 1, 14, %noreg + tSTRspi killed %3, %stack.0.retval, 0, 14, %noreg :: (store 4 into %ir.retval) bb.3.return: - %5 = tLDRspi %stack.0.retval, 0, 14, _ :: (dereferenceable load 4 from %ir.retval) + %5 = tLDRspi %stack.0.retval, 0, 14, %noreg :: (dereferenceable load 4 from %ir.retval) %r0 = COPY %5 - tBX_RET 14, _, implicit %r0 + tBX_RET 14, %noreg, implicit %r0 ... diff --git a/test/CodeGen/ARM/cmpxchg-weak.ll b/test/CodeGen/ARM/cmpxchg-weak.ll index 29d97fef06068..5ee07828526c5 100644 --- a/test/CodeGen/ARM/cmpxchg-weak.ll +++ b/test/CodeGen/ARM/cmpxchg-weak.ll @@ -5,16 +5,16 @@ define void @test_cmpxchg_weak(i32 *%addr, i32 %desired, i32 %new) { %pair = cmpxchg weak i32* %addr, i32 %desired, i32 %new seq_cst monotonic %oldval = extractvalue { i32, i1 } %pair, 0 -; CHECK-NEXT: BB#0: +; CHECK-NEXT: %bb.0: ; CHECK-NEXT: ldrex [[LOADED:r[0-9]+]], [r0] ; CHECK-NEXT: cmp [[LOADED]], r1 ; CHECK-NEXT: bne [[LDFAILBB:LBB[0-9]+_[0-9]+]] -; CHECK-NEXT: BB#1: +; CHECK-NEXT: %bb.1: ; CHECK-NEXT: dmb ish ; CHECK-NEXT: strex [[SUCCESS:r[0-9]+]], r2, [r0] ; CHECK-NEXT: cmp [[SUCCESS]], #0 ; CHECK-NEXT: beq [[SUCCESSBB:LBB[0-9]+_[0-9]+]] -; CHECK-NEXT: BB#2: +; CHECK-NEXT: %bb.2: ; CHECK-NEXT: str r3, [r0] ; CHECK-NEXT: bx lr ; CHECK-NEXT: [[LDFAILBB]]: @@ -37,11 +37,11 @@ define i1 @test_cmpxchg_weak_to_bool(i32, i32 *%addr, i32 %desired, i32 %new) { %pair = cmpxchg weak i32* %addr, i32 %desired, i32 %new seq_cst monotonic %success = extractvalue { i32, i1 } %pair, 1 -; CHECK-NEXT: BB#0: +; CHECK-NEXT: %bb.0: ; CHECK-NEXT: ldrex [[LOADED:r[0-9]+]], [r1] ; CHECK-NEXT: cmp [[LOADED]], r2 ; CHECK-NEXT: bne [[LDFAILBB:LBB[0-9]+_[0-9]+]] -; CHECK-NEXT: BB#1: +; CHECK-NEXT: %bb.1: ; CHECK-NEXT: dmb ish ; CHECK-NEXT: mov r0, #0 ; CHECK-NEXT: strex [[SUCCESS:r[0-9]+]], r3, [r1] diff --git a/test/CodeGen/ARM/constant-islands-cfg.mir b/test/CodeGen/ARM/constant-islands-cfg.mir index 66d854393b547..140ef727e4322 100644 --- a/test/CodeGen/ARM/constant-islands-cfg.mir +++ b/test/CodeGen/ARM/constant-islands-cfg.mir @@ -48,17 +48,17 @@ fixedStack: body: | bb.0: liveins: %r0 - tCMPi8 killed %r0, 0, 14, _, implicit-def %cpsr + tCMPi8 killed %r0, 0, 14, %noreg, implicit-def %cpsr tBcc %bb.2, 1, killed %cpsr - tB %bb.3, 14, _ + tB %bb.3, 14, %noreg bb.1: dead %r0 = SPACE 256, undef %r0 bb.2: - tPOP_RET 14, _, def %pc + tPOP_RET 14, %noreg, def %pc bb.3: - tPOP_RET 14, _, def %pc + tPOP_RET 14, %noreg, def %pc ... diff --git a/test/CodeGen/ARM/cortex-a57-misched-alu.ll b/test/CodeGen/ARM/cortex-a57-misched-alu.ll index 2ced60fbf0d31..7d50a2023ed81 100644 --- a/test/CodeGen/ARM/cortex-a57-misched-alu.ll +++ b/test/CodeGen/ARM/cortex-a57-misched-alu.ll @@ -5,7 +5,7 @@ ; Check the latency for ALU shifted operand variants. ; ; CHECK: ********** MI Scheduling ********** -; CHECK: foo:BB#0 entry +; CHECK: foo:%bb.0 entry ; ALU, basic - 1 cyc I0/I1 ; CHECK: EORrr diff --git a/test/CodeGen/ARM/cortex-a57-misched-basic.ll b/test/CodeGen/ARM/cortex-a57-misched-basic.ll index cfbef7bd42937..ad729c2ff2a3a 100644 --- a/test/CodeGen/ARM/cortex-a57-misched-basic.ll +++ b/test/CodeGen/ARM/cortex-a57-misched-basic.ll @@ -6,7 +6,7 @@ ; SDIV should be scheduled at the block's begin (20 cyc of independent M unit). ; ; CHECK: ********** MI Scheduling ********** -; CHECK: foo:BB#0 entry +; CHECK: foo:%bb.0 entry ; GENERIC: LDRi12 ; GENERIC: Latency : 1 @@ -30,7 +30,7 @@ ; A57_SCHED: SUBrr ; A57_SCHED: Latency : 1 -; CHECK: ** Final schedule for BB#0 *** +; CHECK: ** Final schedule for %bb.0 *** ; GENERIC: LDRi12 ; GENERIC: SDIV ; A57_SCHED: SDIV diff --git a/test/CodeGen/ARM/cortex-a57-misched-vadd.ll b/test/CodeGen/ARM/cortex-a57-misched-vadd.ll index eb8d1c85523ff..cb7490856aba0 100644 --- a/test/CodeGen/ARM/cortex-a57-misched-vadd.ll +++ b/test/CodeGen/ARM/cortex-a57-misched-vadd.ll @@ -1,7 +1,7 @@ ; REQUIRES: asserts ; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -misched-postra -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s -; CHECK-LABEL: addv_i32:BB#0 +; CHECK-LABEL: addv_i32:%bb.0 ; CHECK: SU(8): {{.*}} VADDv4i32 ; CHECK-NEXT: # preds left ; CHECK-NEXT: # succs left @@ -13,7 +13,7 @@ define <4 x i32> @addv_i32(<4 x i32>, <4 x i32>) { ret <4 x i32> %3 } -; CHECK-LABEL: addv_f32:BB#0 +; CHECK-LABEL: addv_f32:%bb.0 ; CHECK: SU(8): {{.*}} VADDfq ; CHECK-NEXT: # preds left ; CHECK-NEXT: # succs left diff --git a/test/CodeGen/ARM/cortex-a57-misched-vfma.ll b/test/CodeGen/ARM/cortex-a57-misched-vfma.ll index 372b2e2f5dc99..a3e07ba17b9a1 100644 --- a/test/CodeGen/ARM/cortex-a57-misched-vfma.ll +++ b/test/CodeGen/ARM/cortex-a57-misched-vfma.ll @@ -5,7 +5,7 @@ define float @Test1(float %f1, float %f2, float %f3, float %f4, float %f5, float %f6) { ; CHECK: ********** MI Scheduling ********** -; CHECK: Test1:BB#0 +; CHECK: Test1:%bb.0 ; CHECK: VMULS ; > VMULS common latency = 5 @@ -44,7 +44,7 @@ define float @Test1(float %f1, float %f2, float %f3, float %f4, float %f5, float ; ASIMD form define <2 x float> @Test2(<2 x float> %f1, <2 x float> %f2, <2 x float> %f3, <2 x float> %f4, <2 x float> %f5, <2 x float> %f6) { ; CHECK: ********** MI Scheduling ********** -; CHECK: Test2:BB#0 +; CHECK: Test2:%bb.0 ; CHECK: VMULfd ; > VMULfd common latency = 5 @@ -82,7 +82,7 @@ define <2 x float> @Test2(<2 x float> %f1, <2 x float> %f2, <2 x float> %f3, <2 define float @Test3(float %f1, float %f2, float %f3, float %f4, float %f5, float %f6) { ; CHECK: ********** MI Scheduling ********** -; CHECK: Test3:BB#0 +; CHECK: Test3:%bb.0 ; CHECK: VMULS ; > VMULS common latency = 5 @@ -121,7 +121,7 @@ define float @Test3(float %f1, float %f2, float %f3, float %f4, float %f5, float ; ASIMD form define <2 x float> @Test4(<2 x float> %f1, <2 x float> %f2, <2 x float> %f3, <2 x float> %f4, <2 x float> %f5, <2 x float> %f6) { ; CHECK: ********** MI Scheduling ********** -; CHECK: Test4:BB#0 +; CHECK: Test4:%bb.0 ; CHECK: VMULfd ; > VMULfd common latency = 5 @@ -159,7 +159,7 @@ define <2 x float> @Test4(<2 x float> %f1, <2 x float> %f2, <2 x float> %f3, <2 define float @Test5(float %f1, float %f2, float %f3) { ; CHECK: ********** MI Scheduling ********** -; CHECK: Test5:BB#0 +; CHECK: Test5:%bb.0 ; CHECK-DEFAULT: VNMLS ; CHECK-FAST: VFNMS @@ -178,7 +178,7 @@ define float @Test5(float %f1, float %f2, float %f3) { define float @Test6(float %f1, float %f2, float %f3) { ; CHECK: ********** MI Scheduling ********** -; CHECK: Test6:BB#0 +; CHECK: Test6:%bb.0 ; CHECK-DEFAULT: VNMLA ; CHECK-FAST: VFNMA diff --git a/test/CodeGen/ARM/cortex-a57-misched-vsub.ll b/test/CodeGen/ARM/cortex-a57-misched-vsub.ll index c3c445d3f0e10..fe14c861f8e64 100644 --- a/test/CodeGen/ARM/cortex-a57-misched-vsub.ll +++ b/test/CodeGen/ARM/cortex-a57-misched-vsub.ll @@ -1,7 +1,7 @@ ; REQUIRES: asserts ; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -misched-postra -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s -; CHECK-LABEL: subv_i32:BB#0 +; CHECK-LABEL: subv_i32:%bb.0 ; CHECK: SU(8): {{.*}} VSUBv4i32 ; CHECK-NEXT: # preds left ; CHECK-NEXT: # succs left @@ -13,7 +13,7 @@ define <4 x i32> @subv_i32(<4 x i32>, <4 x i32>) { ret <4 x i32> %3 } -; CHECK-LABEL: subv_f32:BB#0 +; CHECK-LABEL: subv_f32:%bb.0 ; CHECK: SU(8): {{.*}} VSUBfq ; CHECK-NEXT: # preds left ; CHECK-NEXT: # succs left diff --git a/test/CodeGen/ARM/cortexr52-misched-basic.ll b/test/CodeGen/ARM/cortexr52-misched-basic.ll index 614157eb0e105..0edc6653a033c 100644 --- a/test/CodeGen/ARM/cortexr52-misched-basic.ll +++ b/test/CodeGen/ARM/cortexr52-misched-basic.ll @@ -7,7 +7,7 @@ ; as div takes more cycles to compute than eor. ; ; CHECK: ********** MI Scheduling ********** -; CHECK: foo:BB#0 entry +; CHECK: foo:%bb.0 entry ; CHECK: EORrr ; GENERIC: Latency : 1 ; R52_SCHED: Latency : 3 @@ -17,7 +17,7 @@ ; CHECK: SDIV ; GENERIC: Latency : 0 ; R52_SCHED: Latency : 8 -; CHECK: ** Final schedule for BB#0 *** +; CHECK: ** Final schedule for %bb.0 *** ; GENERIC: EORrr ; GENERIC: SDIV ; R52_SCHED: SDIV diff --git a/test/CodeGen/ARM/crash-greedy.ll b/test/CodeGen/ARM/crash-greedy.ll index 6a58bb871d35a..31d6079db7101 100644 --- a/test/CodeGen/ARM/crash-greedy.ll +++ b/test/CodeGen/ARM/crash-greedy.ll @@ -61,7 +61,7 @@ for.end: ; preds = %cond.end ; CHECK: insert_elem ; This test has a sub-register copy with a kill flag: -; %vreg6:ssub_3 = COPY %vreg6:ssub_2; QPR_VFP2:%vreg6 +; %6:ssub_3 = COPY %6:ssub_2; QPR_VFP2:%6 ; The rewriter must do something sensible with that, or the scavenger crashes. define void @insert_elem() nounwind { entry: diff --git a/test/CodeGen/ARM/crash-on-pow2-shufflevector.ll b/test/CodeGen/ARM/crash-on-pow2-shufflevector.ll index 8395674e880d7..4f6055dee62ac 100644 --- a/test/CodeGen/ARM/crash-on-pow2-shufflevector.ll +++ b/test/CodeGen/ARM/crash-on-pow2-shufflevector.ll @@ -6,7 +6,7 @@ define i32 @foo(%struct.desc* %descs, i32 %num, i32 %cw) local_unnamed_addr #0 { ; CHECK-LABEL: foo: -; CHECK: @ BB#0: @ %entry +; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: mov r1, #32 ; CHECK-NEXT: vld1.32 {d16, d17}, [r0], r1 ; CHECK-NEXT: vld1.32 {d18, d19}, [r0] diff --git a/test/CodeGen/ARM/dbg-range-extension.mir b/test/CodeGen/ARM/dbg-range-extension.mir index a79607705c1c7..02105eabc6df5 100644 --- a/test/CodeGen/ARM/dbg-range-extension.mir +++ b/test/CodeGen/ARM/dbg-range-extension.mir @@ -23,37 +23,37 @@ # CHECK: [[VAR_I:![0-9]+]] = !DILocalVariable(name: "i", # CHECK: bb.0.entry -# CHECK: DBG_VALUE debug-use %r0, debug-use _, [[VAR_A]] -# CHECK: DBG_VALUE debug-use [[REG_A:%r[0-9]+]], debug-use _, [[VAR_A]] -# CHECK: DBG_VALUE debug-use [[REG_B:%r[0-9]+]], debug-use _, [[VAR_B]] +# CHECK: DBG_VALUE debug-use %r0, debug-use %noreg, [[VAR_A]] +# CHECK: DBG_VALUE debug-use [[REG_A:%r[0-9]+]], debug-use %noreg, [[VAR_A]] +# CHECK: DBG_VALUE debug-use [[REG_B:%r[0-9]+]], debug-use %noreg, [[VAR_B]] # CHECK: bb.1.if.then -# CHECK: DBG_VALUE debug-use [[REG_B]], debug-use _, [[VAR_B]] -# CHECK: DBG_VALUE debug-use [[REG_A]], debug-use _, [[VAR_A]] -# CHECK: DBG_VALUE debug-use [[REG_C:%r[0-9]+]], debug-use _, [[VAR_C]] +# CHECK: DBG_VALUE debug-use [[REG_B]], debug-use %noreg, [[VAR_B]] +# CHECK: DBG_VALUE debug-use [[REG_A]], debug-use %noreg, [[VAR_A]] +# CHECK: DBG_VALUE debug-use [[REG_C:%r[0-9]+]], debug-use %noreg, [[VAR_C]] # CHECK: DBG_VALUE 1, 0, [[VAR_I]] # CHECK: bb.2.for.body -# CHECK: DBG_VALUE debug-use [[REG_I:%r[0-9]+]], debug-use _, [[VAR_I]] -# CHECK: DBG_VALUE debug-use [[REG_C]], debug-use _, [[VAR_C]] -# CHECK: DBG_VALUE debug-use [[REG_B]], debug-use _, [[VAR_B]] -# CHECK: DBG_VALUE debug-use [[REG_A]], debug-use _, [[VAR_A]] -# CHECK: DBG_VALUE debug-use [[REG_I]], debug-use _, [[VAR_I]] +# CHECK: DBG_VALUE debug-use [[REG_I:%r[0-9]+]], debug-use %noreg, [[VAR_I]] +# CHECK: DBG_VALUE debug-use [[REG_C]], debug-use %noreg, [[VAR_C]] +# CHECK: DBG_VALUE debug-use [[REG_B]], debug-use %noreg, [[VAR_B]] +# CHECK: DBG_VALUE debug-use [[REG_A]], debug-use %noreg, [[VAR_A]] +# CHECK: DBG_VALUE debug-use [[REG_I]], debug-use %noreg, [[VAR_I]] # CHECK: bb.3.for.cond -# CHECK: DBG_VALUE debug-use [[REG_C]], debug-use _, [[VAR_C]] -# CHECK: DBG_VALUE debug-use [[REG_B]], debug-use _, [[VAR_B]] -# CHECK: DBG_VALUE debug-use [[REG_A]], debug-use _, [[VAR_A]] -# CHECK: DBG_VALUE debug-use [[REG_I]], debug-use _, [[VAR_I]] +# CHECK: DBG_VALUE debug-use [[REG_C]], debug-use %noreg, [[VAR_C]] +# CHECK: DBG_VALUE debug-use [[REG_B]], debug-use %noreg, [[VAR_B]] +# CHECK: DBG_VALUE debug-use [[REG_A]], debug-use %noreg, [[VAR_A]] +# CHECK: DBG_VALUE debug-use [[REG_I]], debug-use %noreg, [[VAR_I]] # CHECK: bb.4.for.cond.cleanup -# CHECK: DBG_VALUE debug-use [[REG_C]], debug-use _, [[VAR_C]] -# CHECK: DBG_VALUE debug-use [[REG_B]], debug-use _, [[VAR_B]] -# CHECK: DBG_VALUE debug-use [[REG_A]], debug-use _, [[VAR_A]] +# CHECK: DBG_VALUE debug-use [[REG_C]], debug-use %noreg, [[VAR_C]] +# CHECK: DBG_VALUE debug-use [[REG_B]], debug-use %noreg, [[VAR_B]] +# CHECK: DBG_VALUE debug-use [[REG_A]], debug-use %noreg, [[VAR_A]] # CHECK: bb.5.if.end -# CHECK: DBG_VALUE debug-use [[REG_B]], debug-use _, [[VAR_B]] -# CHECK: DBG_VALUE debug-use [[REG_A]], debug-use _, [[VAR_A]] +# CHECK: DBG_VALUE debug-use [[REG_B]], debug-use %noreg, [[VAR_B]] +# CHECK: DBG_VALUE debug-use [[REG_A]], debug-use %noreg, [[VAR_A]] --- | ; ModuleID = '/data/kwalker/work/OpenSource-llvm/llvm/test/CodeGen/ARM/dbg-range-extension.ll' source_filename = "/data/kwalker/work/OpenSource-llvm/llvm/test/CodeGen/ARM/dbg-range-extension.ll" @@ -211,7 +211,7 @@ body: | bb.0.entry: liveins: %r0, %r4, %r5, %r6, %r7, %r11, %lr - %sp = frame-setup STMDB_UPD %sp, 14, _, killed %r4, killed %r5, killed %r6, killed %r7, killed %r11, killed %lr + %sp = frame-setup STMDB_UPD %sp, 14, %noreg, killed %r4, killed %r5, killed %r6, killed %r7, killed %r11, killed %lr frame-setup CFI_INSTRUCTION def_cfa_offset 24 frame-setup CFI_INSTRUCTION offset %lr, -4 frame-setup CFI_INSTRUCTION offset %r11, -8 @@ -219,58 +219,58 @@ body: | frame-setup CFI_INSTRUCTION offset %r6, -16 frame-setup CFI_INSTRUCTION offset %r5, -20 frame-setup CFI_INSTRUCTION offset %r4, -24 - DBG_VALUE debug-use %r0, debug-use _, !13, !20, debug-location !21 - %r4 = MOVr killed %r0, 14, _, _ - DBG_VALUE debug-use %r4, debug-use _, !13, !20, debug-location !21 - %r0 = MOVi 10, 14, _, _, debug-location !22 - %r1 = MOVi 11, 14, _, _, debug-location !22 + DBG_VALUE debug-use %r0, debug-use %noreg, !13, !20, debug-location !21 + %r4 = MOVr killed %r0, 14, %noreg, %noreg + DBG_VALUE debug-use %r4, debug-use %noreg, !13, !20, debug-location !21 + %r0 = MOVi 10, 14, %noreg, _, debug-location !22 + %r1 = MOVi 11, 14, %noreg, _, debug-location !22 BL @func2, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit killed %r0, implicit killed %r1, implicit-def %sp, implicit-def %r0, debug-location !22 - %r5 = MOVr killed %r0, 14, _, _, debug-location !22 - DBG_VALUE debug-use %r5, debug-use _, !14, !20, debug-location !23 - CMPri %r4, 0, 14, _, implicit-def %cpsr, debug-location !25 + %r5 = MOVr killed %r0, 14, %noreg, _, debug-location !22 + DBG_VALUE debug-use %r5, debug-use %noreg, !14, !20, debug-location !23 + CMPri %r4, 0, 14, %noreg, implicit-def %cpsr, debug-location !25 Bcc %bb.5.if.end, 0, killed %cpsr bb.1.if.then: liveins: %r4, %r5 - %r0 = MOVi 12, 14, _, _, debug-location !26 - %r1 = MOVi 13, 14, _, _, debug-location !26 + %r0 = MOVi 12, 14, %noreg, _, debug-location !26 + %r1 = MOVi 13, 14, %noreg, _, debug-location !26 BL @func2, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit killed %r0, implicit killed %r1, implicit-def %sp, implicit-def %r0, debug-location !26 - %r6 = MOVr killed %r0, 14, _, _, debug-location !26 - DBG_VALUE debug-use %r6, debug-use _, !15, !20, debug-location !27 - %r7 = MOVi 1, 14, _, _ + %r6 = MOVr killed %r0, 14, %noreg, _, debug-location !26 + DBG_VALUE debug-use %r6, debug-use %noreg, !15, !20, debug-location !27 + %r7 = MOVi 1, 14, %noreg, %noreg DBG_VALUE 1, 0, !18, !20, debug-location !28 B %bb.3.for.cond bb.2.for.body: liveins: %r4, %r5, %r6, %r7 - %r1 = ADDrr %r5, %r7, 14, _, _, debug-location !36 - %r0 = MOVr %r7, 14, _, _, debug-location !36 + %r1 = ADDrr %r5, %r7, 14, %noreg, _, debug-location !36 + %r0 = MOVr %r7, 14, %noreg, _, debug-location !36 BL @func2, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit killed %r0, implicit killed %r1, implicit-def %sp, implicit-def dead %r0, debug-location !36 - %r7 = ADDri killed %r7, 1, 14, _, _, debug-location !38 - DBG_VALUE debug-use %r7, debug-use _, !18, !20, debug-location !28 + %r7 = ADDri killed %r7, 1, 14, %noreg, _, debug-location !38 + DBG_VALUE debug-use %r7, debug-use %noreg, !18, !20, debug-location !28 bb.3.for.cond: liveins: %r4, %r5, %r6, %r7 - DBG_VALUE debug-use %r7, debug-use _, !18, !20, debug-location !28 - CMPrr %r7, %r4, 14, _, implicit-def %cpsr, debug-location !33 + DBG_VALUE debug-use %r7, debug-use %noreg, !18, !20, debug-location !28 + CMPrr %r7, %r4, 14, %noreg, implicit-def %cpsr, debug-location !33 Bcc %bb.2.for.body, 11, killed %cpsr, debug-location !33 bb.4.for.cond.cleanup: liveins: %r4, %r5, %r6 - %r0 = MOVr %r5, 14, _, _, debug-location !34 - %r1 = MOVr killed %r6, 14, _, _, debug-location !34 + %r0 = MOVr %r5, 14, %noreg, _, debug-location !34 + %r1 = MOVr killed %r6, 14, %noreg, _, debug-location !34 BL @func2, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit killed %r0, implicit killed %r1, implicit-def %sp, implicit-def dead %r0, debug-location !34 bb.5.if.end: liveins: %r4, %r5 - %r0 = MOVr killed %r5, 14, _, _, debug-location !43 - %r1 = MOVr killed %r4, 14, _, _, debug-location !43 - %sp = LDMIA_UPD %sp, 14, _, def %r4, def %r5, def %r6, def %r7, def %r11, def %lr, debug-location !43 + %r0 = MOVr killed %r5, 14, %noreg, _, debug-location !43 + %r1 = MOVr killed %r4, 14, %noreg, _, debug-location !43 + %sp = LDMIA_UPD %sp, 14, %noreg, def %r4, def %r5, def %r6, def %r7, def %r11, def %lr, debug-location !43 TAILJMPd @func2, implicit %sp, implicit %sp, implicit killed %r0, implicit killed %r1, debug-location !43 ... diff --git a/test/CodeGen/ARM/deprecated-asm.s b/test/CodeGen/ARM/deprecated-asm.s index 7318e6a68c5a9..465da40c1c145 100644 --- a/test/CodeGen/ARM/deprecated-asm.s +++ b/test/CodeGen/ARM/deprecated-asm.s @@ -25,7 +25,7 @@ .type foo,%function foo: @ @foo .fnstart -@ BB#0: @ %entry +@ %bb.0: @ %entry mov r0, #0 bx lr stmia r4!, {r12-r14} diff --git a/test/CodeGen/ARM/emutls_generic.ll b/test/CodeGen/ARM/emutls_generic.ll index f5633dc23bcde..8c1c40dd6eace 100644 --- a/test/CodeGen/ARM/emutls_generic.ll +++ b/test/CodeGen/ARM/emutls_generic.ll @@ -6,6 +6,10 @@ ; RUN: | FileCheck -check-prefix=ARM_32 %s ; RUN: llc < %s -emulated-tls -mtriple=arm-linux-androidabi -O3 \ ; RUN: | FileCheck -check-prefix=ARM_32 %s +; RUN: llc < %s -emulated-tls -mtriple=arm-apple-darwin -O3 \ +; RUN: | FileCheck -check-prefix=DARWIN %s +; RUN: llc < %s -emulated-tls -mtriple=thumbv7-windows-gnu -O3 \ +; RUN: | FileCheck -check-prefix=WIN %s ; Make sure that TLS symbols are emitted in expected order. @@ -61,3 +65,74 @@ entry: ; ARM_32-LABEL: __emutls_t.internal_y: ; ARM_32-NEXT: .long 9 ; ARM_32-NEXT: .long 0 + +; WIN-LABEL: get_external_x: +; WIN: movw r0, :lower16:__emutls_v.external_x +; WIN: movt r0, :upper16:__emutls_v.external_x +; WIN: bl __emutls_get_address +; WIN-LABEL: get_external_y: +; WIN: movw r0, :lower16:__emutls_v.external_y +; WIN: movt r0, :upper16:__emutls_v.external_y +; WIN: bl __emutls_get_address +; WIN-LABEL: get_internal_y: +; WIN: movw r0, :lower16:__emutls_v.internal_y +; WIN: movt r0, :upper16:__emutls_v.internal_y +; WIN: bl __emutls_get_address +; WIN-NOT: __emutls_t.external_x +; WIN-NOT: __emutls_v.external_x: +; WIN: .data{{$}} +; WIN: .globl __emutls_v.external_y +; WIN: .p2align 2 +; WIN-LABEL: __emutls_v.external_y: +; WIN-NEXT: .long 1 +; WIN-NEXT: .long 2 +; WIN-NEXT: .long 0 +; WIN-NEXT: .long __emutls_t.external_y +; WIN: .section .rdata, +; WIN-LABEL: __emutls_t.external_y: +; WIN-NEXT: .byte 7 +; WIN: .data{{$}} +; WIN-NOT: .globl +; WIN: .p2align 2 +; WIN-LABEL: __emutls_v.internal_y: +; WIN-NEXT: .long 8 +; WIN-NEXT: .long 16 +; WIN-NEXT: .long 0 +; WIN-NEXT: .long __emutls_t.internal_y +; WIN-LABEL: __emutls_t.internal_y: +; .quad 9 is equivalent to .long 9 .long 0 +; WIN-NEXT: .quad 9 + +; DARWIN-LABEL: _get_external_x: +; DARWIN: bl ___emutls_get_address +; DARWIN: .long L___emutls_v.external_x$non_lazy_ptr-(LPC0_0+8) +; DARWIN-LABEL: _get_external_y: +; DARWIN: bl ___emutls_get_address +; DARWIN: .long ___emutls_v.external_y-(LPC1_0+8) +; DARWIN-LABEL: _get_internal_y: +; DARWIN: bl ___emutls_get_address +; DARWIN: .long ___emutls_v.internal_y-(LPC2_0+8) +; DARWIN-NOT: ___emutls_t.external_x +; DARWIN-NOT: ___emutls_v.external_x: +; DARWIN: .section __DATA,__data +; DARWIN: .globl ___emutls_v.external_y +; DARWIN: .p2align 2 +; DARWIN-LABEL: ___emutls_v.external_y: +; DARWIN-NEXT: .long 1 +; DARWIN-NEXT: .long 2 +; DARWIN-NEXT: .long 0 +; DARWIN-NEXT: .long ___emutls_t.external_y +; DARWIN: .section __TEXT,__const +; DARWIN-LABEL: ___emutls_t.external_y: +; DARWIN-NEXT: .byte 7 +; DARWIN: .section __DATA,__data +; DARWIN-NOT: .globl +; DARWIN: .p2align 2 +; DARWIN-LABEL: ___emutls_v.internal_y: +; DARWIN-NEXT: .long 8 +; DARWIN-NEXT: .long 16 +; DARWIN-NEXT: .long 0 +; DARWIN-NEXT: .long ___emutls_t.internal_y +; DARWIN-LABEL: ___emutls_t.internal_y: +; DARWIN-NEXT: .long 9 +; DARWIN-NEXT: .long 0 diff --git a/test/CodeGen/ARM/expand-pseudos.mir b/test/CodeGen/ARM/expand-pseudos.mir index 1cc46bc0f55d7..b35c2dce66da6 100644 --- a/test/CodeGen/ARM/expand-pseudos.mir +++ b/test/CodeGen/ARM/expand-pseudos.mir @@ -25,11 +25,11 @@ body: | bb.0.entry: liveins: %r0 - %r1 = MOVi 2, 14, _, _ - CMPri killed %r0, 0, 14, _, implicit-def %cpsr + %r1 = MOVi 2, 14, %noreg, %noreg + CMPri killed %r0, 0, 14, %noreg, implicit-def %cpsr %r1 = MOVCCi16 killed %r1, 500, 0, killed %cpsr - %r0 = MOVr killed %r1, 14, _, _ - BX_RET 14, _, implicit %r0 + %r0 = MOVr killed %r1, 14, %noreg, %noreg + BX_RET 14, %noreg, implicit %r0 ... --- @@ -42,11 +42,11 @@ body: | bb.0.entry: liveins: %r0 - %r1 = MOVi 2, 14, _, _ - CMPri killed %r0, 0, 14, _, implicit-def %cpsr + %r1 = MOVi 2, 14, %noreg, %noreg + CMPri killed %r0, 0, 14, %noreg, implicit-def %cpsr %r1 = MOVCCi32imm killed %r1, 500500500, 0, killed %cpsr - %r0 = MOVr killed %r1, 14, _, _ - BX_RET 14, _, implicit %r0 + %r0 = MOVr killed %r1, 14, %noreg, %noreg + BX_RET 14, %noreg, implicit %r0 ... --- @@ -60,9 +60,9 @@ body: | bb.0.entry: liveins: %r0, %r1 - CMPri %r1, 500, 14, _, implicit-def %cpsr + CMPri %r1, 500, 14, %noreg, implicit-def %cpsr %r0 = MOVCCr killed %r0, killed %r1, 12, killed %cpsr - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... @@ -72,4 +72,4 @@ body: | # CHECK: %r1 = MOVi16 2068, 0, %cpsr, implicit killed %r1 # CHECK: %r1 = MOVTi16 %r1, 7637, 0, %cpsr # CHECK-LABEL: name: test3 -# CHECK: %r0 = MOVr killed %r1, 12, killed %cpsr, _, implicit killed %r0 +# CHECK: %r0 = MOVr killed %r1, 12, killed %cpsr, %noreg, implicit killed %r0 diff --git a/test/CodeGen/ARM/fpoffset_overflow.mir b/test/CodeGen/ARM/fpoffset_overflow.mir index 4f3524bf7d117..59d981a436eb6 100644 --- a/test/CodeGen/ARM/fpoffset_overflow.mir +++ b/test/CodeGen/ARM/fpoffset_overflow.mir @@ -3,10 +3,10 @@ # This should trigger an emergency spill in the register scavenger because the # frame offset into the large argument is too large. # CHECK-LABEL: name: func0 -# CHECK: t2STRi12 killed [[SPILLED:%r[0-9]+]], %sp, 0, 14, _ :: (store 4 into %stack.0) -# CHECK: [[SPILLED]] = t2ADDri killed %sp, 4096, 14, _, _ -# CHECK: %sp = t2LDRi12 killed [[SPILLED]], 40, 14, _ :: (load 4) -# CHECK: [[SPILLED]] = t2LDRi12 %sp, 0, 14, _ :: (load 4 from %stack.0) +# CHECK: t2STRi12 killed [[SPILLED:%r[0-9]+]], %sp, 0, 14, %noreg :: (store 4 into %stack.0) +# CHECK: [[SPILLED]] = t2ADDri killed %sp, 4096, 14, %noreg, %noreg +# CHECK: %sp = t2LDRi12 killed [[SPILLED]], 40, 14, %noreg :: (load 4) +# CHECK: [[SPILLED]] = t2LDRi12 %sp, 0, 14, %noreg :: (load 4 from %stack.0) name: func0 tracksRegLiveness: true fixedStack: @@ -31,7 +31,7 @@ body: | %r12 = IMPLICIT_DEF %lr = IMPLICIT_DEF - %sp = t2LDRi12 %fixed-stack.0, 0, 14, _ :: (load 4) + %sp = t2LDRi12 %fixed-stack.0, 0, 14, %noreg :: (load 4) KILL %r0 KILL %r1 @@ -53,7 +53,7 @@ body: | # CHECK-LABEL: name: func1 # CHECK-NOT: t2STRi12 # CHECK-NOT: t2ADDri -# CHECK: %r11 = t2LDRi12 %sp, 4092, 14, _ :: (load 4) +# CHECK: %r11 = t2LDRi12 %sp, 4092, 14, %noreg :: (load 4) # CHECK-NOT: t2LDRi12 name: func1 tracksRegLiveness: true @@ -78,7 +78,7 @@ body: | %r12 = IMPLICIT_DEF %lr = IMPLICIT_DEF - %r11 = t2LDRi12 %fixed-stack.0, 0, 14, _ :: (load 4) + %r11 = t2LDRi12 %fixed-stack.0, 0, 14, %noreg :: (load 4) KILL %r0 KILL %r1 diff --git a/test/CodeGen/ARM/ifcvt-branch-weight-bug.ll b/test/CodeGen/ARM/ifcvt-branch-weight-bug.ll index 1c8142e5ddd51..b69f121d10ce5 100644 --- a/test/CodeGen/ARM/ifcvt-branch-weight-bug.ll +++ b/test/CodeGen/ARM/ifcvt-branch-weight-bug.ll @@ -21,8 +21,8 @@ entry: ; Afer if conversion, we have ; for.body -> for.cond.backedge (100%) ; -> cond.false.i (0%) -; CHECK: BB#1: derived from LLVM BB %for.body -; CHECK: Successors according to CFG: BB#2(0x80000000 / 0x80000000 = 100.00%) BB#4(0x00000001 / 0x80000000 = 0.00%) +; CHECK: %bb.1: derived from LLVM BB %for.body +; CHECK: Successors according to CFG: %bb.2(0x80000000 / 0x80000000 = 100.00%) %bb.4(0x00000001 / 0x80000000 = 0.00%) for.body: br i1 undef, label %for.cond.backedge, label %lor.lhs.false.i, !prof !1 diff --git a/test/CodeGen/ARM/ifcvt-branch-weight.ll b/test/CodeGen/ARM/ifcvt-branch-weight.ll index 5c39d63fda100..6f6f8bc1834a3 100644 --- a/test/CodeGen/ARM/ifcvt-branch-weight.ll +++ b/test/CodeGen/ARM/ifcvt-branch-weight.ll @@ -18,8 +18,8 @@ bb: %9 = icmp eq i32 %8, 0 br i1 %9, label %return, label %bb2 -; CHECK: BB#2: derived from LLVM BB %bb2 -; CHECK: Successors according to CFG: BB#4({{[0-9a-fx/= ]+}}50.00%) BB#3({{[0-9a-fx/= ]+}}50.00%) +; CHECK: %bb.2: derived from LLVM BB %bb2 +; CHECK: Successors according to CFG: %bb.4({{[0-9a-fx/= ]+}}50.00%) %bb.3({{[0-9a-fx/= ]+}}50.00%) bb2: %v10 = icmp eq i32 %3, 16 diff --git a/test/CodeGen/ARM/ifcvt-iter-indbr.ll b/test/CodeGen/ARM/ifcvt-iter-indbr.ll index 7349625730615..ccc6ded49f132 100644 --- a/test/CodeGen/ARM/ifcvt-iter-indbr.ll +++ b/test/CodeGen/ARM/ifcvt-iter-indbr.ll @@ -30,10 +30,10 @@ declare i8* @bar(i32, i8*, i8*) ; CHECK-NEXT: [[FOOCALL]]: ; CHECK-NEXT: bl _foo ; -; CHECK-PROB: BB#0: -; CHECK-PROB: Successors according to CFG: BB#1({{[0-9a-fx/= ]+}}50.00%) BB#3({{[0-9a-fx/= ]+}}25.00%) BB#5({{[0-9a-fx/= ]+}}25.00%) -; CHECK-PROB: BB#2: -; CHECK-PROB: Successors according to CFG: BB#3({{[0-9a-fx/= ]+}}50.00%) BB#5({{[0-9a-fx/= ]+}}50.00%) +; CHECK-PROB: %bb.0: +; CHECK-PROB: Successors according to CFG: %bb.1({{[0-9a-fx/= ]+}}50.00%) %bb.3({{[0-9a-fx/= ]+}}25.00%) %bb.5({{[0-9a-fx/= ]+}}25.00%) +; CHECK-PROB: %bb.2: +; CHECK-PROB: Successors according to CFG: %bb.3({{[0-9a-fx/= ]+}}50.00%) %bb.5({{[0-9a-fx/= ]+}}50.00%) define i32 @test(i32 %a, i32 %a2, i32* %p, i32* %p2) "no-frame-pointer-elim"="true" { entry: diff --git a/test/CodeGen/ARM/illegal-bitfield-loadstore.ll b/test/CodeGen/ARM/illegal-bitfield-loadstore.ll index 6d62fd31f978c..6f1e18ffdfca2 100644 --- a/test/CodeGen/ARM/illegal-bitfield-loadstore.ll +++ b/test/CodeGen/ARM/illegal-bitfield-loadstore.ll @@ -4,14 +4,14 @@ define void @i24_or(i24* %a) { ; LE-LABEL: i24_or: -; LE: @ BB#0: +; LE: @ %bb.0: ; LE-NEXT: ldrh r1, [r0] ; LE-NEXT: orr r1, r1, #384 ; LE-NEXT: strh r1, [r0] ; LE-NEXT: mov pc, lr ; ; BE-LABEL: i24_or: -; BE: @ BB#0: +; BE: @ %bb.0: ; BE-NEXT: ldrh r1, [r0] ; BE-NEXT: ldrb r2, [r0, #2] ; BE-NEXT: orr r1, r2, r1, lsl #8 @@ -28,7 +28,7 @@ define void @i24_or(i24* %a) { define void @i24_and_or(i24* %a) { ; LE-LABEL: i24_and_or: -; LE: @ BB#0: +; LE: @ %bb.0: ; LE-NEXT: ldrh r1, [r0] ; LE-NEXT: mov r2, #16256 ; LE-NEXT: orr r2, r2, #49152 @@ -38,7 +38,7 @@ define void @i24_and_or(i24* %a) { ; LE-NEXT: mov pc, lr ; ; BE-LABEL: i24_and_or: -; BE: @ BB#0: +; BE: @ %bb.0: ; BE-NEXT: mov r1, #128 ; BE-NEXT: strb r1, [r0, #2] ; BE-NEXT: ldrh r1, [r0] @@ -54,7 +54,7 @@ define void @i24_and_or(i24* %a) { define void @i24_insert_bit(i24* %a, i1 zeroext %bit) { ; LE-LABEL: i24_insert_bit: -; LE: @ BB#0: +; LE: @ %bb.0: ; LE-NEXT: mov r3, #255 ; LE-NEXT: ldrh r2, [r0] ; LE-NEXT: orr r3, r3, #57088 @@ -64,7 +64,7 @@ define void @i24_insert_bit(i24* %a, i1 zeroext %bit) { ; LE-NEXT: mov pc, lr ; ; BE-LABEL: i24_insert_bit: -; BE: @ BB#0: +; BE: @ %bb.0: ; BE-NEXT: ldrh r2, [r0] ; BE-NEXT: mov r3, #57088 ; BE-NEXT: orr r3, r3, #16711680 @@ -84,14 +84,14 @@ define void @i24_insert_bit(i24* %a, i1 zeroext %bit) { define void @i56_or(i56* %a) { ; LE-LABEL: i56_or: -; LE: @ BB#0: +; LE: @ %bb.0: ; LE-NEXT: ldr r1, [r0] ; LE-NEXT: orr r1, r1, #384 ; LE-NEXT: str r1, [r0] ; LE-NEXT: mov pc, lr ; ; BE-LABEL: i56_or: -; BE: @ BB#0: +; BE: @ %bb.0: ; BE-NEXT: mov r1, r0 ; BE-NEXT: ldr r12, [r0] ; BE-NEXT: ldrh r2, [r1, #4]! @@ -114,7 +114,7 @@ define void @i56_or(i56* %a) { define void @i56_and_or(i56* %a) { ; LE-LABEL: i56_and_or: -; LE: @ BB#0: +; LE: @ %bb.0: ; LE-NEXT: ldr r1, [r0] ; LE-NEXT: orr r1, r1, #384 ; LE-NEXT: bic r1, r1, #127 @@ -122,7 +122,7 @@ define void @i56_and_or(i56* %a) { ; LE-NEXT: mov pc, lr ; ; BE-LABEL: i56_and_or: -; BE: @ BB#0: +; BE: @ %bb.0: ; BE-NEXT: mov r1, r0 ; BE-NEXT: ldr r12, [r0] ; BE-NEXT: ldrh r2, [r1, #4]! @@ -147,7 +147,7 @@ define void @i56_and_or(i56* %a) { define void @i56_insert_bit(i56* %a, i1 zeroext %bit) { ; LE-LABEL: i56_insert_bit: -; LE: @ BB#0: +; LE: @ %bb.0: ; LE-NEXT: ldr r2, [r0] ; LE-NEXT: bic r2, r2, #8192 ; LE-NEXT: orr r1, r2, r1, lsl #13 @@ -155,7 +155,7 @@ define void @i56_insert_bit(i56* %a, i1 zeroext %bit) { ; LE-NEXT: mov pc, lr ; ; BE-LABEL: i56_insert_bit: -; BE: @ BB#0: +; BE: @ %bb.0: ; BE-NEXT: .save {r11, lr} ; BE-NEXT: push {r11, lr} ; BE-NEXT: mov r2, r0 diff --git a/test/CodeGen/ARM/imm-peephole-arm.mir b/test/CodeGen/ARM/imm-peephole-arm.mir index 95ae58ff9bdb6..0457507eb448b 100644 --- a/test/CodeGen/ARM/imm-peephole-arm.mir +++ b/test/CodeGen/ARM/imm-peephole-arm.mir @@ -42,18 +42,18 @@ body: | %0 = COPY %r0 %1 = MOVi32imm -25733 - %2 = SUBrr %0, killed %1, 14, _, _ + %2 = SUBrr %0, killed %1, 14, %noreg, %noreg %3 = MOVi32imm 25733 - %4 = SUBrr %0, killed %3, 14, _, _ + %4 = SUBrr %0, killed %3, 14, %noreg, %noreg %5 = MOVi32imm -25733 - %6 = ADDrr %0, killed %5, 14, _, _ + %6 = ADDrr %0, killed %5, 14, %noreg, %noreg %7 = MOVi32imm 25733 - %8 = ADDrr killed %0, killed %7, 14, _, _ + %8 = ADDrr killed %0, killed %7, 14, %noreg, %noreg %r0 = COPY killed %8 - BX_RET 14, _, implicit %r0 + BX_RET 14, %noreg, implicit %r0 ... diff --git a/test/CodeGen/ARM/imm-peephole-thumb.mir b/test/CodeGen/ARM/imm-peephole-thumb.mir index 553717ba74ac5..04e2b193e96c2 100644 --- a/test/CodeGen/ARM/imm-peephole-thumb.mir +++ b/test/CodeGen/ARM/imm-peephole-thumb.mir @@ -41,18 +41,18 @@ body: | liveins: %r0 %0 = COPY %r0 %1 = t2MOVi32imm -25733 - %2 = t2SUBrr %0, killed %1, 14, _, _ + %2 = t2SUBrr %0, killed %1, 14, %noreg, %noreg %3 = t2MOVi32imm 25733 - %4 = t2SUBrr %0, killed %3, 14, _, _ + %4 = t2SUBrr %0, killed %3, 14, %noreg, %noreg %5 = t2MOVi32imm -25733 - %6= t2ADDrr %0, killed %5, 14, _, _ + %6= t2ADDrr %0, killed %5, 14, %noreg, %noreg %7 = t2MOVi32imm 25733 - %8 = t2ADDrr killed %0, killed %7, 14, _, _ + %8 = t2ADDrr killed %0, killed %7, 14, %noreg, %noreg %r0 = COPY killed %8 - tBX_RET 14, _, implicit %r0 + tBX_RET 14, %noreg, implicit %r0 ... diff --git a/test/CodeGen/ARM/indirect-hidden.ll b/test/CodeGen/ARM/indirect-hidden.ll index ae1c505bb683b..eb0302834879a 100644 --- a/test/CodeGen/ARM/indirect-hidden.ll +++ b/test/CodeGen/ARM/indirect-hidden.ll @@ -19,4 +19,4 @@ define i32* @get_var_hidden() { ; CHECK-NOT: __DATA,__data ; CHECK: .indirect_symbol _var_hidden -; CHECK-NEXT: .long 0 \ No newline at end of file +; CHECK-NEXT: .long 0 diff --git a/test/CodeGen/ARM/jump-table-tbh.ll b/test/CodeGen/ARM/jump-table-tbh.ll index b3ee68ea0758a..ab2c579e514ea 100644 --- a/test/CodeGen/ARM/jump-table-tbh.ll +++ b/test/CodeGen/ARM/jump-table-tbh.ll @@ -10,7 +10,7 @@ define i32 @test_tbh(i1 %tst, i32 %sw, i32 %l) { ; T2-LABEL: test_tbh: ; T2: [[ANCHOR:.LCPI[0-9_]+]]: ; T2: tbh [pc, r{{[0-9]+}}, lsl #1] -; T2-NEXT: @ BB#{{[0-9]+}} +; T2-NEXT: @ %bb.{{[0-9]+}} ; T2-NEXT: LJTI ; T2-NEXT: .short (.LBB0_[[x:[0-9]+]]-([[ANCHOR]]+4))/2 ; T2-NEXT: .short (.LBB0_{{[0-9]+}}-([[ANCHOR]]+4))/2 @@ -24,7 +24,7 @@ define i32 @test_tbh(i1 %tst, i32 %sw, i32 %l) { ; T1: lsls [[x]], [[x]], #1 ; T1: [[ANCHOR:.LCPI[0-9_]+]]: ; T1: add pc, [[x]] -; T1-NEXT: @ BB#2 +; T1-NEXT: @ %bb.2 ; T1-NEXT: .p2align 2 ; T1-NEXT: LJTI ; T1-NEXT: .short (.LBB0_[[x:[0-9]+]]-([[ANCHOR]]+4))/2 diff --git a/test/CodeGen/ARM/litpool-licm.ll b/test/CodeGen/ARM/litpool-licm.ll index dc6b37feaf05a..923971d1afe19 100644 --- a/test/CodeGen/ARM/litpool-licm.ll +++ b/test/CodeGen/ARM/litpool-licm.ll @@ -43,4 +43,4 @@ done: ret void } -declare void @foo(i32*) \ No newline at end of file +declare void @foo(i32*) diff --git a/test/CodeGen/ARM/load_store_opt_kill.mir b/test/CodeGen/ARM/load_store_opt_kill.mir index 4c210eaf8e9fd..85cc5953d1dcd 100644 --- a/test/CodeGen/ARM/load_store_opt_kill.mir +++ b/test/CodeGen/ARM/load_store_opt_kill.mir @@ -3,8 +3,8 @@ # CHECK-LABEL: name: f name: f # Make sure the load into %r0 doesn't clobber the base register before the second load uses it. -# CHECK: %r3 = LDRi12 %r0, 12, 14, _ -# CHECK-NEXT: %r0 = LDRi12 %r0, 8, 14, _ +# CHECK: %r3 = LDRi12 %r0, 12, 14, %noreg +# CHECK-NEXT: %r0 = LDRi12 %r0, 8, 14, %noreg body: | bb.0: liveins: %r0, %r3 diff --git a/test/CodeGen/ARM/local-call.ll b/test/CodeGen/ARM/local-call.ll index a38df62ff905c..c07294685e924 100644 --- a/test/CodeGen/ARM/local-call.ll +++ b/test/CodeGen/ARM/local-call.ll @@ -17,4 +17,4 @@ define i64 @test_local_call(i64 %a, i64 %b) { %res = udiv i64 %a, %b ret i64 %res -} \ No newline at end of file +} diff --git a/test/CodeGen/ARM/machine-copyprop.mir b/test/CodeGen/ARM/machine-copyprop.mir index 9be595f690dbc..bb9c3478d8b4e 100644 --- a/test/CodeGen/ARM/machine-copyprop.mir +++ b/test/CodeGen/ARM/machine-copyprop.mir @@ -3,20 +3,20 @@ # Test that machine copy prop recognizes the implicit-def operands on a COPY # as clobbering the register. # CHECK-LABEL: name: func -# CHECK: %d2 = VMOVv2i32 2, 14, _ +# CHECK: %d2 = VMOVv2i32 2, 14, %noreg # CHECK: %s5 = COPY %s0, implicit %q1, implicit-def %q1 -# CHECK: VST1q32 %r0, 0, %q1, 14, _ +# CHECK: VST1q32 %r0, 0, %q1, 14, %noreg # The following two COPYs must not be removed # CHECK: %s4 = COPY %s20, implicit-def %q1 # CHECK: %s5 = COPY %s0, implicit killed %d0, implicit %q1, implicit-def %q1 -# CHECK: VST1q32 %r2, 0, %q1, 14, _ +# CHECK: VST1q32 %r2, 0, %q1, 14, %noreg name: func body: | bb.0: - %d2 = VMOVv2i32 2, 14, _ + %d2 = VMOVv2i32 2, 14, %noreg %s5 = COPY %s0, implicit %q1, implicit-def %q1 - VST1q32 %r0, 0, %q1, 14, _ + VST1q32 %r0, 0, %q1, 14, %noreg %s4 = COPY %s20, implicit-def %q1 %s5 = COPY %s0, implicit killed %d0, implicit %q1, implicit-def %q1 - VST1q32 %r2, 0, %q1, 14, _ + VST1q32 %r2, 0, %q1, 14, %noreg ... diff --git a/test/CodeGen/ARM/machine-licm.ll b/test/CodeGen/ARM/machine-licm.ll index a1eec78e453f7..9ed1a57616c9b 100644 --- a/test/CodeGen/ARM/machine-licm.ll +++ b/test/CodeGen/ARM/machine-licm.ll @@ -31,7 +31,7 @@ bb.nph: ; preds = %entry ; ARM-NOT: LCPI0_1: ; ARM: .section -; THUMB: BB#1 +; THUMB: %bb.1 ; THUMB: ldr r2, LCPI0_0 ; THUMB: add r2, pc ; THUMB: ldr r{{[0-9]+}}, [r2] diff --git a/test/CodeGen/ARM/misched-copy-arm.ll b/test/CodeGen/ARM/misched-copy-arm.ll index 53f8b8d15042d..ae0b127a6f8e7 100644 --- a/test/CodeGen/ARM/misched-copy-arm.ll +++ b/test/CodeGen/ARM/misched-copy-arm.ll @@ -4,7 +4,7 @@ ; Loop counter copies should be eliminated. ; There is also a MUL here, but we don't care where it is scheduled. ; CHECK: postinc -; CHECK: *** Final schedule for BB#2 *** +; CHECK: *** Final schedule for %bb.2 *** ; CHECK: t2LDRs ; CHECK: t2ADDrr ; CHECK: t2CMPrr @@ -32,10 +32,10 @@ for.end: ; preds = %for.body, %entry ; This case was a crasher in constrainLocalCopy. ; The problem was the t2LDR_PRE defining both the global and local lrg. -; CHECK-LABEL: *** Final schedule for BB#5 *** -; CHECK: %[[R4:vreg[0-9]+]], %[[R1:vreg[0-9]+]] = t2LDR_PRE %[[R1]] -; CHECK: %vreg{{[0-9]+}} = COPY %[[R1]] -; CHECK: %vreg{{[0-9]+}} = COPY %[[R4]] +; CHECK-LABEL: *** Final schedule for %bb.5 *** +; CHECK: %[[R4:[0-9]+]], %[[R1:[0-9]+]] = t2LDR_PRE %[[R1]] +; CHECK: %{{[0-9]+}} = COPY %[[R1]] +; CHECK: %{{[0-9]+}} = COPY %[[R4]] ; CHECK-LABEL: MACHINEINSTRS %struct.rtx_def = type { [4 x i8], [1 x %union.rtunion_def] } %union.rtunion_def = type { i64 } diff --git a/test/CodeGen/ARM/misched-int-basic-thumb2.mir b/test/CodeGen/ARM/misched-int-basic-thumb2.mir index 32d1e03d9a1bb..4048f1122d1fc 100644 --- a/test/CodeGen/ARM/misched-int-basic-thumb2.mir +++ b/test/CodeGen/ARM/misched-int-basic-thumb2.mir @@ -37,62 +37,62 @@ } # # CHECK: ********** MI Scheduling ********** -# CHECK: SU(2): %vreg2 = t2MOVi32imm ; rGPR:%vreg2 +# CHECK: SU(2): %2 = t2MOVi32imm ; rGPR:%2 # CHECK_A9: Latency : 2 # CHECK_SWIFT: Latency : 2 # CHECK_R52: Latency : 2 # -# CHECK: SU(3): %vreg3 = t2LDRi12 %vreg2, 0, pred:14, pred:%noreg; mem:LD4[@g1](dereferenceable) rGPR:%vreg3,%vreg2 +# CHECK: SU(3): %3 = t2LDRi12 %2, 0, pred:14, pred:%noreg; mem:LD4[@g1](dereferenceable) rGPR:%3,%2 # CHECK_A9: Latency : 1 # CHECK_SWIFT: Latency : 3 # CHECK_R52: Latency : 4 # -# CHECK : SU(6): %vreg6 = t2ADDrr %vreg3, %vreg3, pred:14, pred:%noreg, opt:%noreg; rGPR:%vreg6,%vreg3,%vreg3 +# CHECK : SU(6): %6 = t2ADDrr %3, %3, pred:14, pred:%noreg, opt:%noreg; rGPR:%6,%3,%3 # CHECK_A9: Latency : 1 # CHECK_SWIFT: Latency : 1 # CHECK_R52: Latency : 3 -# CHECK: SU(7): %vreg7 = t2SDIV %vreg6, %vreg5, pred:14, pred:%noreg; rGPR:%vreg7,%vreg6,%vreg5 +# CHECK: SU(7): %7 = t2SDIV %6, %5, pred:14, pred:%noreg; rGPR:%7,%6,%5 # CHECK_A9: Latency : 0 # CHECK_SWIFT: Latency : 14 # CHECK_R52: Latency : 8 -# CHECK: SU(8): t2STRi12 %vreg7, %vreg2, 0, pred:14, pred:%noreg; mem:ST4[@g1] rGPR:%vreg7,%vreg2 +# CHECK: SU(8): t2STRi12 %7, %2, 0, pred:14, pred:%noreg; mem:ST4[@g1] rGPR:%7,%2 # CHECK_A9: Latency : 1 # CHECK_SWIFT: Latency : 0 # CHECK_R52: Latency : 4 # -# CHECK: SU(9): %vreg8 = t2SMULBB %vreg1, %vreg1, pred:14, pred:%noreg; rGPR:%vreg8,%vreg1,%vreg1 +# CHECK: SU(9): %8 = t2SMULBB %1, %1, pred:14, pred:%noreg; rGPR:%8,%1,%1 # CHECK_A9: Latency : 2 # CHECK_SWIFT: Latency : 4 # CHECK_R52: Latency : 4 # -# CHECK: SU(10): %vreg9 = t2SMLABB %vreg0, %vreg0, %vreg8, pred:14, pred:%noreg; rGPR:%vreg9,%vreg0,%vreg0,%vreg8 +# CHECK: SU(10): %9 = t2SMLABB %0, %0, %8, pred:14, pred:%noreg; rGPR:%9,%0,%0,%8 # CHECK_A9: Latency : 2 # CHECK_SWIFT: Latency : 4 # CHECK_R52: Latency : 4 # -# CHECK: SU(11): %vreg10 = t2UXTH %vreg9, 0, pred:14, pred:%noreg; rGPR:%vreg10,%vreg9 +# CHECK: SU(11): %10 = t2UXTH %9, 0, pred:14, pred:%noreg; rGPR:%10,%9 # CHECK_A9: Latency : 1 # CHECK_SWIFT: Latency : 1 # CHECK_R52: Latency : 3 # -# CHECK: SU(12): %vreg11 = t2MUL %vreg10, %vreg7, pred:14, pred:%noreg; rGPR:%vreg11,%vreg10,%vreg7 +# CHECK: SU(12): %11 = t2MUL %10, %7, pred:14, pred:%noreg; rGPR:%11,%10,%7 # CHECK_A9: Latency : 2 # CHECK_SWIFT: Latency : 4 # CHECK_R52: Latency : 4 # -# CHECK: SU(13): %vreg12 = t2MLA %vreg11, %vreg11, %vreg11, pred:14, pred:%noreg; rGPR:%vreg12,%vreg11,%vreg11,%vreg11 +# CHECK: SU(13): %12 = t2MLA %11, %11, %11, pred:14, pred:%noreg; rGPR:%12,%11,%11,%11 # CHECK_A9: Latency : 2 # CHECK_SWIFT: Latency : 4 # CHECK_R52: Latency : 4 # -# CHECK: SU(14): %vreg13, %vreg14 = t2UMULL %vreg12, %vreg12, pred:14, pred:%noreg; rGPR:%vreg13,%vreg14,%vreg12,%vreg12 +# CHECK: SU(14): %13, %14 = t2UMULL %12, %12, pred:14, pred:%noreg; rGPR:%13,%14,%12,%12 # CHECK_A9: Latency : 3 # CHECK_SWIFT: Latency : 5 # CHECK_R52: Latency : 4 # -# CHECK: SU(18): %vreg19, %vreg20 = t2UMLAL %vreg12, %vreg12, %vreg19, %vreg20, pred:14, pred:%noreg; rGPR:%vreg19,%vreg20,%vreg12,%vreg12,%vreg20 +# CHECK: SU(18): %19, %20 = t2UMLAL %12, %12, %19, %20, pred:14, pred:%noreg; rGPR:%19,%20,%12,%12,%20 # CHECK_A9: Latency : 3 # CHECK_SWIFT: Latency : 7 # CHECK_R52: Latency : 4 @@ -152,24 +152,24 @@ body: | %1 = COPY %r1 %0 = COPY %r0 %2 = t2MOVi32imm @g1 - %3 = t2LDRi12 %2, 0, 14, _ :: (dereferenceable load 4 from @g1) + %3 = t2LDRi12 %2, 0, 14, %noreg :: (dereferenceable load 4 from @g1) %4 = t2MOVi32imm @g2 - %5 = t2LDRi12 %4, 0, 14, _ :: (dereferenceable load 4 from @g2) - %6 = t2ADDrr %3, %3, 14, _, _ - %7 = t2SDIV %6, %5, 14, _ - t2STRi12 %7, %2, 0, 14, _ :: (store 4 into @g1) - %8 = t2SMULBB %1, %1, 14, _ - %9 = t2SMLABB %0, %0, %8, 14, _ - %10 = t2UXTH %9, 0, 14, _ - %11 = t2MUL %10, %7, 14, _ - %12 = t2MLA %11, %11, %11, 14, _ - %13, %14 = t2UMULL %12, %12, 14, _ - %19, %16 = t2UMULL %13, %13, 14, _ - %17 = t2MLA %13, %14, %16, 14, _ - %20 = t2MLA %13, %14, %17, 14, _ - %19, %20 = t2UMLAL %12, %12, %19, %20, 14, _ + %5 = t2LDRi12 %4, 0, 14, %noreg :: (dereferenceable load 4 from @g2) + %6 = t2ADDrr %3, %3, 14, %noreg, %noreg + %7 = t2SDIV %6, %5, 14, %noreg + t2STRi12 %7, %2, 0, 14, %noreg :: (store 4 into @g1) + %8 = t2SMULBB %1, %1, 14, %noreg + %9 = t2SMLABB %0, %0, %8, 14, %noreg + %10 = t2UXTH %9, 0, 14, %noreg + %11 = t2MUL %10, %7, 14, %noreg + %12 = t2MLA %11, %11, %11, 14, %noreg + %13, %14 = t2UMULL %12, %12, 14, %noreg + %19, %16 = t2UMULL %13, %13, 14, %noreg + %17 = t2MLA %13, %14, %16, 14, %noreg + %20 = t2MLA %13, %14, %17, 14, %noreg + %19, %20 = t2UMLAL %12, %12, %19, %20, 14, %noreg %r0 = COPY %19 %r1 = COPY %20 - tBX_RET 14, _, implicit %r0, implicit %r1 + tBX_RET 14, %noreg, implicit %r0, implicit %r1 ... diff --git a/test/CodeGen/ARM/misched-int-basic.mir b/test/CodeGen/ARM/misched-int-basic.mir index d5231269d732c..0cad54d975e15 100644 --- a/test/CodeGen/ARM/misched-int-basic.mir +++ b/test/CodeGen/ARM/misched-int-basic.mir @@ -28,37 +28,37 @@ } # CHECK: ********** MI Scheduling ********** -# CHECK: SU(2): %vreg2 = SMULBB %vreg1, %vreg1, pred:14, pred:%noreg; GPR:%vreg2,%vreg1,%vreg1 +# CHECK: SU(2): %2 = SMULBB %1, %1, pred:14, pred:%noreg; GPR:%2,%1,%1 # CHECK_A9: Latency : 2 # CHECK_SWIFT: Latency : 4 # CHECK_R52: Latency : 4 # -# CHECK: SU(3): %vreg3 = SMLABB %vreg0, %vreg0, %vreg2, pred:14, pred:%noreg; GPRnopc:%vreg3,%vreg0,%vreg0 GPR:%vreg2 +# CHECK: SU(3): %3 = SMLABB %0, %0, %2, pred:14, pred:%noreg; GPRnopc:%3,%0,%0 GPR:%2 # CHECK_A9: Latency : 2 # CHECK_SWIFT: Latency : 4 # CHECK_R52: Latency : 4 # -# CHECK: SU(4): %vreg4 = UXTH %vreg3, 0, pred:14, pred:%noreg; GPRnopc:%vreg4,%vreg3 +# CHECK: SU(4): %4 = UXTH %3, 0, pred:14, pred:%noreg; GPRnopc:%4,%3 # CHECK_A9: Latency : 1 # CHECK_SWIFT: Latency : 1 # CHECK_R52: Latency : 3 # -# CHECK: SU(5): %vreg5 = MUL %vreg4, %vreg4, pred:14, pred:%noreg, opt:%noreg; GPRnopc:%vreg5,%vreg4,%vreg4 +# CHECK: SU(5): %5 = MUL %4, %4, pred:14, pred:%noreg, opt:%noreg; GPRnopc:%5,%4,%4 # CHECK_A9: Latency : 2 # CHECK_SWIFT: Latency : 4 # CHECK_R52: Latency : 4 # -# CHECK: SU(6): %vreg6 = MLA %vreg5, %vreg5, %vreg5, pred:14, pred:%noreg, opt:%noreg; GPRnopc:%vreg6,%vreg5,%vreg5,%vreg5 +# CHECK: SU(6): %6 = MLA %5, %5, %5, pred:14, pred:%noreg, opt:%noreg; GPRnopc:%6,%5,%5,%5 # CHECK_A9: Latency : 2 # CHECK_SWIFT: Latency : 4 # CHECK_R52: Latency : 4 # -# CHECK: SU(7): %vreg7, %vreg8 = UMULL %vreg6, %vreg6, pred:14, pred:%noreg, opt:%noreg; GPRnopc:%vreg7,%vreg8,%vreg6,%vreg6 +# CHECK: SU(7): %7, %8 = UMULL %6, %6, pred:14, pred:%noreg, opt:%noreg; GPRnopc:%7,%8,%6,%6 # CHECK_A9: Latency : 3 # CHECK_SWIFT: Latency : 5 # CHECK_R52: Latency : 4 # -# CHECK: SU(11): %vreg13, %vreg14 = UMLAL %vreg6, %vreg6, %vreg13, %vreg14, pred:14, pred:%noreg, opt:%noreg; GPR:%vreg13 GPRnopc:%vreg14,%vreg6,%vreg6 +# CHECK: SU(11): %13, %14 = UMLAL %6, %6, %13, %14, pred:14, pred:%noreg, opt:%noreg; GPR:%13 GPRnopc:%14,%6,%6 # CHECK_SWIFT: Latency : 7 # CHECK_A9: Latency : 3 # CHECK_R52: Latency : 4 @@ -111,18 +111,18 @@ body: | %1 = COPY %r1 %0 = COPY %r0 - %2 = SMULBB %1, %1, 14, _ - %3 = SMLABB %0, %0, %2, 14, _ - %4 = UXTH %3, 0, 14, _ - %5 = MUL %4, %4, 14, _, _ - %6 = MLA %5, %5, %5, 14, _, _ - %7, %8 = UMULL %6, %6, 14, _, _ - %13, %10 = UMULL %7, %7, 14, _, _ - %11 = MLA %7, %8, %10, 14, _, _ - %14 = MLA %7, %8, %11, 14, _, _ - %13, %14 = UMLAL %6, %6, %13, %14, 14, _, _ + %2 = SMULBB %1, %1, 14, %noreg + %3 = SMLABB %0, %0, %2, 14, %noreg + %4 = UXTH %3, 0, 14, %noreg + %5 = MUL %4, %4, 14, %noreg, %noreg + %6 = MLA %5, %5, %5, 14, %noreg, %noreg + %7, %8 = UMULL %6, %6, 14, %noreg, %noreg + %13, %10 = UMULL %7, %7, 14, %noreg, %noreg + %11 = MLA %7, %8, %10, 14, %noreg, %noreg + %14 = MLA %7, %8, %11, 14, %noreg, %noreg + %13, %14 = UMLAL %6, %6, %13, %14, 14, %noreg, %noreg %r0 = COPY %13 %r1 = COPY %14 - BX_RET 14, _, implicit %r0, implicit %r1 + BX_RET 14, %noreg, implicit %r0, implicit %r1 ... diff --git a/test/CodeGen/ARM/negate-i1.ll b/test/CodeGen/ARM/negate-i1.ll index 0503763e674f2..493b26a5a8409 100644 --- a/test/CodeGen/ARM/negate-i1.ll +++ b/test/CodeGen/ARM/negate-i1.ll @@ -4,7 +4,7 @@ define i32 @select_i32_neg1_or_0(i1 %a) { ; CHECK-LABEL: select_i32_neg1_or_0: -; CHECK-NEXT: @ BB#0: +; CHECK-NEXT: @ %bb.0: ; CHECK-NEXT: and r0, r0, #1 ; CHECK-NEXT: rsb r0, r0, #0 ; CHECK-NEXT: mov pc, lr @@ -15,7 +15,7 @@ define i32 @select_i32_neg1_or_0(i1 %a) { define i32 @select_i32_neg1_or_0_zeroext(i1 zeroext %a) { ; CHECK-LABEL: select_i32_neg1_or_0_zeroext: -; CHECK-NEXT: @ BB#0: +; CHECK-NEXT: @ %bb.0: ; CHECK-NEXT: rsb r0, r0, #0 ; CHECK-NEXT: mov pc, lr ; diff --git a/test/CodeGen/ARM/neon_vabs.ll b/test/CodeGen/ARM/neon_vabs.ll index 109d09582afdc..4064aae65f665 100644 --- a/test/CodeGen/ARM/neon_vabs.ll +++ b/test/CodeGen/ARM/neon_vabs.ll @@ -3,7 +3,7 @@ define <4 x i32> @test1(<4 x i32> %a) nounwind { ; CHECK-LABEL: test1: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vmov d17, r2, r3 ; CHECK-NEXT: vmov d16, r0, r1 ; CHECK-NEXT: vabs.s32 q8, q8 @@ -18,7 +18,7 @@ define <4 x i32> @test1(<4 x i32> %a) nounwind { define <4 x i32> @test2(<4 x i32> %a) nounwind { ; CHECK-LABEL: test2: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vmov d17, r2, r3 ; CHECK-NEXT: vmov d16, r0, r1 ; CHECK-NEXT: vabs.s32 q8, q8 @@ -33,7 +33,7 @@ define <4 x i32> @test2(<4 x i32> %a) nounwind { define <8 x i16> @test3(<8 x i16> %a) nounwind { ; CHECK-LABEL: test3: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vmov d17, r2, r3 ; CHECK-NEXT: vmov d16, r0, r1 ; CHECK-NEXT: vabs.s16 q8, q8 @@ -48,7 +48,7 @@ define <8 x i16> @test3(<8 x i16> %a) nounwind { define <16 x i8> @test4(<16 x i8> %a) nounwind { ; CHECK-LABEL: test4: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vmov d17, r2, r3 ; CHECK-NEXT: vmov d16, r0, r1 ; CHECK-NEXT: vabs.s8 q8, q8 @@ -63,7 +63,7 @@ define <16 x i8> @test4(<16 x i8> %a) nounwind { define <4 x i32> @test5(<4 x i32> %a) nounwind { ; CHECK-LABEL: test5: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vmov d17, r2, r3 ; CHECK-NEXT: vmov d16, r0, r1 ; CHECK-NEXT: vabs.s32 q8, q8 @@ -78,7 +78,7 @@ define <4 x i32> @test5(<4 x i32> %a) nounwind { define <2 x i32> @test6(<2 x i32> %a) nounwind { ; CHECK-LABEL: test6: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vmov d16, r0, r1 ; CHECK-NEXT: vabs.s32 d16, d16 ; CHECK-NEXT: vmov r0, r1, d16 @@ -91,7 +91,7 @@ define <2 x i32> @test6(<2 x i32> %a) nounwind { define <2 x i32> @test7(<2 x i32> %a) nounwind { ; CHECK-LABEL: test7: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vmov d16, r0, r1 ; CHECK-NEXT: vabs.s32 d16, d16 ; CHECK-NEXT: vmov r0, r1, d16 @@ -104,7 +104,7 @@ define <2 x i32> @test7(<2 x i32> %a) nounwind { define <4 x i16> @test8(<4 x i16> %a) nounwind { ; CHECK-LABEL: test8: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vmov d16, r0, r1 ; CHECK-NEXT: vabs.s16 d16, d16 ; CHECK-NEXT: vmov r0, r1, d16 @@ -117,7 +117,7 @@ define <4 x i16> @test8(<4 x i16> %a) nounwind { define <8 x i8> @test9(<8 x i8> %a) nounwind { ; CHECK-LABEL: test9: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vmov d16, r0, r1 ; CHECK-NEXT: vabs.s8 d16, d16 ; CHECK-NEXT: vmov r0, r1, d16 @@ -130,7 +130,7 @@ define <8 x i8> @test9(<8 x i8> %a) nounwind { define <2 x i32> @test10(<2 x i32> %a) nounwind { ; CHECK-LABEL: test10: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vmov d16, r0, r1 ; CHECK-NEXT: vabs.s32 d16, d16 ; CHECK-NEXT: vmov r0, r1, d16 @@ -146,7 +146,7 @@ define <2 x i32> @test10(<2 x i32> %a) nounwind { define <4 x i32> @test11(<4 x i16> %a, <4 x i16> %b) nounwind { ; CHECK-LABEL: test11: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vmov d16, r2, r3 ; CHECK-NEXT: vmov d17, r0, r1 ; CHECK-NEXT: vabdl.u16 q8, d17, d16 @@ -163,7 +163,7 @@ define <4 x i32> @test11(<4 x i16> %a, <4 x i16> %b) nounwind { } define <8 x i16> @test12(<8 x i8> %a, <8 x i8> %b) nounwind { ; CHECK-LABEL: test12: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vmov d16, r2, r3 ; CHECK-NEXT: vmov d17, r0, r1 ; CHECK-NEXT: vabdl.u8 q8, d17, d16 @@ -181,7 +181,7 @@ define <8 x i16> @test12(<8 x i8> %a, <8 x i8> %b) nounwind { define <2 x i64> @test13(<2 x i32> %a, <2 x i32> %b) nounwind { ; CHECK-LABEL: test13: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vmov d16, r2, r3 ; CHECK-NEXT: vmov d17, r0, r1 ; CHECK-NEXT: vabdl.u32 q8, d17, d16 diff --git a/test/CodeGen/ARM/nest-register.ll b/test/CodeGen/ARM/nest-register.ll index 6b8c3dc47db10..ac7afe0007cd5 100644 --- a/test/CodeGen/ARM/nest-register.ll +++ b/test/CodeGen/ARM/nest-register.ll @@ -5,7 +5,7 @@ define i8* @nest_receiver(i8* nest %arg) nounwind { ; CHECK-LABEL: nest_receiver: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: mov r0, r12 ; CHECK-NEXT: mov pc, lr ret i8* %arg diff --git a/test/CodeGen/ARM/noopt-dmb-v7.ll b/test/CodeGen/ARM/noopt-dmb-v7.ll index 56a29c8a17e84..86b27600eb4b4 100644 --- a/test/CodeGen/ARM/noopt-dmb-v7.ll +++ b/test/CodeGen/ARM/noopt-dmb-v7.ll @@ -9,7 +9,7 @@ entry: ret i32 0 } -; CHECK: @ BB#0: @ %entry +; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: dmb ish ; CHECK-NEXT: dmb ish ; CHECK-NEXT: dmb ish diff --git a/test/CodeGen/ARM/pei-swiftself.mir b/test/CodeGen/ARM/pei-swiftself.mir index 055efeea32892..d2d3469458b73 100644 --- a/test/CodeGen/ARM/pei-swiftself.mir +++ b/test/CodeGen/ARM/pei-swiftself.mir @@ -39,7 +39,7 @@ body: | ; not just use %r10 for that. ; CHECK-NOT: STRi12 %1,{{.*}}%r10 - STRi12 %r1, %stack.0, 0, 14, _ :: (store 4) + STRi12 %r1, %stack.0, 0, 14, %noreg :: (store 4) ; use the swiftself parameter value. KILL %r10 diff --git a/test/CodeGen/ARM/pr25317.ll b/test/CodeGen/ARM/pr25317.ll index 6770c6f84ecd7..679b5a0299af7 100644 --- a/test/CodeGen/ARM/pr25317.ll +++ b/test/CodeGen/ARM/pr25317.ll @@ -8,4 +8,4 @@ target triple = "armv7--linux-gnueabihf" define void @f(i32* %p) { call void asm sideeffect "str lr, $0", "=*o"(i32* %p) ret void -} \ No newline at end of file +} diff --git a/test/CodeGen/ARM/preferred-align.ll b/test/CodeGen/ARM/preferred-align.ll index a9a17229e064b..26dbb1cbd5464 100644 --- a/test/CodeGen/ARM/preferred-align.ll +++ b/test/CodeGen/ARM/preferred-align.ll @@ -18,4 +18,4 @@ @var16 = global i16 zeroinitializer ; CHECK: .globl var16 -; CHECK-NEXT: .p2align 1 \ No newline at end of file +; CHECK-NEXT: .p2align 1 diff --git a/test/CodeGen/ARM/prera-ldst-aliasing.mir b/test/CodeGen/ARM/prera-ldst-aliasing.mir index ce37106ed8d2f..cc3200860796f 100644 --- a/test/CodeGen/ARM/prera-ldst-aliasing.mir +++ b/test/CodeGen/ARM/prera-ldst-aliasing.mir @@ -26,15 +26,15 @@ body: | %1 : gpr = COPY %r1 %0 : gpr = COPY %r0 - %2 : gpr = t2LDRi12 %1, 0, 14, _ :: (load 4 from %ir.y) - t2STRi12 killed %2, %0, 0, 14, _ :: (store 4 into %ir.x) - %3 : gpr = t2LDRi12 %1, 4, 14, _ :: (load 4 from %ir.arrayidx2) - t2STRi12 killed %3, %0, 4, 14, _ :: (store 4 into %ir.arrayidx3) + %2 : gpr = t2LDRi12 %1, 0, 14, %noreg :: (load 4 from %ir.y) + t2STRi12 killed %2, %0, 0, 14, %noreg :: (store 4 into %ir.x) + %3 : gpr = t2LDRi12 %1, 4, 14, %noreg :: (load 4 from %ir.arrayidx2) + t2STRi12 killed %3, %0, 4, 14, %noreg :: (store 4 into %ir.arrayidx3) ; CHECK: t2LDRi12 ; CHECK-NEXT: t2LDRi12 ; CHECK-NEXT: t2STRi12 ; CHECK-NEXT: t2STRi12 - tBX_RET 14, _ + tBX_RET 14, %noreg ... diff --git a/test/CodeGen/ARM/prera-ldst-insertpt.mir b/test/CodeGen/ARM/prera-ldst-insertpt.mir index eafcc7c36d334..c0202eb84faf1 100644 --- a/test/CodeGen/ARM/prera-ldst-insertpt.mir +++ b/test/CodeGen/ARM/prera-ldst-insertpt.mir @@ -28,14 +28,14 @@ body: | %2 : rgpr = COPY %r2 %1 : rgpr = COPY %r1 %0 : gpr = COPY %r0 - %3 : rgpr = t2MUL %2, %2, 14, _ - %4 : rgpr = t2MUL %1, %1, 14, _ + %3 : rgpr = t2MUL %2, %2, 14, %noreg + %4 : rgpr = t2MUL %1, %1, 14, %noreg %5 : rgpr = t2MOVi32imm -858993459 - %6 : rgpr, %7 : rgpr = t2UMULL killed %3, %5, 14, _ - %8 : rgpr, %9 : rgpr = t2UMULL killed %4, %5, 14, _ - t2STRi12 %1, %0, 0, 14, _ :: (store 4) - %10 : rgpr = t2LSLri %2, 1, 14, _, _ - t2STRi12 killed %10, %0, 4, 14, _ :: (store 4) + %6 : rgpr, %7 : rgpr = t2UMULL killed %3, %5, 14, %noreg + %8 : rgpr, %9 : rgpr = t2UMULL killed %4, %5, 14, %noreg + t2STRi12 %1, %0, 0, 14, %noreg :: (store 4) + %10 : rgpr = t2LSLri %2, 1, 14, %noreg, %noreg + t2STRi12 killed %10, %0, 4, 14, %noreg :: (store 4) ; Make sure we move the paired stores next to each other, and ; insert them in an appropriate location. @@ -44,17 +44,17 @@ body: | ; CHECK-NEXT: t2MOVi ; CHECK-NEXT: t2ADDrs - %11 : rgpr = t2MOVi 55, 14, _, _ - %12 : gprnopc = t2ADDrs %11, killed %7, 19, 14, _, _ - t2STRi12 killed %12, %0, 16, 14, _ :: (store 4) - %13 : gprnopc = t2ADDrs %11, killed %9, 19, 14, _, _ - t2STRi12 killed %13, %0, 20, 14, _ :: (store 4) + %11 : rgpr = t2MOVi 55, 14, %noreg, %noreg + %12 : gprnopc = t2ADDrs %11, killed %7, 19, 14, %noreg, %noreg + t2STRi12 killed %12, %0, 16, 14, %noreg :: (store 4) + %13 : gprnopc = t2ADDrs %11, killed %9, 19, 14, %noreg, %noreg + t2STRi12 killed %13, %0, 20, 14, %noreg :: (store 4) ; Make sure we move the paired stores next to each other. ; CHECK: t2STRi12 killed %12, ; CHECK-NEXT: t2STRi12 killed %13, - tBX_RET 14, _ + tBX_RET 14, %noreg --- # CHECK-LABEL: name: b name: b @@ -71,11 +71,11 @@ body: | %2 : rgpr = COPY %r2 %1 : rgpr = COPY %r1 %0 : gpr = COPY %r0 - t2STRi12 %1, %0, 0, 14, _ :: (store 4) - %10 : rgpr = t2LSLri %2, 1, 14, _, _ - t2STRi12 killed %10, %0, 4, 14, _ :: (store 4) - %3 : rgpr = t2MUL %2, %2, 14, _ - t2STRi12 %3, %0, 8, 14, _ :: (store 4) + t2STRi12 %1, %0, 0, 14, %noreg :: (store 4) + %10 : rgpr = t2LSLri %2, 1, 14, %noreg, %noreg + t2STRi12 killed %10, %0, 4, 14, %noreg :: (store 4) + %3 : rgpr = t2MUL %2, %2, 14, %noreg + t2STRi12 %3, %0, 8, 14, %noreg :: (store 4) ; Make sure we move the paired stores next to each other, and ; insert them in an appropriate location. @@ -85,21 +85,21 @@ body: | ; CHECK-NEXT: t2MUL ; CHECK-NEXT: t2MOVi32imm - %4 : rgpr = t2MUL %1, %1, 14, _ + %4 : rgpr = t2MUL %1, %1, 14, %noreg %5 : rgpr = t2MOVi32imm -858993459 - %6 : rgpr, %7 : rgpr = t2UMULL killed %3, %5, 14, _ - %8 : rgpr, %9 : rgpr = t2UMULL killed %4, %5, 14, _ - %10 : rgpr = t2LSLri %2, 1, 14, _, _ - %11 : rgpr = t2MOVi 55, 14, _, _ - %12 : gprnopc = t2ADDrs %11, killed %7, 19, 14, _, _ - t2STRi12 killed %12, %0, 16, 14, _ :: (store 4) - %13 : gprnopc = t2ADDrs %11, killed %9, 19, 14, _, _ - t2STRi12 killed %13, %0, 20, 14, _ :: (store 4) + %6 : rgpr, %7 : rgpr = t2UMULL killed %3, %5, 14, %noreg + %8 : rgpr, %9 : rgpr = t2UMULL killed %4, %5, 14, %noreg + %10 : rgpr = t2LSLri %2, 1, 14, %noreg, %noreg + %11 : rgpr = t2MOVi 55, 14, %noreg, %noreg + %12 : gprnopc = t2ADDrs %11, killed %7, 19, 14, %noreg, %noreg + t2STRi12 killed %12, %0, 16, 14, %noreg :: (store 4) + %13 : gprnopc = t2ADDrs %11, killed %9, 19, 14, %noreg, %noreg + t2STRi12 killed %13, %0, 20, 14, %noreg :: (store 4) ; Make sure we move the paired stores next to each other. ; CHECK: t2STRi12 {{.*}}, 16 ; CHECK-NEXT: t2STRi12 {{.*}}, 20 - tBX_RET 14, _ + tBX_RET 14, %noreg ... diff --git a/test/CodeGen/ARM/scavenging.mir b/test/CodeGen/ARM/scavenging.mir index dfd02fbee75c0..c7fb7b3e86c7a 100644 --- a/test/CodeGen/ARM/scavenging.mir +++ b/test/CodeGen/ARM/scavenging.mir @@ -25,36 +25,36 @@ body: | %r7 = IMPLICIT_DEF %0 : tgpr = IMPLICIT_DEF - %0 = tADDhirr %0, %sp, 14, _ - tSTRi %r0, %0, 0, 14, _ + %0 = tADDhirr %0, %sp, 14, %noreg + tSTRi %r0, %0, 0, 14, %noreg %1 : tgpr = IMPLICIT_DEF - %1 = tADDhirr %1, %sp, 14, _ - tSTRi %r1, %1, 0, 14, _ + %1 = tADDhirr %1, %sp, 14, %noreg + tSTRi %r1, %1, 0, 14, %noreg %2 : tgpr = IMPLICIT_DEF - %2 = tADDhirr %2, %sp, 14, _ - tSTRi %r2, %2, 0, 14, _ + %2 = tADDhirr %2, %sp, 14, %noreg + tSTRi %r2, %2, 0, 14, %noreg %3 : tgpr = IMPLICIT_DEF - %3 = tADDhirr %3, %sp, 14, _ - tSTRi %r3, %3, 0, 14, _ + %3 = tADDhirr %3, %sp, 14, %noreg + tSTRi %r3, %3, 0, 14, %noreg %4 : tgpr = IMPLICIT_DEF - %4 = tADDhirr %4, %sp, 14, _ - tSTRi %r4, %4, 0, 14, _ + %4 = tADDhirr %4, %sp, 14, %noreg + tSTRi %r4, %4, 0, 14, %noreg %5 : tgpr = IMPLICIT_DEF - %5 = tADDhirr %5, %sp, 14, _ - tSTRi %r5, %5, 0, 14, _ + %5 = tADDhirr %5, %sp, 14, %noreg + tSTRi %r5, %5, 0, 14, %noreg %6 : tgpr = IMPLICIT_DEF - %6 = tADDhirr %6, %sp, 14, _ - tSTRi %r6, %6, 0, 14, _ + %6 = tADDhirr %6, %sp, 14, %noreg + tSTRi %r6, %6, 0, 14, %noreg %7 : tgpr = IMPLICIT_DEF - %7 = tADDhirr %7, %sp, 14, _ - tSTRi %r7, %7, 0, 14, _ + %7 = tADDhirr %7, %sp, 14, %noreg + tSTRi %r7, %7, 0, 14, %noreg KILL %r0 KILL %r1 diff --git a/test/CodeGen/ARM/sched-it-debug-nodes.mir b/test/CodeGen/ARM/sched-it-debug-nodes.mir index 2d4fff160673c..d88a57dccca05 100644 --- a/test/CodeGen/ARM/sched-it-debug-nodes.mir +++ b/test/CodeGen/ARM/sched-it-debug-nodes.mir @@ -131,27 +131,27 @@ body: | bb.0.entry: liveins: %r0, %r1, %r2, %r3, %lr, %r7 - DBG_VALUE debug-use %r0, debug-use _, !18, !27, debug-location !28 - DBG_VALUE debug-use %r1, debug-use _, !19, !27, debug-location !28 - DBG_VALUE debug-use %r2, debug-use _, !20, !27, debug-location !28 - DBG_VALUE debug-use %r3, debug-use _, !21, !27, debug-location !28 - t2CMPri %r3, 4, 14, _, implicit-def %cpsr, debug-location !31 - DBG_VALUE debug-use %r1, debug-use _, !19, !27, debug-location !28 - %r0 = t2MOVi -1, 3, %cpsr, _, implicit undef %r0 - DBG_VALUE debug-use %r1, debug-use _, !19, !27, debug-location !28 + DBG_VALUE debug-use %r0, debug-use %noreg, !18, !27, debug-location !28 + DBG_VALUE debug-use %r1, debug-use %noreg, !19, !27, debug-location !28 + DBG_VALUE debug-use %r2, debug-use %noreg, !20, !27, debug-location !28 + DBG_VALUE debug-use %r3, debug-use %noreg, !21, !27, debug-location !28 + t2CMPri %r3, 4, 14, %noreg, implicit-def %cpsr, debug-location !31 + DBG_VALUE debug-use %r1, debug-use %noreg, !19, !27, debug-location !28 + %r0 = t2MOVi -1, 3, %cpsr, %noreg, implicit undef %r0 + DBG_VALUE debug-use %r1, debug-use %noreg, !19, !27, debug-location !28 tBX_RET 3, %cpsr, implicit %r0, debug-location !34 - %sp = frame-setup t2STMDB_UPD %sp, 14, _, killed %r7, killed %lr + %sp = frame-setup t2STMDB_UPD %sp, 14, %noreg, killed %r7, killed %lr frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION offset %lr, -4 frame-setup CFI_INSTRUCTION offset %r7, -8 - DBG_VALUE debug-use %r0, debug-use _, !18, !27, debug-location !28 - DBG_VALUE debug-use %r1, debug-use _, !19, !27, debug-location !28 - DBG_VALUE debug-use %r2, debug-use _, !20, !27, debug-location !28 - DBG_VALUE debug-use %r3, debug-use _, !21, !27, debug-location !28 - %r1 = tMOVr killed %r2, 14, _, debug-location !32 - %r2 = tMOVr killed %r3, 14, _, debug-location !32 - tBL 14, _, @g, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit-def %sp, debug-location !32 - %r0 = t2MOVi 0, 14, _, _ - %sp = t2LDMIA_RET %sp, 14, _, def %r7, def %pc, implicit %r0 + DBG_VALUE debug-use %r0, debug-use %noreg, !18, !27, debug-location !28 + DBG_VALUE debug-use %r1, debug-use %noreg, !19, !27, debug-location !28 + DBG_VALUE debug-use %r2, debug-use %noreg, !20, !27, debug-location !28 + DBG_VALUE debug-use %r3, debug-use %noreg, !21, !27, debug-location !28 + %r1 = tMOVr killed %r2, 14, %noreg, debug-location !32 + %r2 = tMOVr killed %r3, 14, %noreg, debug-location !32 + tBL 14, %noreg, @g, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit-def %sp, debug-location !32 + %r0 = t2MOVi 0, 14, %noreg, %noreg + %sp = t2LDMIA_RET %sp, 14, %noreg, def %r7, def %pc, implicit %r0 ... diff --git a/test/CodeGen/ARM/select_const.ll b/test/CodeGen/ARM/select_const.ll index 23de9c35a5b81..7cce0b0820375 100644 --- a/test/CodeGen/ARM/select_const.ll +++ b/test/CodeGen/ARM/select_const.ll @@ -8,7 +8,7 @@ define i32 @select_0_or_1(i1 %cond) { ; CHECK-LABEL: select_0_or_1: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: mov r1, #1 ; CHECK-NEXT: bic r0, r1, r0 ; CHECK-NEXT: mov pc, lr @@ -18,7 +18,7 @@ define i32 @select_0_or_1(i1 %cond) { define i32 @select_0_or_1_zeroext(i1 zeroext %cond) { ; CHECK-LABEL: select_0_or_1_zeroext: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: eor r0, r0, #1 ; CHECK-NEXT: mov pc, lr %sel = select i1 %cond, i32 0, i32 1 @@ -27,7 +27,7 @@ define i32 @select_0_or_1_zeroext(i1 zeroext %cond) { define i32 @select_0_or_1_signext(i1 signext %cond) { ; CHECK-LABEL: select_0_or_1_signext: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: mov r1, #1 ; CHECK-NEXT: bic r0, r1, r0 ; CHECK-NEXT: mov pc, lr @@ -39,7 +39,7 @@ define i32 @select_0_or_1_signext(i1 signext %cond) { define i32 @select_1_or_0(i1 %cond) { ; CHECK-LABEL: select_1_or_0: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: and r0, r0, #1 ; CHECK-NEXT: mov pc, lr %sel = select i1 %cond, i32 1, i32 0 @@ -48,7 +48,7 @@ define i32 @select_1_or_0(i1 %cond) { define i32 @select_1_or_0_zeroext(i1 zeroext %cond) { ; CHECK-LABEL: select_1_or_0_zeroext: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: mov pc, lr %sel = select i1 %cond, i32 1, i32 0 ret i32 %sel @@ -56,7 +56,7 @@ define i32 @select_1_or_0_zeroext(i1 zeroext %cond) { define i32 @select_1_or_0_signext(i1 signext %cond) { ; CHECK-LABEL: select_1_or_0_signext: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: and r0, r0, #1 ; CHECK-NEXT: mov pc, lr %sel = select i1 %cond, i32 1, i32 0 @@ -67,7 +67,7 @@ define i32 @select_1_or_0_signext(i1 signext %cond) { define i32 @select_0_or_neg1(i1 %cond) { ; CHECK-LABEL: select_0_or_neg1: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: mov r1, #1 ; CHECK-NEXT: bic r0, r1, r0 ; CHECK-NEXT: rsb r0, r0, #0 @@ -78,7 +78,7 @@ define i32 @select_0_or_neg1(i1 %cond) { define i32 @select_0_or_neg1_zeroext(i1 zeroext %cond) { ; CHECK-LABEL: select_0_or_neg1_zeroext: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: eor r0, r0, #1 ; CHECK-NEXT: rsb r0, r0, #0 ; CHECK-NEXT: mov pc, lr @@ -88,7 +88,7 @@ define i32 @select_0_or_neg1_zeroext(i1 zeroext %cond) { define i32 @select_0_or_neg1_signext(i1 signext %cond) { ; CHECK-LABEL: select_0_or_neg1_signext: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: mvn r0, r0 ; CHECK-NEXT: mov pc, lr %sel = select i1 %cond, i32 0, i32 -1 @@ -97,7 +97,7 @@ define i32 @select_0_or_neg1_signext(i1 signext %cond) { define i32 @select_0_or_neg1_alt(i1 %cond) { ; CHECK-LABEL: select_0_or_neg1_alt: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: and r0, r0, #1 ; CHECK-NEXT: sub r0, r0, #1 ; CHECK-NEXT: mov pc, lr @@ -108,7 +108,7 @@ define i32 @select_0_or_neg1_alt(i1 %cond) { define i32 @select_0_or_neg1_alt_zeroext(i1 zeroext %cond) { ; CHECK-LABEL: select_0_or_neg1_alt_zeroext: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: sub r0, r0, #1 ; CHECK-NEXT: mov pc, lr %z = zext i1 %cond to i32 @@ -118,7 +118,7 @@ define i32 @select_0_or_neg1_alt_zeroext(i1 zeroext %cond) { define i32 @select_0_or_neg1_alt_signext(i1 signext %cond) { ; CHECK-LABEL: select_0_or_neg1_alt_signext: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: mvn r0, r0 ; CHECK-NEXT: mov pc, lr %z = zext i1 %cond to i32 @@ -130,7 +130,7 @@ define i32 @select_0_or_neg1_alt_signext(i1 signext %cond) { define i32 @select_neg1_or_0(i1 %cond) { ; CHECK-LABEL: select_neg1_or_0: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: and r0, r0, #1 ; CHECK-NEXT: rsb r0, r0, #0 ; CHECK-NEXT: mov pc, lr @@ -140,7 +140,7 @@ define i32 @select_neg1_or_0(i1 %cond) { define i32 @select_neg1_or_0_zeroext(i1 zeroext %cond) { ; CHECK-LABEL: select_neg1_or_0_zeroext: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: rsb r0, r0, #0 ; CHECK-NEXT: mov pc, lr %sel = select i1 %cond, i32 -1, i32 0 @@ -149,7 +149,7 @@ define i32 @select_neg1_or_0_zeroext(i1 zeroext %cond) { define i32 @select_neg1_or_0_signext(i1 signext %cond) { ; CHECK-LABEL: select_neg1_or_0_signext: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: mov pc, lr %sel = select i1 %cond, i32 -1, i32 0 ret i32 %sel @@ -159,7 +159,7 @@ define i32 @select_neg1_or_0_signext(i1 signext %cond) { define i32 @select_Cplus1_C(i1 %cond) { ; CHECK-LABEL: select_Cplus1_C: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: mov r1, #41 ; CHECK-NEXT: tst r0, #1 ; CHECK-NEXT: movne r1, #42 @@ -171,7 +171,7 @@ define i32 @select_Cplus1_C(i1 %cond) { define i32 @select_Cplus1_C_zeroext(i1 zeroext %cond) { ; CHECK-LABEL: select_Cplus1_C_zeroext: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: mov r1, #41 ; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: movne r1, #42 @@ -183,7 +183,7 @@ define i32 @select_Cplus1_C_zeroext(i1 zeroext %cond) { define i32 @select_Cplus1_C_signext(i1 signext %cond) { ; CHECK-LABEL: select_Cplus1_C_signext: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: mov r1, #41 ; CHECK-NEXT: tst r0, #1 ; CHECK-NEXT: movne r1, #42 @@ -197,7 +197,7 @@ define i32 @select_Cplus1_C_signext(i1 signext %cond) { define i32 @select_C_Cplus1(i1 %cond) { ; CHECK-LABEL: select_C_Cplus1: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: mov r1, #42 ; CHECK-NEXT: tst r0, #1 ; CHECK-NEXT: movne r1, #41 @@ -209,7 +209,7 @@ define i32 @select_C_Cplus1(i1 %cond) { define i32 @select_C_Cplus1_zeroext(i1 zeroext %cond) { ; CHECK-LABEL: select_C_Cplus1_zeroext: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: mov r1, #42 ; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: movne r1, #41 @@ -221,7 +221,7 @@ define i32 @select_C_Cplus1_zeroext(i1 zeroext %cond) { define i32 @select_C_Cplus1_signext(i1 signext %cond) { ; CHECK-LABEL: select_C_Cplus1_signext: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: mov r1, #42 ; CHECK-NEXT: tst r0, #1 ; CHECK-NEXT: movne r1, #41 @@ -236,7 +236,7 @@ define i32 @select_C_Cplus1_signext(i1 signext %cond) { define i32 @select_C1_C2(i1 %cond) { ; CHECK-LABEL: select_C1_C2: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: mov r1, #165 ; CHECK-NEXT: tst r0, #1 ; CHECK-NEXT: orr r1, r1, #256 @@ -249,7 +249,7 @@ define i32 @select_C1_C2(i1 %cond) { define i32 @select_C1_C2_zeroext(i1 zeroext %cond) { ; CHECK-LABEL: select_C1_C2_zeroext: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: mov r1, #165 ; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: orr r1, r1, #256 @@ -262,7 +262,7 @@ define i32 @select_C1_C2_zeroext(i1 zeroext %cond) { define i32 @select_C1_C2_signext(i1 signext %cond) { ; CHECK-LABEL: select_C1_C2_signext: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: mov r1, #165 ; CHECK-NEXT: tst r0, #1 ; CHECK-NEXT: orr r1, r1, #256 @@ -278,7 +278,7 @@ define i32 @select_C1_C2_signext(i1 signext %cond) { define i64 @opaque_constant1(i1 %cond, i64 %x) { ; CHECK-LABEL: opaque_constant1: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: .save {r4, lr} ; CHECK-NEXT: push {r4, lr} ; CHECK-NEXT: mov lr, #1 @@ -310,7 +310,7 @@ define i64 @opaque_constant1(i1 %cond, i64 %x) { define i64 @opaque_constant2(i1 %cond, i64 %x) { ; CHECK-LABEL: opaque_constant2: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: mov r1, #1 ; CHECK-NEXT: tst r0, #1 ; CHECK-NEXT: orr r1, r1, #65536 diff --git a/test/CodeGen/ARM/setcc-logic.ll b/test/CodeGen/ARM/setcc-logic.ll index 79bae1facb3e5..c48636dffa7f3 100644 --- a/test/CodeGen/ARM/setcc-logic.ll +++ b/test/CodeGen/ARM/setcc-logic.ll @@ -3,7 +3,7 @@ define zeroext i1 @ne_neg1_and_ne_zero(i32 %x) nounwind { ; CHECK-LABEL: ne_neg1_and_ne_zero: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: add r1, r0, #1 ; CHECK-NEXT: mov r0, #0 ; CHECK-NEXT: cmp r1, #1 @@ -19,7 +19,7 @@ define zeroext i1 @ne_neg1_and_ne_zero(i32 %x) nounwind { define zeroext i1 @and_eq(i32 %a, i32 %b, i32 %c, i32 %d) nounwind { ; CHECK-LABEL: and_eq: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: eor r2, r2, r3 ; CHECK-NEXT: eor r0, r0, r1 ; CHECK-NEXT: orrs r0, r0, r2 @@ -34,7 +34,7 @@ define zeroext i1 @and_eq(i32 %a, i32 %b, i32 %c, i32 %d) nounwind { define zeroext i1 @or_ne(i32 %a, i32 %b, i32 %c, i32 %d) nounwind { ; CHECK-LABEL: or_ne: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: eor r2, r2, r3 ; CHECK-NEXT: eor r0, r0, r1 ; CHECK-NEXT: orrs r0, r0, r2 @@ -48,7 +48,7 @@ define zeroext i1 @or_ne(i32 %a, i32 %b, i32 %c, i32 %d) nounwind { define <4 x i1> @and_eq_vec(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d) nounwind { ; CHECK-LABEL: and_eq_vec: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: .save {r11, lr} ; CHECK-NEXT: push {r11, lr} ; CHECK-NEXT: vmov d19, r2, r3 diff --git a/test/CodeGen/ARM/single-issue-r52.mir b/test/CodeGen/ARM/single-issue-r52.mir index 1eba074dafb3c..b9857a18299a1 100644 --- a/test/CodeGen/ARM/single-issue-r52.mir +++ b/test/CodeGen/ARM/single-issue-r52.mir @@ -20,22 +20,22 @@ # CHECK: ********** MI Scheduling ********** # CHECK: ScheduleDAGMILive::schedule starting -# CHECK: SU(1): %vreg1 = VLD4d8Pseudo %vreg0, 8, pred:14, pred:%noreg; mem:LD32[%A](align=8) QQPR:%vreg1 GPR:%vreg0 +# CHECK: SU(1): %1 = VLD4d8Pseudo %0, 8, pred:14, pred:%noreg; mem:LD32[%A](align=8) QQPR:%1 GPR:%0 # CHECK: Latency : 8 # CHECK: Single Issue : true; -# CHECK: SU(2): %vreg4 = VADDv8i8 %vreg1:dsub_0, %vreg1:dsub_1, pred:14, pred:%noreg; DPR:%vreg4 QQPR:%vreg1 +# CHECK: SU(2): %4 = VADDv8i8 %1:dsub_0, %1:dsub_1, pred:14, pred:%noreg; DPR:%4 QQPR:%1 # CHECK: Latency : 5 # CHECK: Single Issue : false; -# CHECK: SU(3): %vreg5, %vreg6 = VMOVRRD %vreg4, pred:14, pred:%noreg; GPR:%vreg5,%vreg6 DPR:%vreg4 +# CHECK: SU(3): %5, %6 = VMOVRRD %4, pred:14, pred:%noreg; GPR:%5,%6 DPR:%4 # CHECK: Latency : 4 # CHECK: Single Issue : false; -# TOPDOWN: Scheduling SU(1) %vreg1 = VLD4d8Pseudo +# TOPDOWN: Scheduling SU(1) %1 = VLD4d8Pseudo # TOPDOWN: Bump cycle to end group -# TOPDOWN: Scheduling SU(2) %vreg4 = VADDv8i8 +# TOPDOWN: Scheduling SU(2) %4 = VADDv8i8 -# BOTTOMUP: Scheduling SU(2) %vreg4 = VADDv8i8 -# BOTTOMUP: Scheduling SU(1) %vreg1 = VLD4d8Pseudo +# BOTTOMUP: Scheduling SU(2) %4 = VADDv8i8 +# BOTTOMUP: Scheduling SU(1) %1 = VLD4d8Pseudo # BOTTOMUP: Bump cycle to begin group ... @@ -76,11 +76,11 @@ body: | liveins: %r0 %0 = COPY %r0 - %1 = VLD4d8Pseudo %0, 8, 14, _ :: (load 32 from %ir.A, align 8) - %4 = VADDv8i8 %1.dsub_0, %1.dsub_1, 14, _ - %5, %6 = VMOVRRD %4, 14, _ + %1 = VLD4d8Pseudo %0, 8, 14, %noreg :: (load 32 from %ir.A, align 8) + %4 = VADDv8i8 %1.dsub_0, %1.dsub_1, 14, %noreg + %5, %6 = VMOVRRD %4, 14, %noreg %r0 = COPY %5 %r1 = COPY %6 - BX_RET 14, _, implicit %r0, implicit killed %r1 + BX_RET 14, %noreg, implicit %r0, implicit killed %r1 ... diff --git a/test/CodeGen/ARM/subreg-remat.ll b/test/CodeGen/ARM/subreg-remat.ll index d5abfc0af51b7..616ab1ef7cd18 100644 --- a/test/CodeGen/ARM/subreg-remat.ll +++ b/test/CodeGen/ARM/subreg-remat.ll @@ -4,10 +4,10 @@ target triple = "thumbv7-apple-ios" ; ; The vector %v2 is built like this: ; -; %vreg6:ssub_1 = ... -; %vreg6:ssub_0 = VLDRS , 0, pred:14, pred:%noreg; mem:LD4[ConstantPool] DPR_VFP2:%vreg6 +; %6:ssub_1 = ... +; %6:ssub_0 = VLDRS , 0, pred:14, pred:%noreg; mem:LD4[ConstantPool] DPR_VFP2:%6 ; -; When %vreg6 spills, the VLDRS constant pool load cannot be rematerialized +; When %6 spills, the VLDRS constant pool load cannot be rematerialized ; since it implicitly reads the ssub_1 sub-register. ; ; CHECK: f1 @@ -31,7 +31,7 @@ define void @f1(float %x, <2 x float>* %p) { ; because the bits are undef, we should rematerialize. The vector is now built ; like this: ; -; %vreg2:ssub_0 = VLDRS , 0, pred:14, pred:%noreg, %vreg2; mem:LD4[ConstantPool] +; %2:ssub_0 = VLDRS , 0, pred:14, pred:%noreg, %2; mem:LD4[ConstantPool] ; ; The extra operand indicates that the instruction fully defines the ; virtual register. It doesn't read the old value. diff --git a/test/CodeGen/ARM/tail-dup-bundle.mir b/test/CodeGen/ARM/tail-dup-bundle.mir index 67c1cb5a6b94a..719d616f26bc8 100644 --- a/test/CodeGen/ARM/tail-dup-bundle.mir +++ b/test/CodeGen/ARM/tail-dup-bundle.mir @@ -19,7 +19,7 @@ body: | bb.1: liveins: %r0 - t2CMPri %r0, 32, 14, _, implicit-def %cpsr + t2CMPri %r0, 32, 14, %noreg, implicit-def %cpsr BUNDLE implicit-def dead %itstate, implicit-def %cpsr, implicit killed %r0, implicit killed %cpsr { t2IT 1, 24, implicit-def %itstate t2CMPri killed %r0, 9, 1, killed %cpsr, implicit-def %cpsr, implicit internal killed %itstate @@ -28,9 +28,9 @@ body: | bb.2: %r0 = IMPLICIT_DEF - t2B %bb.1, 14, _ + t2B %bb.1, 14, %noreg bb.3: %r0 = IMPLICIT_DEF - t2B %bb.1, 14, _ + t2B %bb.1, 14, %noreg ... diff --git a/test/CodeGen/ARM/tail-merge-branch-weight.ll b/test/CodeGen/ARM/tail-merge-branch-weight.ll index f83f288157935..f03906b6bf513 100644 --- a/test/CodeGen/ARM/tail-merge-branch-weight.ll +++ b/test/CodeGen/ARM/tail-merge-branch-weight.ll @@ -9,9 +9,9 @@ ; = 0.2 * 0.4 + 0.8 * 0.7 = 0.64 ; CHECK: # Machine code for function test0: -; CHECK: Successors according to CFG: BB#{{[0-9]+}}({{[0-9a-fx/= ]+}}20.00%) BB#{{[0-9]+}}({{[0-9a-fx/= ]+}}80.00%) -; CHECK: BB#{{[0-9]+}}: -; CHECK: BB#{{[0-9]+}}: +; CHECK: Successors according to CFG: %bb.{{[0-9]+}}({{[0-9a-fx/= ]+}}20.00%) %bb.{{[0-9]+}}({{[0-9a-fx/= ]+}}80.00%) +; CHECK: %bb.{{[0-9]+}}: +; CHECK: %bb.{{[0-9]+}}: ; CHECK: # End machine code for function test0. define i32 @test0(i32 %n, i32 %m, i32* nocapture %a, i32* nocapture %b) { diff --git a/test/CodeGen/ARM/taildup-branch-weight.ll b/test/CodeGen/ARM/taildup-branch-weight.ll index 6f8d245e74a02..5b7ba0ae51b02 100644 --- a/test/CodeGen/ARM/taildup-branch-weight.ll +++ b/test/CodeGen/ARM/taildup-branch-weight.ll @@ -3,7 +3,7 @@ ; RUN: | FileCheck %s ; CHECK: Machine code for function test0: -; CHECK: Successors according to CFG: BB#1({{[0-9a-fx/= ]+}}3.12%) BB#2({{[0-9a-fx/= ]+}}96.88%) +; CHECK: Successors according to CFG: %bb.1({{[0-9a-fx/= ]+}}3.12%) %bb.2({{[0-9a-fx/= ]+}}96.88%) define void @test0(i32 %a, i32 %b, i32* %c, i32* %d) { entry: @@ -30,7 +30,7 @@ B4: !0 = !{!"branch_weights", i32 4, i32 124} ; CHECK: Machine code for function test1: -; CHECK: Successors according to CFG: BB#2(0x7c000000 / 0x80000000 = 96.88%) BB#1(0x04000000 / 0x80000000 = 3.12%) +; CHECK: Successors according to CFG: %bb.2(0x7c000000 / 0x80000000 = 96.88%) %bb.1(0x04000000 / 0x80000000 = 3.12%) @g0 = common global i32 0, align 4 diff --git a/test/CodeGen/ARM/thumb-litpool.ll b/test/CodeGen/ARM/thumb-litpool.ll index f68fdb6fdc0f3..bd8829c22bceb 100644 --- a/test/CodeGen/ARM/thumb-litpool.ll +++ b/test/CodeGen/ARM/thumb-litpool.ll @@ -12,4 +12,4 @@ define void @foo() minsize { call void asm sideeffect "", "~{r0},~{r1},~{r2},~{r3},~{r4},~{r5},~{r6},~{r7}"() call void @callee(i8* @var) ret void -} \ No newline at end of file +} diff --git a/test/CodeGen/ARM/v6-jumptable-clobber.mir b/test/CodeGen/ARM/v6-jumptable-clobber.mir index ba25ac2cfe46b..52a39ffc5e1dd 100644 --- a/test/CodeGen/ARM/v6-jumptable-clobber.mir +++ b/test/CodeGen/ARM/v6-jumptable-clobber.mir @@ -231,21 +231,21 @@ body: | successors: %bb.2.d1(0x03c3c3c4), %bb.1(0x7c3c3c3c) liveins: %r0, %r1 - %r2 = tLDRpci %const.0, 14, _ - tSTRi killed %r2, killed %r1, 0, 14, _ :: (store 4 into %ir.addr) + %r2 = tLDRpci %const.0, 14, %noreg + tSTRi killed %r2, killed %r1, 0, 14, %noreg :: (store 4 into %ir.addr) dead %r1 = SPACE 980, undef %r0 - %r0 = tUXTB killed %r0, 14, _ - %r1, dead %cpsr = tSUBi3 killed %r0, 1, 14, _ - tCMPi8 %r1, 25, 14, _, implicit-def %cpsr + %r0 = tUXTB killed %r0, 14, %noreg + %r1, dead %cpsr = tSUBi3 killed %r0, 1, 14, %noreg + tCMPi8 %r1, 25, 14, %noreg, implicit-def %cpsr tBcc %bb.2.d1, 8, killed %cpsr bb.1 (%ir-block.0): successors: %bb.3.d2(0x07c549d2), %bb.9.d8(0x07c549d2), %bb.4.d3(0x07c549d2), %bb.5.d4(0x07c549d2), %bb.6.d5(0x07c549d2), %bb.7.d6(0x07c549d2), %bb.8.d7(0x07c549d2), %bb.10.d9(0x07c549d2), %bb.11.d10(0x07c549d2), %bb.2.d1(0x03ab62db), %bb.12.d11(0x07c549d2), %bb.13.d12(0x07c549d2), %bb.14.d13(0x07c549d2), %bb.15.d14(0x07c549d2), %bb.16.d15(0x07c549d2), %bb.17.d16(0x07c549d2), %bb.18.d17(0x07c549d2) liveins: %r1 - %r0, dead %cpsr = tLSLri killed %r1, 2, 14, _ - %r1 = tLEApcrelJT %jump-table.0, 14, _ - %r0 = tLDRr killed %r1, killed %r0, 14, _ :: (load 4 from jump-table) + %r0, dead %cpsr = tLSLri killed %r1, 2, 14, %noreg + %r1 = tLEApcrelJT %jump-table.0, 14, %noreg + %r0 = tLDRr killed %r1, killed %r0, 14, %noreg :: (load 4 from jump-table) tBR_JTr killed %r0, %jump-table.0 bb.3.d2: @@ -329,20 +329,20 @@ body: | successors: %bb.2.d1(0x03c3c3c4), %bb.1(0x7c3c3c3c) liveins: %r0, %r1 - %r2 = tLDRpci %const.0, 14, _ - tSTRi killed %r2, killed %r1, 0, 14, _ :: (store 4 into %ir.addr) - %r0 = tUXTB killed %r0, 14, _ - %r1, dead %cpsr = tSUBi3 killed %r0, 1, 14, _ - tCMPi8 %r1, 25, 14, _, implicit-def %cpsr + %r2 = tLDRpci %const.0, 14, %noreg + tSTRi killed %r2, killed %r1, 0, 14, %noreg :: (store 4 into %ir.addr) + %r0 = tUXTB killed %r0, 14, %noreg + %r1, dead %cpsr = tSUBi3 killed %r0, 1, 14, %noreg + tCMPi8 %r1, 25, 14, %noreg, implicit-def %cpsr tBcc %bb.2.d1, 8, killed %cpsr bb.1 (%ir-block.0): successors: %bb.3.d2(0x07c549d2), %bb.9.d8(0x07c549d2), %bb.4.d3(0x07c549d2), %bb.5.d4(0x07c549d2), %bb.6.d5(0x07c549d2), %bb.7.d6(0x07c549d2), %bb.8.d7(0x07c549d2), %bb.10.d9(0x07c549d2), %bb.11.d10(0x07c549d2), %bb.2.d1(0x03ab62db), %bb.12.d11(0x07c549d2), %bb.13.d12(0x07c549d2), %bb.14.d13(0x07c549d2), %bb.15.d14(0x07c549d2), %bb.16.d15(0x07c549d2), %bb.17.d16(0x07c549d2), %bb.18.d17(0x07c549d2) liveins: %r1 - %r0, dead %cpsr = tLSLri killed %r1, 2, 14, _ - %r1 = tLEApcrelJT %jump-table.0, 14, _ - %r0 = tLDRr killed %r1, killed %r0, 14, _ :: (load 4 from jump-table) + %r0, dead %cpsr = tLSLri killed %r1, 2, 14, %noreg + %r1 = tLEApcrelJT %jump-table.0, 14, %noreg + %r0 = tLDRr killed %r1, killed %r0, 14, %noreg :: (load 4 from jump-table) tBR_JTr killed %r0, %jump-table.0 bb.3.d2: diff --git a/test/CodeGen/ARM/v8m-tail-call.ll b/test/CodeGen/ARM/v8m-tail-call.ll index c369df0c02220..96438dc5e6478 100644 --- a/test/CodeGen/ARM/v8m-tail-call.ll +++ b/test/CodeGen/ARM/v8m-tail-call.ll @@ -45,3 +45,61 @@ define hidden i32 @f2(i32, i32, i32, i32, i32) { ; CHECK-NEXT: add sp, #4 ; CHECK-NEXT: b h2 } + +; Make sure that tail calls to function pointers that require r0-r3 for argument +; passing do not break the compiler. +@fnptr = global i32 (i32, i32, i32, i32)* null +define i32 @test3() { +; CHECK-LABEL: test3: +; CHECK: blx {{r[0-9]+}} + %1 = load i32 (i32, i32, i32, i32)*, i32 (i32, i32, i32, i32)** @fnptr + %2 = tail call i32 %1(i32 1, i32 2, i32 3, i32 4) + ret i32 %2 +} + +@fnptr2 = global i32 (i32, i32, i64)* null +define i32 @test4() { +; CHECK-LABEL: test4: +; CHECK: blx {{r[0-9]+}} + %1 = load i32 (i32, i32, i64)*, i32 (i32, i32, i64)** @fnptr2 + %2 = tail call i32 %1(i32 1, i32 2, i64 3) + ret i32 %2 +} + +; Check that tail calls to function pointers where not all of r0-r3 are used for +; parameter passing are tail-call optimized. +; test5: params in r0, r1. r2 & r3 are free. +@fnptr3 = global i32 (i32, i32)* null +define i32 @test5() { +; CHECK-LABEL: test5: +; CHECK: ldr [[REG:r[0-9]+]] +; CHECK: bx [[REG]] +; CHECK-NOT: blx [[REG]] + %1 = load i32 (i32, i32)*, i32 (i32, i32)** @fnptr3 + %2 = tail call i32 %1(i32 1, i32 2) + ret i32 %2 +} + +; test6: params in r0 and r2-r3. r1 is free. +@fnptr4 = global i32 (i32, i64)* null +define i32 @test6() { +; CHECK-LABEL: test6: +; CHECK: ldr [[REG:r[0-9]+]] +; CHECK: bx [[REG]] +; CHECK-NOT: blx [[REG]] + %1 = load i32 (i32, i64)*, i32 (i32, i64)** @fnptr4 + %2 = tail call i32 %1(i32 1, i64 2) + ret i32 %2 +} + +; Check that tail calls to functions other than function pointers are +; tail-call optimized. +define i32 @test7() { +; CHECK-LABEL: test7: +; CHECK: b bar +; CHECK-NOT: bl bar + %tail = tail call i32 @bar(i32 1, i32 2, i32 3, i32 4) + ret i32 %tail +} + +declare i32 @bar(i32, i32, i32, i32) diff --git a/test/CodeGen/ARM/v8m.base-jumptable_alignment.ll b/test/CodeGen/ARM/v8m.base-jumptable_alignment.ll index 673e04687a10e..73189fe69dbef 100644 --- a/test/CodeGen/ARM/v8m.base-jumptable_alignment.ll +++ b/test/CodeGen/ARM/v8m.base-jumptable_alignment.ll @@ -30,7 +30,7 @@ for.cond7.preheader.i.us.i.i: ; preds = %for.cond7.preheader unreachable for.cond14.preheader.us.i.i.i: ; preds = %for.inc459.us.i.i.i, %for.cond7.preheader.i.i.preheader.i -; CHECK: @ BB#4 +; CHECK: @ %bb.4 ; CHECK-NEXT: .p2align 2 switch i4 undef, label %func_1.exit.loopexit [ i4 0, label %for.inc459.us.i.i.i diff --git a/test/CodeGen/ARM/vbits.ll b/test/CodeGen/ARM/vbits.ll index 0a7f7698fa88c..2997750ccb1a4 100644 --- a/test/CodeGen/ARM/vbits.ll +++ b/test/CodeGen/ARM/vbits.ll @@ -3,7 +3,7 @@ define <8 x i8> @v_andi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ; CHECK-LABEL: v_andi8: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vldr d16, [r1] ; CHECK-NEXT: vldr d17, [r0] ; CHECK-NEXT: vand d16, d17, d16 @@ -17,7 +17,7 @@ define <8 x i8> @v_andi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i16> @v_andi16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ; CHECK-LABEL: v_andi16: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vldr d16, [r1] ; CHECK-NEXT: vldr d17, [r0] ; CHECK-NEXT: vand d16, d17, d16 @@ -31,7 +31,7 @@ define <4 x i16> @v_andi16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i32> @v_andi32(<2 x i32>* %A, <2 x i32>* %B) nounwind { ; CHECK-LABEL: v_andi32: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vldr d16, [r1] ; CHECK-NEXT: vldr d17, [r0] ; CHECK-NEXT: vand d16, d17, d16 @@ -45,7 +45,7 @@ define <2 x i32> @v_andi32(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <1 x i64> @v_andi64(<1 x i64>* %A, <1 x i64>* %B) nounwind { ; CHECK-LABEL: v_andi64: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vldr d16, [r1] ; CHECK-NEXT: vldr d17, [r0] ; CHECK-NEXT: vand d16, d17, d16 @@ -59,7 +59,7 @@ define <1 x i64> @v_andi64(<1 x i64>* %A, <1 x i64>* %B) nounwind { define <16 x i8> @v_andQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { ; CHECK-LABEL: v_andQi8: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r1] ; CHECK-NEXT: vld1.64 {d18, d19}, [r0] ; CHECK-NEXT: vand q8, q9, q8 @@ -74,7 +74,7 @@ define <16 x i8> @v_andQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <8 x i16> @v_andQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { ; CHECK-LABEL: v_andQi16: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r1] ; CHECK-NEXT: vld1.64 {d18, d19}, [r0] ; CHECK-NEXT: vand q8, q9, q8 @@ -89,7 +89,7 @@ define <8 x i16> @v_andQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i32> @v_andQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { ; CHECK-LABEL: v_andQi32: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r1] ; CHECK-NEXT: vld1.64 {d18, d19}, [r0] ; CHECK-NEXT: vand q8, q9, q8 @@ -104,7 +104,7 @@ define <4 x i32> @v_andQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <2 x i64> @v_andQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind { ; CHECK-LABEL: v_andQi64: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r1] ; CHECK-NEXT: vld1.64 {d18, d19}, [r0] ; CHECK-NEXT: vand q8, q9, q8 @@ -119,7 +119,7 @@ define <2 x i64> @v_andQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind { define <8 x i8> @v_bici8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ; CHECK-LABEL: v_bici8: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vldr d16, [r1] ; CHECK-NEXT: vldr d17, [r0] ; CHECK-NEXT: vbic d16, d17, d16 @@ -134,7 +134,7 @@ define <8 x i8> @v_bici8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i16> @v_bici16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ; CHECK-LABEL: v_bici16: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vldr d16, [r1] ; CHECK-NEXT: vldr d17, [r0] ; CHECK-NEXT: vbic d16, d17, d16 @@ -149,7 +149,7 @@ define <4 x i16> @v_bici16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i32> @v_bici32(<2 x i32>* %A, <2 x i32>* %B) nounwind { ; CHECK-LABEL: v_bici32: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vldr d16, [r1] ; CHECK-NEXT: vldr d17, [r0] ; CHECK-NEXT: vbic d16, d17, d16 @@ -164,7 +164,7 @@ define <2 x i32> @v_bici32(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <1 x i64> @v_bici64(<1 x i64>* %A, <1 x i64>* %B) nounwind { ; CHECK-LABEL: v_bici64: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vldr d16, [r1] ; CHECK-NEXT: vldr d17, [r0] ; CHECK-NEXT: vbic d16, d17, d16 @@ -179,7 +179,7 @@ define <1 x i64> @v_bici64(<1 x i64>* %A, <1 x i64>* %B) nounwind { define <16 x i8> @v_bicQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { ; CHECK-LABEL: v_bicQi8: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r1] ; CHECK-NEXT: vld1.64 {d18, d19}, [r0] ; CHECK-NEXT: vbic q8, q9, q8 @@ -195,7 +195,7 @@ define <16 x i8> @v_bicQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <8 x i16> @v_bicQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { ; CHECK-LABEL: v_bicQi16: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r1] ; CHECK-NEXT: vld1.64 {d18, d19}, [r0] ; CHECK-NEXT: vbic q8, q9, q8 @@ -211,7 +211,7 @@ define <8 x i16> @v_bicQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i32> @v_bicQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { ; CHECK-LABEL: v_bicQi32: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r1] ; CHECK-NEXT: vld1.64 {d18, d19}, [r0] ; CHECK-NEXT: vbic q8, q9, q8 @@ -227,7 +227,7 @@ define <4 x i32> @v_bicQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <2 x i64> @v_bicQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind { ; CHECK-LABEL: v_bicQi64: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r1] ; CHECK-NEXT: vld1.64 {d18, d19}, [r0] ; CHECK-NEXT: vbic q8, q9, q8 @@ -243,7 +243,7 @@ define <2 x i64> @v_bicQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind { define <8 x i8> @v_eori8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ; CHECK-LABEL: v_eori8: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vldr d16, [r1] ; CHECK-NEXT: vldr d17, [r0] ; CHECK-NEXT: veor d16, d17, d16 @@ -257,7 +257,7 @@ define <8 x i8> @v_eori8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i16> @v_eori16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ; CHECK-LABEL: v_eori16: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vldr d16, [r1] ; CHECK-NEXT: vldr d17, [r0] ; CHECK-NEXT: veor d16, d17, d16 @@ -271,7 +271,7 @@ define <4 x i16> @v_eori16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i32> @v_eori32(<2 x i32>* %A, <2 x i32>* %B) nounwind { ; CHECK-LABEL: v_eori32: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vldr d16, [r1] ; CHECK-NEXT: vldr d17, [r0] ; CHECK-NEXT: veor d16, d17, d16 @@ -285,7 +285,7 @@ define <2 x i32> @v_eori32(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <1 x i64> @v_eori64(<1 x i64>* %A, <1 x i64>* %B) nounwind { ; CHECK-LABEL: v_eori64: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vldr d16, [r1] ; CHECK-NEXT: vldr d17, [r0] ; CHECK-NEXT: veor d16, d17, d16 @@ -299,7 +299,7 @@ define <1 x i64> @v_eori64(<1 x i64>* %A, <1 x i64>* %B) nounwind { define <16 x i8> @v_eorQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { ; CHECK-LABEL: v_eorQi8: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r1] ; CHECK-NEXT: vld1.64 {d18, d19}, [r0] ; CHECK-NEXT: veor q8, q9, q8 @@ -314,7 +314,7 @@ define <16 x i8> @v_eorQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <8 x i16> @v_eorQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { ; CHECK-LABEL: v_eorQi16: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r1] ; CHECK-NEXT: vld1.64 {d18, d19}, [r0] ; CHECK-NEXT: veor q8, q9, q8 @@ -329,7 +329,7 @@ define <8 x i16> @v_eorQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i32> @v_eorQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { ; CHECK-LABEL: v_eorQi32: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r1] ; CHECK-NEXT: vld1.64 {d18, d19}, [r0] ; CHECK-NEXT: veor q8, q9, q8 @@ -344,7 +344,7 @@ define <4 x i32> @v_eorQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <2 x i64> @v_eorQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind { ; CHECK-LABEL: v_eorQi64: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r1] ; CHECK-NEXT: vld1.64 {d18, d19}, [r0] ; CHECK-NEXT: veor q8, q9, q8 @@ -359,7 +359,7 @@ define <2 x i64> @v_eorQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind { define <8 x i8> @v_mvni8(<8 x i8>* %A) nounwind { ; CHECK-LABEL: v_mvni8: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vldr d16, [r0] ; CHECK-NEXT: vmvn d16, d16 ; CHECK-NEXT: vmov r0, r1, d16 @@ -371,7 +371,7 @@ define <8 x i8> @v_mvni8(<8 x i8>* %A) nounwind { define <4 x i16> @v_mvni16(<4 x i16>* %A) nounwind { ; CHECK-LABEL: v_mvni16: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vldr d16, [r0] ; CHECK-NEXT: vmvn d16, d16 ; CHECK-NEXT: vmov r0, r1, d16 @@ -383,7 +383,7 @@ define <4 x i16> @v_mvni16(<4 x i16>* %A) nounwind { define <2 x i32> @v_mvni32(<2 x i32>* %A) nounwind { ; CHECK-LABEL: v_mvni32: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vldr d16, [r0] ; CHECK-NEXT: vmvn d16, d16 ; CHECK-NEXT: vmov r0, r1, d16 @@ -395,7 +395,7 @@ define <2 x i32> @v_mvni32(<2 x i32>* %A) nounwind { define <1 x i64> @v_mvni64(<1 x i64>* %A) nounwind { ; CHECK-LABEL: v_mvni64: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vldr d16, [r0] ; CHECK-NEXT: vmvn d16, d16 ; CHECK-NEXT: vmov r0, r1, d16 @@ -407,7 +407,7 @@ define <1 x i64> @v_mvni64(<1 x i64>* %A) nounwind { define <16 x i8> @v_mvnQi8(<16 x i8>* %A) nounwind { ; CHECK-LABEL: v_mvnQi8: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r0] ; CHECK-NEXT: vmvn q8, q8 ; CHECK-NEXT: vmov r0, r1, d16 @@ -420,7 +420,7 @@ define <16 x i8> @v_mvnQi8(<16 x i8>* %A) nounwind { define <8 x i16> @v_mvnQi16(<8 x i16>* %A) nounwind { ; CHECK-LABEL: v_mvnQi16: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r0] ; CHECK-NEXT: vmvn q8, q8 ; CHECK-NEXT: vmov r0, r1, d16 @@ -433,7 +433,7 @@ define <8 x i16> @v_mvnQi16(<8 x i16>* %A) nounwind { define <4 x i32> @v_mvnQi32(<4 x i32>* %A) nounwind { ; CHECK-LABEL: v_mvnQi32: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r0] ; CHECK-NEXT: vmvn q8, q8 ; CHECK-NEXT: vmov r0, r1, d16 @@ -446,7 +446,7 @@ define <4 x i32> @v_mvnQi32(<4 x i32>* %A) nounwind { define <2 x i64> @v_mvnQi64(<2 x i64>* %A) nounwind { ; CHECK-LABEL: v_mvnQi64: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r0] ; CHECK-NEXT: vmvn q8, q8 ; CHECK-NEXT: vmov r0, r1, d16 @@ -459,7 +459,7 @@ define <2 x i64> @v_mvnQi64(<2 x i64>* %A) nounwind { define <8 x i8> @v_orri8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ; CHECK-LABEL: v_orri8: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vldr d16, [r1] ; CHECK-NEXT: vldr d17, [r0] ; CHECK-NEXT: vorr d16, d17, d16 @@ -473,7 +473,7 @@ define <8 x i8> @v_orri8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i16> @v_orri16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ; CHECK-LABEL: v_orri16: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vldr d16, [r1] ; CHECK-NEXT: vldr d17, [r0] ; CHECK-NEXT: vorr d16, d17, d16 @@ -487,7 +487,7 @@ define <4 x i16> @v_orri16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i32> @v_orri32(<2 x i32>* %A, <2 x i32>* %B) nounwind { ; CHECK-LABEL: v_orri32: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vldr d16, [r1] ; CHECK-NEXT: vldr d17, [r0] ; CHECK-NEXT: vorr d16, d17, d16 @@ -501,7 +501,7 @@ define <2 x i32> @v_orri32(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <1 x i64> @v_orri64(<1 x i64>* %A, <1 x i64>* %B) nounwind { ; CHECK-LABEL: v_orri64: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vldr d16, [r1] ; CHECK-NEXT: vldr d17, [r0] ; CHECK-NEXT: vorr d16, d17, d16 @@ -515,7 +515,7 @@ define <1 x i64> @v_orri64(<1 x i64>* %A, <1 x i64>* %B) nounwind { define <16 x i8> @v_orrQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { ; CHECK-LABEL: v_orrQi8: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r1] ; CHECK-NEXT: vld1.64 {d18, d19}, [r0] ; CHECK-NEXT: vorr q8, q9, q8 @@ -530,7 +530,7 @@ define <16 x i8> @v_orrQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <8 x i16> @v_orrQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { ; CHECK-LABEL: v_orrQi16: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r1] ; CHECK-NEXT: vld1.64 {d18, d19}, [r0] ; CHECK-NEXT: vorr q8, q9, q8 @@ -545,7 +545,7 @@ define <8 x i16> @v_orrQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i32> @v_orrQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { ; CHECK-LABEL: v_orrQi32: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r1] ; CHECK-NEXT: vld1.64 {d18, d19}, [r0] ; CHECK-NEXT: vorr q8, q9, q8 @@ -560,7 +560,7 @@ define <4 x i32> @v_orrQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <2 x i64> @v_orrQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind { ; CHECK-LABEL: v_orrQi64: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r1] ; CHECK-NEXT: vld1.64 {d18, d19}, [r0] ; CHECK-NEXT: vorr q8, q9, q8 @@ -575,7 +575,7 @@ define <2 x i64> @v_orrQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind { define <8 x i8> @v_orni8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ; CHECK-LABEL: v_orni8: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vldr d16, [r1] ; CHECK-NEXT: vldr d17, [r0] ; CHECK-NEXT: vorn d16, d17, d16 @@ -590,7 +590,7 @@ define <8 x i8> @v_orni8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i16> @v_orni16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ; CHECK-LABEL: v_orni16: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vldr d16, [r1] ; CHECK-NEXT: vldr d17, [r0] ; CHECK-NEXT: vorn d16, d17, d16 @@ -605,7 +605,7 @@ define <4 x i16> @v_orni16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i32> @v_orni32(<2 x i32>* %A, <2 x i32>* %B) nounwind { ; CHECK-LABEL: v_orni32: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vldr d16, [r1] ; CHECK-NEXT: vldr d17, [r0] ; CHECK-NEXT: vorn d16, d17, d16 @@ -620,7 +620,7 @@ define <2 x i32> @v_orni32(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <1 x i64> @v_orni64(<1 x i64>* %A, <1 x i64>* %B) nounwind { ; CHECK-LABEL: v_orni64: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vldr d16, [r1] ; CHECK-NEXT: vldr d17, [r0] ; CHECK-NEXT: vorn d16, d17, d16 @@ -635,7 +635,7 @@ define <1 x i64> @v_orni64(<1 x i64>* %A, <1 x i64>* %B) nounwind { define <16 x i8> @v_ornQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { ; CHECK-LABEL: v_ornQi8: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r1] ; CHECK-NEXT: vld1.64 {d18, d19}, [r0] ; CHECK-NEXT: vorn q8, q9, q8 @@ -651,7 +651,7 @@ define <16 x i8> @v_ornQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <8 x i16> @v_ornQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { ; CHECK-LABEL: v_ornQi16: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r1] ; CHECK-NEXT: vld1.64 {d18, d19}, [r0] ; CHECK-NEXT: vorn q8, q9, q8 @@ -667,7 +667,7 @@ define <8 x i16> @v_ornQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i32> @v_ornQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { ; CHECK-LABEL: v_ornQi32: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r1] ; CHECK-NEXT: vld1.64 {d18, d19}, [r0] ; CHECK-NEXT: vorn q8, q9, q8 @@ -683,7 +683,7 @@ define <4 x i32> @v_ornQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <2 x i64> @v_ornQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind { ; CHECK-LABEL: v_ornQi64: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r1] ; CHECK-NEXT: vld1.64 {d18, d19}, [r0] ; CHECK-NEXT: vorn q8, q9, q8 @@ -699,7 +699,7 @@ define <2 x i64> @v_ornQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind { define <8 x i8> @vtsti8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ; CHECK-LABEL: vtsti8: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vldr d16, [r1] ; CHECK-NEXT: vldr d17, [r0] ; CHECK-NEXT: vtst.8 d16, d17, d16 @@ -715,7 +715,7 @@ define <8 x i8> @vtsti8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i16> @vtsti16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ; CHECK-LABEL: vtsti16: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vldr d16, [r1] ; CHECK-NEXT: vldr d17, [r0] ; CHECK-NEXT: vtst.16 d16, d17, d16 @@ -731,7 +731,7 @@ define <4 x i16> @vtsti16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i32> @vtsti32(<2 x i32>* %A, <2 x i32>* %B) nounwind { ; CHECK-LABEL: vtsti32: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vldr d16, [r1] ; CHECK-NEXT: vldr d17, [r0] ; CHECK-NEXT: vtst.32 d16, d17, d16 @@ -747,7 +747,7 @@ define <2 x i32> @vtsti32(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <16 x i8> @vtstQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { ; CHECK-LABEL: vtstQi8: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r1] ; CHECK-NEXT: vld1.64 {d18, d19}, [r0] ; CHECK-NEXT: vtst.8 q8, q9, q8 @@ -764,7 +764,7 @@ define <16 x i8> @vtstQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <8 x i16> @vtstQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { ; CHECK-LABEL: vtstQi16: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r1] ; CHECK-NEXT: vld1.64 {d18, d19}, [r0] ; CHECK-NEXT: vtst.16 q8, q9, q8 @@ -781,7 +781,7 @@ define <8 x i16> @vtstQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i32> @vtstQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { ; CHECK-LABEL: vtstQi32: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r1] ; CHECK-NEXT: vld1.64 {d18, d19}, [r0] ; CHECK-NEXT: vtst.32 q8, q9, q8 @@ -798,7 +798,7 @@ define <4 x i32> @vtstQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <8 x i8> @v_orrimm(<8 x i8>* %A) nounwind { ; CHECK-LABEL: v_orrimm: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vldr d16, [r0] ; CHECK-NEXT: vorr.i32 d16, #0x1000000 ; CHECK-NEXT: vmov r0, r1, d16 @@ -810,7 +810,7 @@ define <8 x i8> @v_orrimm(<8 x i8>* %A) nounwind { define <16 x i8> @v_orrimmQ(<16 x i8>* %A) nounwind { ; CHECK-LABEL: v_orrimmQ: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r0] ; CHECK-NEXT: vorr.i32 q8, #0x1000000 ; CHECK-NEXT: vmov r0, r1, d16 @@ -823,7 +823,7 @@ define <16 x i8> @v_orrimmQ(<16 x i8>* %A) nounwind { define <8 x i8> @v_bicimm(<8 x i8>* %A) nounwind { ; CHECK-LABEL: v_bicimm: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vldr d16, [r0] ; CHECK-NEXT: vbic.i32 d16, #0xff000000 ; CHECK-NEXT: vmov r0, r1, d16 @@ -835,7 +835,7 @@ define <8 x i8> @v_bicimm(<8 x i8>* %A) nounwind { define <16 x i8> @v_bicimmQ(<16 x i8>* %A) nounwind { ; CHECK-LABEL: v_bicimmQ: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r0] ; CHECK-NEXT: vbic.i32 q8, #0xff000000 ; CHECK-NEXT: vmov r0, r1, d16 @@ -848,7 +848,7 @@ define <16 x i8> @v_bicimmQ(<16 x i8>* %A) nounwind { define <4 x i32> @hidden_not_v4i32(<4 x i32> %x) nounwind { ; CHECK-LABEL: hidden_not_v4i32: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vmov d19, r2, r3 ; CHECK-NEXT: vmov.i32 q8, #0x6 ; CHECK-NEXT: vmov d18, r0, r1 diff --git a/test/CodeGen/ARM/vcvt.ll b/test/CodeGen/ARM/vcvt.ll index 5f470d60707c9..7052607bf80f4 100644 --- a/test/CodeGen/ARM/vcvt.ll +++ b/test/CodeGen/ARM/vcvt.ll @@ -3,7 +3,7 @@ define <2 x i32> @vcvt_f32tos32(<2 x float>* %A) nounwind { ; CHECK-LABEL: vcvt_f32tos32: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vldr d16, [r0] ; CHECK-NEXT: vcvt.s32.f32 d16, d16 ; CHECK-NEXT: vmov r0, r1, d16 @@ -15,7 +15,7 @@ define <2 x i32> @vcvt_f32tos32(<2 x float>* %A) nounwind { define <2 x i32> @vcvt_f32tou32(<2 x float>* %A) nounwind { ; CHECK-LABEL: vcvt_f32tou32: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vldr d16, [r0] ; CHECK-NEXT: vcvt.u32.f32 d16, d16 ; CHECK-NEXT: vmov r0, r1, d16 @@ -27,7 +27,7 @@ define <2 x i32> @vcvt_f32tou32(<2 x float>* %A) nounwind { define <2 x float> @vcvt_s32tof32(<2 x i32>* %A) nounwind { ; CHECK-LABEL: vcvt_s32tof32: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vldr d16, [r0] ; CHECK-NEXT: vcvt.f32.s32 d16, d16 ; CHECK-NEXT: vmov r0, r1, d16 @@ -39,7 +39,7 @@ define <2 x float> @vcvt_s32tof32(<2 x i32>* %A) nounwind { define <2 x float> @vcvt_u32tof32(<2 x i32>* %A) nounwind { ; CHECK-LABEL: vcvt_u32tof32: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vldr d16, [r0] ; CHECK-NEXT: vcvt.f32.u32 d16, d16 ; CHECK-NEXT: vmov r0, r1, d16 @@ -51,7 +51,7 @@ define <2 x float> @vcvt_u32tof32(<2 x i32>* %A) nounwind { define <4 x i32> @vcvtQ_f32tos32(<4 x float>* %A) nounwind { ; CHECK-LABEL: vcvtQ_f32tos32: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r0] ; CHECK-NEXT: vcvt.s32.f32 q8, q8 ; CHECK-NEXT: vmov r0, r1, d16 @@ -64,7 +64,7 @@ define <4 x i32> @vcvtQ_f32tos32(<4 x float>* %A) nounwind { define <4 x i32> @vcvtQ_f32tou32(<4 x float>* %A) nounwind { ; CHECK-LABEL: vcvtQ_f32tou32: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r0] ; CHECK-NEXT: vcvt.u32.f32 q8, q8 ; CHECK-NEXT: vmov r0, r1, d16 @@ -77,7 +77,7 @@ define <4 x i32> @vcvtQ_f32tou32(<4 x float>* %A) nounwind { define <4 x float> @vcvtQ_s32tof32(<4 x i32>* %A) nounwind { ; CHECK-LABEL: vcvtQ_s32tof32: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r0] ; CHECK-NEXT: vcvt.f32.s32 q8, q8 ; CHECK-NEXT: vmov r0, r1, d16 @@ -90,7 +90,7 @@ define <4 x float> @vcvtQ_s32tof32(<4 x i32>* %A) nounwind { define <4 x float> @vcvtQ_u32tof32(<4 x i32>* %A) nounwind { ; CHECK-LABEL: vcvtQ_u32tof32: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r0] ; CHECK-NEXT: vcvt.f32.u32 q8, q8 ; CHECK-NEXT: vmov r0, r1, d16 @@ -103,7 +103,7 @@ define <4 x float> @vcvtQ_u32tof32(<4 x i32>* %A) nounwind { define <2 x i32> @vcvt_n_f32tos32(<2 x float>* %A) nounwind { ; CHECK-LABEL: vcvt_n_f32tos32: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vldr d16, [r0] ; CHECK-NEXT: vcvt.s32.f32 d16, d16, #1 ; CHECK-NEXT: vmov r0, r1, d16 @@ -115,7 +115,7 @@ define <2 x i32> @vcvt_n_f32tos32(<2 x float>* %A) nounwind { define <2 x i32> @vcvt_n_f32tou32(<2 x float>* %A) nounwind { ; CHECK-LABEL: vcvt_n_f32tou32: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vldr d16, [r0] ; CHECK-NEXT: vcvt.u32.f32 d16, d16, #1 ; CHECK-NEXT: vmov r0, r1, d16 @@ -127,7 +127,7 @@ define <2 x i32> @vcvt_n_f32tou32(<2 x float>* %A) nounwind { define <2 x float> @vcvt_n_s32tof32(<2 x i32>* %A) nounwind { ; CHECK-LABEL: vcvt_n_s32tof32: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vldr d16, [r0] ; CHECK-NEXT: vcvt.f32.s32 d16, d16, #1 ; CHECK-NEXT: vmov r0, r1, d16 @@ -139,7 +139,7 @@ define <2 x float> @vcvt_n_s32tof32(<2 x i32>* %A) nounwind { define <2 x float> @vcvt_n_u32tof32(<2 x i32>* %A) nounwind { ; CHECK-LABEL: vcvt_n_u32tof32: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vldr d16, [r0] ; CHECK-NEXT: vcvt.f32.u32 d16, d16, #1 ; CHECK-NEXT: vmov r0, r1, d16 @@ -156,7 +156,7 @@ declare <2 x float> @llvm.arm.neon.vcvtfxu2fp.v2f32.v2i32(<2 x i32>, i32) nounwi define <4 x i32> @vcvtQ_n_f32tos32(<4 x float>* %A) nounwind { ; CHECK-LABEL: vcvtQ_n_f32tos32: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r0] ; CHECK-NEXT: vcvt.s32.f32 q8, q8, #1 ; CHECK-NEXT: vmov r0, r1, d16 @@ -169,7 +169,7 @@ define <4 x i32> @vcvtQ_n_f32tos32(<4 x float>* %A) nounwind { define <4 x i32> @vcvtQ_n_f32tou32(<4 x float>* %A) nounwind { ; CHECK-LABEL: vcvtQ_n_f32tou32: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r0] ; CHECK-NEXT: vcvt.u32.f32 q8, q8, #1 ; CHECK-NEXT: vmov r0, r1, d16 @@ -182,7 +182,7 @@ define <4 x i32> @vcvtQ_n_f32tou32(<4 x float>* %A) nounwind { define <4 x float> @vcvtQ_n_s32tof32(<4 x i32>* %A) nounwind { ; CHECK-LABEL: vcvtQ_n_s32tof32: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r0] ; CHECK-NEXT: vcvt.f32.s32 q8, q8, #1 ; CHECK-NEXT: vmov r0, r1, d16 @@ -195,7 +195,7 @@ define <4 x float> @vcvtQ_n_s32tof32(<4 x i32>* %A) nounwind { define <4 x float> @vcvtQ_n_u32tof32(<4 x i32>* %A) nounwind { ; CHECK-LABEL: vcvtQ_n_u32tof32: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r0] ; CHECK-NEXT: vcvt.f32.u32 q8, q8, #1 ; CHECK-NEXT: vmov r0, r1, d16 @@ -213,7 +213,7 @@ declare <4 x float> @llvm.arm.neon.vcvtfxu2fp.v4f32.v4i32(<4 x i32>, i32) nounwi define <4 x float> @vcvt_f16tof32(<4 x i16>* %A) nounwind { ; CHECK-LABEL: vcvt_f16tof32: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vldr d16, [r0] ; CHECK-NEXT: vcvt.f32.f16 q8, d16 ; CHECK-NEXT: vmov r0, r1, d16 @@ -226,7 +226,7 @@ define <4 x float> @vcvt_f16tof32(<4 x i16>* %A) nounwind { define <4 x i16> @vcvt_f32tof16(<4 x float>* %A) nounwind { ; CHECK-LABEL: vcvt_f32tof16: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r0] ; CHECK-NEXT: vcvt.f16.f32 d16, q8 ; CHECK-NEXT: vmov r0, r1, d16 @@ -242,7 +242,7 @@ declare <4 x i16> @llvm.arm.neon.vcvtfp2hf(<4 x float>) nounwind readnone define <4 x i16> @fix_float_to_i16(<4 x float> %in) { ; CHECK-LABEL: fix_float_to_i16: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vmov d17, r2, r3 ; CHECK-NEXT: vmov d16, r0, r1 ; CHECK-NEXT: vcvt.u32.f32 q8, q8, #1 @@ -257,7 +257,7 @@ define <4 x i16> @fix_float_to_i16(<4 x float> %in) { define <2 x i64> @fix_float_to_i64(<2 x float> %in) { ; CHECK-LABEL: fix_float_to_i64: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: .save {r4, lr} ; CHECK-NEXT: push {r4, lr} ; CHECK-NEXT: .vsave {d8, d9} @@ -287,7 +287,7 @@ define <2 x i64> @fix_float_to_i64(<2 x float> %in) { define <4 x i16> @fix_double_to_i16(<4 x double> %in) { ; CHECK-LABEL: fix_double_to_i16: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vmov d18, r0, r1 ; CHECK-NEXT: mov r12, sp ; CHECK-NEXT: vld1.64 {d16, d17}, [r12] @@ -319,7 +319,7 @@ define <4 x i16> @fix_double_to_i16(<4 x double> %in) { define <2 x i64> @fix_double_to_i64(<2 x double> %in) { ; CHECK-LABEL: fix_double_to_i64: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: .save {r4, lr} ; CHECK-NEXT: push {r4, lr} ; CHECK-NEXT: .vsave {d8, d9} @@ -352,7 +352,7 @@ define <2 x i64> @fix_double_to_i64(<2 x double> %in) { define i32 @multi_sint(double %c, i32* nocapture %p, i32* nocapture %q) { ; CHECK-LABEL: multi_sint: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vmov d16, r0, r1 ; CHECK-NEXT: vcvt.s32.f64 s0, d16 ; CHECK-NEXT: vstr s0, [r2] @@ -369,7 +369,7 @@ define i32 @multi_sint(double %c, i32* nocapture %p, i32* nocapture %q) { define i32 @multi_uint(double %c, i32* nocapture %p, i32* nocapture %q) { ; CHECK-LABEL: multi_uint: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vmov d16, r0, r1 ; CHECK-NEXT: vcvt.u32.f64 s0, d16 ; CHECK-NEXT: vstr s0, [r2] @@ -386,7 +386,7 @@ define i32 @multi_uint(double %c, i32* nocapture %p, i32* nocapture %q) { define void @double_to_sint_store(double %c, i32* nocapture %p) { ; CHECK-LABEL: double_to_sint_store: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vmov d16, r0, r1 ; CHECK-NEXT: vcvt.s32.f64 s0, d16 ; CHECK-NEXT: vstr s0, [r2] @@ -398,7 +398,7 @@ define void @double_to_sint_store(double %c, i32* nocapture %p) { define void @double_to_uint_store(double %c, i32* nocapture %p) { ; CHECK-LABEL: double_to_uint_store: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vmov d16, r0, r1 ; CHECK-NEXT: vcvt.u32.f64 s0, d16 ; CHECK-NEXT: vstr s0, [r2] @@ -410,7 +410,7 @@ define void @double_to_uint_store(double %c, i32* nocapture %p) { define void @float_to_sint_store(float %c, i32* nocapture %p) { ; CHECK-LABEL: float_to_sint_store: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vcvt.s32.f32 s0, s0 ; CHECK-NEXT: vstr s0, [r1] @@ -422,7 +422,7 @@ define void @float_to_sint_store(float %c, i32* nocapture %p) { define void @float_to_uint_store(float %c, i32* nocapture %p) { ; CHECK-LABEL: float_to_uint_store: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vcvt.u32.f32 s0, s0 ; CHECK-NEXT: vstr s0, [r1] diff --git a/test/CodeGen/ARM/vcvt_combine.ll b/test/CodeGen/ARM/vcvt_combine.ll index 11bed5a1a474e..326c5f761a987 100644 --- a/test/CodeGen/ARM/vcvt_combine.ll +++ b/test/CodeGen/ARM/vcvt_combine.ll @@ -69,4 +69,4 @@ define <3 x i32> @test_illegal_fp_to_int(<3 x float> %in) { %scale = fmul <3 x float> %in, %val = fptosi <3 x float> %scale to <3 x i32> ret <3 x i32> %val -} \ No newline at end of file +} diff --git a/test/CodeGen/ARM/vdiv_combine.ll b/test/CodeGen/ARM/vdiv_combine.ll index 4a6c36b427727..d88fe31a59d26 100644 --- a/test/CodeGen/ARM/vdiv_combine.ll +++ b/test/CodeGen/ARM/vdiv_combine.ll @@ -160,4 +160,4 @@ define <3 x float> @test_illegal_int_to_fp(<3 x i32> %in) { %conv = sitofp <3 x i32> %in to <3 x float> %res = fdiv <3 x float> %conv, ret <3 x float> %res -} \ No newline at end of file +} diff --git a/test/CodeGen/ARM/vext.ll b/test/CodeGen/ARM/vext.ll index 5b524145be760..397680c5b0cfe 100644 --- a/test/CodeGen/ARM/vext.ll +++ b/test/CodeGen/ARM/vext.ll @@ -3,7 +3,7 @@ define <8 x i8> @test_vextd(<8 x i8>* %A, <8 x i8>* %B) nounwind { ; CHECK-LABEL: test_vextd: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vldr d16, [r1] ; CHECK-NEXT: vldr d17, [r0] ; CHECK-NEXT: vext.8 d16, d17, d16, #3 @@ -17,7 +17,7 @@ define <8 x i8> @test_vextd(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <8 x i8> @test_vextRd(<8 x i8>* %A, <8 x i8>* %B) nounwind { ; CHECK-LABEL: test_vextRd: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vldr d16, [r0] ; CHECK-NEXT: vldr d17, [r1] ; CHECK-NEXT: vext.8 d16, d17, d16, #5 @@ -31,7 +31,7 @@ define <8 x i8> @test_vextRd(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <16 x i8> @test_vextq(<16 x i8>* %A, <16 x i8>* %B) nounwind { ; CHECK-LABEL: test_vextq: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r1] ; CHECK-NEXT: vld1.64 {d18, d19}, [r0] ; CHECK-NEXT: vext.8 q8, q9, q8, #3 @@ -46,7 +46,7 @@ define <16 x i8> @test_vextq(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <16 x i8> @test_vextRq(<16 x i8>* %A, <16 x i8>* %B) nounwind { ; CHECK-LABEL: test_vextRq: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r0] ; CHECK-NEXT: vld1.64 {d18, d19}, [r1] ; CHECK-NEXT: vext.8 q8, q9, q8, #7 @@ -61,7 +61,7 @@ define <16 x i8> @test_vextRq(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <4 x i16> @test_vextd16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ; CHECK-LABEL: test_vextd16: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vldr d16, [r1] ; CHECK-NEXT: vldr d17, [r0] ; CHECK-NEXT: vext.16 d16, d17, d16, #3 @@ -75,7 +75,7 @@ define <4 x i16> @test_vextd16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <4 x i32> @test_vextq32(<4 x i32>* %A, <4 x i32>* %B) nounwind { ; CHECK-LABEL: test_vextq32: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r1] ; CHECK-NEXT: vld1.64 {d18, d19}, [r0] ; CHECK-NEXT: vext.32 q8, q9, q8, #3 @@ -92,7 +92,7 @@ define <4 x i32> @test_vextq32(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <8 x i8> @test_vextd_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind { ; CHECK-LABEL: test_vextd_undef: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vldr d16, [r1] ; CHECK-NEXT: vldr d17, [r0] ; CHECK-NEXT: vext.8 d16, d17, d16, #3 @@ -106,7 +106,7 @@ define <8 x i8> @test_vextd_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <16 x i8> @test_vextRq_undef(<16 x i8>* %A, <16 x i8>* %B) nounwind { ; CHECK-LABEL: test_vextRq_undef: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r0] ; CHECK-NEXT: vld1.64 {d18, d19}, [r1] ; CHECK-NEXT: vext.8 q8, q9, q8, #7 @@ -121,7 +121,7 @@ define <16 x i8> @test_vextRq_undef(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <16 x i8> @test_vextq_undef_op2(<16 x i8> %a) nounwind { ; CHECK-LABEL: test_vextq_undef_op2: -; CHECK: @ BB#0: @ %entry +; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vmov d17, r2, r3 ; CHECK-NEXT: vmov d16, r0, r1 ; CHECK-NEXT: vext.8 q8, q8, q8, #2 @@ -135,7 +135,7 @@ entry: define <8 x i8> @test_vextd_undef_op2(<8 x i8> %a) nounwind { ; CHECK-LABEL: test_vextd_undef_op2: -; CHECK: @ BB#0: @ %entry +; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vmov d16, r0, r1 ; CHECK-NEXT: vext.8 d16, d16, d16, #2 ; CHECK-NEXT: vmov r0, r1, d16 @@ -148,7 +148,7 @@ entry: define <16 x i8> @test_vextq_undef_op2_undef(<16 x i8> %a) nounwind { ; CHECK-LABEL: test_vextq_undef_op2_undef: -; CHECK: @ BB#0: @ %entry +; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vmov d17, r2, r3 ; CHECK-NEXT: vmov d16, r0, r1 ; CHECK-NEXT: vext.8 q8, q8, q8, #2 @@ -162,7 +162,7 @@ entry: define <8 x i8> @test_vextd_undef_op2_undef(<8 x i8> %a) nounwind { ; CHECK-LABEL: test_vextd_undef_op2_undef: -; CHECK: @ BB#0: @ %entry +; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vmov d16, r0, r1 ; CHECK-NEXT: vext.8 d16, d16, d16, #2 ; CHECK-NEXT: vmov r0, r1, d16 @@ -180,7 +180,7 @@ entry: ; Essence: a vext is used on %A and something saner than stack load/store for final result. define <4 x i16> @test_interleaved(<8 x i16>* %A, <8 x i16>* %B) nounwind { ; CHECK-LABEL: test_interleaved: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r0] ; CHECK-NEXT: vext.16 d16, d16, d17, #3 ; CHECK-NEXT: vorr d17, d16, d16 @@ -198,7 +198,7 @@ define <4 x i16> @test_interleaved(<8 x i16>* %A, <8 x i16>* %B) nounwind { ; An undef in the shuffle list should still be optimizable define <4 x i16> @test_undef(<8 x i16>* %A, <8 x i16>* %B) nounwind { ; CHECK-LABEL: test_undef: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vldr d16, [r1] ; CHECK-NEXT: vldr d17, [r0, #8] ; CHECK-NEXT: vzip.16 d17, d16 @@ -215,7 +215,7 @@ define <4 x i16> @test_undef(<8 x i16>* %A, <8 x i16>* %B) nounwind { ; Try to look for fallback to by-element inserts. define <4 x i16> @test_multisource(<32 x i16>* %B) nounwind { ; CHECK-LABEL: test_multisource: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: mov r1, r0 ; CHECK-NEXT: add r2, r0, #48 ; CHECK-NEXT: add r0, r0, #32 @@ -240,7 +240,7 @@ define <4 x i16> @test_multisource(<32 x i16>* %B) nounwind { ; Again, test for fallback to by-element inserts. define <4 x i16> @test_largespan(<8 x i16>* %B) nounwind { ; CHECK-LABEL: test_largespan: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r0] ; CHECK-NEXT: vorr d18, d16, d16 ; CHECK-NEXT: vuzp.16 d18, d17 @@ -258,7 +258,7 @@ define <4 x i16> @test_largespan(<8 x i16>* %B) nounwind { ; really important.) define <8 x i16> @test_illegal(<8 x i16>* %A, <8 x i16>* %B) nounwind { ; CHECK-LABEL: test_illegal: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r0] ; CHECK-NEXT: vorr d22, d16, d16 ; CHECK-NEXT: vmov.u16 r0, d16[0] @@ -287,7 +287,7 @@ define <8 x i16> @test_illegal(<8 x i16>* %A, <8 x i16>* %B) nounwind { ; Make sure this doesn't crash define arm_aapcscc void @test_elem_mismatch(<2 x i64>* nocapture %src, <4 x i16>* nocapture %dest) nounwind { ; CHECK-LABEL: test_elem_mismatch: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r0:128] ; CHECK-NEXT: vmov.32 r0, d16[0] ; CHECK-NEXT: vmov.32 r2, d17[0] @@ -309,7 +309,7 @@ define arm_aapcscc void @test_elem_mismatch(<2 x i64>* nocapture %src, <4 x i16> define <4 x i32> @test_reverse_and_extract(<2 x i32>* %A) { ; CHECK-LABEL: test_reverse_and_extract: -; CHECK: @ BB#0: @ %entry +; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vldr d16, [r0] ; CHECK-NEXT: vrev64.32 q9, q8 ; CHECK-NEXT: vext.32 q8, q8, q9, #2 @@ -324,7 +324,7 @@ entry: define <4 x i32> @test_dup_and_extract(<2 x i32>* %A) { ; CHECK-LABEL: test_dup_and_extract: -; CHECK: @ BB#0: @ %entry +; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vldr d16, [r0] ; CHECK-NEXT: vdup.32 q9, d16[0] ; CHECK-NEXT: vext.32 q8, q9, q8, #2 @@ -339,7 +339,7 @@ entry: define <4 x i32> @test_zip_and_extract(<2 x i32>* %A) { ; CHECK-LABEL: test_zip_and_extract: -; CHECK: @ BB#0: @ %entry +; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vldr d16, [r0] ; CHECK-NEXT: vorr q9, q8, q8 ; CHECK-NEXT: vorr q10, q8, q8 diff --git a/test/CodeGen/ARM/virtregrewriter-subregliveness.mir b/test/CodeGen/ARM/virtregrewriter-subregliveness.mir index 83335a3ccffdf..44bc856c914d1 100644 --- a/test/CodeGen/ARM/virtregrewriter-subregliveness.mir +++ b/test/CodeGen/ARM/virtregrewriter-subregliveness.mir @@ -33,7 +33,7 @@ body: | ; CHECK-NEXT: %r1 = KILL %r1, implicit killed %r0_r1 undef %0.gsub_0 = COPY %r0 %0.gsub_1 = COPY %r1 - tBX_RET 14, _, implicit %0 + tBX_RET 14, %noreg, implicit %0 ... @@ -55,7 +55,7 @@ body: | ; CHECK: %r0 = KILL %r0, implicit-def %r0_r1 ; CHECK-NEXT: tBX_RET undef %0.gsub_0 = COPY %r0 - tBX_RET 14, _, implicit %0 + tBX_RET 14, %noreg, implicit %0 ... @@ -78,7 +78,7 @@ body: | ; CHECK: %r0 = KILL %r0, implicit-def %r1, implicit-def %r0_r1 ; CHECK-NEXT: tBX_RET undef %0.gsub_0 = COPY %r0, implicit-def %r1 - tBX_RET 14, _, implicit %0 + tBX_RET 14, %noreg, implicit %0 ... diff --git a/test/CodeGen/ARM/vldm-liveness.mir b/test/CodeGen/ARM/vldm-liveness.mir index a85a018a8b1a5..2056be4f00889 100644 --- a/test/CodeGen/ARM/vldm-liveness.mir +++ b/test/CodeGen/ARM/vldm-liveness.mir @@ -26,15 +26,15 @@ body: | bb.0 (%ir-block.0): liveins: %r0 - %s1 = VLDRS %r0, 1, 14, _, implicit-def %q0 :: (load 4) - %s3 = VLDRS %r0, 2, 14, _, implicit killed %q0, implicit-def %q0 :: (load 4) - ; CHECK: %s3 = VLDRS %r0, 2, 14, _, implicit killed undef %q0, implicit-def %q0 :: (load 4) + %s1 = VLDRS %r0, 1, 14, %noreg, implicit-def %q0 :: (load 4) + %s3 = VLDRS %r0, 2, 14, %noreg, implicit killed %q0, implicit-def %q0 :: (load 4) + ; CHECK: %s3 = VLDRS %r0, 2, 14, %noreg, implicit killed undef %q0, implicit-def %q0 :: (load 4) - %s0 = VLDRS %r0, 0, 14, _, implicit killed %q0, implicit-def %q0 :: (load 4) - ; CHECK: VLDMSIA %r0, 14, _, def %s0, def %s1, implicit-def _ + %s0 = VLDRS %r0, 0, 14, %noreg, implicit killed %q0, implicit-def %q0 :: (load 4) + ; CHECK: VLDMSIA %r0, 14, %noreg, def %s0, def %s1, implicit-def %noreg - %s2 = VLDRS killed %r0, 4, 14, _, implicit killed %q0, implicit-def %q0 :: (load 4) - ; CHECK: %s2 = VLDRS killed %r0, 4, 14, _, implicit killed %q0, implicit-def %q0 :: (load 4) + %s2 = VLDRS killed %r0, 4, 14, %noreg, implicit killed %q0, implicit-def %q0 :: (load 4) + ; CHECK: %s2 = VLDRS killed %r0, 4, 14, %noreg, implicit killed %q0, implicit-def %q0 :: (load 4) - tBX_RET 14, _, implicit %q0 + tBX_RET 14, %noreg, implicit %q0 ... diff --git a/test/CodeGen/ARM/vpadd.ll b/test/CodeGen/ARM/vpadd.ll index 3fa93bb43f03d..731bc373aaa61 100644 --- a/test/CodeGen/ARM/vpadd.ll +++ b/test/CodeGen/ARM/vpadd.ll @@ -3,7 +3,7 @@ define <8 x i8> @vpaddi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ; CHECK-LABEL: vpaddi8: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vldr d16, [r1] ; CHECK-NEXT: vldr d17, [r0] ; CHECK-NEXT: vpadd.i8 d16, d17, d16 @@ -17,7 +17,7 @@ define <8 x i8> @vpaddi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i16> @vpaddi16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ; CHECK-LABEL: vpaddi16: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vldr d16, [r1] ; CHECK-NEXT: vldr d17, [r0] ; CHECK-NEXT: vpadd.i16 d16, d17, d16 @@ -31,7 +31,7 @@ define <4 x i16> @vpaddi16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i32> @vpaddi32(<2 x i32>* %A, <2 x i32>* %B) nounwind { ; CHECK-LABEL: vpaddi32: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vldr d16, [r1] ; CHECK-NEXT: vldr d17, [r0] ; CHECK-NEXT: vpadd.i32 d16, d17, d16 @@ -45,7 +45,7 @@ define <2 x i32> @vpaddi32(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <2 x float> @vpaddf32(<2 x float>* %A, <2 x float>* %B) nounwind { ; CHECK-LABEL: vpaddf32: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vldr d16, [r1] ; CHECK-NEXT: vldr d17, [r0] ; CHECK-NEXT: vpadd.f32 d16, d17, d16 @@ -65,7 +65,7 @@ declare <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float>, <2 x float>) nounwin define <4 x i16> @vpaddls8(<8 x i8>* %A) nounwind { ; CHECK-LABEL: vpaddls8: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vldr d16, [r0] ; CHECK-NEXT: vpaddl.s8 d16, d16 ; CHECK-NEXT: vmov r0, r1, d16 @@ -77,7 +77,7 @@ define <4 x i16> @vpaddls8(<8 x i8>* %A) nounwind { define <2 x i32> @vpaddls16(<4 x i16>* %A) nounwind { ; CHECK-LABEL: vpaddls16: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vldr d16, [r0] ; CHECK-NEXT: vpaddl.s16 d16, d16 ; CHECK-NEXT: vmov r0, r1, d16 @@ -89,7 +89,7 @@ define <2 x i32> @vpaddls16(<4 x i16>* %A) nounwind { define <1 x i64> @vpaddls32(<2 x i32>* %A) nounwind { ; CHECK-LABEL: vpaddls32: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vldr d16, [r0] ; CHECK-NEXT: vpaddl.s32 d16, d16 ; CHECK-NEXT: vmov r0, r1, d16 @@ -101,7 +101,7 @@ define <1 x i64> @vpaddls32(<2 x i32>* %A) nounwind { define <4 x i16> @vpaddlu8(<8 x i8>* %A) nounwind { ; CHECK-LABEL: vpaddlu8: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vldr d16, [r0] ; CHECK-NEXT: vpaddl.u8 d16, d16 ; CHECK-NEXT: vmov r0, r1, d16 @@ -113,7 +113,7 @@ define <4 x i16> @vpaddlu8(<8 x i8>* %A) nounwind { define <2 x i32> @vpaddlu16(<4 x i16>* %A) nounwind { ; CHECK-LABEL: vpaddlu16: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vldr d16, [r0] ; CHECK-NEXT: vpaddl.u16 d16, d16 ; CHECK-NEXT: vmov r0, r1, d16 @@ -125,7 +125,7 @@ define <2 x i32> @vpaddlu16(<4 x i16>* %A) nounwind { define <1 x i64> @vpaddlu32(<2 x i32>* %A) nounwind { ; CHECK-LABEL: vpaddlu32: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vldr d16, [r0] ; CHECK-NEXT: vpaddl.u32 d16, d16 ; CHECK-NEXT: vmov r0, r1, d16 @@ -137,7 +137,7 @@ define <1 x i64> @vpaddlu32(<2 x i32>* %A) nounwind { define <8 x i16> @vpaddlQs8(<16 x i8>* %A) nounwind { ; CHECK-LABEL: vpaddlQs8: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r0] ; CHECK-NEXT: vpaddl.s8 q8, q8 ; CHECK-NEXT: vmov r0, r1, d16 @@ -150,7 +150,7 @@ define <8 x i16> @vpaddlQs8(<16 x i8>* %A) nounwind { define <4 x i32> @vpaddlQs16(<8 x i16>* %A) nounwind { ; CHECK-LABEL: vpaddlQs16: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r0] ; CHECK-NEXT: vpaddl.s16 q8, q8 ; CHECK-NEXT: vmov r0, r1, d16 @@ -163,7 +163,7 @@ define <4 x i32> @vpaddlQs16(<8 x i16>* %A) nounwind { define <2 x i64> @vpaddlQs32(<4 x i32>* %A) nounwind { ; CHECK-LABEL: vpaddlQs32: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r0] ; CHECK-NEXT: vpaddl.s32 q8, q8 ; CHECK-NEXT: vmov r0, r1, d16 @@ -176,7 +176,7 @@ define <2 x i64> @vpaddlQs32(<4 x i32>* %A) nounwind { define <8 x i16> @vpaddlQu8(<16 x i8>* %A) nounwind { ; CHECK-LABEL: vpaddlQu8: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r0] ; CHECK-NEXT: vpaddl.u8 q8, q8 ; CHECK-NEXT: vmov r0, r1, d16 @@ -189,7 +189,7 @@ define <8 x i16> @vpaddlQu8(<16 x i8>* %A) nounwind { define <4 x i32> @vpaddlQu16(<8 x i16>* %A) nounwind { ; CHECK-LABEL: vpaddlQu16: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r0] ; CHECK-NEXT: vpaddl.u16 q8, q8 ; CHECK-NEXT: vmov r0, r1, d16 @@ -202,7 +202,7 @@ define <4 x i32> @vpaddlQu16(<8 x i16>* %A) nounwind { define <2 x i64> @vpaddlQu32(<4 x i32>* %A) nounwind { ; CHECK-LABEL: vpaddlQu32: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r0] ; CHECK-NEXT: vpaddl.u32 q8, q8 ; CHECK-NEXT: vmov r0, r1, d16 @@ -216,7 +216,7 @@ define <2 x i64> @vpaddlQu32(<4 x i32>* %A) nounwind { ; Combine vuzp+vadd->vpadd. define void @addCombineToVPADD_i8(<16 x i8> *%cbcr, <8 x i8> *%X) nounwind ssp { ; CHECK-LABEL: addCombineToVPADD_i8: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r0] ; CHECK-NEXT: vpadd.i8 d16, d16, d17 ; CHECK-NEXT: vstr d16, [r1] @@ -233,7 +233,7 @@ define void @addCombineToVPADD_i8(<16 x i8> *%cbcr, <8 x i8> *%X) nounwind ssp { ; Combine vuzp+vadd->vpadd. define void @addCombineToVPADD_i16(<8 x i16> *%cbcr, <4 x i16> *%X) nounwind ssp { ; CHECK-LABEL: addCombineToVPADD_i16: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r0] ; CHECK-NEXT: vpadd.i16 d16, d16, d17 ; CHECK-NEXT: vstr d16, [r1] @@ -249,7 +249,7 @@ define void @addCombineToVPADD_i16(<8 x i16> *%cbcr, <4 x i16> *%X) nounwind ssp ; Combine vtrn+vadd->vpadd. define void @addCombineToVPADD_i32(<4 x i32> *%cbcr, <2 x i32> *%X) nounwind ssp { ; CHECK-LABEL: addCombineToVPADD_i32: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r0] ; CHECK-NEXT: vpadd.i32 d16, d16, d17 ; CHECK-NEXT: vstr d16, [r1] @@ -265,7 +265,7 @@ define void @addCombineToVPADD_i32(<4 x i32> *%cbcr, <2 x i32> *%X) nounwind ssp ; Combine vuzp+vaddl->vpaddl define void @addCombineToVPADDLq_s8(<16 x i8> *%cbcr, <8 x i16> *%X) nounwind ssp { ; CHECK-LABEL: addCombineToVPADDLq_s8: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r0] ; CHECK-NEXT: vpaddl.s8 q8, q8 ; CHECK-NEXT: vst1.64 {d16, d17}, [r1] @@ -284,7 +284,7 @@ define void @addCombineToVPADDLq_s8(<16 x i8> *%cbcr, <8 x i16> *%X) nounwind ss ; FIXME: Legalization butchers the shuffles. define void @addCombineToVPADDL_s8(<16 x i8> *%cbcr, <4 x i16> *%X) nounwind ssp { ; CHECK-LABEL: addCombineToVPADDL_s8: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vmov.i16 d16, #0x8 ; CHECK-NEXT: vld1.64 {d18, d19}, [r0] ; CHECK-NEXT: vext.8 d17, d18, d16, #1 @@ -309,7 +309,7 @@ define void @addCombineToVPADDL_s8(<16 x i8> *%cbcr, <4 x i16> *%X) nounwind ssp ; Combine vuzp+vaddl->vpaddl define void @addCombineToVPADDLq_u8(<16 x i8> *%cbcr, <8 x i16> *%X) nounwind ssp { ; CHECK-LABEL: addCombineToVPADDLq_u8: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r0] ; CHECK-NEXT: vpaddl.u8 q8, q8 ; CHECK-NEXT: vst1.64 {d16, d17}, [r1] @@ -328,7 +328,7 @@ define void @addCombineToVPADDLq_u8(<16 x i8> *%cbcr, <8 x i16> *%X) nounwind ss ; shuffle is awkward, so this doesn't match at the moment. define void @addCombineToVPADDLq_u8_early_zext(<16 x i8> *%cbcr, <8 x i16> *%X) nounwind ssp { ; CHECK-LABEL: addCombineToVPADDLq_u8_early_zext: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r0] ; CHECK-NEXT: vmovl.u8 q9, d17 ; CHECK-NEXT: vmovl.u8 q8, d16 @@ -349,7 +349,7 @@ define void @addCombineToVPADDLq_u8_early_zext(<16 x i8> *%cbcr, <8 x i16> *%X) ; FIXME: Legalization butchers the shuffle. define void @addCombineToVPADDL_u8(<16 x i8> *%cbcr, <4 x i16> *%X) nounwind ssp { ; CHECK-LABEL: addCombineToVPADDL_u8: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r0] ; CHECK-NEXT: vext.8 d18, d16, d16, #1 ; CHECK-NEXT: vbic.i16 d16, #0xff00 @@ -370,7 +370,7 @@ define void @addCombineToVPADDL_u8(<16 x i8> *%cbcr, <4 x i16> *%X) nounwind ssp ; Matching to vpaddl.8 requires matching shuffle(zext()). define void @addCombineToVPADDL_u8_early_zext(<16 x i8> *%cbcr, <4 x i16> *%X) nounwind ssp { ; CHECK-LABEL: addCombineToVPADDL_u8_early_zext: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r0] ; CHECK-NEXT: vmovl.u8 q8, d16 ; CHECK-NEXT: vpadd.i16 d16, d16, d17 @@ -388,7 +388,7 @@ define void @addCombineToVPADDL_u8_early_zext(<16 x i8> *%cbcr, <4 x i16> *%X) n ; Combine vuzp+vaddl->vpaddl define void @addCombineToVPADDLq_s16(<8 x i16> *%cbcr, <4 x i32> *%X) nounwind ssp { ; CHECK-LABEL: addCombineToVPADDLq_s16: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r0] ; CHECK-NEXT: vpaddl.s16 q8, q8 ; CHECK-NEXT: vst1.64 {d16, d17}, [r1] @@ -406,7 +406,7 @@ define void @addCombineToVPADDLq_s16(<8 x i16> *%cbcr, <4 x i32> *%X) nounwind s ; Combine vuzp+vaddl->vpaddl define void @addCombineToVPADDLq_u16(<8 x i16> *%cbcr, <4 x i32> *%X) nounwind ssp { ; CHECK-LABEL: addCombineToVPADDLq_u16: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r0] ; CHECK-NEXT: vpaddl.u16 q8, q8 ; CHECK-NEXT: vst1.64 {d16, d17}, [r1] @@ -424,7 +424,7 @@ define void @addCombineToVPADDLq_u16(<8 x i16> *%cbcr, <4 x i32> *%X) nounwind s ; Combine vtrn+vaddl->vpaddl define void @addCombineToVPADDLq_s32(<4 x i32> *%cbcr, <2 x i64> *%X) nounwind ssp { ; CHECK-LABEL: addCombineToVPADDLq_s32: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r0] ; CHECK-NEXT: vpaddl.s32 q8, q8 ; CHECK-NEXT: vst1.64 {d16, d17}, [r1] @@ -442,7 +442,7 @@ define void @addCombineToVPADDLq_s32(<4 x i32> *%cbcr, <2 x i64> *%X) nounwind s ; Combine vtrn+vaddl->vpaddl define void @addCombineToVPADDLq_u32(<4 x i32> *%cbcr, <2 x i64> *%X) nounwind ssp { ; CHECK-LABEL: addCombineToVPADDLq_u32: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r0] ; CHECK-NEXT: vpaddl.u32 q8, q8 ; CHECK-NEXT: vst1.64 {d16, d17}, [r1] @@ -460,7 +460,7 @@ define void @addCombineToVPADDLq_u32(<4 x i32> *%cbcr, <2 x i64> *%X) nounwind s ; Legalization promotes the <4 x i8> to <4 x i16>. define <4 x i8> @fromExtendingExtractVectorElt_i8(<8 x i8> %in) { ; CHECK-LABEL: fromExtendingExtractVectorElt_i8: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vmov d16, r0, r1 ; CHECK-NEXT: vpaddl.s8 d16, d16 ; CHECK-NEXT: vmov r0, r1, d16 @@ -474,7 +474,7 @@ define <4 x i8> @fromExtendingExtractVectorElt_i8(<8 x i8> %in) { ; Legalization promotes the <2 x i16> to <2 x i32>. define <2 x i16> @fromExtendingExtractVectorElt_i16(<4 x i16> %in) { ; CHECK-LABEL: fromExtendingExtractVectorElt_i16: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vmov d16, r0, r1 ; CHECK-NEXT: vpaddl.s16 d16, d16 ; CHECK-NEXT: vmov r0, r1, d16 diff --git a/test/CodeGen/ARM/vtrn.ll b/test/CodeGen/ARM/vtrn.ll index df6336043fdfb..12cb504eda794 100644 --- a/test/CodeGen/ARM/vtrn.ll +++ b/test/CodeGen/ARM/vtrn.ll @@ -2,7 +2,7 @@ define <8 x i8> @vtrni8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ; CHECK-LABEL: vtrni8: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vldr d16, [r1] ; CHECK-NEXT: vldr d17, [r0] ; CHECK-NEXT: vtrn.8 d17, d16 @@ -19,7 +19,7 @@ define <8 x i8> @vtrni8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <16 x i8> @vtrni8_Qres(<8 x i8>* %A, <8 x i8>* %B) nounwind { ; CHECK-LABEL: vtrni8_Qres: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vldr [[LDR1:d[0-9]+]], [r1] ; CHECK-NEXT: vldr [[LDR0:d[0-9]+]], [r0] ; CHECK-NEXT: vtrn.8 [[LDR0]], [[LDR1]] @@ -34,7 +34,7 @@ define <16 x i8> @vtrni8_Qres(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i16> @vtrni16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ; CHECK-LABEL: vtrni16: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vldr d16, [r1] ; CHECK-NEXT: vldr d17, [r0] ; CHECK-NEXT: vtrn.16 d17, d16 @@ -51,7 +51,7 @@ define <4 x i16> @vtrni16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <8 x i16> @vtrni16_Qres(<4 x i16>* %A, <4 x i16>* %B) nounwind { ; CHECK-LABEL: vtrni16_Qres: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vldr [[LDR1:d[0-9]+]], [r1] ; CHECK-NEXT: vldr [[LDR0:d[0-9]+]], [r0] ; CHECK-NEXT: vtrn.16 [[LDR0]], [[LDR1]] @@ -66,7 +66,7 @@ define <8 x i16> @vtrni16_Qres(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i32> @vtrni32(<2 x i32>* %A, <2 x i32>* %B) nounwind { ; CHECK-LABEL: vtrni32: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vldr d16, [r1] ; CHECK-NEXT: vldr d17, [r0] ; CHECK-NEXT: vtrn.32 d17, d16 @@ -83,7 +83,7 @@ define <2 x i32> @vtrni32(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <4 x i32> @vtrni32_Qres(<2 x i32>* %A, <2 x i32>* %B) nounwind { ; CHECK-LABEL: vtrni32_Qres: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vldr [[LDR1:d[0-9]+]], [r1] ; CHECK-NEXT: vldr [[LDR0:d[0-9]+]], [r0] ; CHECK-NEXT: vtrn.32 [[LDR0]], [[LDR1]] @@ -98,7 +98,7 @@ define <4 x i32> @vtrni32_Qres(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <2 x float> @vtrnf(<2 x float>* %A, <2 x float>* %B) nounwind { ; CHECK-LABEL: vtrnf: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vldr d16, [r1] ; CHECK-NEXT: vldr d17, [r0] ; CHECK-NEXT: vtrn.32 d17, d16 @@ -115,7 +115,7 @@ define <2 x float> @vtrnf(<2 x float>* %A, <2 x float>* %B) nounwind { define <4 x float> @vtrnf_Qres(<2 x float>* %A, <2 x float>* %B) nounwind { ; CHECK-LABEL: vtrnf_Qres: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vldr [[LDR1:d[0-9]+]], [r1] ; CHECK-NEXT: vldr [[LDR0:d[0-9]+]], [r0] ; CHECK-NEXT: vtrn.32 [[LDR0]], [[LDR1]] @@ -130,7 +130,7 @@ define <4 x float> @vtrnf_Qres(<2 x float>* %A, <2 x float>* %B) nounwind { define <16 x i8> @vtrnQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { ; CHECK-LABEL: vtrnQi8: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r1] ; CHECK-NEXT: vld1.64 {d18, d19}, [r0] ; CHECK-NEXT: vtrn.8 q9, q8 @@ -148,7 +148,7 @@ define <16 x i8> @vtrnQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <32 x i8> @vtrnQi8_QQres(<16 x i8>* %A, <16 x i8>* %B) nounwind { ; CHECK-LABEL: vtrnQi8_QQres: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r2] ; CHECK-NEXT: vld1.64 {d18, d19}, [r1] ; CHECK-NEXT: vtrn.8 q9, q8 @@ -163,7 +163,7 @@ define <32 x i8> @vtrnQi8_QQres(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <8 x i16> @vtrnQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { ; CHECK-LABEL: vtrnQi16: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r1] ; CHECK-NEXT: vld1.64 {d18, d19}, [r0] ; CHECK-NEXT: vtrn.16 q9, q8 @@ -181,7 +181,7 @@ define <8 x i16> @vtrnQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <16 x i16> @vtrnQi16_QQres(<8 x i16>* %A, <8 x i16>* %B) nounwind { ; CHECK-LABEL: vtrnQi16_QQres: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r2] ; CHECK-NEXT: vld1.64 {d18, d19}, [r1] ; CHECK-NEXT: vtrn.16 q9, q8 @@ -196,7 +196,7 @@ define <16 x i16> @vtrnQi16_QQres(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i32> @vtrnQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { ; CHECK-LABEL: vtrnQi32: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r1] ; CHECK-NEXT: vld1.64 {d18, d19}, [r0] ; CHECK-NEXT: vtrn.32 q9, q8 @@ -214,7 +214,7 @@ define <4 x i32> @vtrnQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <8 x i32> @vtrnQi32_QQres(<4 x i32>* %A, <4 x i32>* %B) nounwind { ; CHECK-LABEL: vtrnQi32_QQres: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r2] ; CHECK-NEXT: vld1.64 {d18, d19}, [r1] ; CHECK-NEXT: vtrn.32 q9, q8 @@ -229,7 +229,7 @@ define <8 x i32> @vtrnQi32_QQres(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <4 x float> @vtrnQf(<4 x float>* %A, <4 x float>* %B) nounwind { ; CHECK-LABEL: vtrnQf: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r1] ; CHECK-NEXT: vld1.64 {d18, d19}, [r0] ; CHECK-NEXT: vtrn.32 q9, q8 @@ -247,7 +247,7 @@ define <4 x float> @vtrnQf(<4 x float>* %A, <4 x float>* %B) nounwind { define <8 x float> @vtrnQf_QQres(<4 x float>* %A, <4 x float>* %B) nounwind { ; CHECK-LABEL: vtrnQf_QQres: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r2] ; CHECK-NEXT: vld1.64 {d18, d19}, [r1] ; CHECK-NEXT: vtrn.32 q9, q8 @@ -263,7 +263,7 @@ define <8 x float> @vtrnQf_QQres(<4 x float>* %A, <4 x float>* %B) nounwind { define <8 x i8> @vtrni8_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind { ; CHECK-LABEL: vtrni8_undef: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vldr d16, [r1] ; CHECK-NEXT: vldr d17, [r0] ; CHECK-NEXT: vtrn.8 d17, d16 @@ -280,7 +280,7 @@ define <8 x i8> @vtrni8_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <16 x i8> @vtrni8_undef_Qres(<8 x i8>* %A, <8 x i8>* %B) nounwind { ; CHECK-LABEL: vtrni8_undef_Qres: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vldr [[LDR1:d[0-9]+]], [r1] ; CHECK-NEXT: vldr [[LDR0:d[0-9]+]], [r0] ; CHECK-NEXT: vtrn.8 [[LDR0]], [[LDR1]] @@ -295,7 +295,7 @@ define <16 x i8> @vtrni8_undef_Qres(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <8 x i16> @vtrnQi16_undef(<8 x i16>* %A, <8 x i16>* %B) nounwind { ; CHECK-LABEL: vtrnQi16_undef: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r1] ; CHECK-NEXT: vld1.64 {d18, d19}, [r0] ; CHECK-NEXT: vtrn.16 q9, q8 @@ -313,7 +313,7 @@ define <8 x i16> @vtrnQi16_undef(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <16 x i16> @vtrnQi16_undef_QQres(<8 x i16>* %A, <8 x i16>* %B) nounwind { ; CHECK-LABEL: vtrnQi16_undef_QQres: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r2] ; CHECK-NEXT: vld1.64 {d18, d19}, [r1] ; CHECK-NEXT: vtrn.16 q9, q8 @@ -375,7 +375,7 @@ define <8 x i8> @vtrn_mismatched_builvector1(<8 x i8> %tr0, <8 x i8> %tr1, define void @lower_twice_no_vtrn(<4 x i16>* %A, <4 x i16>* %B, <8 x i16>* %C) { entry: ; CHECK-LABEL: lower_twice_no_vtrn: - ; CHECK: @ BB#0: + ; CHECK: @ %bb.0: ; CHECK-NEXT: vldr d16, [r1] ; CHECK-NEXT: vldr d18, [r0] ; CHECK-NEXT: vtrn.16 d18, d16 @@ -394,7 +394,7 @@ entry: define void @upper_twice_no_vtrn(<4 x i16>* %A, <4 x i16>* %B, <8 x i16>* %C) { entry: ; CHECK-LABEL: upper_twice_no_vtrn: - ; CHECK: @ BB#0: + ; CHECK: @ %bb.0: ; CHECK-NEXT: vldr d16, [r1] ; CHECK-NEXT: vldr d18, [r0] ; CHECK-NEXT: vtrn.16 d18, d16 diff --git a/test/CodeGen/ARM/vuzp.ll b/test/CodeGen/ARM/vuzp.ll index 24090cfd6c651..0ac366be3fea2 100644 --- a/test/CodeGen/ARM/vuzp.ll +++ b/test/CodeGen/ARM/vuzp.ll @@ -3,7 +3,7 @@ define <8 x i8> @vuzpi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ; CHECK-LABEL: vuzpi8: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vldr d16, [r1] ; CHECK-NEXT: vldr d17, [r0] ; CHECK-NEXT: vuzp.8 d17, d16 @@ -20,7 +20,7 @@ define <8 x i8> @vuzpi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <16 x i8> @vuzpi8_Qres(<8 x i8>* %A, <8 x i8>* %B) nounwind { ; CHECK-LABEL: vuzpi8_Qres: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vldr d17, [r1] ; CHECK-NEXT: vldr d16, [r0] ; CHECK-NEXT: vuzp.8 d16, d17 @@ -35,7 +35,7 @@ define <16 x i8> @vuzpi8_Qres(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i16> @vuzpi16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ; CHECK-LABEL: vuzpi16: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vldr d16, [r1] ; CHECK-NEXT: vldr d17, [r0] ; CHECK-NEXT: vuzp.16 d17, d16 @@ -52,7 +52,7 @@ define <4 x i16> @vuzpi16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <8 x i16> @vuzpi16_Qres(<4 x i16>* %A, <4 x i16>* %B) nounwind { ; CHECK-LABEL: vuzpi16_Qres: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vldr d17, [r1] ; CHECK-NEXT: vldr d16, [r0] ; CHECK-NEXT: vuzp.16 d16, d17 @@ -69,7 +69,7 @@ define <8 x i16> @vuzpi16_Qres(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <16 x i8> @vuzpQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { ; CHECK-LABEL: vuzpQi8: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r1] ; CHECK-NEXT: vld1.64 {d18, d19}, [r0] ; CHECK-NEXT: vuzp.8 q9, q8 @@ -87,7 +87,7 @@ define <16 x i8> @vuzpQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <32 x i8> @vuzpQi8_QQres(<16 x i8>* %A, <16 x i8>* %B) nounwind { ; CHECK-LABEL: vuzpQi8_QQres: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r2] ; CHECK-NEXT: vld1.64 {d18, d19}, [r1] ; CHECK-NEXT: vuzp.8 q9, q8 @@ -102,7 +102,7 @@ define <32 x i8> @vuzpQi8_QQres(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <8 x i16> @vuzpQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { ; CHECK-LABEL: vuzpQi16: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r1] ; CHECK-NEXT: vld1.64 {d18, d19}, [r0] ; CHECK-NEXT: vuzp.16 q9, q8 @@ -120,7 +120,7 @@ define <8 x i16> @vuzpQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <16 x i16> @vuzpQi16_QQres(<8 x i16>* %A, <8 x i16>* %B) nounwind { ; CHECK-LABEL: vuzpQi16_QQres: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r2] ; CHECK-NEXT: vld1.64 {d18, d19}, [r1] ; CHECK-NEXT: vuzp.16 q9, q8 @@ -135,7 +135,7 @@ define <16 x i16> @vuzpQi16_QQres(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i32> @vuzpQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { ; CHECK-LABEL: vuzpQi32: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r1] ; CHECK-NEXT: vld1.64 {d18, d19}, [r0] ; CHECK-NEXT: vuzp.32 q9, q8 @@ -153,7 +153,7 @@ define <4 x i32> @vuzpQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <8 x i32> @vuzpQi32_QQres(<4 x i32>* %A, <4 x i32>* %B) nounwind { ; CHECK-LABEL: vuzpQi32_QQres: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r2] ; CHECK-NEXT: vld1.64 {d18, d19}, [r1] ; CHECK-NEXT: vuzp.32 q9, q8 @@ -168,7 +168,7 @@ define <8 x i32> @vuzpQi32_QQres(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <4 x float> @vuzpQf(<4 x float>* %A, <4 x float>* %B) nounwind { ; CHECK-LABEL: vuzpQf: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r1] ; CHECK-NEXT: vld1.64 {d18, d19}, [r0] ; CHECK-NEXT: vuzp.32 q9, q8 @@ -186,7 +186,7 @@ define <4 x float> @vuzpQf(<4 x float>* %A, <4 x float>* %B) nounwind { define <8 x float> @vuzpQf_QQres(<4 x float>* %A, <4 x float>* %B) nounwind { ; CHECK-LABEL: vuzpQf_QQres: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r2] ; CHECK-NEXT: vld1.64 {d18, d19}, [r1] ; CHECK-NEXT: vuzp.32 q9, q8 @@ -203,7 +203,7 @@ define <8 x float> @vuzpQf_QQres(<4 x float>* %A, <4 x float>* %B) nounwind { define <8 x i8> @vuzpi8_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind { ; CHECK-LABEL: vuzpi8_undef: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vldr d16, [r1] ; CHECK-NEXT: vldr d17, [r0] ; CHECK-NEXT: vuzp.8 d17, d16 @@ -220,7 +220,7 @@ define <8 x i8> @vuzpi8_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <16 x i8> @vuzpi8_undef_Qres(<8 x i8>* %A, <8 x i8>* %B) nounwind { ; CHECK-LABEL: vuzpi8_undef_Qres: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vldr d17, [r1] ; CHECK-NEXT: vldr d16, [r0] ; CHECK-NEXT: vuzp.8 d16, d17 @@ -235,7 +235,7 @@ define <16 x i8> @vuzpi8_undef_Qres(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <8 x i16> @vuzpQi16_undef(<8 x i16>* %A, <8 x i16>* %B) nounwind { ; CHECK-LABEL: vuzpQi16_undef: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r1] ; CHECK-NEXT: vld1.64 {d18, d19}, [r0] ; CHECK-NEXT: vuzp.16 q9, q8 @@ -253,7 +253,7 @@ define <8 x i16> @vuzpQi16_undef(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <16 x i16> @vuzpQi16_undef_QQres(<8 x i16>* %A, <8 x i16>* %B) nounwind { ; CHECK-LABEL: vuzpQi16_undef_QQres: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r2] ; CHECK-NEXT: vld1.64 {d18, d19}, [r1] ; CHECK-NEXT: vuzp.16 q9, q8 @@ -268,7 +268,7 @@ define <16 x i16> @vuzpQi16_undef_QQres(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <8 x i16> @vuzp_lower_shufflemask_undef(<4 x i16>* %A, <4 x i16>* %B) { ; CHECK-LABEL: vuzp_lower_shufflemask_undef: -; CHECK: @ BB#0: @ %entry +; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vldr d17, [r1] ; CHECK-NEXT: vldr d16, [r0] ; CHECK-NEXT: vorr q9, q8, q8 @@ -285,7 +285,7 @@ entry: define <4 x i32> @vuzp_lower_shufflemask_zeroed(<2 x i32>* %A, <2 x i32>* %B) { ; CHECK-LABEL: vuzp_lower_shufflemask_zeroed: -; CHECK: @ BB#0: @ %entry +; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vldr d17, [r1] ; CHECK-NEXT: vldr d16, [r0] ; CHECK-NEXT: vdup.32 q9, d16[0] @@ -303,7 +303,7 @@ entry: define void @vuzp_rev_shufflemask_vtrn(<2 x i32>* %A, <2 x i32>* %B, <4 x i32>* %C) { ; CHECK-LABEL: vuzp_rev_shufflemask_vtrn: -; CHECK: @ BB#0: @ %entry +; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vldr d17, [r1] ; CHECK-NEXT: vldr d16, [r0] ; CHECK-NEXT: vrev64.32 q9, q8 @@ -323,7 +323,7 @@ define <8 x i8> @cmpsel_trunc(<8 x i8> %in0, <8 x i8> %in1, <8 x i32> %cmp0, <8 ; This results in a build_vector with mismatched types. We will generate two vmovn.i32 instructions to ; truncate from i32 to i16 and one vmovn.i16 to perform the final truncation for i8. ; CHECK-LABEL: cmpsel_trunc: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: add r12, sp, #16 ; CHECK-NEXT: vld1.64 {d16, d17}, [r12] ; CHECK-NEXT: mov r12, sp @@ -352,7 +352,7 @@ define <8 x i8> @cmpsel_trunc(<8 x i8> %in0, <8 x i8> %in1, <8 x i32> %cmp0, <8 ; to perform the vuzp and get the vbsl mask. define <8 x i8> @vuzp_trunc_and_shuffle(<8 x i8> %tr0, <8 x i8> %tr1, ; CHECK-LABEL: vuzp_trunc_and_shuffle: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: .save {r11, lr} ; CHECK-NEXT: push {r11, lr} ; CHECK-NEXT: add r12, sp, #8 @@ -388,7 +388,7 @@ define <8 x i8> @vuzp_trunc_and_shuffle(<8 x i8> %tr0, <8 x i8> %tr1, ; This produces a build_vector with some of the operands undefs. define <8 x i8> @vuzp_trunc_and_shuffle_undef_right(<8 x i8> %tr0, <8 x i8> %tr1, ; CHECK-LABEL: vuzp_trunc_and_shuffle_undef_right: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: mov r12, sp ; CHECK-NEXT: vld1.64 {d16, d17}, [r12] ; CHECK-NEXT: add r12, sp, #16 @@ -416,7 +416,7 @@ define <8 x i8> @vuzp_trunc_and_shuffle_undef_right(<8 x i8> %tr0, <8 x i8> %tr1 define <8 x i8> @vuzp_trunc_and_shuffle_undef_left(<8 x i8> %tr0, <8 x i8> %tr1, ; CHECK-LABEL: vuzp_trunc_and_shuffle_undef_left: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: mov r12, sp ; CHECK-NEXT: vld1.64 {d16, d17}, [r12] ; CHECK-NEXT: add r12, sp, #16 @@ -435,7 +435,7 @@ define <8 x i8> @vuzp_trunc_and_shuffle_undef_left(<8 x i8> %tr0, <8 x i8> %tr1, ; CHECK-NEXT: vmov r0, r1, d16 ; CHECK-NEXT: mov pc, lr ; CHECK-NEXT: .p2align 3 -; CHECK-NEXT: @ BB#1: +; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI22_0: ; CHECK-NEXT: .byte 255 @ 0xff ; CHECK-NEXT: .byte 255 @ 0xff @@ -458,7 +458,7 @@ define <8 x i8> @vuzp_trunc_and_shuffle_undef_left(<8 x i8> %tr0, <8 x i8> %tr1, ; get some vector size that we can represent. define <10 x i8> @vuzp_wide_type(<10 x i8> %tr0, <10 x i8> %tr1, ; CHECK-LABEL: vuzp_wide_type: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: .save {r4, r10, r11, lr} ; CHECK-NEXT: push {r4, r10, r11, lr} ; CHECK-NEXT: .setfp r11, sp, #8 @@ -517,7 +517,7 @@ define <10 x i8> @vuzp_wide_type(<10 x i8> %tr0, <10 x i8> %tr1, ; CHECK-NEXT: pop {r4, r10, r11, lr} ; CHECK-NEXT: mov pc, lr ; CHECK-NEXT: .p2align 3 -; CHECK-NEXT: @ BB#1: +; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI23_0: ; CHECK-NEXT: .byte 0 @ 0x0 ; CHECK-NEXT: .byte 1 @ 0x1 @@ -539,7 +539,7 @@ define <10 x i8> @vuzp_wide_type(<10 x i8> %tr0, <10 x i8> %tr1, %struct.uint8x8x2_t = type { [2 x <8 x i8>] } define %struct.uint8x8x2_t @vuzp_extract_subvector(<16 x i8> %t) #0 { ; CHECK-LABEL: vuzp_extract_subvector: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vmov d17, r2, r3 ; CHECK-NEXT: vmov d16, r0, r1 ; CHECK-NEXT: vorr d18, d17, d17 diff --git a/test/CodeGen/ARM/vzip.ll b/test/CodeGen/ARM/vzip.ll index 06b49ab94053d..5047b3e087ad3 100644 --- a/test/CodeGen/ARM/vzip.ll +++ b/test/CodeGen/ARM/vzip.ll @@ -3,7 +3,7 @@ define <8 x i8> @vzipi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ; CHECK-LABEL: vzipi8: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vldr d16, [r1] ; CHECK-NEXT: vldr d17, [r0] ; CHECK-NEXT: vzip.8 d17, d16 @@ -20,7 +20,7 @@ define <8 x i8> @vzipi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <16 x i8> @vzipi8_Qres(<8 x i8>* %A, <8 x i8>* %B) nounwind { ; CHECK-LABEL: vzipi8_Qres: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vldr d17, [r1] ; CHECK-NEXT: vldr d16, [r0] ; CHECK-NEXT: vzip.8 d16, d17 @@ -35,7 +35,7 @@ define <16 x i8> @vzipi8_Qres(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i16> @vzipi16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ; CHECK-LABEL: vzipi16: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vldr d16, [r1] ; CHECK-NEXT: vldr d17, [r0] ; CHECK-NEXT: vzip.16 d17, d16 @@ -52,7 +52,7 @@ define <4 x i16> @vzipi16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <8 x i16> @vzipi16_Qres(<4 x i16>* %A, <4 x i16>* %B) nounwind { ; CHECK-LABEL: vzipi16_Qres: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vldr d17, [r1] ; CHECK-NEXT: vldr d16, [r0] ; CHECK-NEXT: vzip.16 d16, d17 @@ -69,7 +69,7 @@ define <8 x i16> @vzipi16_Qres(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <16 x i8> @vzipQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { ; CHECK-LABEL: vzipQi8: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r1] ; CHECK-NEXT: vld1.64 {d18, d19}, [r0] ; CHECK-NEXT: vzip.8 q9, q8 @@ -87,7 +87,7 @@ define <16 x i8> @vzipQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <32 x i8> @vzipQi8_QQres(<16 x i8>* %A, <16 x i8>* %B) nounwind { ; CHECK-LABEL: vzipQi8_QQres: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r2] ; CHECK-NEXT: vld1.64 {d18, d19}, [r1] ; CHECK-NEXT: vzip.8 q9, q8 @@ -102,7 +102,7 @@ define <32 x i8> @vzipQi8_QQres(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <8 x i16> @vzipQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { ; CHECK-LABEL: vzipQi16: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r1] ; CHECK-NEXT: vld1.64 {d18, d19}, [r0] ; CHECK-NEXT: vzip.16 q9, q8 @@ -120,7 +120,7 @@ define <8 x i16> @vzipQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <16 x i16> @vzipQi16_QQres(<8 x i16>* %A, <8 x i16>* %B) nounwind { ; CHECK-LABEL: vzipQi16_QQres: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r2] ; CHECK-NEXT: vld1.64 {d18, d19}, [r1] ; CHECK-NEXT: vzip.16 q9, q8 @@ -135,7 +135,7 @@ define <16 x i16> @vzipQi16_QQres(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i32> @vzipQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { ; CHECK-LABEL: vzipQi32: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r1] ; CHECK-NEXT: vld1.64 {d18, d19}, [r0] ; CHECK-NEXT: vzip.32 q9, q8 @@ -153,7 +153,7 @@ define <4 x i32> @vzipQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <8 x i32> @vzipQi32_QQres(<4 x i32>* %A, <4 x i32>* %B) nounwind { ; CHECK-LABEL: vzipQi32_QQres: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r2] ; CHECK-NEXT: vld1.64 {d18, d19}, [r1] ; CHECK-NEXT: vzip.32 q9, q8 @@ -168,7 +168,7 @@ define <8 x i32> @vzipQi32_QQres(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <4 x float> @vzipQf(<4 x float>* %A, <4 x float>* %B) nounwind { ; CHECK-LABEL: vzipQf: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r1] ; CHECK-NEXT: vld1.64 {d18, d19}, [r0] ; CHECK-NEXT: vzip.32 q9, q8 @@ -186,7 +186,7 @@ define <4 x float> @vzipQf(<4 x float>* %A, <4 x float>* %B) nounwind { define <8 x float> @vzipQf_QQres(<4 x float>* %A, <4 x float>* %B) nounwind { ; CHECK-LABEL: vzipQf_QQres: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r2] ; CHECK-NEXT: vld1.64 {d18, d19}, [r1] ; CHECK-NEXT: vzip.32 q9, q8 @@ -203,7 +203,7 @@ define <8 x float> @vzipQf_QQres(<4 x float>* %A, <4 x float>* %B) nounwind { define <8 x i8> @vzipi8_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind { ; CHECK-LABEL: vzipi8_undef: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vldr d16, [r1] ; CHECK-NEXT: vldr d17, [r0] ; CHECK-NEXT: vzip.8 d17, d16 @@ -220,7 +220,7 @@ define <8 x i8> @vzipi8_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <16 x i8> @vzipi8_undef_Qres(<8 x i8>* %A, <8 x i8>* %B) nounwind { ; CHECK-LABEL: vzipi8_undef_Qres: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vldr d17, [r1] ; CHECK-NEXT: vldr d16, [r0] ; CHECK-NEXT: vzip.8 d16, d17 @@ -235,7 +235,7 @@ define <16 x i8> @vzipi8_undef_Qres(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <16 x i8> @vzipQi8_undef(<16 x i8>* %A, <16 x i8>* %B) nounwind { ; CHECK-LABEL: vzipQi8_undef: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r1] ; CHECK-NEXT: vld1.64 {d18, d19}, [r0] ; CHECK-NEXT: vzip.8 q9, q8 @@ -253,7 +253,7 @@ define <16 x i8> @vzipQi8_undef(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <32 x i8> @vzipQi8_undef_QQres(<16 x i8>* %A, <16 x i8>* %B) nounwind { ; CHECK-LABEL: vzipQi8_undef_QQres: -; CHECK: @ BB#0: +; CHECK: @ %bb.0: ; CHECK-NEXT: vld1.64 {d16, d17}, [r2] ; CHECK-NEXT: vld1.64 {d18, d19}, [r1] ; CHECK-NEXT: vzip.8 q9, q8 @@ -268,7 +268,7 @@ define <32 x i8> @vzipQi8_undef_QQres(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <8 x i16> @vzip_lower_shufflemask_undef(<4 x i16>* %A, <4 x i16>* %B) { ; CHECK-LABEL: vzip_lower_shufflemask_undef: -; CHECK: @ BB#0: @ %entry +; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vldr d17, [r1] ; CHECK-NEXT: vldr d16, [r0] ; CHECK-NEXT: vzip.16 d16, d17 @@ -287,7 +287,7 @@ entry: ; as a vtrn. define <8 x i16> @vzip_lower_shufflemask_undef_rev(<4 x i16>* %A, <4 x i16>* %B) { ; CHECK-LABEL: vzip_lower_shufflemask_undef_rev: -; CHECK: @ BB#0: @ %entry +; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vldr d16, [r1] ; CHECK-NEXT: vldr d19, [r0] ; CHECK-NEXT: vtrn.16 d19, d16 @@ -303,7 +303,7 @@ entry: define <4 x i32> @vzip_lower_shufflemask_zeroed(<2 x i32>* %A) { ; CHECK-LABEL: vzip_lower_shufflemask_zeroed: -; CHECK: @ BB#0: @ %entry +; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vldr d16, [r0] ; CHECK-NEXT: vdup.32 q9, d16[0] ; CHECK-NEXT: vzip.32 q8, q9 @@ -318,7 +318,7 @@ entry: define <4 x i32> @vzip_lower_shufflemask_vuzp(<2 x i32>* %A) { ; CHECK-LABEL: vzip_lower_shufflemask_vuzp: -; CHECK: @ BB#0: @ %entry +; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vldr d16, [r0] ; CHECK-NEXT: vdup.32 q9, d16[0] ; CHECK-NEXT: vzip.32 q8, q9 @@ -333,7 +333,7 @@ entry: define void @vzip_undef_rev_shufflemask_vtrn(<2 x i32>* %A, <4 x i32>* %B) { ; CHECK-LABEL: vzip_undef_rev_shufflemask_vtrn: -; CHECK: @ BB#0: @ %entry +; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vldr d16, [r0] ; CHECK-NEXT: vorr q9, q8, q8 ; CHECK-NEXT: vzip.32 q8, q9 @@ -349,7 +349,7 @@ entry: define void @vzip_vext_factor(<8 x i16>* %A, <4 x i16>* %B) { ; CHECK-LABEL: vzip_vext_factor: -; CHECK: @ BB#0: @ %entry +; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vld1.64 {d16, d17}, [r0] ; CHECK-NEXT: vext.16 d18, d16, d17, #1 ; CHECK-NEXT: vext.16 d16, d18, d17, #2 @@ -365,7 +365,7 @@ entry: define <8 x i8> @vdup_zip(i8* nocapture readonly %x, i8* nocapture readonly %y) { ; CHECK-LABEL: vdup_zip: -; CHECK: @ BB#0: @ %entry +; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vld1.8 {d16[]}, [r1] ; CHECK-NEXT: vld1.8 {d17[]}, [r0] ; CHECK-NEXT: vzip.8 d17, d16 diff --git a/test/CodeGen/AVR/atomics/fence.ll b/test/CodeGen/AVR/atomics/fence.ll index 6ea49bc7e3fcf..b4cd215f3a26a 100644 --- a/test/CodeGen/AVR/atomics/fence.ll +++ b/test/CodeGen/AVR/atomics/fence.ll @@ -4,7 +4,7 @@ ; AVR is always singlethreaded so fences do nothing. ; CHECK_LABEL: atomic_fence8 -; CHECK: ; BB#0: +; CHECK: ; %bb.0: ; CHECK-NEXT: ret define void @atomic_fence8() { fence acquire diff --git a/test/CodeGen/AVR/select-must-add-unconditional-jump.ll b/test/CodeGen/AVR/select-must-add-unconditional-jump.ll index e6344dfc69279..5c247f6e8e6c1 100644 --- a/test/CodeGen/AVR/select-must-add-unconditional-jump.ll +++ b/test/CodeGen/AVR/select-must-add-unconditional-jump.ll @@ -9,18 +9,18 @@ ; ; This issue manifests in a CFG that looks something like this: ; -; BB#2: derived from LLVM BB %finish -; Predecessors according to CFG: BB#0 BB#1 -; %vreg0 = PHI %vreg3, , %vreg5, -; %vreg7 = LDIRdK 2 -; %vreg8 = LDIRdK 1 -; CPRdRr %vreg2, %vreg0, %SREG -; BREQk , %SREG -; Successors according to CFG: BB#5(?%) BB#6(?%) +; %bb.2: derived from LLVM BB %finish +; Predecessors according to CFG: %bb.0 %bb.1 +; %0 = PHI %3, <%bb.0>, %5, <%bb.1> +; %7 = LDIRdK 2 +; %8 = LDIRdK 1 +; CPRdRr %2, %0, %SREG +; BREQk <%bb.6>, %SREG +; Successors according to CFG: %bb.5(?%) %bb.6(?%) ; -; The code assumes it the fallthrough block after this is BB#5, but -; it's actually BB#3! To be proper, there should be an unconditional -; jump tying this block to BB#5. +; The code assumes it the fallthrough block after this is %bb.5, but +; it's actually %bb.3! To be proper, there should be an unconditional +; jump tying this block to %bb.5. define i8 @select_must_add_unconditional_jump(i8 %arg0, i8 %arg1) unnamed_addr { entry-block: @@ -49,10 +49,10 @@ dead: ; basic block containing `select` needs to contain explicit jumps to ; both successors. -; CHECK: BB#2: derived from LLVM BB %finish -; CHECK: BREQk <[[BRANCHED:BB#[0-9]+]]> -; CHECK: RJMPk <[[DIRECT:BB#[0-9]+]]> +; CHECK: %bb.2: derived from LLVM BB %finish +; CHECK: BREQk <[[BRANCHED:%bb.[0-9]+]]> +; CHECK: RJMPk <[[DIRECT:%bb.[0-9]+]]> ; CHECK: Successors according to CFG ; CHECK-SAME-DAG: {{.*}}[[BRANCHED]] ; CHECK-SAME-DAG: {{.*}}[[DIRECT]] -; CHECK: BB#3: derived from LLVM BB +; CHECK: %bb.3: derived from LLVM BB diff --git a/test/CodeGen/Generic/MachineBranchProb.ll b/test/CodeGen/Generic/MachineBranchProb.ll index 75e9a191e3d10..dc4a52ab7111d 100644 --- a/test/CodeGen/Generic/MachineBranchProb.ll +++ b/test/CodeGen/Generic/MachineBranchProb.ll @@ -21,14 +21,14 @@ entry: i64 5, label %sw.bb1 i64 15, label %sw.bb ], !prof !0 -; CHECK: BB#0: derived from LLVM BB %entry -; CHECK: Successors according to CFG: BB#1({{[0-9a-fx/= ]+}}92.17%) BB#4({{[0-9a-fx/= ]+}}7.83%) -; CHECK: BB#4: derived from LLVM BB %entry -; CHECK: Successors according to CFG: BB#2({{[0-9a-fx/= ]+}}75.29%) BB#5({{[0-9a-fx/= ]+}}24.71%) -; CHECK: BB#5: derived from LLVM BB %entry -; CHECK: Successors according to CFG: BB#1({{[0-9a-fx/= ]+}}47.62%) BB#6({{[0-9a-fx/= ]+}}52.38%) -; CHECK: BB#6: derived from LLVM BB %entry -; CHECK: Successors according to CFG: BB#1({{[0-9a-fx/= ]+}}36.36%) BB#3({{[0-9a-fx/= ]+}}63.64%) +; CHECK: %bb.0: derived from LLVM BB %entry +; CHECK: Successors according to CFG: %bb.1({{[0-9a-fx/= ]+}}92.17%) %bb.4({{[0-9a-fx/= ]+}}7.83%) +; CHECK: %bb.4: derived from LLVM BB %entry +; CHECK: Successors according to CFG: %bb.2({{[0-9a-fx/= ]+}}75.29%) %bb.5({{[0-9a-fx/= ]+}}24.71%) +; CHECK: %bb.5: derived from LLVM BB %entry +; CHECK: Successors according to CFG: %bb.1({{[0-9a-fx/= ]+}}47.62%) %bb.6({{[0-9a-fx/= ]+}}52.38%) +; CHECK: %bb.6: derived from LLVM BB %entry +; CHECK: Successors according to CFG: %bb.1({{[0-9a-fx/= ]+}}36.36%) %bb.3({{[0-9a-fx/= ]+}}63.64%) sw.bb: ; this call will prevent simplifyCFG from optimizing the block away in ARM/AArch64. @@ -70,9 +70,9 @@ return: ret void ; right with weight 20. ; ; CHECK-LABEL: Machine code for function left_leaning_weight_balanced_tree: -; CHECK: BB#0: derived from LLVM BB %entry +; CHECK: %bb.0: derived from LLVM BB %entry ; CHECK-NOT: Successors -; CHECK: Successors according to CFG: BB#8({{[0-9a-fx/= ]+}}39.71%) BB#9({{[0-9a-fx/= ]+}}60.29%) +; CHECK: Successors according to CFG: %bb.8({{[0-9a-fx/= ]+}}39.71%) %bb.9({{[0-9a-fx/= ]+}}60.29%) } !1 = !{!"branch_weights", diff --git a/test/CodeGen/Generic/bswap.ll b/test/CodeGen/Generic/bswap.ll new file mode 100644 index 0000000000000..bd4f02be2b178 --- /dev/null +++ b/test/CodeGen/Generic/bswap.ll @@ -0,0 +1,50 @@ +; tests lowering of vector bswap +; RUN: lli -force-interpreter %s | FileCheck %s + +; CHECK: 0x100 +; CHECK: 0x10000 +; CHECK: 0x1001000000000000 +; CHECK: 0x100 +; CHECK: 0x10000 +; CHECK: 0x1001000000000000 + + + +target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" + +declare i16 @llvm.bswap.i16(i16); +declare i32 @llvm.bswap.i32(i32); +declare i64 @llvm.bswap.i64(i64); +declare <4 x i16> @llvm.bswap.v4i16(<4 x i16>); +declare <4 x i32> @llvm.bswap.v4i32(<4 x i32>); +declare <4 x i64> @llvm.bswap.v4i64(<4 x i64>); +declare i32 @printf(i8* nocapture readonly, ...); + +@.str = private unnamed_addr constant [5 x i8] c"%#x\0A\00", align 1 +@.strs = private unnamed_addr constant [6 x i8] c"%#hx\0A\00", align 1 +@.strl = private unnamed_addr constant [6 x i8] c"%#lx\0A\00", align 1 + +define i32 @main() local_unnamed_addr { + %ra = tail call i16 @llvm.bswap.i16(i16 1) + %pa = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.strs, i64 0, i64 0), i16 %ra) + + %rb = tail call i32 @llvm.bswap.i32(i32 256) + %pb = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([5 x i8], [5 x i8]* @.str, i64 0, i64 0), i32 %rb) + + %rc = tail call i64 @llvm.bswap.i64(i64 272) + %pc = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.strl, i64 0, i64 0), i64 %rc) + + %r0 = tail call <4 x i16> @llvm.bswap.v4i16(<4 x i16> ) + %e0 = extractelement <4 x i16> %r0, i8 0 + %p0 = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.strs, i64 0, i64 0), i16 %e0) + + %r1 = tail call <4 x i32> @llvm.bswap.v4i32(<4 x i32> ) + %e1 = extractelement <4 x i32> %r1, i8 1 + %p1 = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([5 x i8], [5 x i8]* @.str, i64 0, i64 0), i32 %e1) + + %r2 = tail call <4 x i64> @llvm.bswap.v4i64(<4 x i64> ) + %e2 = extractelement <4 x i64> %r2, i8 2 + %p2 = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.strl, i64 0, i64 0), i64 %e2) + + ret i32 0 +} diff --git a/test/CodeGen/Hexagon/branch-folder-hoist-kills.mir b/test/CodeGen/Hexagon/branch-folder-hoist-kills.mir index 47da85b23089e..c685a0c274037 100644 --- a/test/CodeGen/Hexagon/branch-folder-hoist-kills.mir +++ b/test/CodeGen/Hexagon/branch-folder-hoist-kills.mir @@ -11,7 +11,7 @@ # then created code, where the first predicated instruction has incorrect # implicit use of r0: # -# BB#0: +# %bb.0: # Live Ins: %R0 # %R1 = A2_sxth %R0 ; hoisted, kills r0 # A2_nop %P0 diff --git a/test/CodeGen/Hexagon/circ_ldd_bug.ll b/test/CodeGen/Hexagon/circ_ldd_bug.ll index d15b5c964eb7e..40584cae7b0da 100644 --- a/test/CodeGen/Hexagon/circ_ldd_bug.ll +++ b/test/CodeGen/Hexagon/circ_ldd_bug.ll @@ -7,10 +7,10 @@ target triple = "hexagon" ; UNREACHABLE executed at llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp:615! ; This happened because after unrolling a loop with a ldd_circ instruction we ; would have several TFCR and ldd_circ instruction sequences. -; %vreg0 (CRRegs) = TFCR %vreg0 (IntRegs) -; = ldd_circ( , , vreg0) -; %vreg1 (CRRegs) = TFCR %vreg1 (IntRegs) -; = ldd_circ( , , vreg0) +; %0 (CRRegs) = TFCR %0 (IntRegs) +; = ldd_circ( , , %0) +; %1 (CRRegs) = TFCR %1 (IntRegs) +; = ldd_circ( , , %0) ; The scheduler would move the CRRegs to the top of the loop. The allocator ; would try to spill the CRRegs after running out of them. We don't have code to ; spill CRRegs and the above assertion would be triggered. diff --git a/test/CodeGen/Hexagon/duplex.ll b/test/CodeGen/Hexagon/duplex.ll index 80fe61ceccca3..9f25726cf597d 100644 --- a/test/CodeGen/Hexagon/duplex.ll +++ b/test/CodeGen/Hexagon/duplex.ll @@ -4,4 +4,4 @@ define i32 @foo() { ret i32 0 -} \ No newline at end of file +} diff --git a/test/CodeGen/Hexagon/early-if-debug.mir b/test/CodeGen/Hexagon/early-if-debug.mir index 7c8fb0aee10de..2f4a2db0a6e85 100644 --- a/test/CodeGen/Hexagon/early-if-debug.mir +++ b/test/CodeGen/Hexagon/early-if-debug.mir @@ -6,11 +6,11 @@ # CHECK: %0:intregs = COPY %r0 # CHECK: %1:predregs = C2_cmpeqi %0, 0 # CHECK: %2:intregs = A2_tfrsi 123 -# CHECK: DBG_VALUE debug-use %0, debug-use _ -# CHECK: DBG_VALUE debug-use %0, debug-use _ -# CHECK: DBG_VALUE debug-use %0, debug-use _ -# CHECK: DBG_VALUE debug-use %0, debug-use _ -# CHECK: DBG_VALUE debug-use %0, debug-use _ +# CHECK: DBG_VALUE debug-use %0, debug-use %noreg +# CHECK: DBG_VALUE debug-use %0, debug-use %noreg +# CHECK: DBG_VALUE debug-use %0, debug-use %noreg +# CHECK: DBG_VALUE debug-use %0, debug-use %noreg +# CHECK: DBG_VALUE debug-use %0, debug-use %noreg # CHECK: %3:intregs = A2_tfrsi 321 # CHECK: %5:intregs = C2_mux %1, %2, %3 @@ -40,11 +40,11 @@ body: | J2_jump %bb.1, implicit-def dead %pc bb.1: - DBG_VALUE debug-use %0, debug-use _, !1, !1 - DBG_VALUE debug-use %0, debug-use _, !1, !1 - DBG_VALUE debug-use %0, debug-use _, !1, !1 - DBG_VALUE debug-use %0, debug-use _, !1, !1 - DBG_VALUE debug-use %0, debug-use _, !1, !1 + DBG_VALUE debug-use %0, debug-use %noreg, !1, !1 + DBG_VALUE debug-use %0, debug-use %noreg, !1, !1 + DBG_VALUE debug-use %0, debug-use %noreg, !1, !1 + DBG_VALUE debug-use %0, debug-use %noreg, !1, !1 + DBG_VALUE debug-use %0, debug-use %noreg, !1, !1 %3 = A2_tfrsi 321 bb.2: diff --git a/test/CodeGen/Hexagon/expand-condsets-rm-reg.mir b/test/CodeGen/Hexagon/expand-condsets-rm-reg.mir index e4c54c4b9888d..550e5c55550e0 100644 --- a/test/CodeGen/Hexagon/expand-condsets-rm-reg.mir +++ b/test/CodeGen/Hexagon/expand-condsets-rm-reg.mir @@ -3,12 +3,12 @@ # Check that coalesced registers are removed from live intervals. # -# Check that vreg3 is coalesced into vreg4, and that after coalescing +# Check that %3 is coalesced into %4, and that after coalescing # it is no longer in live intervals. # CHECK-LABEL: After expand-condsets # CHECK: INTERVALS -# CHECK-NOT: vreg3 +# CHECK-NOT: %3 # CHECK: MACHINEINSTRS diff --git a/test/CodeGen/Hexagon/hwloop-redef-imm.mir b/test/CodeGen/Hexagon/hwloop-redef-imm.mir index 014908e20a7fb..7b6044c9a502a 100644 --- a/test/CodeGen/Hexagon/hwloop-redef-imm.mir +++ b/test/CodeGen/Hexagon/hwloop-redef-imm.mir @@ -8,10 +8,10 @@ # loop setup in the preheader). # CHECK: [[R0:%[0-9]+]]:intregs = A2_tfrsi 1920 -# CHECK: J2_loop0r %bb.1.b1, [[R0]] +# CHECK: J2_loop0r %bb.1, [[R0]] # # CHECK: bb.1.b1 (address-taken): -# CHECK: ENDLOOP0 %bb.1.b1 +# CHECK: ENDLOOP0 %bb.1 --- | diff --git a/test/CodeGen/Hexagon/ifcvt-edge-weight.ll b/test/CodeGen/Hexagon/ifcvt-edge-weight.ll index 341567e1d02fd..250a81938bdbc 100644 --- a/test/CodeGen/Hexagon/ifcvt-edge-weight.ll +++ b/test/CodeGen/Hexagon/ifcvt-edge-weight.ll @@ -1,8 +1,8 @@ ; RUN: llc -march=hexagon -mcpu=hexagonv5 -hexagon-eif=0 -print-machineinstrs=if-converter %s -o /dev/null 2>&1 | FileCheck %s ; Check that the edge weights are updated correctly after if-conversion. -; CHECK: BB#3: -; CHECK: Successors according to CFG: BB#2({{[0-9a-fx/= ]+}}10.00%) BB#1({{[0-9a-fx/= ]+}}90.00%) +; CHECK: %bb.3: +; CHECK: Successors according to CFG: %bb.2({{[0-9a-fx/= ]+}}10.00%) %bb.1({{[0-9a-fx/= ]+}}90.00%) @a = external global i32 @d = external global i32 diff --git a/test/CodeGen/Hexagon/newvaluejump-solo.mir b/test/CodeGen/Hexagon/newvaluejump-solo.mir new file mode 100644 index 0000000000000..0676cfb943c78 --- /dev/null +++ b/test/CodeGen/Hexagon/newvaluejump-solo.mir @@ -0,0 +1,19 @@ +# RUN: llc -march=hexagon -run-pass hexagon-nvj %s -o - | FileCheck %s + +# Check that there is no new-value jump: +# CHECK-LABEL: name: fred +# CHECK-NOT: jumpnv +--- +name: fred +tracksRegLiveness: true + +body: | + bb.0: + successors: %bb.1 + %r0 = A2_tfrsi 0 + %r0 = V6_extractw killed undef %v0, %r0 + %p0 = C2_cmpeqi killed %r0, 1 + J2_jumpf killed %p0, %bb.1, implicit-def %pc + + bb.1: +... diff --git a/test/CodeGen/Hexagon/post-inc-aa-metadata.ll b/test/CodeGen/Hexagon/post-inc-aa-metadata.ll index 673a9b41ff22a..688a71352cd0a 100644 --- a/test/CodeGen/Hexagon/post-inc-aa-metadata.ll +++ b/test/CodeGen/Hexagon/post-inc-aa-metadata.ll @@ -3,7 +3,7 @@ ; Check that the generated post-increment load has TBAA information. ; CHECK-LABEL: Machine code for function fred: -; CHECK: = V6_vL32b_pi %vreg{{[0-9]+}}, 64; mem:LD64[{{.*}}](tbaa= +; CHECK: = V6_vL32b_pi %{{[0-9]+}}, 64; mem:LD64[{{.*}}](tbaa= target triple = "hexagon" diff --git a/test/CodeGen/Lanai/lanai-misched-trivial-disjoint.ll b/test/CodeGen/Lanai/lanai-misched-trivial-disjoint.ll index 242ee53f19f2e..6279a2ea6a75d 100644 --- a/test/CodeGen/Lanai/lanai-misched-trivial-disjoint.ll +++ b/test/CodeGen/Lanai/lanai-misched-trivial-disjoint.ll @@ -36,7 +36,7 @@ entry: ; CHECK-LABEL: SU({{.*}}): SW_RI{{.*}}, 4, ; CHECK: # preds left : 2 ; CHECK: # succs left : 0 -; CHECK-LABEL: SU({{.*}}): %vreg{{.*}} = LDW_RI{{.*}}, 12, +; CHECK-LABEL: SU({{.*}}): %{{.*}} = LDW_RI{{.*}}, 12, ; CHECK: # preds left : 1 ; CHECK: # succs left : 4 ; CHECK-LABEL: SU({{.*}}): STH_RI{{.*}}, 10, diff --git a/test/CodeGen/MIR/AArch64/spill-fold.mir b/test/CodeGen/MIR/AArch64/spill-fold.mir index f812bc710aaf2..8e80828b1cef8 100644 --- a/test/CodeGen/MIR/AArch64/spill-fold.mir +++ b/test/CodeGen/MIR/AArch64/spill-fold.mir @@ -22,7 +22,7 @@ body: | ... --- # CHECK-LABEL: name: test_subreg_spill_fold2 -# Similar to test_subreg_spill_fold, but with a vreg0 register class not containing %WZR. +# Similar to test_subreg_spill_fold, but with a %0 register class not containing %WZR. name: test_subreg_spill_fold2 registers: - { id: 0, class: gpr64sp } diff --git a/test/CodeGen/MIR/ARM/bundled-instructions.mir b/test/CodeGen/MIR/ARM/bundled-instructions.mir index 56e21e3627071..462d45c90b5f7 100644 --- a/test/CodeGen/MIR/ARM/bundled-instructions.mir +++ b/test/CodeGen/MIR/ARM/bundled-instructions.mir @@ -28,14 +28,14 @@ body: | bb.0.entry: liveins: %r0 ; CHECK-LABEL: name: test1 - ; CHECK: %r1 = t2MOVi 0, 14, _, _ - ; CHECK-NEXT: t2CMNri killed %r0, 78, 14, _, implicit-def %cpsr + ; CHECK: %r1 = t2MOVi 0, 14, %noreg, %noreg + ; CHECK-NEXT: t2CMNri killed %r0, 78, 14, %noreg, implicit-def %cpsr ; CHECK-NEXT: BUNDLE implicit-def dead %itstate, implicit-def %r1, implicit killed %cpsr { ; CHECK-NEXT: t2IT 12, 8, implicit-def %itstate - ; CHECK-NEXT: %r1 = t2MOVi 1, 12, killed %cpsr, _, implicit internal killed %itstate + ; CHECK-NEXT: %r1 = t2MOVi 1, 12, killed %cpsr, %noreg, implicit internal killed %itstate ; CHECK-NEXT: } - ; CHECK-NEXT: %r0 = tMOVr killed %r1, 14, _ - ; CHECK-NEXT: tBX_RET 14, _, implicit killed %r0 + ; CHECK-NEXT: %r0 = tMOVr killed %r1, 14, %noreg + ; CHECK-NEXT: tBX_RET 14, %noreg, implicit killed %r0 %r1 = t2MOVi 0, 14, _, _ t2CMNri killed %r0, 78, 14, _, implicit-def %cpsr BUNDLE implicit-def dead %itstate, implicit-def %r1, implicit killed %cpsr { @@ -58,14 +58,14 @@ body: | ; '{' or '}'. ; CHECK-LABEL: name: test2 - ; CHECK: %r1 = t2MOVi 0, 14, _, _ - ; CHECK-NEXT: t2CMNri killed %r0, 78, 14, _, implicit-def %cpsr + ; CHECK: %r1 = t2MOVi 0, 14, %noreg, %noreg + ; CHECK-NEXT: t2CMNri killed %r0, 78, 14, %noreg, implicit-def %cpsr ; CHECK-NEXT: BUNDLE implicit-def dead %itstate, implicit-def %r1, implicit killed %cpsr { ; CHECK-NEXT: t2IT 12, 8, implicit-def %itstate - ; CHECK-NEXT: %r1 = t2MOVi 1, 12, killed %cpsr, _, implicit internal killed %itstate + ; CHECK-NEXT: %r1 = t2MOVi 1, 12, killed %cpsr, %noreg, implicit internal killed %itstate ; CHECK-NEXT: } - ; CHECK-NEXT: %r0 = tMOVr killed %r1, 14, _ - ; CHECK-NEXT: tBX_RET 14, _, implicit killed %r0 + ; CHECK-NEXT: %r0 = tMOVr killed %r1, 14, %noreg + ; CHECK-NEXT: tBX_RET 14, %noreg, implicit killed %r0 %r1 = t2MOVi 0, 14, _, _ t2CMNri killed %r0, 78, 14, _, implicit-def %cpsr BUNDLE implicit-def dead %itstate, implicit-def %r1, implicit killed %cpsr { t2IT 12, 8, implicit-def %itstate diff --git a/test/CodeGen/MIR/ARM/ifcvt_diamond_unanalyzable.mir b/test/CodeGen/MIR/ARM/ifcvt_diamond_unanalyzable.mir index a6e5521fd2cbc..6b7ad20aa12fc 100644 --- a/test/CodeGen/MIR/ARM/ifcvt_diamond_unanalyzable.mir +++ b/test/CodeGen/MIR/ARM/ifcvt_diamond_unanalyzable.mir @@ -26,5 +26,5 @@ body: | # CHECK: bb.0: # CHECK: %sp = tADDspi %sp, 2, 1, %cpsr # CHECK: %sp = tADDspi %sp, 1, 0, %cpsr, implicit %sp -# CHECK: %sp = tADDspi %sp, 3, 14, _ -# CHECK: BX_RET 14, _ +# CHECK: %sp = tADDspi %sp, 3, 14, %noreg +# CHECK: BX_RET 14, %noreg diff --git a/test/CodeGen/MIR/ARM/ifcvt_forked_diamond_unanalyzable.mir b/test/CodeGen/MIR/ARM/ifcvt_forked_diamond_unanalyzable.mir index 652c333c523c3..f5f09a8ec4a9c 100644 --- a/test/CodeGen/MIR/ARM/ifcvt_forked_diamond_unanalyzable.mir +++ b/test/CodeGen/MIR/ARM/ifcvt_forked_diamond_unanalyzable.mir @@ -40,9 +40,9 @@ body: | # CHECK: Bcc %bb.2, 1, %cpsr # CHECK: bb.1: -# CHECK: %sp = tADDspi %sp, 4, 14, _ -# CHECK: BX_RET 14, _ +# CHECK: %sp = tADDspi %sp, 4, 14, %noreg +# CHECK: BX_RET 14, %noreg # CHECK: bb.2: -# CHECK: %sp = tADDspi %sp, 3, 14, _ -# CHECK: BX_RET 14, _ +# CHECK: %sp = tADDspi %sp, 3, 14, %noreg +# CHECK: BX_RET 14, %noreg diff --git a/test/CodeGen/MIR/ARM/ifcvt_simple_unanalyzable.mir b/test/CodeGen/MIR/ARM/ifcvt_simple_unanalyzable.mir index d0c6ffdb3fa0f..8d1c71ac98fb1 100644 --- a/test/CodeGen/MIR/ARM/ifcvt_simple_unanalyzable.mir +++ b/test/CodeGen/MIR/ARM/ifcvt_simple_unanalyzable.mir @@ -21,5 +21,5 @@ body: | # CHECK: bb.0: # CHECK: %sp = tADDspi %sp, 2, 0, %cpsr # CHECK: BX_RET 0, %cpsr -# CHECK: BX_RET 14, _ +# CHECK: BX_RET 14, %noreg diff --git a/test/CodeGen/MIR/ARM/ifcvt_triangleWoCvtToNextEdge.mir b/test/CodeGen/MIR/ARM/ifcvt_triangleWoCvtToNextEdge.mir index 981752654fc30..92ecbc8dbbe84 100644 --- a/test/CodeGen/MIR/ARM/ifcvt_triangleWoCvtToNextEdge.mir +++ b/test/CodeGen/MIR/ARM/ifcvt_triangleWoCvtToNextEdge.mir @@ -47,6 +47,6 @@ body: | # CHECK: bb.2: # CHECK-NOT: successors: %bb # CHECK: tBL 1, %cpsr, @__stack_chk_fail -# CHECK: %sp = tADDspi %sp, 2, 14, _ -# CHECK: %sp = tADDspi %sp, 2, 14, _ +# CHECK: %sp = tADDspi %sp, 2, 14, %noreg +# CHECK: %sp = tADDspi %sp, 2, 14, %noreg # CHECK: tTAILJMPdND @bar, 14, %cpsr diff --git a/test/CodeGen/MIR/X86/block-address-operands.mir b/test/CodeGen/MIR/X86/block-address-operands.mir index 2207f9360965c..85ce65275ced8 100644 --- a/test/CodeGen/MIR/X86/block-address-operands.mir +++ b/test/CodeGen/MIR/X86/block-address-operands.mir @@ -57,7 +57,7 @@ name: test body: | bb.0.entry: successors: %bb.1.block - ; CHECK: %rax = LEA64r %rip, 1, _, blockaddress(@test, %ir-block.block), _ + ; CHECK: %rax = LEA64r %rip, 1, %noreg, blockaddress(@test, %ir-block.block), %noreg %rax = LEA64r %rip, 1, _, blockaddress(@test, %ir-block.block), _ MOV64mr %rip, 1, _, @addr, _, killed %rax JMP64m %rip, 1, _, @addr, _ @@ -71,7 +71,7 @@ tracksRegLiveness: true body: | bb.0.entry: successors: %bb.1 - ; CHECK: %rax = LEA64r %rip, 1, _, blockaddress(@test2, %ir-block."quoted block"), _ + ; CHECK: %rax = LEA64r %rip, 1, %noreg, blockaddress(@test2, %ir-block."quoted block"), %noreg %rax = LEA64r %rip, 1, _, blockaddress(@test2, %ir-block."quoted block"), _ MOV64mr %rip, 1, _, @addr, _, killed %rax JMP64m %rip, 1, _, @addr, _ @@ -86,7 +86,7 @@ body: | bb.0.entry: liveins: %rdi ; CHECK-LABEL: name: slot_in_other_function - ; CHECK: %rax = LEA64r %rip, 1, _, blockaddress(@test3, %ir-block.0), _ + ; CHECK: %rax = LEA64r %rip, 1, %noreg, blockaddress(@test3, %ir-block.0), %noreg %rax = LEA64r %rip, 1, _, blockaddress(@test3, %ir-block.0), _ MOV64mr killed %rdi, 1, _, 0, _, killed %rax RETQ @@ -98,7 +98,7 @@ body: | bb.0.entry: successors: %bb.1 ; CHECK-LABEL: name: test3 - ; CHECK: %rax = LEA64r %rip, 1, _, blockaddress(@test3, %ir-block.0), _ + ; CHECK: %rax = LEA64r %rip, 1, %noreg, blockaddress(@test3, %ir-block.0), %noreg %rax = LEA64r %rip, 1, _, blockaddress(@test3, %ir-block.0), _ MOV64mr %rip, 1, _, @addr, _, killed %rax JMP64m %rip, 1, _, @addr, _ @@ -111,7 +111,7 @@ name: test4 body: | bb.0.entry: successors: %bb.1.block - ; CHECK: %rax = LEA64r %rip, 1, _, blockaddress(@test, %ir-block.block) + 2, _ + ; CHECK: %rax = LEA64r %rip, 1, %noreg, blockaddress(@test, %ir-block.block) + 2, %noreg %rax = LEA64r %rip, 1, _, blockaddress(@test, %ir-block.block) + 2, _ MOV64mr %rip, 1, _, @addr, _, killed %rax JMP64m %rip, 1, _, @addr, _ diff --git a/test/CodeGen/MIR/X86/constant-pool.mir b/test/CodeGen/MIR/X86/constant-pool.mir index 60e12d3ddcd97..431af44b0c51c 100644 --- a/test/CodeGen/MIR/X86/constant-pool.mir +++ b/test/CodeGen/MIR/X86/constant-pool.mir @@ -61,8 +61,8 @@ constants: alignment: 4 body: | bb.0.entry: - ; CHECK: %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _ - ; CHECK-NEXT: %xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.1, _ + ; CHECK: %xmm0 = ADDSDrm killed %xmm0, %rip, 1, %noreg, %const.0, %noreg + ; CHECK-NEXT: %xmm1 = ADDSSrm killed %xmm1, %rip, 1, %noreg, %const.1, %noreg %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _ %xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.1, _ %xmm1 = CVTSS2SDrr killed %xmm1 @@ -117,8 +117,8 @@ constants: alignment: 1 body: | bb.0.entry: - ; CHECK: %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _ - ; CHECK-NEXT: %xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.1, _ + ; CHECK: %xmm0 = ADDSDrm killed %xmm0, %rip, 1, %noreg, %const.0, %noreg + ; CHECK-NEXT: %xmm1 = ADDSSrm killed %xmm1, %rip, 1, %noreg, %const.1, %noreg %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _ %xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.1, _ %xmm1 = CVTSS2SDrr killed %xmm1 @@ -135,8 +135,8 @@ constants: value: 'float 6.250000e+00' body: | bb.0.entry: - ; CHECK: %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.1 - 12, _ - ; CHECK-NEXT: %xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.0 + 8, _ + ; CHECK: %xmm0 = ADDSDrm killed %xmm0, %rip, 1, %noreg, %const.1 - 12, %noreg + ; CHECK-NEXT: %xmm1 = ADDSSrm killed %xmm1, %rip, 1, %noreg, %const.0 + 8, %noreg %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.1 - 12, _ %xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.0 + 8, _ %xmm1 = CVTSS2SDrr killed %xmm1 diff --git a/test/CodeGen/MIR/X86/fixed-stack-memory-operands.mir b/test/CodeGen/MIR/X86/fixed-stack-memory-operands.mir index 8ae76753984d9..92ceb1e78e05c 100644 --- a/test/CodeGen/MIR/X86/fixed-stack-memory-operands.mir +++ b/test/CodeGen/MIR/X86/fixed-stack-memory-operands.mir @@ -31,7 +31,7 @@ body: | frame-setup PUSH32r undef %eax, implicit-def %esp, implicit %esp CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: name: test - ; CHECK: %eax = MOV32rm %esp, 1, _, 8, _ :: (load 4 from %fixed-stack.0, align 16) + ; CHECK: %eax = MOV32rm %esp, 1, %noreg, 8, %noreg :: (load 4 from %fixed-stack.0, align 16) %eax = MOV32rm %esp, 1, _, 8, _ :: (load 4 from %fixed-stack.0, align 16) MOV32mr %esp, 1, _, 0, _, %eax :: (store 4 into %ir.b) %edx = POP32r implicit-def %esp, implicit %esp diff --git a/test/CodeGen/MIR/X86/frame-info-save-restore-points.mir b/test/CodeGen/MIR/X86/frame-info-save-restore-points.mir index d9b117bd9c240..f5d63287affa1 100644 --- a/test/CodeGen/MIR/X86/frame-info-save-restore-points.mir +++ b/test/CodeGen/MIR/X86/frame-info-save-restore-points.mir @@ -30,33 +30,33 @@ liveins: - { reg: '%edi' } - { reg: '%esi' } # CHECK: frameInfo: -# CHECK: savePoint: '%bb.2.true' -# CHECK-NEXT: restorePoint: '%bb.2.true' +# CHECK: savePoint: '%bb.2' +# CHECK-NEXT: restorePoint: '%bb.2' # CHECK: stack frameInfo: maxAlignment: 4 hasCalls: true - savePoint: '%bb.2.true' - restorePoint: '%bb.2.true' + savePoint: '%bb.2' + restorePoint: '%bb.2' stack: - { id: 0, name: tmp, offset: 0, size: 4, alignment: 4 } body: | bb.0: - successors: %bb.2.true, %bb.1 + successors: %bb.2, %bb.1 liveins: %edi, %esi %eax = COPY %edi CMP32rr %eax, killed %esi, implicit-def %eflags - JL_1 %bb.2.true, implicit killed %eflags + JL_1 %bb.2, implicit killed %eflags bb.1: - successors: %bb.3.false + successors: %bb.3 liveins: %eax - JMP_1 %bb.3.false + JMP_1 %bb.3 bb.2.true: - successors: %bb.3.false + successors: %bb.3 liveins: %eax MOV32mr %stack.0.tmp, 1, _, 0, _, killed %eax diff --git a/test/CodeGen/MIR/X86/global-value-operands.mir b/test/CodeGen/MIR/X86/global-value-operands.mir index 9b9554da7bd69..8c8dee9214f2c 100644 --- a/test/CodeGen/MIR/X86/global-value-operands.mir +++ b/test/CodeGen/MIR/X86/global-value-operands.mir @@ -64,7 +64,7 @@ name: inc body: | bb.0.entry: - ; CHECK: %rax = MOV64rm %rip, 1, _, @G, _ + ; CHECK: %rax = MOV64rm %rip, 1, %noreg, @G, %noreg %rax = MOV64rm %rip, 1, _, @G, _ %eax = MOV32rm %rax, 1, _, 0, _ %eax = INC32r %eax, implicit-def %eflags @@ -75,7 +75,7 @@ body: | name: inc2 body: | bb.0.entry: - ; CHECK: %rax = MOV64rm %rip, 1, _, @0, _ + ; CHECK: %rax = MOV64rm %rip, 1, %noreg, @0, %noreg %rax = MOV64rm %rip, 1, _, @0, _ %eax = MOV32rm %rax, 1, _, 0, _ %eax = INC32r %eax, implicit-def %eflags @@ -132,7 +132,7 @@ body: | name: tf body: | bb.0.entry: - ; CHECK: %rax = MOV64rm %rip, 1, _, target-flags(x86-gotpcrel) @G, _ + ; CHECK: %rax = MOV64rm %rip, 1, %noreg, target-flags(x86-gotpcrel) @G, %noreg %rax = MOV64rm %rip, 1, _, target-flags(x86-gotpcrel) @G, _ %eax = MOV32rm %rax, 1, _, 0, _ %eax = INC32r %eax, implicit-def %eflags diff --git a/test/CodeGen/MIR/X86/implicit-register-flag.mir b/test/CodeGen/MIR/X86/implicit-register-flag.mir index 70b1cc5009445..dddbfc90cf650 100644 --- a/test/CodeGen/MIR/X86/implicit-register-flag.mir +++ b/test/CodeGen/MIR/X86/implicit-register-flag.mir @@ -31,11 +31,11 @@ name: foo body: | bb.0.entry: - successors: %bb.1.less, %bb.2.exit + successors: %bb.1, %bb.2 ; CHECK: CMP32ri8 %edi, 10, implicit-def %eflags - ; CHECK-NEXT: JG_1 %bb.2.exit, implicit %eflags + ; CHECK-NEXT: JG_1 %bb.2, implicit %eflags CMP32ri8 %edi, 10, implicit-def %eflags - JG_1 %bb.2.exit, implicit %eflags + JG_1 %bb.2, implicit %eflags bb.1.less: ; CHECK: %eax = MOV32r0 implicit-def %eflags diff --git a/test/CodeGen/MIR/X86/instructions-debug-location.mir b/test/CodeGen/MIR/X86/instructions-debug-location.mir index 28809d3ee9072..c49dfec53bb95 100644 --- a/test/CodeGen/MIR/X86/instructions-debug-location.mir +++ b/test/CodeGen/MIR/X86/instructions-debug-location.mir @@ -59,7 +59,7 @@ stack: body: | bb.0.entry: liveins: %edi - ; CHECK: DBG_VALUE debug-use _, 0, !11, !DIExpression(), debug-location !12 + ; CHECK: DBG_VALUE debug-use %noreg, 0, !11, !DIExpression(), debug-location !12 ; CHECK: %eax = COPY %0, debug-location !13 ; CHECK: RETQ %eax, debug-location !13 %0 = COPY %edi @@ -82,9 +82,9 @@ body: | liveins: %edi %0 = COPY %edi - ; CHECK: DBG_VALUE _, i32 0, !DIExpression(), !12 - ; CHECK-NEXT: DBG_VALUE _, i64 -22, !DIExpression(), !12 - ; CHECK-NEXT: DBG_VALUE _, i128 123492148938512984928424384934328985928, !DIExpression(), !12 + ; CHECK: DBG_VALUE %noreg, i32 0, !DIExpression(), !12 + ; CHECK-NEXT: DBG_VALUE %noreg, i64 -22, !DIExpression(), !12 + ; CHECK-NEXT: DBG_VALUE %noreg, i128 123492148938512984928424384934328985928, !DIExpression(), !12 DBG_VALUE _, i32 0, !DIExpression(), !13 DBG_VALUE _, i64 -22, !DIExpression(), !13 DBG_VALUE _, i128 123492148938512984928424384934328985928, !DIExpression(), !13 diff --git a/test/CodeGen/MIR/X86/jump-table-info.mir b/test/CodeGen/MIR/X86/jump-table-info.mir index e44f4b237df46..71dd46b821813 100644 --- a/test/CodeGen/MIR/X86/jump-table-info.mir +++ b/test/CodeGen/MIR/X86/jump-table-info.mir @@ -61,24 +61,24 @@ name: test_jumptable # CHECK-NEXT: kind: label-difference32 # CHECK-NEXT: entries: # CHECK-NEXT: - id: 0 -# CHECK-NEXT: blocks: [ '%bb.3.lbl1', '%bb.4.lbl2', '%bb.5.lbl3', '%bb.6.lbl4' ] +# CHECK-NEXT: blocks: [ '%bb.3', '%bb.4', '%bb.5', '%bb.6' ] # CHECK-NEXT: body: jumpTable: kind: label-difference32 entries: - id: 0 - blocks: [ '%bb.3.lbl1', '%bb.4.lbl2', '%bb.5.lbl3', '%bb.6.lbl4' ] + blocks: [ '%bb.3', '%bb.4', '%bb.5', '%bb.6' ] body: | bb.0.entry: - successors: %bb.2.def, %bb.1.entry + successors: %bb.2, %bb.1 %eax = MOV32rr %edi, implicit-def %rax CMP32ri8 %edi, 3, implicit-def %eflags - JA_1 %bb.2.def, implicit %eflags + JA_1 %bb.2, implicit %eflags bb.1.entry: - successors: %bb.3.lbl1, %bb.4.lbl2, %bb.5.lbl3, %bb.6.lbl4 - ; CHECK: %rcx = LEA64r %rip, 1, _, %jump-table.0, _ + successors: %bb.3, %bb.4, %bb.5, %bb.6 + ; CHECK: %rcx = LEA64r %rip, 1, %noreg, %jump-table.0, %noreg %rcx = LEA64r %rip, 1, _, %jump-table.0, _ %rax = MOVSX64rm32 %rcx, 4, %rax, 0, _ %rax = ADD64rr %rax, %rcx, implicit-def %eflags @@ -110,19 +110,19 @@ jumpTable: kind: label-difference32 entries: - id: 1 - blocks: [ '%bb.3.lbl1', '%bb.4.lbl2', '%bb.5.lbl3', '%bb.6.lbl4' ] + blocks: [ '%bb.3', '%bb.4', '%bb.5', '%bb.6' ] body: | bb.0.entry: - successors: %bb.2.def, %bb.1.entry + successors: %bb.2, %bb.1 %eax = MOV32rr %edi, implicit-def %rax CMP32ri8 %edi, 3, implicit-def %eflags - JA_1 %bb.2.def, implicit %eflags + JA_1 %bb.2, implicit %eflags bb.1.entry: - successors: %bb.3.lbl1, %bb.4.lbl2, %bb.5.lbl3, %bb.6.lbl4 + successors: %bb.3, %bb.4, %bb.5, %bb.6 ; Verify that the printer will use an id of 0 for this jump table: - ; CHECK: %rcx = LEA64r %rip, 1, _, %jump-table.0, _ + ; CHECK: %rcx = LEA64r %rip, 1, %noreg, %jump-table.0, %noreg %rcx = LEA64r %rip, 1, _, %jump-table.1, _ %rax = MOVSX64rm32 %rcx, 4, %rax, 0, _ %rax = ADD64rr %rax, %rcx, implicit-def %eflags diff --git a/test/CodeGen/MIR/X86/machine-basic-block-operands.mir b/test/CodeGen/MIR/X86/machine-basic-block-operands.mir index f59157386796c..a7866f239be66 100644 --- a/test/CodeGen/MIR/X86/machine-basic-block-operands.mir +++ b/test/CodeGen/MIR/X86/machine-basic-block-operands.mir @@ -36,13 +36,13 @@ name: foo body: | ; CHECK: bb.0.entry bb.0.entry: - successors: %bb.1.less, %bb.2.exit + successors: %bb.1, %bb.2 %eax = MOV32rm %rdi, 1, _, 0, _ ; CHECK: CMP32ri8 %eax, 10 - ; CHECK-NEXT: JG_1 %bb.2.exit + ; CHECK-NEXT: JG_1 %bb.2 CMP32ri8 %eax, 10, implicit-def %eflags - JG_1 %bb.2.exit, implicit %eflags + JG_1 %bb.2, implicit %eflags ; CHECK: bb.1.less: bb.1.less: diff --git a/test/CodeGen/MIR/X86/memory-operands.mir b/test/CodeGen/MIR/X86/memory-operands.mir index 5ac932e90348c..5db721da72ecd 100644 --- a/test/CodeGen/MIR/X86/memory-operands.mir +++ b/test/CodeGen/MIR/X86/memory-operands.mir @@ -198,8 +198,8 @@ liveins: body: | bb.0.entry: liveins: %rdi - ; CHECK: %eax = MOV32rm %rdi, 1, _, 0, _ :: (load 4 from %ir.a) - ; CHECK-NEXT: MOV32mi killed %rdi, 1, _, 0, _, 42 :: (store 4 into %ir.a) + ; CHECK: %eax = MOV32rm %rdi, 1, %noreg, 0, %noreg :: (load 4 from %ir.a) + ; CHECK-NEXT: MOV32mi killed %rdi, 1, %noreg, 0, %noreg, 42 :: (store 4 into %ir.a) %eax = MOV32rm %rdi, 1, _, 0, _ :: (load 4 from %ir.a) MOV32mi killed %rdi, 1, _, 0, _, 42 :: (store 4 into %ir.a) RETQ %eax @@ -212,7 +212,7 @@ liveins: body: | bb.0.entry2: liveins: %rdi - ; CHECK: INC32m killed %rdi, 1, _, 0, _, implicit-def dead %eflags :: (store 4 into %ir."a value"), (load 4 from %ir."a value") + ; CHECK: INC32m killed %rdi, 1, %noreg, 0, %noreg, implicit-def dead %eflags :: (store 4 into %ir."a value"), (load 4 from %ir."a value") INC32m killed %rdi, 1, _, 0, _, implicit-def dead %eflags :: (store 4 into %ir."a value"), (load 4 from %ir."a value") RETQ ... @@ -230,8 +230,8 @@ body: | liveins: %rdi ; Verify that the unnamed local values can be serialized. ; CHECK-LABEL: name: test3 - ; CHECK: %eax = MOV32rm killed %rdi, 1, _, 0, _ :: (load 4 from %ir.0) - ; CHECK: MOV32mr %rsp, 1, _, -4, _, killed %eax :: (store 4 into %ir.1) + ; CHECK: %eax = MOV32rm killed %rdi, 1, %noreg, 0, %noreg :: (load 4 from %ir.0) + ; CHECK: MOV32mr %rsp, 1, %noreg, -4, %noreg, killed %eax :: (store 4 into %ir.1) %eax = MOV32rm killed %rdi, 1, _, 0, _ :: (load 4 from %ir.0) %eax = INC32r killed %eax, implicit-def dead %eflags MOV32mr %rsp, 1, _, -4, _, killed %eax :: (store 4 into %ir.1) @@ -246,8 +246,8 @@ body: | bb.0.entry: liveins: %rdi ; CHECK: name: volatile_inc - ; CHECK: %eax = MOV32rm %rdi, 1, _, 0, _ :: (volatile load 4 from %ir.x) - ; CHECK: MOV32mr killed %rdi, 1, _, 0, _, %eax :: (volatile store 4 into %ir.x) + ; CHECK: %eax = MOV32rm %rdi, 1, %noreg, 0, %noreg :: (volatile load 4 from %ir.x) + ; CHECK: MOV32mr killed %rdi, 1, %noreg, 0, %noreg, %eax :: (volatile store 4 into %ir.x) %eax = MOV32rm %rdi, 1, _, 0, _ :: (volatile load 4 from %ir.x) %eax = INC32r killed %eax, implicit-def dead %eflags MOV32mr killed %rdi, 1, _, 0, _, %eax :: (volatile store 4 into %ir.x) @@ -263,7 +263,7 @@ body: | bb.0.entry: liveins: %esi, %rdi ; CHECK: name: non_temporal_store - ; CHECK: MOVNTImr killed %rdi, 1, _, 0, _, killed %esi :: (non-temporal store 4 into %ir.a) + ; CHECK: MOVNTImr killed %rdi, 1, %noreg, 0, %noreg, killed %esi :: (non-temporal store 4 into %ir.a) MOVNTImr killed %rdi, 1, _, 0, _, killed %esi :: (non-temporal store 4 into %ir.a) RETQ ... @@ -276,7 +276,7 @@ body: | bb.0.entry: liveins: %rdi ; CHECK: name: invariant_load - ; CHECK: %eax = MOV32rm killed %rdi, 1, _, 0, _ :: (invariant load 4 from %ir.x) + ; CHECK: %eax = MOV32rm killed %rdi, 1, %noreg, 0, %noreg :: (invariant load 4 from %ir.x) %eax = MOV32rm killed %rdi, 1, _, 0, _ :: (invariant load 4 from %ir.x) RETQ %eax ... @@ -289,10 +289,10 @@ body: | bb.0.entry: liveins: %rdi ; CHECK: name: memory_offset - ; CHECK: %xmm0 = MOVAPSrm %rdi, 1, _, 0, _ :: (load 16 from %ir.vec) - ; CHECK-NEXT: %xmm1 = MOVAPSrm %rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16) - ; CHECK: MOVAPSmr %rdi, 1, _, 0, _, killed %xmm0 :: (store 16 into %ir.vec) - ; CHECK-NEXT: MOVAPSmr killed %rdi, 1, _, 16, _, killed %xmm1 :: (store 16 into %ir.vec + 16) + ; CHECK: %xmm0 = MOVAPSrm %rdi, 1, %noreg, 0, %noreg :: (load 16 from %ir.vec) + ; CHECK-NEXT: %xmm1 = MOVAPSrm %rdi, 1, %noreg, 16, %noreg :: (load 16 from %ir.vec + 16) + ; CHECK: MOVAPSmr %rdi, 1, %noreg, 0, %noreg, killed %xmm0 :: (store 16 into %ir.vec) + ; CHECK-NEXT: MOVAPSmr killed %rdi, 1, %noreg, 16, %noreg, killed %xmm1 :: (store 16 into %ir.vec + 16) %xmm0 = MOVAPSrm %rdi, 1, _, 0, _ :: (load 16 from %ir.vec) %xmm1 = MOVAPSrm %rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16) %xmm2 = FsFLD0SS @@ -310,10 +310,10 @@ body: | bb.0.entry: liveins: %rdi ; CHECK: name: memory_alignment - ; CHECK: %xmm0 = MOVAPSrm %rdi, 1, _, 0, _ :: (load 16 from %ir.vec, align 32) - ; CHECK-NEXT: %xmm1 = MOVAPSrm %rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16, align 32) - ; CHECK: MOVAPSmr %rdi, 1, _, 0, _, killed %xmm0 :: (store 16 into %ir.vec, align 32) - ; CHECK-NEXT: MOVAPSmr killed %rdi, 1, _, 16, _, killed %xmm1 :: (store 16 into %ir.vec + 16, align 32) + ; CHECK: %xmm0 = MOVAPSrm %rdi, 1, %noreg, 0, %noreg :: (load 16 from %ir.vec, align 32) + ; CHECK-NEXT: %xmm1 = MOVAPSrm %rdi, 1, %noreg, 16, %noreg :: (load 16 from %ir.vec + 16, align 32) + ; CHECK: MOVAPSmr %rdi, 1, %noreg, 0, %noreg, killed %xmm0 :: (store 16 into %ir.vec, align 32) + ; CHECK-NEXT: MOVAPSmr killed %rdi, 1, %noreg, 16, %noreg, killed %xmm1 :: (store 16 into %ir.vec + 16, align 32) %xmm0 = MOVAPSrm %rdi, 1, _, 0, _ :: (load 16 from %ir.vec, align 32) %xmm1 = MOVAPSrm %rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16, align 32) %xmm2 = FsFLD0SS @@ -334,8 +334,8 @@ body: | bb.0.entry: liveins: %xmm0 ; CHECK: name: constant_pool_psv - ; CHECK: %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _ :: (load 8 from constant-pool) - ; CHECK-NEXT: %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _ :: (load 8 from constant-pool + 8) + ; CHECK: %xmm0 = ADDSDrm killed %xmm0, %rip, 1, %noreg, %const.0, %noreg :: (load 8 from constant-pool) + ; CHECK-NEXT: %xmm0 = ADDSDrm killed %xmm0, %rip, 1, %noreg, %const.0, %noreg :: (load 8 from constant-pool + 8) %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _ :: (load 8 from constant-pool) %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _ :: (load 8 from constant-pool + 8) RETQ %xmm0 @@ -355,9 +355,9 @@ body: | bb.0.entry: %rsp = frame-setup SUB64ri8 %rsp, 24, implicit-def dead %eflags CFI_INSTRUCTION def_cfa_offset 32 - LD_F80m %rsp, 1, _, 32, _, implicit-def dead %fpsw + LD_F80m %rsp, 1, %noreg, 32, %noreg, implicit-def dead %fpsw ; CHECK: name: stack_psv - ; CHECK: ST_FP80m %rsp, 1, _, 0, _, implicit-def dead %fpsw :: (store 10 into stack, align 16) + ; CHECK: ST_FP80m %rsp, 1, %noreg, 0, %noreg, implicit-def dead %fpsw :: (store 10 into stack, align 16) ST_FP80m %rsp, 1, _, 0, _, implicit-def dead %fpsw :: (store 10 into stack, align 16) CALL64pcrel32 $cosl, csr_64, implicit %rsp, implicit-def %rsp, implicit-def %fp0 %rsp = ADD64ri8 %rsp, 24, implicit-def dead %eflags @@ -369,7 +369,7 @@ tracksRegLiveness: true body: | bb.0.entry: ; CHECK: name: got_psv - ; CHECK: %rax = MOV64rm %rip, 1, _, @G, _ :: (load 8 from got) + ; CHECK: %rax = MOV64rm %rip, 1, %noreg, @G, %noreg :: (load 8 from got) %rax = MOV64rm %rip, 1, _, @G, _ :: (load 8 from got) %eax = MOV32rm killed %rax, 1, _, 0, _ %eax = INC32r killed %eax, implicit-def dead %eflags @@ -382,8 +382,8 @@ body: | bb.0.entry: %rax = MOV64rm %rip, 1, _, @G, _ ; CHECK-LABEL: name: global_value - ; CHECK: %eax = MOV32rm killed %rax, 1, _, 0, _, implicit-def %rax :: (load 4 from @G) - ; CHECK: %ecx = MOV32rm killed %rcx, 1, _, 0, _, implicit-def %rcx :: (load 4 from @0) + ; CHECK: %eax = MOV32rm killed %rax, 1, %noreg, 0, %noreg, implicit-def %rax :: (load 4 from @G) + ; CHECK: %ecx = MOV32rm killed %rcx, 1, %noreg, 0, %noreg, implicit-def %rcx :: (load 4 from @0) %eax = MOV32rm killed %rax, 1, _, 0, _, implicit-def %rax :: (load 4 from @G) %rcx = MOV64rm %rip, 1, _, @0, _ %ecx = MOV32rm killed %rcx, 1, _, 0, _, implicit-def %rcx :: (load 4 from @0) @@ -415,7 +415,7 @@ body: | %rcx = LEA64r %rip, 1, _, %jump-table.0, _ ; CHECK: name: jumptable_psv - ; CHECK: %rax = MOVSX64rm32 %rcx, 4, killed %rax, 0, _ :: (load 4 from jump-table, align 8) + ; CHECK: %rax = MOVSX64rm32 %rcx, 4, killed %rax, 0, %noreg :: (load 4 from jump-table, align 8) %rax = MOVSX64rm32 %rcx, 4, killed %rax, 0, _ :: (load 4 from jump-table, align 8) %rax = ADD64rr killed %rax, killed %rcx, implicit-def dead %eflags JMP64r killed %rax @@ -447,8 +447,8 @@ body: | bb.0.entry: %rax = MOV64rm %rip, 1, _, @a, _ :: (load 8 from got) ; CHECK-LABEL: name: tbaa_metadata - ; CHECK: %eax = MOV32rm killed %rax, 1, _, 0, _, implicit-def %rax :: (load 4 from @a, !tbaa !2) - ; CHECK-NEXT: %eax = MOV32rm killed %rax, 1, _, 0, _ :: (load 4 from %ir.total_len2, !tbaa !6) + ; CHECK: %eax = MOV32rm killed %rax, 1, %noreg, 0, %noreg, implicit-def %rax :: (load 4 from @a, !tbaa !2) + ; CHECK-NEXT: %eax = MOV32rm killed %rax, 1, %noreg, 0, %noreg :: (load 4 from %ir.total_len2, !tbaa !6) %eax = MOV32rm killed %rax, 1, _, 0, _, implicit-def %rax :: (load 4 from @a, !tbaa !2) %eax = MOV32rm killed %rax, 1, _, 0, _ :: (load 4 from %ir.total_len2, !tbaa !6) RETQ %eax @@ -463,9 +463,9 @@ body: | bb.0.entry: liveins: %rdi, %rsi ; CHECK-LABEL: name: aa_scope - ; CHECK: %xmm0 = MOVSSrm %rsi, 1, _, 0, _ :: (load 4 from %ir.c, !alias.scope !9) + ; CHECK: %xmm0 = MOVSSrm %rsi, 1, %noreg, 0, %noreg :: (load 4 from %ir.c, !alias.scope !9) %xmm0 = MOVSSrm %rsi, 1, _, 0, _ :: (load 4 from %ir.c, !alias.scope !9) - ; CHECK-NEXT: MOVSSmr %rdi, 1, _, 20, _, killed %xmm0 :: (store 4 into %ir.arrayidx.i, !noalias !9) + ; CHECK-NEXT: MOVSSmr %rdi, 1, %noreg, 20, %noreg, killed %xmm0 :: (store 4 into %ir.arrayidx.i, !noalias !9) MOVSSmr %rdi, 1, _, 20, _, killed %xmm0 :: (store 4 into %ir.arrayidx.i, !noalias !9) %xmm0 = MOVSSrm killed %rsi, 1, _, 0, _ :: (load 4 from %ir.c) MOVSSmr killed %rdi, 1, _, 28, _, killed %xmm0 :: (store 4 into %ir.arrayidx) @@ -480,7 +480,7 @@ body: | bb.0.entry: liveins: %rdi ; CHECK-LABEL: name: range_metadata - ; CHECK: %al = MOV8rm killed %rdi, 1, _, 0, _ :: (load 1 from %ir.x, !range !11) + ; CHECK: %al = MOV8rm killed %rdi, 1, %noreg, 0, %noreg :: (load 1 from %ir.x, !range !11) %al = MOV8rm killed %rdi, 1, _, 0, _ :: (load 1 from %ir.x, !range !11) RETQ %al ... @@ -495,7 +495,7 @@ body: | %rax = MOV64rm %rip, 1, _, @values, _ :: (load 8 from got) ; CHECK-LABEL: gep_value - ; CHECK: MOV32mr killed %rax, 1, _, 0, _, %edi, implicit killed %rdi :: (store 4 into `i32* getelementptr inbounds ([50 x %st], [50 x %st]* @values, i64 0, i64 0, i32 0)`, align 16) + ; CHECK: MOV32mr killed %rax, 1, %noreg, 0, %noreg, %edi, implicit killed %rdi :: (store 4 into `i32* getelementptr inbounds ([50 x %st], [50 x %st]* @values, i64 0, i64 0, i32 0)`, align 16) MOV32mr killed %rax, 1, _, 0, _, %edi, implicit killed %rdi :: (store 4 into `i32* getelementptr inbounds ([50 x %st], [50 x %st]* @values, i64 0, i64 0, i32 0)`, align 16) RETQ ... @@ -505,14 +505,14 @@ tracksRegLiveness: true body: | bb.0.entry: ; CHECK-LABEL: name: undef_value - ; CHECK: %rax = MOV64rm undef %rax, 1, _, 0, _ :: (load 8 from `i8** undef`) + ; CHECK: %rax = MOV64rm undef %rax, 1, %noreg, 0, %noreg :: (load 8 from `i8** undef`) %rax = MOV64rm undef %rax, 1, _, 0, _ :: (load 8 from `i8** undef`) RETQ %rax ... --- # Test memory operand without associated value. # CHECK-LABEL: name: dummy0 -# CHECK: %rax = MOV64rm undef %rax, 1, _, 0, _ :: (load 8) +# CHECK: %rax = MOV64rm undef %rax, 1, %noreg, 0, %noreg :: (load 8) name: dummy0 tracksRegLiveness: true body: | @@ -523,7 +523,7 @@ body: | --- # Test parsing of stack references in machine memory operands. # CHECK-LABEL: name: dummy1 -# CHECK: %rax = MOV64rm %rsp, 1, _, 0, _ :: (load 8 from %stack.0) +# CHECK: %rax = MOV64rm %rsp, 1, %noreg, 0, %noreg :: (load 8 from %stack.0) name: dummy1 tracksRegLiveness: true stack: diff --git a/test/CodeGen/MIR/X86/metadata-operands.mir b/test/CodeGen/MIR/X86/metadata-operands.mir index 501d0c58a635e..94091cdb827a4 100644 --- a/test/CodeGen/MIR/X86/metadata-operands.mir +++ b/test/CodeGen/MIR/X86/metadata-operands.mir @@ -51,7 +51,7 @@ body: | bb.0.entry: liveins: %edi ; CHECK: %0:gr32 = COPY %edi - ; CHECK-NEXT: DBG_VALUE _, 0, !11, !DIExpression() + ; CHECK-NEXT: DBG_VALUE %noreg, 0, !11, !DIExpression() %0 = COPY %edi DBG_VALUE _, 0, !12, !DIExpression() MOV32mr %stack.0.x.addr, 1, _, 0, _, %0 diff --git a/test/CodeGen/MIR/X86/newline-handling.mir b/test/CodeGen/MIR/X86/newline-handling.mir index ce53e49eddbbe..1a93c1a642503 100644 --- a/test/CodeGen/MIR/X86/newline-handling.mir +++ b/test/CodeGen/MIR/X86/newline-handling.mir @@ -35,10 +35,10 @@ liveins: # CHECK-LABEL: name: foo # CHECK: body: | # CHECK-NEXT: bb.0.entry: -# CHECK-NEXT: successors: %bb.1.less(0x40000000), %bb.2.exit(0x40000000) +# CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) # CHECK-NEXT: liveins: %edi # CHECK: CMP32ri8 %edi, 10, implicit-def %eflags -# CHECK-NEXT: JG_1 %bb.2.exit, implicit killed %eflags +# CHECK-NEXT: JG_1 %bb.2, implicit killed %eflags # CHECK: bb.1.less: # CHECK-NEXT: %eax = MOV32r0 implicit-def dead %eflags @@ -50,13 +50,13 @@ liveins: # CHECK-NEXT: RETQ killed %eax body: | bb.0.entry: - successors: %bb.1.less, %bb.2.exit + successors: %bb.1, %bb.2 liveins: %edi CMP32ri8 %edi, 10, implicit-def %eflags - JG_1 %bb.2.exit, implicit killed %eflags + JG_1 %bb.2, implicit killed %eflags bb.1.less: @@ -79,10 +79,10 @@ liveins: # CHECK-LABEL: name: bar # CHECK: body: | # CHECK-NEXT: bb.0.entry: -# CHECK-NEXT: successors: %bb.1.less(0x40000000), %bb.2.exit(0x40000000) +# CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) # CHECK-NEXT: liveins: %edi # CHECK: CMP32ri8 %edi, 10, implicit-def %eflags -# CHECK-NEXT: JG_1 %bb.2.exit, implicit killed %eflags +# CHECK-NEXT: JG_1 %bb.2, implicit killed %eflags # CHECK: bb.1.less: # CHECK-NEXT: %eax = MOV32r0 implicit-def dead %eflags @@ -95,10 +95,10 @@ liveins: body: | bb.0.entry: - successors: %bb.1.less, %bb.2.exit + successors: %bb.1, %bb.2 liveins: %edi CMP32ri8 %edi, 10, implicit-def %eflags - JG_1 %bb.2.exit, implicit killed %eflags + JG_1 %bb.2, implicit killed %eflags bb.1.less: %eax = MOV32r0 implicit-def dead %eflags RETQ killed %eax diff --git a/test/CodeGen/MIR/X86/null-register-operands.mir b/test/CodeGen/MIR/X86/null-register-operands.mir index 9cba00bc9e5e4..bb7a2e5688c0f 100644 --- a/test/CodeGen/MIR/X86/null-register-operands.mir +++ b/test/CodeGen/MIR/X86/null-register-operands.mir @@ -15,7 +15,7 @@ name: deref body: | bb.0.entry: - ; CHECK: %eax = MOV32rm %rdi, 1, _, 0, _ + ; CHECK: %eax = MOV32rm %rdi, 1, %noreg, 0, %noreg ; CHECK-NEXT: RETQ %eax %eax = MOV32rm %rdi, 1, _, 0, %noreg RETQ %eax diff --git a/test/CodeGen/MIR/X86/roundtrip.mir b/test/CodeGen/MIR/X86/roundtrip.mir index 9679b52f2bac3..6d5c3516f3375 100644 --- a/test/CodeGen/MIR/X86/roundtrip.mir +++ b/test/CodeGen/MIR/X86/roundtrip.mir @@ -8,7 +8,7 @@ # CHECK: bb.0: # CHECK: %0:gr32 = MOV32r0 implicit-def %eflags # CHECK: dead %1:gr32 = COPY %0 -# CHECK: MOV32mr undef %rcx, 1, _, 0, _, killed %0 :: (volatile store 4) +# CHECK: MOV32mr undef %rcx, 1, %noreg, 0, %noreg, killed %0 :: (volatile store 4) # CHECK: RETQ undef %eax name: func0 body: | diff --git a/test/CodeGen/MIR/X86/stack-object-operands.mir b/test/CodeGen/MIR/X86/stack-object-operands.mir index 262b6dcb3993d..806caf6a290aa 100644 --- a/test/CodeGen/MIR/X86/stack-object-operands.mir +++ b/test/CodeGen/MIR/X86/stack-object-operands.mir @@ -32,10 +32,10 @@ stack: body: | bb.0.entry: ; CHECK-LABEL: name: test - ; CHECK: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.0, 1, _, 0, _ - ; CHECK: MOV32mr %stack.0.b, 1, _, 0, _, [[MOV32rm]] - ; CHECK: MOV32mi %stack.1, 1, _, 0, _, 2 - ; CHECK: [[MOV32rm1:%[0-9]+]]:gr32 = MOV32rm %stack.0.b, 1, _, 0, _ + ; CHECK: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.0, 1, %noreg, 0, %noreg + ; CHECK: MOV32mr %stack.0.b, 1, %noreg, 0, %noreg, [[MOV32rm]] + ; CHECK: MOV32mi %stack.1, 1, %noreg, 0, %noreg, 2 + ; CHECK: [[MOV32rm1:%[0-9]+]]:gr32 = MOV32rm %stack.0.b, 1, %noreg, 0, %noreg ; CHECK: %eax = COPY [[MOV32rm1]] ; CHECK: RETL %eax %0 = MOV32rm %fixed-stack.0, 1, _, 0, _ diff --git a/test/CodeGen/MIR/X86/successor-basic-blocks-weights.mir b/test/CodeGen/MIR/X86/successor-basic-blocks-weights.mir index 512ba4e41aac2..5a22557f3246d 100644 --- a/test/CodeGen/MIR/X86/successor-basic-blocks-weights.mir +++ b/test/CodeGen/MIR/X86/successor-basic-blocks-weights.mir @@ -21,14 +21,14 @@ name: foo body: | ; CHECK-LABEL: bb.0.entry: - ; CHECK: successors: %bb.1.less(0x2a3d70a4), %bb.2.exit(0x55c28f5c) + ; CHECK: successors: %bb.1(0x2a3d70a4), %bb.2(0x55c28f5c) ; CHECK-LABEL: bb.1.less: bb.0.entry: - successors: %bb.1.less (33), %bb.2.exit(67) + successors: %bb.1 (33), %bb.2(67) liveins: %edi CMP32ri8 %edi, 10, implicit-def %eflags - JG_1 %bb.2.exit, implicit killed %eflags + JG_1 %bb.2, implicit killed %eflags bb.1.less: %eax = MOV32r0 implicit-def dead %eflags diff --git a/test/CodeGen/MSP430/BranchSelector.ll b/test/CodeGen/MSP430/BranchSelector.ll index 4dfd95bf41afb..a36da626234a2 100644 --- a/test/CodeGen/MSP430/BranchSelector.ll +++ b/test/CodeGen/MSP430/BranchSelector.ll @@ -579,7 +579,7 @@ begin: ; This branch should not be expanded ; CHECK-LABEL: .LBB1_1: ; CHECK: jeq .LBB1_1 -; CHECK: BB#2: +; CHECK: %bb.2: ; CHECK: ret br i1 %lnot, label %begin, label %end diff --git a/test/CodeGen/Mips/compactbranches/empty-block.mir b/test/CodeGen/Mips/compactbranches/empty-block.mir index 7fb1afae91210..5bfaef0cb6933 100644 --- a/test/CodeGen/Mips/compactbranches/empty-block.mir +++ b/test/CodeGen/Mips/compactbranches/empty-block.mir @@ -5,11 +5,11 @@ # CHECK: blezc # CHECK: nop -# CHECK: # BB#1: +# CHECK: # %bb.1: # CHECK: .insn -# CHECK: # BB#2: +# CHECK: # %bb.2: # CHECK: .insn -# CHECK: # BB#3: +# CHECK: # %bb.3: # CHECK: jal --- | diff --git a/test/CodeGen/Mips/const-mult.ll b/test/CodeGen/Mips/const-mult.ll index 47efdbf163cc2..459aad61828c4 100644 --- a/test/CodeGen/Mips/const-mult.ll +++ b/test/CodeGen/Mips/const-mult.ll @@ -90,4 +90,4 @@ define i128 @mul170141183460469231731687303715884105723_128(i128 signext %a) { entry: %mul = mul nsw i128 %a, 170141183460469231731687303715884105723 ret i128 %mul -} \ No newline at end of file +} diff --git a/test/CodeGen/Mips/lcb4a.ll b/test/CodeGen/Mips/lcb4a.ll index 4a99ef26efcae..016e895d12efc 100644 --- a/test/CodeGen/Mips/lcb4a.ll +++ b/test/CodeGen/Mips/lcb4a.ll @@ -26,7 +26,7 @@ if.end: ; preds = %if.else, %if.then } ; ci: beqz $3, $BB0_2 -; ci: # BB#1: # %if.else +; ci: # %bb.1: # %if.else ; Function Attrs: nounwind optsize diff --git a/test/CodeGen/Mips/mips64signextendsesf.ll b/test/CodeGen/Mips/mips64signextendsesf.ll index d0ce1b86bf561..2ee1e09f50029 100644 --- a/test/CodeGen/Mips/mips64signextendsesf.ll +++ b/test/CodeGen/Mips/mips64signextendsesf.ll @@ -211,4 +211,4 @@ declare float @fminf(float, float) #1 attributes #0 = { nounwind "use-soft-float"="true" } -attributes #1 = { nounwind readnone "use-soft-float"="true" } \ No newline at end of file +attributes #1 = { nounwind readnone "use-soft-float"="true" } diff --git a/test/CodeGen/Mips/prevent-hoisting.ll b/test/CodeGen/Mips/prevent-hoisting.ll index ca71bf7d1af41..1fc7462811cb2 100644 --- a/test/CodeGen/Mips/prevent-hoisting.ll +++ b/test/CodeGen/Mips/prevent-hoisting.ll @@ -16,7 +16,7 @@ ; CHECK: sll ; Check that at the start of a fallthrough block there is a instruction that writes to $1. -; CHECK: {{BB[0-9_#]+}}: +; CHECK: {{%bb.[0-9]+}}: ; CHECK: sll $1, $[[R0:[0-9]+]], 4 ; CHECK: lw $[[R1:[0-9]+]], %got(assignSE2partition)($[[R2:[0-9]+]]) diff --git a/test/CodeGen/NVPTX/symbol-naming.ll b/test/CodeGen/NVPTX/symbol-naming.ll index 7a3e6310ffdf9..3f1caf927dc81 100644 --- a/test/CodeGen/NVPTX/symbol-naming.ll +++ b/test/CodeGen/NVPTX/symbol-naming.ll @@ -1,17 +1,17 @@ -; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s --check-prefix=PTX32 -; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck %s --check-prefix=PTX64 +; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s +; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck %s ; Verify that the NVPTX target removes invalid symbol names prior to emitting ; PTX. -; PTX32-NOT: .str -; PTX64-NOT: .str +; CHECK-NOT: .str +; CHECK-NOT: .function. -; PTX32-DAG: _$_str.1 -; PTX32-DAG: _$_str +; CHECK-DAG: _$_str +; CHECK-DAG: _$_str1 -; PTX64-DAG: _$_str.1 -; PTX64-DAG: _$_str +; CHECK-DAG: _$_function_$_ +; CHECK-DAG: _$_function_$_2 target datalayout = "e-i64:64-v16:16-v32:32-n16:32:64" target triple = "nvptx64-unknown-unknown" @@ -22,10 +22,25 @@ target triple = "nvptx64-unknown-unknown" ; Function Attrs: nounwind -define void @foo(i32 %a, float %b, i8 signext %c, i32 %e) { +define internal void @.function.() { entry: %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([13 x i8], [13 x i8]* @.str, i32 0, i32 0)) ret void } +; Function Attrs: nounwind +define internal void @_$_function_$_() { +entry: + %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([13 x i8], [13 x i8]* @_$_str, i32 0, i32 0)) + ret void +} + +; Function Attrs: nounwind +define void @global_function() { +entry: + call void @.function.() + call void @_$_function_$_() + ret void +} + declare i32 @printf(i8*, ...) diff --git a/test/CodeGen/PowerPC/2006-07-07-ComputeMaskedBits.ll b/test/CodeGen/PowerPC/2006-07-07-ComputeMaskedBits.ll index 56f4a4173ef59..5b8b8147cce2a 100644 --- a/test/CodeGen/PowerPC/2006-07-07-ComputeMaskedBits.ll +++ b/test/CodeGen/PowerPC/2006-07-07-ComputeMaskedBits.ll @@ -6,7 +6,7 @@ define i32 @test(i32 %i) { ; CHECK-LABEL: test: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: addis 4, 2, .LC0@toc@ha ; CHECK-NEXT: extsw 3, 3 ; CHECK-NEXT: addis 5, 2, .LC1@toc@ha diff --git a/test/CodeGen/PowerPC/CompareEliminationSpillIssue.ll b/test/CodeGen/PowerPC/CompareEliminationSpillIssue.ll index 74093aa1da494..75cac9030ef89 100644 --- a/test/CodeGen/PowerPC/CompareEliminationSpillIssue.ll +++ b/test/CodeGen/PowerPC/CompareEliminationSpillIssue.ll @@ -1,14 +1,13 @@ -; XFAIL: * ; The purpose of the test case is to ensure that a spill that happens during ; intermediate calculations for a comparison performed in a GPR spills the ; full register. Some i32 comparisons performed in GPRs use code that uses ; the full 64-bits of the register in intermediate stages. Spilling such a value ; as a 32-bit value is incorrect. ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl @glob = common local_unnamed_addr global i64 0, align 8 @.str = private unnamed_addr constant [12 x i8] c"Value = %d\0A\00", align 1 diff --git a/test/CodeGen/PowerPC/addegluecrash.ll b/test/CodeGen/PowerPC/addegluecrash.ll index f17b6dce9a9dd..642960f84900c 100644 --- a/test/CodeGen/PowerPC/addegluecrash.ll +++ b/test/CodeGen/PowerPC/addegluecrash.ll @@ -5,7 +5,7 @@ target triple = "powerpc64le-unknown-linux-gnu" define void @bn_mul_comba8(i64* nocapture %r, i64* nocapture readonly %a, i64* nocapture readonly %b) { ; CHECK-LABEL: bn_mul_comba8: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: ld 6, 0(4) ; CHECK-NEXT: ld 7, 0(5) ; CHECK-NEXT: mulhdu 8, 7, 6 diff --git a/test/CodeGen/PowerPC/andc.ll b/test/CodeGen/PowerPC/andc.ll index df47bfc1e38ef..9bfbda2bbd715 100644 --- a/test/CodeGen/PowerPC/andc.ll +++ b/test/CodeGen/PowerPC/andc.ll @@ -3,7 +3,7 @@ define i1 @and_cmp1(i32 %x, i32 %y) { ; CHECK-LABEL: and_cmp1: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: andc 3, 4, 3 ; CHECK-NEXT: cntlzw 3, 3 ; CHECK-NEXT: rlwinm 3, 3, 27, 31, 31 @@ -15,7 +15,7 @@ define i1 @and_cmp1(i32 %x, i32 %y) { define i1 @and_cmp_const(i32 %x) { ; CHECK-LABEL: and_cmp_const: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: li 4, 43 ; CHECK-NEXT: andc 3, 4, 3 ; CHECK-NEXT: cntlzw 3, 3 @@ -28,7 +28,7 @@ define i1 @and_cmp_const(i32 %x) { define i1 @foo(i32 %i) { ; CHECK-LABEL: foo: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: lis 4, 4660 ; CHECK-NEXT: ori 4, 4, 22136 ; CHECK-NEXT: andc 3, 4, 3 @@ -42,7 +42,7 @@ define i1 @foo(i32 %i) { define <4 x i32> @hidden_not_v4i32(<4 x i32> %x) { ; CHECK-LABEL: hidden_not_v4i32: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vspltisw 3, 6 ; CHECK-NEXT: xxlandc 34, 35, 34 ; CHECK-NEXT: blr diff --git a/test/CodeGen/PowerPC/atomics-constant.ll b/test/CodeGen/PowerPC/atomics-constant.ll index 77825c608a3bb..559cd9eb656ac 100644 --- a/test/CodeGen/PowerPC/atomics-constant.ll +++ b/test/CodeGen/PowerPC/atomics-constant.ll @@ -7,7 +7,7 @@ target triple = "powerpc64le-unknown-linux-gnu" define i64 @foo() { ; CHECK-LABEL: foo: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis 3, 2, .LC0@toc@ha ; CHECK-NEXT: li 4, 0 ; CHECK-NEXT: ld 3, .LC0@toc@l(3) diff --git a/test/CodeGen/PowerPC/atomics-regression.ll b/test/CodeGen/PowerPC/atomics-regression.ll index c8fb1e74e73f4..7079f6dd52e90 100644 --- a/test/CodeGen/PowerPC/atomics-regression.ll +++ b/test/CodeGen/PowerPC/atomics-regression.ll @@ -3,7 +3,7 @@ define i8 @test0(i8* %ptr) { ; PPC64LE-LABEL: test0: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lbz 3, 0(3) ; PPC64LE-NEXT: blr %val = load atomic i8, i8* %ptr unordered, align 1 @@ -12,7 +12,7 @@ define i8 @test0(i8* %ptr) { define i8 @test1(i8* %ptr) { ; PPC64LE-LABEL: test1: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lbz 3, 0(3) ; PPC64LE-NEXT: blr %val = load atomic i8, i8* %ptr monotonic, align 1 @@ -21,7 +21,7 @@ define i8 @test1(i8* %ptr) { define i8 @test2(i8* %ptr) { ; PPC64LE-LABEL: test2: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lbz 3, 0(3) ; PPC64LE-NEXT: cmpd 7, 3, 3 ; PPC64LE-NEXT: bne- 7, .+4 @@ -33,7 +33,7 @@ define i8 @test2(i8* %ptr) { define i8 @test3(i8* %ptr) { ; PPC64LE-LABEL: test3: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: ori 2, 2, 0 ; PPC64LE-NEXT: lbz 3, 0(3) @@ -47,7 +47,7 @@ define i8 @test3(i8* %ptr) { define i16 @test4(i16* %ptr) { ; PPC64LE-LABEL: test4: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lhz 3, 0(3) ; PPC64LE-NEXT: blr %val = load atomic i16, i16* %ptr unordered, align 2 @@ -56,7 +56,7 @@ define i16 @test4(i16* %ptr) { define i16 @test5(i16* %ptr) { ; PPC64LE-LABEL: test5: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lhz 3, 0(3) ; PPC64LE-NEXT: blr %val = load atomic i16, i16* %ptr monotonic, align 2 @@ -65,7 +65,7 @@ define i16 @test5(i16* %ptr) { define i16 @test6(i16* %ptr) { ; PPC64LE-LABEL: test6: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lhz 3, 0(3) ; PPC64LE-NEXT: cmpd 7, 3, 3 ; PPC64LE-NEXT: bne- 7, .+4 @@ -77,7 +77,7 @@ define i16 @test6(i16* %ptr) { define i16 @test7(i16* %ptr) { ; PPC64LE-LABEL: test7: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: ori 2, 2, 0 ; PPC64LE-NEXT: lhz 3, 0(3) @@ -91,7 +91,7 @@ define i16 @test7(i16* %ptr) { define i32 @test8(i32* %ptr) { ; PPC64LE-LABEL: test8: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwz 3, 0(3) ; PPC64LE-NEXT: blr %val = load atomic i32, i32* %ptr unordered, align 4 @@ -100,7 +100,7 @@ define i32 @test8(i32* %ptr) { define i32 @test9(i32* %ptr) { ; PPC64LE-LABEL: test9: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwz 3, 0(3) ; PPC64LE-NEXT: blr %val = load atomic i32, i32* %ptr monotonic, align 4 @@ -109,7 +109,7 @@ define i32 @test9(i32* %ptr) { define i32 @test10(i32* %ptr) { ; PPC64LE-LABEL: test10: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwz 3, 0(3) ; PPC64LE-NEXT: cmpd 7, 3, 3 ; PPC64LE-NEXT: bne- 7, .+4 @@ -121,7 +121,7 @@ define i32 @test10(i32* %ptr) { define i32 @test11(i32* %ptr) { ; PPC64LE-LABEL: test11: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: ori 2, 2, 0 ; PPC64LE-NEXT: lwz 3, 0(3) @@ -135,7 +135,7 @@ define i32 @test11(i32* %ptr) { define i64 @test12(i64* %ptr) { ; PPC64LE-LABEL: test12: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: ld 3, 0(3) ; PPC64LE-NEXT: blr %val = load atomic i64, i64* %ptr unordered, align 8 @@ -144,7 +144,7 @@ define i64 @test12(i64* %ptr) { define i64 @test13(i64* %ptr) { ; PPC64LE-LABEL: test13: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: ld 3, 0(3) ; PPC64LE-NEXT: blr %val = load atomic i64, i64* %ptr monotonic, align 8 @@ -153,7 +153,7 @@ define i64 @test13(i64* %ptr) { define i64 @test14(i64* %ptr) { ; PPC64LE-LABEL: test14: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: ld 3, 0(3) ; PPC64LE-NEXT: cmpd 7, 3, 3 ; PPC64LE-NEXT: bne- 7, .+4 @@ -165,7 +165,7 @@ define i64 @test14(i64* %ptr) { define i64 @test15(i64* %ptr) { ; PPC64LE-LABEL: test15: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: ori 2, 2, 0 ; PPC64LE-NEXT: ld 3, 0(3) @@ -179,7 +179,7 @@ define i64 @test15(i64* %ptr) { define void @test16(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test16: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: stb 4, 0(3) ; PPC64LE-NEXT: blr store atomic i8 %val, i8* %ptr unordered, align 1 @@ -188,7 +188,7 @@ define void @test16(i8* %ptr, i8 %val) { define void @test17(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test17: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: stb 4, 0(3) ; PPC64LE-NEXT: blr store atomic i8 %val, i8* %ptr monotonic, align 1 @@ -197,7 +197,7 @@ define void @test17(i8* %ptr, i8 %val) { define void @test18(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test18: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: stb 4, 0(3) ; PPC64LE-NEXT: blr @@ -207,7 +207,7 @@ define void @test18(i8* %ptr, i8 %val) { define void @test19(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test19: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: stb 4, 0(3) ; PPC64LE-NEXT: blr @@ -217,7 +217,7 @@ define void @test19(i8* %ptr, i8 %val) { define void @test20(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test20: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sth 4, 0(3) ; PPC64LE-NEXT: blr store atomic i16 %val, i16* %ptr unordered, align 2 @@ -226,7 +226,7 @@ define void @test20(i16* %ptr, i16 %val) { define void @test21(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test21: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sth 4, 0(3) ; PPC64LE-NEXT: blr store atomic i16 %val, i16* %ptr monotonic, align 2 @@ -235,7 +235,7 @@ define void @test21(i16* %ptr, i16 %val) { define void @test22(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test22: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: sth 4, 0(3) ; PPC64LE-NEXT: blr @@ -245,7 +245,7 @@ define void @test22(i16* %ptr, i16 %val) { define void @test23(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test23: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sth 4, 0(3) ; PPC64LE-NEXT: blr @@ -255,7 +255,7 @@ define void @test23(i16* %ptr, i16 %val) { define void @test24(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test24: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: stw 4, 0(3) ; PPC64LE-NEXT: blr store atomic i32 %val, i32* %ptr unordered, align 4 @@ -264,7 +264,7 @@ define void @test24(i32* %ptr, i32 %val) { define void @test25(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test25: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: stw 4, 0(3) ; PPC64LE-NEXT: blr store atomic i32 %val, i32* %ptr monotonic, align 4 @@ -273,7 +273,7 @@ define void @test25(i32* %ptr, i32 %val) { define void @test26(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test26: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: stw 4, 0(3) ; PPC64LE-NEXT: blr @@ -283,7 +283,7 @@ define void @test26(i32* %ptr, i32 %val) { define void @test27(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test27: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: stw 4, 0(3) ; PPC64LE-NEXT: blr @@ -293,7 +293,7 @@ define void @test27(i32* %ptr, i32 %val) { define void @test28(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test28: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: std 4, 0(3) ; PPC64LE-NEXT: blr store atomic i64 %val, i64* %ptr unordered, align 8 @@ -302,7 +302,7 @@ define void @test28(i64* %ptr, i64 %val) { define void @test29(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test29: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: std 4, 0(3) ; PPC64LE-NEXT: blr store atomic i64 %val, i64* %ptr monotonic, align 8 @@ -311,7 +311,7 @@ define void @test29(i64* %ptr, i64 %val) { define void @test30(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test30: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: std 4, 0(3) ; PPC64LE-NEXT: blr @@ -321,7 +321,7 @@ define void @test30(i64* %ptr, i64 %val) { define void @test31(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test31: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: std 4, 0(3) ; PPC64LE-NEXT: blr @@ -331,7 +331,7 @@ define void @test31(i64* %ptr, i64 %val) { define void @test32() { ; PPC64LE-LABEL: test32: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr fence acquire @@ -340,7 +340,7 @@ define void @test32() { define void @test33() { ; PPC64LE-LABEL: test33: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr fence release @@ -349,7 +349,7 @@ define void @test33() { define void @test34() { ; PPC64LE-LABEL: test34: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr fence acq_rel @@ -358,7 +358,7 @@ define void @test34() { define void @test35() { ; PPC64LE-LABEL: test35: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: blr fence seq_cst @@ -367,7 +367,7 @@ define void @test35() { define void @test36() { ; PPC64LE-LABEL: test36: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr fence syncscope("singlethread") acquire @@ -376,7 +376,7 @@ define void @test36() { define void @test37() { ; PPC64LE-LABEL: test37: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr fence syncscope("singlethread") release @@ -385,7 +385,7 @@ define void @test37() { define void @test38() { ; PPC64LE-LABEL: test38: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr fence syncscope("singlethread") acq_rel @@ -394,7 +394,7 @@ define void @test38() { define void @test39() { ; PPC64LE-LABEL: test39: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: blr fence syncscope("singlethread") seq_cst @@ -403,7 +403,7 @@ define void @test39() { define void @test40(i8* %ptr, i8 %cmp, i8 %val) { ; PPC64LE-LABEL: test40: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: b .LBB40_2 ; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB40_1: @@ -413,7 +413,7 @@ define void @test40(i8* %ptr, i8 %cmp, i8 %val) { ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: beq 0, .LBB40_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: blr %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val monotonic monotonic @@ -422,15 +422,15 @@ define void @test40(i8* %ptr, i8 %cmp, i8 %val) { define void @test41(i8* %ptr, i8 %cmp, i8 %val) { ; PPC64LE-LABEL: test41: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB41_1: ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB41_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB41_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB41_4: @@ -443,15 +443,15 @@ define void @test41(i8* %ptr, i8 %cmp, i8 %val) { define void @test42(i8* %ptr, i8 %cmp, i8 %val) { ; PPC64LE-LABEL: test42: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB42_1: ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB42_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB42_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB42_4: @@ -464,7 +464,7 @@ define void @test42(i8* %ptr, i8 %cmp, i8 %val) { define void @test43(i8* %ptr, i8 %cmp, i8 %val) { ; PPC64LE-LABEL: test43: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: b .LBB43_2 ; PPC64LE-NEXT: .p2align 5 @@ -475,7 +475,7 @@ define void @test43(i8* %ptr, i8 %cmp, i8 %val) { ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: beq 0, .LBB43_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: blr %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val release monotonic @@ -484,7 +484,7 @@ define void @test43(i8* %ptr, i8 %cmp, i8 %val) { define void @test44(i8* %ptr, i8 %cmp, i8 %val) { ; PPC64LE-LABEL: test44: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: b .LBB44_2 ; PPC64LE-NEXT: .p2align 5 @@ -495,7 +495,7 @@ define void @test44(i8* %ptr, i8 %cmp, i8 %val) { ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: beq 0, .LBB44_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: blr %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val release acquire @@ -504,16 +504,16 @@ define void @test44(i8* %ptr, i8 %cmp, i8 %val) { define void @test45(i8* %ptr, i8 %cmp, i8 %val) { ; PPC64LE-LABEL: test45: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB45_1: ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB45_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB45_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB45_4: @@ -526,16 +526,16 @@ define void @test45(i8* %ptr, i8 %cmp, i8 %val) { define void @test46(i8* %ptr, i8 %cmp, i8 %val) { ; PPC64LE-LABEL: test46: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB46_1: ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB46_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB46_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB46_4: @@ -548,16 +548,16 @@ define void @test46(i8* %ptr, i8 %cmp, i8 %val) { define void @test47(i8* %ptr, i8 %cmp, i8 %val) { ; PPC64LE-LABEL: test47: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB47_1: ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB47_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB47_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB47_4: @@ -570,16 +570,16 @@ define void @test47(i8* %ptr, i8 %cmp, i8 %val) { define void @test48(i8* %ptr, i8 %cmp, i8 %val) { ; PPC64LE-LABEL: test48: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB48_1: ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB48_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB48_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB48_4: @@ -592,16 +592,16 @@ define void @test48(i8* %ptr, i8 %cmp, i8 %val) { define void @test49(i8* %ptr, i8 %cmp, i8 %val) { ; PPC64LE-LABEL: test49: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB49_1: ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB49_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB49_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB49_4: @@ -614,7 +614,7 @@ define void @test49(i8* %ptr, i8 %cmp, i8 %val) { define void @test50(i16* %ptr, i16 %cmp, i16 %val) { ; PPC64LE-LABEL: test50: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: b .LBB50_2 ; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB50_1: @@ -624,7 +624,7 @@ define void @test50(i16* %ptr, i16 %cmp, i16 %val) { ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: beq 0, .LBB50_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: blr %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val monotonic monotonic @@ -633,15 +633,15 @@ define void @test50(i16* %ptr, i16 %cmp, i16 %val) { define void @test51(i16* %ptr, i16 %cmp, i16 %val) { ; PPC64LE-LABEL: test51: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB51_1: ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB51_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB51_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB51_4: @@ -654,15 +654,15 @@ define void @test51(i16* %ptr, i16 %cmp, i16 %val) { define void @test52(i16* %ptr, i16 %cmp, i16 %val) { ; PPC64LE-LABEL: test52: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB52_1: ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB52_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB52_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB52_4: @@ -675,7 +675,7 @@ define void @test52(i16* %ptr, i16 %cmp, i16 %val) { define void @test53(i16* %ptr, i16 %cmp, i16 %val) { ; PPC64LE-LABEL: test53: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: b .LBB53_2 ; PPC64LE-NEXT: .p2align 5 @@ -686,7 +686,7 @@ define void @test53(i16* %ptr, i16 %cmp, i16 %val) { ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: beq 0, .LBB53_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: blr %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val release monotonic @@ -695,7 +695,7 @@ define void @test53(i16* %ptr, i16 %cmp, i16 %val) { define void @test54(i16* %ptr, i16 %cmp, i16 %val) { ; PPC64LE-LABEL: test54: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: b .LBB54_2 ; PPC64LE-NEXT: .p2align 5 @@ -706,7 +706,7 @@ define void @test54(i16* %ptr, i16 %cmp, i16 %val) { ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: beq 0, .LBB54_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: blr %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val release acquire @@ -715,16 +715,16 @@ define void @test54(i16* %ptr, i16 %cmp, i16 %val) { define void @test55(i16* %ptr, i16 %cmp, i16 %val) { ; PPC64LE-LABEL: test55: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB55_1: ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB55_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB55_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB55_4: @@ -737,16 +737,16 @@ define void @test55(i16* %ptr, i16 %cmp, i16 %val) { define void @test56(i16* %ptr, i16 %cmp, i16 %val) { ; PPC64LE-LABEL: test56: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB56_1: ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB56_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB56_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB56_4: @@ -759,16 +759,16 @@ define void @test56(i16* %ptr, i16 %cmp, i16 %val) { define void @test57(i16* %ptr, i16 %cmp, i16 %val) { ; PPC64LE-LABEL: test57: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB57_1: ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB57_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB57_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB57_4: @@ -781,16 +781,16 @@ define void @test57(i16* %ptr, i16 %cmp, i16 %val) { define void @test58(i16* %ptr, i16 %cmp, i16 %val) { ; PPC64LE-LABEL: test58: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB58_1: ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB58_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB58_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB58_4: @@ -803,16 +803,16 @@ define void @test58(i16* %ptr, i16 %cmp, i16 %val) { define void @test59(i16* %ptr, i16 %cmp, i16 %val) { ; PPC64LE-LABEL: test59: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB59_1: ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB59_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB59_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB59_4: @@ -825,7 +825,7 @@ define void @test59(i16* %ptr, i16 %cmp, i16 %val) { define void @test60(i32* %ptr, i32 %cmp, i32 %val) { ; PPC64LE-LABEL: test60: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: b .LBB60_2 ; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB60_1: @@ -835,7 +835,7 @@ define void @test60(i32* %ptr, i32 %cmp, i32 %val) { ; PPC64LE-NEXT: lwarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: beq 0, .LBB60_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: blr %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val monotonic monotonic @@ -844,15 +844,15 @@ define void @test60(i32* %ptr, i32 %cmp, i32 %val) { define void @test61(i32* %ptr, i32 %cmp, i32 %val) { ; PPC64LE-LABEL: test61: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB61_1: ; PPC64LE-NEXT: lwarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB61_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB61_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB61_4: @@ -865,15 +865,15 @@ define void @test61(i32* %ptr, i32 %cmp, i32 %val) { define void @test62(i32* %ptr, i32 %cmp, i32 %val) { ; PPC64LE-LABEL: test62: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB62_1: ; PPC64LE-NEXT: lwarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB62_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB62_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB62_4: @@ -886,7 +886,7 @@ define void @test62(i32* %ptr, i32 %cmp, i32 %val) { define void @test63(i32* %ptr, i32 %cmp, i32 %val) { ; PPC64LE-LABEL: test63: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: b .LBB63_2 ; PPC64LE-NEXT: .p2align 5 @@ -897,7 +897,7 @@ define void @test63(i32* %ptr, i32 %cmp, i32 %val) { ; PPC64LE-NEXT: lwarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: beq 0, .LBB63_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: blr %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val release monotonic @@ -906,7 +906,7 @@ define void @test63(i32* %ptr, i32 %cmp, i32 %val) { define void @test64(i32* %ptr, i32 %cmp, i32 %val) { ; PPC64LE-LABEL: test64: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: b .LBB64_2 ; PPC64LE-NEXT: .p2align 5 @@ -917,7 +917,7 @@ define void @test64(i32* %ptr, i32 %cmp, i32 %val) { ; PPC64LE-NEXT: lwarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: beq 0, .LBB64_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: blr %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val release acquire @@ -926,16 +926,16 @@ define void @test64(i32* %ptr, i32 %cmp, i32 %val) { define void @test65(i32* %ptr, i32 %cmp, i32 %val) { ; PPC64LE-LABEL: test65: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB65_1: ; PPC64LE-NEXT: lwarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB65_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB65_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB65_4: @@ -948,16 +948,16 @@ define void @test65(i32* %ptr, i32 %cmp, i32 %val) { define void @test66(i32* %ptr, i32 %cmp, i32 %val) { ; PPC64LE-LABEL: test66: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB66_1: ; PPC64LE-NEXT: lwarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB66_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB66_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB66_4: @@ -970,16 +970,16 @@ define void @test66(i32* %ptr, i32 %cmp, i32 %val) { define void @test67(i32* %ptr, i32 %cmp, i32 %val) { ; PPC64LE-LABEL: test67: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB67_1: ; PPC64LE-NEXT: lwarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB67_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB67_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB67_4: @@ -992,16 +992,16 @@ define void @test67(i32* %ptr, i32 %cmp, i32 %val) { define void @test68(i32* %ptr, i32 %cmp, i32 %val) { ; PPC64LE-LABEL: test68: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB68_1: ; PPC64LE-NEXT: lwarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB68_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB68_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB68_4: @@ -1014,16 +1014,16 @@ define void @test68(i32* %ptr, i32 %cmp, i32 %val) { define void @test69(i32* %ptr, i32 %cmp, i32 %val) { ; PPC64LE-LABEL: test69: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB69_1: ; PPC64LE-NEXT: lwarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB69_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB69_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB69_4: @@ -1036,7 +1036,7 @@ define void @test69(i32* %ptr, i32 %cmp, i32 %val) { define void @test70(i64* %ptr, i64 %cmp, i64 %val) { ; PPC64LE-LABEL: test70: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: b .LBB70_2 ; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB70_1: @@ -1046,7 +1046,7 @@ define void @test70(i64* %ptr, i64 %cmp, i64 %val) { ; PPC64LE-NEXT: ldarx 6, 0, 3 ; PPC64LE-NEXT: cmpd 4, 6 ; PPC64LE-NEXT: beq 0, .LBB70_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: blr %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val monotonic monotonic @@ -1055,15 +1055,15 @@ define void @test70(i64* %ptr, i64 %cmp, i64 %val) { define void @test71(i64* %ptr, i64 %cmp, i64 %val) { ; PPC64LE-LABEL: test71: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB71_1: ; PPC64LE-NEXT: ldarx 6, 0, 3 ; PPC64LE-NEXT: cmpd 4, 6 ; PPC64LE-NEXT: bne 0, .LBB71_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB71_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB71_4: @@ -1076,15 +1076,15 @@ define void @test71(i64* %ptr, i64 %cmp, i64 %val) { define void @test72(i64* %ptr, i64 %cmp, i64 %val) { ; PPC64LE-LABEL: test72: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB72_1: ; PPC64LE-NEXT: ldarx 6, 0, 3 ; PPC64LE-NEXT: cmpd 4, 6 ; PPC64LE-NEXT: bne 0, .LBB72_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB72_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB72_4: @@ -1097,7 +1097,7 @@ define void @test72(i64* %ptr, i64 %cmp, i64 %val) { define void @test73(i64* %ptr, i64 %cmp, i64 %val) { ; PPC64LE-LABEL: test73: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: b .LBB73_2 ; PPC64LE-NEXT: .p2align 5 @@ -1108,7 +1108,7 @@ define void @test73(i64* %ptr, i64 %cmp, i64 %val) { ; PPC64LE-NEXT: ldarx 6, 0, 3 ; PPC64LE-NEXT: cmpd 4, 6 ; PPC64LE-NEXT: beq 0, .LBB73_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: blr %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val release monotonic @@ -1117,7 +1117,7 @@ define void @test73(i64* %ptr, i64 %cmp, i64 %val) { define void @test74(i64* %ptr, i64 %cmp, i64 %val) { ; PPC64LE-LABEL: test74: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: b .LBB74_2 ; PPC64LE-NEXT: .p2align 5 @@ -1128,7 +1128,7 @@ define void @test74(i64* %ptr, i64 %cmp, i64 %val) { ; PPC64LE-NEXT: ldarx 6, 0, 3 ; PPC64LE-NEXT: cmpd 4, 6 ; PPC64LE-NEXT: beq 0, .LBB74_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: blr %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val release acquire @@ -1137,16 +1137,16 @@ define void @test74(i64* %ptr, i64 %cmp, i64 %val) { define void @test75(i64* %ptr, i64 %cmp, i64 %val) { ; PPC64LE-LABEL: test75: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB75_1: ; PPC64LE-NEXT: ldarx 6, 0, 3 ; PPC64LE-NEXT: cmpd 4, 6 ; PPC64LE-NEXT: bne 0, .LBB75_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB75_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB75_4: @@ -1159,16 +1159,16 @@ define void @test75(i64* %ptr, i64 %cmp, i64 %val) { define void @test76(i64* %ptr, i64 %cmp, i64 %val) { ; PPC64LE-LABEL: test76: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB76_1: ; PPC64LE-NEXT: ldarx 6, 0, 3 ; PPC64LE-NEXT: cmpd 4, 6 ; PPC64LE-NEXT: bne 0, .LBB76_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB76_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB76_4: @@ -1181,16 +1181,16 @@ define void @test76(i64* %ptr, i64 %cmp, i64 %val) { define void @test77(i64* %ptr, i64 %cmp, i64 %val) { ; PPC64LE-LABEL: test77: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB77_1: ; PPC64LE-NEXT: ldarx 6, 0, 3 ; PPC64LE-NEXT: cmpd 4, 6 ; PPC64LE-NEXT: bne 0, .LBB77_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB77_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB77_4: @@ -1203,16 +1203,16 @@ define void @test77(i64* %ptr, i64 %cmp, i64 %val) { define void @test78(i64* %ptr, i64 %cmp, i64 %val) { ; PPC64LE-LABEL: test78: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB78_1: ; PPC64LE-NEXT: ldarx 6, 0, 3 ; PPC64LE-NEXT: cmpd 4, 6 ; PPC64LE-NEXT: bne 0, .LBB78_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB78_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB78_4: @@ -1225,16 +1225,16 @@ define void @test78(i64* %ptr, i64 %cmp, i64 %val) { define void @test79(i64* %ptr, i64 %cmp, i64 %val) { ; PPC64LE-LABEL: test79: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB79_1: ; PPC64LE-NEXT: ldarx 6, 0, 3 ; PPC64LE-NEXT: cmpd 4, 6 ; PPC64LE-NEXT: bne 0, .LBB79_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB79_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB79_4: @@ -1247,7 +1247,7 @@ define void @test79(i64* %ptr, i64 %cmp, i64 %val) { define void @test80(i8* %ptr, i8 %cmp, i8 %val) { ; PPC64LE-LABEL: test80: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: b .LBB80_2 ; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB80_1: @@ -1257,7 +1257,7 @@ define void @test80(i8* %ptr, i8 %cmp, i8 %val) { ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: beq 0, .LBB80_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: blr %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") monotonic monotonic @@ -1266,15 +1266,15 @@ define void @test80(i8* %ptr, i8 %cmp, i8 %val) { define void @test81(i8* %ptr, i8 %cmp, i8 %val) { ; PPC64LE-LABEL: test81: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB81_1: ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB81_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB81_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB81_4: @@ -1287,15 +1287,15 @@ define void @test81(i8* %ptr, i8 %cmp, i8 %val) { define void @test82(i8* %ptr, i8 %cmp, i8 %val) { ; PPC64LE-LABEL: test82: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB82_1: ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB82_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB82_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB82_4: @@ -1308,7 +1308,7 @@ define void @test82(i8* %ptr, i8 %cmp, i8 %val) { define void @test83(i8* %ptr, i8 %cmp, i8 %val) { ; PPC64LE-LABEL: test83: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: b .LBB83_2 ; PPC64LE-NEXT: .p2align 5 @@ -1319,7 +1319,7 @@ define void @test83(i8* %ptr, i8 %cmp, i8 %val) { ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: beq 0, .LBB83_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: blr %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") release monotonic @@ -1328,7 +1328,7 @@ define void @test83(i8* %ptr, i8 %cmp, i8 %val) { define void @test84(i8* %ptr, i8 %cmp, i8 %val) { ; PPC64LE-LABEL: test84: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: b .LBB84_2 ; PPC64LE-NEXT: .p2align 5 @@ -1339,7 +1339,7 @@ define void @test84(i8* %ptr, i8 %cmp, i8 %val) { ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: beq 0, .LBB84_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: blr %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") release acquire @@ -1348,16 +1348,16 @@ define void @test84(i8* %ptr, i8 %cmp, i8 %val) { define void @test85(i8* %ptr, i8 %cmp, i8 %val) { ; PPC64LE-LABEL: test85: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB85_1: ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB85_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB85_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB85_4: @@ -1370,16 +1370,16 @@ define void @test85(i8* %ptr, i8 %cmp, i8 %val) { define void @test86(i8* %ptr, i8 %cmp, i8 %val) { ; PPC64LE-LABEL: test86: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB86_1: ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB86_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB86_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB86_4: @@ -1392,16 +1392,16 @@ define void @test86(i8* %ptr, i8 %cmp, i8 %val) { define void @test87(i8* %ptr, i8 %cmp, i8 %val) { ; PPC64LE-LABEL: test87: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB87_1: ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB87_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB87_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB87_4: @@ -1414,16 +1414,16 @@ define void @test87(i8* %ptr, i8 %cmp, i8 %val) { define void @test88(i8* %ptr, i8 %cmp, i8 %val) { ; PPC64LE-LABEL: test88: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB88_1: ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB88_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB88_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB88_4: @@ -1436,16 +1436,16 @@ define void @test88(i8* %ptr, i8 %cmp, i8 %val) { define void @test89(i8* %ptr, i8 %cmp, i8 %val) { ; PPC64LE-LABEL: test89: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB89_1: ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB89_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB89_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB89_4: @@ -1458,7 +1458,7 @@ define void @test89(i8* %ptr, i8 %cmp, i8 %val) { define void @test90(i16* %ptr, i16 %cmp, i16 %val) { ; PPC64LE-LABEL: test90: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: b .LBB90_2 ; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB90_1: @@ -1468,7 +1468,7 @@ define void @test90(i16* %ptr, i16 %cmp, i16 %val) { ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: beq 0, .LBB90_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: blr %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") monotonic monotonic @@ -1477,15 +1477,15 @@ define void @test90(i16* %ptr, i16 %cmp, i16 %val) { define void @test91(i16* %ptr, i16 %cmp, i16 %val) { ; PPC64LE-LABEL: test91: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB91_1: ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB91_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB91_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB91_4: @@ -1498,15 +1498,15 @@ define void @test91(i16* %ptr, i16 %cmp, i16 %val) { define void @test92(i16* %ptr, i16 %cmp, i16 %val) { ; PPC64LE-LABEL: test92: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB92_1: ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB92_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB92_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB92_4: @@ -1519,7 +1519,7 @@ define void @test92(i16* %ptr, i16 %cmp, i16 %val) { define void @test93(i16* %ptr, i16 %cmp, i16 %val) { ; PPC64LE-LABEL: test93: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: b .LBB93_2 ; PPC64LE-NEXT: .p2align 5 @@ -1530,7 +1530,7 @@ define void @test93(i16* %ptr, i16 %cmp, i16 %val) { ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: beq 0, .LBB93_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: blr %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") release monotonic @@ -1539,7 +1539,7 @@ define void @test93(i16* %ptr, i16 %cmp, i16 %val) { define void @test94(i16* %ptr, i16 %cmp, i16 %val) { ; PPC64LE-LABEL: test94: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: b .LBB94_2 ; PPC64LE-NEXT: .p2align 5 @@ -1550,7 +1550,7 @@ define void @test94(i16* %ptr, i16 %cmp, i16 %val) { ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: beq 0, .LBB94_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: blr %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") release acquire @@ -1559,16 +1559,16 @@ define void @test94(i16* %ptr, i16 %cmp, i16 %val) { define void @test95(i16* %ptr, i16 %cmp, i16 %val) { ; PPC64LE-LABEL: test95: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB95_1: ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB95_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB95_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB95_4: @@ -1581,16 +1581,16 @@ define void @test95(i16* %ptr, i16 %cmp, i16 %val) { define void @test96(i16* %ptr, i16 %cmp, i16 %val) { ; PPC64LE-LABEL: test96: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB96_1: ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB96_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB96_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB96_4: @@ -1603,16 +1603,16 @@ define void @test96(i16* %ptr, i16 %cmp, i16 %val) { define void @test97(i16* %ptr, i16 %cmp, i16 %val) { ; PPC64LE-LABEL: test97: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB97_1: ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB97_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB97_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB97_4: @@ -1625,16 +1625,16 @@ define void @test97(i16* %ptr, i16 %cmp, i16 %val) { define void @test98(i16* %ptr, i16 %cmp, i16 %val) { ; PPC64LE-LABEL: test98: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB98_1: ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB98_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB98_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB98_4: @@ -1647,16 +1647,16 @@ define void @test98(i16* %ptr, i16 %cmp, i16 %val) { define void @test99(i16* %ptr, i16 %cmp, i16 %val) { ; PPC64LE-LABEL: test99: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB99_1: ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB99_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB99_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB99_4: @@ -1669,7 +1669,7 @@ define void @test99(i16* %ptr, i16 %cmp, i16 %val) { define void @test100(i32* %ptr, i32 %cmp, i32 %val) { ; PPC64LE-LABEL: test100: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: b .LBB100_2 ; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB100_1: @@ -1679,7 +1679,7 @@ define void @test100(i32* %ptr, i32 %cmp, i32 %val) { ; PPC64LE-NEXT: lwarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: beq 0, .LBB100_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: blr %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val syncscope("singlethread") monotonic monotonic @@ -1688,15 +1688,15 @@ define void @test100(i32* %ptr, i32 %cmp, i32 %val) { define void @test101(i32* %ptr, i32 %cmp, i32 %val) { ; PPC64LE-LABEL: test101: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB101_1: ; PPC64LE-NEXT: lwarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB101_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB101_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB101_4: @@ -1709,15 +1709,15 @@ define void @test101(i32* %ptr, i32 %cmp, i32 %val) { define void @test102(i32* %ptr, i32 %cmp, i32 %val) { ; PPC64LE-LABEL: test102: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB102_1: ; PPC64LE-NEXT: lwarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB102_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB102_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB102_4: @@ -1730,7 +1730,7 @@ define void @test102(i32* %ptr, i32 %cmp, i32 %val) { define void @test103(i32* %ptr, i32 %cmp, i32 %val) { ; PPC64LE-LABEL: test103: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: b .LBB103_2 ; PPC64LE-NEXT: .p2align 5 @@ -1741,7 +1741,7 @@ define void @test103(i32* %ptr, i32 %cmp, i32 %val) { ; PPC64LE-NEXT: lwarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: beq 0, .LBB103_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: blr %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val syncscope("singlethread") release monotonic @@ -1750,7 +1750,7 @@ define void @test103(i32* %ptr, i32 %cmp, i32 %val) { define void @test104(i32* %ptr, i32 %cmp, i32 %val) { ; PPC64LE-LABEL: test104: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: b .LBB104_2 ; PPC64LE-NEXT: .p2align 5 @@ -1761,7 +1761,7 @@ define void @test104(i32* %ptr, i32 %cmp, i32 %val) { ; PPC64LE-NEXT: lwarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: beq 0, .LBB104_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: blr %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val syncscope("singlethread") release acquire @@ -1770,16 +1770,16 @@ define void @test104(i32* %ptr, i32 %cmp, i32 %val) { define void @test105(i32* %ptr, i32 %cmp, i32 %val) { ; PPC64LE-LABEL: test105: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB105_1: ; PPC64LE-NEXT: lwarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB105_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB105_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB105_4: @@ -1792,16 +1792,16 @@ define void @test105(i32* %ptr, i32 %cmp, i32 %val) { define void @test106(i32* %ptr, i32 %cmp, i32 %val) { ; PPC64LE-LABEL: test106: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB106_1: ; PPC64LE-NEXT: lwarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB106_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB106_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB106_4: @@ -1814,16 +1814,16 @@ define void @test106(i32* %ptr, i32 %cmp, i32 %val) { define void @test107(i32* %ptr, i32 %cmp, i32 %val) { ; PPC64LE-LABEL: test107: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB107_1: ; PPC64LE-NEXT: lwarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB107_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB107_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB107_4: @@ -1836,16 +1836,16 @@ define void @test107(i32* %ptr, i32 %cmp, i32 %val) { define void @test108(i32* %ptr, i32 %cmp, i32 %val) { ; PPC64LE-LABEL: test108: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB108_1: ; PPC64LE-NEXT: lwarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB108_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB108_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB108_4: @@ -1858,16 +1858,16 @@ define void @test108(i32* %ptr, i32 %cmp, i32 %val) { define void @test109(i32* %ptr, i32 %cmp, i32 %val) { ; PPC64LE-LABEL: test109: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB109_1: ; PPC64LE-NEXT: lwarx 6, 0, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bne 0, .LBB109_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB109_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB109_4: @@ -1880,7 +1880,7 @@ define void @test109(i32* %ptr, i32 %cmp, i32 %val) { define void @test110(i64* %ptr, i64 %cmp, i64 %val) { ; PPC64LE-LABEL: test110: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: b .LBB110_2 ; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB110_1: @@ -1890,7 +1890,7 @@ define void @test110(i64* %ptr, i64 %cmp, i64 %val) { ; PPC64LE-NEXT: ldarx 6, 0, 3 ; PPC64LE-NEXT: cmpd 4, 6 ; PPC64LE-NEXT: beq 0, .LBB110_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: blr %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val syncscope("singlethread") monotonic monotonic @@ -1899,15 +1899,15 @@ define void @test110(i64* %ptr, i64 %cmp, i64 %val) { define void @test111(i64* %ptr, i64 %cmp, i64 %val) { ; PPC64LE-LABEL: test111: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB111_1: ; PPC64LE-NEXT: ldarx 6, 0, 3 ; PPC64LE-NEXT: cmpd 4, 6 ; PPC64LE-NEXT: bne 0, .LBB111_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB111_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB111_4: @@ -1920,15 +1920,15 @@ define void @test111(i64* %ptr, i64 %cmp, i64 %val) { define void @test112(i64* %ptr, i64 %cmp, i64 %val) { ; PPC64LE-LABEL: test112: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB112_1: ; PPC64LE-NEXT: ldarx 6, 0, 3 ; PPC64LE-NEXT: cmpd 4, 6 ; PPC64LE-NEXT: bne 0, .LBB112_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB112_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB112_4: @@ -1941,7 +1941,7 @@ define void @test112(i64* %ptr, i64 %cmp, i64 %val) { define void @test113(i64* %ptr, i64 %cmp, i64 %val) { ; PPC64LE-LABEL: test113: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: b .LBB113_2 ; PPC64LE-NEXT: .p2align 5 @@ -1952,7 +1952,7 @@ define void @test113(i64* %ptr, i64 %cmp, i64 %val) { ; PPC64LE-NEXT: ldarx 6, 0, 3 ; PPC64LE-NEXT: cmpd 4, 6 ; PPC64LE-NEXT: beq 0, .LBB113_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: blr %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val syncscope("singlethread") release monotonic @@ -1961,7 +1961,7 @@ define void @test113(i64* %ptr, i64 %cmp, i64 %val) { define void @test114(i64* %ptr, i64 %cmp, i64 %val) { ; PPC64LE-LABEL: test114: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: b .LBB114_2 ; PPC64LE-NEXT: .p2align 5 @@ -1972,7 +1972,7 @@ define void @test114(i64* %ptr, i64 %cmp, i64 %val) { ; PPC64LE-NEXT: ldarx 6, 0, 3 ; PPC64LE-NEXT: cmpd 4, 6 ; PPC64LE-NEXT: beq 0, .LBB114_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: blr %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val syncscope("singlethread") release acquire @@ -1981,16 +1981,16 @@ define void @test114(i64* %ptr, i64 %cmp, i64 %val) { define void @test115(i64* %ptr, i64 %cmp, i64 %val) { ; PPC64LE-LABEL: test115: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB115_1: ; PPC64LE-NEXT: ldarx 6, 0, 3 ; PPC64LE-NEXT: cmpd 4, 6 ; PPC64LE-NEXT: bne 0, .LBB115_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB115_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB115_4: @@ -2003,16 +2003,16 @@ define void @test115(i64* %ptr, i64 %cmp, i64 %val) { define void @test116(i64* %ptr, i64 %cmp, i64 %val) { ; PPC64LE-LABEL: test116: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB116_1: ; PPC64LE-NEXT: ldarx 6, 0, 3 ; PPC64LE-NEXT: cmpd 4, 6 ; PPC64LE-NEXT: bne 0, .LBB116_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB116_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB116_4: @@ -2025,16 +2025,16 @@ define void @test116(i64* %ptr, i64 %cmp, i64 %val) { define void @test117(i64* %ptr, i64 %cmp, i64 %val) { ; PPC64LE-LABEL: test117: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB117_1: ; PPC64LE-NEXT: ldarx 6, 0, 3 ; PPC64LE-NEXT: cmpd 4, 6 ; PPC64LE-NEXT: bne 0, .LBB117_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB117_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB117_4: @@ -2047,16 +2047,16 @@ define void @test117(i64* %ptr, i64 %cmp, i64 %val) { define void @test118(i64* %ptr, i64 %cmp, i64 %val) { ; PPC64LE-LABEL: test118: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB118_1: ; PPC64LE-NEXT: ldarx 6, 0, 3 ; PPC64LE-NEXT: cmpd 4, 6 ; PPC64LE-NEXT: bne 0, .LBB118_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB118_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB118_4: @@ -2069,16 +2069,16 @@ define void @test118(i64* %ptr, i64 %cmp, i64 %val) { define void @test119(i64* %ptr, i64 %cmp, i64 %val) { ; PPC64LE-LABEL: test119: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB119_1: ; PPC64LE-NEXT: ldarx 6, 0, 3 ; PPC64LE-NEXT: cmpd 4, 6 ; PPC64LE-NEXT: bne 0, .LBB119_4 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 5, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB119_1 -; PPC64LE-NEXT: # BB#3: +; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr ; PPC64LE-NEXT: .LBB119_4: @@ -2091,12 +2091,12 @@ define void @test119(i64* %ptr, i64 %cmp, i64 %val) { define i8 @test120(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test120: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB120_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB120_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw xchg i8* %ptr, i8 %val monotonic @@ -2105,13 +2105,13 @@ define i8 @test120(i8* %ptr, i8 %val) { define i8 @test121(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test121: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB121_1: ; PPC64LE-NEXT: lbarx 3, 0, 5 ; PPC64LE-NEXT: stbcx. 4, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB121_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw xchg i8* %ptr, i8 %val acquire @@ -2120,13 +2120,13 @@ define i8 @test121(i8* %ptr, i8 %val) { define i8 @test122(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test122: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB122_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB122_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw xchg i8* %ptr, i8 %val release @@ -2135,13 +2135,13 @@ define i8 @test122(i8* %ptr, i8 %val) { define i8 @test123(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test123: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB123_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB123_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -2151,13 +2151,13 @@ define i8 @test123(i8* %ptr, i8 %val) { define i8 @test124(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test124: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB124_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB124_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -2167,12 +2167,12 @@ define i8 @test124(i8* %ptr, i8 %val) { define i16 @test125(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test125: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB125_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB125_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw xchg i16* %ptr, i16 %val monotonic @@ -2181,13 +2181,13 @@ define i16 @test125(i16* %ptr, i16 %val) { define i16 @test126(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test126: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB126_1: ; PPC64LE-NEXT: lharx 3, 0, 5 ; PPC64LE-NEXT: sthcx. 4, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB126_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw xchg i16* %ptr, i16 %val acquire @@ -2196,13 +2196,13 @@ define i16 @test126(i16* %ptr, i16 %val) { define i16 @test127(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test127: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB127_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB127_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw xchg i16* %ptr, i16 %val release @@ -2211,13 +2211,13 @@ define i16 @test127(i16* %ptr, i16 %val) { define i16 @test128(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test128: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB128_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB128_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -2227,13 +2227,13 @@ define i16 @test128(i16* %ptr, i16 %val) { define i16 @test129(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test129: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB129_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB129_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -2243,12 +2243,12 @@ define i16 @test129(i16* %ptr, i16 %val) { define i32 @test130(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test130: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB130_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB130_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw xchg i32* %ptr, i32 %val monotonic @@ -2257,13 +2257,13 @@ define i32 @test130(i32* %ptr, i32 %val) { define i32 @test131(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test131: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB131_1: ; PPC64LE-NEXT: lwarx 3, 0, 5 ; PPC64LE-NEXT: stwcx. 4, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB131_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw xchg i32* %ptr, i32 %val acquire @@ -2272,13 +2272,13 @@ define i32 @test131(i32* %ptr, i32 %val) { define i32 @test132(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test132: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB132_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB132_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw xchg i32* %ptr, i32 %val release @@ -2287,13 +2287,13 @@ define i32 @test132(i32* %ptr, i32 %val) { define i32 @test133(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test133: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB133_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB133_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -2303,13 +2303,13 @@ define i32 @test133(i32* %ptr, i32 %val) { define i32 @test134(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test134: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB134_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB134_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -2319,12 +2319,12 @@ define i32 @test134(i32* %ptr, i32 %val) { define i64 @test135(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test135: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB135_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB135_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw xchg i64* %ptr, i64 %val monotonic @@ -2333,13 +2333,13 @@ define i64 @test135(i64* %ptr, i64 %val) { define i64 @test136(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test136: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB136_1: ; PPC64LE-NEXT: ldarx 3, 0, 5 ; PPC64LE-NEXT: stdcx. 4, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB136_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw xchg i64* %ptr, i64 %val acquire @@ -2348,13 +2348,13 @@ define i64 @test136(i64* %ptr, i64 %val) { define i64 @test137(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test137: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB137_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB137_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw xchg i64* %ptr, i64 %val release @@ -2363,13 +2363,13 @@ define i64 @test137(i64* %ptr, i64 %val) { define i64 @test138(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test138: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB138_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB138_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -2379,13 +2379,13 @@ define i64 @test138(i64* %ptr, i64 %val) { define i64 @test139(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test139: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB139_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB139_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -2395,13 +2395,13 @@ define i64 @test139(i64* %ptr, i64 %val) { define i8 @test140(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test140: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB140_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB140_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw add i8* %ptr, i8 %val monotonic @@ -2410,14 +2410,14 @@ define i8 @test140(i8* %ptr, i8 %val) { define i8 @test141(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test141: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB141_1: ; PPC64LE-NEXT: lbarx 3, 0, 5 ; PPC64LE-NEXT: add 6, 4, 3 ; PPC64LE-NEXT: stbcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB141_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw add i8* %ptr, i8 %val acquire @@ -2426,14 +2426,14 @@ define i8 @test141(i8* %ptr, i8 %val) { define i8 @test142(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test142: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB142_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB142_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw add i8* %ptr, i8 %val release @@ -2442,14 +2442,14 @@ define i8 @test142(i8* %ptr, i8 %val) { define i8 @test143(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test143: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB143_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB143_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -2459,14 +2459,14 @@ define i8 @test143(i8* %ptr, i8 %val) { define i8 @test144(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test144: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB144_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB144_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -2476,13 +2476,13 @@ define i8 @test144(i8* %ptr, i8 %val) { define i16 @test145(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test145: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB145_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB145_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw add i16* %ptr, i16 %val monotonic @@ -2491,14 +2491,14 @@ define i16 @test145(i16* %ptr, i16 %val) { define i16 @test146(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test146: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB146_1: ; PPC64LE-NEXT: lharx 3, 0, 5 ; PPC64LE-NEXT: add 6, 4, 3 ; PPC64LE-NEXT: sthcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB146_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw add i16* %ptr, i16 %val acquire @@ -2507,14 +2507,14 @@ define i16 @test146(i16* %ptr, i16 %val) { define i16 @test147(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test147: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB147_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB147_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw add i16* %ptr, i16 %val release @@ -2523,14 +2523,14 @@ define i16 @test147(i16* %ptr, i16 %val) { define i16 @test148(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test148: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB148_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB148_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -2540,14 +2540,14 @@ define i16 @test148(i16* %ptr, i16 %val) { define i16 @test149(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test149: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB149_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB149_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -2557,13 +2557,13 @@ define i16 @test149(i16* %ptr, i16 %val) { define i32 @test150(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test150: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB150_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB150_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw add i32* %ptr, i32 %val monotonic @@ -2572,14 +2572,14 @@ define i32 @test150(i32* %ptr, i32 %val) { define i32 @test151(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test151: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB151_1: ; PPC64LE-NEXT: lwarx 3, 0, 5 ; PPC64LE-NEXT: add 6, 4, 3 ; PPC64LE-NEXT: stwcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB151_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw add i32* %ptr, i32 %val acquire @@ -2588,14 +2588,14 @@ define i32 @test151(i32* %ptr, i32 %val) { define i32 @test152(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test152: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB152_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB152_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw add i32* %ptr, i32 %val release @@ -2604,14 +2604,14 @@ define i32 @test152(i32* %ptr, i32 %val) { define i32 @test153(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test153: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB153_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB153_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -2621,14 +2621,14 @@ define i32 @test153(i32* %ptr, i32 %val) { define i32 @test154(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test154: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB154_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB154_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -2638,13 +2638,13 @@ define i32 @test154(i32* %ptr, i32 %val) { define i64 @test155(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test155: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB155_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB155_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw add i64* %ptr, i64 %val monotonic @@ -2653,14 +2653,14 @@ define i64 @test155(i64* %ptr, i64 %val) { define i64 @test156(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test156: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB156_1: ; PPC64LE-NEXT: ldarx 3, 0, 5 ; PPC64LE-NEXT: add 6, 4, 3 ; PPC64LE-NEXT: stdcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB156_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw add i64* %ptr, i64 %val acquire @@ -2669,14 +2669,14 @@ define i64 @test156(i64* %ptr, i64 %val) { define i64 @test157(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test157: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB157_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB157_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw add i64* %ptr, i64 %val release @@ -2685,14 +2685,14 @@ define i64 @test157(i64* %ptr, i64 %val) { define i64 @test158(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test158: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB158_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB158_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -2702,14 +2702,14 @@ define i64 @test158(i64* %ptr, i64 %val) { define i64 @test159(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test159: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB159_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB159_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -2719,13 +2719,13 @@ define i64 @test159(i64* %ptr, i64 %val) { define i8 @test160(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test160: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB160_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: subf 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB160_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw sub i8* %ptr, i8 %val monotonic @@ -2734,14 +2734,14 @@ define i8 @test160(i8* %ptr, i8 %val) { define i8 @test161(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test161: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB161_1: ; PPC64LE-NEXT: lbarx 3, 0, 5 ; PPC64LE-NEXT: subf 6, 4, 3 ; PPC64LE-NEXT: stbcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB161_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw sub i8* %ptr, i8 %val acquire @@ -2750,14 +2750,14 @@ define i8 @test161(i8* %ptr, i8 %val) { define i8 @test162(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test162: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB162_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: subf 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB162_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw sub i8* %ptr, i8 %val release @@ -2766,14 +2766,14 @@ define i8 @test162(i8* %ptr, i8 %val) { define i8 @test163(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test163: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB163_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: subf 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB163_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -2783,14 +2783,14 @@ define i8 @test163(i8* %ptr, i8 %val) { define i8 @test164(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test164: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB164_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: subf 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB164_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -2800,13 +2800,13 @@ define i8 @test164(i8* %ptr, i8 %val) { define i16 @test165(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test165: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB165_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: subf 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB165_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw sub i16* %ptr, i16 %val monotonic @@ -2815,14 +2815,14 @@ define i16 @test165(i16* %ptr, i16 %val) { define i16 @test166(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test166: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB166_1: ; PPC64LE-NEXT: lharx 3, 0, 5 ; PPC64LE-NEXT: subf 6, 4, 3 ; PPC64LE-NEXT: sthcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB166_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw sub i16* %ptr, i16 %val acquire @@ -2831,14 +2831,14 @@ define i16 @test166(i16* %ptr, i16 %val) { define i16 @test167(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test167: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB167_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: subf 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB167_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw sub i16* %ptr, i16 %val release @@ -2847,14 +2847,14 @@ define i16 @test167(i16* %ptr, i16 %val) { define i16 @test168(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test168: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB168_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: subf 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB168_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -2864,14 +2864,14 @@ define i16 @test168(i16* %ptr, i16 %val) { define i16 @test169(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test169: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB169_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: subf 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB169_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -2881,13 +2881,13 @@ define i16 @test169(i16* %ptr, i16 %val) { define i32 @test170(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test170: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB170_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: subf 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB170_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw sub i32* %ptr, i32 %val monotonic @@ -2896,14 +2896,14 @@ define i32 @test170(i32* %ptr, i32 %val) { define i32 @test171(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test171: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB171_1: ; PPC64LE-NEXT: lwarx 3, 0, 5 ; PPC64LE-NEXT: subf 6, 4, 3 ; PPC64LE-NEXT: stwcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB171_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw sub i32* %ptr, i32 %val acquire @@ -2912,14 +2912,14 @@ define i32 @test171(i32* %ptr, i32 %val) { define i32 @test172(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test172: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB172_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: subf 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB172_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw sub i32* %ptr, i32 %val release @@ -2928,14 +2928,14 @@ define i32 @test172(i32* %ptr, i32 %val) { define i32 @test173(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test173: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB173_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: subf 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB173_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -2945,14 +2945,14 @@ define i32 @test173(i32* %ptr, i32 %val) { define i32 @test174(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test174: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB174_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: subf 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB174_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -2962,13 +2962,13 @@ define i32 @test174(i32* %ptr, i32 %val) { define i64 @test175(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test175: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB175_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: sub 6, 5, 4 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB175_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw sub i64* %ptr, i64 %val monotonic @@ -2977,14 +2977,14 @@ define i64 @test175(i64* %ptr, i64 %val) { define i64 @test176(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test176: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB176_1: ; PPC64LE-NEXT: ldarx 3, 0, 5 ; PPC64LE-NEXT: sub 6, 3, 4 ; PPC64LE-NEXT: stdcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB176_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw sub i64* %ptr, i64 %val acquire @@ -2993,14 +2993,14 @@ define i64 @test176(i64* %ptr, i64 %val) { define i64 @test177(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test177: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB177_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: sub 6, 5, 4 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB177_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw sub i64* %ptr, i64 %val release @@ -3009,14 +3009,14 @@ define i64 @test177(i64* %ptr, i64 %val) { define i64 @test178(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test178: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB178_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: sub 6, 5, 4 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB178_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -3026,14 +3026,14 @@ define i64 @test178(i64* %ptr, i64 %val) { define i64 @test179(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test179: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB179_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: sub 6, 5, 4 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB179_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -3043,13 +3043,13 @@ define i64 @test179(i64* %ptr, i64 %val) { define i8 @test180(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test180: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB180_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB180_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw and i8* %ptr, i8 %val monotonic @@ -3058,14 +3058,14 @@ define i8 @test180(i8* %ptr, i8 %val) { define i8 @test181(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test181: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB181_1: ; PPC64LE-NEXT: lbarx 3, 0, 5 ; PPC64LE-NEXT: and 6, 4, 3 ; PPC64LE-NEXT: stbcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB181_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw and i8* %ptr, i8 %val acquire @@ -3074,14 +3074,14 @@ define i8 @test181(i8* %ptr, i8 %val) { define i8 @test182(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test182: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB182_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB182_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw and i8* %ptr, i8 %val release @@ -3090,14 +3090,14 @@ define i8 @test182(i8* %ptr, i8 %val) { define i8 @test183(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test183: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB183_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB183_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -3107,14 +3107,14 @@ define i8 @test183(i8* %ptr, i8 %val) { define i8 @test184(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test184: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB184_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB184_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -3124,13 +3124,13 @@ define i8 @test184(i8* %ptr, i8 %val) { define i16 @test185(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test185: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB185_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB185_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw and i16* %ptr, i16 %val monotonic @@ -3139,14 +3139,14 @@ define i16 @test185(i16* %ptr, i16 %val) { define i16 @test186(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test186: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB186_1: ; PPC64LE-NEXT: lharx 3, 0, 5 ; PPC64LE-NEXT: and 6, 4, 3 ; PPC64LE-NEXT: sthcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB186_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw and i16* %ptr, i16 %val acquire @@ -3155,14 +3155,14 @@ define i16 @test186(i16* %ptr, i16 %val) { define i16 @test187(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test187: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB187_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB187_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw and i16* %ptr, i16 %val release @@ -3171,14 +3171,14 @@ define i16 @test187(i16* %ptr, i16 %val) { define i16 @test188(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test188: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB188_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB188_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -3188,14 +3188,14 @@ define i16 @test188(i16* %ptr, i16 %val) { define i16 @test189(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test189: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB189_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB189_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -3205,13 +3205,13 @@ define i16 @test189(i16* %ptr, i16 %val) { define i32 @test190(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test190: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB190_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB190_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw and i32* %ptr, i32 %val monotonic @@ -3220,14 +3220,14 @@ define i32 @test190(i32* %ptr, i32 %val) { define i32 @test191(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test191: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB191_1: ; PPC64LE-NEXT: lwarx 3, 0, 5 ; PPC64LE-NEXT: and 6, 4, 3 ; PPC64LE-NEXT: stwcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB191_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw and i32* %ptr, i32 %val acquire @@ -3236,14 +3236,14 @@ define i32 @test191(i32* %ptr, i32 %val) { define i32 @test192(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test192: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB192_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB192_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw and i32* %ptr, i32 %val release @@ -3252,14 +3252,14 @@ define i32 @test192(i32* %ptr, i32 %val) { define i32 @test193(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test193: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB193_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB193_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -3269,14 +3269,14 @@ define i32 @test193(i32* %ptr, i32 %val) { define i32 @test194(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test194: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB194_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB194_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -3286,13 +3286,13 @@ define i32 @test194(i32* %ptr, i32 %val) { define i64 @test195(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test195: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB195_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB195_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw and i64* %ptr, i64 %val monotonic @@ -3301,14 +3301,14 @@ define i64 @test195(i64* %ptr, i64 %val) { define i64 @test196(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test196: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB196_1: ; PPC64LE-NEXT: ldarx 3, 0, 5 ; PPC64LE-NEXT: and 6, 4, 3 ; PPC64LE-NEXT: stdcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB196_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw and i64* %ptr, i64 %val acquire @@ -3317,14 +3317,14 @@ define i64 @test196(i64* %ptr, i64 %val) { define i64 @test197(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test197: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB197_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB197_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw and i64* %ptr, i64 %val release @@ -3333,14 +3333,14 @@ define i64 @test197(i64* %ptr, i64 %val) { define i64 @test198(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test198: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB198_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB198_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -3350,14 +3350,14 @@ define i64 @test198(i64* %ptr, i64 %val) { define i64 @test199(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test199: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB199_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB199_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -3367,13 +3367,13 @@ define i64 @test199(i64* %ptr, i64 %val) { define i8 @test200(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test200: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB200_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB200_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw nand i8* %ptr, i8 %val monotonic @@ -3382,14 +3382,14 @@ define i8 @test200(i8* %ptr, i8 %val) { define i8 @test201(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test201: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB201_1: ; PPC64LE-NEXT: lbarx 3, 0, 5 ; PPC64LE-NEXT: nand 6, 4, 3 ; PPC64LE-NEXT: stbcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB201_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw nand i8* %ptr, i8 %val acquire @@ -3398,14 +3398,14 @@ define i8 @test201(i8* %ptr, i8 %val) { define i8 @test202(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test202: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB202_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB202_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw nand i8* %ptr, i8 %val release @@ -3414,14 +3414,14 @@ define i8 @test202(i8* %ptr, i8 %val) { define i8 @test203(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test203: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB203_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB203_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -3431,14 +3431,14 @@ define i8 @test203(i8* %ptr, i8 %val) { define i8 @test204(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test204: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB204_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB204_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -3448,13 +3448,13 @@ define i8 @test204(i8* %ptr, i8 %val) { define i16 @test205(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test205: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB205_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB205_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw nand i16* %ptr, i16 %val monotonic @@ -3463,14 +3463,14 @@ define i16 @test205(i16* %ptr, i16 %val) { define i16 @test206(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test206: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB206_1: ; PPC64LE-NEXT: lharx 3, 0, 5 ; PPC64LE-NEXT: nand 6, 4, 3 ; PPC64LE-NEXT: sthcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB206_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw nand i16* %ptr, i16 %val acquire @@ -3479,14 +3479,14 @@ define i16 @test206(i16* %ptr, i16 %val) { define i16 @test207(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test207: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB207_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB207_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw nand i16* %ptr, i16 %val release @@ -3495,14 +3495,14 @@ define i16 @test207(i16* %ptr, i16 %val) { define i16 @test208(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test208: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB208_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB208_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -3512,14 +3512,14 @@ define i16 @test208(i16* %ptr, i16 %val) { define i16 @test209(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test209: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB209_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB209_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -3529,13 +3529,13 @@ define i16 @test209(i16* %ptr, i16 %val) { define i32 @test210(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test210: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB210_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB210_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw nand i32* %ptr, i32 %val monotonic @@ -3544,14 +3544,14 @@ define i32 @test210(i32* %ptr, i32 %val) { define i32 @test211(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test211: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB211_1: ; PPC64LE-NEXT: lwarx 3, 0, 5 ; PPC64LE-NEXT: nand 6, 4, 3 ; PPC64LE-NEXT: stwcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB211_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw nand i32* %ptr, i32 %val acquire @@ -3560,14 +3560,14 @@ define i32 @test211(i32* %ptr, i32 %val) { define i32 @test212(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test212: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB212_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB212_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw nand i32* %ptr, i32 %val release @@ -3576,14 +3576,14 @@ define i32 @test212(i32* %ptr, i32 %val) { define i32 @test213(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test213: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB213_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB213_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -3593,14 +3593,14 @@ define i32 @test213(i32* %ptr, i32 %val) { define i32 @test214(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test214: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB214_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB214_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -3610,13 +3610,13 @@ define i32 @test214(i32* %ptr, i32 %val) { define i64 @test215(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test215: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB215_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB215_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw nand i64* %ptr, i64 %val monotonic @@ -3625,14 +3625,14 @@ define i64 @test215(i64* %ptr, i64 %val) { define i64 @test216(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test216: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB216_1: ; PPC64LE-NEXT: ldarx 3, 0, 5 ; PPC64LE-NEXT: nand 6, 4, 3 ; PPC64LE-NEXT: stdcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB216_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw nand i64* %ptr, i64 %val acquire @@ -3641,14 +3641,14 @@ define i64 @test216(i64* %ptr, i64 %val) { define i64 @test217(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test217: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB217_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB217_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw nand i64* %ptr, i64 %val release @@ -3657,14 +3657,14 @@ define i64 @test217(i64* %ptr, i64 %val) { define i64 @test218(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test218: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB218_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB218_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -3674,14 +3674,14 @@ define i64 @test218(i64* %ptr, i64 %val) { define i64 @test219(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test219: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB219_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB219_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -3691,13 +3691,13 @@ define i64 @test219(i64* %ptr, i64 %val) { define i8 @test220(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test220: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB220_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB220_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw or i8* %ptr, i8 %val monotonic @@ -3706,14 +3706,14 @@ define i8 @test220(i8* %ptr, i8 %val) { define i8 @test221(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test221: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB221_1: ; PPC64LE-NEXT: lbarx 3, 0, 5 ; PPC64LE-NEXT: or 6, 4, 3 ; PPC64LE-NEXT: stbcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB221_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw or i8* %ptr, i8 %val acquire @@ -3722,14 +3722,14 @@ define i8 @test221(i8* %ptr, i8 %val) { define i8 @test222(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test222: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB222_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB222_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw or i8* %ptr, i8 %val release @@ -3738,14 +3738,14 @@ define i8 @test222(i8* %ptr, i8 %val) { define i8 @test223(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test223: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB223_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB223_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -3755,14 +3755,14 @@ define i8 @test223(i8* %ptr, i8 %val) { define i8 @test224(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test224: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB224_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB224_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -3772,13 +3772,13 @@ define i8 @test224(i8* %ptr, i8 %val) { define i16 @test225(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test225: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB225_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB225_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw or i16* %ptr, i16 %val monotonic @@ -3787,14 +3787,14 @@ define i16 @test225(i16* %ptr, i16 %val) { define i16 @test226(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test226: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB226_1: ; PPC64LE-NEXT: lharx 3, 0, 5 ; PPC64LE-NEXT: or 6, 4, 3 ; PPC64LE-NEXT: sthcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB226_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw or i16* %ptr, i16 %val acquire @@ -3803,14 +3803,14 @@ define i16 @test226(i16* %ptr, i16 %val) { define i16 @test227(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test227: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB227_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB227_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw or i16* %ptr, i16 %val release @@ -3819,14 +3819,14 @@ define i16 @test227(i16* %ptr, i16 %val) { define i16 @test228(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test228: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB228_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB228_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -3836,14 +3836,14 @@ define i16 @test228(i16* %ptr, i16 %val) { define i16 @test229(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test229: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB229_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB229_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -3853,13 +3853,13 @@ define i16 @test229(i16* %ptr, i16 %val) { define i32 @test230(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test230: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB230_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB230_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw or i32* %ptr, i32 %val monotonic @@ -3868,14 +3868,14 @@ define i32 @test230(i32* %ptr, i32 %val) { define i32 @test231(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test231: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB231_1: ; PPC64LE-NEXT: lwarx 3, 0, 5 ; PPC64LE-NEXT: or 6, 4, 3 ; PPC64LE-NEXT: stwcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB231_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw or i32* %ptr, i32 %val acquire @@ -3884,14 +3884,14 @@ define i32 @test231(i32* %ptr, i32 %val) { define i32 @test232(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test232: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB232_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB232_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw or i32* %ptr, i32 %val release @@ -3900,14 +3900,14 @@ define i32 @test232(i32* %ptr, i32 %val) { define i32 @test233(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test233: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB233_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB233_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -3917,14 +3917,14 @@ define i32 @test233(i32* %ptr, i32 %val) { define i32 @test234(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test234: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB234_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB234_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -3934,13 +3934,13 @@ define i32 @test234(i32* %ptr, i32 %val) { define i64 @test235(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test235: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB235_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB235_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw or i64* %ptr, i64 %val monotonic @@ -3949,14 +3949,14 @@ define i64 @test235(i64* %ptr, i64 %val) { define i64 @test236(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test236: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB236_1: ; PPC64LE-NEXT: ldarx 3, 0, 5 ; PPC64LE-NEXT: or 6, 4, 3 ; PPC64LE-NEXT: stdcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB236_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw or i64* %ptr, i64 %val acquire @@ -3965,14 +3965,14 @@ define i64 @test236(i64* %ptr, i64 %val) { define i64 @test237(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test237: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB237_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB237_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw or i64* %ptr, i64 %val release @@ -3981,14 +3981,14 @@ define i64 @test237(i64* %ptr, i64 %val) { define i64 @test238(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test238: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB238_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB238_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -3998,14 +3998,14 @@ define i64 @test238(i64* %ptr, i64 %val) { define i64 @test239(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test239: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB239_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB239_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -4015,13 +4015,13 @@ define i64 @test239(i64* %ptr, i64 %val) { define i8 @test240(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test240: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB240_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB240_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw xor i8* %ptr, i8 %val monotonic @@ -4030,14 +4030,14 @@ define i8 @test240(i8* %ptr, i8 %val) { define i8 @test241(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test241: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB241_1: ; PPC64LE-NEXT: lbarx 3, 0, 5 ; PPC64LE-NEXT: xor 6, 4, 3 ; PPC64LE-NEXT: stbcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB241_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw xor i8* %ptr, i8 %val acquire @@ -4046,14 +4046,14 @@ define i8 @test241(i8* %ptr, i8 %val) { define i8 @test242(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test242: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB242_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB242_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw xor i8* %ptr, i8 %val release @@ -4062,14 +4062,14 @@ define i8 @test242(i8* %ptr, i8 %val) { define i8 @test243(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test243: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB243_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB243_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -4079,14 +4079,14 @@ define i8 @test243(i8* %ptr, i8 %val) { define i8 @test244(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test244: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB244_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB244_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -4096,13 +4096,13 @@ define i8 @test244(i8* %ptr, i8 %val) { define i16 @test245(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test245: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB245_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB245_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw xor i16* %ptr, i16 %val monotonic @@ -4111,14 +4111,14 @@ define i16 @test245(i16* %ptr, i16 %val) { define i16 @test246(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test246: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB246_1: ; PPC64LE-NEXT: lharx 3, 0, 5 ; PPC64LE-NEXT: xor 6, 4, 3 ; PPC64LE-NEXT: sthcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB246_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw xor i16* %ptr, i16 %val acquire @@ -4127,14 +4127,14 @@ define i16 @test246(i16* %ptr, i16 %val) { define i16 @test247(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test247: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB247_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB247_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw xor i16* %ptr, i16 %val release @@ -4143,14 +4143,14 @@ define i16 @test247(i16* %ptr, i16 %val) { define i16 @test248(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test248: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB248_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB248_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -4160,14 +4160,14 @@ define i16 @test248(i16* %ptr, i16 %val) { define i16 @test249(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test249: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB249_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB249_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -4177,13 +4177,13 @@ define i16 @test249(i16* %ptr, i16 %val) { define i32 @test250(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test250: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB250_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB250_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw xor i32* %ptr, i32 %val monotonic @@ -4192,14 +4192,14 @@ define i32 @test250(i32* %ptr, i32 %val) { define i32 @test251(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test251: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB251_1: ; PPC64LE-NEXT: lwarx 3, 0, 5 ; PPC64LE-NEXT: xor 6, 4, 3 ; PPC64LE-NEXT: stwcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB251_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw xor i32* %ptr, i32 %val acquire @@ -4208,14 +4208,14 @@ define i32 @test251(i32* %ptr, i32 %val) { define i32 @test252(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test252: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB252_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB252_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw xor i32* %ptr, i32 %val release @@ -4224,14 +4224,14 @@ define i32 @test252(i32* %ptr, i32 %val) { define i32 @test253(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test253: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB253_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB253_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -4241,14 +4241,14 @@ define i32 @test253(i32* %ptr, i32 %val) { define i32 @test254(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test254: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB254_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB254_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -4258,13 +4258,13 @@ define i32 @test254(i32* %ptr, i32 %val) { define i64 @test255(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test255: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB255_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB255_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw xor i64* %ptr, i64 %val monotonic @@ -4273,14 +4273,14 @@ define i64 @test255(i64* %ptr, i64 %val) { define i64 @test256(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test256: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB256_1: ; PPC64LE-NEXT: ldarx 3, 0, 5 ; PPC64LE-NEXT: xor 6, 4, 3 ; PPC64LE-NEXT: stdcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB256_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw xor i64* %ptr, i64 %val acquire @@ -4289,14 +4289,14 @@ define i64 @test256(i64* %ptr, i64 %val) { define i64 @test257(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test257: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB257_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB257_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw xor i64* %ptr, i64 %val release @@ -4305,14 +4305,14 @@ define i64 @test257(i64* %ptr, i64 %val) { define i64 @test258(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test258: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB258_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB258_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -4322,14 +4322,14 @@ define i64 @test258(i64* %ptr, i64 %val) { define i64 @test259(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test259: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB259_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB259_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -4339,13 +4339,13 @@ define i64 @test259(i64* %ptr, i64 %val) { define i8 @test260(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test260: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB260_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: extsb 6, 5 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: ble 0, .LBB260_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB260_1 ; PPC64LE-NEXT: .LBB260_3: @@ -4357,14 +4357,14 @@ define i8 @test260(i8* %ptr, i8 %val) { define i8 @test261(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test261: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB261_1: ; PPC64LE-NEXT: lbarx 3, 0, 5 ; PPC64LE-NEXT: extsb 6, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: ble 0, .LBB261_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB261_1 ; PPC64LE-NEXT: .LBB261_3: @@ -4376,14 +4376,14 @@ define i8 @test261(i8* %ptr, i8 %val) { define i8 @test262(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test262: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB262_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: extsb 6, 5 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: ble 0, .LBB262_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB262_1 ; PPC64LE-NEXT: .LBB262_3: @@ -4395,14 +4395,14 @@ define i8 @test262(i8* %ptr, i8 %val) { define i8 @test263(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test263: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB263_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: extsb 6, 5 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: ble 0, .LBB263_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB263_1 ; PPC64LE-NEXT: .LBB263_3: @@ -4415,14 +4415,14 @@ define i8 @test263(i8* %ptr, i8 %val) { define i8 @test264(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test264: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB264_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: extsb 6, 5 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: ble 0, .LBB264_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB264_1 ; PPC64LE-NEXT: .LBB264_3: @@ -4435,13 +4435,13 @@ define i8 @test264(i8* %ptr, i8 %val) { define i16 @test265(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test265: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB265_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: extsh 6, 5 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: ble 0, .LBB265_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB265_1 ; PPC64LE-NEXT: .LBB265_3: @@ -4453,14 +4453,14 @@ define i16 @test265(i16* %ptr, i16 %val) { define i16 @test266(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test266: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB266_1: ; PPC64LE-NEXT: lharx 3, 0, 5 ; PPC64LE-NEXT: extsh 6, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: ble 0, .LBB266_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB266_1 ; PPC64LE-NEXT: .LBB266_3: @@ -4472,14 +4472,14 @@ define i16 @test266(i16* %ptr, i16 %val) { define i16 @test267(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test267: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB267_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: extsh 6, 5 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: ble 0, .LBB267_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB267_1 ; PPC64LE-NEXT: .LBB267_3: @@ -4491,14 +4491,14 @@ define i16 @test267(i16* %ptr, i16 %val) { define i16 @test268(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test268: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB268_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: extsh 6, 5 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: ble 0, .LBB268_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB268_1 ; PPC64LE-NEXT: .LBB268_3: @@ -4511,14 +4511,14 @@ define i16 @test268(i16* %ptr, i16 %val) { define i16 @test269(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test269: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB269_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: extsh 6, 5 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: ble 0, .LBB269_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB269_1 ; PPC64LE-NEXT: .LBB269_3: @@ -4531,12 +4531,12 @@ define i16 @test269(i16* %ptr, i16 %val) { define i32 @test270(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test270: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB270_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: cmpw 4, 5 ; PPC64LE-NEXT: ble 0, .LBB270_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB270_1 ; PPC64LE-NEXT: .LBB270_3: @@ -4548,13 +4548,13 @@ define i32 @test270(i32* %ptr, i32 %val) { define i32 @test271(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test271: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB271_1: ; PPC64LE-NEXT: lwarx 3, 0, 5 ; PPC64LE-NEXT: cmpw 4, 3 ; PPC64LE-NEXT: ble 0, .LBB271_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB271_1 ; PPC64LE-NEXT: .LBB271_3: @@ -4566,13 +4566,13 @@ define i32 @test271(i32* %ptr, i32 %val) { define i32 @test272(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test272: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB272_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: cmpw 4, 5 ; PPC64LE-NEXT: ble 0, .LBB272_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB272_1 ; PPC64LE-NEXT: .LBB272_3: @@ -4584,13 +4584,13 @@ define i32 @test272(i32* %ptr, i32 %val) { define i32 @test273(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test273: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB273_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: cmpw 4, 5 ; PPC64LE-NEXT: ble 0, .LBB273_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB273_1 ; PPC64LE-NEXT: .LBB273_3: @@ -4603,13 +4603,13 @@ define i32 @test273(i32* %ptr, i32 %val) { define i32 @test274(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test274: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB274_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: cmpw 4, 5 ; PPC64LE-NEXT: ble 0, .LBB274_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB274_1 ; PPC64LE-NEXT: .LBB274_3: @@ -4622,12 +4622,12 @@ define i32 @test274(i32* %ptr, i32 %val) { define i64 @test275(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test275: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB275_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: cmpd 4, 5 ; PPC64LE-NEXT: ble 0, .LBB275_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB275_1 ; PPC64LE-NEXT: .LBB275_3: @@ -4639,13 +4639,13 @@ define i64 @test275(i64* %ptr, i64 %val) { define i64 @test276(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test276: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB276_1: ; PPC64LE-NEXT: ldarx 3, 0, 5 ; PPC64LE-NEXT: cmpd 4, 3 ; PPC64LE-NEXT: ble 0, .LBB276_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB276_1 ; PPC64LE-NEXT: .LBB276_3: @@ -4657,13 +4657,13 @@ define i64 @test276(i64* %ptr, i64 %val) { define i64 @test277(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test277: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB277_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: cmpd 4, 5 ; PPC64LE-NEXT: ble 0, .LBB277_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB277_1 ; PPC64LE-NEXT: .LBB277_3: @@ -4675,13 +4675,13 @@ define i64 @test277(i64* %ptr, i64 %val) { define i64 @test278(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test278: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB278_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: cmpd 4, 5 ; PPC64LE-NEXT: ble 0, .LBB278_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB278_1 ; PPC64LE-NEXT: .LBB278_3: @@ -4694,13 +4694,13 @@ define i64 @test278(i64* %ptr, i64 %val) { define i64 @test279(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test279: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB279_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: cmpd 4, 5 ; PPC64LE-NEXT: ble 0, .LBB279_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB279_1 ; PPC64LE-NEXT: .LBB279_3: @@ -4713,13 +4713,13 @@ define i64 @test279(i64* %ptr, i64 %val) { define i8 @test280(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test280: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB280_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: extsb 6, 5 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bge 0, .LBB280_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB280_1 ; PPC64LE-NEXT: .LBB280_3: @@ -4731,14 +4731,14 @@ define i8 @test280(i8* %ptr, i8 %val) { define i8 @test281(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test281: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB281_1: ; PPC64LE-NEXT: lbarx 3, 0, 5 ; PPC64LE-NEXT: extsb 6, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bge 0, .LBB281_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB281_1 ; PPC64LE-NEXT: .LBB281_3: @@ -4750,14 +4750,14 @@ define i8 @test281(i8* %ptr, i8 %val) { define i8 @test282(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test282: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB282_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: extsb 6, 5 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bge 0, .LBB282_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB282_1 ; PPC64LE-NEXT: .LBB282_3: @@ -4769,14 +4769,14 @@ define i8 @test282(i8* %ptr, i8 %val) { define i8 @test283(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test283: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB283_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: extsb 6, 5 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bge 0, .LBB283_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB283_1 ; PPC64LE-NEXT: .LBB283_3: @@ -4789,14 +4789,14 @@ define i8 @test283(i8* %ptr, i8 %val) { define i8 @test284(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test284: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB284_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: extsb 6, 5 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bge 0, .LBB284_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB284_1 ; PPC64LE-NEXT: .LBB284_3: @@ -4809,13 +4809,13 @@ define i8 @test284(i8* %ptr, i8 %val) { define i16 @test285(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test285: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB285_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: extsh 6, 5 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bge 0, .LBB285_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB285_1 ; PPC64LE-NEXT: .LBB285_3: @@ -4827,14 +4827,14 @@ define i16 @test285(i16* %ptr, i16 %val) { define i16 @test286(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test286: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB286_1: ; PPC64LE-NEXT: lharx 3, 0, 5 ; PPC64LE-NEXT: extsh 6, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bge 0, .LBB286_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB286_1 ; PPC64LE-NEXT: .LBB286_3: @@ -4846,14 +4846,14 @@ define i16 @test286(i16* %ptr, i16 %val) { define i16 @test287(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test287: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB287_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: extsh 6, 5 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bge 0, .LBB287_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB287_1 ; PPC64LE-NEXT: .LBB287_3: @@ -4865,14 +4865,14 @@ define i16 @test287(i16* %ptr, i16 %val) { define i16 @test288(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test288: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB288_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: extsh 6, 5 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bge 0, .LBB288_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB288_1 ; PPC64LE-NEXT: .LBB288_3: @@ -4885,14 +4885,14 @@ define i16 @test288(i16* %ptr, i16 %val) { define i16 @test289(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test289: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB289_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: extsh 6, 5 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bge 0, .LBB289_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB289_1 ; PPC64LE-NEXT: .LBB289_3: @@ -4905,12 +4905,12 @@ define i16 @test289(i16* %ptr, i16 %val) { define i32 @test290(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test290: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB290_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: cmpw 4, 5 ; PPC64LE-NEXT: bge 0, .LBB290_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB290_1 ; PPC64LE-NEXT: .LBB290_3: @@ -4922,13 +4922,13 @@ define i32 @test290(i32* %ptr, i32 %val) { define i32 @test291(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test291: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB291_1: ; PPC64LE-NEXT: lwarx 3, 0, 5 ; PPC64LE-NEXT: cmpw 4, 3 ; PPC64LE-NEXT: bge 0, .LBB291_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB291_1 ; PPC64LE-NEXT: .LBB291_3: @@ -4940,13 +4940,13 @@ define i32 @test291(i32* %ptr, i32 %val) { define i32 @test292(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test292: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB292_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: cmpw 4, 5 ; PPC64LE-NEXT: bge 0, .LBB292_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB292_1 ; PPC64LE-NEXT: .LBB292_3: @@ -4958,13 +4958,13 @@ define i32 @test292(i32* %ptr, i32 %val) { define i32 @test293(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test293: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB293_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: cmpw 4, 5 ; PPC64LE-NEXT: bge 0, .LBB293_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB293_1 ; PPC64LE-NEXT: .LBB293_3: @@ -4977,13 +4977,13 @@ define i32 @test293(i32* %ptr, i32 %val) { define i32 @test294(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test294: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB294_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: cmpw 4, 5 ; PPC64LE-NEXT: bge 0, .LBB294_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB294_1 ; PPC64LE-NEXT: .LBB294_3: @@ -4996,12 +4996,12 @@ define i32 @test294(i32* %ptr, i32 %val) { define i64 @test295(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test295: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB295_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: cmpd 4, 5 ; PPC64LE-NEXT: bge 0, .LBB295_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB295_1 ; PPC64LE-NEXT: .LBB295_3: @@ -5013,13 +5013,13 @@ define i64 @test295(i64* %ptr, i64 %val) { define i64 @test296(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test296: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB296_1: ; PPC64LE-NEXT: ldarx 3, 0, 5 ; PPC64LE-NEXT: cmpd 4, 3 ; PPC64LE-NEXT: bge 0, .LBB296_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB296_1 ; PPC64LE-NEXT: .LBB296_3: @@ -5031,13 +5031,13 @@ define i64 @test296(i64* %ptr, i64 %val) { define i64 @test297(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test297: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB297_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: cmpd 4, 5 ; PPC64LE-NEXT: bge 0, .LBB297_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB297_1 ; PPC64LE-NEXT: .LBB297_3: @@ -5049,13 +5049,13 @@ define i64 @test297(i64* %ptr, i64 %val) { define i64 @test298(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test298: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB298_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: cmpd 4, 5 ; PPC64LE-NEXT: bge 0, .LBB298_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB298_1 ; PPC64LE-NEXT: .LBB298_3: @@ -5068,13 +5068,13 @@ define i64 @test298(i64* %ptr, i64 %val) { define i64 @test299(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test299: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB299_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: cmpd 4, 5 ; PPC64LE-NEXT: bge 0, .LBB299_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB299_1 ; PPC64LE-NEXT: .LBB299_3: @@ -5087,12 +5087,12 @@ define i64 @test299(i64* %ptr, i64 %val) { define i8 @test300(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test300: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB300_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: ble 0, .LBB300_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB300_1 ; PPC64LE-NEXT: .LBB300_3: @@ -5104,13 +5104,13 @@ define i8 @test300(i8* %ptr, i8 %val) { define i8 @test301(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test301: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB301_1: ; PPC64LE-NEXT: lbarx 3, 0, 5 ; PPC64LE-NEXT: cmplw 4, 3 ; PPC64LE-NEXT: ble 0, .LBB301_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB301_1 ; PPC64LE-NEXT: .LBB301_3: @@ -5122,13 +5122,13 @@ define i8 @test301(i8* %ptr, i8 %val) { define i8 @test302(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test302: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB302_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: ble 0, .LBB302_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB302_1 ; PPC64LE-NEXT: .LBB302_3: @@ -5140,13 +5140,13 @@ define i8 @test302(i8* %ptr, i8 %val) { define i8 @test303(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test303: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB303_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: ble 0, .LBB303_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB303_1 ; PPC64LE-NEXT: .LBB303_3: @@ -5159,13 +5159,13 @@ define i8 @test303(i8* %ptr, i8 %val) { define i8 @test304(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test304: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB304_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: ble 0, .LBB304_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB304_1 ; PPC64LE-NEXT: .LBB304_3: @@ -5178,12 +5178,12 @@ define i8 @test304(i8* %ptr, i8 %val) { define i16 @test305(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test305: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB305_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: ble 0, .LBB305_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB305_1 ; PPC64LE-NEXT: .LBB305_3: @@ -5195,13 +5195,13 @@ define i16 @test305(i16* %ptr, i16 %val) { define i16 @test306(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test306: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB306_1: ; PPC64LE-NEXT: lharx 3, 0, 5 ; PPC64LE-NEXT: cmplw 4, 3 ; PPC64LE-NEXT: ble 0, .LBB306_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB306_1 ; PPC64LE-NEXT: .LBB306_3: @@ -5213,13 +5213,13 @@ define i16 @test306(i16* %ptr, i16 %val) { define i16 @test307(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test307: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB307_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: ble 0, .LBB307_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB307_1 ; PPC64LE-NEXT: .LBB307_3: @@ -5231,13 +5231,13 @@ define i16 @test307(i16* %ptr, i16 %val) { define i16 @test308(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test308: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB308_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: ble 0, .LBB308_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB308_1 ; PPC64LE-NEXT: .LBB308_3: @@ -5250,13 +5250,13 @@ define i16 @test308(i16* %ptr, i16 %val) { define i16 @test309(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test309: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB309_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: ble 0, .LBB309_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB309_1 ; PPC64LE-NEXT: .LBB309_3: @@ -5269,12 +5269,12 @@ define i16 @test309(i16* %ptr, i16 %val) { define i32 @test310(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test310: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB310_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: ble 0, .LBB310_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB310_1 ; PPC64LE-NEXT: .LBB310_3: @@ -5286,13 +5286,13 @@ define i32 @test310(i32* %ptr, i32 %val) { define i32 @test311(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test311: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB311_1: ; PPC64LE-NEXT: lwarx 3, 0, 5 ; PPC64LE-NEXT: cmplw 4, 3 ; PPC64LE-NEXT: ble 0, .LBB311_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB311_1 ; PPC64LE-NEXT: .LBB311_3: @@ -5304,13 +5304,13 @@ define i32 @test311(i32* %ptr, i32 %val) { define i32 @test312(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test312: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB312_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: ble 0, .LBB312_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB312_1 ; PPC64LE-NEXT: .LBB312_3: @@ -5322,13 +5322,13 @@ define i32 @test312(i32* %ptr, i32 %val) { define i32 @test313(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test313: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB313_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: ble 0, .LBB313_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB313_1 ; PPC64LE-NEXT: .LBB313_3: @@ -5341,13 +5341,13 @@ define i32 @test313(i32* %ptr, i32 %val) { define i32 @test314(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test314: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB314_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: ble 0, .LBB314_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB314_1 ; PPC64LE-NEXT: .LBB314_3: @@ -5360,12 +5360,12 @@ define i32 @test314(i32* %ptr, i32 %val) { define i64 @test315(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test315: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB315_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: cmpld 4, 5 ; PPC64LE-NEXT: ble 0, .LBB315_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB315_1 ; PPC64LE-NEXT: .LBB315_3: @@ -5377,13 +5377,13 @@ define i64 @test315(i64* %ptr, i64 %val) { define i64 @test316(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test316: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB316_1: ; PPC64LE-NEXT: ldarx 3, 0, 5 ; PPC64LE-NEXT: cmpld 4, 3 ; PPC64LE-NEXT: ble 0, .LBB316_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB316_1 ; PPC64LE-NEXT: .LBB316_3: @@ -5395,13 +5395,13 @@ define i64 @test316(i64* %ptr, i64 %val) { define i64 @test317(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test317: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB317_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: cmpld 4, 5 ; PPC64LE-NEXT: ble 0, .LBB317_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB317_1 ; PPC64LE-NEXT: .LBB317_3: @@ -5413,13 +5413,13 @@ define i64 @test317(i64* %ptr, i64 %val) { define i64 @test318(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test318: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB318_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: cmpld 4, 5 ; PPC64LE-NEXT: ble 0, .LBB318_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB318_1 ; PPC64LE-NEXT: .LBB318_3: @@ -5432,13 +5432,13 @@ define i64 @test318(i64* %ptr, i64 %val) { define i64 @test319(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test319: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB319_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: cmpld 4, 5 ; PPC64LE-NEXT: ble 0, .LBB319_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB319_1 ; PPC64LE-NEXT: .LBB319_3: @@ -5451,12 +5451,12 @@ define i64 @test319(i64* %ptr, i64 %val) { define i8 @test320(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test320: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB320_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: bge 0, .LBB320_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB320_1 ; PPC64LE-NEXT: .LBB320_3: @@ -5468,13 +5468,13 @@ define i8 @test320(i8* %ptr, i8 %val) { define i8 @test321(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test321: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB321_1: ; PPC64LE-NEXT: lbarx 3, 0, 5 ; PPC64LE-NEXT: cmplw 4, 3 ; PPC64LE-NEXT: bge 0, .LBB321_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB321_1 ; PPC64LE-NEXT: .LBB321_3: @@ -5486,13 +5486,13 @@ define i8 @test321(i8* %ptr, i8 %val) { define i8 @test322(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test322: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB322_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: bge 0, .LBB322_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB322_1 ; PPC64LE-NEXT: .LBB322_3: @@ -5504,13 +5504,13 @@ define i8 @test322(i8* %ptr, i8 %val) { define i8 @test323(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test323: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB323_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: bge 0, .LBB323_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB323_1 ; PPC64LE-NEXT: .LBB323_3: @@ -5523,13 +5523,13 @@ define i8 @test323(i8* %ptr, i8 %val) { define i8 @test324(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test324: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB324_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: bge 0, .LBB324_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB324_1 ; PPC64LE-NEXT: .LBB324_3: @@ -5542,12 +5542,12 @@ define i8 @test324(i8* %ptr, i8 %val) { define i16 @test325(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test325: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB325_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: bge 0, .LBB325_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB325_1 ; PPC64LE-NEXT: .LBB325_3: @@ -5559,13 +5559,13 @@ define i16 @test325(i16* %ptr, i16 %val) { define i16 @test326(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test326: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB326_1: ; PPC64LE-NEXT: lharx 3, 0, 5 ; PPC64LE-NEXT: cmplw 4, 3 ; PPC64LE-NEXT: bge 0, .LBB326_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB326_1 ; PPC64LE-NEXT: .LBB326_3: @@ -5577,13 +5577,13 @@ define i16 @test326(i16* %ptr, i16 %val) { define i16 @test327(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test327: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB327_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: bge 0, .LBB327_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB327_1 ; PPC64LE-NEXT: .LBB327_3: @@ -5595,13 +5595,13 @@ define i16 @test327(i16* %ptr, i16 %val) { define i16 @test328(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test328: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB328_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: bge 0, .LBB328_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB328_1 ; PPC64LE-NEXT: .LBB328_3: @@ -5614,13 +5614,13 @@ define i16 @test328(i16* %ptr, i16 %val) { define i16 @test329(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test329: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB329_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: bge 0, .LBB329_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB329_1 ; PPC64LE-NEXT: .LBB329_3: @@ -5633,12 +5633,12 @@ define i16 @test329(i16* %ptr, i16 %val) { define i32 @test330(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test330: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB330_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: bge 0, .LBB330_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB330_1 ; PPC64LE-NEXT: .LBB330_3: @@ -5650,13 +5650,13 @@ define i32 @test330(i32* %ptr, i32 %val) { define i32 @test331(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test331: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB331_1: ; PPC64LE-NEXT: lwarx 3, 0, 5 ; PPC64LE-NEXT: cmplw 4, 3 ; PPC64LE-NEXT: bge 0, .LBB331_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB331_1 ; PPC64LE-NEXT: .LBB331_3: @@ -5668,13 +5668,13 @@ define i32 @test331(i32* %ptr, i32 %val) { define i32 @test332(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test332: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB332_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: bge 0, .LBB332_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB332_1 ; PPC64LE-NEXT: .LBB332_3: @@ -5686,13 +5686,13 @@ define i32 @test332(i32* %ptr, i32 %val) { define i32 @test333(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test333: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB333_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: bge 0, .LBB333_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB333_1 ; PPC64LE-NEXT: .LBB333_3: @@ -5705,13 +5705,13 @@ define i32 @test333(i32* %ptr, i32 %val) { define i32 @test334(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test334: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB334_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: bge 0, .LBB334_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB334_1 ; PPC64LE-NEXT: .LBB334_3: @@ -5724,12 +5724,12 @@ define i32 @test334(i32* %ptr, i32 %val) { define i64 @test335(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test335: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB335_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: cmpld 4, 5 ; PPC64LE-NEXT: bge 0, .LBB335_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB335_1 ; PPC64LE-NEXT: .LBB335_3: @@ -5741,13 +5741,13 @@ define i64 @test335(i64* %ptr, i64 %val) { define i64 @test336(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test336: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB336_1: ; PPC64LE-NEXT: ldarx 3, 0, 5 ; PPC64LE-NEXT: cmpld 4, 3 ; PPC64LE-NEXT: bge 0, .LBB336_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB336_1 ; PPC64LE-NEXT: .LBB336_3: @@ -5759,13 +5759,13 @@ define i64 @test336(i64* %ptr, i64 %val) { define i64 @test337(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test337: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB337_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: cmpld 4, 5 ; PPC64LE-NEXT: bge 0, .LBB337_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB337_1 ; PPC64LE-NEXT: .LBB337_3: @@ -5777,13 +5777,13 @@ define i64 @test337(i64* %ptr, i64 %val) { define i64 @test338(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test338: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB338_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: cmpld 4, 5 ; PPC64LE-NEXT: bge 0, .LBB338_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB338_1 ; PPC64LE-NEXT: .LBB338_3: @@ -5796,13 +5796,13 @@ define i64 @test338(i64* %ptr, i64 %val) { define i64 @test339(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test339: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB339_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: cmpld 4, 5 ; PPC64LE-NEXT: bge 0, .LBB339_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB339_1 ; PPC64LE-NEXT: .LBB339_3: @@ -5815,12 +5815,12 @@ define i64 @test339(i64* %ptr, i64 %val) { define i8 @test340(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test340: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB340_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB340_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw xchg i8* %ptr, i8 %val syncscope("singlethread") monotonic @@ -5829,13 +5829,13 @@ define i8 @test340(i8* %ptr, i8 %val) { define i8 @test341(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test341: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB341_1: ; PPC64LE-NEXT: lbarx 3, 0, 5 ; PPC64LE-NEXT: stbcx. 4, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB341_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw xchg i8* %ptr, i8 %val syncscope("singlethread") acquire @@ -5844,13 +5844,13 @@ define i8 @test341(i8* %ptr, i8 %val) { define i8 @test342(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test342: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB342_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB342_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw xchg i8* %ptr, i8 %val syncscope("singlethread") release @@ -5859,13 +5859,13 @@ define i8 @test342(i8* %ptr, i8 %val) { define i8 @test343(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test343: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB343_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB343_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -5875,13 +5875,13 @@ define i8 @test343(i8* %ptr, i8 %val) { define i8 @test344(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test344: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB344_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB344_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -5891,12 +5891,12 @@ define i8 @test344(i8* %ptr, i8 %val) { define i16 @test345(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test345: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB345_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB345_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw xchg i16* %ptr, i16 %val syncscope("singlethread") monotonic @@ -5905,13 +5905,13 @@ define i16 @test345(i16* %ptr, i16 %val) { define i16 @test346(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test346: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB346_1: ; PPC64LE-NEXT: lharx 3, 0, 5 ; PPC64LE-NEXT: sthcx. 4, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB346_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw xchg i16* %ptr, i16 %val syncscope("singlethread") acquire @@ -5920,13 +5920,13 @@ define i16 @test346(i16* %ptr, i16 %val) { define i16 @test347(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test347: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB347_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB347_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw xchg i16* %ptr, i16 %val syncscope("singlethread") release @@ -5935,13 +5935,13 @@ define i16 @test347(i16* %ptr, i16 %val) { define i16 @test348(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test348: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB348_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB348_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -5951,13 +5951,13 @@ define i16 @test348(i16* %ptr, i16 %val) { define i16 @test349(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test349: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB349_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB349_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -5967,12 +5967,12 @@ define i16 @test349(i16* %ptr, i16 %val) { define i32 @test350(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test350: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB350_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB350_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw xchg i32* %ptr, i32 %val syncscope("singlethread") monotonic @@ -5981,13 +5981,13 @@ define i32 @test350(i32* %ptr, i32 %val) { define i32 @test351(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test351: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB351_1: ; PPC64LE-NEXT: lwarx 3, 0, 5 ; PPC64LE-NEXT: stwcx. 4, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB351_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw xchg i32* %ptr, i32 %val syncscope("singlethread") acquire @@ -5996,13 +5996,13 @@ define i32 @test351(i32* %ptr, i32 %val) { define i32 @test352(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test352: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB352_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB352_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw xchg i32* %ptr, i32 %val syncscope("singlethread") release @@ -6011,13 +6011,13 @@ define i32 @test352(i32* %ptr, i32 %val) { define i32 @test353(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test353: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB353_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB353_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -6027,13 +6027,13 @@ define i32 @test353(i32* %ptr, i32 %val) { define i32 @test354(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test354: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB354_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB354_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -6043,12 +6043,12 @@ define i32 @test354(i32* %ptr, i32 %val) { define i64 @test355(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test355: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB355_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB355_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw xchg i64* %ptr, i64 %val syncscope("singlethread") monotonic @@ -6057,13 +6057,13 @@ define i64 @test355(i64* %ptr, i64 %val) { define i64 @test356(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test356: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB356_1: ; PPC64LE-NEXT: ldarx 3, 0, 5 ; PPC64LE-NEXT: stdcx. 4, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB356_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw xchg i64* %ptr, i64 %val syncscope("singlethread") acquire @@ -6072,13 +6072,13 @@ define i64 @test356(i64* %ptr, i64 %val) { define i64 @test357(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test357: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB357_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB357_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw xchg i64* %ptr, i64 %val syncscope("singlethread") release @@ -6087,13 +6087,13 @@ define i64 @test357(i64* %ptr, i64 %val) { define i64 @test358(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test358: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB358_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB358_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -6103,13 +6103,13 @@ define i64 @test358(i64* %ptr, i64 %val) { define i64 @test359(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test359: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB359_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB359_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -6119,13 +6119,13 @@ define i64 @test359(i64* %ptr, i64 %val) { define i8 @test360(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test360: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB360_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB360_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw add i8* %ptr, i8 %val syncscope("singlethread") monotonic @@ -6134,14 +6134,14 @@ define i8 @test360(i8* %ptr, i8 %val) { define i8 @test361(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test361: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB361_1: ; PPC64LE-NEXT: lbarx 3, 0, 5 ; PPC64LE-NEXT: add 6, 4, 3 ; PPC64LE-NEXT: stbcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB361_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw add i8* %ptr, i8 %val syncscope("singlethread") acquire @@ -6150,14 +6150,14 @@ define i8 @test361(i8* %ptr, i8 %val) { define i8 @test362(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test362: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB362_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB362_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw add i8* %ptr, i8 %val syncscope("singlethread") release @@ -6166,14 +6166,14 @@ define i8 @test362(i8* %ptr, i8 %val) { define i8 @test363(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test363: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB363_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB363_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -6183,14 +6183,14 @@ define i8 @test363(i8* %ptr, i8 %val) { define i8 @test364(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test364: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB364_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB364_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -6200,13 +6200,13 @@ define i8 @test364(i8* %ptr, i8 %val) { define i16 @test365(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test365: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB365_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB365_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw add i16* %ptr, i16 %val syncscope("singlethread") monotonic @@ -6215,14 +6215,14 @@ define i16 @test365(i16* %ptr, i16 %val) { define i16 @test366(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test366: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB366_1: ; PPC64LE-NEXT: lharx 3, 0, 5 ; PPC64LE-NEXT: add 6, 4, 3 ; PPC64LE-NEXT: sthcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB366_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw add i16* %ptr, i16 %val syncscope("singlethread") acquire @@ -6231,14 +6231,14 @@ define i16 @test366(i16* %ptr, i16 %val) { define i16 @test367(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test367: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB367_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB367_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw add i16* %ptr, i16 %val syncscope("singlethread") release @@ -6247,14 +6247,14 @@ define i16 @test367(i16* %ptr, i16 %val) { define i16 @test368(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test368: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB368_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB368_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -6264,14 +6264,14 @@ define i16 @test368(i16* %ptr, i16 %val) { define i16 @test369(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test369: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB369_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB369_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -6281,13 +6281,13 @@ define i16 @test369(i16* %ptr, i16 %val) { define i32 @test370(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test370: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB370_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB370_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw add i32* %ptr, i32 %val syncscope("singlethread") monotonic @@ -6296,14 +6296,14 @@ define i32 @test370(i32* %ptr, i32 %val) { define i32 @test371(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test371: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB371_1: ; PPC64LE-NEXT: lwarx 3, 0, 5 ; PPC64LE-NEXT: add 6, 4, 3 ; PPC64LE-NEXT: stwcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB371_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw add i32* %ptr, i32 %val syncscope("singlethread") acquire @@ -6312,14 +6312,14 @@ define i32 @test371(i32* %ptr, i32 %val) { define i32 @test372(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test372: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB372_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB372_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw add i32* %ptr, i32 %val syncscope("singlethread") release @@ -6328,14 +6328,14 @@ define i32 @test372(i32* %ptr, i32 %val) { define i32 @test373(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test373: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB373_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB373_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -6345,14 +6345,14 @@ define i32 @test373(i32* %ptr, i32 %val) { define i32 @test374(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test374: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB374_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB374_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -6362,13 +6362,13 @@ define i32 @test374(i32* %ptr, i32 %val) { define i64 @test375(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test375: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB375_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB375_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw add i64* %ptr, i64 %val syncscope("singlethread") monotonic @@ -6377,14 +6377,14 @@ define i64 @test375(i64* %ptr, i64 %val) { define i64 @test376(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test376: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB376_1: ; PPC64LE-NEXT: ldarx 3, 0, 5 ; PPC64LE-NEXT: add 6, 4, 3 ; PPC64LE-NEXT: stdcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB376_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw add i64* %ptr, i64 %val syncscope("singlethread") acquire @@ -6393,14 +6393,14 @@ define i64 @test376(i64* %ptr, i64 %val) { define i64 @test377(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test377: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB377_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB377_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw add i64* %ptr, i64 %val syncscope("singlethread") release @@ -6409,14 +6409,14 @@ define i64 @test377(i64* %ptr, i64 %val) { define i64 @test378(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test378: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB378_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB378_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -6426,14 +6426,14 @@ define i64 @test378(i64* %ptr, i64 %val) { define i64 @test379(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test379: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB379_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: add 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB379_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -6443,13 +6443,13 @@ define i64 @test379(i64* %ptr, i64 %val) { define i8 @test380(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test380: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB380_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: subf 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB380_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw sub i8* %ptr, i8 %val syncscope("singlethread") monotonic @@ -6458,14 +6458,14 @@ define i8 @test380(i8* %ptr, i8 %val) { define i8 @test381(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test381: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB381_1: ; PPC64LE-NEXT: lbarx 3, 0, 5 ; PPC64LE-NEXT: subf 6, 4, 3 ; PPC64LE-NEXT: stbcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB381_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw sub i8* %ptr, i8 %val syncscope("singlethread") acquire @@ -6474,14 +6474,14 @@ define i8 @test381(i8* %ptr, i8 %val) { define i8 @test382(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test382: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB382_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: subf 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB382_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw sub i8* %ptr, i8 %val syncscope("singlethread") release @@ -6490,14 +6490,14 @@ define i8 @test382(i8* %ptr, i8 %val) { define i8 @test383(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test383: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB383_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: subf 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB383_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -6507,14 +6507,14 @@ define i8 @test383(i8* %ptr, i8 %val) { define i8 @test384(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test384: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB384_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: subf 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB384_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -6524,13 +6524,13 @@ define i8 @test384(i8* %ptr, i8 %val) { define i16 @test385(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test385: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB385_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: subf 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB385_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw sub i16* %ptr, i16 %val syncscope("singlethread") monotonic @@ -6539,14 +6539,14 @@ define i16 @test385(i16* %ptr, i16 %val) { define i16 @test386(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test386: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB386_1: ; PPC64LE-NEXT: lharx 3, 0, 5 ; PPC64LE-NEXT: subf 6, 4, 3 ; PPC64LE-NEXT: sthcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB386_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw sub i16* %ptr, i16 %val syncscope("singlethread") acquire @@ -6555,14 +6555,14 @@ define i16 @test386(i16* %ptr, i16 %val) { define i16 @test387(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test387: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB387_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: subf 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB387_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw sub i16* %ptr, i16 %val syncscope("singlethread") release @@ -6571,14 +6571,14 @@ define i16 @test387(i16* %ptr, i16 %val) { define i16 @test388(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test388: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB388_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: subf 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB388_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -6588,14 +6588,14 @@ define i16 @test388(i16* %ptr, i16 %val) { define i16 @test389(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test389: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB389_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: subf 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB389_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -6605,13 +6605,13 @@ define i16 @test389(i16* %ptr, i16 %val) { define i32 @test390(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test390: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB390_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: subf 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB390_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw sub i32* %ptr, i32 %val syncscope("singlethread") monotonic @@ -6620,14 +6620,14 @@ define i32 @test390(i32* %ptr, i32 %val) { define i32 @test391(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test391: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB391_1: ; PPC64LE-NEXT: lwarx 3, 0, 5 ; PPC64LE-NEXT: subf 6, 4, 3 ; PPC64LE-NEXT: stwcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB391_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw sub i32* %ptr, i32 %val syncscope("singlethread") acquire @@ -6636,14 +6636,14 @@ define i32 @test391(i32* %ptr, i32 %val) { define i32 @test392(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test392: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB392_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: subf 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB392_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw sub i32* %ptr, i32 %val syncscope("singlethread") release @@ -6652,14 +6652,14 @@ define i32 @test392(i32* %ptr, i32 %val) { define i32 @test393(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test393: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB393_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: subf 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB393_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -6669,14 +6669,14 @@ define i32 @test393(i32* %ptr, i32 %val) { define i32 @test394(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test394: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB394_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: subf 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB394_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -6686,13 +6686,13 @@ define i32 @test394(i32* %ptr, i32 %val) { define i64 @test395(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test395: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB395_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: sub 6, 5, 4 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB395_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw sub i64* %ptr, i64 %val syncscope("singlethread") monotonic @@ -6701,14 +6701,14 @@ define i64 @test395(i64* %ptr, i64 %val) { define i64 @test396(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test396: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB396_1: ; PPC64LE-NEXT: ldarx 3, 0, 5 ; PPC64LE-NEXT: sub 6, 3, 4 ; PPC64LE-NEXT: stdcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB396_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw sub i64* %ptr, i64 %val syncscope("singlethread") acquire @@ -6717,14 +6717,14 @@ define i64 @test396(i64* %ptr, i64 %val) { define i64 @test397(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test397: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB397_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: sub 6, 5, 4 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB397_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw sub i64* %ptr, i64 %val syncscope("singlethread") release @@ -6733,14 +6733,14 @@ define i64 @test397(i64* %ptr, i64 %val) { define i64 @test398(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test398: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB398_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: sub 6, 5, 4 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB398_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -6750,14 +6750,14 @@ define i64 @test398(i64* %ptr, i64 %val) { define i64 @test399(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test399: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB399_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: sub 6, 5, 4 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB399_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -6767,13 +6767,13 @@ define i64 @test399(i64* %ptr, i64 %val) { define i8 @test400(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test400: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB400_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB400_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw and i8* %ptr, i8 %val syncscope("singlethread") monotonic @@ -6782,14 +6782,14 @@ define i8 @test400(i8* %ptr, i8 %val) { define i8 @test401(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test401: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB401_1: ; PPC64LE-NEXT: lbarx 3, 0, 5 ; PPC64LE-NEXT: and 6, 4, 3 ; PPC64LE-NEXT: stbcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB401_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw and i8* %ptr, i8 %val syncscope("singlethread") acquire @@ -6798,14 +6798,14 @@ define i8 @test401(i8* %ptr, i8 %val) { define i8 @test402(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test402: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB402_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB402_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw and i8* %ptr, i8 %val syncscope("singlethread") release @@ -6814,14 +6814,14 @@ define i8 @test402(i8* %ptr, i8 %val) { define i8 @test403(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test403: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB403_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB403_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -6831,14 +6831,14 @@ define i8 @test403(i8* %ptr, i8 %val) { define i8 @test404(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test404: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB404_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB404_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -6848,13 +6848,13 @@ define i8 @test404(i8* %ptr, i8 %val) { define i16 @test405(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test405: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB405_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB405_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw and i16* %ptr, i16 %val syncscope("singlethread") monotonic @@ -6863,14 +6863,14 @@ define i16 @test405(i16* %ptr, i16 %val) { define i16 @test406(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test406: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB406_1: ; PPC64LE-NEXT: lharx 3, 0, 5 ; PPC64LE-NEXT: and 6, 4, 3 ; PPC64LE-NEXT: sthcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB406_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw and i16* %ptr, i16 %val syncscope("singlethread") acquire @@ -6879,14 +6879,14 @@ define i16 @test406(i16* %ptr, i16 %val) { define i16 @test407(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test407: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB407_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB407_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw and i16* %ptr, i16 %val syncscope("singlethread") release @@ -6895,14 +6895,14 @@ define i16 @test407(i16* %ptr, i16 %val) { define i16 @test408(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test408: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB408_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB408_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -6912,14 +6912,14 @@ define i16 @test408(i16* %ptr, i16 %val) { define i16 @test409(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test409: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB409_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB409_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -6929,13 +6929,13 @@ define i16 @test409(i16* %ptr, i16 %val) { define i32 @test410(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test410: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB410_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB410_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw and i32* %ptr, i32 %val syncscope("singlethread") monotonic @@ -6944,14 +6944,14 @@ define i32 @test410(i32* %ptr, i32 %val) { define i32 @test411(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test411: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB411_1: ; PPC64LE-NEXT: lwarx 3, 0, 5 ; PPC64LE-NEXT: and 6, 4, 3 ; PPC64LE-NEXT: stwcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB411_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw and i32* %ptr, i32 %val syncscope("singlethread") acquire @@ -6960,14 +6960,14 @@ define i32 @test411(i32* %ptr, i32 %val) { define i32 @test412(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test412: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB412_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB412_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw and i32* %ptr, i32 %val syncscope("singlethread") release @@ -6976,14 +6976,14 @@ define i32 @test412(i32* %ptr, i32 %val) { define i32 @test413(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test413: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB413_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB413_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -6993,14 +6993,14 @@ define i32 @test413(i32* %ptr, i32 %val) { define i32 @test414(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test414: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB414_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB414_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -7010,13 +7010,13 @@ define i32 @test414(i32* %ptr, i32 %val) { define i64 @test415(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test415: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB415_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB415_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw and i64* %ptr, i64 %val syncscope("singlethread") monotonic @@ -7025,14 +7025,14 @@ define i64 @test415(i64* %ptr, i64 %val) { define i64 @test416(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test416: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB416_1: ; PPC64LE-NEXT: ldarx 3, 0, 5 ; PPC64LE-NEXT: and 6, 4, 3 ; PPC64LE-NEXT: stdcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB416_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw and i64* %ptr, i64 %val syncscope("singlethread") acquire @@ -7041,14 +7041,14 @@ define i64 @test416(i64* %ptr, i64 %val) { define i64 @test417(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test417: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB417_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB417_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw and i64* %ptr, i64 %val syncscope("singlethread") release @@ -7057,14 +7057,14 @@ define i64 @test417(i64* %ptr, i64 %val) { define i64 @test418(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test418: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB418_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB418_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -7074,14 +7074,14 @@ define i64 @test418(i64* %ptr, i64 %val) { define i64 @test419(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test419: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB419_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: and 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB419_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -7091,13 +7091,13 @@ define i64 @test419(i64* %ptr, i64 %val) { define i8 @test420(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test420: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB420_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB420_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw nand i8* %ptr, i8 %val syncscope("singlethread") monotonic @@ -7106,14 +7106,14 @@ define i8 @test420(i8* %ptr, i8 %val) { define i8 @test421(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test421: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB421_1: ; PPC64LE-NEXT: lbarx 3, 0, 5 ; PPC64LE-NEXT: nand 6, 4, 3 ; PPC64LE-NEXT: stbcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB421_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw nand i8* %ptr, i8 %val syncscope("singlethread") acquire @@ -7122,14 +7122,14 @@ define i8 @test421(i8* %ptr, i8 %val) { define i8 @test422(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test422: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB422_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB422_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw nand i8* %ptr, i8 %val syncscope("singlethread") release @@ -7138,14 +7138,14 @@ define i8 @test422(i8* %ptr, i8 %val) { define i8 @test423(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test423: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB423_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB423_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -7155,14 +7155,14 @@ define i8 @test423(i8* %ptr, i8 %val) { define i8 @test424(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test424: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB424_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB424_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -7172,13 +7172,13 @@ define i8 @test424(i8* %ptr, i8 %val) { define i16 @test425(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test425: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB425_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB425_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw nand i16* %ptr, i16 %val syncscope("singlethread") monotonic @@ -7187,14 +7187,14 @@ define i16 @test425(i16* %ptr, i16 %val) { define i16 @test426(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test426: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB426_1: ; PPC64LE-NEXT: lharx 3, 0, 5 ; PPC64LE-NEXT: nand 6, 4, 3 ; PPC64LE-NEXT: sthcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB426_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw nand i16* %ptr, i16 %val syncscope("singlethread") acquire @@ -7203,14 +7203,14 @@ define i16 @test426(i16* %ptr, i16 %val) { define i16 @test427(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test427: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB427_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB427_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw nand i16* %ptr, i16 %val syncscope("singlethread") release @@ -7219,14 +7219,14 @@ define i16 @test427(i16* %ptr, i16 %val) { define i16 @test428(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test428: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB428_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB428_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -7236,14 +7236,14 @@ define i16 @test428(i16* %ptr, i16 %val) { define i16 @test429(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test429: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB429_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB429_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -7253,13 +7253,13 @@ define i16 @test429(i16* %ptr, i16 %val) { define i32 @test430(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test430: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB430_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB430_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw nand i32* %ptr, i32 %val syncscope("singlethread") monotonic @@ -7268,14 +7268,14 @@ define i32 @test430(i32* %ptr, i32 %val) { define i32 @test431(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test431: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB431_1: ; PPC64LE-NEXT: lwarx 3, 0, 5 ; PPC64LE-NEXT: nand 6, 4, 3 ; PPC64LE-NEXT: stwcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB431_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw nand i32* %ptr, i32 %val syncscope("singlethread") acquire @@ -7284,14 +7284,14 @@ define i32 @test431(i32* %ptr, i32 %val) { define i32 @test432(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test432: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB432_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB432_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw nand i32* %ptr, i32 %val syncscope("singlethread") release @@ -7300,14 +7300,14 @@ define i32 @test432(i32* %ptr, i32 %val) { define i32 @test433(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test433: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB433_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB433_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -7317,14 +7317,14 @@ define i32 @test433(i32* %ptr, i32 %val) { define i32 @test434(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test434: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB434_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB434_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -7334,13 +7334,13 @@ define i32 @test434(i32* %ptr, i32 %val) { define i64 @test435(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test435: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB435_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB435_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw nand i64* %ptr, i64 %val syncscope("singlethread") monotonic @@ -7349,14 +7349,14 @@ define i64 @test435(i64* %ptr, i64 %val) { define i64 @test436(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test436: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB436_1: ; PPC64LE-NEXT: ldarx 3, 0, 5 ; PPC64LE-NEXT: nand 6, 4, 3 ; PPC64LE-NEXT: stdcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB436_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw nand i64* %ptr, i64 %val syncscope("singlethread") acquire @@ -7365,14 +7365,14 @@ define i64 @test436(i64* %ptr, i64 %val) { define i64 @test437(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test437: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB437_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB437_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw nand i64* %ptr, i64 %val syncscope("singlethread") release @@ -7381,14 +7381,14 @@ define i64 @test437(i64* %ptr, i64 %val) { define i64 @test438(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test438: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB438_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB438_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -7398,14 +7398,14 @@ define i64 @test438(i64* %ptr, i64 %val) { define i64 @test439(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test439: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB439_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: nand 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB439_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -7415,13 +7415,13 @@ define i64 @test439(i64* %ptr, i64 %val) { define i8 @test440(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test440: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB440_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB440_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw or i8* %ptr, i8 %val syncscope("singlethread") monotonic @@ -7430,14 +7430,14 @@ define i8 @test440(i8* %ptr, i8 %val) { define i8 @test441(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test441: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB441_1: ; PPC64LE-NEXT: lbarx 3, 0, 5 ; PPC64LE-NEXT: or 6, 4, 3 ; PPC64LE-NEXT: stbcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB441_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw or i8* %ptr, i8 %val syncscope("singlethread") acquire @@ -7446,14 +7446,14 @@ define i8 @test441(i8* %ptr, i8 %val) { define i8 @test442(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test442: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB442_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB442_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw or i8* %ptr, i8 %val syncscope("singlethread") release @@ -7462,14 +7462,14 @@ define i8 @test442(i8* %ptr, i8 %val) { define i8 @test443(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test443: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB443_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB443_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -7479,14 +7479,14 @@ define i8 @test443(i8* %ptr, i8 %val) { define i8 @test444(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test444: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB444_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB444_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -7496,13 +7496,13 @@ define i8 @test444(i8* %ptr, i8 %val) { define i16 @test445(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test445: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB445_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB445_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw or i16* %ptr, i16 %val syncscope("singlethread") monotonic @@ -7511,14 +7511,14 @@ define i16 @test445(i16* %ptr, i16 %val) { define i16 @test446(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test446: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB446_1: ; PPC64LE-NEXT: lharx 3, 0, 5 ; PPC64LE-NEXT: or 6, 4, 3 ; PPC64LE-NEXT: sthcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB446_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw or i16* %ptr, i16 %val syncscope("singlethread") acquire @@ -7527,14 +7527,14 @@ define i16 @test446(i16* %ptr, i16 %val) { define i16 @test447(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test447: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB447_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB447_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw or i16* %ptr, i16 %val syncscope("singlethread") release @@ -7543,14 +7543,14 @@ define i16 @test447(i16* %ptr, i16 %val) { define i16 @test448(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test448: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB448_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB448_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -7560,14 +7560,14 @@ define i16 @test448(i16* %ptr, i16 %val) { define i16 @test449(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test449: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB449_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB449_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -7577,13 +7577,13 @@ define i16 @test449(i16* %ptr, i16 %val) { define i32 @test450(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test450: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB450_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB450_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw or i32* %ptr, i32 %val syncscope("singlethread") monotonic @@ -7592,14 +7592,14 @@ define i32 @test450(i32* %ptr, i32 %val) { define i32 @test451(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test451: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB451_1: ; PPC64LE-NEXT: lwarx 3, 0, 5 ; PPC64LE-NEXT: or 6, 4, 3 ; PPC64LE-NEXT: stwcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB451_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw or i32* %ptr, i32 %val syncscope("singlethread") acquire @@ -7608,14 +7608,14 @@ define i32 @test451(i32* %ptr, i32 %val) { define i32 @test452(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test452: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB452_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB452_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw or i32* %ptr, i32 %val syncscope("singlethread") release @@ -7624,14 +7624,14 @@ define i32 @test452(i32* %ptr, i32 %val) { define i32 @test453(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test453: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB453_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB453_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -7641,14 +7641,14 @@ define i32 @test453(i32* %ptr, i32 %val) { define i32 @test454(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test454: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB454_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB454_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -7658,13 +7658,13 @@ define i32 @test454(i32* %ptr, i32 %val) { define i64 @test455(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test455: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB455_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB455_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw or i64* %ptr, i64 %val syncscope("singlethread") monotonic @@ -7673,14 +7673,14 @@ define i64 @test455(i64* %ptr, i64 %val) { define i64 @test456(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test456: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB456_1: ; PPC64LE-NEXT: ldarx 3, 0, 5 ; PPC64LE-NEXT: or 6, 4, 3 ; PPC64LE-NEXT: stdcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB456_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw or i64* %ptr, i64 %val syncscope("singlethread") acquire @@ -7689,14 +7689,14 @@ define i64 @test456(i64* %ptr, i64 %val) { define i64 @test457(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test457: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB457_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB457_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw or i64* %ptr, i64 %val syncscope("singlethread") release @@ -7705,14 +7705,14 @@ define i64 @test457(i64* %ptr, i64 %val) { define i64 @test458(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test458: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB458_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB458_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -7722,14 +7722,14 @@ define i64 @test458(i64* %ptr, i64 %val) { define i64 @test459(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test459: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB459_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: or 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB459_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -7739,13 +7739,13 @@ define i64 @test459(i64* %ptr, i64 %val) { define i8 @test460(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test460: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB460_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB460_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw xor i8* %ptr, i8 %val syncscope("singlethread") monotonic @@ -7754,14 +7754,14 @@ define i8 @test460(i8* %ptr, i8 %val) { define i8 @test461(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test461: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB461_1: ; PPC64LE-NEXT: lbarx 3, 0, 5 ; PPC64LE-NEXT: xor 6, 4, 3 ; PPC64LE-NEXT: stbcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB461_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw xor i8* %ptr, i8 %val syncscope("singlethread") acquire @@ -7770,14 +7770,14 @@ define i8 @test461(i8* %ptr, i8 %val) { define i8 @test462(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test462: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB462_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB462_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw xor i8* %ptr, i8 %val syncscope("singlethread") release @@ -7786,14 +7786,14 @@ define i8 @test462(i8* %ptr, i8 %val) { define i8 @test463(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test463: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB463_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB463_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -7803,14 +7803,14 @@ define i8 @test463(i8* %ptr, i8 %val) { define i8 @test464(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test464: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB464_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB464_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -7820,13 +7820,13 @@ define i8 @test464(i8* %ptr, i8 %val) { define i16 @test465(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test465: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB465_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB465_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw xor i16* %ptr, i16 %val syncscope("singlethread") monotonic @@ -7835,14 +7835,14 @@ define i16 @test465(i16* %ptr, i16 %val) { define i16 @test466(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test466: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB466_1: ; PPC64LE-NEXT: lharx 3, 0, 5 ; PPC64LE-NEXT: xor 6, 4, 3 ; PPC64LE-NEXT: sthcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB466_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw xor i16* %ptr, i16 %val syncscope("singlethread") acquire @@ -7851,14 +7851,14 @@ define i16 @test466(i16* %ptr, i16 %val) { define i16 @test467(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test467: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB467_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB467_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw xor i16* %ptr, i16 %val syncscope("singlethread") release @@ -7867,14 +7867,14 @@ define i16 @test467(i16* %ptr, i16 %val) { define i16 @test468(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test468: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB468_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB468_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -7884,14 +7884,14 @@ define i16 @test468(i16* %ptr, i16 %val) { define i16 @test469(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test469: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB469_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB469_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -7901,13 +7901,13 @@ define i16 @test469(i16* %ptr, i16 %val) { define i32 @test470(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test470: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB470_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB470_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw xor i32* %ptr, i32 %val syncscope("singlethread") monotonic @@ -7916,14 +7916,14 @@ define i32 @test470(i32* %ptr, i32 %val) { define i32 @test471(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test471: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB471_1: ; PPC64LE-NEXT: lwarx 3, 0, 5 ; PPC64LE-NEXT: xor 6, 4, 3 ; PPC64LE-NEXT: stwcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB471_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw xor i32* %ptr, i32 %val syncscope("singlethread") acquire @@ -7932,14 +7932,14 @@ define i32 @test471(i32* %ptr, i32 %val) { define i32 @test472(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test472: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB472_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB472_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw xor i32* %ptr, i32 %val syncscope("singlethread") release @@ -7948,14 +7948,14 @@ define i32 @test472(i32* %ptr, i32 %val) { define i32 @test473(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test473: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB473_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB473_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -7965,14 +7965,14 @@ define i32 @test473(i32* %ptr, i32 %val) { define i32 @test474(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test474: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB474_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: stwcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB474_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -7982,13 +7982,13 @@ define i32 @test474(i32* %ptr, i32 %val) { define i64 @test475(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test475: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB475_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB475_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw xor i64* %ptr, i64 %val syncscope("singlethread") monotonic @@ -7997,14 +7997,14 @@ define i64 @test475(i64* %ptr, i64 %val) { define i64 @test476(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test476: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB476_1: ; PPC64LE-NEXT: ldarx 3, 0, 5 ; PPC64LE-NEXT: xor 6, 4, 3 ; PPC64LE-NEXT: stdcx. 6, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB476_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %ret = atomicrmw xor i64* %ptr, i64 %val syncscope("singlethread") acquire @@ -8013,14 +8013,14 @@ define i64 @test476(i64* %ptr, i64 %val) { define i64 @test477(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test477: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB477_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB477_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: blr %ret = atomicrmw xor i64* %ptr, i64 %val syncscope("singlethread") release @@ -8029,14 +8029,14 @@ define i64 @test477(i64* %ptr, i64 %val) { define i64 @test478(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test478: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB478_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB478_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -8046,14 +8046,14 @@ define i64 @test478(i64* %ptr, i64 %val) { define i64 @test479(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test479: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB479_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: xor 6, 4, 5 ; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB479_1 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: mr 3, 5 ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -8063,13 +8063,13 @@ define i64 @test479(i64* %ptr, i64 %val) { define i8 @test480(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test480: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB480_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: extsb 6, 5 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: ble 0, .LBB480_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB480_1 ; PPC64LE-NEXT: .LBB480_3: @@ -8081,14 +8081,14 @@ define i8 @test480(i8* %ptr, i8 %val) { define i8 @test481(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test481: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB481_1: ; PPC64LE-NEXT: lbarx 3, 0, 5 ; PPC64LE-NEXT: extsb 6, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: ble 0, .LBB481_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB481_1 ; PPC64LE-NEXT: .LBB481_3: @@ -8100,14 +8100,14 @@ define i8 @test481(i8* %ptr, i8 %val) { define i8 @test482(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test482: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB482_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: extsb 6, 5 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: ble 0, .LBB482_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB482_1 ; PPC64LE-NEXT: .LBB482_3: @@ -8119,14 +8119,14 @@ define i8 @test482(i8* %ptr, i8 %val) { define i8 @test483(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test483: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB483_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: extsb 6, 5 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: ble 0, .LBB483_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB483_1 ; PPC64LE-NEXT: .LBB483_3: @@ -8139,14 +8139,14 @@ define i8 @test483(i8* %ptr, i8 %val) { define i8 @test484(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test484: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB484_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: extsb 6, 5 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: ble 0, .LBB484_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB484_1 ; PPC64LE-NEXT: .LBB484_3: @@ -8159,13 +8159,13 @@ define i8 @test484(i8* %ptr, i8 %val) { define i16 @test485(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test485: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB485_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: extsh 6, 5 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: ble 0, .LBB485_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB485_1 ; PPC64LE-NEXT: .LBB485_3: @@ -8177,14 +8177,14 @@ define i16 @test485(i16* %ptr, i16 %val) { define i16 @test486(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test486: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB486_1: ; PPC64LE-NEXT: lharx 3, 0, 5 ; PPC64LE-NEXT: extsh 6, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: ble 0, .LBB486_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB486_1 ; PPC64LE-NEXT: .LBB486_3: @@ -8196,14 +8196,14 @@ define i16 @test486(i16* %ptr, i16 %val) { define i16 @test487(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test487: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB487_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: extsh 6, 5 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: ble 0, .LBB487_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB487_1 ; PPC64LE-NEXT: .LBB487_3: @@ -8215,14 +8215,14 @@ define i16 @test487(i16* %ptr, i16 %val) { define i16 @test488(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test488: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB488_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: extsh 6, 5 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: ble 0, .LBB488_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB488_1 ; PPC64LE-NEXT: .LBB488_3: @@ -8235,14 +8235,14 @@ define i16 @test488(i16* %ptr, i16 %val) { define i16 @test489(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test489: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB489_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: extsh 6, 5 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: ble 0, .LBB489_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB489_1 ; PPC64LE-NEXT: .LBB489_3: @@ -8255,12 +8255,12 @@ define i16 @test489(i16* %ptr, i16 %val) { define i32 @test490(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test490: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB490_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: cmpw 4, 5 ; PPC64LE-NEXT: ble 0, .LBB490_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB490_1 ; PPC64LE-NEXT: .LBB490_3: @@ -8272,13 +8272,13 @@ define i32 @test490(i32* %ptr, i32 %val) { define i32 @test491(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test491: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB491_1: ; PPC64LE-NEXT: lwarx 3, 0, 5 ; PPC64LE-NEXT: cmpw 4, 3 ; PPC64LE-NEXT: ble 0, .LBB491_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB491_1 ; PPC64LE-NEXT: .LBB491_3: @@ -8290,13 +8290,13 @@ define i32 @test491(i32* %ptr, i32 %val) { define i32 @test492(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test492: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB492_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: cmpw 4, 5 ; PPC64LE-NEXT: ble 0, .LBB492_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB492_1 ; PPC64LE-NEXT: .LBB492_3: @@ -8308,13 +8308,13 @@ define i32 @test492(i32* %ptr, i32 %val) { define i32 @test493(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test493: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB493_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: cmpw 4, 5 ; PPC64LE-NEXT: ble 0, .LBB493_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB493_1 ; PPC64LE-NEXT: .LBB493_3: @@ -8327,13 +8327,13 @@ define i32 @test493(i32* %ptr, i32 %val) { define i32 @test494(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test494: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB494_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: cmpw 4, 5 ; PPC64LE-NEXT: ble 0, .LBB494_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB494_1 ; PPC64LE-NEXT: .LBB494_3: @@ -8346,12 +8346,12 @@ define i32 @test494(i32* %ptr, i32 %val) { define i64 @test495(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test495: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB495_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: cmpd 4, 5 ; PPC64LE-NEXT: ble 0, .LBB495_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB495_1 ; PPC64LE-NEXT: .LBB495_3: @@ -8363,13 +8363,13 @@ define i64 @test495(i64* %ptr, i64 %val) { define i64 @test496(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test496: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB496_1: ; PPC64LE-NEXT: ldarx 3, 0, 5 ; PPC64LE-NEXT: cmpd 4, 3 ; PPC64LE-NEXT: ble 0, .LBB496_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB496_1 ; PPC64LE-NEXT: .LBB496_3: @@ -8381,13 +8381,13 @@ define i64 @test496(i64* %ptr, i64 %val) { define i64 @test497(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test497: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB497_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: cmpd 4, 5 ; PPC64LE-NEXT: ble 0, .LBB497_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB497_1 ; PPC64LE-NEXT: .LBB497_3: @@ -8399,13 +8399,13 @@ define i64 @test497(i64* %ptr, i64 %val) { define i64 @test498(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test498: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB498_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: cmpd 4, 5 ; PPC64LE-NEXT: ble 0, .LBB498_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB498_1 ; PPC64LE-NEXT: .LBB498_3: @@ -8418,13 +8418,13 @@ define i64 @test498(i64* %ptr, i64 %val) { define i64 @test499(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test499: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB499_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: cmpd 4, 5 ; PPC64LE-NEXT: ble 0, .LBB499_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB499_1 ; PPC64LE-NEXT: .LBB499_3: @@ -8437,13 +8437,13 @@ define i64 @test499(i64* %ptr, i64 %val) { define i8 @test500(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test500: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB500_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: extsb 6, 5 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bge 0, .LBB500_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB500_1 ; PPC64LE-NEXT: .LBB500_3: @@ -8455,14 +8455,14 @@ define i8 @test500(i8* %ptr, i8 %val) { define i8 @test501(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test501: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB501_1: ; PPC64LE-NEXT: lbarx 3, 0, 5 ; PPC64LE-NEXT: extsb 6, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bge 0, .LBB501_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB501_1 ; PPC64LE-NEXT: .LBB501_3: @@ -8474,14 +8474,14 @@ define i8 @test501(i8* %ptr, i8 %val) { define i8 @test502(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test502: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB502_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: extsb 6, 5 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bge 0, .LBB502_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB502_1 ; PPC64LE-NEXT: .LBB502_3: @@ -8493,14 +8493,14 @@ define i8 @test502(i8* %ptr, i8 %val) { define i8 @test503(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test503: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB503_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: extsb 6, 5 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bge 0, .LBB503_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB503_1 ; PPC64LE-NEXT: .LBB503_3: @@ -8513,14 +8513,14 @@ define i8 @test503(i8* %ptr, i8 %val) { define i8 @test504(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test504: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB504_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: extsb 6, 5 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bge 0, .LBB504_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB504_1 ; PPC64LE-NEXT: .LBB504_3: @@ -8533,13 +8533,13 @@ define i8 @test504(i8* %ptr, i8 %val) { define i16 @test505(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test505: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB505_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: extsh 6, 5 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bge 0, .LBB505_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB505_1 ; PPC64LE-NEXT: .LBB505_3: @@ -8551,14 +8551,14 @@ define i16 @test505(i16* %ptr, i16 %val) { define i16 @test506(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test506: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB506_1: ; PPC64LE-NEXT: lharx 3, 0, 5 ; PPC64LE-NEXT: extsh 6, 3 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bge 0, .LBB506_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB506_1 ; PPC64LE-NEXT: .LBB506_3: @@ -8570,14 +8570,14 @@ define i16 @test506(i16* %ptr, i16 %val) { define i16 @test507(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test507: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB507_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: extsh 6, 5 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bge 0, .LBB507_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB507_1 ; PPC64LE-NEXT: .LBB507_3: @@ -8589,14 +8589,14 @@ define i16 @test507(i16* %ptr, i16 %val) { define i16 @test508(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test508: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB508_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: extsh 6, 5 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bge 0, .LBB508_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB508_1 ; PPC64LE-NEXT: .LBB508_3: @@ -8609,14 +8609,14 @@ define i16 @test508(i16* %ptr, i16 %val) { define i16 @test509(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test509: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB509_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: extsh 6, 5 ; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: bge 0, .LBB509_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB509_1 ; PPC64LE-NEXT: .LBB509_3: @@ -8629,12 +8629,12 @@ define i16 @test509(i16* %ptr, i16 %val) { define i32 @test510(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test510: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB510_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: cmpw 4, 5 ; PPC64LE-NEXT: bge 0, .LBB510_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB510_1 ; PPC64LE-NEXT: .LBB510_3: @@ -8646,13 +8646,13 @@ define i32 @test510(i32* %ptr, i32 %val) { define i32 @test511(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test511: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB511_1: ; PPC64LE-NEXT: lwarx 3, 0, 5 ; PPC64LE-NEXT: cmpw 4, 3 ; PPC64LE-NEXT: bge 0, .LBB511_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB511_1 ; PPC64LE-NEXT: .LBB511_3: @@ -8664,13 +8664,13 @@ define i32 @test511(i32* %ptr, i32 %val) { define i32 @test512(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test512: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB512_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: cmpw 4, 5 ; PPC64LE-NEXT: bge 0, .LBB512_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB512_1 ; PPC64LE-NEXT: .LBB512_3: @@ -8682,13 +8682,13 @@ define i32 @test512(i32* %ptr, i32 %val) { define i32 @test513(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test513: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB513_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: cmpw 4, 5 ; PPC64LE-NEXT: bge 0, .LBB513_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB513_1 ; PPC64LE-NEXT: .LBB513_3: @@ -8701,13 +8701,13 @@ define i32 @test513(i32* %ptr, i32 %val) { define i32 @test514(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test514: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB514_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: cmpw 4, 5 ; PPC64LE-NEXT: bge 0, .LBB514_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB514_1 ; PPC64LE-NEXT: .LBB514_3: @@ -8720,12 +8720,12 @@ define i32 @test514(i32* %ptr, i32 %val) { define i64 @test515(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test515: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB515_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: cmpd 4, 5 ; PPC64LE-NEXT: bge 0, .LBB515_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB515_1 ; PPC64LE-NEXT: .LBB515_3: @@ -8737,13 +8737,13 @@ define i64 @test515(i64* %ptr, i64 %val) { define i64 @test516(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test516: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB516_1: ; PPC64LE-NEXT: ldarx 3, 0, 5 ; PPC64LE-NEXT: cmpd 4, 3 ; PPC64LE-NEXT: bge 0, .LBB516_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB516_1 ; PPC64LE-NEXT: .LBB516_3: @@ -8755,13 +8755,13 @@ define i64 @test516(i64* %ptr, i64 %val) { define i64 @test517(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test517: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB517_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: cmpd 4, 5 ; PPC64LE-NEXT: bge 0, .LBB517_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB517_1 ; PPC64LE-NEXT: .LBB517_3: @@ -8773,13 +8773,13 @@ define i64 @test517(i64* %ptr, i64 %val) { define i64 @test518(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test518: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB518_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: cmpd 4, 5 ; PPC64LE-NEXT: bge 0, .LBB518_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB518_1 ; PPC64LE-NEXT: .LBB518_3: @@ -8792,13 +8792,13 @@ define i64 @test518(i64* %ptr, i64 %val) { define i64 @test519(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test519: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB519_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: cmpd 4, 5 ; PPC64LE-NEXT: bge 0, .LBB519_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB519_1 ; PPC64LE-NEXT: .LBB519_3: @@ -8811,12 +8811,12 @@ define i64 @test519(i64* %ptr, i64 %val) { define i8 @test520(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test520: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB520_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: ble 0, .LBB520_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB520_1 ; PPC64LE-NEXT: .LBB520_3: @@ -8828,13 +8828,13 @@ define i8 @test520(i8* %ptr, i8 %val) { define i8 @test521(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test521: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB521_1: ; PPC64LE-NEXT: lbarx 3, 0, 5 ; PPC64LE-NEXT: cmplw 4, 3 ; PPC64LE-NEXT: ble 0, .LBB521_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB521_1 ; PPC64LE-NEXT: .LBB521_3: @@ -8846,13 +8846,13 @@ define i8 @test521(i8* %ptr, i8 %val) { define i8 @test522(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test522: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB522_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: ble 0, .LBB522_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB522_1 ; PPC64LE-NEXT: .LBB522_3: @@ -8864,13 +8864,13 @@ define i8 @test522(i8* %ptr, i8 %val) { define i8 @test523(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test523: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB523_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: ble 0, .LBB523_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB523_1 ; PPC64LE-NEXT: .LBB523_3: @@ -8883,13 +8883,13 @@ define i8 @test523(i8* %ptr, i8 %val) { define i8 @test524(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test524: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB524_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: ble 0, .LBB524_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB524_1 ; PPC64LE-NEXT: .LBB524_3: @@ -8902,12 +8902,12 @@ define i8 @test524(i8* %ptr, i8 %val) { define i16 @test525(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test525: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB525_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: ble 0, .LBB525_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB525_1 ; PPC64LE-NEXT: .LBB525_3: @@ -8919,13 +8919,13 @@ define i16 @test525(i16* %ptr, i16 %val) { define i16 @test526(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test526: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB526_1: ; PPC64LE-NEXT: lharx 3, 0, 5 ; PPC64LE-NEXT: cmplw 4, 3 ; PPC64LE-NEXT: ble 0, .LBB526_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB526_1 ; PPC64LE-NEXT: .LBB526_3: @@ -8937,13 +8937,13 @@ define i16 @test526(i16* %ptr, i16 %val) { define i16 @test527(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test527: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB527_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: ble 0, .LBB527_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB527_1 ; PPC64LE-NEXT: .LBB527_3: @@ -8955,13 +8955,13 @@ define i16 @test527(i16* %ptr, i16 %val) { define i16 @test528(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test528: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB528_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: ble 0, .LBB528_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB528_1 ; PPC64LE-NEXT: .LBB528_3: @@ -8974,13 +8974,13 @@ define i16 @test528(i16* %ptr, i16 %val) { define i16 @test529(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test529: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB529_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: ble 0, .LBB529_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB529_1 ; PPC64LE-NEXT: .LBB529_3: @@ -8993,12 +8993,12 @@ define i16 @test529(i16* %ptr, i16 %val) { define i32 @test530(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test530: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB530_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: ble 0, .LBB530_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB530_1 ; PPC64LE-NEXT: .LBB530_3: @@ -9010,13 +9010,13 @@ define i32 @test530(i32* %ptr, i32 %val) { define i32 @test531(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test531: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB531_1: ; PPC64LE-NEXT: lwarx 3, 0, 5 ; PPC64LE-NEXT: cmplw 4, 3 ; PPC64LE-NEXT: ble 0, .LBB531_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB531_1 ; PPC64LE-NEXT: .LBB531_3: @@ -9028,13 +9028,13 @@ define i32 @test531(i32* %ptr, i32 %val) { define i32 @test532(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test532: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB532_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: ble 0, .LBB532_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB532_1 ; PPC64LE-NEXT: .LBB532_3: @@ -9046,13 +9046,13 @@ define i32 @test532(i32* %ptr, i32 %val) { define i32 @test533(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test533: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB533_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: ble 0, .LBB533_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB533_1 ; PPC64LE-NEXT: .LBB533_3: @@ -9065,13 +9065,13 @@ define i32 @test533(i32* %ptr, i32 %val) { define i32 @test534(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test534: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB534_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: ble 0, .LBB534_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB534_1 ; PPC64LE-NEXT: .LBB534_3: @@ -9084,12 +9084,12 @@ define i32 @test534(i32* %ptr, i32 %val) { define i64 @test535(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test535: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB535_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: cmpld 4, 5 ; PPC64LE-NEXT: ble 0, .LBB535_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB535_1 ; PPC64LE-NEXT: .LBB535_3: @@ -9101,13 +9101,13 @@ define i64 @test535(i64* %ptr, i64 %val) { define i64 @test536(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test536: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB536_1: ; PPC64LE-NEXT: ldarx 3, 0, 5 ; PPC64LE-NEXT: cmpld 4, 3 ; PPC64LE-NEXT: ble 0, .LBB536_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB536_1 ; PPC64LE-NEXT: .LBB536_3: @@ -9119,13 +9119,13 @@ define i64 @test536(i64* %ptr, i64 %val) { define i64 @test537(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test537: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB537_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: cmpld 4, 5 ; PPC64LE-NEXT: ble 0, .LBB537_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB537_1 ; PPC64LE-NEXT: .LBB537_3: @@ -9137,13 +9137,13 @@ define i64 @test537(i64* %ptr, i64 %val) { define i64 @test538(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test538: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB538_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: cmpld 4, 5 ; PPC64LE-NEXT: ble 0, .LBB538_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB538_1 ; PPC64LE-NEXT: .LBB538_3: @@ -9156,13 +9156,13 @@ define i64 @test538(i64* %ptr, i64 %val) { define i64 @test539(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test539: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB539_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: cmpld 4, 5 ; PPC64LE-NEXT: ble 0, .LBB539_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB539_1 ; PPC64LE-NEXT: .LBB539_3: @@ -9175,12 +9175,12 @@ define i64 @test539(i64* %ptr, i64 %val) { define i8 @test540(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test540: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB540_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: bge 0, .LBB540_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB540_1 ; PPC64LE-NEXT: .LBB540_3: @@ -9192,13 +9192,13 @@ define i8 @test540(i8* %ptr, i8 %val) { define i8 @test541(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test541: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB541_1: ; PPC64LE-NEXT: lbarx 3, 0, 5 ; PPC64LE-NEXT: cmplw 4, 3 ; PPC64LE-NEXT: bge 0, .LBB541_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB541_1 ; PPC64LE-NEXT: .LBB541_3: @@ -9210,13 +9210,13 @@ define i8 @test541(i8* %ptr, i8 %val) { define i8 @test542(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test542: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB542_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: bge 0, .LBB542_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB542_1 ; PPC64LE-NEXT: .LBB542_3: @@ -9228,13 +9228,13 @@ define i8 @test542(i8* %ptr, i8 %val) { define i8 @test543(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test543: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB543_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: bge 0, .LBB543_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB543_1 ; PPC64LE-NEXT: .LBB543_3: @@ -9247,13 +9247,13 @@ define i8 @test543(i8* %ptr, i8 %val) { define i8 @test544(i8* %ptr, i8 %val) { ; PPC64LE-LABEL: test544: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB544_1: ; PPC64LE-NEXT: lbarx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: bge 0, .LBB544_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stbcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB544_1 ; PPC64LE-NEXT: .LBB544_3: @@ -9266,12 +9266,12 @@ define i8 @test544(i8* %ptr, i8 %val) { define i16 @test545(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test545: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB545_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: bge 0, .LBB545_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB545_1 ; PPC64LE-NEXT: .LBB545_3: @@ -9283,13 +9283,13 @@ define i16 @test545(i16* %ptr, i16 %val) { define i16 @test546(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test546: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB546_1: ; PPC64LE-NEXT: lharx 3, 0, 5 ; PPC64LE-NEXT: cmplw 4, 3 ; PPC64LE-NEXT: bge 0, .LBB546_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB546_1 ; PPC64LE-NEXT: .LBB546_3: @@ -9301,13 +9301,13 @@ define i16 @test546(i16* %ptr, i16 %val) { define i16 @test547(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test547: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB547_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: bge 0, .LBB547_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB547_1 ; PPC64LE-NEXT: .LBB547_3: @@ -9319,13 +9319,13 @@ define i16 @test547(i16* %ptr, i16 %val) { define i16 @test548(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test548: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB548_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: bge 0, .LBB548_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB548_1 ; PPC64LE-NEXT: .LBB548_3: @@ -9338,13 +9338,13 @@ define i16 @test548(i16* %ptr, i16 %val) { define i16 @test549(i16* %ptr, i16 %val) { ; PPC64LE-LABEL: test549: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB549_1: ; PPC64LE-NEXT: lharx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: bge 0, .LBB549_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: sthcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB549_1 ; PPC64LE-NEXT: .LBB549_3: @@ -9357,12 +9357,12 @@ define i16 @test549(i16* %ptr, i16 %val) { define i32 @test550(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test550: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB550_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: bge 0, .LBB550_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB550_1 ; PPC64LE-NEXT: .LBB550_3: @@ -9374,13 +9374,13 @@ define i32 @test550(i32* %ptr, i32 %val) { define i32 @test551(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test551: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB551_1: ; PPC64LE-NEXT: lwarx 3, 0, 5 ; PPC64LE-NEXT: cmplw 4, 3 ; PPC64LE-NEXT: bge 0, .LBB551_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB551_1 ; PPC64LE-NEXT: .LBB551_3: @@ -9392,13 +9392,13 @@ define i32 @test551(i32* %ptr, i32 %val) { define i32 @test552(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test552: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB552_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: bge 0, .LBB552_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB552_1 ; PPC64LE-NEXT: .LBB552_3: @@ -9410,13 +9410,13 @@ define i32 @test552(i32* %ptr, i32 %val) { define i32 @test553(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test553: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB553_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: bge 0, .LBB553_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB553_1 ; PPC64LE-NEXT: .LBB553_3: @@ -9429,13 +9429,13 @@ define i32 @test553(i32* %ptr, i32 %val) { define i32 @test554(i32* %ptr, i32 %val) { ; PPC64LE-LABEL: test554: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB554_1: ; PPC64LE-NEXT: lwarx 5, 0, 3 ; PPC64LE-NEXT: cmplw 4, 5 ; PPC64LE-NEXT: bge 0, .LBB554_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stwcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB554_1 ; PPC64LE-NEXT: .LBB554_3: @@ -9448,12 +9448,12 @@ define i32 @test554(i32* %ptr, i32 %val) { define i64 @test555(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test555: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: .LBB555_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: cmpld 4, 5 ; PPC64LE-NEXT: bge 0, .LBB555_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB555_1 ; PPC64LE-NEXT: .LBB555_3: @@ -9465,13 +9465,13 @@ define i64 @test555(i64* %ptr, i64 %val) { define i64 @test556(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test556: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: mr 5, 3 ; PPC64LE-NEXT: .LBB556_1: ; PPC64LE-NEXT: ldarx 3, 0, 5 ; PPC64LE-NEXT: cmpld 4, 3 ; PPC64LE-NEXT: bge 0, .LBB556_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 5 ; PPC64LE-NEXT: bne 0, .LBB556_1 ; PPC64LE-NEXT: .LBB556_3: @@ -9483,13 +9483,13 @@ define i64 @test556(i64* %ptr, i64 %val) { define i64 @test557(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test557: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB557_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: cmpld 4, 5 ; PPC64LE-NEXT: bge 0, .LBB557_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB557_1 ; PPC64LE-NEXT: .LBB557_3: @@ -9501,13 +9501,13 @@ define i64 @test557(i64* %ptr, i64 %val) { define i64 @test558(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test558: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .LBB558_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: cmpld 4, 5 ; PPC64LE-NEXT: bge 0, .LBB558_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB558_1 ; PPC64LE-NEXT: .LBB558_3: @@ -9520,13 +9520,13 @@ define i64 @test558(i64* %ptr, i64 %val) { define i64 @test559(i64* %ptr, i64 %val) { ; PPC64LE-LABEL: test559: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: .LBB559_1: ; PPC64LE-NEXT: ldarx 5, 0, 3 ; PPC64LE-NEXT: cmpld 4, 5 ; PPC64LE-NEXT: bge 0, .LBB559_3 -; PPC64LE-NEXT: # BB#2: +; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: stdcx. 4, 0, 3 ; PPC64LE-NEXT: bne 0, .LBB559_1 ; PPC64LE-NEXT: .LBB559_3: @@ -9540,7 +9540,7 @@ define i64 @test559(i64* %ptr, i64 %val) { ; The second load should never be scheduled before isync. define i32 @test_ordering0(i32* %ptr1, i32* %ptr2) { ; PPC64LE-LABEL: test_ordering0: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwz 4, 0(3) ; PPC64LE-NEXT: cmpd 7, 4, 4 ; PPC64LE-NEXT: bne- 7, .+4 @@ -9557,7 +9557,7 @@ define i32 @test_ordering0(i32* %ptr1, i32* %ptr2) { ; The second store should never be scheduled before isync. define i32 @test_ordering1(i32* %ptr1, i32 %val1, i32* %ptr2) { ; PPC64LE-LABEL: test_ordering1: -; PPC64LE: # BB#0: +; PPC64LE: # %bb.0: ; PPC64LE-NEXT: lwz 3, 0(3) ; PPC64LE-NEXT: cmpd 7, 3, 3 ; PPC64LE-NEXT: bne- 7, .+4 diff --git a/test/CodeGen/PowerPC/branch_coalesce.ll b/test/CodeGen/PowerPC/branch_coalesce.ll index 007eef27b2d75..a57dec111bca9 100644 --- a/test/CodeGen/PowerPC/branch_coalesce.ll +++ b/test/CodeGen/PowerPC/branch_coalesce.ll @@ -23,10 +23,10 @@ define double @testBranchCoal(double %a, double %b, double %c, i32 %x) { ; CHECK: blr ; CHECK-NOCOALESCE-LABEL: testBranchCoal: -; CHECK-NOCOALESCE: # BB#0: # %entry +; CHECK-NOCOALESCE: # %bb.0: # %entry ; CHECK-NOCOALESCE-NEXT: cmplwi 0, 6, 0 ; CHECK-NOCOALESCE-NEXT: bne 0, .LBB0_5 -; CHECK-NOCOALESCE-NEXT: # BB#1: # %entry +; CHECK-NOCOALESCE-NEXT: # %bb.1: # %entry ; CHECK-NOCOALESCE-NEXT: bne 0, .LBB0_6 ; CHECK-NOCOALESCE-NEXT: .LBB0_2: # %entry ; CHECK-NOCOALESCE-NEXT: beq 0, .LBB0_4 diff --git a/test/CodeGen/PowerPC/crbits.ll b/test/CodeGen/PowerPC/crbits.ll index e401179d63793..18d149558635b 100644 --- a/test/CodeGen/PowerPC/crbits.ll +++ b/test/CodeGen/PowerPC/crbits.ll @@ -1,6 +1,5 @@ -; XFAIL: * -; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s -; RUN: llc -verify-machineinstrs -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s +; RUN: llc -ppc-gpr-icmps=all -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s +; RUN: llc -ppc-gpr-icmps=all -verify-machineinstrs -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s target datalayout = "E-m:e-i64:64-n32:64" target triple = "powerpc64-unknown-linux-gnu" diff --git a/test/CodeGen/PowerPC/cxx_tlscc64.ll b/test/CodeGen/PowerPC/cxx_tlscc64.ll index 0f45652cd29e3..cfa243f200af7 100644 --- a/test/CodeGen/PowerPC/cxx_tlscc64.ll +++ b/test/CodeGen/PowerPC/cxx_tlscc64.ll @@ -40,4 +40,4 @@ define cxx_fast_tlscc i32* @_ZTW4sum2() #0 { ret i32* @sum1 } -attributes #0 = { nounwind "no-frame-pointer-elim"="true" } \ No newline at end of file +attributes #0 = { nounwind "no-frame-pointer-elim"="true" } diff --git a/test/CodeGen/PowerPC/debuginfo-split-int.ll b/test/CodeGen/PowerPC/debuginfo-split-int.ll index 4bcf43c9dae24..e6f0ee2020823 100644 --- a/test/CodeGen/PowerPC/debuginfo-split-int.ll +++ b/test/CodeGen/PowerPC/debuginfo-split-int.ll @@ -27,9 +27,9 @@ target triple = "ppc32" ; ; High 32 bits in R3, low 32 bits in R4 ; CHECK: %0:gprc = COPY %r3 -; CHECK: DBG_VALUE debug-use %0, debug-use _, [[DL]], !DIExpression(DW_OP_LLVM_fragment, 0, 32) +; CHECK: DBG_VALUE debug-use %0, debug-use %noreg, [[DL]], !DIExpression(DW_OP_LLVM_fragment, 0, 32) ; CHECK: %1:gprc = COPY %r4 -; CHECK: DBG_VALUE debug-use %1, debug-use _, [[DL]], !DIExpression(DW_OP_LLVM_fragment, 32, 32) +; CHECK: DBG_VALUE debug-use %1, debug-use %noreg, [[DL]], !DIExpression(DW_OP_LLVM_fragment, 32, 32) define void @bar() local_unnamed_addr #0 !dbg !6 { %1 = alloca i64, align 8 %2 = tail call i64 @foo() diff --git a/test/CodeGen/PowerPC/expand-isel.ll b/test/CodeGen/PowerPC/expand-isel.ll index 76479705f020a..bae3c8912d618 100644 --- a/test/CodeGen/PowerPC/expand-isel.ll +++ b/test/CodeGen/PowerPC/expand-isel.ll @@ -1,7 +1,6 @@ -; XFAIL: * target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" target triple = "powerpc64-unknown-linux-gnu" -; RUN: llc -verify-machineinstrs -O2 -ppc-asm-full-reg-names -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck %s --implicit-check-not isel +; RUN: llc -ppc-gpr-icmps=all -verify-machineinstrs -O2 -ppc-asm-full-reg-names -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck %s --implicit-check-not isel ; Function Attrs: norecurse nounwind readnone define signext i32 @testExpandISELToIfElse(i32 signext %i, i32 signext %j) { entry: @@ -213,9 +212,12 @@ cleanup: ret i32 %retval.0 ; CHECK-LABEL: @testComplexISEL -; CHECK-DAG: [[LI:r[0-9]+]], 1 -; CHECK-DAG: cmplwi [[LD:r[0-9]+]], 0 -; CHECK: bnelr cr0 +; CHECK: cmplwi r3, 0 +; CHECK: li r3, 1 +; CHECK: beq cr0, [[TGT:.LBB[0-9_]+]] +; CHECK: clrldi r3, r3, 32 +; CHECK: blr +; CHECK: [[TGT]] ; CHECK: xor [[XOR:r[0-9]+]] ; CHECK: cntlzd [[CZ:r[0-9]+]], [[XOR]] ; CHECK: rldicl [[SH:r[0-9]+]], [[CZ]], 58, 63 diff --git a/test/CodeGen/PowerPC/fabs.ll b/test/CodeGen/PowerPC/fabs.ll index c8cbd00b4dcf9..369803af9794b 100644 --- a/test/CodeGen/PowerPC/fabs.ll +++ b/test/CodeGen/PowerPC/fabs.ll @@ -2,7 +2,7 @@ define double @fabs(double %f) { ; CHECK-LABEL: fabs: -; CHECK: ; BB#0: +; CHECK: ; %bb.0: ; CHECK-NEXT: fabs f1, f1 ; CHECK-NEXT: blr ; @@ -12,7 +12,7 @@ define double @fabs(double %f) { define float @bitcast_fabs(float %x) { ; CHECK-LABEL: bitcast_fabs: -; CHECK: ; BB#0: +; CHECK: ; %bb.0: ; CHECK-NEXT: stfs f1, -8(r1) ; CHECK-NEXT: nop ; CHECK-NEXT: nop diff --git a/test/CodeGen/PowerPC/fma-aggr-FMF.ll b/test/CodeGen/PowerPC/fma-aggr-FMF.ll index 8e97115bd1f2b..e861c9df37aba 100644 --- a/test/CodeGen/PowerPC/fma-aggr-FMF.ll +++ b/test/CodeGen/PowerPC/fma-aggr-FMF.ll @@ -3,7 +3,7 @@ define float @can_fma_with_fewer_uses(float %f1, float %f2, float %f3, float %f4) { ; CHECK-LABEL: can_fma_with_fewer_uses: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: xsmulsp 0, 1, 2 ; CHECK-NEXT: fmr 1, 0 ; CHECK-NEXT: xsmaddasp 1, 3, 4 @@ -21,7 +21,7 @@ define float @can_fma_with_fewer_uses(float %f1, float %f2, float %f3, float %f4 ; around beside the fma. define float @no_fma_with_fewer_uses(float %f1, float %f2, float %f3, float %f4) { ; CHECK-LABEL: no_fma_with_fewer_uses: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: xsmulsp 0, 3, 4 ; CHECK-NEXT: xsmulsp 13, 1, 2 ; CHECK-NEXT: xsmaddasp 0, 1, 2 diff --git a/test/CodeGen/PowerPC/fp64-to-int16.ll b/test/CodeGen/PowerPC/fp64-to-int16.ll index 0c5274d9426c2..360a98665182e 100644 --- a/test/CodeGen/PowerPC/fp64-to-int16.ll +++ b/test/CodeGen/PowerPC/fp64-to-int16.ll @@ -4,7 +4,7 @@ target triple = "powerpc64le--linux-gnu" define i1 @Test(double %a) { ; CHECK-LABEL: Test: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xscvdpsxws 1, 1 ; CHECK-NEXT: mfvsrwz 3, 1 ; CHECK-NEXT: xori 3, 3, 65534 diff --git a/test/CodeGen/PowerPC/hello-reloc.s b/test/CodeGen/PowerPC/hello-reloc.s index bbf1e7cacbd46..66bc9a84f5c20 100644 --- a/test/CodeGen/PowerPC/hello-reloc.s +++ b/test/CodeGen/PowerPC/hello-reloc.s @@ -11,7 +11,7 @@ .globl _main .align 4 _main: ; @main -; BB#0: ; %entry +; %bb.0: ; %entry mflr r0 stw r31, -4(r1) stw r0, 8(r1) diff --git a/test/CodeGen/PowerPC/licm-remat.ll b/test/CodeGen/PowerPC/licm-remat.ll index cbd1af62b8429..393c56bcb8644 100644 --- a/test/CodeGen/PowerPC/licm-remat.ll +++ b/test/CodeGen/PowerPC/licm-remat.ll @@ -18,7 +18,7 @@ declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture writeonly, i8* nocapture r define linkonce_odr void @ZN6snappyDecompressor_(%"class.snappy::SnappyDecompressor"* %this, %"class.snappy::SnappyIOVecWriter"* %writer) { ; CHECK-LABEL: ZN6snappyDecompressor_: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK: addis 3, 2, _ZN6snappy8internalL8wordmaskE@toc@ha ; CHECK-DAG: addi 25, 3, _ZN6snappy8internalL8wordmaskE@toc@l ; CHECK-DAG: addis 4, 2, _ZN6snappy8internalL10char_tableE@toc@ha diff --git a/test/CodeGen/PowerPC/licm-tocReg.ll b/test/CodeGen/PowerPC/licm-tocReg.ll index 824d554991af3..efbec9091a5a2 100644 --- a/test/CodeGen/PowerPC/licm-tocReg.ll +++ b/test/CodeGen/PowerPC/licm-tocReg.ll @@ -64,7 +64,7 @@ define signext i32 @test(i32 (i32)* nocapture %FP) local_unnamed_addr #0 { ; CHECK-LABEL: test: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis 6, 2, .LC0@toc@ha ; CHECK-NEXT: addis 4, 2, .LC1@toc@ha ; CHECK-NEXT: ld 5, .LC1@toc@l(4) diff --git a/test/CodeGen/PowerPC/logic-ops-on-compares.ll b/test/CodeGen/PowerPC/logic-ops-on-compares.ll index e448afd03eaab..b1b26f0ab7607 100644 --- a/test/CodeGen/PowerPC/logic-ops-on-compares.ll +++ b/test/CodeGen/PowerPC/logic-ops-on-compares.ll @@ -43,11 +43,11 @@ return: ; preds = %if.end, %if.then define void @neg_truncate_i32_eq(i32 *%ptr) { ; CHECK-LABEL: neg_truncate_i32_eq: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lwz r3, 0(r3) ; CHECK-NEXT: rldicl. r3, r3, 0, 63 ; CHECK-NEXT: bclr 12, eq, 0 -; CHECK-NEXT: # BB#1: # %if.end29.thread136 +; CHECK-NEXT: # %bb.1: # %if.end29.thread136 entry: %0 = load i32, i32* %ptr, align 4 %rem17127 = and i32 %0, 1 @@ -101,11 +101,11 @@ return: ; preds = %if.end, %if.then define void @neg_truncate_i64_eq(i64 *%ptr) { ; CHECK-LABEL: neg_truncate_i64_eq: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: ld r3, 0(r3) ; CHECK-NEXT: rldicl. r3, r3, 0, 63 ; CHECK-NEXT: bclr 12, eq, 0 -; CHECK-NEXT: # BB#1: # %if.end29.thread136 +; CHECK-NEXT: # %bb.1: # %if.end29.thread136 entry: %0 = load i64, i64* %ptr, align 4 %rem17127 = and i64 %0, 1 @@ -161,11 +161,11 @@ return: ; preds = %if.end, %if.then define void @neg_truncate_i64_ne(i64 *%ptr) { ; CHECK-LABEL: neg_truncate_i64_ne: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: ld r3, 0(r3) ; CHECK-NEXT: andi. r3, r3, 1 ; CHECK-NEXT: bclr 12, gt, 0 -; CHECK-NEXT: # BB#1: # %if.end29.thread136 +; CHECK-NEXT: # %bb.1: # %if.end29.thread136 entry: %0 = load i64, i64* %ptr, align 4 %rem17127 = and i64 %0, 1 diff --git a/test/CodeGen/PowerPC/machine-combiner.ll b/test/CodeGen/PowerPC/machine-combiner.ll index e026017710ef3..c7337e3637e31 100644 --- a/test/CodeGen/PowerPC/machine-combiner.ll +++ b/test/CodeGen/PowerPC/machine-combiner.ll @@ -8,7 +8,7 @@ target triple = "powerpc64-unknown-linux-gnu" define float @reassociate_adds1(float %x0, float %x1, float %x2, float %x3) { ; CHECK-LABEL: reassociate_adds1: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK: fadds [[REG0:[0-9]+]], 1, 2 ; CHECK: fadds [[REG1:[0-9]+]], 3, 4 ; CHECK: fadds 1, [[REG0]], [[REG1]] @@ -22,7 +22,7 @@ define float @reassociate_adds1(float %x0, float %x1, float %x2, float %x3) { define float @reassociate_adds2(float %x0, float %x1, float %x2, float %x3) { ; CHECK-LABEL: reassociate_adds2: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK: fadds [[REG0:[0-9]+]], 1, 2 ; CHECK: fadds [[REG1:[0-9]+]], 3, 4 ; CHECK: fadds 1, [[REG0]], [[REG1]] @@ -36,7 +36,7 @@ define float @reassociate_adds2(float %x0, float %x1, float %x2, float %x3) { define float @reassociate_adds3(float %x0, float %x1, float %x2, float %x3) { ; CHECK-LABEL: reassociate_adds3: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK: fadds [[REG0:[0-9]+]], 1, 2 ; CHECK: fadds [[REG1:[0-9]+]], 3, 4 ; CHECK: fadds 1, [[REG0]], [[REG1]] @@ -50,7 +50,7 @@ define float @reassociate_adds3(float %x0, float %x1, float %x2, float %x3) { define float @reassociate_adds4(float %x0, float %x1, float %x2, float %x3) { ; CHECK-LABEL: reassociate_adds4: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK: fadds [[REG0:[0-9]+]], 1, 2 ; CHECK: fadds [[REG1:[0-9]+]], 3, 4 ; CHECK: fadds 1, [[REG0]], [[REG1]] @@ -67,7 +67,7 @@ define float @reassociate_adds4(float %x0, float %x1, float %x2, float %x3) { define float @reassociate_adds5(float %x0, float %x1, float %x2, float %x3, float %x4, float %x5, float %x6, float %x7) { ; CHECK-LABEL: reassociate_adds5: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK: fadds [[REG12:[0-9]+]], 5, 6 ; CHECK: fadds [[REG0:[0-9]+]], 1, 2 ; CHECK: fadds [[REG11:[0-9]+]], 3, 4 @@ -91,7 +91,7 @@ define float @reassociate_adds5(float %x0, float %x1, float %x2, float %x3, floa define <4 x float> @vector_reassociate_adds1(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, <4 x float> %x3) { ; CHECK-LABEL: vector_reassociate_adds1: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-QPX: qvfadds [[REG0:[0-9]+]], 1, 2 ; CHECK-QPX: qvfadds [[REG1:[0-9]+]], 3, 4 ; CHECK-QPX: qvfadds 1, [[REG0]], [[REG1]] @@ -108,7 +108,7 @@ define <4 x float> @vector_reassociate_adds1(<4 x float> %x0, <4 x float> %x1, < define <4 x float> @vector_reassociate_adds2(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, <4 x float> %x3) { ; CHECK-LABEL: vector_reassociate_adds2: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-QPX: qvfadds [[REG0:[0-9]+]], 1, 2 ; CHECK-QPX: qvfadds [[REG1:[0-9]+]], 3, 4 ; CHECK-QPX: qvfadds 1, [[REG0]], [[REG1]] @@ -125,7 +125,7 @@ define <4 x float> @vector_reassociate_adds2(<4 x float> %x0, <4 x float> %x1, < define <4 x float> @vector_reassociate_adds3(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, <4 x float> %x3) { ; CHECK-LABEL: vector_reassociate_adds3: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-QPX: qvfadds [[REG0:[0-9]+]], 1, 2 ; CHECK-QPX: qvfadds [[REG1:[0-9]+]], 3, 4 ; CHECK-QPX: qvfadds 1, [[REG0]], [[REG1]] @@ -142,7 +142,7 @@ define <4 x float> @vector_reassociate_adds3(<4 x float> %x0, <4 x float> %x1, < define <4 x float> @vector_reassociate_adds4(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, <4 x float> %x3) { ; CHECK-LABEL: vector_reassociate_adds4: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-QPX: qvfadds [[REG0:[0-9]+]], 1, 2 ; CHECK-QPX: qvfadds [[REG1:[0-9]+]], 3, 4 ; CHECK-QPX: qvfadds 1, [[REG0]], [[REG1]] diff --git a/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll b/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll index 27e9c1b8819d8..3bfc0de1b8724 100644 --- a/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll +++ b/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll @@ -1,6 +1,5 @@ -; XFAIL: * ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -verify-machineinstrs -mcpu=pwr8 < %s | FileCheck %s +; RUN: llc -ppc-gpr-icmps=all -verify-machineinstrs -mcpu=pwr8 < %s | FileCheck %s target datalayout = "e-m:e-i64:64-n32:64" target triple = "powerpc64le-unknown-linux-gnu" @@ -18,7 +17,7 @@ declare signext i32 @memcmp(i8* nocapture, i8* nocapture, i64) local_unnamed_add ; Check 4 bytes - requires 1 load for each param. define signext i32 @zeroEqualityTest02(i8* %x, i8* %y) { ; CHECK-LABEL: zeroEqualityTest02: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: lwz 3, 0(3) ; CHECK-NEXT: lwz 4, 0(4) ; CHECK-NEXT: xor 3, 3, 4 @@ -35,19 +34,21 @@ define signext i32 @zeroEqualityTest02(i8* %x, i8* %y) { ; Check 16 bytes - requires 2 loads for each param (or use vectors?). define signext i32 @zeroEqualityTest01(i8* %x, i8* %y) { ; CHECK-LABEL: zeroEqualityTest01: -; CHECK: # BB#0: # %loadbb +; CHECK: # %bb.0: ; CHECK-NEXT: ld 5, 0(3) ; CHECK-NEXT: ld 6, 0(4) ; CHECK-NEXT: cmpld 5, 6 ; CHECK-NEXT: bne 0, .LBB1_2 -; CHECK-NEXT: # BB#1: # %loadbb1 +; CHECK-NEXT: # %bb.1: # %loadbb1 ; CHECK-NEXT: ld 3, 8(3) ; CHECK-NEXT: ld 4, 8(4) ; CHECK-NEXT: cmpld 3, 4 ; CHECK-NEXT: li 3, 0 -; CHECK-NEXT: beqlr 0 +; CHECK-NEXT: beq 0, .LBB1_3 ; CHECK-NEXT: .LBB1_2: # %res_block ; CHECK-NEXT: li 3, 1 +; CHECK-NEXT: .LBB1_3: # %endblock +; CHECK-NEXT: clrldi 3, 3, 32 ; CHECK-NEXT: blr %call = tail call signext i32 @memcmp(i8* %x, i8* %y, i64 16) %not.tobool = icmp ne i32 %call, 0 @@ -58,24 +59,26 @@ define signext i32 @zeroEqualityTest01(i8* %x, i8* %y) { ; Check 7 bytes - requires 3 loads for each param. define signext i32 @zeroEqualityTest03(i8* %x, i8* %y) { ; CHECK-LABEL: zeroEqualityTest03: -; CHECK: # BB#0: # %loadbb +; CHECK: # %bb.0: ; CHECK-NEXT: lwz 5, 0(3) ; CHECK-NEXT: lwz 6, 0(4) ; CHECK-NEXT: cmplw 5, 6 ; CHECK-NEXT: bne 0, .LBB2_3 -; CHECK-NEXT: # BB#1: # %loadbb1 +; CHECK-NEXT: # %bb.1: # %loadbb1 ; CHECK-NEXT: lhz 5, 4(3) ; CHECK-NEXT: lhz 6, 4(4) ; CHECK-NEXT: cmplw 5, 6 ; CHECK-NEXT: bne 0, .LBB2_3 -; CHECK-NEXT: # BB#2: # %loadbb2 +; CHECK-NEXT: # %bb.2: # %loadbb2 ; CHECK-NEXT: lbz 3, 6(3) ; CHECK-NEXT: lbz 4, 6(4) ; CHECK-NEXT: cmplw 3, 4 ; CHECK-NEXT: li 3, 0 -; CHECK-NEXT: beqlr 0 +; CHECK-NEXT: beq 0, .LBB2_4 ; CHECK-NEXT: .LBB2_3: # %res_block ; CHECK-NEXT: li 3, 1 +; CHECK-NEXT: .LBB2_4: # %endblock +; CHECK-NEXT: clrldi 3, 3, 32 ; CHECK-NEXT: blr %call = tail call signext i32 @memcmp(i8* %x, i8* %y, i64 7) %not.lnot = icmp ne i32 %call, 0 @@ -86,7 +89,7 @@ define signext i32 @zeroEqualityTest03(i8* %x, i8* %y) { ; Validate with > 0 define signext i32 @zeroEqualityTest04() { ; CHECK-LABEL: zeroEqualityTest04: -; CHECK: # BB#0: # %loadbb +; CHECK: # %bb.0: ; CHECK-NEXT: addis 3, 2, .LzeroEqualityTest02.buffer1@toc@ha ; CHECK-NEXT: addis 4, 2, .LzeroEqualityTest02.buffer2@toc@ha ; CHECK-NEXT: addi 6, 3, .LzeroEqualityTest02.buffer1@toc@l @@ -95,7 +98,7 @@ define signext i32 @zeroEqualityTest04() { ; CHECK-NEXT: ldbrx 4, 0, 5 ; CHECK-NEXT: cmpld 3, 4 ; CHECK-NEXT: bne 0, .LBB3_2 -; CHECK-NEXT: # BB#1: # %loadbb1 +; CHECK-NEXT: # %bb.1: # %loadbb1 ; CHECK-NEXT: li 4, 8 ; CHECK-NEXT: ldbrx 3, 6, 4 ; CHECK-NEXT: ldbrx 4, 5, 4 @@ -108,7 +111,8 @@ define signext i32 @zeroEqualityTest04() { ; CHECK-NEXT: li 12, -1 ; CHECK-NEXT: isel 5, 12, 11, 0 ; CHECK-NEXT: .LBB3_3: # %endblock -; CHECK-NEXT: neg 3, 5 +; CHECK-NEXT: extsw 3, 5 +; CHECK-NEXT: neg 3, 3 ; CHECK-NEXT: rldicl 3, 3, 1, 63 ; CHECK-NEXT: xori 3, 3, 1 ; CHECK-NEXT: blr @@ -121,7 +125,7 @@ define signext i32 @zeroEqualityTest04() { ; Validate with < 0 define signext i32 @zeroEqualityTest05() { ; CHECK-LABEL: zeroEqualityTest05: -; CHECK: # BB#0: # %loadbb +; CHECK: # %bb.0: ; CHECK-NEXT: addis 3, 2, .LzeroEqualityTest03.buffer1@toc@ha ; CHECK-NEXT: addis 4, 2, .LzeroEqualityTest03.buffer2@toc@ha ; CHECK-NEXT: addi 6, 3, .LzeroEqualityTest03.buffer1@toc@l @@ -130,7 +134,7 @@ define signext i32 @zeroEqualityTest05() { ; CHECK-NEXT: ldbrx 4, 0, 5 ; CHECK-NEXT: cmpld 3, 4 ; CHECK-NEXT: bne 0, .LBB4_2 -; CHECK-NEXT: # BB#1: # %loadbb1 +; CHECK-NEXT: # %bb.1: # %loadbb1 ; CHECK-NEXT: li 4, 8 ; CHECK-NEXT: ldbrx 3, 6, 4 ; CHECK-NEXT: ldbrx 4, 5, 4 @@ -156,7 +160,7 @@ define signext i32 @zeroEqualityTest05() { ; Validate with memcmp()?: define signext i32 @equalityFoldTwoConstants() { ; CHECK-LABEL: equalityFoldTwoConstants: -; CHECK: # BB#0: # %endblock +; CHECK: # %bb.0: # %endblock ; CHECK-NEXT: li 3, 1 ; CHECK-NEXT: blr %call = tail call signext i32 @memcmp(i8* bitcast ([15 x i32]* @zeroEqualityTest04.buffer1 to i8*), i8* bitcast ([15 x i32]* @zeroEqualityTest04.buffer2 to i8*), i64 16) @@ -167,13 +171,13 @@ define signext i32 @equalityFoldTwoConstants() { define signext i32 @equalityFoldOneConstant(i8* %X) { ; CHECK-LABEL: equalityFoldOneConstant: -; CHECK: # BB#0: # %loadbb -; CHECK-NEXT: li 4, 1 -; CHECK-NEXT: ld 5, 0(3) -; CHECK-NEXT: sldi 4, 4, 32 -; CHECK-NEXT: cmpld 5, 4 +; CHECK: # %bb.0: +; CHECK-NEXT: li 5, 1 +; CHECK-NEXT: ld 4, 0(3) +; CHECK-NEXT: sldi 5, 5, 32 +; CHECK-NEXT: cmpld 4, 5 ; CHECK-NEXT: bne 0, .LBB6_2 -; CHECK-NEXT: # BB#1: # %loadbb1 +; CHECK-NEXT: # %bb.1: # %loadbb1 ; CHECK-NEXT: li 4, 3 ; CHECK-NEXT: ld 3, 8(3) ; CHECK-NEXT: sldi 4, 4, 32 @@ -195,7 +199,7 @@ define signext i32 @equalityFoldOneConstant(i8* %X) { define i1 @length2_eq_nobuiltin_attr(i8* %X, i8* %Y) { ; CHECK-LABEL: length2_eq_nobuiltin_attr: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: mflr 0 ; CHECK-NEXT: std 0, 16(1) ; CHECK-NEXT: stdu 1, -32(1) diff --git a/test/CodeGen/PowerPC/memcmp.ll b/test/CodeGen/PowerPC/memcmp.ll index 36ba5256becb8..4aa5b400dd7c4 100644 --- a/test/CodeGen/PowerPC/memcmp.ll +++ b/test/CodeGen/PowerPC/memcmp.ll @@ -3,14 +3,15 @@ define signext i32 @memcmp8(i32* nocapture readonly %buffer1, i32* nocapture readonly %buffer2) { ; CHECK-LABEL: memcmp8: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: ldbrx 3, 0, 3 ; CHECK-NEXT: ldbrx 4, 0, 4 -; CHECK-NEXT: li 5, 0 -; CHECK-NEXT: cmpld 3, 4 -; CHECK-NEXT: li 3, 1 -; CHECK-NEXT: isel 4, 3, 5, 1 -; CHECK-NEXT: isel 3, 3, 5, 0 +; CHECK-NEXT: subfc 5, 3, 4 +; CHECK-NEXT: subfe 5, 4, 4 +; CHECK-NEXT: subfc 4, 4, 3 +; CHECK-NEXT: subfe 3, 3, 3 +; CHECK-NEXT: neg 4, 5 +; CHECK-NEXT: neg 3, 3 ; CHECK-NEXT: subf 3, 3, 4 ; CHECK-NEXT: extsw 3, 3 ; CHECK-NEXT: blr @@ -22,7 +23,7 @@ define signext i32 @memcmp8(i32* nocapture readonly %buffer1, i32* nocapture rea define signext i32 @memcmp4(i32* nocapture readonly %buffer1, i32* nocapture readonly %buffer2) { ; CHECK-LABEL: memcmp4: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: lwbrx 3, 0, 3 ; CHECK-NEXT: lwbrx 4, 0, 4 ; CHECK-NEXT: sub 5, 4, 3 @@ -40,7 +41,7 @@ define signext i32 @memcmp4(i32* nocapture readonly %buffer1, i32* nocapture rea define signext i32 @memcmp2(i32* nocapture readonly %buffer1, i32* nocapture readonly %buffer2) { ; CHECK-LABEL: memcmp2: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: lhbrx 3, 0, 3 ; CHECK-NEXT: lhbrx 4, 0, 4 ; CHECK-NEXT: subf 3, 4, 3 @@ -54,7 +55,7 @@ define signext i32 @memcmp2(i32* nocapture readonly %buffer1, i32* nocapture rea define signext i32 @memcmp1(i32* nocapture readonly %buffer1, i32* nocapture readonly %buffer2) { ; CHECK-LABEL: memcmp1: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: lbz 3, 0(3) ; CHECK-NEXT: lbz 4, 0(4) ; CHECK-NEXT: subf 3, 4, 3 diff --git a/test/CodeGen/PowerPC/negate-i1.ll b/test/CodeGen/PowerPC/negate-i1.ll index c6a7867fe9dbc..a56048d67a873 100644 --- a/test/CodeGen/PowerPC/negate-i1.ll +++ b/test/CodeGen/PowerPC/negate-i1.ll @@ -4,7 +4,7 @@ define i32 @select_i32_neg1_or_0(i1 %a) { ; CHECK-LABEL: select_i32_neg1_or_0: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: clrldi 3, 3, 63 ; CHECK-NEXT: neg 3, 3 ; CHECK-NEXT: blr @@ -15,7 +15,7 @@ define i32 @select_i32_neg1_or_0(i1 %a) { define i32 @select_i32_neg1_or_0_zeroext(i1 zeroext %a) { ; CHECK-LABEL: select_i32_neg1_or_0_zeroext: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: neg 3, 3 ; CHECK-NEXT: blr ; diff --git a/test/CodeGen/PowerPC/optcmp.ll b/test/CodeGen/PowerPC/optcmp.ll index 68ac832a039d5..acb5b4e6f67ce 100644 --- a/test/CodeGen/PowerPC/optcmp.ll +++ b/test/CodeGen/PowerPC/optcmp.ll @@ -1,6 +1,5 @@ -; XFAIL: * -; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 -mattr=-crbits -disable-ppc-cmp-opt=0 | FileCheck %s -; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 -mattr=-crbits -disable-ppc-cmp-opt=0 -ppc-gen-isel=false | FileCheck --check-prefix=CHECK-NO-ISEL %s +; RUN: llc -ppc-gpr-icmps=all -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 -mattr=-crbits -disable-ppc-cmp-opt=0 | FileCheck %s +; RUN: llc -ppc-gpr-icmps=all -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 -mattr=-crbits -disable-ppc-cmp-opt=0 -ppc-gen-isel=false | FileCheck --check-prefix=CHECK-NO-ISEL %s target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target triple = "powerpc64-unknown-linux-gnu" diff --git a/test/CodeGen/PowerPC/ppc-crbits-onoff.ll b/test/CodeGen/PowerPC/ppc-crbits-onoff.ll index 50a5192ce76ab..c5546254fe38f 100644 --- a/test/CodeGen/PowerPC/ppc-crbits-onoff.ll +++ b/test/CodeGen/PowerPC/ppc-crbits-onoff.ll @@ -1,6 +1,5 @@ -; XFAIL: * -; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s -; RUN: llc -verify-machineinstrs -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s +; RUN: llc -ppc-gpr-icmps=all -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s +; RUN: llc -ppc-gpr-icmps=all -verify-machineinstrs -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s target datalayout = "E-m:e-i64:64-n32:64" target triple = "powerpc64-unknown-linux-gnu" diff --git a/test/CodeGen/PowerPC/ppc32-align-long-double-sf.ll b/test/CodeGen/PowerPC/ppc32-align-long-double-sf.ll index c8435a97b7966..740bc787ec9ab 100644 --- a/test/CodeGen/PowerPC/ppc32-align-long-double-sf.ll +++ b/test/CodeGen/PowerPC/ppc32-align-long-double-sf.ll @@ -18,4 +18,4 @@ declare i32 @printf(i8* nocapture readonly, ...) #0 attributes #0 = { "use-soft-float"="true" } - \ No newline at end of file + diff --git a/test/CodeGen/PowerPC/ppc32-nest.ll b/test/CodeGen/PowerPC/ppc32-nest.ll index 221e8be295158..b933edcf61631 100644 --- a/test/CodeGen/PowerPC/ppc32-nest.ll +++ b/test/CodeGen/PowerPC/ppc32-nest.ll @@ -7,7 +7,7 @@ target triple = "powerpc-unknown-linux-gnu" define i8* @nest_receiver(i8* nest %arg) nounwind { ; CHECK-LABEL: nest_receiver: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: mr 3, 11 ; CHECK-NEXT: blr diff --git a/test/CodeGen/PowerPC/ppc64-nest.ll b/test/CodeGen/PowerPC/ppc64-nest.ll index 14872632e8140..cd2366cfa4504 100644 --- a/test/CodeGen/PowerPC/ppc64-nest.ll +++ b/test/CodeGen/PowerPC/ppc64-nest.ll @@ -7,7 +7,7 @@ target triple = "powerpc64-unknown-linux-gnu" define i8* @nest_receiver(i8* nest %arg) nounwind { ; CHECK-LABEL: nest_receiver: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: mr 3, 11 ; CHECK-NEXT: blr diff --git a/test/CodeGen/PowerPC/pr32140.ll b/test/CodeGen/PowerPC/pr32140.ll index 827a90404e4b1..3feb9bd9c9e19 100644 --- a/test/CodeGen/PowerPC/pr32140.ll +++ b/test/CodeGen/PowerPC/pr32140.ll @@ -9,7 +9,7 @@ define void @bswapStorei64Toi32() { ; CHECK-LABEL: bswapStorei64Toi32: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK: lwa 3, 0(3) ; CHECK-NEXT: rldicl 3, 3, 32, 32 ; CHECK-NEXT: stwbrx 3, 0, 4 @@ -25,7 +25,7 @@ entry: define void @bswapStorei32Toi16() { ; CHECK-LABEL: bswapStorei32Toi16: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK: lha 3, 0(3) ; CHECK-NEXT: srwi 3, 3, 16 ; CHECK-NEXT: sthbrx 3, 0, 4 @@ -41,7 +41,7 @@ entry: define void @bswapStorei64Toi16() { ; CHECK-LABEL: bswapStorei64Toi16: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK: lha 3, 0(3) ; CHECK-NEXT: rldicl 3, 3, 16, 48 ; CHECK-NEXT: sthbrx 3, 0, 4 diff --git a/test/CodeGen/PowerPC/pr33093.ll b/test/CodeGen/PowerPC/pr33093.ll index fc28bcfd0ca85..af0350e17fd92 100644 --- a/test/CodeGen/PowerPC/pr33093.ll +++ b/test/CodeGen/PowerPC/pr33093.ll @@ -4,7 +4,7 @@ define zeroext i32 @ReverseBits(i32 zeroext %n) { ; CHECK-LABEL: ReverseBits: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lis 4, -21846 ; CHECK-NEXT: lis 5, 21845 ; CHECK-NEXT: slwi 6, 3, 1 @@ -68,7 +68,7 @@ entry: define i64 @ReverseBits64(i64 %n) { ; CHECK-LABEL: ReverseBits64: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lis 4, -21846 ; CHECK-NEXT: lis 5, 21845 ; CHECK-NEXT: lis 6, -13108 diff --git a/test/CodeGen/PowerPC/quadint-return.ll b/test/CodeGen/PowerPC/quadint-return.ll index 2cc995f3f207e..e9681071bf2a1 100644 --- a/test/CodeGen/PowerPC/quadint-return.ll +++ b/test/CodeGen/PowerPC/quadint-return.ll @@ -14,6 +14,6 @@ entry: ; CHECK: ********** Function: foo ; CHECK: ********** FAST REGISTER ALLOCATION ********** -; CHECK: %x3 = COPY %vreg -; CHECK-NEXT: %x4 = COPY %vreg +; CHECK: %x3 = COPY %{{[0-9]+}} +; CHECK-NEXT: %x4 = COPY %{{[0-9]+}} ; CHECK-NEXT: BLR diff --git a/test/CodeGen/PowerPC/select-addrRegRegOnly.ll b/test/CodeGen/PowerPC/select-addrRegRegOnly.ll index 6be31eaea7432..46b23ff04f2be 100644 --- a/test/CodeGen/PowerPC/select-addrRegRegOnly.ll +++ b/test/CodeGen/PowerPC/select-addrRegRegOnly.ll @@ -4,7 +4,7 @@ ; Function Attrs: norecurse nounwind readonly define float @testSingleAccess(i32* nocapture readonly %arr) local_unnamed_addr #0 { ; CHECK-LABEL: testSingleAccess: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addi 3, 3, 8 ; CHECK-NEXT: lfiwax 0, 0, 3 ; CHECK-NEXT: xscvsxdsp 1, 0 @@ -19,7 +19,7 @@ entry: ; Function Attrs: norecurse nounwind readonly define float @testMultipleAccess(i32* nocapture readonly %arr) local_unnamed_addr #0 { ; CHECK-LABEL: testMultipleAccess: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lwz 4, 8(3) ; CHECK-NEXT: lwz 12, 12(3) ; CHECK-NEXT: add 3, 12, 4 diff --git a/test/CodeGen/PowerPC/select_const.ll b/test/CodeGen/PowerPC/select_const.ll index fd864805abd81..178d9187e3b46 100644 --- a/test/CodeGen/PowerPC/select_const.ll +++ b/test/CodeGen/PowerPC/select_const.ll @@ -9,7 +9,7 @@ define i32 @select_0_or_1(i1 %cond) { ; ALL-LABEL: select_0_or_1: -; ALL: # BB#0: +; ALL: # %bb.0: ; ALL-NEXT: not 3, 3 ; ALL-NEXT: clrldi 3, 3, 63 ; ALL-NEXT: blr @@ -19,7 +19,7 @@ define i32 @select_0_or_1(i1 %cond) { define i32 @select_0_or_1_zeroext(i1 zeroext %cond) { ; ALL-LABEL: select_0_or_1_zeroext: -; ALL: # BB#0: +; ALL: # %bb.0: ; ALL-NEXT: xori 3, 3, 1 ; ALL-NEXT: blr %sel = select i1 %cond, i32 0, i32 1 @@ -28,7 +28,7 @@ define i32 @select_0_or_1_zeroext(i1 zeroext %cond) { define i32 @select_0_or_1_signext(i1 signext %cond) { ; ALL-LABEL: select_0_or_1_signext: -; ALL: # BB#0: +; ALL: # %bb.0: ; ALL-NEXT: not 3, 3 ; ALL-NEXT: clrldi 3, 3, 63 ; ALL-NEXT: blr @@ -40,7 +40,7 @@ define i32 @select_0_or_1_signext(i1 signext %cond) { define i32 @select_1_or_0(i1 %cond) { ; ALL-LABEL: select_1_or_0: -; ALL: # BB#0: +; ALL: # %bb.0: ; ALL-NEXT: clrldi 3, 3, 63 ; ALL-NEXT: blr %sel = select i1 %cond, i32 1, i32 0 @@ -49,7 +49,7 @@ define i32 @select_1_or_0(i1 %cond) { define i32 @select_1_or_0_zeroext(i1 zeroext %cond) { ; ALL-LABEL: select_1_or_0_zeroext: -; ALL: # BB#0: +; ALL: # %bb.0: ; ALL-NEXT: blr %sel = select i1 %cond, i32 1, i32 0 ret i32 %sel @@ -57,7 +57,7 @@ define i32 @select_1_or_0_zeroext(i1 zeroext %cond) { define i32 @select_1_or_0_signext(i1 signext %cond) { ; ALL-LABEL: select_1_or_0_signext: -; ALL: # BB#0: +; ALL: # %bb.0: ; ALL-NEXT: clrldi 3, 3, 63 ; ALL-NEXT: blr %sel = select i1 %cond, i32 1, i32 0 @@ -68,7 +68,7 @@ define i32 @select_1_or_0_signext(i1 signext %cond) { define i32 @select_0_or_neg1(i1 %cond) { ; ISEL-LABEL: select_0_or_neg1: -; ISEL: # BB#0: +; ISEL: # %bb.0: ; ISEL-NEXT: li 4, 0 ; ISEL-NEXT: andi. 3, 3, 1 ; ISEL-NEXT: oris 3, 4, 65535 @@ -77,7 +77,7 @@ define i32 @select_0_or_neg1(i1 %cond) { ; ISEL-NEXT: blr ; ; NO_ISEL-LABEL: select_0_or_neg1: -; NO_ISEL: # BB#0: +; NO_ISEL: # %bb.0: ; NO_ISEL-NEXT: li 4, 0 ; NO_ISEL-NEXT: andi. 3, 3, 1 ; NO_ISEL-NEXT: oris 3, 4, 65535 @@ -93,7 +93,7 @@ define i32 @select_0_or_neg1(i1 %cond) { define i32 @select_0_or_neg1_zeroext(i1 zeroext %cond) { ; ISEL-LABEL: select_0_or_neg1_zeroext: -; ISEL: # BB#0: +; ISEL: # %bb.0: ; ISEL-NEXT: li 4, 0 ; ISEL-NEXT: andi. 3, 3, 1 ; ISEL-NEXT: oris 3, 4, 65535 @@ -102,7 +102,7 @@ define i32 @select_0_or_neg1_zeroext(i1 zeroext %cond) { ; ISEL-NEXT: blr ; ; NO_ISEL-LABEL: select_0_or_neg1_zeroext: -; NO_ISEL: # BB#0: +; NO_ISEL: # %bb.0: ; NO_ISEL-NEXT: li 4, 0 ; NO_ISEL-NEXT: andi. 3, 3, 1 ; NO_ISEL-NEXT: oris 3, 4, 65535 @@ -118,7 +118,7 @@ define i32 @select_0_or_neg1_zeroext(i1 zeroext %cond) { define i32 @select_0_or_neg1_signext(i1 signext %cond) { ; ISEL-LABEL: select_0_or_neg1_signext: -; ISEL: # BB#0: +; ISEL: # %bb.0: ; ISEL-NEXT: li 4, 0 ; ISEL-NEXT: andi. 3, 3, 1 ; ISEL-NEXT: oris 3, 4, 65535 @@ -127,7 +127,7 @@ define i32 @select_0_or_neg1_signext(i1 signext %cond) { ; ISEL-NEXT: blr ; ; NO_ISEL-LABEL: select_0_or_neg1_signext: -; NO_ISEL: # BB#0: +; NO_ISEL: # %bb.0: ; NO_ISEL-NEXT: li 4, 0 ; NO_ISEL-NEXT: andi. 3, 3, 1 ; NO_ISEL-NEXT: oris 3, 4, 65535 @@ -145,7 +145,7 @@ define i32 @select_0_or_neg1_signext(i1 signext %cond) { define i32 @select_neg1_or_0(i1 %cond) { ; ISEL-LABEL: select_neg1_or_0: -; ISEL: # BB#0: +; ISEL: # %bb.0: ; ISEL-NEXT: li 4, 0 ; ISEL-NEXT: andi. 3, 3, 1 ; ISEL-NEXT: oris 3, 4, 65535 @@ -154,13 +154,13 @@ define i32 @select_neg1_or_0(i1 %cond) { ; ISEL-NEXT: blr ; ; NO_ISEL-LABEL: select_neg1_or_0: -; NO_ISEL: # BB#0: +; NO_ISEL: # %bb.0: ; NO_ISEL-NEXT: li 4, 0 ; NO_ISEL-NEXT: andi. 3, 3, 1 ; NO_ISEL-NEXT: oris 3, 4, 65535 ; NO_ISEL-NEXT: ori 3, 3, 65535 ; NO_ISEL-NEXT: bclr 12, 1, 0 -; NO_ISEL-NEXT: # BB#1: +; NO_ISEL-NEXT: # %bb.1: ; NO_ISEL-NEXT: ori 3, 4, 0 ; NO_ISEL-NEXT: blr %sel = select i1 %cond, i32 -1, i32 0 @@ -169,7 +169,7 @@ define i32 @select_neg1_or_0(i1 %cond) { define i32 @select_neg1_or_0_zeroext(i1 zeroext %cond) { ; ISEL-LABEL: select_neg1_or_0_zeroext: -; ISEL: # BB#0: +; ISEL: # %bb.0: ; ISEL-NEXT: li 4, 0 ; ISEL-NEXT: andi. 3, 3, 1 ; ISEL-NEXT: oris 3, 4, 65535 @@ -178,13 +178,13 @@ define i32 @select_neg1_or_0_zeroext(i1 zeroext %cond) { ; ISEL-NEXT: blr ; ; NO_ISEL-LABEL: select_neg1_or_0_zeroext: -; NO_ISEL: # BB#0: +; NO_ISEL: # %bb.0: ; NO_ISEL-NEXT: li 4, 0 ; NO_ISEL-NEXT: andi. 3, 3, 1 ; NO_ISEL-NEXT: oris 3, 4, 65535 ; NO_ISEL-NEXT: ori 3, 3, 65535 ; NO_ISEL-NEXT: bclr 12, 1, 0 -; NO_ISEL-NEXT: # BB#1: +; NO_ISEL-NEXT: # %bb.1: ; NO_ISEL-NEXT: ori 3, 4, 0 ; NO_ISEL-NEXT: blr %sel = select i1 %cond, i32 -1, i32 0 @@ -193,7 +193,7 @@ define i32 @select_neg1_or_0_zeroext(i1 zeroext %cond) { define i32 @select_neg1_or_0_signext(i1 signext %cond) { ; ISEL-LABEL: select_neg1_or_0_signext: -; ISEL: # BB#0: +; ISEL: # %bb.0: ; ISEL-NEXT: li 4, 0 ; ISEL-NEXT: andi. 3, 3, 1 ; ISEL-NEXT: oris 3, 4, 65535 @@ -202,13 +202,13 @@ define i32 @select_neg1_or_0_signext(i1 signext %cond) { ; ISEL-NEXT: blr ; ; NO_ISEL-LABEL: select_neg1_or_0_signext: -; NO_ISEL: # BB#0: +; NO_ISEL: # %bb.0: ; NO_ISEL-NEXT: li 4, 0 ; NO_ISEL-NEXT: andi. 3, 3, 1 ; NO_ISEL-NEXT: oris 3, 4, 65535 ; NO_ISEL-NEXT: ori 3, 3, 65535 ; NO_ISEL-NEXT: bclr 12, 1, 0 -; NO_ISEL-NEXT: # BB#1: +; NO_ISEL-NEXT: # %bb.1: ; NO_ISEL-NEXT: ori 3, 4, 0 ; NO_ISEL-NEXT: blr %sel = select i1 %cond, i32 -1, i32 0 @@ -219,7 +219,7 @@ define i32 @select_neg1_or_0_signext(i1 signext %cond) { define i32 @select_Cplus1_C(i1 %cond) { ; ALL-LABEL: select_Cplus1_C: -; ALL: # BB#0: +; ALL: # %bb.0: ; ALL-NEXT: clrldi 3, 3, 63 ; ALL-NEXT: addi 3, 3, 41 ; ALL-NEXT: blr @@ -229,7 +229,7 @@ define i32 @select_Cplus1_C(i1 %cond) { define i32 @select_Cplus1_C_zeroext(i1 zeroext %cond) { ; ALL-LABEL: select_Cplus1_C_zeroext: -; ALL: # BB#0: +; ALL: # %bb.0: ; ALL-NEXT: addi 3, 3, 41 ; ALL-NEXT: blr %sel = select i1 %cond, i32 42, i32 41 @@ -238,7 +238,7 @@ define i32 @select_Cplus1_C_zeroext(i1 zeroext %cond) { define i32 @select_Cplus1_C_signext(i1 signext %cond) { ; ALL-LABEL: select_Cplus1_C_signext: -; ALL: # BB#0: +; ALL: # %bb.0: ; ALL-NEXT: subfic 3, 3, 41 ; ALL-NEXT: blr %sel = select i1 %cond, i32 42, i32 41 @@ -249,7 +249,7 @@ define i32 @select_Cplus1_C_signext(i1 signext %cond) { define i32 @select_C_Cplus1(i1 %cond) { ; ALL-LABEL: select_C_Cplus1: -; ALL: # BB#0: +; ALL: # %bb.0: ; ALL-NEXT: clrldi 3, 3, 63 ; ALL-NEXT: subfic 3, 3, 42 ; ALL-NEXT: blr @@ -259,7 +259,7 @@ define i32 @select_C_Cplus1(i1 %cond) { define i32 @select_C_Cplus1_zeroext(i1 zeroext %cond) { ; ALL-LABEL: select_C_Cplus1_zeroext: -; ALL: # BB#0: +; ALL: # %bb.0: ; ALL-NEXT: subfic 3, 3, 42 ; ALL-NEXT: blr %sel = select i1 %cond, i32 41, i32 42 @@ -268,7 +268,7 @@ define i32 @select_C_Cplus1_zeroext(i1 zeroext %cond) { define i32 @select_C_Cplus1_signext(i1 signext %cond) { ; ALL-LABEL: select_C_Cplus1_signext: -; ALL: # BB#0: +; ALL: # %bb.0: ; ALL-NEXT: addi 3, 3, 42 ; ALL-NEXT: blr %sel = select i1 %cond, i32 41, i32 42 @@ -280,7 +280,7 @@ define i32 @select_C_Cplus1_signext(i1 signext %cond) { define i32 @select_C1_C2(i1 %cond) { ; ISEL-LABEL: select_C1_C2: -; ISEL: # BB#0: +; ISEL: # %bb.0: ; ISEL-NEXT: andi. 3, 3, 1 ; ISEL-NEXT: li 4, 421 ; ISEL-NEXT: li 3, 42 @@ -288,7 +288,7 @@ define i32 @select_C1_C2(i1 %cond) { ; ISEL-NEXT: blr ; ; NO_ISEL-LABEL: select_C1_C2: -; NO_ISEL: # BB#0: +; NO_ISEL: # %bb.0: ; NO_ISEL-NEXT: andi. 3, 3, 1 ; NO_ISEL-NEXT: li 4, 421 ; NO_ISEL-NEXT: li 3, 42 @@ -303,7 +303,7 @@ define i32 @select_C1_C2(i1 %cond) { define i32 @select_C1_C2_zeroext(i1 zeroext %cond) { ; ISEL-LABEL: select_C1_C2_zeroext: -; ISEL: # BB#0: +; ISEL: # %bb.0: ; ISEL-NEXT: andi. 3, 3, 1 ; ISEL-NEXT: li 4, 421 ; ISEL-NEXT: li 3, 42 @@ -311,7 +311,7 @@ define i32 @select_C1_C2_zeroext(i1 zeroext %cond) { ; ISEL-NEXT: blr ; ; NO_ISEL-LABEL: select_C1_C2_zeroext: -; NO_ISEL: # BB#0: +; NO_ISEL: # %bb.0: ; NO_ISEL-NEXT: andi. 3, 3, 1 ; NO_ISEL-NEXT: li 4, 421 ; NO_ISEL-NEXT: li 3, 42 @@ -326,7 +326,7 @@ define i32 @select_C1_C2_zeroext(i1 zeroext %cond) { define i32 @select_C1_C2_signext(i1 signext %cond) { ; ISEL-LABEL: select_C1_C2_signext: -; ISEL: # BB#0: +; ISEL: # %bb.0: ; ISEL-NEXT: andi. 3, 3, 1 ; ISEL-NEXT: li 4, 421 ; ISEL-NEXT: li 3, 42 @@ -334,7 +334,7 @@ define i32 @select_C1_C2_signext(i1 signext %cond) { ; ISEL-NEXT: blr ; ; NO_ISEL-LABEL: select_C1_C2_signext: -; NO_ISEL: # BB#0: +; NO_ISEL: # %bb.0: ; NO_ISEL-NEXT: andi. 3, 3, 1 ; NO_ISEL-NEXT: li 4, 421 ; NO_ISEL-NEXT: li 3, 42 @@ -351,7 +351,7 @@ define i32 @select_C1_C2_signext(i1 signext %cond) { define i8 @sel_constants_add_constant(i1 %cond) { ; ISEL-LABEL: sel_constants_add_constant: -; ISEL: # BB#0: +; ISEL: # %bb.0: ; ISEL-NEXT: andi. 3, 3, 1 ; ISEL-NEXT: li 4, 1 ; ISEL-NEXT: li 3, 28 @@ -359,7 +359,7 @@ define i8 @sel_constants_add_constant(i1 %cond) { ; ISEL-NEXT: blr ; ; NO_ISEL-LABEL: sel_constants_add_constant: -; NO_ISEL: # BB#0: +; NO_ISEL: # %bb.0: ; NO_ISEL-NEXT: andi. 3, 3, 1 ; NO_ISEL-NEXT: li 4, 1 ; NO_ISEL-NEXT: li 3, 28 @@ -375,7 +375,7 @@ define i8 @sel_constants_add_constant(i1 %cond) { define i8 @sel_constants_sub_constant(i1 %cond) { ; ISEL-LABEL: sel_constants_sub_constant: -; ISEL: # BB#0: +; ISEL: # %bb.0: ; ISEL-NEXT: li 4, 0 ; ISEL-NEXT: andi. 3, 3, 1 ; ISEL-NEXT: oris 3, 4, 65535 @@ -385,14 +385,14 @@ define i8 @sel_constants_sub_constant(i1 %cond) { ; ISEL-NEXT: blr ; ; NO_ISEL-LABEL: sel_constants_sub_constant: -; NO_ISEL: # BB#0: +; NO_ISEL: # %bb.0: ; NO_ISEL-NEXT: li 4, 0 ; NO_ISEL-NEXT: andi. 3, 3, 1 ; NO_ISEL-NEXT: oris 3, 4, 65535 ; NO_ISEL-NEXT: li 4, 18 ; NO_ISEL-NEXT: ori 3, 3, 65527 ; NO_ISEL-NEXT: bclr 12, 1, 0 -; NO_ISEL-NEXT: # BB#1: +; NO_ISEL-NEXT: # %bb.1: ; NO_ISEL-NEXT: ori 3, 4, 0 ; NO_ISEL-NEXT: blr %sel = select i1 %cond, i8 -4, i8 23 @@ -402,7 +402,7 @@ define i8 @sel_constants_sub_constant(i1 %cond) { define i8 @sel_constants_mul_constant(i1 %cond) { ; ISEL-LABEL: sel_constants_mul_constant: -; ISEL: # BB#0: +; ISEL: # %bb.0: ; ISEL-NEXT: lis 4, 16383 ; ISEL-NEXT: andi. 3, 3, 1 ; ISEL-NEXT: ori 3, 4, 65531 @@ -412,14 +412,14 @@ define i8 @sel_constants_mul_constant(i1 %cond) { ; ISEL-NEXT: blr ; ; NO_ISEL-LABEL: sel_constants_mul_constant: -; NO_ISEL: # BB#0: +; NO_ISEL: # %bb.0: ; NO_ISEL-NEXT: lis 4, 16383 ; NO_ISEL-NEXT: andi. 3, 3, 1 ; NO_ISEL-NEXT: ori 3, 4, 65531 ; NO_ISEL-NEXT: li 4, 115 ; NO_ISEL-NEXT: sldi 3, 3, 2 ; NO_ISEL-NEXT: bclr 12, 1, 0 -; NO_ISEL-NEXT: # BB#1: +; NO_ISEL-NEXT: # %bb.1: ; NO_ISEL-NEXT: ori 3, 4, 0 ; NO_ISEL-NEXT: blr %sel = select i1 %cond, i8 -4, i8 23 @@ -429,14 +429,14 @@ define i8 @sel_constants_mul_constant(i1 %cond) { define i8 @sel_constants_sdiv_constant(i1 %cond) { ; ISEL-LABEL: sel_constants_sdiv_constant: -; ISEL: # BB#0: +; ISEL: # %bb.0: ; ISEL-NEXT: andi. 3, 3, 1 ; ISEL-NEXT: li 3, 4 ; ISEL-NEXT: isel 3, 0, 3, 1 ; ISEL-NEXT: blr ; ; NO_ISEL-LABEL: sel_constants_sdiv_constant: -; NO_ISEL: # BB#0: +; NO_ISEL: # %bb.0: ; NO_ISEL-NEXT: andi. 3, 3, 1 ; NO_ISEL-NEXT: li 3, 4 ; NO_ISEL-NEXT: bc 12, 1, .LBB24_1 @@ -451,7 +451,7 @@ define i8 @sel_constants_sdiv_constant(i1 %cond) { define i8 @sel_constants_udiv_constant(i1 %cond) { ; ISEL-LABEL: sel_constants_udiv_constant: -; ISEL: # BB#0: +; ISEL: # %bb.0: ; ISEL-NEXT: andi. 3, 3, 1 ; ISEL-NEXT: li 4, 50 ; ISEL-NEXT: li 3, 4 @@ -459,7 +459,7 @@ define i8 @sel_constants_udiv_constant(i1 %cond) { ; ISEL-NEXT: blr ; ; NO_ISEL-LABEL: sel_constants_udiv_constant: -; NO_ISEL: # BB#0: +; NO_ISEL: # %bb.0: ; NO_ISEL-NEXT: andi. 3, 3, 1 ; NO_ISEL-NEXT: li 4, 50 ; NO_ISEL-NEXT: li 3, 4 @@ -475,7 +475,7 @@ define i8 @sel_constants_udiv_constant(i1 %cond) { define i8 @sel_constants_srem_constant(i1 %cond) { ; ISEL-LABEL: sel_constants_srem_constant: -; ISEL: # BB#0: +; ISEL: # %bb.0: ; ISEL-NEXT: lis 4, 16383 ; ISEL-NEXT: andi. 3, 3, 1 ; ISEL-NEXT: ori 3, 4, 65535 @@ -485,14 +485,14 @@ define i8 @sel_constants_srem_constant(i1 %cond) { ; ISEL-NEXT: blr ; ; NO_ISEL-LABEL: sel_constants_srem_constant: -; NO_ISEL: # BB#0: +; NO_ISEL: # %bb.0: ; NO_ISEL-NEXT: lis 4, 16383 ; NO_ISEL-NEXT: andi. 3, 3, 1 ; NO_ISEL-NEXT: ori 3, 4, 65535 ; NO_ISEL-NEXT: li 4, 3 ; NO_ISEL-NEXT: sldi 3, 3, 2 ; NO_ISEL-NEXT: bclr 12, 1, 0 -; NO_ISEL-NEXT: # BB#1: +; NO_ISEL-NEXT: # %bb.1: ; NO_ISEL-NEXT: ori 3, 4, 0 ; NO_ISEL-NEXT: blr %sel = select i1 %cond, i8 -4, i8 23 @@ -502,7 +502,7 @@ define i8 @sel_constants_srem_constant(i1 %cond) { define i8 @sel_constants_urem_constant(i1 %cond) { ; ALL-LABEL: sel_constants_urem_constant: -; ALL: # BB#0: +; ALL: # %bb.0: ; ALL-NEXT: rlwinm 3, 3, 0, 31, 31 ; ALL-NEXT: subfic 3, 3, 3 ; ALL-NEXT: blr @@ -513,7 +513,7 @@ define i8 @sel_constants_urem_constant(i1 %cond) { define i8 @sel_constants_and_constant(i1 %cond) { ; ALL-LABEL: sel_constants_and_constant: -; ALL: # BB#0: +; ALL: # %bb.0: ; ALL-NEXT: rlwinm 3, 3, 0, 31, 31 ; ALL-NEXT: subfic 3, 3, 5 ; ALL-NEXT: blr @@ -524,7 +524,7 @@ define i8 @sel_constants_and_constant(i1 %cond) { define i8 @sel_constants_or_constant(i1 %cond) { ; ISEL-LABEL: sel_constants_or_constant: -; ISEL: # BB#0: +; ISEL: # %bb.0: ; ISEL-NEXT: li 4, 0 ; ISEL-NEXT: andi. 3, 3, 1 ; ISEL-NEXT: oris 3, 4, 65535 @@ -534,14 +534,14 @@ define i8 @sel_constants_or_constant(i1 %cond) { ; ISEL-NEXT: blr ; ; NO_ISEL-LABEL: sel_constants_or_constant: -; NO_ISEL: # BB#0: +; NO_ISEL: # %bb.0: ; NO_ISEL-NEXT: li 4, 0 ; NO_ISEL-NEXT: andi. 3, 3, 1 ; NO_ISEL-NEXT: oris 3, 4, 65535 ; NO_ISEL-NEXT: li 4, 23 ; NO_ISEL-NEXT: ori 3, 3, 65533 ; NO_ISEL-NEXT: bclr 12, 1, 0 -; NO_ISEL-NEXT: # BB#1: +; NO_ISEL-NEXT: # %bb.1: ; NO_ISEL-NEXT: ori 3, 4, 0 ; NO_ISEL-NEXT: blr %sel = select i1 %cond, i8 -4, i8 23 @@ -551,7 +551,7 @@ define i8 @sel_constants_or_constant(i1 %cond) { define i8 @sel_constants_xor_constant(i1 %cond) { ; ISEL-LABEL: sel_constants_xor_constant: -; ISEL: # BB#0: +; ISEL: # %bb.0: ; ISEL-NEXT: li 4, 0 ; ISEL-NEXT: andi. 3, 3, 1 ; ISEL-NEXT: oris 3, 4, 65535 @@ -561,14 +561,14 @@ define i8 @sel_constants_xor_constant(i1 %cond) { ; ISEL-NEXT: blr ; ; NO_ISEL-LABEL: sel_constants_xor_constant: -; NO_ISEL: # BB#0: +; NO_ISEL: # %bb.0: ; NO_ISEL-NEXT: li 4, 0 ; NO_ISEL-NEXT: andi. 3, 3, 1 ; NO_ISEL-NEXT: oris 3, 4, 65535 ; NO_ISEL-NEXT: li 4, 18 ; NO_ISEL-NEXT: ori 3, 3, 65529 ; NO_ISEL-NEXT: bclr 12, 1, 0 -; NO_ISEL-NEXT: # BB#1: +; NO_ISEL-NEXT: # %bb.1: ; NO_ISEL-NEXT: ori 3, 4, 0 ; NO_ISEL-NEXT: blr %sel = select i1 %cond, i8 -4, i8 23 @@ -578,7 +578,7 @@ define i8 @sel_constants_xor_constant(i1 %cond) { define i8 @sel_constants_shl_constant(i1 %cond) { ; ISEL-LABEL: sel_constants_shl_constant: -; ISEL: # BB#0: +; ISEL: # %bb.0: ; ISEL-NEXT: lis 5, 511 ; ISEL-NEXT: lis 4, 2047 ; ISEL-NEXT: andi. 3, 3, 1 @@ -590,7 +590,7 @@ define i8 @sel_constants_shl_constant(i1 %cond) { ; ISEL-NEXT: blr ; ; NO_ISEL-LABEL: sel_constants_shl_constant: -; NO_ISEL: # BB#0: +; NO_ISEL: # %bb.0: ; NO_ISEL-NEXT: lis 5, 511 ; NO_ISEL-NEXT: lis 4, 2047 ; NO_ISEL-NEXT: andi. 3, 3, 1 @@ -610,7 +610,7 @@ define i8 @sel_constants_shl_constant(i1 %cond) { define i8 @sel_constants_lshr_constant(i1 %cond) { ; ISEL-LABEL: sel_constants_lshr_constant: -; ISEL: # BB#0: +; ISEL: # %bb.0: ; ISEL-NEXT: andi. 3, 3, 1 ; ISEL-NEXT: li 4, 7 ; ISEL-NEXT: li 3, 0 @@ -618,7 +618,7 @@ define i8 @sel_constants_lshr_constant(i1 %cond) { ; ISEL-NEXT: blr ; ; NO_ISEL-LABEL: sel_constants_lshr_constant: -; NO_ISEL: # BB#0: +; NO_ISEL: # %bb.0: ; NO_ISEL-NEXT: andi. 3, 3, 1 ; NO_ISEL-NEXT: li 4, 7 ; NO_ISEL-NEXT: li 3, 0 @@ -634,7 +634,7 @@ define i8 @sel_constants_lshr_constant(i1 %cond) { define i8 @sel_constants_ashr_constant(i1 %cond) { ; ALL-LABEL: sel_constants_ashr_constant: -; ALL: # BB#0: +; ALL: # %bb.0: ; ALL-NEXT: clrldi 3, 3, 63 ; ALL-NEXT: neg 3, 3 ; ALL-NEXT: blr @@ -645,7 +645,7 @@ define i8 @sel_constants_ashr_constant(i1 %cond) { define double @sel_constants_fadd_constant(i1 %cond) { ; ISEL-LABEL: sel_constants_fadd_constant: -; ISEL: # BB#0: +; ISEL: # %bb.0: ; ISEL-NEXT: andi. 3, 3, 1 ; ISEL-NEXT: addis 4, 2, .LCPI34_0@toc@ha ; ISEL-NEXT: addis 3, 2, .LCPI34_1@toc@ha @@ -656,14 +656,14 @@ define double @sel_constants_fadd_constant(i1 %cond) { ; ISEL-NEXT: blr ; ; NO_ISEL-LABEL: sel_constants_fadd_constant: -; NO_ISEL: # BB#0: +; NO_ISEL: # %bb.0: ; NO_ISEL-NEXT: andi. 3, 3, 1 ; NO_ISEL-NEXT: addis 4, 2, .LCPI34_0@toc@ha ; NO_ISEL-NEXT: addis 3, 2, .LCPI34_1@toc@ha ; NO_ISEL-NEXT: addi 4, 4, .LCPI34_0@toc@l ; NO_ISEL-NEXT: addi 3, 3, .LCPI34_1@toc@l ; NO_ISEL-NEXT: bc 12, 1, .LBB34_2 -; NO_ISEL-NEXT: # BB#1: +; NO_ISEL-NEXT: # %bb.1: ; NO_ISEL-NEXT: ori 3, 4, 0 ; NO_ISEL-NEXT: b .LBB34_2 ; NO_ISEL-NEXT: .LBB34_2: @@ -676,7 +676,7 @@ define double @sel_constants_fadd_constant(i1 %cond) { define double @sel_constants_fsub_constant(i1 %cond) { ; ISEL-LABEL: sel_constants_fsub_constant: -; ISEL: # BB#0: +; ISEL: # %bb.0: ; ISEL-NEXT: andi. 3, 3, 1 ; ISEL-NEXT: addis 4, 2, .LCPI35_0@toc@ha ; ISEL-NEXT: addis 3, 2, .LCPI35_1@toc@ha @@ -687,14 +687,14 @@ define double @sel_constants_fsub_constant(i1 %cond) { ; ISEL-NEXT: blr ; ; NO_ISEL-LABEL: sel_constants_fsub_constant: -; NO_ISEL: # BB#0: +; NO_ISEL: # %bb.0: ; NO_ISEL-NEXT: andi. 3, 3, 1 ; NO_ISEL-NEXT: addis 4, 2, .LCPI35_0@toc@ha ; NO_ISEL-NEXT: addis 3, 2, .LCPI35_1@toc@ha ; NO_ISEL-NEXT: addi 4, 4, .LCPI35_0@toc@l ; NO_ISEL-NEXT: addi 3, 3, .LCPI35_1@toc@l ; NO_ISEL-NEXT: bc 12, 1, .LBB35_2 -; NO_ISEL-NEXT: # BB#1: +; NO_ISEL-NEXT: # %bb.1: ; NO_ISEL-NEXT: ori 3, 4, 0 ; NO_ISEL-NEXT: b .LBB35_2 ; NO_ISEL-NEXT: .LBB35_2: @@ -707,7 +707,7 @@ define double @sel_constants_fsub_constant(i1 %cond) { define double @sel_constants_fmul_constant(i1 %cond) { ; ISEL-LABEL: sel_constants_fmul_constant: -; ISEL: # BB#0: +; ISEL: # %bb.0: ; ISEL-NEXT: andi. 3, 3, 1 ; ISEL-NEXT: addis 4, 2, .LCPI36_0@toc@ha ; ISEL-NEXT: addis 3, 2, .LCPI36_1@toc@ha @@ -718,14 +718,14 @@ define double @sel_constants_fmul_constant(i1 %cond) { ; ISEL-NEXT: blr ; ; NO_ISEL-LABEL: sel_constants_fmul_constant: -; NO_ISEL: # BB#0: +; NO_ISEL: # %bb.0: ; NO_ISEL-NEXT: andi. 3, 3, 1 ; NO_ISEL-NEXT: addis 4, 2, .LCPI36_0@toc@ha ; NO_ISEL-NEXT: addis 3, 2, .LCPI36_1@toc@ha ; NO_ISEL-NEXT: addi 4, 4, .LCPI36_0@toc@l ; NO_ISEL-NEXT: addi 3, 3, .LCPI36_1@toc@l ; NO_ISEL-NEXT: bc 12, 1, .LBB36_2 -; NO_ISEL-NEXT: # BB#1: +; NO_ISEL-NEXT: # %bb.1: ; NO_ISEL-NEXT: ori 3, 4, 0 ; NO_ISEL-NEXT: b .LBB36_2 ; NO_ISEL-NEXT: .LBB36_2: @@ -738,7 +738,7 @@ define double @sel_constants_fmul_constant(i1 %cond) { define double @sel_constants_fdiv_constant(i1 %cond) { ; ISEL-LABEL: sel_constants_fdiv_constant: -; ISEL: # BB#0: +; ISEL: # %bb.0: ; ISEL-NEXT: andi. 3, 3, 1 ; ISEL-NEXT: addis 4, 2, .LCPI37_0@toc@ha ; ISEL-NEXT: addis 3, 2, .LCPI37_1@toc@ha @@ -749,14 +749,14 @@ define double @sel_constants_fdiv_constant(i1 %cond) { ; ISEL-NEXT: blr ; ; NO_ISEL-LABEL: sel_constants_fdiv_constant: -; NO_ISEL: # BB#0: +; NO_ISEL: # %bb.0: ; NO_ISEL-NEXT: andi. 3, 3, 1 ; NO_ISEL-NEXT: addis 4, 2, .LCPI37_0@toc@ha ; NO_ISEL-NEXT: addis 3, 2, .LCPI37_1@toc@ha ; NO_ISEL-NEXT: addi 4, 4, .LCPI37_0@toc@l ; NO_ISEL-NEXT: addi 3, 3, .LCPI37_1@toc@l ; NO_ISEL-NEXT: bc 12, 1, .LBB37_2 -; NO_ISEL-NEXT: # BB#1: +; NO_ISEL-NEXT: # %bb.1: ; NO_ISEL-NEXT: ori 3, 4, 0 ; NO_ISEL-NEXT: b .LBB37_2 ; NO_ISEL-NEXT: .LBB37_2: @@ -769,10 +769,10 @@ define double @sel_constants_fdiv_constant(i1 %cond) { define double @sel_constants_frem_constant(i1 %cond) { ; ALL-LABEL: sel_constants_frem_constant: -; ALL: # BB#0: +; ALL: # %bb.0: ; ALL-NEXT: andi. 3, 3, 1 ; ALL-NEXT: bc 12, 1, .LBB38_2 -; ALL-NEXT: # BB#1: +; ALL-NEXT: # %bb.1: ; ALL-NEXT: addis 3, 2, .LCPI38_0@toc@ha ; ALL-NEXT: addi 3, 3, .LCPI38_0@toc@l ; ALL-NEXT: lxsdx 1, 0, 3 diff --git a/test/CodeGen/PowerPC/setcc-logic.ll b/test/CodeGen/PowerPC/setcc-logic.ll index be5171d3b7e7d..b17869f312c9b 100644 --- a/test/CodeGen/PowerPC/setcc-logic.ll +++ b/test/CodeGen/PowerPC/setcc-logic.ll @@ -1,10 +1,9 @@ -; XFAIL: * ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown | FileCheck %s +; RUN: llc < %s -ppc-gpr-icmps=all -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown | FileCheck %s define zeroext i1 @all_bits_clear(i32 %P, i32 %Q) { ; CHECK-LABEL: all_bits_clear: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: or 3, 3, 4 ; CHECK-NEXT: cntlzw 3, 3 ; CHECK-NEXT: srwi 3, 3, 5 @@ -17,7 +16,7 @@ define zeroext i1 @all_bits_clear(i32 %P, i32 %Q) { define zeroext i1 @all_sign_bits_clear(i32 %P, i32 %Q) { ; CHECK-LABEL: all_sign_bits_clear: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: or 3, 3, 4 ; CHECK-NEXT: nor 3, 3, 3 ; CHECK-NEXT: srwi 3, 3, 31 @@ -30,7 +29,7 @@ define zeroext i1 @all_sign_bits_clear(i32 %P, i32 %Q) { define zeroext i1 @all_bits_set(i32 %P, i32 %Q) { ; CHECK-LABEL: all_bits_set: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: li 5, -1 ; CHECK-NEXT: and 3, 3, 4 ; CHECK-NEXT: xor 3, 3, 5 @@ -45,7 +44,7 @@ define zeroext i1 @all_bits_set(i32 %P, i32 %Q) { define zeroext i1 @all_sign_bits_set(i32 %P, i32 %Q) { ; CHECK-LABEL: all_sign_bits_set: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: and 3, 3, 4 ; CHECK-NEXT: srwi 3, 3, 31 ; CHECK-NEXT: blr @@ -57,7 +56,7 @@ define zeroext i1 @all_sign_bits_set(i32 %P, i32 %Q) { define zeroext i1 @any_bits_set(i32 %P, i32 %Q) { ; CHECK-LABEL: any_bits_set: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: or 3, 3, 4 ; CHECK-NEXT: cntlzw 3, 3 ; CHECK-NEXT: srwi 3, 3, 5 @@ -71,7 +70,7 @@ define zeroext i1 @any_bits_set(i32 %P, i32 %Q) { define zeroext i1 @any_sign_bits_set(i32 %P, i32 %Q) { ; CHECK-LABEL: any_sign_bits_set: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: or 3, 3, 4 ; CHECK-NEXT: srwi 3, 3, 31 ; CHECK-NEXT: blr @@ -83,7 +82,7 @@ define zeroext i1 @any_sign_bits_set(i32 %P, i32 %Q) { define zeroext i1 @any_bits_clear(i32 %P, i32 %Q) { ; CHECK-LABEL: any_bits_clear: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: li 5, -1 ; CHECK-NEXT: and 3, 3, 4 ; CHECK-NEXT: xor 3, 3, 5 @@ -99,7 +98,7 @@ define zeroext i1 @any_bits_clear(i32 %P, i32 %Q) { define zeroext i1 @any_sign_bits_clear(i32 %P, i32 %Q) { ; CHECK-LABEL: any_sign_bits_clear: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: and 3, 3, 4 ; CHECK-NEXT: nor 3, 3, 3 ; CHECK-NEXT: srwi 3, 3, 31 @@ -113,10 +112,10 @@ define zeroext i1 @any_sign_bits_clear(i32 %P, i32 %Q) { ; PR3351 - (P == 0) & (Q == 0) -> (P|Q) == 0 define i32 @all_bits_clear_branch(i32* %P, i32* %Q) { ; CHECK-LABEL: all_bits_clear_branch: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: or. 3, 3, 4 ; CHECK-NEXT: bne 0, .LBB8_2 -; CHECK-NEXT: # BB#1: # %bb1 +; CHECK-NEXT: # %bb.1: # %bb1 ; CHECK-NEXT: li 3, 4 ; CHECK-NEXT: blr ; CHECK-NEXT: .LBB8_2: # %return @@ -137,11 +136,11 @@ return: define i32 @all_sign_bits_clear_branch(i32 %P, i32 %Q) { ; CHECK-LABEL: all_sign_bits_clear_branch: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: or 3, 3, 4 ; CHECK-NEXT: cmpwi 0, 3, 0 ; CHECK-NEXT: blt 0, .LBB9_2 -; CHECK-NEXT: # BB#1: # %bb1 +; CHECK-NEXT: # %bb.1: # %bb1 ; CHECK-NEXT: li 3, 4 ; CHECK-NEXT: blr ; CHECK-NEXT: .LBB9_2: # %return @@ -162,11 +161,11 @@ return: define i32 @all_bits_set_branch(i32 %P, i32 %Q) { ; CHECK-LABEL: all_bits_set_branch: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: and 3, 3, 4 ; CHECK-NEXT: cmpwi 0, 3, -1 ; CHECK-NEXT: bne 0, .LBB10_2 -; CHECK-NEXT: # BB#1: # %bb1 +; CHECK-NEXT: # %bb.1: # %bb1 ; CHECK-NEXT: li 3, 4 ; CHECK-NEXT: blr ; CHECK-NEXT: .LBB10_2: # %return @@ -187,11 +186,11 @@ return: define i32 @all_sign_bits_set_branch(i32 %P, i32 %Q) { ; CHECK-LABEL: all_sign_bits_set_branch: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: and 3, 3, 4 ; CHECK-NEXT: cmpwi 0, 3, -1 ; CHECK-NEXT: bgt 0, .LBB11_2 -; CHECK-NEXT: # BB#1: # %bb1 +; CHECK-NEXT: # %bb.1: # %bb1 ; CHECK-NEXT: li 3, 4 ; CHECK-NEXT: blr ; CHECK-NEXT: .LBB11_2: # %return @@ -213,10 +212,10 @@ return: ; PR3351 - (P != 0) | (Q != 0) -> (P|Q) != 0 define i32 @any_bits_set_branch(i32* %P, i32* %Q) { ; CHECK-LABEL: any_bits_set_branch: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: or. 3, 3, 4 ; CHECK-NEXT: beq 0, .LBB12_2 -; CHECK-NEXT: # BB#1: # %bb1 +; CHECK-NEXT: # %bb.1: # %bb1 ; CHECK-NEXT: li 3, 4 ; CHECK-NEXT: blr ; CHECK-NEXT: .LBB12_2: # %return @@ -237,11 +236,11 @@ return: define i32 @any_sign_bits_set_branch(i32 %P, i32 %Q) { ; CHECK-LABEL: any_sign_bits_set_branch: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: or 3, 3, 4 ; CHECK-NEXT: cmpwi 0, 3, -1 ; CHECK-NEXT: bgt 0, .LBB13_2 -; CHECK-NEXT: # BB#1: # %bb1 +; CHECK-NEXT: # %bb.1: # %bb1 ; CHECK-NEXT: li 3, 4 ; CHECK-NEXT: blr ; CHECK-NEXT: .LBB13_2: # %return @@ -262,11 +261,11 @@ return: define i32 @any_bits_clear_branch(i32 %P, i32 %Q) { ; CHECK-LABEL: any_bits_clear_branch: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: and 3, 3, 4 ; CHECK-NEXT: cmpwi 0, 3, -1 ; CHECK-NEXT: beq 0, .LBB14_2 -; CHECK-NEXT: # BB#1: # %bb1 +; CHECK-NEXT: # %bb.1: # %bb1 ; CHECK-NEXT: li 3, 4 ; CHECK-NEXT: blr ; CHECK-NEXT: .LBB14_2: # %return @@ -287,11 +286,11 @@ return: define i32 @any_sign_bits_clear_branch(i32 %P, i32 %Q) { ; CHECK-LABEL: any_sign_bits_clear_branch: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: and 3, 3, 4 ; CHECK-NEXT: cmpwi 0, 3, 0 ; CHECK-NEXT: blt 0, .LBB15_2 -; CHECK-NEXT: # BB#1: # %bb1 +; CHECK-NEXT: # %bb.1: # %bb1 ; CHECK-NEXT: li 3, 4 ; CHECK-NEXT: blr ; CHECK-NEXT: .LBB15_2: # %return @@ -312,7 +311,7 @@ return: define <4 x i1> @all_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) { ; CHECK-LABEL: all_bits_clear_vec: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: xxlxor 36, 36, 36 ; CHECK-NEXT: xxlor 34, 34, 35 ; CHECK-NEXT: vcmpequw 2, 2, 4 @@ -325,7 +324,7 @@ define <4 x i1> @all_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) { define <4 x i1> @all_sign_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) { ; CHECK-LABEL: all_sign_bits_clear_vec: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vspltisb 4, -1 ; CHECK-NEXT: xxlor 34, 34, 35 ; CHECK-NEXT: vcmpgtsw 2, 2, 4 @@ -338,7 +337,7 @@ define <4 x i1> @all_sign_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) { define <4 x i1> @all_bits_set_vec(<4 x i32> %P, <4 x i32> %Q) { ; CHECK-LABEL: all_bits_set_vec: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vspltisb 4, -1 ; CHECK-NEXT: xxland 34, 34, 35 ; CHECK-NEXT: vcmpequw 2, 2, 4 @@ -351,7 +350,7 @@ define <4 x i1> @all_bits_set_vec(<4 x i32> %P, <4 x i32> %Q) { define <4 x i1> @all_sign_bits_set_vec(<4 x i32> %P, <4 x i32> %Q) { ; CHECK-LABEL: all_sign_bits_set_vec: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: xxlxor 36, 36, 36 ; CHECK-NEXT: xxland 34, 34, 35 ; CHECK-NEXT: vcmpgtsw 2, 4, 2 @@ -364,7 +363,7 @@ define <4 x i1> @all_sign_bits_set_vec(<4 x i32> %P, <4 x i32> %Q) { define <4 x i1> @any_bits_set_vec(<4 x i32> %P, <4 x i32> %Q) { ; CHECK-LABEL: any_bits_set_vec: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: xxlxor 36, 36, 36 ; CHECK-NEXT: xxlor 34, 34, 35 ; CHECK-NEXT: vcmpequw 2, 2, 4 @@ -378,7 +377,7 @@ define <4 x i1> @any_bits_set_vec(<4 x i32> %P, <4 x i32> %Q) { define <4 x i1> @any_sign_bits_set_vec(<4 x i32> %P, <4 x i32> %Q) { ; CHECK-LABEL: any_sign_bits_set_vec: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: xxlxor 36, 36, 36 ; CHECK-NEXT: xxlor 34, 34, 35 ; CHECK-NEXT: vcmpgtsw 2, 4, 2 @@ -391,7 +390,7 @@ define <4 x i1> @any_sign_bits_set_vec(<4 x i32> %P, <4 x i32> %Q) { define <4 x i1> @any_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) { ; CHECK-LABEL: any_bits_clear_vec: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vspltisb 4, -1 ; CHECK-NEXT: xxland 34, 34, 35 ; CHECK-NEXT: vcmpequw 2, 2, 4 @@ -405,7 +404,7 @@ define <4 x i1> @any_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) { define <4 x i1> @any_sign_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) { ; CHECK-LABEL: any_sign_bits_clear_vec: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vspltisb 4, -1 ; CHECK-NEXT: xxland 34, 34, 35 ; CHECK-NEXT: vcmpgtsw 2, 2, 4 @@ -418,12 +417,12 @@ define <4 x i1> @any_sign_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) { define zeroext i1 @ne_neg1_and_ne_zero(i64 %x) { ; CHECK-LABEL: ne_neg1_and_ne_zero: -; CHECK: # BB#0: +; CHECK: # %bb.0: +; CHECK-NEXT: li 4, 1 ; CHECK-NEXT: addi 3, 3, 1 -; CHECK-NEXT: li 4, 0 -; CHECK-NEXT: li 12, 1 -; CHECK-NEXT: cmpldi 3, 1 -; CHECK-NEXT: isel 3, 12, 4, 1 +; CHECK-NEXT: subfc 3, 3, 4 +; CHECK-NEXT: subfe 3, 4, 4 +; CHECK-NEXT: neg 3, 3 ; CHECK-NEXT: blr %cmp1 = icmp ne i64 %x, -1 %cmp2 = icmp ne i64 %x, 0 @@ -435,7 +434,7 @@ define zeroext i1 @ne_neg1_and_ne_zero(i64 %x) { define zeroext i1 @and_eq(i16 zeroext %a, i16 zeroext %b, i16 zeroext %c, i16 zeroext %d) { ; CHECK-LABEL: and_eq: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: xor 5, 5, 6 ; CHECK-NEXT: xor 3, 3, 4 ; CHECK-NEXT: or 3, 3, 5 @@ -450,7 +449,7 @@ define zeroext i1 @and_eq(i16 zeroext %a, i16 zeroext %b, i16 zeroext %c, i16 z define zeroext i1 @or_ne(i32 %a, i32 %b, i32 %c, i32 %d) { ; CHECK-LABEL: or_ne: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: xor 5, 5, 6 ; CHECK-NEXT: xor 3, 3, 4 ; CHECK-NEXT: or 3, 3, 5 @@ -468,7 +467,7 @@ define zeroext i1 @or_ne(i32 %a, i32 %b, i32 %c, i32 %d) { define <4 x i1> @and_eq_vec(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d) { ; CHECK-LABEL: and_eq_vec: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vcmpequw 2, 2, 3 ; CHECK-NEXT: vcmpequw 19, 4, 5 ; CHECK-NEXT: xxland 34, 34, 51 diff --git a/test/CodeGen/PowerPC/setcc-to-sub.ll b/test/CodeGen/PowerPC/setcc-to-sub.ll index 752ebe0c9d8b5..a143d73c7c0ca 100644 --- a/test/CodeGen/PowerPC/setcc-to-sub.ll +++ b/test/CodeGen/PowerPC/setcc-to-sub.ll @@ -8,7 +8,7 @@ ; Function Attrs: norecurse nounwind readonly define zeroext i1 @test1(%class.PB2* %s_a, %class.PB2* %s_b) local_unnamed_addr #0 { ; CHECK-LABEL: test1: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lwz 3, 0(3) ; CHECK-NEXT: lwz 4, 0(4) ; CHECK-NEXT: rlwinm 3, 3, 0, 28, 28 @@ -30,7 +30,7 @@ entry: ; Function Attrs: norecurse nounwind readonly define zeroext i1 @test2(%class.PB2* %s_a, %class.PB2* %s_b) local_unnamed_addr #0 { ; CHECK-LABEL: test2: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lwz 3, 0(3) ; CHECK-NEXT: lwz 4, 0(4) ; CHECK-NEXT: rlwinm 3, 3, 0, 28, 28 @@ -53,7 +53,7 @@ entry: ; Function Attrs: norecurse nounwind readonly define zeroext i1 @test3(%class.PB2* %s_a, %class.PB2* %s_b) local_unnamed_addr #0 { ; CHECK-LABEL: test3: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lwz 3, 0(3) ; CHECK-NEXT: lwz 4, 0(4) ; CHECK-NEXT: rlwinm 3, 3, 0, 28, 28 @@ -75,7 +75,7 @@ entry: ; Function Attrs: norecurse nounwind readonly define zeroext i1 @test4(%class.PB2* %s_a, %class.PB2* %s_b) local_unnamed_addr #0 { ; CHECK-LABEL: test4: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lwz 3, 0(3) ; CHECK-NEXT: lwz 4, 0(4) ; CHECK-NEXT: rlwinm 3, 3, 0, 28, 28 diff --git a/test/CodeGen/PowerPC/shift_mask.ll b/test/CodeGen/PowerPC/shift_mask.ll index e9ca9b0bdf022..59382c6153119 100644 --- a/test/CodeGen/PowerPC/shift_mask.ll +++ b/test/CodeGen/PowerPC/shift_mask.ll @@ -4,7 +4,7 @@ target triple = "powerpc64le-linux-gnu" define i8 @test000(i8 %a, i8 %b) { ; CHECK-LABEL: test000: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: rlwinm 4, 4, 0, 29, 31 ; CHECK-NEXT: slw 3, 3, 4 ; CHECK-NEXT: blr @@ -15,7 +15,7 @@ define i8 @test000(i8 %a, i8 %b) { define i16 @test001(i16 %a, i16 %b) { ; CHECK-LABEL: test001: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: rlwinm 4, 4, 0, 28, 31 ; CHECK-NEXT: slw 3, 3, 4 ; CHECK-NEXT: blr @@ -26,7 +26,7 @@ define i16 @test001(i16 %a, i16 %b) { define i32 @test002(i32 %a, i32 %b) { ; CHECK-LABEL: test002: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: rlwinm 4, 4, 0, 27, 31 ; CHECK-NEXT: slw 3, 3, 4 ; CHECK-NEXT: blr @@ -37,7 +37,7 @@ define i32 @test002(i32 %a, i32 %b) { define i64 @test003(i64 %a, i64 %b) { ; CHECK-LABEL: test003: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: rlwinm 4, 4, 0, 26, 31 ; CHECK-NEXT: sld 3, 3, 4 ; CHECK-NEXT: blr @@ -48,7 +48,7 @@ define i64 @test003(i64 %a, i64 %b) { define <16 x i8> @test010(<16 x i8> %a, <16 x i8> %b) { ; CHECK-LABEL: test010: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vslb 2, 2, 3 ; CHECK-NEXT: blr %rem = and <16 x i8> %b, @@ -58,7 +58,7 @@ define <16 x i8> @test010(<16 x i8> %a, <16 x i8> %b) { define <8 x i16> @test011(<8 x i16> %a, <8 x i16> %b) { ; CHECK-LABEL: test011: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vslh 2, 2, 3 ; CHECK-NEXT: blr %rem = and <8 x i16> %b, @@ -68,7 +68,7 @@ define <8 x i16> @test011(<8 x i16> %a, <8 x i16> %b) { define <4 x i32> @test012(<4 x i32> %a, <4 x i32> %b) { ; CHECK-LABEL: test012: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vslw 2, 2, 3 ; CHECK-NEXT: blr %rem = and <4 x i32> %b, @@ -78,7 +78,7 @@ define <4 x i32> @test012(<4 x i32> %a, <4 x i32> %b) { define <2 x i64> @test013(<2 x i64> %a, <2 x i64> %b) { ; CHECK-LABEL: test013: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vsld 2, 2, 3 ; CHECK-NEXT: blr %rem = and <2 x i64> %b, @@ -88,7 +88,7 @@ define <2 x i64> @test013(<2 x i64> %a, <2 x i64> %b) { define i8 @test100(i8 %a, i8 %b) { ; CHECK-LABEL: test100: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: rlwinm 3, 3, 0, 24, 31 ; CHECK-NEXT: rlwinm 4, 4, 0, 29, 31 ; CHECK-NEXT: srw 3, 3, 4 @@ -100,7 +100,7 @@ define i8 @test100(i8 %a, i8 %b) { define i16 @test101(i16 %a, i16 %b) { ; CHECK-LABEL: test101: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: rlwinm 3, 3, 0, 16, 31 ; CHECK-NEXT: rlwinm 4, 4, 0, 28, 31 ; CHECK-NEXT: srw 3, 3, 4 @@ -112,7 +112,7 @@ define i16 @test101(i16 %a, i16 %b) { define i32 @test102(i32 %a, i32 %b) { ; CHECK-LABEL: test102: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: rlwinm 4, 4, 0, 27, 31 ; CHECK-NEXT: srw 3, 3, 4 ; CHECK-NEXT: blr @@ -123,7 +123,7 @@ define i32 @test102(i32 %a, i32 %b) { define i64 @test103(i64 %a, i64 %b) { ; CHECK-LABEL: test103: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: rlwinm 4, 4, 0, 26, 31 ; CHECK-NEXT: srd 3, 3, 4 ; CHECK-NEXT: blr @@ -134,7 +134,7 @@ define i64 @test103(i64 %a, i64 %b) { define <16 x i8> @test110(<16 x i8> %a, <16 x i8> %b) { ; CHECK-LABEL: test110: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vsrb 2, 2, 3 ; CHECK-NEXT: blr %rem = and <16 x i8> %b, @@ -144,7 +144,7 @@ define <16 x i8> @test110(<16 x i8> %a, <16 x i8> %b) { define <8 x i16> @test111(<8 x i16> %a, <8 x i16> %b) { ; CHECK-LABEL: test111: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vsrh 2, 2, 3 ; CHECK-NEXT: blr %rem = and <8 x i16> %b, @@ -154,7 +154,7 @@ define <8 x i16> @test111(<8 x i16> %a, <8 x i16> %b) { define <4 x i32> @test112(<4 x i32> %a, <4 x i32> %b) { ; CHECK-LABEL: test112: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vsrw 2, 2, 3 ; CHECK-NEXT: blr %rem = and <4 x i32> %b, @@ -164,7 +164,7 @@ define <4 x i32> @test112(<4 x i32> %a, <4 x i32> %b) { define <2 x i64> @test113(<2 x i64> %a, <2 x i64> %b) { ; CHECK-LABEL: test113: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vsrd 2, 2, 3 ; CHECK-NEXT: blr %rem = and <2 x i64> %b, @@ -174,7 +174,7 @@ define <2 x i64> @test113(<2 x i64> %a, <2 x i64> %b) { define i8 @test200(i8 %a, i8 %b) { ; CHECK-LABEL: test200: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: extsb 3, 3 ; CHECK-NEXT: rlwinm 4, 4, 0, 29, 31 ; CHECK-NEXT: sraw 3, 3, 4 @@ -186,7 +186,7 @@ define i8 @test200(i8 %a, i8 %b) { define i16 @test201(i16 %a, i16 %b) { ; CHECK-LABEL: test201: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: extsh 3, 3 ; CHECK-NEXT: rlwinm 4, 4, 0, 28, 31 ; CHECK-NEXT: sraw 3, 3, 4 @@ -198,7 +198,7 @@ define i16 @test201(i16 %a, i16 %b) { define i32 @test202(i32 %a, i32 %b) { ; CHECK-LABEL: test202: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: rlwinm 4, 4, 0, 27, 31 ; CHECK-NEXT: sraw 3, 3, 4 ; CHECK-NEXT: blr @@ -209,7 +209,7 @@ define i32 @test202(i32 %a, i32 %b) { define i64 @test203(i64 %a, i64 %b) { ; CHECK-LABEL: test203: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: rlwinm 4, 4, 0, 26, 31 ; CHECK-NEXT: srad 3, 3, 4 ; CHECK-NEXT: blr @@ -220,7 +220,7 @@ define i64 @test203(i64 %a, i64 %b) { define <16 x i8> @test210(<16 x i8> %a, <16 x i8> %b) { ; CHECK-LABEL: test210: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vsrab 2, 2, 3 ; CHECK-NEXT: blr %rem = and <16 x i8> %b, @@ -230,7 +230,7 @@ define <16 x i8> @test210(<16 x i8> %a, <16 x i8> %b) { define <8 x i16> @test211(<8 x i16> %a, <8 x i16> %b) { ; CHECK-LABEL: test211: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vsrah 2, 2, 3 ; CHECK-NEXT: blr %rem = and <8 x i16> %b, @@ -240,7 +240,7 @@ define <8 x i16> @test211(<8 x i16> %a, <8 x i16> %b) { define <4 x i32> @test212(<4 x i32> %a, <4 x i32> %b) { ; CHECK-LABEL: test212: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vsraw 2, 2, 3 ; CHECK-NEXT: blr %rem = and <4 x i32> %b, @@ -250,7 +250,7 @@ define <4 x i32> @test212(<4 x i32> %a, <4 x i32> %b) { define <2 x i64> @test213(<2 x i64> %a, <2 x i64> %b) { ; CHECK-LABEL: test213: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vsrad 2, 2, 3 ; CHECK-NEXT: blr %rem = and <2 x i64> %b, diff --git a/test/CodeGen/PowerPC/sjlj.ll b/test/CodeGen/PowerPC/sjlj.ll index 14aec5838911f..68b53417f01ec 100644 --- a/test/CodeGen/PowerPC/sjlj.ll +++ b/test/CodeGen/PowerPC/sjlj.ll @@ -77,7 +77,7 @@ return: ; preds = %if.end, %if.then ; CHECK: bcl 20, 31, .LBB1_3 ; CHECK: li 3, 1 ; CHECK: #EH_SjLj_Setup .LBB1_3 -; CHECK: # BB#1: +; CHECK: # %bb.1: ; CHECK: .LBB1_3: ; CHECK: mflr [[REGL:[0-9]+]] diff --git a/test/CodeGen/PowerPC/tail-dup-branch-to-fallthrough.ll b/test/CodeGen/PowerPC/tail-dup-branch-to-fallthrough.ll index 0b1014571613d..3ff4753200ef6 100644 --- a/test/CodeGen/PowerPC/tail-dup-branch-to-fallthrough.ll +++ b/test/CodeGen/PowerPC/tail-dup-branch-to-fallthrough.ll @@ -12,17 +12,17 @@ declare void @f4() ; Function Attrs: nounwind ; CHECK-LABEL: tail_dup_fallthrough_with_branch -; CHECK: # %entry +; CHECK: # %bb.{{[0-9]+}}: # %entry ; CHECK-NOT: # %{{[-_a-zA-Z0-9]+}} -; CHECK: # %entry +; CHECK: # %bb.{{[0-9]+}}: # %entry ; CHECK-NOT: # %{{[-_a-zA-Z0-9]+}} -; CHECK: # %sw.0 +; CHECK: # %bb.{{[0-9]+}}: # %sw.0 ; CHECK-NOT: # %{{[-_a-zA-Z0-9]+}} ; CHECK: # %sw.1 ; CHECK-NOT: # %{{[-_a-zA-Z0-9]+}} ; CHECK: # %sw.default ; CHECK-NOT: # %{{[-_a-zA-Z0-9]+}} -; CHECK: # %if.then +; CHECK: # %bb.{{[0-9]+}}: # %if.then ; CHECK-NOT: # %{{[-_a-zA-Z0-9]+}} ; CHECK: # %if.else ; CHECK-NOT: # %{{[-_a-zA-Z0-9]+}} diff --git a/test/CodeGen/PowerPC/tail-dup-layout.ll b/test/CodeGen/PowerPC/tail-dup-layout.ll index 9665901e874fc..badeed5b30a1f 100644 --- a/test/CodeGen/PowerPC/tail-dup-layout.ll +++ b/test/CodeGen/PowerPC/tail-dup-layout.ll @@ -278,7 +278,7 @@ exit: ;CHECK: addi ;CHECK: .[[CHECKLABEL:[._0-9A-Za-z]+]]: # %for.check ;CHECK: lwz [[TAGREG:[0-9]+]], 0([[TAGPTRREG]]) -;CHECK: # %test1 +;CHECK: # %bb.{{[0-9]+}}: # %test1 ;CHECK: andi. {{[0-9]+}}, [[TAGREG]], 1 ;CHECK-NEXT: bc 12, 1, .[[OPT1LABEL:[._0-9A-Za-z]+]] ;CHECK-NEXT: # %test2 @@ -366,12 +366,12 @@ exit: ; code is independent of the outlining code, which works by choosing the ; "unavoidable" blocks. ; CHECK-LABEL: avoidable_test: -; CHECK: # %entry +; CHECK: # %bb.{{[0-9]+}}: # %entry ; CHECK: andi. -; CHECK: # %test2 +; CHECK: # %bb.{{[0-9]+}}: # %test2 ; Make sure then2 falls through from test2 ; CHECK-NOT: # %{{[-_a-zA-Z0-9]+}} -; CHECK: # %then2 +; CHECK: # %bb.{{[0-9]+}}: # %then2 ; CHECK: rlwinm. {{[0-9]+}}, {{[0-9]+}}, 0, 29, 29 ; CHECK: # %else1 ; CHECK: bl a @@ -420,8 +420,8 @@ end1: ; The f;g->h;i trellis should be resolved as f->i;g->h. ; The h;i->j;ret trellis contains a triangle edge, and should be resolved as ; h->j->ret -; CHECK: # %entry -; CHECK: # %c10 +; CHECK: # %bb.{{[0-9]+}}: # %entry +; CHECK: # %bb.{{[0-9]+}}: # %c10 ; CHECK: # %e9 ; CHECK: # %g10 ; CHECK: # %h10 @@ -504,8 +504,8 @@ ret: ; checking, it's profitable to duplicate G into F. The weights here are not ; really important. They are there to help make the test stable. ; CHECK-LABEL: trellis_then_dup_test -; CHECK: # %entry -; CHECK: # %b +; CHECK: # %bb.{{[0-9]+}}: # %entry +; CHECK: # %bb.{{[0-9]+}}: # %b ; CHECK: # %d ; CHECK: # %g ; CHECK: # %ret1 @@ -568,8 +568,8 @@ ret: ; Verify that we did not mis-identify triangle trellises if it is not ; really a triangle. ; CHECK-LABEL: trellis_no_triangle -; CHECK: # %entry -; CHECK: # %b +; CHECK: # %bb.{{[0-9]+}}: # %entry +; CHECK: # %bb.{{[0-9]+}}: # %b ; CHECK: # %d ; CHECK: # %ret ; CHECK: # %c diff --git a/test/CodeGen/PowerPC/testBitReverse.ll b/test/CodeGen/PowerPC/testBitReverse.ll index 1508af9e4d0d5..22fefe4546833 100644 --- a/test/CodeGen/PowerPC/testBitReverse.ll +++ b/test/CodeGen/PowerPC/testBitReverse.ll @@ -4,7 +4,7 @@ declare i32 @llvm.bitreverse.i32(i32) define i32 @testBitReverseIntrinsicI32(i32 %arg) { ; CHECK-LABEL: testBitReverseIntrinsicI32: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: lis 4, -21846 ; CHECK-NEXT: lis 5, 21845 ; CHECK-NEXT: slwi 6, 3, 1 @@ -44,7 +44,7 @@ define i32 @testBitReverseIntrinsicI32(i32 %arg) { declare i64 @llvm.bitreverse.i64(i64) define i64 @testBitReverseIntrinsicI64(i64 %arg) { ; CHECK-LABEL: testBitReverseIntrinsicI64: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: lis 4, -21846 ; CHECK-NEXT: lis 5, 21845 ; CHECK-NEXT: lis 6, -13108 diff --git a/test/CodeGen/PowerPC/testComparesi32gtu.ll b/test/CodeGen/PowerPC/testComparesi32gtu.ll index c6f456aa86434..4341b59390e70 100644 --- a/test/CodeGen/PowerPC/testComparesi32gtu.ll +++ b/test/CodeGen/PowerPC/testComparesi32gtu.ll @@ -1,9 +1,8 @@ -; XFAIL: * ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl %struct.tree_common = type { i8, [3 x i8] } @@ -12,7 +11,7 @@ declare signext i32 @fn2(...) local_unnamed_addr #1 ; Function Attrs: nounwind define i32 @testCompare1(%struct.tree_common* nocapture readonly %arg1) { ; CHECK-LABEL: testCompare1: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK: lbz r3, 0(r3) ; CHECK-DAG: clrlwi r3, r3, 31 ; CHECK-DAG: clrldi r3, r3, 32 @@ -36,7 +35,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define signext i32 @testCompare2(i32 zeroext %a, i32 zeroext %b) { ; CHECK-LABEL: testCompare2: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-DAG: rlwinm r3, r3, 0, 31, 31 ; CHECK-DAG: rlwinm r4, r4, 0, 31, 31 ; CHECK-DAG: clrldi r3, r3, 32 diff --git a/test/CodeGen/PowerPC/testComparesi32leu.ll b/test/CodeGen/PowerPC/testComparesi32leu.ll index 59a3e6693494e..3ba967b51dad0 100644 --- a/test/CodeGen/PowerPC/testComparesi32leu.ll +++ b/test/CodeGen/PowerPC/testComparesi32leu.ll @@ -1,15 +1,14 @@ -; XFAIL: * ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl define signext i32 @test(i8 zeroext %a, i8 zeroext %b) { ; CHECK-LABEL: test: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: rlwinm r3, r3, 0, 31, 31 ; CHECK-NEXT: rlwinm r4, r4, 0, 31, 31 ; CHECK-NEXT: clrldi r3, r3, 32 diff --git a/test/CodeGen/PowerPC/testComparesi32ltu.ll b/test/CodeGen/PowerPC/testComparesi32ltu.ll index 9df93f3e8d4d8..9623a63e9bc37 100644 --- a/test/CodeGen/PowerPC/testComparesi32ltu.ll +++ b/test/CodeGen/PowerPC/testComparesi32ltu.ll @@ -1,9 +1,8 @@ -; XFAIL: * ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl %struct.tree_common = type { i8, [3 x i8] } @@ -12,7 +11,7 @@ declare signext i32 @fn2(...) local_unnamed_addr #1 ; Function Attrs: nounwind define i32 @testCompare1(%struct.tree_common* nocapture readonly %arg1) { ; CHECK-LABEL: testCompare1: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK: lbz r3, 0(r3) ; CHECK-DAG: clrlwi r3, r3, 31 ; CHECK-DAG: clrldi r3, r3, 32 @@ -36,7 +35,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define signext i32 @testCompare2(i32 zeroext %a, i32 zeroext %b) { ; CHECK-LABEL: testCompare2: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-DAG: rlwinm r3, r3, 0, 31, 31 ; CHECK-DAG: rlwinm r4, r4, 0, 31, 31 ; CHECK-DAG: clrldi r3, r3, 32 diff --git a/test/CodeGen/PowerPC/testComparesieqsc.ll b/test/CodeGen/PowerPC/testComparesieqsc.ll index e457dd61b071a..aa0211ebb6507 100644 --- a/test/CodeGen/PowerPC/testComparesieqsc.ll +++ b/test/CodeGen/PowerPC/testComparesieqsc.ll @@ -1,10 +1,9 @@ -; XFAIL: * ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; ModuleID = 'ComparisonTestCases/testComparesieqsc.c' @@ -13,7 +12,7 @@ ; Function Attrs: norecurse nounwind readnone define signext i32 @test_ieqsc(i8 signext %a, i8 signext %b) { ; CHECK-LABEL: test_ieqsc: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 @@ -27,7 +26,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define signext i32 @test_ieqsc_sext(i8 signext %a, i8 signext %b) { ; CHECK-LABEL: test_ieqsc_sext: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 @@ -42,7 +41,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define signext i32 @test_ieqsc_z(i8 signext %a) { ; CHECK-LABEL: test_ieqsc_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: blr @@ -55,7 +54,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define signext i32 @test_ieqsc_sext_z(i8 signext %a) { ; CHECK-LABEL: test_ieqsc_sext_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 @@ -69,7 +68,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_ieqsc_store(i8 signext %a, i8 signext %b) { ; CHECK-LABEL: test_ieqsc_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5) @@ -87,7 +86,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_ieqsc_sext_store(i8 signext %a, i8 signext %b) { ; CHECK-LABEL: test_ieqsc_sext_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 @@ -106,7 +105,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_ieqsc_z_store(i8 signext %a) { ; CHECK-LABEL: test_ieqsc_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) @@ -123,7 +122,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_ieqsc_sext_z_store(i8 signext %a) { ; CHECK-LABEL: test_ieqsc_sext_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) diff --git a/test/CodeGen/PowerPC/testComparesieqsi.ll b/test/CodeGen/PowerPC/testComparesieqsi.ll index fb76f2a0403bf..0a6b7b9ca351a 100644 --- a/test/CodeGen/PowerPC/testComparesieqsi.ll +++ b/test/CodeGen/PowerPC/testComparesieqsi.ll @@ -1,10 +1,9 @@ -; XFAIL: * ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; ModuleID = 'ComparisonTestCases/testComparesieqsi.c' @@ -13,7 +12,7 @@ ; Function Attrs: norecurse nounwind readnone define signext i32 @test_ieqsi(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: test_ieqsi: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 @@ -27,7 +26,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define signext i32 @test_ieqsi_sext(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: test_ieqsi_sext: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 @@ -42,7 +41,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define signext i32 @test_ieqsi_z(i32 signext %a) { ; CHECK-LABEL: test_ieqsi_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: blr @@ -55,7 +54,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define signext i32 @test_ieqsi_sext_z(i32 signext %a) { ; CHECK-LABEL: test_ieqsi_sext_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 @@ -69,7 +68,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_ieqsi_store(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: test_ieqsi_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5) @@ -87,7 +86,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_ieqsi_sext_store(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: test_ieqsi_sext_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 @@ -106,7 +105,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_ieqsi_z_store(i32 signext %a) { ; CHECK-LABEL: test_ieqsi_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) @@ -123,7 +122,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_ieqsi_sext_z_store(i32 signext %a) { ; CHECK-LABEL: test_ieqsi_sext_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) diff --git a/test/CodeGen/PowerPC/testComparesieqsll.ll b/test/CodeGen/PowerPC/testComparesieqsll.ll index bc5f00f6aef77..1dae985c36c19 100644 --- a/test/CodeGen/PowerPC/testComparesieqsll.ll +++ b/test/CodeGen/PowerPC/testComparesieqsll.ll @@ -1,10 +1,9 @@ -; XFAIL: * ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; ModuleID = 'ComparisonTestCases/testComparesieqsll.c' @@ -13,7 +12,7 @@ ; Function Attrs: norecurse nounwind readnone define signext i32 @test_ieqsll(i64 %a, i64 %b) { ; CHECK-LABEL: test_ieqsll: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzd r3, r3 ; CHECK-NEXT: rldicl r3, r3, 58, 63 @@ -27,7 +26,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define signext i32 @test_ieqsll_sext(i64 %a, i64 %b) { ; CHECK-LABEL: test_ieqsll_sext: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: addic r3, r3, -1 ; CHECK-NEXT: subfe r3, r3, r3 @@ -41,7 +40,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define signext i32 @test_ieqsll_z(i64 %a) { ; CHECK-LABEL: test_ieqsll_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cntlzd r3, r3 ; CHECK-NEXT: rldicl r3, r3, 58, 63 ; CHECK-NEXT: blr @@ -54,7 +53,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define signext i32 @test_ieqsll_sext_z(i64 %a) { ; CHECK-LABEL: test_ieqsll_sext_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addic r3, r3, -1 ; CHECK-NEXT: subfe r3, r3, r3 ; CHECK-NEXT: blr @@ -67,7 +66,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_ieqsll_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_ieqsll_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5) @@ -85,7 +84,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_ieqsll_sext_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_ieqsll_sext_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5) @@ -103,7 +102,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_ieqsll_z_store(i64 %a) { ; CHECK-LABEL: test_ieqsll_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzd r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) @@ -120,7 +119,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_ieqsll_sext_z_store(i64 %a) { ; CHECK-LABEL: test_ieqsll_sext_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: addic r3, r3, -1 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) diff --git a/test/CodeGen/PowerPC/testComparesieqss.ll b/test/CodeGen/PowerPC/testComparesieqss.ll index 787fca6d22d25..93a92e1780727 100644 --- a/test/CodeGen/PowerPC/testComparesieqss.ll +++ b/test/CodeGen/PowerPC/testComparesieqss.ll @@ -1,10 +1,9 @@ -; XFAIL: * ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; ModuleID = 'ComparisonTestCases/testComparesieqss.c' @@ -13,7 +12,7 @@ ; Function Attrs: norecurse nounwind readnone define signext i32 @test_ieqss(i16 signext %a, i16 signext %b) { ; CHECK-LABEL: test_ieqss: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 @@ -27,7 +26,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define signext i32 @test_ieqss_sext(i16 signext %a, i16 signext %b) { ; CHECK-LABEL: test_ieqss_sext: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 @@ -42,7 +41,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define signext i32 @test_ieqss_z(i16 signext %a) { ; CHECK-LABEL: test_ieqss_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: blr @@ -55,7 +54,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define signext i32 @test_ieqss_sext_z(i16 signext %a) { ; CHECK-LABEL: test_ieqss_sext_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 @@ -69,7 +68,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_ieqss_store(i16 signext %a, i16 signext %b) { ; CHECK-LABEL: test_ieqss_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5) @@ -87,7 +86,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_ieqss_sext_store(i16 signext %a, i16 signext %b) { ; CHECK-LABEL: test_ieqss_sext_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 @@ -106,7 +105,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_ieqss_z_store(i16 signext %a) { ; CHECK-LABEL: test_ieqss_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) @@ -123,7 +122,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_ieqss_sext_z_store(i16 signext %a) { ; CHECK-LABEL: test_ieqss_sext_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) diff --git a/test/CodeGen/PowerPC/testComparesiequc.ll b/test/CodeGen/PowerPC/testComparesiequc.ll index a9e622796b6c0..592f7bc83bb8d 100644 --- a/test/CodeGen/PowerPC/testComparesiequc.ll +++ b/test/CodeGen/PowerPC/testComparesiequc.ll @@ -1,10 +1,9 @@ -; XFAIL: * ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; ModuleID = 'ComparisonTestCases/testComparesiequc.c' @@ -13,7 +12,7 @@ ; Function Attrs: norecurse nounwind readnone define signext i32 @test_iequc(i8 zeroext %a, i8 zeroext %b) { ; CHECK-LABEL: test_iequc: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 @@ -27,7 +26,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define signext i32 @test_iequc_sext(i8 zeroext %a, i8 zeroext %b) { ; CHECK-LABEL: test_iequc_sext: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 @@ -42,7 +41,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define signext i32 @test_iequc_z(i8 zeroext %a) { ; CHECK-LABEL: test_iequc_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: blr @@ -55,7 +54,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define signext i32 @test_iequc_sext_z(i8 zeroext %a) { ; CHECK-LABEL: test_iequc_sext_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 @@ -69,7 +68,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_iequc_store(i8 zeroext %a, i8 zeroext %b) { ; CHECK-LABEL: test_iequc_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5) @@ -87,7 +86,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_iequc_sext_store(i8 zeroext %a, i8 zeroext %b) { ; CHECK-LABEL: test_iequc_sext_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 @@ -106,7 +105,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_iequc_z_store(i8 zeroext %a) { ; CHECK-LABEL: test_iequc_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) @@ -123,7 +122,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_iequc_sext_z_store(i8 zeroext %a) { ; CHECK-LABEL: test_iequc_sext_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) diff --git a/test/CodeGen/PowerPC/testComparesiequi.ll b/test/CodeGen/PowerPC/testComparesiequi.ll index 5a9f64c9fde57..9a639dc54100c 100644 --- a/test/CodeGen/PowerPC/testComparesiequi.ll +++ b/test/CodeGen/PowerPC/testComparesiequi.ll @@ -1,10 +1,9 @@ -; XFAIL: * ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; ModuleID = 'ComparisonTestCases/testComparesiequi.c' @@ -13,7 +12,7 @@ ; Function Attrs: norecurse nounwind readnone define signext i32 @test_iequi(i32 zeroext %a, i32 zeroext %b) { ; CHECK-LABEL: test_iequi: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 @@ -27,7 +26,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define signext i32 @test_iequi_sext(i32 zeroext %a, i32 zeroext %b) { ; CHECK-LABEL: test_iequi_sext: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 @@ -42,7 +41,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define signext i32 @test_iequi_z(i32 zeroext %a) { ; CHECK-LABEL: test_iequi_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: blr @@ -55,7 +54,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define signext i32 @test_iequi_sext_z(i32 zeroext %a) { ; CHECK-LABEL: test_iequi_sext_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 @@ -69,7 +68,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_iequi_store(i32 zeroext %a, i32 zeroext %b) { ; CHECK-LABEL: test_iequi_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5) @@ -87,7 +86,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_iequi_sext_store(i32 zeroext %a, i32 zeroext %b) { ; CHECK-LABEL: test_iequi_sext_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 @@ -106,7 +105,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_iequi_z_store(i32 zeroext %a) { ; CHECK-LABEL: test_iequi_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) @@ -123,7 +122,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_iequi_sext_z_store(i32 zeroext %a) { ; CHECK-LABEL: test_iequi_sext_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) diff --git a/test/CodeGen/PowerPC/testComparesiequll.ll b/test/CodeGen/PowerPC/testComparesiequll.ll index 95e732baf1d46..f147478d5ea8a 100644 --- a/test/CodeGen/PowerPC/testComparesiequll.ll +++ b/test/CodeGen/PowerPC/testComparesiequll.ll @@ -1,10 +1,9 @@ -; XFAIL: * ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; ModuleID = 'ComparisonTestCases/testComparesiequll.c' @@ -13,7 +12,7 @@ ; Function Attrs: norecurse nounwind readnone define signext i32 @test_iequll(i64 %a, i64 %b) { ; CHECK-LABEL: test_iequll: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzd r3, r3 ; CHECK-NEXT: rldicl r3, r3, 58, 63 @@ -27,7 +26,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define signext i32 @test_iequll_sext(i64 %a, i64 %b) { ; CHECK-LABEL: test_iequll_sext: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: addic r3, r3, -1 ; CHECK-NEXT: subfe r3, r3, r3 @@ -41,7 +40,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define signext i32 @test_iequll_z(i64 %a) { ; CHECK-LABEL: test_iequll_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cntlzd r3, r3 ; CHECK-NEXT: rldicl r3, r3, 58, 63 ; CHECK-NEXT: blr @@ -54,7 +53,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define signext i32 @test_iequll_sext_z(i64 %a) { ; CHECK-LABEL: test_iequll_sext_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addic r3, r3, -1 ; CHECK-NEXT: subfe r3, r3, r3 ; CHECK-NEXT: blr @@ -67,7 +66,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_iequll_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_iequll_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5) @@ -85,7 +84,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_iequll_sext_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_iequll_sext_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5) @@ -103,7 +102,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_iequll_z_store(i64 %a) { ; CHECK-LABEL: test_iequll_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzd r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) @@ -120,7 +119,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_iequll_sext_z_store(i64 %a) { ; CHECK-LABEL: test_iequll_sext_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: addic r3, r3, -1 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) diff --git a/test/CodeGen/PowerPC/testComparesiequs.ll b/test/CodeGen/PowerPC/testComparesiequs.ll index 20f8020d70504..195339ddb2e51 100644 --- a/test/CodeGen/PowerPC/testComparesiequs.ll +++ b/test/CodeGen/PowerPC/testComparesiequs.ll @@ -1,10 +1,9 @@ -; XFAIL: * ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; ModuleID = 'ComparisonTestCases/testComparesiequs.c' @@ -13,7 +12,7 @@ ; Function Attrs: norecurse nounwind readnone define signext i32 @test_iequs(i16 zeroext %a, i16 zeroext %b) { ; CHECK-LABEL: test_iequs: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 @@ -27,7 +26,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define signext i32 @test_iequs_sext(i16 zeroext %a, i16 zeroext %b) { ; CHECK-LABEL: test_iequs_sext: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 @@ -42,7 +41,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define signext i32 @test_iequs_z(i16 zeroext %a) { ; CHECK-LABEL: test_iequs_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: blr @@ -55,7 +54,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define signext i32 @test_iequs_sext_z(i16 zeroext %a) { ; CHECK-LABEL: test_iequs_sext_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 @@ -69,7 +68,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_iequs_store(i16 zeroext %a, i16 zeroext %b) { ; CHECK-LABEL: test_iequs_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5) @@ -87,7 +86,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_iequs_sext_store(i16 zeroext %a, i16 zeroext %b) { ; CHECK-LABEL: test_iequs_sext_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 @@ -106,7 +105,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_iequs_z_store(i16 zeroext %a) { ; CHECK-LABEL: test_iequs_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) @@ -123,7 +122,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_iequs_sext_z_store(i16 zeroext %a) { ; CHECK-LABEL: test_iequs_sext_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) diff --git a/test/CodeGen/PowerPC/testComparesigesc.ll b/test/CodeGen/PowerPC/testComparesigesc.ll index 42d50a602ec14..69dd97fc9c449 100644 --- a/test/CodeGen/PowerPC/testComparesigesc.ll +++ b/test/CodeGen/PowerPC/testComparesigesc.ll @@ -1,16 +1,15 @@ -; XFAIL: * +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl -; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py @glob = common local_unnamed_addr global i8 0, align 1 define signext i32 @test_igesc(i8 signext %a, i8 signext %b) { ; CHECK-LABEL: test_igesc: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: xori r3, r3, 1 @@ -23,7 +22,7 @@ entry: define signext i32 @test_igesc_sext(i8 signext %a, i8 signext %b) { ; CHECK-LABEL: test_igesc_sext: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: addi r3, r3, -1 @@ -36,7 +35,7 @@ entry: define void @test_igesc_store(i8 signext %a, i8 signext %b) { ; CHECK-LABEL: test_igesc_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5) @@ -53,7 +52,7 @@ entry: define void @test_igesc_sext_store(i8 signext %a, i8 signext %b) { ; CHECK-LABEL: test_igesc_sext_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5) diff --git a/test/CodeGen/PowerPC/testComparesigesi.ll b/test/CodeGen/PowerPC/testComparesigesi.ll index 316f8ed5600fc..7efc8ae82450b 100644 --- a/test/CodeGen/PowerPC/testComparesigesi.ll +++ b/test/CodeGen/PowerPC/testComparesigesi.ll @@ -1,16 +1,15 @@ -; XFAIL: * ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py @glob = common local_unnamed_addr global i32 0, align 4 define signext i32 @test_igesi(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: test_igesi: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: xori r3, r3, 1 @@ -23,7 +22,7 @@ entry: define signext i32 @test_igesi_sext(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: test_igesi_sext: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: addi r3, r3, -1 @@ -36,7 +35,7 @@ entry: define void @test_igesi_store(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: test_igesi_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5) @@ -53,7 +52,7 @@ entry: define void @test_igesi_sext_store(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: test_igesi_sext_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5) diff --git a/test/CodeGen/PowerPC/testComparesigesll.ll b/test/CodeGen/PowerPC/testComparesigesll.ll index 30ed8c0e959f7..30efe3da3e91d 100644 --- a/test/CodeGen/PowerPC/testComparesigesll.ll +++ b/test/CodeGen/PowerPC/testComparesigesll.ll @@ -1,16 +1,15 @@ -; XFAIL: * ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py @glob = common local_unnamed_addr global i64 0, align 8 define signext i32 @test_igesll(i64 %a, i64 %b) { ; CHECK-LABEL: test_igesll: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: sradi r5, r3, 63 ; CHECK-NEXT: rldicl r6, r4, 1, 63 ; CHECK-NEXT: subfc r3, r4, r3 @@ -24,7 +23,7 @@ entry: define signext i32 @test_igesll_sext(i64 %a, i64 %b) { ; CHECK-LABEL: test_igesll_sext: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: sradi r5, r3, 63 ; CHECK-NEXT: rldicl r6, r4, 1, 63 ; CHECK-NEXT: subfc r3, r4, r3 @@ -39,7 +38,7 @@ entry: define signext i32 @test_igesll_z(i64 %a) { ; CHECK-LABEL: test_igesll_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: blr @@ -51,7 +50,7 @@ entry: define signext i32 @test_igesll_sext_z(i64 %a) { ; CHECK-LABEL: test_igesll_sext_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: sradi r3, r3, 63 ; CHECK-NEXT: not r3, r3 ; CHECK-NEXT: blr @@ -63,7 +62,7 @@ entry: define void @test_igesll_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_igesll_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK: sradi r6, r3, 63 ; CHECK: subfc r3, r4, r3 ; CHECK: rldicl r3, r4, 1, 63 @@ -79,7 +78,7 @@ entry: define void @test_igesll_sext_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_igesll_sext_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: sradi r6, r3, 63 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: subfc r3, r4, r3 @@ -98,7 +97,7 @@ entry: define void @test_igesll_z_store(i64 %a) { ; CHECK-LABEL: test_igesll_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) @@ -114,7 +113,7 @@ entry: define void @test_igesll_sext_z_store(i64 %a) { ; CHECK-LABEL: test_igesll_sext_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: sradi r3, r3, 63 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) diff --git a/test/CodeGen/PowerPC/testComparesigess.ll b/test/CodeGen/PowerPC/testComparesigess.ll index abcb556d0c39a..231a26c916db0 100644 --- a/test/CodeGen/PowerPC/testComparesigess.ll +++ b/test/CodeGen/PowerPC/testComparesigess.ll @@ -1,16 +1,15 @@ -; XFAIL: * +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl -; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py @glob = common local_unnamed_addr global i16 0, align 2 define signext i32 @test_igess(i16 signext %a, i16 signext %b) { ; CHECK-LABEL: test_igess: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: xori r3, r3, 1 @@ -23,7 +22,7 @@ entry: define signext i32 @test_igess_sext(i16 signext %a, i16 signext %b) { ; CHECK-LABEL: test_igess_sext: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: addi r3, r3, -1 @@ -36,7 +35,7 @@ entry: define void @test_igess_store(i16 signext %a, i16 signext %b) { ; CHECK-LABEL: test_igess_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5) @@ -53,7 +52,7 @@ entry: define void @test_igess_sext_store(i16 signext %a, i16 signext %b) { ; CHECK-LABEL: test_igess_sext_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5) diff --git a/test/CodeGen/PowerPC/testComparesigeuc.ll b/test/CodeGen/PowerPC/testComparesigeuc.ll index 3cb7b33e14736..cdc67ec335d07 100644 --- a/test/CodeGen/PowerPC/testComparesigeuc.ll +++ b/test/CodeGen/PowerPC/testComparesigeuc.ll @@ -1,9 +1,8 @@ -; XFAIL: * ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl @glob = common local_unnamed_addr global i8 0, align 1 diff --git a/test/CodeGen/PowerPC/testComparesigeui.ll b/test/CodeGen/PowerPC/testComparesigeui.ll index 165460c26cbf6..a77cea72cfa9c 100644 --- a/test/CodeGen/PowerPC/testComparesigeui.ll +++ b/test/CodeGen/PowerPC/testComparesigeui.ll @@ -1,9 +1,8 @@ -; XFAIL: * ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl @glob = common local_unnamed_addr global i32 0, align 4 @@ -106,8 +105,10 @@ entry: store i32 %conv1, i32* @glob ret void ; CHECK-LABEL: @test_igeui_sext_z_store -; CHECK: li [[REG1:r[0-9]+]], -1 -; CHECK: stw [[REG1]] -; CHECK: blr +; CHECK: li [[REG1:r[0-9]+]], 0 +; CHECK: oris [[REG2:r[0-9]+]], [[REG1]], 65535 +; CHECK: ori [[REG3:r[0-9]+]], [[REG2]], 65535 +; CHECK: stw [[REG3]] +; CHECK: blr } diff --git a/test/CodeGen/PowerPC/testComparesigeull.ll b/test/CodeGen/PowerPC/testComparesigeull.ll new file mode 100644 index 0000000000000..103eeb1c70593 --- /dev/null +++ b/test/CodeGen/PowerPC/testComparesigeull.ll @@ -0,0 +1,111 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl + +@glob = common local_unnamed_addr global i64 0, align 8 + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_igeull(i64 %a, i64 %b) { +entry: + %cmp = icmp uge i64 %a, %b + %conv = zext i1 %cmp to i32 + ret i32 %conv +; CHECK-LABEL: test_igeull: +; CHECK: subfc {{r[0-9]+}}, r4, r3 +; CHECK-NEXT: subfe [[REG1:r[0-9]+]], r4, r4 +; CHECK-NEXT: addi r3, [[REG1]], 1 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_igeull_sext(i64 %a, i64 %b) { +entry: + %cmp = icmp uge i64 %a, %b + %sub = sext i1 %cmp to i32 + ret i32 %sub +; CHECK-LABEL: @test_igeull_sext +; CHECK: subfc [[REG1:r[0-9]+]], r4, r3 +; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}} +; CHECK: not r3, [[REG2]] +; CHECK: blr +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_igeull_z(i64 %a) { +entry: + %cmp = icmp uge i64 %a, 0 + %sub = zext i1 %cmp to i32 + ret i32 %sub +; CHECK-LABEL: @test_igeull_z +; CHECK: li r3, 1 +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_igeull_sext_z(i64 %a) { +entry: + %cmp = icmp uge i64 %a, 0 + %sub = sext i1 %cmp to i32 + ret i32 %sub +; CHECK-LABEL: @test_igeull_sext_z +; CHECK: li r3, -1 +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind +define void @test_igeull_store(i64 %a, i64 %b) { +entry: + %cmp = icmp uge i64 %a, %b + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob + ret void +; CHECK-LABEL: test_igeull_store: +; CHECK: subfc {{r[0-9]+}}, r4, r3 +; CHECK: subfe [[REG1:r[0-9]+]], r4, r4 +; CHECK: addi {{r[0-9]+}}, [[REG1]], 1 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_igeull_sext_store(i64 %a, i64 %b) { +entry: + %cmp = icmp uge i64 %a, %b + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob + ret void +; CHECK-LABEL: @test_igeull_sext_store +; CHECK: subfc [[REG1:r[0-9]+]], r4, r3 +; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}} +; CHECK: not [[REG3:r[0-9]+]], [[REG2]] +; CHECK: std [[REG3]] +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_igeull_z_store(i64 %a) { +entry: + %cmp = icmp uge i64 %a, 0 + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob + ret void +; CHECK-LABEL: @test_igeull_z_store +; CHECK: li [[REG1:r[0-9]+]], 1 +; CHECK: std [[REG1]] +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_igeull_sext_z_store(i64 %a) { +entry: + %cmp = icmp uge i64 %a, 0 + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob + ret void +; CHECK-LABEL: @test_igeull_sext_z_store +; CHECK: li [[REG1:r[0-9]+]], -1 +; CHECK: std [[REG1]] +; CHECK: blr +} diff --git a/test/CodeGen/PowerPC/testComparesigeus.ll b/test/CodeGen/PowerPC/testComparesigeus.ll index 58a876fbca390..65693b5ebbfa3 100644 --- a/test/CodeGen/PowerPC/testComparesigeus.ll +++ b/test/CodeGen/PowerPC/testComparesigeus.ll @@ -1,9 +1,8 @@ -; XFAIL: * ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl @glob = common local_unnamed_addr global i16 0, align 2 @@ -106,7 +105,7 @@ entry: store i16 %conv3, i16* @glob ret void ; CHECK-LABEL: @test_igeus_sext_z_store -; CHECK: lis [[REG1:r[0-9]+]], 0 +; CHECK: li [[REG1:r[0-9]+]], 0 ; CHECK: ori [[REG2:r[0-9]+]], [[REG1]], 65535 ; CHECK: sth [[REG2]] ; CHECK: blr diff --git a/test/CodeGen/PowerPC/testComparesigtsc.ll b/test/CodeGen/PowerPC/testComparesigtsc.ll index 32eb2c833b262..8009043c45d95 100644 --- a/test/CodeGen/PowerPC/testComparesigtsc.ll +++ b/test/CodeGen/PowerPC/testComparesigtsc.ll @@ -1,17 +1,16 @@ -; XFAIL: * ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ -; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ -; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl @glob = common local_unnamed_addr global i8 0, align 1 ; Function Attrs: norecurse nounwind readnone define signext i32 @test_igtsc(i8 signext %a, i8 signext %b) { ; CHECK-LABEL: test_igtsc: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: sub [[REG:r[0-9]+]], r4, r3 ; CHECK-NEXT: rldicl r3, [[REG]], 1, 63 ; CHECK-NEXT: blr @@ -24,7 +23,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define signext i32 @test_igtsc_sext(i8 signext %a, i8 signext %b) { ; CHECK-LABEL: test_igtsc_sext: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: sub [[REG:r[0-9]+]], r4, r3 ; CHECK-NEXT: sradi r3, [[REG]], 63 ; CHECK-NEXT: blr @@ -38,7 +37,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define signext i32 @test_igtsc_z(i8 signext %a) { ; CHECK-LABEL: test_igtsc_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: blr @@ -63,7 +62,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_igtsc_store(i8 signext %a, i8 signext %b) { ; CHECK-LABEL: test_igtsc_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK: sub [[REG:r[0-9]+]], r4, r3 ; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63 entry: @@ -76,7 +75,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_igtsc_sext_store(i8 signext %a, i8 signext %b) { ; CHECK-LABEL: test_igtsc_sext_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK: sub [[REG:r[0-9]+]], r4, r3 ; CHECK: sradi {{r[0-9]+}}, [[REG]], 63 entry: @@ -90,7 +89,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_igtsc_z_store(i8 signext %a) { ; CHECK-LABEL: test_igtsc_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) diff --git a/test/CodeGen/PowerPC/testComparesigtsi.ll b/test/CodeGen/PowerPC/testComparesigtsi.ll index 4d8c235267a39..77dfc3583f1ae 100644 --- a/test/CodeGen/PowerPC/testComparesigtsi.ll +++ b/test/CodeGen/PowerPC/testComparesigtsi.ll @@ -1,9 +1,8 @@ -; XFAIL: * ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl @glob = common local_unnamed_addr global i32 0, align 4 @@ -11,7 +10,7 @@ ; Function Attrs: norecurse nounwind readnone define signext i32 @test_igtsi(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: test_igtsi: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: sub [[REG:r[0-9]+]], r4, r3 ; CHECK-NEXT: rldicl r3, [[REG]], 1, 63 ; CHECK-NEXT: blr @@ -24,7 +23,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define signext i32 @test_igtsi_sext(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: test_igtsi_sext: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: sub [[REG:r[0-9]+]], r4, r3 ; CHECK-NEXT: sradi r3, [[REG]], 63 ; CHECK-NEXT: blr @@ -38,7 +37,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define signext i32 @test_igtsi_z(i32 signext %a) { ; CHECK-LABEL: test_igtsi_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: blr @@ -63,7 +62,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_igtsi_store(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: test_igtsi_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK: sub [[REG:r[0-9]+]], r4, r3 ; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63 entry: @@ -76,7 +75,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_igtsi_sext_store(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: test_igtsi_sext_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK: sub [[REG:r[0-9]+]], r4, r3 ; CHECK: sradi {{r[0-9]+}}, [[REG]], 63 entry: @@ -90,7 +89,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_igtsi_z_store(i32 signext %a) { ; CHECK-LABEL: test_igtsi_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) diff --git a/test/CodeGen/PowerPC/testComparesigtsll.ll b/test/CodeGen/PowerPC/testComparesigtsll.ll index abf120c55dd08..75314d708f525 100644 --- a/test/CodeGen/PowerPC/testComparesigtsll.ll +++ b/test/CodeGen/PowerPC/testComparesigtsll.ll @@ -1,9 +1,8 @@ -; XFAIL: * ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl @glob = common local_unnamed_addr global i64 0, align 8 @@ -11,7 +10,7 @@ ; Function Attrs: norecurse nounwind readnone define signext i32 @test_igtsll(i64 %a, i64 %b) { ; CHECK-LABEL: test_igtsll: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: sradi [[REG1:r[0-9]+]], r4, 63 ; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], r3, 1, 63 ; CHECK-NEXT: subfc [[REG3:r[0-9]+]], r3, r4 @@ -27,7 +26,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define signext i32 @test_igtsll_sext(i64 %a, i64 %b) { ; CHECK-LABEL: test_igtsll_sext: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: sradi [[REG1:r[0-9]+]], r4, 63 ; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], r3, 1, 63 ; CHECK-NEXT: subfc [[REG3:r[0-9]+]], r3, r4 @@ -45,7 +44,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define signext i32 @test_igtsll_z(i64 %a) { ; CHECK-LABEL: test_igtsll_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addi r4, r3, -1 ; CHECK-NEXT: nor r3, r4, r3 ; CHECK-NEXT: rldicl r3, r3, 1, 63 @@ -71,7 +70,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_igtsll_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_igtsll_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK: sradi [[REG1:r[0-9]+]], r4, 63 ; CHECK: rldicl [[REG2:r[0-9]+]], r3, 1, 63 ; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r3, r4 @@ -88,7 +87,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_igtsll_sext_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_igtsll_sext_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK: sradi [[REG1:r[0-9]+]], r4, 63 ; CHECK: rldicl [[REG2:r[0-9]+]], r3, 1, 63 ; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r3, r4 @@ -106,7 +105,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_igtsll_z_store(i64 %a) { ; CHECK-LABEL: test_igtsll_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: addi r5, r3, -1 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) diff --git a/test/CodeGen/PowerPC/testComparesigtss.ll b/test/CodeGen/PowerPC/testComparesigtss.ll index a8e0e0a04e652..23ddbe30f7e45 100644 --- a/test/CodeGen/PowerPC/testComparesigtss.ll +++ b/test/CodeGen/PowerPC/testComparesigtss.ll @@ -1,17 +1,16 @@ -; XFAIL: * ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ -; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ -; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl @glob = common local_unnamed_addr global i16 0, align 2 ; Function Attrs: norecurse nounwind readnone define signext i32 @test_igtss(i16 signext %a, i16 signext %b) { ; CHECK-LABEL: test_igtss: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: sub [[REG1:r[0-9]+]], r4, r3 ; CHECK-NEXT: rldicl r3, [[REG1]], 1, 63 ; CHECK-NEXT: blr @@ -24,7 +23,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define signext i32 @test_igtss_sext(i16 signext %a, i16 signext %b) { ; CHECK-LABEL: test_igtss_sext: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: sub [[REG:r[0-9]+]], r4, r3 ; CHECK-NEXT: sradi r3, [[REG]], 63 ; CHECK-NEXT: blr @@ -38,7 +37,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define signext i32 @test_igtss_z(i16 signext %a) { ; CHECK-LABEL: test_igtss_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: blr @@ -51,7 +50,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define signext i32 @test_igtss_sext_z(i16 signext %a) { ; CHECK-LABEL: test_igtss_sext_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK: neg [[REG2:r[0-9]+]], r3 ; CHECK-NEXT: sradi r3, [[REG2]], 63 ; CHECK-NEXT: blr @@ -64,7 +63,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_igtss_store(i16 signext %a, i16 signext %b) { ; CHECK-LABEL: test_igtss_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK: sub [[REG1:r[0-9]+]], r4, r3 ; CHECK: rldicl {{r[0-9]+}}, [[REG1]], 1, 63 entry: @@ -77,7 +76,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_igtss_sext_store(i16 signext %a, i16 signext %b) { ; CHECK-LABEL: test_igtss_sext_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK: sub [[REG:r[0-9]+]], r4, r3 ; CHECK: sradi {{r[0-9]+}}, [[REG]], 63 entry: @@ -91,7 +90,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_igtss_z_store(i16 signext %a) { ; CHECK-LABEL: test_igtss_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) diff --git a/test/CodeGen/PowerPC/testComparesigtuc.ll b/test/CodeGen/PowerPC/testComparesigtuc.ll index 068e8bd73467d..540b82001c2cf 100644 --- a/test/CodeGen/PowerPC/testComparesigtuc.ll +++ b/test/CodeGen/PowerPC/testComparesigtuc.ll @@ -1,9 +1,8 @@ -; XFAIL: * ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl @glob = common local_unnamed_addr global i8 0, align 1 diff --git a/test/CodeGen/PowerPC/testComparesigtui.ll b/test/CodeGen/PowerPC/testComparesigtui.ll index c17919a36b652..6fef78c6b0b96 100644 --- a/test/CodeGen/PowerPC/testComparesigtui.ll +++ b/test/CodeGen/PowerPC/testComparesigtui.ll @@ -1,9 +1,8 @@ -; XFAIL: * ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl @glob = common local_unnamed_addr global i32 0, align 4 diff --git a/test/CodeGen/PowerPC/testComparesigtus.ll b/test/CodeGen/PowerPC/testComparesigtus.ll index ad5df67349234..07e810115f977 100644 --- a/test/CodeGen/PowerPC/testComparesigtus.ll +++ b/test/CodeGen/PowerPC/testComparesigtus.ll @@ -1,9 +1,8 @@ -; XFAIL: * ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl @glob = common local_unnamed_addr global i16 0, align 2 diff --git a/test/CodeGen/PowerPC/testComparesilesc.ll b/test/CodeGen/PowerPC/testComparesilesc.ll index a605a8443af79..422dc3adc5d64 100644 --- a/test/CodeGen/PowerPC/testComparesilesc.ll +++ b/test/CodeGen/PowerPC/testComparesilesc.ll @@ -1,16 +1,15 @@ -; XFAIL: * ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ -; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ -; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py @glob = common local_unnamed_addr global i8 0, align 1 define signext i32 @test_ilesc(i8 signext %a, i8 signext %b) { ; CHECK-LABEL: test_ilesc: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: xori r3, r3, 1 @@ -23,7 +22,7 @@ entry: define signext i32 @test_ilesc_sext(i8 signext %a, i8 signext %b) { ; CHECK-LABEL: test_ilesc_sext: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: addi r3, r3, -1 @@ -36,7 +35,7 @@ entry: define void @test_ilesc_store(i8 signext %a, i8 signext %b) { ; CHECK-LABEL: test_ilesc_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5) @@ -53,7 +52,7 @@ entry: define void @test_ilesc_sext_store(i8 signext %a, i8 signext %b) { ; CHECK-LABEL: test_ilesc_sext_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5) diff --git a/test/CodeGen/PowerPC/testComparesilesi.ll b/test/CodeGen/PowerPC/testComparesilesi.ll index fff978f7f4f59..72439bd9aa3a8 100644 --- a/test/CodeGen/PowerPC/testComparesilesi.ll +++ b/test/CodeGen/PowerPC/testComparesilesi.ll @@ -1,16 +1,15 @@ -; XFAIL: * ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py @glob = common local_unnamed_addr global i32 0, align 4 define signext i32 @test_ilesi(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: test_ilesi: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: xori r3, r3, 1 @@ -23,7 +22,7 @@ entry: define signext i32 @test_ilesi_sext(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: test_ilesi_sext: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: addi r3, r3, -1 @@ -36,7 +35,7 @@ entry: define void @test_ilesi_store(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: test_ilesi_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5) @@ -53,7 +52,7 @@ entry: define void @test_ilesi_sext_store(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: test_ilesi_sext_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5) diff --git a/test/CodeGen/PowerPC/testComparesilesll.ll b/test/CodeGen/PowerPC/testComparesilesll.ll index 74a770178bae5..21b67664c30d0 100644 --- a/test/CodeGen/PowerPC/testComparesilesll.ll +++ b/test/CodeGen/PowerPC/testComparesilesll.ll @@ -1,16 +1,15 @@ -; XFAIL: * ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py @glob = common local_unnamed_addr global i64 0, align 8 define signext i32 @test_ilesll(i64 %a, i64 %b) { ; CHECK-LABEL: test_ilesll: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: sradi r5, r4, 63 ; CHECK-NEXT: rldicl r6, r3, 1, 63 ; CHECK-NEXT: subfc r12, r3, r4 @@ -24,7 +23,7 @@ entry: define signext i32 @test_ilesll_sext(i64 %a, i64 %b) { ; CHECK-LABEL: test_ilesll_sext: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: sradi r5, r4, 63 ; CHECK-NEXT: rldicl r6, r3, 1, 63 ; CHECK-NEXT: subfc r12, r3, r4 @@ -39,7 +38,7 @@ entry: define signext i32 @test_ilesll_z(i64 %a) { ; CHECK-LABEL: test_ilesll_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addi r4, r3, -1 ; CHECK-NEXT: or r3, r4, r3 ; CHECK-NEXT: rldicl r3, r3, 1, 63 @@ -52,7 +51,7 @@ entry: define signext i32 @test_ilesll_sext_z(i64 %a) { ; CHECK-LABEL: test_ilesll_sext_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addi r4, r3, -1 ; CHECK-NEXT: or r3, r4, r3 ; CHECK-NEXT: sradi r3, r3, 63 @@ -65,7 +64,7 @@ entry: define void @test_ilesll_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_ilesll_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK: sradi r6, r4, 63 ; CHECK: subfc r4, r3, r4 ; CHECK: rldicl r3, r3, 1, 63 @@ -81,7 +80,7 @@ entry: define void @test_ilesll_sext_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_ilesll_sext_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK: sradi r6, r4, 63 ; CHECK-DAG: rldicl r3, r3, 1, 63 ; CHECK-DAG: subfc r4, r3, r4 @@ -98,7 +97,7 @@ entry: define void @test_ilesll_z_store(i64 %a) { ; CHECK-LABEL: test_ilesll_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: addi r5, r3, -1 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) @@ -115,7 +114,7 @@ entry: define void @test_ilesll_sext_z_store(i64 %a) { ; CHECK-LABEL: test_ilesll_sext_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: addi r5, r3, -1 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) diff --git a/test/CodeGen/PowerPC/testComparesiless.ll b/test/CodeGen/PowerPC/testComparesiless.ll index b985bc5f7b48d..c85ff6078e7de 100644 --- a/test/CodeGen/PowerPC/testComparesiless.ll +++ b/test/CodeGen/PowerPC/testComparesiless.ll @@ -1,16 +1,15 @@ -; XFAIL: * ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ -; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ -; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py @glob = common local_unnamed_addr global i16 0, align 2 define signext i32 @test_iless(i16 signext %a, i16 signext %b) { ; CHECK-LABEL: test_iless: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: xori r3, r3, 1 @@ -23,7 +22,7 @@ entry: define signext i32 @test_iless_sext(i16 signext %a, i16 signext %b) { ; CHECK-LABEL: test_iless_sext: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: addi r3, r3, -1 @@ -36,7 +35,7 @@ entry: define void @test_iless_store(i16 signext %a, i16 signext %b) { ; CHECK-LABEL: test_iless_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5) @@ -53,7 +52,7 @@ entry: define void @test_iless_sext_store(i16 signext %a, i16 signext %b) { ; CHECK-LABEL: test_iless_sext_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5) diff --git a/test/CodeGen/PowerPC/testComparesileuc.ll b/test/CodeGen/PowerPC/testComparesileuc.ll index 072d89fa40bf7..b387d4b867f7e 100644 --- a/test/CodeGen/PowerPC/testComparesileuc.ll +++ b/test/CodeGen/PowerPC/testComparesileuc.ll @@ -1,9 +1,8 @@ -; XFAIL: * ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl @glob = common local_unnamed_addr global i8 0, align 1 diff --git a/test/CodeGen/PowerPC/testComparesileui.ll b/test/CodeGen/PowerPC/testComparesileui.ll index 5c614bc2d4d60..fd80167e50aef 100644 --- a/test/CodeGen/PowerPC/testComparesileui.ll +++ b/test/CodeGen/PowerPC/testComparesileui.ll @@ -1,9 +1,8 @@ -; XFAIL: * ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl @glob = common local_unnamed_addr global i32 0, align 4 diff --git a/test/CodeGen/PowerPC/testComparesileull.ll b/test/CodeGen/PowerPC/testComparesileull.ll new file mode 100644 index 0000000000000..afcf0ce4bbdb0 --- /dev/null +++ b/test/CodeGen/PowerPC/testComparesileull.ll @@ -0,0 +1,115 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl + +@glob = common local_unnamed_addr global i64 0, align 8 + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_ileull(i64 %a, i64 %b) { +entry: + %cmp = icmp ule i64 %a, %b + %conv = zext i1 %cmp to i32 + ret i32 %conv +; CHECK-LABEL: test_ileull: +; CHECK: subfc {{r[0-9]+}}, r3, r4 +; CHECK-NEXT: subfe [[REG1:r[0-9]+]], r3, r3 +; CHECK-NEXT: addi r3, [[REG1]], 1 +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_ileull_sext(i64 %a, i64 %b) { +entry: + %cmp = icmp ule i64 %a, %b + %sub = sext i1 %cmp to i32 + ret i32 %sub +; CHECK-LABEL: @test_ileull_sext +; CHECK: subfc [[REG1:r[0-9]+]], r3, r4 +; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}} +; CHECK: not r3, [[REG2]] +; CHECK: blr +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_ileull_z(i64 %a) { +entry: + %cmp = icmp ule i64 %a, 0 + %conv = zext i1 %cmp to i32 + ret i32 %conv +; CHECK-LABEL: test_ileull_z +; CHECK: cntlzd [[REG1:r[0-9]+]], r3 +; CHECK-NEXT: rldicl r3, [[REG1]], 58, 63 +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_ileull_sext_z(i64 %a) { +entry: + %cmp = icmp ule i64 %a, 0 + %sub = sext i1 %cmp to i32 + ret i32 %sub +; CHECK-LABEL: @test_ileull_sext_z +; CHECK: addic [[REG1:r[0-9]+]], r3, -1 +; CHECK: subfe r3, [[REG1]] +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_ileull_store(i64 %a, i64 %b) { +entry: + %cmp = icmp ule i64 %a, %b + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob + ret void +; CHECK-LABEL: test_ileull_store: +; CHECK: subfc {{r[0-9]+}}, r3, r4 +; CHECK: subfe [[REG1:r[0-9]+]], r3, r3 +; CHECK: addi {{r[0-9]+}}, [[REG1]], 1 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_ileull_sext_store(i64 %a, i64 %b) { +entry: + %cmp = icmp ule i64 %a, %b + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob + ret void +; CHECK-LABEL: @test_ileull_sext_store +; CHECK: subfc [[REG1:r[0-9]+]], r3, r4 +; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}} +; CHECK: not [[REG3:r[0-9]+]], [[REG2]] +; CHECK: std [[REG3]] +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_ileull_z_store(i64 %a) { +entry: + %cmp = icmp ule i64 %a, 0 + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob + ret void +; CHECK-LABEL: test_ileull_z_store: +; CHECK: cntlzd [[REG1:r[0-9]+]], r3 +; CHECK: rldicl {{r[0-9]+}}, [[REG1]], 58, 63 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_ileull_sext_z_store(i64 %a) { +entry: + %cmp = icmp ule i64 %a, 0 + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob + ret void +; CHECK-LABEL: @test_ileull_sext_z_store +; CHECK: addic [[REG1:r[0-9]+]], r3, -1 +; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}} +; CHECK: std [[REG2]] +; CHECK: blr +} + diff --git a/test/CodeGen/PowerPC/testComparesileus.ll b/test/CodeGen/PowerPC/testComparesileus.ll index b2034f7e41d67..6e54c5a521005 100644 --- a/test/CodeGen/PowerPC/testComparesileus.ll +++ b/test/CodeGen/PowerPC/testComparesileus.ll @@ -1,9 +1,8 @@ -; XFAIL: * ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl @glob = common local_unnamed_addr global i16 0, align 2 diff --git a/test/CodeGen/PowerPC/testComparesiltsc.ll b/test/CodeGen/PowerPC/testComparesiltsc.ll index 0161dd060e6cb..08a023302bddf 100644 --- a/test/CodeGen/PowerPC/testComparesiltsc.ll +++ b/test/CodeGen/PowerPC/testComparesiltsc.ll @@ -1,10 +1,9 @@ -; XFAIL: * ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ -; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ -; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py @glob = common local_unnamed_addr global i8 0, align 1 @@ -12,7 +11,7 @@ ; Function Attrs: norecurse nounwind readnone define signext i32 @test_iltsc(i8 signext %a, i8 signext %b) { ; CHECK-LABEL: test_iltsc: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: sub [[REG:r[0-9]+]], r3, r4 ; CHECK-NEXT: rldicl r3, [[REG]], 1, 63 ; CHECK-NEXT: blr @@ -25,7 +24,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define signext i32 @test_iltsc_sext(i8 signext %a, i8 signext %b) { ; CHECK-LABEL: test_iltsc_sext: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: sub [[REG:r[0-9]+]], r3, r4 ; CHECK-NEXT: sradi r3, [[REG]], 63 ; CHECK-NEXT: blr @@ -49,7 +48,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_iltsc_store(i8 signext %a, i8 signext %b) { ; CHECK-LABEL: test_iltsc_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK: sub [[REG:r[0-9]+]], r3, r4 ; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63 entry: @@ -62,7 +61,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_iltsc_sext_store(i8 signext %a, i8 signext %b) { ; CHECK-LABEL: test_iltsc_sext_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK: sub [[REG:r[0-9]+]], r3, r4 ; CHECK: sradi {{r[0-9]+}}, [[REG]], 63 entry: diff --git a/test/CodeGen/PowerPC/testComparesiltsi.ll b/test/CodeGen/PowerPC/testComparesiltsi.ll index 6f2148ce0fe88..39f37387f534f 100644 --- a/test/CodeGen/PowerPC/testComparesiltsi.ll +++ b/test/CodeGen/PowerPC/testComparesiltsi.ll @@ -1,9 +1,8 @@ -; XFAIL: * ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py @@ -12,7 +11,7 @@ ; Function Attrs: norecurse nounwind readnone define signext i32 @test_iltsi(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: test_iltsi: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: sub [[REG:r[0-9]+]], r3, r4 ; CHECK-NEXT: rldicl r3, [[REG]], 1, 63 ; CHECK-NEXT: blr @@ -25,7 +24,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define signext i32 @test_iltsi_sext(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: test_iltsi_sext: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: sub [[REG:r[0-9]+]], r3, r4 ; CHECK-NEXT: sradi r3, [[REG]], 63 ; CHECK-NEXT: blr @@ -38,7 +37,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define signext i32 @test_iltsi_sext_z(i32 signext %a) { ; CHECK-LABEL: test_iltsi_sext_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: srawi r3, r3, 31 ; CHECK-NEXT: blr entry: @@ -50,7 +49,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_iltsi_store(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: test_iltsi_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK: sub [[REG:r[0-9]+]], r3, r4 ; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63 entry: @@ -63,7 +62,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_iltsi_sext_store(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: test_iltsi_sext_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK: sub [[REG:r[0-9]+]], r3, r4 ; CHECK: sradi {{r[0-9]+}}, [[REG]], 63 entry: diff --git a/test/CodeGen/PowerPC/testComparesiltsll.ll b/test/CodeGen/PowerPC/testComparesiltsll.ll index 6fbf8bca92bde..4152b8556df00 100644 --- a/test/CodeGen/PowerPC/testComparesiltsll.ll +++ b/test/CodeGen/PowerPC/testComparesiltsll.ll @@ -1,9 +1,8 @@ -; XFAIL: * ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py @@ -12,7 +11,7 @@ ; Function Attrs: norecurse nounwind readnone define signext i32 @test_iltsll(i64 %a, i64 %b) { ; CHECK-LABEL: test_iltsll: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: sradi [[REG1:r[0-9]+]], r3, 63 ; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], r4, 1, 63 ; CHECK-NEXT: subfc [[REG3:r[0-9]+]], r4, r3 @@ -28,7 +27,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define signext i32 @test_iltsll_sext(i64 %a, i64 %b) { ; CHECK-LABEL: test_iltsll_sext: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: sradi [[REG1:r[0-9]+]], r3, 63 ; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], r4, 1, 63 ; CHECK-NEXT: subfc [[REG3:r[0-9]+]], r4, r3 @@ -45,7 +44,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define signext i32 @test_iltsll_sext_z(i64 %a) { ; CHECK-LABEL: test_iltsll_sext_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: sradi r3, r3, 63 ; CHECK-NEXT: blr entry: @@ -57,7 +56,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_iltsll_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_iltsll_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK: sradi [[REG1:r[0-9]+]], r3, 63 ; CHECK: rldicl [[REG2:r[0-9]+]], r4, 1, 63 ; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r4, r3 @@ -74,7 +73,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_iltsll_sext_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_iltsll_sext_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK: sradi [[REG1:r[0-9]+]], r3, 63 ; CHECK: rldicl [[REG2:r[0-9]+]], r4, 1, 63 ; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r4, r3 diff --git a/test/CodeGen/PowerPC/testComparesiltss.ll b/test/CodeGen/PowerPC/testComparesiltss.ll index f538e18b8c3fb..db5a60dfb66b4 100644 --- a/test/CodeGen/PowerPC/testComparesiltss.ll +++ b/test/CodeGen/PowerPC/testComparesiltss.ll @@ -1,10 +1,9 @@ -; XFAIL: * ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ -; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ -; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py @glob = common local_unnamed_addr global i16 0, align 2 @@ -12,7 +11,7 @@ ; Function Attrs: norecurse nounwind readnone define signext i32 @test_iltss(i16 signext %a, i16 signext %b) { ; CHECK-LABEL: test_iltss: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: sub [[REG:r[0-9]+]], r3, r4 ; CHECK-NEXT: rldicl r3, [[REG]], 1, 63 ; CHECK-NEXT: blr @@ -25,7 +24,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define signext i32 @test_iltss_sext(i16 signext %a, i16 signext %b) { ; CHECK-LABEL: test_iltss_sext: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: sub [[REG:r[0-9]+]], r3, r4 ; CHECK-NEXT: sradi r3, [[REG]], 63 ; CHECK-NEXT: blr @@ -49,7 +48,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_iltss_store(i16 signext %a, i16 signext %b) { ; CHECK-LABEL: test_iltss_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK: sub [[REG:r[0-9]+]], r3, r4 ; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63 entry: @@ -62,7 +61,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_iltss_sext_store(i16 signext %a, i16 signext %b) { ; CHECK-LABEL: test_iltss_sext_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK: sub [[REG:r[0-9]+]], r3, r4 ; CHECK: sradi {{r[0-9]+}}, [[REG]], 63 entry: diff --git a/test/CodeGen/PowerPC/testComparesiltuc.ll b/test/CodeGen/PowerPC/testComparesiltuc.ll index ddfda95bc9760..19db29a50c99a 100644 --- a/test/CodeGen/PowerPC/testComparesiltuc.ll +++ b/test/CodeGen/PowerPC/testComparesiltuc.ll @@ -1,9 +1,8 @@ -; XFAIL: * ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl @glob = common local_unnamed_addr global i8 0, align 1 diff --git a/test/CodeGen/PowerPC/testComparesiltui.ll b/test/CodeGen/PowerPC/testComparesiltui.ll index ac61f977b28e7..dd9a202cbc998 100644 --- a/test/CodeGen/PowerPC/testComparesiltui.ll +++ b/test/CodeGen/PowerPC/testComparesiltui.ll @@ -1,9 +1,8 @@ -; XFAIL: * ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl @glob = common local_unnamed_addr global i32 0, align 4 diff --git a/test/CodeGen/PowerPC/testComparesiltus.ll b/test/CodeGen/PowerPC/testComparesiltus.ll index 349ec2696be65..1174572505983 100644 --- a/test/CodeGen/PowerPC/testComparesiltus.ll +++ b/test/CodeGen/PowerPC/testComparesiltus.ll @@ -1,9 +1,8 @@ -; XFAIL: * ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl @glob = common local_unnamed_addr global i16 0, align 2 diff --git a/test/CodeGen/PowerPC/testComparesinesc.ll b/test/CodeGen/PowerPC/testComparesinesc.ll index d67d7a5d5d038..a498f64462224 100644 --- a/test/CodeGen/PowerPC/testComparesinesc.ll +++ b/test/CodeGen/PowerPC/testComparesinesc.ll @@ -1,9 +1,8 @@ -; XFAIL: * ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py diff --git a/test/CodeGen/PowerPC/testComparesinesi.ll b/test/CodeGen/PowerPC/testComparesinesi.ll index dce15a4eb2a21..b47f6c808495e 100644 --- a/test/CodeGen/PowerPC/testComparesinesi.ll +++ b/test/CodeGen/PowerPC/testComparesinesi.ll @@ -1,9 +1,8 @@ -; XFAIL: * ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py diff --git a/test/CodeGen/PowerPC/testComparesinesll.ll b/test/CodeGen/PowerPC/testComparesinesll.ll index 2703690d297a0..cccff24c504ff 100644 --- a/test/CodeGen/PowerPC/testComparesinesll.ll +++ b/test/CodeGen/PowerPC/testComparesinesll.ll @@ -1,9 +1,8 @@ -; XFAIL: * ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py @@ -11,7 +10,7 @@ define signext i32 @test_inesll(i64 %a, i64 %b) { ; CHECK-LABEL: test_inesll: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: addic r4, r3, -1 ; CHECK-NEXT: subfe r3, r4, r3 @@ -24,7 +23,7 @@ entry: define signext i32 @test_inesll_sext(i64 %a, i64 %b) { ; CHECK-LABEL: test_inesll_sext: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: subfic r3, r3, 0 ; CHECK-NEXT: subfe r3, r3, r3 @@ -37,7 +36,7 @@ entry: define signext i32 @test_inesll_z(i64 %a) { ; CHECK-LABEL: test_inesll_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addic r4, r3, -1 ; CHECK-NEXT: subfe r3, r4, r3 ; CHECK-NEXT: blr @@ -49,7 +48,7 @@ entry: define signext i32 @test_inesll_sext_z(i64 %a) { ; CHECK-LABEL: test_inesll_sext_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: subfic r3, r3, 0 ; CHECK-NEXT: subfe r3, r3, r3 ; CHECK-NEXT: blr @@ -61,7 +60,7 @@ entry: define void @test_inesll_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_inesll_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5) @@ -78,7 +77,7 @@ entry: define void @test_inesll_sext_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_inesll_sext_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5) @@ -95,7 +94,7 @@ entry: define void @test_inesll_z_store(i64 %a) { ; CHECK-LABEL: test_inesll_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: addic r5, r3, -1 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) @@ -111,7 +110,7 @@ entry: define void @test_inesll_sext_z_store(i64 %a) { ; CHECK-LABEL: test_inesll_sext_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: subfic r3, r3, 0 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) diff --git a/test/CodeGen/PowerPC/testComparesiness.ll b/test/CodeGen/PowerPC/testComparesiness.ll index 47f99816bfee8..66c95cd0d91d0 100644 --- a/test/CodeGen/PowerPC/testComparesiness.ll +++ b/test/CodeGen/PowerPC/testComparesiness.ll @@ -1,9 +1,8 @@ -; XFAIL: * ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py diff --git a/test/CodeGen/PowerPC/testComparesineuc.ll b/test/CodeGen/PowerPC/testComparesineuc.ll index dfe3fff477a81..c478041b19e0e 100644 --- a/test/CodeGen/PowerPC/testComparesineuc.ll +++ b/test/CodeGen/PowerPC/testComparesineuc.ll @@ -1,16 +1,15 @@ -; XFAIL: * ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py @glob = common local_unnamed_addr global i8 0, align 1 define signext i32 @test_ineuc(i8 zeroext %a, i8 zeroext %b) { ; CHECK-LABEL: test_ineuc: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 @@ -24,7 +23,7 @@ entry: define signext i32 @test_ineuc_sext(i8 zeroext %a, i8 zeroext %b) { ; CHECK-LABEL: test_ineuc_sext: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 @@ -39,7 +38,7 @@ entry: define signext i32 @test_ineuc_z(i8 zeroext %a) { ; CHECK-LABEL: test_ineuc_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: xori r3, r3, 1 @@ -52,7 +51,7 @@ entry: define signext i32 @test_ineuc_sext_z(i8 zeroext %a) { ; CHECK-LABEL: test_ineuc_sext_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: xori r3, r3, 1 @@ -66,7 +65,7 @@ entry: define void @test_ineuc_store(i8 zeroext %a, i8 zeroext %b) { ; CHECK-LABEL: test_ineuc_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 @@ -84,7 +83,7 @@ entry: define void @test_ineuc_sext_store(i8 zeroext %a, i8 zeroext %b) { ; CHECK-LABEL: test_ineuc_sext_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 @@ -103,7 +102,7 @@ entry: define void @test_ineuc_z_store(i8 zeroext %a) { ; CHECK-LABEL: test_ineuc_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) @@ -120,7 +119,7 @@ entry: define void @test_ineuc_sext_z_store(i8 zeroext %a) { ; CHECK-LABEL: test_ineuc_sext_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 diff --git a/test/CodeGen/PowerPC/testComparesineui.ll b/test/CodeGen/PowerPC/testComparesineui.ll index 44f661c3a80d6..ef126270f418b 100644 --- a/test/CodeGen/PowerPC/testComparesineui.ll +++ b/test/CodeGen/PowerPC/testComparesineui.ll @@ -1,9 +1,8 @@ -; XFAIL: * ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py diff --git a/test/CodeGen/PowerPC/testComparesineull.ll b/test/CodeGen/PowerPC/testComparesineull.ll index 00231b5792ef6..ba388a45fadde 100644 --- a/test/CodeGen/PowerPC/testComparesineull.ll +++ b/test/CodeGen/PowerPC/testComparesineull.ll @@ -1,9 +1,8 @@ -; XFAIL: * ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py @@ -11,7 +10,7 @@ define signext i32 @test_ineull(i64 %a, i64 %b) { ; CHECK-LABEL: test_ineull: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: addic r4, r3, -1 ; CHECK-NEXT: subfe r3, r4, r3 @@ -24,7 +23,7 @@ entry: define signext i32 @test_ineull_sext(i64 %a, i64 %b) { ; CHECK-LABEL: test_ineull_sext: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: subfic r3, r3, 0 ; CHECK-NEXT: subfe r3, r3, r3 @@ -37,7 +36,7 @@ entry: define signext i32 @test_ineull_z(i64 %a) { ; CHECK-LABEL: test_ineull_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addic r4, r3, -1 ; CHECK-NEXT: subfe r3, r4, r3 ; CHECK-NEXT: blr @@ -49,7 +48,7 @@ entry: define signext i32 @test_ineull_sext_z(i64 %a) { ; CHECK-LABEL: test_ineull_sext_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: subfic r3, r3, 0 ; CHECK-NEXT: subfe r3, r3, r3 ; CHECK-NEXT: blr @@ -61,7 +60,7 @@ entry: define void @test_ineull_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_ineull_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5) @@ -78,7 +77,7 @@ entry: define void @test_ineull_sext_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_ineull_sext_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5) @@ -95,7 +94,7 @@ entry: define void @test_ineull_z_store(i64 %a) { ; CHECK-LABEL: test_ineull_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: addic r5, r3, -1 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) @@ -111,7 +110,7 @@ entry: define void @test_ineull_sext_z_store(i64 %a) { ; CHECK-LABEL: test_ineull_sext_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: subfic r3, r3, 0 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) diff --git a/test/CodeGen/PowerPC/testComparesineus.ll b/test/CodeGen/PowerPC/testComparesineus.ll index 32dfed54d923a..a78671b640758 100644 --- a/test/CodeGen/PowerPC/testComparesineus.ll +++ b/test/CodeGen/PowerPC/testComparesineus.ll @@ -1,9 +1,8 @@ -; XFAIL: * ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py @@ -11,7 +10,7 @@ define signext i32 @test_ineus(i16 zeroext %a, i16 zeroext %b) { ; CHECK-LABEL: test_ineus: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 @@ -25,7 +24,7 @@ entry: define signext i32 @test_ineus_sext(i16 zeroext %a, i16 zeroext %b) { ; CHECK-LABEL: test_ineus_sext: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 @@ -40,7 +39,7 @@ entry: define signext i32 @test_ineus_z(i16 zeroext %a) { ; CHECK-LABEL: test_ineus_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: xori r3, r3, 1 @@ -53,7 +52,7 @@ entry: define signext i32 @test_ineus_sext_z(i16 zeroext %a) { ; CHECK-LABEL: test_ineus_sext_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: xori r3, r3, 1 @@ -67,7 +66,7 @@ entry: define void @test_ineus_store(i16 zeroext %a, i16 zeroext %b) { ; CHECK-LABEL: test_ineus_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 @@ -85,7 +84,7 @@ entry: define void @test_ineus_sext_store(i16 zeroext %a, i16 zeroext %b) { ; CHECK-LABEL: test_ineus_sext_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 @@ -104,7 +103,7 @@ entry: define void @test_ineus_z_store(i16 zeroext %a) { ; CHECK-LABEL: test_ineus_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) @@ -121,7 +120,7 @@ entry: define void @test_ineus_sext_z_store(i16 zeroext %a) { ; CHECK-LABEL: test_ineus_sext_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 diff --git a/test/CodeGen/PowerPC/testCompareslleqsc.ll b/test/CodeGen/PowerPC/testCompareslleqsc.ll index 7042f6c32893e..43fb358efef65 100644 --- a/test/CodeGen/PowerPC/testCompareslleqsc.ll +++ b/test/CodeGen/PowerPC/testCompareslleqsc.ll @@ -1,10 +1,9 @@ -; XFAIL: * ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; ModuleID = 'ComparisonTestCases/testCompareslleqsc.c' @@ -13,7 +12,7 @@ ; Function Attrs: norecurse nounwind readnone define i64 @test_lleqsc(i8 signext %a, i8 signext %b) { ; CHECK-LABEL: test_lleqsc: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 @@ -27,7 +26,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define i64 @test_lleqsc_sext(i8 signext %a, i8 signext %b) { ; CHECK-LABEL: test_lleqsc_sext: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 @@ -42,7 +41,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define i64 @test_lleqsc_z(i8 signext %a) { ; CHECK-LABEL: test_lleqsc_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: blr @@ -55,7 +54,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define i64 @test_lleqsc_sext_z(i8 signext %a) { ; CHECK-LABEL: test_lleqsc_sext_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 @@ -69,7 +68,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_lleqsc_store(i8 signext %a, i8 signext %b) { ; CHECK-LABEL: test_lleqsc_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5) @@ -87,7 +86,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_lleqsc_sext_store(i8 signext %a, i8 signext %b) { ; CHECK-LABEL: test_lleqsc_sext_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 @@ -106,7 +105,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_lleqsc_z_store(i8 signext %a) { ; CHECK-LABEL: test_lleqsc_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) @@ -123,7 +122,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_lleqsc_sext_z_store(i8 signext %a) { ; CHECK-LABEL: test_lleqsc_sext_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) diff --git a/test/CodeGen/PowerPC/testCompareslleqsi.ll b/test/CodeGen/PowerPC/testCompareslleqsi.ll index 9c59c263b327f..ae8dffb1e2215 100644 --- a/test/CodeGen/PowerPC/testCompareslleqsi.ll +++ b/test/CodeGen/PowerPC/testCompareslleqsi.ll @@ -1,10 +1,9 @@ -; XFAIL: * ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl @glob = common local_unnamed_addr global i32 0, align 4 @@ -12,7 +11,7 @@ ; Function Attrs: norecurse nounwind readnone define i64 @test_lleqsi(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: test_lleqsi: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 @@ -26,7 +25,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define i64 @test_lleqsi_sext(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: test_lleqsi_sext: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 @@ -41,7 +40,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define i64 @test_lleqsi_z(i32 signext %a) { ; CHECK-LABEL: test_lleqsi_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: blr @@ -54,7 +53,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define i64 @test_lleqsi_sext_z(i32 signext %a) { ; CHECK-LABEL: test_lleqsi_sext_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 @@ -68,7 +67,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_lleqsi_store(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: test_lleqsi_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5) @@ -86,7 +85,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_lleqsi_sext_store(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: test_lleqsi_sext_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 @@ -105,7 +104,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_lleqsi_z_store(i32 signext %a) { ; CHECK-LABEL: test_lleqsi_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) @@ -123,7 +122,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_lleqsi_sext_z_store(i32 signext %a) { ; CHECK-LABEL: test_lleqsi_sext_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) diff --git a/test/CodeGen/PowerPC/testCompareslleqsll.ll b/test/CodeGen/PowerPC/testCompareslleqsll.ll index 226dd1e33dd53..89ef960a6f9ec 100644 --- a/test/CodeGen/PowerPC/testCompareslleqsll.ll +++ b/test/CodeGen/PowerPC/testCompareslleqsll.ll @@ -1,10 +1,9 @@ -; XFAIL: * ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl @glob = common local_unnamed_addr global i64 0, align 8 @@ -12,7 +11,7 @@ ; Function Attrs: norecurse nounwind readnone define i64 @test_lleqsll(i64 %a, i64 %b) { ; CHECK-LABEL: test_lleqsll: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzd r3, r3 ; CHECK-NEXT: rldicl r3, r3, 58, 63 @@ -26,7 +25,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define i64 @test_lleqsll_sext(i64 %a, i64 %b) { ; CHECK-LABEL: test_lleqsll_sext: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: addic r3, r3, -1 ; CHECK-NEXT: subfe r3, r3, r3 @@ -40,7 +39,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define i64 @test_lleqsll_z(i64 %a) { ; CHECK-LABEL: test_lleqsll_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cntlzd r3, r3 ; CHECK-NEXT: rldicl r3, r3, 58, 63 ; CHECK-NEXT: blr @@ -53,7 +52,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define i64 @test_lleqsll_sext_z(i64 %a) { ; CHECK-LABEL: test_lleqsll_sext_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addic r3, r3, -1 ; CHECK-NEXT: subfe r3, r3, r3 ; CHECK-NEXT: blr @@ -66,7 +65,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_lleqsll_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_lleqsll_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5) @@ -84,7 +83,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_lleqsll_sext_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_lleqsll_sext_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5) @@ -102,7 +101,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_lleqsll_z_store(i64 %a) { ; CHECK-LABEL: test_lleqsll_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzd r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) @@ -119,7 +118,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_lleqsll_sext_z_store(i64 %a) { ; CHECK-LABEL: test_lleqsll_sext_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: addic r3, r3, -1 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) diff --git a/test/CodeGen/PowerPC/testCompareslleqss.ll b/test/CodeGen/PowerPC/testCompareslleqss.ll index 19f18c0b6a91d..5d1945d73e309 100644 --- a/test/CodeGen/PowerPC/testCompareslleqss.ll +++ b/test/CodeGen/PowerPC/testCompareslleqss.ll @@ -1,10 +1,9 @@ -; XFAIL: * ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl @glob = common local_unnamed_addr global i16 0, align 2 @@ -12,7 +11,7 @@ ; Function Attrs: norecurse nounwind readnone define i64 @test_lleqss(i16 signext %a, i16 signext %b) { ; CHECK-LABEL: test_lleqss: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 @@ -26,7 +25,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define i64 @test_lleqss_sext(i16 signext %a, i16 signext %b) { ; CHECK-LABEL: test_lleqss_sext: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 @@ -41,7 +40,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define i64 @test_lleqss_z(i16 signext %a) { ; CHECK-LABEL: test_lleqss_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: blr @@ -54,7 +53,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define i64 @test_lleqss_sext_z(i16 signext %a) { ; CHECK-LABEL: test_lleqss_sext_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 @@ -68,7 +67,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_lleqss_store(i16 signext %a, i16 signext %b) { ; CHECK-LABEL: test_lleqss_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5) @@ -86,7 +85,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_lleqss_sext_store(i16 signext %a, i16 signext %b) { ; CHECK-LABEL: test_lleqss_sext_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 @@ -105,7 +104,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_lleqss_z_store(i16 signext %a) { ; CHECK-LABEL: test_lleqss_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) @@ -122,7 +121,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_lleqss_sext_z_store(i16 signext %a) { ; CHECK-LABEL: test_lleqss_sext_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) diff --git a/test/CodeGen/PowerPC/testComparesllequc.ll b/test/CodeGen/PowerPC/testComparesllequc.ll index af130bacfd156..0f5d4c6f2879a 100644 --- a/test/CodeGen/PowerPC/testComparesllequc.ll +++ b/test/CodeGen/PowerPC/testComparesllequc.ll @@ -1,10 +1,9 @@ -; XFAIL: * ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl @glob = common local_unnamed_addr global i8 0, align 1 @@ -12,7 +11,7 @@ ; Function Attrs: norecurse nounwind readnone define i64 @test_llequc(i8 zeroext %a, i8 zeroext %b) { ; CHECK-LABEL: test_llequc: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 @@ -26,7 +25,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define i64 @test_llequc_sext(i8 zeroext %a, i8 zeroext %b) { ; CHECK-LABEL: test_llequc_sext: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 @@ -41,7 +40,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define i64 @test_llequc_z(i8 zeroext %a) { ; CHECK-LABEL: test_llequc_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: blr @@ -54,7 +53,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define i64 @test_llequc_sext_z(i8 zeroext %a) { ; CHECK-LABEL: test_llequc_sext_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 @@ -68,7 +67,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_llequc_store(i8 zeroext %a, i8 zeroext %b) { ; CHECK-LABEL: test_llequc_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5) @@ -86,7 +85,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_llequc_sext_store(i8 zeroext %a, i8 zeroext %b) { ; CHECK-LABEL: test_llequc_sext_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 @@ -105,7 +104,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_llequc_z_store(i8 zeroext %a) { ; CHECK-LABEL: test_llequc_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) @@ -122,7 +121,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_llequc_sext_z_store(i8 zeroext %a) { ; CHECK-LABEL: test_llequc_sext_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) diff --git a/test/CodeGen/PowerPC/testComparesllequi.ll b/test/CodeGen/PowerPC/testComparesllequi.ll index 14ce4973013b5..350168e0e6ccc 100644 --- a/test/CodeGen/PowerPC/testComparesllequi.ll +++ b/test/CodeGen/PowerPC/testComparesllequi.ll @@ -1,10 +1,9 @@ -; XFAIL: * ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl @glob = common local_unnamed_addr global i32 0, align 4 @@ -12,7 +11,7 @@ ; Function Attrs: norecurse nounwind readnone define i64 @test_llequi(i32 zeroext %a, i32 zeroext %b) { ; CHECK-LABEL: test_llequi: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 @@ -26,7 +25,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define i64 @test_llequi_sext(i32 zeroext %a, i32 zeroext %b) { ; CHECK-LABEL: test_llequi_sext: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 @@ -41,7 +40,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define i64 @test_llequi_z(i32 zeroext %a) { ; CHECK-LABEL: test_llequi_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: blr @@ -54,7 +53,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define i64 @test_llequi_sext_z(i32 zeroext %a) { ; CHECK-LABEL: test_llequi_sext_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 @@ -68,7 +67,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_llequi_store(i32 zeroext %a, i32 zeroext %b) { ; CHECK-LABEL: test_llequi_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5) @@ -86,7 +85,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_llequi_sext_store(i32 zeroext %a, i32 zeroext %b) { ; CHECK-LABEL: test_llequi_sext_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 @@ -105,7 +104,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_llequi_z_store(i32 zeroext %a) { ; CHECK-LABEL: test_llequi_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) @@ -122,7 +121,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_llequi_sext_z_store(i32 zeroext %a) { ; CHECK-LABEL: test_llequi_sext_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) diff --git a/test/CodeGen/PowerPC/testComparesllequll.ll b/test/CodeGen/PowerPC/testComparesllequll.ll index 91032b76fb4e8..7d1fe527e8a54 100644 --- a/test/CodeGen/PowerPC/testComparesllequll.ll +++ b/test/CodeGen/PowerPC/testComparesllequll.ll @@ -1,10 +1,9 @@ -; XFAIL: * ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl @glob = common local_unnamed_addr global i64 0, align 8 @@ -12,7 +11,7 @@ ; Function Attrs: norecurse nounwind readnone define i64 @test_llequll(i64 %a, i64 %b) { ; CHECK-LABEL: test_llequll: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzd r3, r3 ; CHECK-NEXT: rldicl r3, r3, 58, 63 @@ -26,7 +25,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define i64 @test_llequll_sext(i64 %a, i64 %b) { ; CHECK-LABEL: test_llequll_sext: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: addic r3, r3, -1 ; CHECK-NEXT: subfe r3, r3, r3 @@ -40,7 +39,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define i64 @test_llequll_z(i64 %a) { ; CHECK-LABEL: test_llequll_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cntlzd r3, r3 ; CHECK-NEXT: rldicl r3, r3, 58, 63 ; CHECK-NEXT: blr @@ -53,7 +52,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define i64 @test_llequll_sext_z(i64 %a) { ; CHECK-LABEL: test_llequll_sext_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addic r3, r3, -1 ; CHECK-NEXT: subfe r3, r3, r3 ; CHECK-NEXT: blr @@ -66,7 +65,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_llequll_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_llequll_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5) @@ -84,7 +83,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_llequll_sext_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_llequll_sext_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5) @@ -102,7 +101,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_llequll_z_store(i64 %a) { ; CHECK-LABEL: test_llequll_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzd r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) @@ -119,7 +118,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_llequll_sext_z_store(i64 %a) { ; CHECK-LABEL: test_llequll_sext_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: addic r3, r3, -1 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) diff --git a/test/CodeGen/PowerPC/testComparesllequs.ll b/test/CodeGen/PowerPC/testComparesllequs.ll index 9edadd4a03625..cc215216dfc42 100644 --- a/test/CodeGen/PowerPC/testComparesllequs.ll +++ b/test/CodeGen/PowerPC/testComparesllequs.ll @@ -1,10 +1,9 @@ -; XFAIL: * ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl @glob = common local_unnamed_addr global i16 0, align 2 @@ -12,7 +11,7 @@ ; Function Attrs: norecurse nounwind readnone define i64 @test_llequs(i16 zeroext %a, i16 zeroext %b) { ; CHECK-LABEL: test_llequs: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 @@ -26,7 +25,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define i64 @test_llequs_sext(i16 zeroext %a, i16 zeroext %b) { ; CHECK-LABEL: test_llequs_sext: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 @@ -41,7 +40,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define i64 @test_llequs_z(i16 zeroext %a) { ; CHECK-LABEL: test_llequs_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: blr @@ -54,7 +53,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define i64 @test_llequs_sext_z(i16 zeroext %a) { ; CHECK-LABEL: test_llequs_sext_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: neg r3, r3 @@ -68,7 +67,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_llequs_store(i16 zeroext %a, i16 zeroext %b) { ; CHECK-LABEL: test_llequs_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5) @@ -86,7 +85,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_llequs_sext_store(i16 zeroext %a, i16 zeroext %b) { ; CHECK-LABEL: test_llequs_sext_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 @@ -105,7 +104,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_llequs_z_store(i16 zeroext %a) { ; CHECK-LABEL: test_llequs_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) @@ -122,7 +121,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_llequs_sext_z_store(i16 zeroext %a) { ; CHECK-LABEL: test_llequs_sext_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) diff --git a/test/CodeGen/PowerPC/testComparesllgesc.ll b/test/CodeGen/PowerPC/testComparesllgesc.ll index a0335e4af4fe1..82f54cd6b1b91 100644 --- a/test/CodeGen/PowerPC/testComparesllgesc.ll +++ b/test/CodeGen/PowerPC/testComparesllgesc.ll @@ -1,16 +1,15 @@ -; XFAIL: * ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ -; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ -; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py @glob = common local_unnamed_addr global i8 0, align 1 define i64 @test_llgesc(i8 signext %a, i8 signext %b) { ; CHECK-LABEL: test_llgesc: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: xori r3, r3, 1 @@ -23,7 +22,7 @@ entry: define i64 @test_llgesc_sext(i8 signext %a, i8 signext %b) { ; CHECK-LABEL: test_llgesc_sext: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: addi r3, r3, -1 @@ -36,7 +35,7 @@ entry: define void @test_llgesc_store(i8 signext %a, i8 signext %b) { ; CHECK-LABEL: test_llgesc_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5) @@ -53,7 +52,7 @@ entry: define void @test_llgesc_sext_store(i8 signext %a, i8 signext %b) { ; CHECK-LABEL: test_llgesc_sext_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5) diff --git a/test/CodeGen/PowerPC/testComparesllgesi.ll b/test/CodeGen/PowerPC/testComparesllgesi.ll index e9b9079d9a64f..82c1fa11b8b64 100644 --- a/test/CodeGen/PowerPC/testComparesllgesi.ll +++ b/test/CodeGen/PowerPC/testComparesllgesi.ll @@ -1,16 +1,15 @@ -; XFAIL: * ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py @glob = common local_unnamed_addr global i32 0, align 4 define i64 @test_llgesi(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: test_llgesi: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: xori r3, r3, 1 @@ -23,7 +22,7 @@ entry: define i64 @test_llgesi_sext(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: test_llgesi_sext: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: addi r3, r3, -1 @@ -36,7 +35,7 @@ entry: define void @test_llgesi_store(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: test_llgesi_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5) @@ -53,7 +52,7 @@ entry: define void @test_llgesi_sext_store(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: test_llgesi_sext_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5) diff --git a/test/CodeGen/PowerPC/testComparesllgesll.ll b/test/CodeGen/PowerPC/testComparesllgesll.ll index b875816733581..6fb53977a55a1 100644 --- a/test/CodeGen/PowerPC/testComparesllgesll.ll +++ b/test/CodeGen/PowerPC/testComparesllgesll.ll @@ -1,16 +1,15 @@ -; XFAIL: * ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py @glob = common local_unnamed_addr global i64 0, align 8 define i64 @test_llgesll(i64 %a, i64 %b) { ; CHECK-LABEL: test_llgesll: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: sradi r5, r3, 63 ; CHECK-NEXT: rldicl r6, r4, 1, 63 ; CHECK-NEXT: subfc r3, r4, r3 @@ -24,7 +23,7 @@ entry: define i64 @test_llgesll_sext(i64 %a, i64 %b) { ; CHECK-LABEL: test_llgesll_sext: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: sradi r5, r3, 63 ; CHECK-NEXT: rldicl r6, r4, 1, 63 ; CHECK-NEXT: subfc r3, r4, r3 @@ -39,7 +38,7 @@ entry: define i64 @test_llgesll_z(i64 %a) { ; CHECK-LABEL: test_llgesll_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: blr @@ -51,7 +50,7 @@ entry: define i64 @test_llgesll_sext_z(i64 %a) { ; CHECK-LABEL: test_llgesll_sext_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: sradi r3, r3, 63 ; CHECK-NEXT: not r3, r3 ; CHECK-NEXT: blr @@ -63,7 +62,7 @@ entry: define void @test_llgesll_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_llgesll_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK: sradi r6, r3, 63 ; CHECK: subfc r3, r4, r3 ; CHECK: rldicl r3, r4, 1, 63 @@ -79,7 +78,7 @@ entry: define void @test_llgesll_sext_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_llgesll_sext_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: sradi r6, r3, 63 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: subfc r3, r4, r3 @@ -98,7 +97,7 @@ entry: define void @test_llgesll_z_store(i64 %a) { ; CHECK-LABEL: test_llgesll_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) @@ -114,7 +113,7 @@ entry: define void @test_llgesll_sext_z_store(i64 %a) { ; CHECK-LABEL: test_llgesll_sext_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: sradi r3, r3, 63 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) diff --git a/test/CodeGen/PowerPC/testComparesllgess.ll b/test/CodeGen/PowerPC/testComparesllgess.ll index 0bf9d14bf0579..1206339a23b77 100644 --- a/test/CodeGen/PowerPC/testComparesllgess.ll +++ b/test/CodeGen/PowerPC/testComparesllgess.ll @@ -1,16 +1,15 @@ -; XFAIL: * ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ -; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ -; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py @glob = common local_unnamed_addr global i16 0, align 2 define i64 @test_llgess(i16 signext %a, i16 signext %b) { ; CHECK-LABEL: test_llgess: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: xori r3, r3, 1 @@ -23,7 +22,7 @@ entry: define i64 @test_llgess_sext(i16 signext %a, i16 signext %b) { ; CHECK-LABEL: test_llgess_sext: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: addi r3, r3, -1 @@ -36,7 +35,7 @@ entry: define void @test_llgess_store(i16 signext %a, i16 signext %b) { ; CHECK-LABEL: test_llgess_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5) @@ -53,7 +52,7 @@ entry: define void @test_llgess_sext_store(i16 signext %a, i16 signext %b) { ; CHECK-LABEL: test_llgess_sext_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5) diff --git a/test/CodeGen/PowerPC/testComparesllgeuc.ll b/test/CodeGen/PowerPC/testComparesllgeuc.ll index 071185d4f3987..6369cdc23d9f8 100644 --- a/test/CodeGen/PowerPC/testComparesllgeuc.ll +++ b/test/CodeGen/PowerPC/testComparesllgeuc.ll @@ -1,9 +1,8 @@ -; XFAIL: * ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl @glob = common local_unnamed_addr global i8 0, align 1 diff --git a/test/CodeGen/PowerPC/testComparesllgeui.ll b/test/CodeGen/PowerPC/testComparesllgeui.ll index 26858b5ca0c90..856d3a0f3cc43 100644 --- a/test/CodeGen/PowerPC/testComparesllgeui.ll +++ b/test/CodeGen/PowerPC/testComparesllgeui.ll @@ -1,9 +1,8 @@ -; XFAIL: * ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl @glob = common local_unnamed_addr global i32 0, align 4 @@ -106,8 +105,10 @@ entry: store i32 %sub, i32* @glob ret void ; CHECK-LABEL: @test_llgeui_sext_z_store -; CHECK: li [[REG1:r[0-9]+]], -1 -; CHECK: stw [[REG1]] -; CHECK: blr +; CHECK: li [[REG1:r[0-9]+]], 0 +; CHECK: oris [[REG2:r[0-9]+]], [[REG1]], 65535 +; CHECK: ori [[REG3:r[0-9]+]], [[REG2]], 65535 +; CHECK: stw [[REG3]] +; CHECK: blr } diff --git a/test/CodeGen/PowerPC/testComparesllgeull.ll b/test/CodeGen/PowerPC/testComparesllgeull.ll new file mode 100644 index 0000000000000..be1db4f754018 --- /dev/null +++ b/test/CodeGen/PowerPC/testComparesllgeull.ll @@ -0,0 +1,110 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl + +@glob = common local_unnamed_addr global i64 0, align 8 + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llgeull(i64 %a, i64 %b) { +entry: + %cmp = icmp uge i64 %a, %b + %conv1 = zext i1 %cmp to i64 + ret i64 %conv1 +; CHECK-LABEL: test_llgeull: +; CHECK: subfc {{r[0-9]+}}, r4, r3 +; CHECK-NEXT: subfe [[REG1:r[0-9]+]], r4, r4 +; CHECK-NEXT: addi r3, [[REG1]], 1 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llgeull_sext(i64 %a, i64 %b) { +entry: + %cmp = icmp uge i64 %a, %b + %conv1 = sext i1 %cmp to i64 + ret i64 %conv1 +; CHECK-LABEL: @test_llgeull_sext +; CHECK: subfc [[REG1:r[0-9]+]], r4, r3 +; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}} +; CHECK: not [[REG3:r[0-9]+]], [[REG2]] +; CHECK: blr +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llgeull_z(i64 %a) { +entry: + %cmp = icmp uge i64 %a, 0 + %conv1 = zext i1 %cmp to i64 + ret i64 %conv1 +; CHECK-LABEL: @test_llgeull_z +; CHECK: li r3, 1 +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llgeull_sext_z(i64 %a) { +entry: + %cmp = icmp uge i64 %a, 0 + %conv1 = sext i1 %cmp to i64 + ret i64 %conv1 +; CHECK-LABEL: @test_llgeull_sext_z +; CHECK: li r3, -1 +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind +define void @test_llgeull_store(i64 %a, i64 %b) { +entry: + %cmp = icmp uge i64 %a, %b + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob + ret void +; CHECK-LABEL: test_llgeull_store: +; CHECK: subfc {{r[0-9]+}}, r4, r3 +; CHECK: subfe [[REG1:r[0-9]+]], r4, r4 +; CHECK: addi {{r[0-9]+}}, [[REG1]], 1 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_llgeull_sext_store(i64 %a, i64 %b) { +entry: + %cmp = icmp uge i64 %a, %b + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob + ret void +; CHECK-LABEL: @test_llgeull_sext_store +; CHECK: subfc [[REG1:r[0-9]+]], r4, r3 +; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}} +; CHECK: not [[REG3:r[0-9]+]], [[REG2]] +; CHECK: std [[REG3]] +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_llgeull_z_store(i64 %a) { +entry: + %cmp = icmp uge i64 %a, 0 + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob + ret void +; CHECK-LABEL: @test_llgeull_z_store +; CHECK: li [[REG1:r[0-9]+]], 1 +; CHECK: std [[REG1]] +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_llgeull_sext_z_store(i64 %a) { +entry: + store i64 -1, i64* @glob + ret void +; CHECK-LABEL: @test_llgeull_sext_z_store +; CHECK: li [[REG1:r[0-9]+]], -1 +; CHECK: std [[REG1]] +; CHECK: blr +} + diff --git a/test/CodeGen/PowerPC/testComparesllgeus.ll b/test/CodeGen/PowerPC/testComparesllgeus.ll index 8148dcea878fe..a458715a7e6d4 100644 --- a/test/CodeGen/PowerPC/testComparesllgeus.ll +++ b/test/CodeGen/PowerPC/testComparesllgeus.ll @@ -1,9 +1,8 @@ -; XFAIL: * ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl @glob = common local_unnamed_addr global i16 0, align 2 @@ -106,7 +105,7 @@ entry: store i16 %conv1, i16* @glob ret void ; CHECK-LABEL: @test_llgeus_sext_z_store -; CHECK: lis [[REG1:r[0-9]+]], 0 +; CHECK: li [[REG1:r[0-9]+]], 0 ; CHECK: ori [[REG2:r[0-9]+]], [[REG1]], 65535 ; CHECK: sth [[REG2]] ; CHECK: blr diff --git a/test/CodeGen/PowerPC/testComparesllgtsll.ll b/test/CodeGen/PowerPC/testComparesllgtsll.ll index e64975deed833..0dc1374374f79 100644 --- a/test/CodeGen/PowerPC/testComparesllgtsll.ll +++ b/test/CodeGen/PowerPC/testComparesllgtsll.ll @@ -1,9 +1,8 @@ -; XFAIL: * ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl @glob = common local_unnamed_addr global i64 0, align 8 @@ -11,7 +10,7 @@ ; Function Attrs: norecurse nounwind readnone define i64 @test_llgtsll(i64 %a, i64 %b) { ; CHECK-LABEL: test_llgtsll: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: sradi [[REG1:r[0-9]+]], r4, 63 ; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], r3, 1, 63 ; CHECK-NEXT: subfc [[REG3:r[0-9]+]], r3, r4 @@ -27,7 +26,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define i64 @test_llgtsll_sext(i64 %a, i64 %b) { ; CHECK-LABEL: test_llgtsll_sext: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: sradi [[REG1:r[0-9]+]], r4, 63 ; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], r3, 1, 63 ; CHECK-NEXT: subfc [[REG3:r[0-9]+]], r3, r4 @@ -45,7 +44,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define i64 @test_llgtsll_z(i64 %a) { ; CHECK-LABEL: test_llgtsll_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addi r4, r3, -1 ; CHECK-NEXT: nor r3, r4, r3 ; CHECK-NEXT: rldicl r3, r3, 1, 63 @@ -71,7 +70,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_llgtsll_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_llgtsll_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK: sradi [[REG1:r[0-9]+]], r4, 63 ; CHECK: rldicl [[REG2:r[0-9]+]], r3, 1, 63 ; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r3, r4 @@ -88,7 +87,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_llgtsll_sext_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_llgtsll_sext_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK: sradi [[REG1:r[0-9]+]], r4, 63 ; CHECK: rldicl [[REG2:r[0-9]+]], r3, 1, 63 ; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r3, r4 @@ -106,7 +105,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_llgtsll_z_store(i64 %a) { ; CHECK-LABEL: test_llgtsll_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: addi r5, r3, -1 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) diff --git a/test/CodeGen/PowerPC/testComparesllgtuc.ll b/test/CodeGen/PowerPC/testComparesllgtuc.ll index ba2a3980dbbd9..ba70713d61e58 100644 --- a/test/CodeGen/PowerPC/testComparesllgtuc.ll +++ b/test/CodeGen/PowerPC/testComparesllgtuc.ll @@ -1,9 +1,8 @@ -; XFAIL: * ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl @glob = common local_unnamed_addr global i8 0, align 1 diff --git a/test/CodeGen/PowerPC/testComparesllgtui.ll b/test/CodeGen/PowerPC/testComparesllgtui.ll index 681aa4bb677fa..d07e85972f2dc 100644 --- a/test/CodeGen/PowerPC/testComparesllgtui.ll +++ b/test/CodeGen/PowerPC/testComparesllgtui.ll @@ -1,9 +1,8 @@ -; XFAIL: * ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl @glob = common local_unnamed_addr global i32 0, align 4 diff --git a/test/CodeGen/PowerPC/testComparesllgtus.ll b/test/CodeGen/PowerPC/testComparesllgtus.ll index c3c2daa67ebb4..3758e8e097cee 100644 --- a/test/CodeGen/PowerPC/testComparesllgtus.ll +++ b/test/CodeGen/PowerPC/testComparesllgtus.ll @@ -1,9 +1,8 @@ -; XFAIL: * ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl @glob = common local_unnamed_addr global i16 0, align 2 @@ -11,7 +10,7 @@ ; Function Attrs: norecurse nounwind readnone define i64 @test_llgtus(i16 zeroext %a, i16 zeroext %b) { ; CHECK-LABEL: test_llgtus: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: sub [[REG:r[0-9]+]], r4, r3 ; CHECK-NEXT: rldicl r3, [[REG]], 1, 63 ; CHECK-NEXT: blr @@ -24,7 +23,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define i64 @test_llgtus_sext(i16 zeroext %a, i16 zeroext %b) { ; CHECK-LABEL: test_llgtus_sext: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: sub [[REG:r[0-9]+]], r4, r3 ; CHECK-NEXT: sradi r3, [[REG]], 63 ; CHECK-NEXT: blr @@ -37,7 +36,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define i64 @test_llgtus_z(i16 zeroext %a) { ; CHECK-LABEL: test_llgtus_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: xori r3, r3, 1 @@ -51,7 +50,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define i64 @test_llgtus_sext_z(i16 zeroext %a) { ; CHECK-LABEL: test_llgtus_sext_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: xori r3, r3, 1 @@ -66,7 +65,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_llgtus_store(i16 zeroext %a, i16 zeroext %b) { ; CHECK-LABEL: test_llgtus_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK: sub [[REG:r[0-9]+]], r4, r3 ; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63 entry: @@ -79,7 +78,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_llgtus_sext_store(i16 zeroext %a, i16 zeroext %b) { ; CHECK-LABEL: test_llgtus_sext_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK: sub [[REG:r[0-9]+]], r4, r3 ; CHECK: sradi {{r[0-9]+}}, [[REG]], 63 entry: @@ -92,7 +91,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_llgtus_z_store(i16 zeroext %a) { ; CHECK-LABEL: test_llgtus_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) @@ -110,7 +109,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_llgtus_sext_z_store(i16 zeroext %a) { ; CHECK-LABEL: test_llgtus_sext_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: srwi r3, r3, 5 diff --git a/test/CodeGen/PowerPC/testCompareslllesc.ll b/test/CodeGen/PowerPC/testCompareslllesc.ll index 7021662e14540..f9352990f2c44 100644 --- a/test/CodeGen/PowerPC/testCompareslllesc.ll +++ b/test/CodeGen/PowerPC/testCompareslllesc.ll @@ -1,17 +1,16 @@ -; XFAIL: * ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ -; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ -; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py @glob = common local_unnamed_addr global i8 0, align 1 define i64 @test_lllesc(i8 signext %a, i8 signext %b) { ; CHECK-LABEL: test_lllesc: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: xori r3, r3, 1 @@ -24,7 +23,7 @@ entry: define i64 @test_lllesc_sext(i8 signext %a, i8 signext %b) { ; CHECK-LABEL: test_lllesc_sext: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: addi r3, r3, -1 @@ -37,7 +36,7 @@ entry: define void @test_lllesc_store(i8 signext %a, i8 signext %b) { ; CHECK-LABEL: test_lllesc_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5) @@ -54,7 +53,7 @@ entry: define void @test_lllesc_sext_store(i8 signext %a, i8 signext %b) { ; CHECK-LABEL: test_lllesc_sext_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5) diff --git a/test/CodeGen/PowerPC/testCompareslllesi.ll b/test/CodeGen/PowerPC/testCompareslllesi.ll index 3f1e23aa86074..42062692a080d 100644 --- a/test/CodeGen/PowerPC/testCompareslllesi.ll +++ b/test/CodeGen/PowerPC/testCompareslllesi.ll @@ -1,9 +1,8 @@ -; XFAIL: * ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py @@ -11,7 +10,7 @@ define i64 @test_lllesi(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: test_lllesi: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: xori r3, r3, 1 @@ -24,7 +23,7 @@ entry: define i64 @test_lllesi_sext(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: test_lllesi_sext: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: addi r3, r3, -1 @@ -37,7 +36,7 @@ entry: define void @test_lllesi_store(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: test_lllesi_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5) @@ -54,7 +53,7 @@ entry: define void @test_lllesi_sext_store(i32 signext %a, i32 signext %b) { ; CHECK-LABEL: test_lllesi_sext_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5) diff --git a/test/CodeGen/PowerPC/testCompareslllesll.ll b/test/CodeGen/PowerPC/testCompareslllesll.ll index de29bdc710617..8db1ee19ebb06 100644 --- a/test/CodeGen/PowerPC/testCompareslllesll.ll +++ b/test/CodeGen/PowerPC/testCompareslllesll.ll @@ -1,9 +1,8 @@ -; XFAIL: * ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py @glob = common local_unnamed_addr global i64 0, align 8 @@ -11,7 +10,7 @@ ; Function Attrs: norecurse nounwind readnone define i64 @test_lllesll(i64 %a, i64 %b) { ; CHECK-LABEL: test_lllesll: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: sradi r5, r4, 63 ; CHECK-NEXT: rldicl r6, r3, 1, 63 ; CHECK-NEXT: subfc r12, r3, r4 @@ -26,7 +25,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define i64 @test_lllesll_sext(i64 %a, i64 %b) { ; CHECK-LABEL: test_lllesll_sext: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: sradi r5, r4, 63 ; CHECK-NEXT: rldicl r6, r3, 1, 63 ; CHECK-NEXT: subfc r12, r3, r4 @@ -42,7 +41,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define i64 @test_lllesll_z(i64 %a) { ; CHECK-LABEL: test_lllesll_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addi r4, r3, -1 ; CHECK-NEXT: or r3, r4, r3 ; CHECK-NEXT: rldicl r3, r3, 1, 63 @@ -56,7 +55,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define i64 @test_lllesll_sext_z(i64 %a) { ; CHECK-LABEL: test_lllesll_sext_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addi r4, r3, -1 ; CHECK-NEXT: or r3, r4, r3 ; CHECK-NEXT: sradi r3, r3, 63 @@ -70,7 +69,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_lllesll_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_lllesll_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK: sradi r6, r4, 63 ; CHECK: subfc r4, r3, r4 ; CHECK: rldicl r3, r3, 1, 63 @@ -87,7 +86,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_lllesll_sext_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_lllesll_sext_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK: sradi r6, r4, 63 ; CHECK-DAG: rldicl r3, r3, 1, 63 ; CHECK-DAG: subfc r4, r3, r4 @@ -105,7 +104,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_lllesll_z_store(i64 %a) { ; CHECK-LABEL: test_lllesll_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: addi r5, r3, -1 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) @@ -123,7 +122,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_lllesll_sext_z_store(i64 %a) { ; CHECK-LABEL: test_lllesll_sext_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: addi r5, r3, -1 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) diff --git a/test/CodeGen/PowerPC/testComparesllless.ll b/test/CodeGen/PowerPC/testComparesllless.ll index 6ed73d863f8d7..a6f3b5e3988b3 100644 --- a/test/CodeGen/PowerPC/testComparesllless.ll +++ b/test/CodeGen/PowerPC/testComparesllless.ll @@ -1,17 +1,16 @@ -; XFAIL: * ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ -; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ -; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py @glob = common local_unnamed_addr global i16 0, align 2 define i64 @test_llless(i16 signext %a, i16 signext %b) { ; CHECK-LABEL: test_llless: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: xori r3, r3, 1 @@ -24,7 +23,7 @@ entry: define i64 @test_llless_sext(i16 signext %a, i16 signext %b) { ; CHECK-LABEL: test_llless_sext: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: addi r3, r3, -1 @@ -37,7 +36,7 @@ entry: define void @test_llless_store(i16 signext %a, i16 signext %b) { ; CHECK-LABEL: test_llless_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5) @@ -54,7 +53,7 @@ entry: define void @test_llless_sext_store(i16 signext %a, i16 signext %b) { ; CHECK-LABEL: test_llless_sext_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5) diff --git a/test/CodeGen/PowerPC/testComparesllleuc.ll b/test/CodeGen/PowerPC/testComparesllleuc.ll index 0f603baa8f617..3e4beb73b6fba 100644 --- a/test/CodeGen/PowerPC/testComparesllleuc.ll +++ b/test/CodeGen/PowerPC/testComparesllleuc.ll @@ -1,9 +1,8 @@ -; XFAIL: * ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl @glob = common local_unnamed_addr global i8 0, align 1 diff --git a/test/CodeGen/PowerPC/testComparesllleui.ll b/test/CodeGen/PowerPC/testComparesllleui.ll index 673d3d0dff9f4..0dca0dcb56fae 100644 --- a/test/CodeGen/PowerPC/testComparesllleui.ll +++ b/test/CodeGen/PowerPC/testComparesllleui.ll @@ -1,9 +1,8 @@ -; XFAIL: * ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl @glob = common local_unnamed_addr global i32 0, align 4 diff --git a/test/CodeGen/PowerPC/testComparesllleull.ll b/test/CodeGen/PowerPC/testComparesllleull.ll new file mode 100644 index 0000000000000..bd75f8c736bee --- /dev/null +++ b/test/CodeGen/PowerPC/testComparesllleull.ll @@ -0,0 +1,115 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl + +@glob = common local_unnamed_addr global i64 0, align 8 + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llleull(i64 %a, i64 %b) { +entry: + %cmp = icmp ule i64 %a, %b + %conv1 = zext i1 %cmp to i64 + ret i64 %conv1 +; CHECK-LABEL: test_llleull: +; CHECK: subfc {{r[0-9]+}}, r3, r4 +; CHECK-NEXT: subfe [[REG1:r[0-9]+]], r3, r3 +; CHECK-NEXT: addi r3, [[REG1]], 1 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llleull_sext(i64 %a, i64 %b) { +entry: + %cmp = icmp ule i64 %a, %b + %conv1 = sext i1 %cmp to i64 + ret i64 %conv1 +; CHECK-LABEL: @test_llleull_sext +; CHECK: subfc [[REG1:r[0-9]+]], r3, r4 +; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}} +; CHECK: not [[REG3:r[0-9]+]], [[REG2]] +; CHECK: blr +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llleull_z(i64 %a) { +entry: + %cmp = icmp ule i64 %a, 0 + %conv1 = zext i1 %cmp to i64 + ret i64 %conv1 +; CHECK-LABEL: test_llleull_z +; CHECK: cntlzd [[REG1:r[0-9]+]], r3 +; CHECK-NEXT: rldicl r3, [[REG1]], 58, 63 +; CHECK-NEXT: blr +} + +; Function Attrs: norecurse nounwind readnone +define i64 @test_llleull_sext_z(i64 %a) { +entry: + %cmp = icmp ule i64 %a, 0 + %conv1 = sext i1 %cmp to i64 + ret i64 %conv1 +; CHECK-LABEL: @test_llleull_sext_z +; CHECK: addic [[REG1:r[0-9]+]], r3, -1 +; CHECK: subfe r3, [[REG1]] +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_llleull_store(i64 %a, i64 %b) { +entry: + %cmp = icmp ule i64 %a, %b + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob + ret void +; CHECK-LABEL: test_llleull_store: +; CHECK: subfc {{r[0-9]+}}, r3, r4 +; CHECK: subfe [[REG1:r[0-9]+]], r3, r3 +; CHECK: addi r3, [[REG1]], 1 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_llleull_sext_store(i64 %a, i64 %b) { +entry: + %cmp = icmp ule i64 %a, %b + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob + ret void +; CHECK-LABEL: @test_llleull_sext_store +; CHECK: subfc [[REG1:r[0-9]+]], r3, r4 +; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}} +; CHECK: not [[REG3:r[0-9]+]], [[REG2]] +; CHECK: std [[REG3]] +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_llleull_z_store(i64 %a) { +entry: + %cmp = icmp ule i64 %a, 0 + %conv1 = zext i1 %cmp to i64 + store i64 %conv1, i64* @glob + ret void +; CHECK-LABEL: test_llleull_z_store: +; CHECK: cntlzd [[REG1:r[0-9]+]], r3 +; CHECK: rldicl {{r[0-9]+}}, [[REG1]], 58, 63 +; CHECK: blr +} + +; Function Attrs: norecurse nounwind +define void @test_llleull_sext_z_store(i64 %a) { +entry: + %cmp = icmp ule i64 %a, 0 + %conv1 = sext i1 %cmp to i64 + store i64 %conv1, i64* @glob + ret void +; CHECK-LABEL: @test_llleull_sext_z_store +; CHECK: addic [[REG1:r[0-9]+]], r3, -1 +; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}} +; CHECK: std [[REG2]] +; CHECK: blr +} + diff --git a/test/CodeGen/PowerPC/testComparesllleus.ll b/test/CodeGen/PowerPC/testComparesllleus.ll index d49739ebb32ec..422a2b3f0f26c 100644 --- a/test/CodeGen/PowerPC/testComparesllleus.ll +++ b/test/CodeGen/PowerPC/testComparesllleus.ll @@ -1,9 +1,8 @@ -; XFAIL: * ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl @glob = common local_unnamed_addr global i16 0, align 2 diff --git a/test/CodeGen/PowerPC/testComparesllltsll.ll b/test/CodeGen/PowerPC/testComparesllltsll.ll index 9e40907debba4..3e37daf046f02 100644 --- a/test/CodeGen/PowerPC/testComparesllltsll.ll +++ b/test/CodeGen/PowerPC/testComparesllltsll.ll @@ -1,9 +1,8 @@ -; XFAIL: * ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py @@ -12,7 +11,7 @@ ; Function Attrs: norecurse nounwind readnone define i64 @test_llltsll(i64 %a, i64 %b) { ; CHECK-LABEL: test_llltsll: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: sradi [[REG1:r[0-9]+]], r3, 63 ; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], r4, 1, 63 ; CHECK-NEXT: subfc [[REG3:r[0-9]+]], r4, r3 @@ -28,7 +27,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define i64 @test_llltsll_sext(i64 %a, i64 %b) { ; CHECK-LABEL: test_llltsll_sext: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: sradi [[REG1:r[0-9]+]], r3, 63 ; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], r4, 1, 63 ; CHECK-NEXT: subfc [[REG3:r[0-9]+]], r4, r3 @@ -45,7 +44,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define i64 @test_llltsll_sext_z(i64 %a) { ; CHECK-LABEL: test_llltsll_sext_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: sradi r3, r3, 63 ; CHECK-NEXT: blr entry: @@ -57,7 +56,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_llltsll_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_llltsll_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK: sradi [[REG1:r[0-9]+]], r3, 63 ; CHECK: rldicl [[REG2:r[0-9]+]], r4, 1, 63 ; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r4, r3 @@ -74,7 +73,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_llltsll_sext_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_llltsll_sext_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK: sradi [[REG1:r[0-9]+]], r3, 63 ; CHECK: rldicl [[REG2:r[0-9]+]], r4, 1, 63 ; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r4, r3 diff --git a/test/CodeGen/PowerPC/testComparesllltuc.ll b/test/CodeGen/PowerPC/testComparesllltuc.ll index 30679733c1685..a8244e757b15d 100644 --- a/test/CodeGen/PowerPC/testComparesllltuc.ll +++ b/test/CodeGen/PowerPC/testComparesllltuc.ll @@ -1,9 +1,8 @@ -; XFAIL: * ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl @glob = common local_unnamed_addr global i8 0, align 1 @@ -11,7 +10,7 @@ ; Function Attrs: norecurse nounwind readnone define i64 @test_llltuc(i8 zeroext %a, i8 zeroext %b) { ; CHECK-LABEL: test_llltuc: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: sub [[REG:r[0-9]+]], r3, r4 ; CHECK-NEXT: rldicl r3, [[REG]], 1, 63 ; CHECK-NEXT: blr @@ -24,7 +23,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define i64 @test_llltuc_sext(i8 zeroext %a, i8 zeroext %b) { ; CHECK-LABEL: test_llltuc_sext: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: sub [[REG:r[0-9]+]], r3, r4 ; CHECK-NEXT: sradi r3, [[REG]], 63 ; CHECK-NEXT: blr @@ -37,7 +36,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_llltuc_store(i8 zeroext %a, i8 zeroext %b) { ; CHECK-LABEL: test_llltuc_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK: sub [[REG:r[2-9]+]], r3, r4 ; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63 entry: @@ -50,7 +49,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_llltuc_sext_store(i8 zeroext %a, i8 zeroext %b) { ; CHECK-LABEL: test_llltuc_sext_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK: sub [[REG:r[0-9]+]], r3, r4 ; CHECK: sradi {{r[0-9]+}}, [[REG]], 63 entry: diff --git a/test/CodeGen/PowerPC/testComparesllltui.ll b/test/CodeGen/PowerPC/testComparesllltui.ll index 374711db523ee..e785942b3c9ff 100644 --- a/test/CodeGen/PowerPC/testComparesllltui.ll +++ b/test/CodeGen/PowerPC/testComparesllltui.ll @@ -1,9 +1,8 @@ -; XFAIL: * ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl @glob = common local_unnamed_addr global i32 0, align 4 @@ -11,7 +10,7 @@ ; Function Attrs: norecurse nounwind readnone define i64 @test_llltui(i32 zeroext %a, i32 zeroext %b) { ; CHECK-LABEL: test_llltui: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NOT: clrldi ; CHECK-NEXT: sub [[REG:r[0-9]+]], r3, r4 ; CHECK-NEXT: rldicl r3, [[REG]], 1, 63 @@ -25,7 +24,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define i64 @test_llltui_sext(i32 zeroext %a, i32 zeroext %b) { ; CHECK-LABEL: test_llltui_sext: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: sub [[REG:r[0-9]+]], r3, r4 ; CHECK-NEXT: sradi r3, [[REG]], 63 ; CHECK-NEXT: blr @@ -38,7 +37,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define i64 @test_llltui_z(i32 zeroext %a) { ; CHECK-LABEL: test_llltui_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: li r3, 0 ; CHECK-NEXT: blr entry: @@ -48,7 +47,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define i64 @test_llltui_sext_z(i32 zeroext %a) { ; CHECK-LABEL: test_llltui_sext_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: li r3, 0 ; CHECK-NEXT: blr entry: @@ -58,7 +57,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_llltui_store(i32 zeroext %a, i32 zeroext %b) { ; CHECK-LABEL: test_llltui_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NOT: clrldi ; CHECK: sub [[REG:r[2-9]+]], r3, r4 ; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63 @@ -72,7 +71,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_llltui_sext_store(i32 zeroext %a, i32 zeroext %b) { ; CHECK-LABEL: test_llltui_sext_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NOT: clrldi ; CHECK: sub [[REG:r[0-9]+]], r3, r4 ; CHECK: sradi {{r[0-9]+}}, [[REG]], 63 @@ -86,7 +85,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_llltui_z_store(i32 zeroext %a) { ; CHECK-LABEL: test_llltui_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK: li [[REG:r[0-9]+]], 0 ; CHECK: stw [[REG]], 0(r3) ; CHECK-NEXT: blr @@ -98,7 +97,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_llltui_sext_z_store(i32 zeroext %a) { ; CHECK-LABEL: test_llltui_sext_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK: li [[REG:r[0-9]+]], 0 ; CHECK: stw [[REG]], 0(r3) ; CHECK-NEXT: blr diff --git a/test/CodeGen/PowerPC/testComparesllltus.ll b/test/CodeGen/PowerPC/testComparesllltus.ll index bf3c14f0628d8..e997d0aa8b82b 100644 --- a/test/CodeGen/PowerPC/testComparesllltus.ll +++ b/test/CodeGen/PowerPC/testComparesllltus.ll @@ -1,9 +1,8 @@ -; XFAIL: * ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl @glob = common local_unnamed_addr global i16 0, align 2 @@ -11,7 +10,7 @@ ; Function Attrs: norecurse nounwind readnone define i64 @test_llltus(i16 zeroext %a, i16 zeroext %b) { ; CHECK-LABEL: test_llltus: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: sub [[REG:r[0-9]+]], r3, r4 ; CHECK-NEXT: rldicl r3, [[REG]], 1, 63 ; CHECK-NEXT: blr @@ -24,7 +23,7 @@ entry: ; Function Attrs: norecurse nounwind readnone define i64 @test_llltus_sext(i16 zeroext %a, i16 zeroext %b) { ; CHECK-LABEL: test_llltus_sext: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: sub [[REG:r[0-9]+]], r3, r4 ; CHECK-NEXT: sradi r3, [[REG]], 63 ; CHECK-NEXT: blr @@ -49,7 +48,7 @@ entry: ; Function Attrs: norecurse nounwind define void @test_llltus_sext_store(i16 zeroext %a, i16 zeroext %b) { ; CHECK-LABEL: test_llltus_sext_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK: sub [[REG:r[0-9]+]], r3, r4 ; CHECK: sradi {{r[0-9]+}}, [[REG]], 63 entry: diff --git a/test/CodeGen/PowerPC/testComparesllnesll.ll b/test/CodeGen/PowerPC/testComparesllnesll.ll index 19b00b7b78f36..cdd272f57bd41 100644 --- a/test/CodeGen/PowerPC/testComparesllnesll.ll +++ b/test/CodeGen/PowerPC/testComparesllnesll.ll @@ -1,9 +1,8 @@ -; XFAIL: * ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py @@ -11,7 +10,7 @@ define i64 @test_llnesll(i64 %a, i64 %b) { ; CHECK-LABEL: test_llnesll: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: addic r4, r3, -1 ; CHECK-NEXT: subfe r3, r4, r3 @@ -24,7 +23,7 @@ entry: define i64 @test_llnesll_sext(i64 %a, i64 %b) { ; CHECK-LABEL: test_llnesll_sext: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: subfic r3, r3, 0 ; CHECK-NEXT: subfe r3, r3, r3 @@ -37,7 +36,7 @@ entry: define i64 @test_llnesll_z(i64 %a) { ; CHECK-LABEL: test_llnesll_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addic r4, r3, -1 ; CHECK-NEXT: subfe r3, r4, r3 ; CHECK-NEXT: blr @@ -49,7 +48,7 @@ entry: define i64 @test_llnesll_sext_z(i64 %a) { ; CHECK-LABEL: test_llnesll_sext_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: subfic r3, r3, 0 ; CHECK-NEXT: subfe r3, r3, r3 ; CHECK-NEXT: blr @@ -61,7 +60,7 @@ entry: define void @test_llnesll_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_llnesll_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5) @@ -78,7 +77,7 @@ entry: define void @test_llnesll_sext_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_llnesll_sext_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5) @@ -95,7 +94,7 @@ entry: define void @test_llnesll_z_store(i64 %a) { ; CHECK-LABEL: test_llnesll_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: addic r5, r3, -1 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) @@ -111,7 +110,7 @@ entry: define void @test_llnesll_sext_z_store(i64 %a) { ; CHECK-LABEL: test_llnesll_sext_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: subfic r3, r3, 0 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) diff --git a/test/CodeGen/PowerPC/testComparesllneull.ll b/test/CodeGen/PowerPC/testComparesllneull.ll index 58fa714f4c168..7956881f495a0 100644 --- a/test/CodeGen/PowerPC/testComparesllneull.ll +++ b/test/CodeGen/PowerPC/testComparesllneull.ll @@ -1,9 +1,8 @@ -; XFAIL: * ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py @@ -11,7 +10,7 @@ define i64 @test_llneull(i64 %a, i64 %b) { ; CHECK-LABEL: test_llneull: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: addic r4, r3, -1 ; CHECK-NEXT: subfe r3, r4, r3 @@ -24,7 +23,7 @@ entry: define i64 @test_llneull_sext(i64 %a, i64 %b) { ; CHECK-LABEL: test_llneull_sext: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: subfic r3, r3, 0 ; CHECK-NEXT: subfe r3, r3, r3 @@ -37,7 +36,7 @@ entry: define i64 @test_llneull_z(i64 %a) { ; CHECK-LABEL: test_llneull_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addic r4, r3, -1 ; CHECK-NEXT: subfe r3, r4, r3 ; CHECK-NEXT: blr @@ -49,7 +48,7 @@ entry: define i64 @test_llneull_sext_z(i64 %a) { ; CHECK-LABEL: test_llneull_sext_z: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: subfic r3, r3, 0 ; CHECK-NEXT: subfe r3, r3, r3 ; CHECK-NEXT: blr @@ -61,7 +60,7 @@ entry: define void @test_llneull_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_llneull_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5) @@ -78,7 +77,7 @@ entry: define void @test_llneull_sext_store(i64 %a, i64 %b) { ; CHECK-LABEL: test_llneull_sext_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5) @@ -95,7 +94,7 @@ entry: define void @test_llneull_z_store(i64 %a) { ; CHECK-LABEL: test_llneull_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: addic r5, r3, -1 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) @@ -111,7 +110,7 @@ entry: define void @test_llneull_sext_z_store(i64 %a) { ; CHECK-LABEL: test_llneull_sext_z_store: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: subfic r3, r3, 0 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) diff --git a/test/CodeGen/PowerPC/vec_add_sub_quadword.ll b/test/CodeGen/PowerPC/vec_add_sub_quadword.ll index f42f7d1178319..8f3864ff26836 100644 --- a/test/CodeGen/PowerPC/vec_add_sub_quadword.ll +++ b/test/CodeGen/PowerPC/vec_add_sub_quadword.ll @@ -8,7 +8,7 @@ define <1 x i128> @out_of_bounds_insertelement(<1 x i128> %x, i128 %val) nounwin %result = add <1 x i128> %x, %tmpvec ret <1 x i128> %result ; CHECK-LABEL: @out_of_bounds_insertelement -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: blr } diff --git a/test/CodeGen/PowerPC/vec_extract_p9.ll b/test/CodeGen/PowerPC/vec_extract_p9.ll index b07c905ceecf0..7e397f546848c 100644 --- a/test/CodeGen/PowerPC/vec_extract_p9.ll +++ b/test/CodeGen/PowerPC/vec_extract_p9.ll @@ -4,12 +4,12 @@ define zeroext i8 @test1(<16 x i8> %a, i32 signext %index) { ; CHECK-LE-LABEL: test1: -; CHECK-LE: # BB#0: # %entry +; CHECK-LE: # %bb.0: # %entry ; CHECK-LE-NEXT: vextubrx 3, 5, 2 ; CHECK-LE-NEXT: clrldi 3, 3, 56 ; CHECK-LE-NEXT: blr ; CHECK-BE-LABEL: test1: -; CHECK-BE: # BB#0: # %entry +; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: vextublx 3, 5, 2 ; CHECK-BE-NEXT: clrldi 3, 3, 56 ; CHECK-BE-NEXT: blr @@ -21,12 +21,12 @@ entry: define signext i8 @test2(<16 x i8> %a, i32 signext %index) { ; CHECK-LE-LABEL: test2: -; CHECK-LE: # BB#0: # %entry +; CHECK-LE: # %bb.0: # %entry ; CHECK-LE-NEXT: vextubrx 3, 5, 2 ; CHECK-LE-NEXT: extsb 3, 3 ; CHECK-LE-NEXT: blr ; CHECK-BE-LABEL: test2: -; CHECK-BE: # BB#0: # %entry +; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: vextublx 3, 5, 2 ; CHECK-BE-NEXT: extsb 3, 3 ; CHECK-BE-NEXT: blr @@ -38,13 +38,13 @@ entry: define zeroext i16 @test3(<8 x i16> %a, i32 signext %index) { ; CHECK-LE-LABEL: test3: -; CHECK-LE: # BB#0: # %entry +; CHECK-LE: # %bb.0: # %entry ; CHECK-LE-NEXT: rlwinm 3, 5, 1, 28, 30 ; CHECK-LE-NEXT: vextuhrx 3, 3, 2 ; CHECK-LE-NEXT: clrldi 3, 3, 48 ; CHECK-LE-NEXT: blr ; CHECK-BE-LABEL: test3: -; CHECK-BE: # BB#0: # %entry +; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: rlwinm 3, 5, 1, 28, 30 ; CHECK-BE-NEXT: vextuhlx 3, 3, 2 ; CHECK-BE-NEXT: clrldi 3, 3, 48 @@ -57,13 +57,13 @@ entry: define signext i16 @test4(<8 x i16> %a, i32 signext %index) { ; CHECK-LE-LABEL: test4: -; CHECK-LE: # BB#0: # %entry +; CHECK-LE: # %bb.0: # %entry ; CHECK-LE-NEXT: rlwinm 3, 5, 1, 28, 30 ; CHECK-LE-NEXT: vextuhrx 3, 3, 2 ; CHECK-LE-NEXT: extsh 3, 3 ; CHECK-LE-NEXT: blr ; CHECK-BE-LABEL: test4: -; CHECK-BE: # BB#0: # %entry +; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: rlwinm 3, 5, 1, 28, 30 ; CHECK-BE-NEXT: vextuhlx 3, 3, 2 ; CHECK-BE-NEXT: extsh 3, 3 @@ -76,12 +76,12 @@ entry: define zeroext i32 @test5(<4 x i32> %a, i32 signext %index) { ; CHECK-LE-LABEL: test5: -; CHECK-LE: # BB#0: # %entry +; CHECK-LE: # %bb.0: # %entry ; CHECK-LE-NEXT: rlwinm 3, 5, 2, 28, 29 ; CHECK-LE-NEXT: vextuwrx 3, 3, 2 ; CHECK-LE-NEXT: blr ; CHECK-BE-LABEL: test5: -; CHECK-BE: # BB#0: # %entry +; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: rlwinm 3, 5, 2, 28, 29 ; CHECK-BE-NEXT: vextuwlx 3, 3, 2 ; CHECK-BE-NEXT: blr @@ -93,13 +93,13 @@ entry: define signext i32 @test6(<4 x i32> %a, i32 signext %index) { ; CHECK-LE-LABEL: test6: -; CHECK-LE: # BB#0: # %entry +; CHECK-LE: # %bb.0: # %entry ; CHECK-LE-NEXT: rlwinm 3, 5, 2, 28, 29 ; CHECK-LE-NEXT: vextuwrx 3, 3, 2 ; CHECK-LE-NEXT: extsw 3, 3 ; CHECK-LE-NEXT: blr ; CHECK-BE-LABEL: test6: -; CHECK-BE: # BB#0: # %entry +; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: rlwinm 3, 5, 2, 28, 29 ; CHECK-BE-NEXT: vextuwlx 3, 3, 2 ; CHECK-BE-NEXT: extsw 3, 3 @@ -113,13 +113,13 @@ entry: ; Test with immediate index define zeroext i8 @test7(<16 x i8> %a) { ; CHECK-LE-LABEL: test7: -; CHECK-LE: # BB#0: # %entry +; CHECK-LE: # %bb.0: # %entry ; CHECK-LE-NEXT: li 3, 1 ; CHECK-LE-NEXT: vextubrx 3, 3, 2 ; CHECK-LE-NEXT: clrldi 3, 3, 56 ; CHECK-LE-NEXT: blr ; CHECK-BE-LABEL: test7: -; CHECK-BE: # BB#0: # %entry +; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: li 3, 1 ; CHECK-BE-NEXT: vextublx 3, 3, 2 ; CHECK-BE-NEXT: clrldi 3, 3, 56 @@ -132,13 +132,13 @@ entry: define zeroext i16 @test8(<8 x i16> %a) { ; CHECK-LE-LABEL: test8: -; CHECK-LE: # BB#0: # %entry +; CHECK-LE: # %bb.0: # %entry ; CHECK-LE-NEXT: li 3, 2 ; CHECK-LE-NEXT: vextuhrx 3, 3, 2 ; CHECK-LE-NEXT: clrldi 3, 3, 48 ; CHECK-LE-NEXT: blr ; CHECK-BE-LABEL: test8: -; CHECK-BE: # BB#0: # %entry +; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: li 3, 2 ; CHECK-BE-NEXT: vextuhlx 3, 3, 2 ; CHECK-BE-NEXT: clrldi 3, 3, 48 @@ -151,12 +151,12 @@ entry: define zeroext i32 @test9(<4 x i32> %a) { ; CHECK-LE-LABEL: test9: -; CHECK-LE: # BB#0: # %entry +; CHECK-LE: # %bb.0: # %entry ; CHECK-LE-NEXT: li 3, 12 ; CHECK-LE-NEXT: vextuwrx 3, 3, 2 ; CHECK-LE-NEXT: blr ; CHECK-BE-LABEL: test9: -; CHECK-BE: # BB#0: # %entry +; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: li 3, 12 ; CHECK-BE-NEXT: vextuwlx 3, 3, 2 ; CHECK-BE-NEXT: blr diff --git a/test/CodeGen/PowerPC/vec_extract_p9_2.ll b/test/CodeGen/PowerPC/vec_extract_p9_2.ll index 9734a88fdecd4..f2ce7924ed90f 100644 --- a/test/CodeGen/PowerPC/vec_extract_p9_2.ll +++ b/test/CodeGen/PowerPC/vec_extract_p9_2.ll @@ -4,13 +4,13 @@ define zeroext i8 @test_add1(<16 x i8> %a, i32 signext %index, i8 zeroext %c) { ; CHECK-LE-LABEL: test_add1: -; CHECK-LE: # BB#0: # %entry +; CHECK-LE: # %bb.0: # %entry ; CHECK-LE-NEXT: vextubrx 3, 5, 2 ; CHECK-LE-NEXT: add 3, 3, 6 ; CHECK-LE-NEXT: rlwinm 3, 3, 0, 24, 31 ; CHECK-LE-NEXT: blr ; CHECK-BE-LABEL: test_add1: -; CHECK-BE: # BB#0: # %entry +; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: vextublx 3, 5, 2 ; CHECK-BE-NEXT: add 3, 3, 6 ; CHECK-BE-NEXT: rlwinm 3, 3, 0, 24, 31 @@ -26,13 +26,13 @@ entry: define signext i8 @test_add2(<16 x i8> %a, i32 signext %index, i8 signext %c) { ; CHECK-LE-LABEL: test_add2: -; CHECK-LE: # BB#0: # %entry +; CHECK-LE: # %bb.0: # %entry ; CHECK-LE-NEXT: vextubrx 3, 5, 2 ; CHECK-LE-NEXT: add 3, 3, 6 ; CHECK-LE-NEXT: extsb 3, 3 ; CHECK-LE-NEXT: blr ; CHECK-BE-LABEL: test_add2: -; CHECK-BE: # BB#0: # %entry +; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: vextublx 3, 5, 2 ; CHECK-BE-NEXT: add 3, 3, 6 ; CHECK-BE-NEXT: extsb 3, 3 @@ -48,14 +48,14 @@ entry: define zeroext i16 @test_add3(<8 x i16> %a, i32 signext %index, i16 zeroext %c) { ; CHECK-LE-LABEL: test_add3: -; CHECK-LE: # BB#0: # %entry +; CHECK-LE: # %bb.0: # %entry ; CHECK-LE-NEXT: rlwinm 3, 5, 1, 28, 30 ; CHECK-LE-NEXT: vextuhrx 3, 3, 2 ; CHECK-LE-NEXT: add 3, 3, 6 ; CHECK-LE-NEXT: rlwinm 3, 3, 0, 16, 31 ; CHECK-LE-NEXT: blr ; CHECK-BE-LABEL: test_add3: -; CHECK-BE: # BB#0: # %entry +; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: rlwinm 3, 5, 1, 28, 30 ; CHECK-BE-NEXT: vextuhlx 3, 3, 2 ; CHECK-BE-NEXT: add 3, 3, 6 @@ -72,14 +72,14 @@ entry: define signext i16 @test_add4(<8 x i16> %a, i32 signext %index, i16 signext %c) { ; CHECK-LE-LABEL: test_add4: -; CHECK-LE: # BB#0: # %entry +; CHECK-LE: # %bb.0: # %entry ; CHECK-LE-NEXT: rlwinm 3, 5, 1, 28, 30 ; CHECK-LE-NEXT: vextuhrx 3, 3, 2 ; CHECK-LE-NEXT: add 3, 3, 6 ; CHECK-LE-NEXT: extsh 3, 3 ; CHECK-LE-NEXT: blr ; CHECK-BE-LABEL: test_add4: -; CHECK-BE: # BB#0: # %entry +; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: rlwinm 3, 5, 1, 28, 30 ; CHECK-BE-NEXT: vextuhlx 3, 3, 2 ; CHECK-BE-NEXT: add 3, 3, 6 @@ -96,14 +96,14 @@ entry: define zeroext i32 @test_add5(<4 x i32> %a, i32 signext %index, i32 zeroext %c) { ; CHECK-LE-LABEL: test_add5: -; CHECK-LE: # BB#0: # %entry +; CHECK-LE: # %bb.0: # %entry ; CHECK-LE-NEXT: rlwinm 3, 5, 2, 28, 29 ; CHECK-LE-NEXT: vextuwrx 3, 3, 2 ; CHECK-LE-NEXT: add 3, 3, 6 ; CHECK-LE-NEXT: clrldi 3, 3, 32 ; CHECK-LE-NEXT: blr ; CHECK-BE-LABEL: test_add5: -; CHECK-BE: # BB#0: # %entry +; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: rlwinm 3, 5, 2, 28, 29 ; CHECK-BE-NEXT: vextuwlx 3, 3, 2 ; CHECK-BE-NEXT: add 3, 3, 6 @@ -117,14 +117,14 @@ entry: define signext i32 @test_add6(<4 x i32> %a, i32 signext %index, i32 signext %c) { ; CHECK-LE-LABEL: test_add6: -; CHECK-LE: # BB#0: # %entry +; CHECK-LE: # %bb.0: # %entry ; CHECK-LE-NEXT: rlwinm 3, 5, 2, 28, 29 ; CHECK-LE-NEXT: vextuwrx 3, 3, 2 ; CHECK-LE-NEXT: add 3, 3, 6 ; CHECK-LE-NEXT: extsw 3, 3 ; CHECK-LE-NEXT: blr ; CHECK-BE-LABEL: test_add6: -; CHECK-BE: # BB#0: # %entry +; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: rlwinm 3, 5, 2, 28, 29 ; CHECK-BE-NEXT: vextuwlx 3, 3, 2 ; CHECK-BE-NEXT: add 3, 3, 6 @@ -139,11 +139,11 @@ entry: ; When extracting word element 2 on LE, it's better to use mfvsrwz rather than vextuwrx define zeroext i32 @test7(<4 x i32> %a) { ; CHECK-LE-LABEL: test7: -; CHECK-LE: # BB#0: # %entry +; CHECK-LE: # %bb.0: # %entry ; CHECK-LE-NEXT: mfvsrwz 3, 34 ; CHECK-LE-NEXT: blr ; CHECK-BE-LABEL: test7: -; CHECK-BE: # BB#0: # %entry +; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: li 3, 8 ; CHECK-BE-NEXT: vextuwlx 3, 3, 2 ; CHECK-BE-NEXT: blr @@ -154,13 +154,13 @@ entry: define zeroext i32 @testadd_7(<4 x i32> %a, i32 zeroext %c) { ; CHECK-LE-LABEL: testadd_7: -; CHECK-LE: # BB#0: # %entry +; CHECK-LE: # %bb.0: # %entry ; CHECK-LE-NEXT: mfvsrwz 3, 34 ; CHECK-LE-NEXT: add 3, 3, 5 ; CHECK-LE-NEXT: clrldi 3, 3, 32 ; CHECK-LE-NEXT: blr ; CHECK-BE-LABEL: testadd_7: -; CHECK-BE: # BB#0: # %entry +; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: li 3, 8 ; CHECK-BE-NEXT: vextuwlx 3, 3, 2 ; CHECK-BE-NEXT: add 3, 3, 5 @@ -174,12 +174,12 @@ entry: define signext i32 @test8(<4 x i32> %a) { ; CHECK-LE-LABEL: test8: -; CHECK-LE: # BB#0: # %entry +; CHECK-LE: # %bb.0: # %entry ; CHECK-LE-NEXT: mfvsrwz 3, 34 ; CHECK-LE-NEXT: extsw 3, 3 ; CHECK-LE-NEXT: blr ; CHECK-BE-LABEL: test8: -; CHECK-BE: # BB#0: # %entry +; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: li 3, 8 ; CHECK-BE-NEXT: vextuwlx 3, 3, 2 ; CHECK-BE-NEXT: extsw 3, 3 @@ -191,13 +191,13 @@ entry: define signext i32 @testadd_8(<4 x i32> %a, i32 signext %c) { ; CHECK-LE-LABEL: testadd_8: -; CHECK-LE: # BB#0: # %entry +; CHECK-LE: # %bb.0: # %entry ; CHECK-LE-NEXT: mfvsrwz 3, 34 ; CHECK-LE-NEXT: add 3, 3, 5 ; CHECK-LE-NEXT: extsw 3, 3 ; CHECK-LE-NEXT: blr ; CHECK-BE-LABEL: testadd_8: -; CHECK-BE: # BB#0: # %entry +; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: li 3, 8 ; CHECK-BE-NEXT: vextuwlx 3, 3, 2 ; CHECK-BE-NEXT: add 3, 3, 5 @@ -212,13 +212,13 @@ entry: ; When extracting word element 1 on BE, it's better to use mfvsrwz rather than vextuwlx define signext i32 @test9(<4 x i32> %a) { ; CHECK-LE-LABEL: test9: -; CHECK-LE: # BB#0: # %entry +; CHECK-LE: # %bb.0: # %entry ; CHECK-LE-NEXT: li 3, 4 ; CHECK-LE-NEXT: vextuwrx 3, 3, 2 ; CHECK-LE-NEXT: extsw 3, 3 ; CHECK-LE-NEXT: blr ; CHECK-BE-LABEL: test9: -; CHECK-BE: # BB#0: # %entry +; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: mfvsrwz 3, 34 ; CHECK-BE-NEXT: extsw 3, 3 ; CHECK-BE-NEXT: blr @@ -229,14 +229,14 @@ entry: define signext i32 @testadd_9(<4 x i32> %a, i32 signext %c) { ; CHECK-LE-LABEL: testadd_9: -; CHECK-LE: # BB#0: # %entry +; CHECK-LE: # %bb.0: # %entry ; CHECK-LE-NEXT: li 3, 4 ; CHECK-LE-NEXT: vextuwrx 3, 3, 2 ; CHECK-LE-NEXT: add 3, 3, 5 ; CHECK-LE-NEXT: extsw 3, 3 ; CHECK-LE-NEXT: blr ; CHECK-BE-LABEL: testadd_9: -; CHECK-BE: # BB#0: # %entry +; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: mfvsrwz 3, 34 ; CHECK-BE-NEXT: add 3, 3, 5 ; CHECK-BE-NEXT: extsw 3, 3 diff --git a/test/CodeGen/PowerPC/vec_int_ext.ll b/test/CodeGen/PowerPC/vec_int_ext.ll index d7bed503318eb..1c86e38d06046 100644 --- a/test/CodeGen/PowerPC/vec_int_ext.ll +++ b/test/CodeGen/PowerPC/vec_int_ext.ll @@ -4,11 +4,11 @@ define <4 x i32> @vextsb2wLE(<16 x i8> %a) { ; CHECK-LE-LABEL: vextsb2wLE: -; CHECK-LE: # BB#0: # %entry +; CHECK-LE: # %bb.0: # %entry ; CHECK-LE-NEXT: vextsb2w 2, 2 ; CHECK-LE-NEXT: blr ; CHECK-BE-LABEL: vextsb2wLE: -; CHECK-BE: # BB#0: # %entry +; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: vperm 2, 2, 2, 3 ; CHECK-BE-NEXT: vextsb2w 2, 2 ; CHECK-BE-NEXT: blr @@ -31,11 +31,11 @@ entry: define <2 x i64> @vextsb2dLE(<16 x i8> %a) { ; CHECK-LE-LABEL: vextsb2dLE: -; CHECK-LE: # BB#0: # %entry +; CHECK-LE: # %bb.0: # %entry ; CHECK-LE-NEXT: vextsb2d 2, 2 ; CHECK-LE-NEXT: blr ; CHECK-BE-LABEL: vextsb2dLE: -; CHECK-BE: # BB#0: # %entry +; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: vperm 2, 2, 2, 3 ; CHECK-BE-NEXT: vextsb2d 2, 2 ; CHECK-BE-NEXT: blr @@ -52,11 +52,11 @@ entry: define <4 x i32> @vextsh2wLE(<8 x i16> %a) { ; CHECK-LE-LABEL: vextsh2wLE: -; CHECK-LE: # BB#0: # %entry +; CHECK-LE: # %bb.0: # %entry ; CHECK-LE-NEXT: vextsh2w 2, 2 ; CHECK-LE-NEXT: blr ; CHECK-BE-LABEL: vextsh2wLE: -; CHECK-BE: # BB#0: # %entry +; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: vperm 2, 2, 2, 3 ; CHECK-BE-NEXT: vextsh2w 2, 2 ; CHECK-BE-NEXT: blr @@ -79,11 +79,11 @@ entry: define <2 x i64> @vextsh2dLE(<8 x i16> %a) { ; CHECK-LE-LABEL: vextsh2dLE: -; CHECK-LE: # BB#0: # %entry +; CHECK-LE: # %bb.0: # %entry ; CHECK-LE-NEXT: vextsh2d 2, 2 ; CHECK-LE-NEXT: blr ; CHECK-BE-LABEL: vextsh2dLE: -; CHECK-BE: # BB#0: # %entry +; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: vperm 2, 2, 2, 3 ; CHECK-BE-NEXT: vextsh2d 2, 2 ; CHECK-BE-NEXT: blr @@ -100,11 +100,11 @@ entry: define <2 x i64> @vextsw2dLE(<4 x i32> %a) { ; CHECK-LE-LABEL: vextsw2dLE: -; CHECK-LE: # BB#0: # %entry +; CHECK-LE: # %bb.0: # %entry ; CHECK-LE-NEXT: vextsw2d 2, 2 ; CHECK-LE-NEXT: blr ; CHECK-BE-LABEL: vextsw2dLE: -; CHECK-BE: # BB#0: # %entry +; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: vmrgew ; CHECK-BE-NEXT: vextsw2d 2, 2 ; CHECK-BE-NEXT: blr @@ -121,11 +121,11 @@ entry: define <4 x i32> @vextsb2wBE(<16 x i8> %a) { ; CHECK-BE-LABEL: vextsb2wBE: -; CHECK-BE: # BB#0: # %entry +; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: vextsb2w 2, 2 ; CHECK-BE-NEXT: blr ; CHECK-LE-LABEL: vextsb2wBE: -; CHECK-LE: # BB#0: # %entry +; CHECK-LE: # %bb.0: # %entry ; CHECK-LE-NEXT: vsldoi 2, 2, 2, 13 ; CHECK-LE-NEXT: vextsb2w 2, 2 ; CHECK-LE-NEXT: blr @@ -147,11 +147,11 @@ entry: define <2 x i64> @vextsb2dBE(<16 x i8> %a) { ; CHECK-BE-LABEL: vextsb2dBE: -; CHECK-BE: # BB#0: # %entry +; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: vextsb2d 2, 2 ; CHECK-BE-NEXT: blr ; CHECK-LE-LABEL: vextsb2dBE: -; CHECK-LE: # BB#0: # %entry +; CHECK-LE: # %bb.0: # %entry ; CHECK-LE-NEXT: vsldoi 2, 2, 2, 9 ; CHECK-LE-NEXT: vextsb2d 2, 2 ; CHECK-LE-NEXT: blr @@ -167,11 +167,11 @@ entry: define <4 x i32> @vextsh2wBE(<8 x i16> %a) { ; CHECK-BE-LABEL: vextsh2wBE: -; CHECK-BE: # BB#0: # %entry +; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: vextsh2w 2, 2 ; CHECK-BE-NEXT: blr ; CHECK-LE-LABEL: vextsh2wBE: -; CHECK-LE: # BB#0: # %entry +; CHECK-LE: # %bb.0: # %entry ; CHECK-LE-NEXT: vsldoi 2, 2, 2, 14 ; CHECK-LE-NEXT: vextsh2w 2, 2 ; CHECK-LE-NEXT: blr @@ -193,11 +193,11 @@ entry: define <2 x i64> @vextsh2dBE(<8 x i16> %a) { ; CHECK-BE-LABEL: vextsh2dBE: -; CHECK-BE: # BB#0: # %entry +; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: vextsh2d 2, 2 ; CHECK-BE-NEXT: blr ; CHECK-LE-LABEL: vextsh2dBE: -; CHECK-LE: # BB#0: # %entry +; CHECK-LE: # %bb.0: # %entry ; CHECK-LE-NEXT: vsldoi 2, 2, 2, 10 ; CHECK-LE-NEXT: vextsh2d 2, 2 ; CHECK-LE-NEXT: blr @@ -213,11 +213,11 @@ entry: define <2 x i64> @vextsw2dBE(<4 x i32> %a) { ; CHECK-BE-LABEL: vextsw2dBE: -; CHECK-BE: # BB#0: # %entry +; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: vextsw2d 2, 2 ; CHECK-BE-NEXT: blr ; CHECK-LE-LABEL: vextsw2dBE: -; CHECK-LE: # BB#0: # %entry +; CHECK-LE: # %bb.0: # %entry ; CHECK-LE-NEXT: vsldoi 2, 2, 2, 12 ; CHECK-LE-NEXT: vextsw2d 2, 2 ; CHECK-LE-NEXT: blr @@ -233,11 +233,11 @@ entry: define <2 x i64> @vextDiffVectors(<4 x i32> %a, <4 x i32> %b) { ; CHECK-LE-LABEL: vextDiffVectors: -; CHECK-LE: # BB#0: # %entry +; CHECK-LE: # %bb.0: # %entry ; CHECK-LE-NOT: vextsw2d ; CHECK-BE-LABEL: vextDiffVectors: -; CHECK-BE: # BB#0: # %entry +; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NOT: vextsw2d entry: %vecext = extractelement <4 x i32> %a, i32 0 @@ -252,11 +252,11 @@ entry: define <8 x i16> @testInvalidExtend(<16 x i8> %a) { entry: ; CHECK-LE-LABEL: testInvalidExtend: -; CHECK-LE: # BB#0: # %entry +; CHECK-LE: # %bb.0: # %entry ; CHECK-LE-NOT: vexts ; CHECK-BE-LABEL: testInvalidExtend: -; CHECK-BE: # BB#0: # %entry +; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NOT: vexts %vecext = extractelement <16 x i8> %a, i32 0 diff --git a/test/CodeGen/PowerPC/vec_revb.ll b/test/CodeGen/PowerPC/vec_revb.ll index c09164bae13eb..00c08a1204fe2 100644 --- a/test/CodeGen/PowerPC/vec_revb.ll +++ b/test/CodeGen/PowerPC/vec_revb.ll @@ -3,7 +3,7 @@ define <8 x i16> @testXXBRH(<8 x i16> %a) { ; CHECK-LABEL: testXXBRH: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xxbrh 34, 34 ; CHECK-NEXT: blr @@ -16,7 +16,7 @@ entry: define <4 x i32> @testXXBRW(<4 x i32> %a) { ; CHECK-LABEL: testXXBRW: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xxbrw 34, 34 ; CHECK-NEXT: blr @@ -29,7 +29,7 @@ entry: define <2 x double> @testXXBRD(<2 x double> %a) { ; CHECK-LABEL: testXXBRD: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xxbrd 34, 34 ; CHECK-NEXT: blr @@ -42,7 +42,7 @@ entry: define <1 x i128> @testXXBRQ(<1 x i128> %a) { ; CHECK-LABEL: testXXBRQ: -; CHECK: # BB#0: # %entry +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xxbrq 34, 34 ; CHECK-NEXT: blr diff --git a/test/CodeGen/PowerPC/vselect-constants.ll b/test/CodeGen/PowerPC/vselect-constants.ll index 077eb2defc0e1..5f23c3e40de6f 100644 --- a/test/CodeGen/PowerPC/vselect-constants.ll +++ b/test/CodeGen/PowerPC/vselect-constants.ll @@ -9,7 +9,7 @@ define <4 x i32> @sel_C1_or_C2_vec(<4 x i1> %cond) { ; CHECK-LABEL: sel_C1_or_C2_vec: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vspltisw 3, -16 ; CHECK-NEXT: vspltisw 4, 15 ; CHECK-NEXT: addis 3, 2, .LCPI0_0@toc@ha @@ -29,7 +29,7 @@ define <4 x i32> @sel_C1_or_C2_vec(<4 x i1> %cond) { define <4 x i32> @cmp_sel_C1_or_C2_vec(<4 x i32> %x, <4 x i32> %y) { ; CHECK-LABEL: cmp_sel_C1_or_C2_vec: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vcmpequw 2, 2, 3 ; CHECK-NEXT: addis 3, 2, .LCPI1_0@toc@ha ; CHECK-NEXT: addis 4, 2, .LCPI1_1@toc@ha @@ -46,7 +46,7 @@ define <4 x i32> @cmp_sel_C1_or_C2_vec(<4 x i32> %x, <4 x i32> %y) { define <4 x i32> @sel_Cplus1_or_C_vec(<4 x i1> %cond) { ; CHECK-LABEL: sel_Cplus1_or_C_vec: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vspltisw 3, 1 ; CHECK-NEXT: addis 3, 2, .LCPI2_0@toc@ha ; CHECK-NEXT: addi 3, 3, .LCPI2_0@toc@l @@ -60,7 +60,7 @@ define <4 x i32> @sel_Cplus1_or_C_vec(<4 x i1> %cond) { define <4 x i32> @cmp_sel_Cplus1_or_C_vec(<4 x i32> %x, <4 x i32> %y) { ; CHECK-LABEL: cmp_sel_Cplus1_or_C_vec: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vcmpequw 2, 2, 3 ; CHECK-NEXT: addis 3, 2, .LCPI3_0@toc@ha ; CHECK-NEXT: addi 3, 3, .LCPI3_0@toc@l @@ -74,7 +74,7 @@ define <4 x i32> @cmp_sel_Cplus1_or_C_vec(<4 x i32> %x, <4 x i32> %y) { define <4 x i32> @sel_Cminus1_or_C_vec(<4 x i1> %cond) { ; CHECK-LABEL: sel_Cminus1_or_C_vec: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vspltisw 3, -16 ; CHECK-NEXT: vspltisw 4, 15 ; CHECK-NEXT: addis 3, 2, .LCPI4_0@toc@ha @@ -91,7 +91,7 @@ define <4 x i32> @sel_Cminus1_or_C_vec(<4 x i1> %cond) { define <4 x i32> @cmp_sel_Cminus1_or_C_vec(<4 x i32> %x, <4 x i32> %y) { ; CHECK-LABEL: cmp_sel_Cminus1_or_C_vec: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vcmpequw 2, 2, 3 ; CHECK-NEXT: addis 3, 2, .LCPI5_0@toc@ha ; CHECK-NEXT: addi 3, 3, .LCPI5_0@toc@l @@ -105,7 +105,7 @@ define <4 x i32> @cmp_sel_Cminus1_or_C_vec(<4 x i32> %x, <4 x i32> %y) { define <4 x i32> @sel_minus1_or_0_vec(<4 x i1> %cond) { ; CHECK-LABEL: sel_minus1_or_0_vec: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vspltisw 3, -16 ; CHECK-NEXT: vspltisw 4, 15 ; CHECK-NEXT: vsubuwm 3, 4, 3 @@ -118,7 +118,7 @@ define <4 x i32> @sel_minus1_or_0_vec(<4 x i1> %cond) { define <4 x i32> @cmp_sel_minus1_or_0_vec(<4 x i32> %x, <4 x i32> %y) { ; CHECK-LABEL: cmp_sel_minus1_or_0_vec: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vcmpequw 2, 2, 3 ; CHECK-NEXT: blr %cond = icmp eq <4 x i32> %x, %y @@ -128,7 +128,7 @@ define <4 x i32> @cmp_sel_minus1_or_0_vec(<4 x i32> %x, <4 x i32> %y) { define <4 x i32> @sel_0_or_minus1_vec(<4 x i1> %cond) { ; CHECK-LABEL: sel_0_or_minus1_vec: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vspltisw 3, 1 ; CHECK-NEXT: vspltisb 4, -1 ; CHECK-NEXT: xxland 34, 34, 35 @@ -140,7 +140,7 @@ define <4 x i32> @sel_0_or_minus1_vec(<4 x i1> %cond) { define <4 x i32> @cmp_sel_0_or_minus1_vec(<4 x i32> %x, <4 x i32> %y) { ; CHECK-LABEL: cmp_sel_0_or_minus1_vec: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vcmpequw 2, 2, 3 ; CHECK-NEXT: xxlnor 34, 34, 34 ; CHECK-NEXT: blr @@ -151,7 +151,7 @@ define <4 x i32> @cmp_sel_0_or_minus1_vec(<4 x i32> %x, <4 x i32> %y) { define <4 x i32> @sel_1_or_0_vec(<4 x i1> %cond) { ; CHECK-LABEL: sel_1_or_0_vec: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vspltisw 3, 1 ; CHECK-NEXT: xxland 34, 34, 35 ; CHECK-NEXT: blr @@ -161,7 +161,7 @@ define <4 x i32> @sel_1_or_0_vec(<4 x i1> %cond) { define <4 x i32> @cmp_sel_1_or_0_vec(<4 x i32> %x, <4 x i32> %y) { ; CHECK-LABEL: cmp_sel_1_or_0_vec: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vcmpequw 2, 2, 3 ; CHECK-NEXT: vspltisw 19, 1 ; CHECK-NEXT: xxland 34, 34, 51 @@ -173,7 +173,7 @@ define <4 x i32> @cmp_sel_1_or_0_vec(<4 x i32> %x, <4 x i32> %y) { define <4 x i32> @sel_0_or_1_vec(<4 x i1> %cond) { ; CHECK-LABEL: sel_0_or_1_vec: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vspltisw 3, 1 ; CHECK-NEXT: xxlandc 34, 35, 34 ; CHECK-NEXT: blr @@ -183,7 +183,7 @@ define <4 x i32> @sel_0_or_1_vec(<4 x i1> %cond) { define <4 x i32> @cmp_sel_0_or_1_vec(<4 x i32> %x, <4 x i32> %y) { ; CHECK-LABEL: cmp_sel_0_or_1_vec: -; CHECK: # BB#0: +; CHECK: # %bb.0: ; CHECK-NEXT: vcmpequw 2, 2, 3 ; CHECK-NEXT: vspltisw 19, 1 ; CHECK-NEXT: xxlnor 0, 34, 34 diff --git a/test/CodeGen/RISCV/addc-adde-sube-subc.ll b/test/CodeGen/RISCV/addc-adde-sube-subc.ll index 50de47d7c1ffa..54f5482b9e74d 100644 --- a/test/CodeGen/RISCV/addc-adde-sube-subc.ll +++ b/test/CodeGen/RISCV/addc-adde-sube-subc.ll @@ -6,7 +6,7 @@ define i64 @addc_adde(i64 %a, i64 %b) { ; RV32I-LABEL: addc_adde: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: add a1, a1, a3 ; RV32I-NEXT: add a2, a0, a2 ; RV32I-NEXT: sltu a0, a2, a0 @@ -19,7 +19,7 @@ define i64 @addc_adde(i64 %a, i64 %b) { define i64 @subc_sube(i64 %a, i64 %b) { ; RV32I-LABEL: subc_sube: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: sub a1, a1, a3 ; RV32I-NEXT: sltu a3, a0, a2 ; RV32I-NEXT: sub a1, a1, a3 diff --git a/test/CodeGen/RISCV/alu32.ll b/test/CodeGen/RISCV/alu32.ll index 9aa6058c2a051..e7c8218102759 100644 --- a/test/CodeGen/RISCV/alu32.ll +++ b/test/CodeGen/RISCV/alu32.ll @@ -10,7 +10,7 @@ define i32 @addi(i32 %a) nounwind { ; RV32I-LABEL: addi: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: addi a0, a0, 1 ; RV32I-NEXT: jalr zero, ra, 0 %1 = add i32 %a, 1 @@ -19,7 +19,7 @@ define i32 @addi(i32 %a) nounwind { define i32 @slti(i32 %a) nounwind { ; RV32I-LABEL: slti: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: slti a0, a0, 2 ; RV32I-NEXT: jalr zero, ra, 0 %1 = icmp slt i32 %a, 2 @@ -29,7 +29,7 @@ define i32 @slti(i32 %a) nounwind { define i32 @sltiu(i32 %a) nounwind { ; RV32I-LABEL: sltiu: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: sltiu a0, a0, 3 ; RV32I-NEXT: jalr zero, ra, 0 %1 = icmp ult i32 %a, 3 @@ -39,7 +39,7 @@ define i32 @sltiu(i32 %a) nounwind { define i32 @xori(i32 %a) nounwind { ; RV32I-LABEL: xori: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: xori a0, a0, 4 ; RV32I-NEXT: jalr zero, ra, 0 %1 = xor i32 %a, 4 @@ -48,7 +48,7 @@ define i32 @xori(i32 %a) nounwind { define i32 @ori(i32 %a) nounwind { ; RV32I-LABEL: ori: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: ori a0, a0, 5 ; RV32I-NEXT: jalr zero, ra, 0 %1 = or i32 %a, 5 @@ -57,7 +57,7 @@ define i32 @ori(i32 %a) nounwind { define i32 @andi(i32 %a) nounwind { ; RV32I-LABEL: andi: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: andi a0, a0, 6 ; RV32I-NEXT: jalr zero, ra, 0 %1 = and i32 %a, 6 @@ -66,7 +66,7 @@ define i32 @andi(i32 %a) nounwind { define i32 @slli(i32 %a) nounwind { ; RV32I-LABEL: slli: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: slli a0, a0, 7 ; RV32I-NEXT: jalr zero, ra, 0 %1 = shl i32 %a, 7 @@ -75,7 +75,7 @@ define i32 @slli(i32 %a) nounwind { define i32 @srli(i32 %a) nounwind { ; RV32I-LABEL: srli: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: srli a0, a0, 8 ; RV32I-NEXT: jalr zero, ra, 0 %1 = lshr i32 %a, 8 @@ -84,7 +84,7 @@ define i32 @srli(i32 %a) nounwind { define i32 @srai(i32 %a) nounwind { ; RV32I-LABEL: srai: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: srai a0, a0, 9 ; RV32I-NEXT: jalr zero, ra, 0 %1 = ashr i32 %a, 9 @@ -95,7 +95,7 @@ define i32 @srai(i32 %a) nounwind { define i32 @add(i32 %a, i32 %b) nounwind { ; RV32I-LABEL: add: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: jalr zero, ra, 0 %1 = add i32 %a, %b @@ -104,7 +104,7 @@ define i32 @add(i32 %a, i32 %b) nounwind { define i32 @sub(i32 %a, i32 %b) nounwind { ; RV32I-LABEL: sub: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: sub a0, a0, a1 ; RV32I-NEXT: jalr zero, ra, 0 %1 = sub i32 %a, %b @@ -113,7 +113,7 @@ define i32 @sub(i32 %a, i32 %b) nounwind { define i32 @sll(i32 %a, i32 %b) nounwind { ; RV32I-LABEL: sll: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: sll a0, a0, a1 ; RV32I-NEXT: jalr zero, ra, 0 %1 = shl i32 %a, %b @@ -122,7 +122,7 @@ define i32 @sll(i32 %a, i32 %b) nounwind { define i32 @slt(i32 %a, i32 %b) nounwind { ; RV32I-LABEL: slt: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: slt a0, a0, a1 ; RV32I-NEXT: jalr zero, ra, 0 %1 = icmp slt i32 %a, %b @@ -132,7 +132,7 @@ define i32 @slt(i32 %a, i32 %b) nounwind { define i32 @sltu(i32 %a, i32 %b) nounwind { ; RV32I-LABEL: sltu: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: sltu a0, a0, a1 ; RV32I-NEXT: jalr zero, ra, 0 %1 = icmp ult i32 %a, %b @@ -142,7 +142,7 @@ define i32 @sltu(i32 %a, i32 %b) nounwind { define i32 @xor(i32 %a, i32 %b) nounwind { ; RV32I-LABEL: xor: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: xor a0, a0, a1 ; RV32I-NEXT: jalr zero, ra, 0 %1 = xor i32 %a, %b @@ -151,7 +151,7 @@ define i32 @xor(i32 %a, i32 %b) nounwind { define i32 @srl(i32 %a, i32 %b) nounwind { ; RV32I-LABEL: srl: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: srl a0, a0, a1 ; RV32I-NEXT: jalr zero, ra, 0 %1 = lshr i32 %a, %b @@ -160,7 +160,7 @@ define i32 @srl(i32 %a, i32 %b) nounwind { define i32 @sra(i32 %a, i32 %b) nounwind { ; RV32I-LABEL: sra: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: sra a0, a0, a1 ; RV32I-NEXT: jalr zero, ra, 0 %1 = ashr i32 %a, %b @@ -169,7 +169,7 @@ define i32 @sra(i32 %a, i32 %b) nounwind { define i32 @or(i32 %a, i32 %b) nounwind { ; RV32I-LABEL: or: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: jalr zero, ra, 0 %1 = or i32 %a, %b @@ -178,7 +178,7 @@ define i32 @or(i32 %a, i32 %b) nounwind { define i32 @and(i32 %a, i32 %b) nounwind { ; RV32I-LABEL: and: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: jalr zero, ra, 0 %1 = and i32 %a, %b diff --git a/test/CodeGen/RISCV/bare-select.ll b/test/CodeGen/RISCV/bare-select.ll index ec98b6d18b215..a46afe27143ca 100644 --- a/test/CodeGen/RISCV/bare-select.ll +++ b/test/CodeGen/RISCV/bare-select.ll @@ -4,10 +4,10 @@ define i32 @bare_select(i1 %a, i32 %b, i32 %c) { ; RV32I-LABEL: bare_select: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: andi a0, a0, 1 ; RV32I-NEXT: bne a0, zero, .LBB0_2 -; RV32I-NEXT: # BB#1: +; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: addi a1, a2, 0 ; RV32I-NEXT: .LBB0_2: ; RV32I-NEXT: addi a0, a1, 0 diff --git a/test/CodeGen/RISCV/blockaddress.ll b/test/CodeGen/RISCV/blockaddress.ll index f51598ff5a7c8..9eb4e3d404d14 100644 --- a/test/CodeGen/RISCV/blockaddress.ll +++ b/test/CodeGen/RISCV/blockaddress.ll @@ -6,7 +6,7 @@ define void @test_blockaddress() nounwind { ; RV32I-LABEL: test_blockaddress: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: sw ra, 0(s0) ; RV32I-NEXT: lui a0, %hi(addr) ; RV32I-NEXT: addi a0, a0, %lo(addr) diff --git a/test/CodeGen/RISCV/branch.ll b/test/CodeGen/RISCV/branch.ll index 194083b07c71a..e2593d3309b35 100644 --- a/test/CodeGen/RISCV/branch.ll +++ b/test/CodeGen/RISCV/branch.ll @@ -4,7 +4,7 @@ define void @foo(i32 %a, i32 *%b, i1 %c) { ; RV32I-LABEL: foo: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: lw a3, 0(a1) ; RV32I-NEXT: beq a3, a0, .LBB0_12 ; RV32I-NEXT: jal zero, .LBB0_1 diff --git a/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll b/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll index 6521f66cf6a4f..150dfed357356 100644 --- a/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll +++ b/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll @@ -14,7 +14,7 @@ declare i32 @llvm.ctpop.i32(i32) define i16 @test_bswap_i16(i16 %a) nounwind { ; RV32I-LABEL: test_bswap_i16: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: lui a1, 4080 ; RV32I-NEXT: addi a1, a1, 0 ; RV32I-NEXT: slli a2, a0, 8 @@ -29,7 +29,7 @@ define i16 @test_bswap_i16(i16 %a) nounwind { define i32 @test_bswap_i32(i32 %a) nounwind { ; RV32I-LABEL: test_bswap_i32: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: lui a1, 16 ; RV32I-NEXT: addi a1, a1, -256 ; RV32I-NEXT: srli a2, a0, 8 @@ -50,7 +50,7 @@ define i32 @test_bswap_i32(i32 %a) nounwind { define i64 @test_bswap_i64(i64 %a) nounwind { ; RV32I-LABEL: test_bswap_i64: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: lui a2, 16 ; RV32I-NEXT: addi a3, a2, -256 ; RV32I-NEXT: srli a2, a1, 8 @@ -81,7 +81,7 @@ define i64 @test_bswap_i64(i64 %a) nounwind { define i8 @test_cttz_i8(i8 %a) nounwind { ; RV32I-LABEL: test_cttz_i8: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: sw ra, 12(s0) ; RV32I-NEXT: addi a1, a0, 0 ; RV32I-NEXT: addi a0, zero, 8 @@ -123,7 +123,7 @@ define i8 @test_cttz_i8(i8 %a) nounwind { define i16 @test_cttz_i16(i16 %a) nounwind { ; RV32I-LABEL: test_cttz_i16: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: sw ra, 12(s0) ; RV32I-NEXT: addi a1, a0, 0 ; RV32I-NEXT: addi a0, zero, 16 @@ -167,7 +167,7 @@ define i16 @test_cttz_i16(i16 %a) nounwind { define i32 @test_cttz_i32(i32 %a) nounwind { ; RV32I-LABEL: test_cttz_i32: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: sw ra, 12(s0) ; RV32I-NEXT: addi a1, a0, 0 ; RV32I-NEXT: addi a0, zero, 32 @@ -208,7 +208,7 @@ define i32 @test_cttz_i32(i32 %a) nounwind { define i32 @test_ctlz_i32(i32 %a) nounwind { ; RV32I-LABEL: test_ctlz_i32: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: sw ra, 12(s0) ; RV32I-NEXT: addi a1, a0, 0 ; RV32I-NEXT: addi a0, zero, 32 @@ -257,7 +257,7 @@ define i32 @test_ctlz_i32(i32 %a) nounwind { define i64 @test_cttz_i64(i64 %a) nounwind { ; RV32I-LABEL: test_cttz_i64: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: sw ra, 28(s0) ; RV32I-NEXT: sw s1, 24(s0) ; RV32I-NEXT: sw s2, 20(s0) @@ -311,7 +311,7 @@ define i64 @test_cttz_i64(i64 %a) nounwind { ; RV32I-NEXT: addi a1, s3, 0 ; RV32I-NEXT: jalr ra, s6, 0 ; RV32I-NEXT: bne s2, zero, .LBB7_2 -; RV32I-NEXT: # BB#1: +; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: srli a0, a0, 24 ; RV32I-NEXT: addi s1, a0, 32 ; RV32I-NEXT: .LBB7_2: @@ -332,7 +332,7 @@ define i64 @test_cttz_i64(i64 %a) nounwind { define i8 @test_cttz_i8_zero_undef(i8 %a) nounwind { ; RV32I-LABEL: test_cttz_i8_zero_undef: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: sw ra, 12(s0) ; RV32I-NEXT: addi a1, a0, -1 ; RV32I-NEXT: xori a0, a0, -1 @@ -367,7 +367,7 @@ define i8 @test_cttz_i8_zero_undef(i8 %a) nounwind { define i16 @test_cttz_i16_zero_undef(i16 %a) nounwind { ; RV32I-LABEL: test_cttz_i16_zero_undef: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: sw ra, 12(s0) ; RV32I-NEXT: addi a1, a0, -1 ; RV32I-NEXT: xori a0, a0, -1 @@ -402,7 +402,7 @@ define i16 @test_cttz_i16_zero_undef(i16 %a) nounwind { define i32 @test_cttz_i32_zero_undef(i32 %a) nounwind { ; RV32I-LABEL: test_cttz_i32_zero_undef: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: sw ra, 12(s0) ; RV32I-NEXT: addi a1, a0, -1 ; RV32I-NEXT: xori a0, a0, -1 @@ -437,7 +437,7 @@ define i32 @test_cttz_i32_zero_undef(i32 %a) nounwind { define i64 @test_cttz_i64_zero_undef(i64 %a) nounwind { ; RV32I-LABEL: test_cttz_i64_zero_undef: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: sw ra, 28(s0) ; RV32I-NEXT: sw s1, 24(s0) ; RV32I-NEXT: sw s2, 20(s0) @@ -491,7 +491,7 @@ define i64 @test_cttz_i64_zero_undef(i64 %a) nounwind { ; RV32I-NEXT: addi a1, s3, 0 ; RV32I-NEXT: jalr ra, s6, 0 ; RV32I-NEXT: bne s2, zero, .LBB11_2 -; RV32I-NEXT: # BB#1: +; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: srli a0, a0, 24 ; RV32I-NEXT: addi s1, a0, 32 ; RV32I-NEXT: .LBB11_2: @@ -512,7 +512,7 @@ define i64 @test_cttz_i64_zero_undef(i64 %a) nounwind { define i32 @test_ctpop_i32(i32 %a) nounwind { ; RV32I-LABEL: test_ctpop_i32: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: sw ra, 12(s0) ; RV32I-NEXT: lui a1, 349525 ; RV32I-NEXT: addi a1, a1, 1365 diff --git a/test/CodeGen/RISCV/calls.ll b/test/CodeGen/RISCV/calls.ll index 8abe5e92a8e0d..77f612907059f 100644 --- a/test/CodeGen/RISCV/calls.ll +++ b/test/CodeGen/RISCV/calls.ll @@ -6,7 +6,7 @@ declare i32 @external_function(i32) define i32 @test_call_external(i32 %a) nounwind { ; RV32I-LABEL: test_call_external: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: sw ra, 12(s0) ; RV32I-NEXT: lui a1, %hi(external_function) ; RV32I-NEXT: addi a1, a1, %lo(external_function) @@ -19,7 +19,7 @@ define i32 @test_call_external(i32 %a) nounwind { define i32 @defined_function(i32 %a) nounwind { ; RV32I-LABEL: defined_function: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: addi a0, a0, 1 ; RV32I-NEXT: jalr zero, ra, 0 %1 = add i32 %a, 1 @@ -28,7 +28,7 @@ define i32 @defined_function(i32 %a) nounwind { define i32 @test_call_defined(i32 %a) nounwind { ; RV32I-LABEL: test_call_defined: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: sw ra, 12(s0) ; RV32I-NEXT: lui a1, %hi(defined_function) ; RV32I-NEXT: addi a1, a1, %lo(defined_function) @@ -41,7 +41,7 @@ define i32 @test_call_defined(i32 %a) nounwind { define i32 @test_call_indirect(i32 (i32)* %a, i32 %b) nounwind { ; RV32I-LABEL: test_call_indirect: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: sw ra, 12(s0) ; RV32I-NEXT: addi a2, a0, 0 ; RV32I-NEXT: addi a0, a1, 0 @@ -57,7 +57,7 @@ define i32 @test_call_indirect(i32 (i32)* %a, i32 %b) nounwind { define fastcc i32 @fastcc_function(i32 %a, i32 %b) nounwind { ; RV32I-LABEL: fastcc_function: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: jalr zero, ra, 0 %1 = add i32 %a, %b @@ -66,7 +66,7 @@ define fastcc i32 @fastcc_function(i32 %a, i32 %b) nounwind { define i32 @test_call_fastcc(i32 %a, i32 %b) nounwind { ; RV32I-LABEL: test_call_fastcc: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: sw ra, 12(s0) ; RV32I-NEXT: sw s1, 8(s0) ; RV32I-NEXT: addi s1, a0, 0 diff --git a/test/CodeGen/RISCV/div.ll b/test/CodeGen/RISCV/div.ll index 4c0f5de03583e..a53c51c94d882 100644 --- a/test/CodeGen/RISCV/div.ll +++ b/test/CodeGen/RISCV/div.ll @@ -4,7 +4,7 @@ define i32 @udiv(i32 %a, i32 %b) { ; RV32I-LABEL: udiv: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: sw ra, 12(s0) ; RV32I-NEXT: lui a2, %hi(__udivsi3) ; RV32I-NEXT: addi a2, a2, %lo(__udivsi3) @@ -17,7 +17,7 @@ define i32 @udiv(i32 %a, i32 %b) { define i32 @udiv_constant(i32 %a) { ; RV32I-LABEL: udiv_constant: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: sw ra, 12(s0) ; RV32I-NEXT: lui a1, %hi(__udivsi3) ; RV32I-NEXT: addi a2, a1, %lo(__udivsi3) @@ -31,7 +31,7 @@ define i32 @udiv_constant(i32 %a) { define i32 @udiv_pow2(i32 %a) { ; RV32I-LABEL: udiv_pow2: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: srli a0, a0, 3 ; RV32I-NEXT: jalr zero, ra, 0 %1 = udiv i32 %a, 8 @@ -40,7 +40,7 @@ define i32 @udiv_pow2(i32 %a) { define i64 @udiv64(i64 %a, i64 %b) { ; RV32I-LABEL: udiv64: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: sw ra, 12(s0) ; RV32I-NEXT: lui a4, %hi(__udivdi3) ; RV32I-NEXT: addi a4, a4, %lo(__udivdi3) @@ -53,7 +53,7 @@ define i64 @udiv64(i64 %a, i64 %b) { define i64 @udiv64_constant(i64 %a) { ; RV32I-LABEL: udiv64_constant: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: sw ra, 12(s0) ; RV32I-NEXT: lui a2, %hi(__udivdi3) ; RV32I-NEXT: addi a4, a2, %lo(__udivdi3) @@ -68,7 +68,7 @@ define i64 @udiv64_constant(i64 %a) { define i32 @sdiv(i32 %a, i32 %b) { ; RV32I-LABEL: sdiv: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: sw ra, 12(s0) ; RV32I-NEXT: lui a2, %hi(__divsi3) ; RV32I-NEXT: addi a2, a2, %lo(__divsi3) @@ -81,7 +81,7 @@ define i32 @sdiv(i32 %a, i32 %b) { define i32 @sdiv_constant(i32 %a) { ; RV32I-LABEL: sdiv_constant: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: sw ra, 12(s0) ; RV32I-NEXT: lui a1, %hi(__divsi3) ; RV32I-NEXT: addi a2, a1, %lo(__divsi3) @@ -95,7 +95,7 @@ define i32 @sdiv_constant(i32 %a) { define i32 @sdiv_pow2(i32 %a) { ; RV32I-LABEL: sdiv_pow2: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: srai a1, a0, 31 ; RV32I-NEXT: srli a1, a1, 29 ; RV32I-NEXT: add a0, a0, a1 @@ -107,7 +107,7 @@ define i32 @sdiv_pow2(i32 %a) { define i64 @sdiv64(i64 %a, i64 %b) { ; RV32I-LABEL: sdiv64: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: sw ra, 12(s0) ; RV32I-NEXT: lui a4, %hi(__divdi3) ; RV32I-NEXT: addi a4, a4, %lo(__divdi3) @@ -120,7 +120,7 @@ define i64 @sdiv64(i64 %a, i64 %b) { define i64 @sdiv64_constant(i64 %a) { ; RV32I-LABEL: sdiv64_constant: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: sw ra, 12(s0) ; RV32I-NEXT: lui a2, %hi(__divdi3) ; RV32I-NEXT: addi a4, a2, %lo(__divdi3) diff --git a/test/CodeGen/RISCV/i32-icmp.ll b/test/CodeGen/RISCV/i32-icmp.ll index 4d86ced2584a5..bc06ec805e9ef 100644 --- a/test/CodeGen/RISCV/i32-icmp.ll +++ b/test/CodeGen/RISCV/i32-icmp.ll @@ -7,7 +7,7 @@ define i32 @icmp_eq(i32 %a, i32 %b) nounwind { ; RV32I-LABEL: icmp_eq: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: xor a0, a0, a1 ; RV32I-NEXT: sltiu a0, a0, 1 ; RV32I-NEXT: jalr zero, ra, 0 @@ -18,7 +18,7 @@ define i32 @icmp_eq(i32 %a, i32 %b) nounwind { define i32 @icmp_ne(i32 %a, i32 %b) nounwind { ; RV32I-LABEL: icmp_ne: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: xor a0, a0, a1 ; RV32I-NEXT: sltu a0, zero, a0 ; RV32I-NEXT: jalr zero, ra, 0 @@ -29,7 +29,7 @@ define i32 @icmp_ne(i32 %a, i32 %b) nounwind { define i32 @icmp_ugt(i32 %a, i32 %b) nounwind { ; RV32I-LABEL: icmp_ugt: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: sltu a0, a1, a0 ; RV32I-NEXT: jalr zero, ra, 0 %1 = icmp ugt i32 %a, %b @@ -39,7 +39,7 @@ define i32 @icmp_ugt(i32 %a, i32 %b) nounwind { define i32 @icmp_uge(i32 %a, i32 %b) nounwind { ; RV32I-LABEL: icmp_uge: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: sltu a0, a0, a1 ; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: jalr zero, ra, 0 @@ -50,7 +50,7 @@ define i32 @icmp_uge(i32 %a, i32 %b) nounwind { define i32 @icmp_ult(i32 %a, i32 %b) nounwind { ; RV32I-LABEL: icmp_ult: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: sltu a0, a0, a1 ; RV32I-NEXT: jalr zero, ra, 0 %1 = icmp ult i32 %a, %b @@ -60,7 +60,7 @@ define i32 @icmp_ult(i32 %a, i32 %b) nounwind { define i32 @icmp_ule(i32 %a, i32 %b) nounwind { ; RV32I-LABEL: icmp_ule: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: sltu a0, a1, a0 ; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: jalr zero, ra, 0 @@ -71,7 +71,7 @@ define i32 @icmp_ule(i32 %a, i32 %b) nounwind { define i32 @icmp_sgt(i32 %a, i32 %b) nounwind { ; RV32I-LABEL: icmp_sgt: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: slt a0, a1, a0 ; RV32I-NEXT: jalr zero, ra, 0 %1 = icmp sgt i32 %a, %b @@ -81,7 +81,7 @@ define i32 @icmp_sgt(i32 %a, i32 %b) nounwind { define i32 @icmp_sge(i32 %a, i32 %b) nounwind { ; RV32I-LABEL: icmp_sge: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: slt a0, a0, a1 ; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: jalr zero, ra, 0 @@ -92,7 +92,7 @@ define i32 @icmp_sge(i32 %a, i32 %b) nounwind { define i32 @icmp_slt(i32 %a, i32 %b) nounwind { ; RV32I-LABEL: icmp_slt: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: slt a0, a0, a1 ; RV32I-NEXT: jalr zero, ra, 0 %1 = icmp slt i32 %a, %b @@ -102,7 +102,7 @@ define i32 @icmp_slt(i32 %a, i32 %b) nounwind { define i32 @icmp_sle(i32 %a, i32 %b) nounwind { ; RV32I-LABEL: icmp_sle: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: slt a0, a1, a0 ; RV32I-NEXT: xori a0, a0, 1 ; RV32I-NEXT: jalr zero, ra, 0 diff --git a/test/CodeGen/RISCV/imm.ll b/test/CodeGen/RISCV/imm.ll index c52638da02eb0..ddefa22835aee 100644 --- a/test/CodeGen/RISCV/imm.ll +++ b/test/CodeGen/RISCV/imm.ll @@ -6,7 +6,7 @@ define i32 @zero() nounwind { ; RV32I-LABEL: zero: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: addi a0, zero, 0 ; RV32I-NEXT: jalr zero, ra, 0 ret i32 0 @@ -14,7 +14,7 @@ define i32 @zero() nounwind { define i32 @pos_small() nounwind { ; RV32I-LABEL: pos_small: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: addi a0, zero, 2047 ; RV32I-NEXT: jalr zero, ra, 0 ret i32 2047 @@ -22,7 +22,7 @@ define i32 @pos_small() nounwind { define i32 @neg_small() nounwind { ; RV32I-LABEL: neg_small: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: addi a0, zero, -2048 ; RV32I-NEXT: jalr zero, ra, 0 ret i32 -2048 @@ -30,7 +30,7 @@ define i32 @neg_small() nounwind { define i32 @pos_i32() nounwind { ; RV32I-LABEL: pos_i32: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: lui a0, 423811 ; RV32I-NEXT: addi a0, a0, -1297 ; RV32I-NEXT: jalr zero, ra, 0 @@ -39,7 +39,7 @@ define i32 @pos_i32() nounwind { define i32 @neg_i32() nounwind { ; RV32I-LABEL: neg_i32: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: lui a0, 912092 ; RV32I-NEXT: addi a0, a0, -273 ; RV32I-NEXT: jalr zero, ra, 0 diff --git a/test/CodeGen/RISCV/indirectbr.ll b/test/CodeGen/RISCV/indirectbr.ll index 0a51e3d0b2efe..40641da6d6f2e 100644 --- a/test/CodeGen/RISCV/indirectbr.ll +++ b/test/CodeGen/RISCV/indirectbr.ll @@ -4,7 +4,7 @@ define i32 @indirectbr(i8* %target) nounwind { ; RV32I-LABEL: indirectbr: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: sw ra, 0(s0) ; RV32I-NEXT: jalr zero, a0, 0 ; RV32I-NEXT: .LBB0_1: # %ret @@ -20,7 +20,7 @@ ret: define i32 @indirectbr_with_offset(i8* %a) nounwind { ; RV32I-LABEL: indirectbr_with_offset: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: sw ra, 0(s0) ; RV32I-NEXT: jalr zero, a0, 1380 ; RV32I-NEXT: .LBB1_1: # %ret diff --git a/test/CodeGen/RISCV/jumptable.ll b/test/CodeGen/RISCV/jumptable.ll index 98144c7c1e643..68f4f1cb72192 100644 --- a/test/CodeGen/RISCV/jumptable.ll +++ b/test/CodeGen/RISCV/jumptable.ll @@ -4,7 +4,7 @@ define void @jt(i32 %in, i32* %out) { ; RV32I-LABEL: jt: -; RV32I: # BB#0: # %entry +; RV32I: # %bb.0: # %entry ; RV32I-NEXT: addi a2, zero, 2 ; RV32I-NEXT: blt a2, a0, .LBB0_3 ; RV32I-NEXT: jal zero, .LBB0_1 diff --git a/test/CodeGen/RISCV/mem.ll b/test/CodeGen/RISCV/mem.ll index b06382f8742aa..6446034e542ae 100644 --- a/test/CodeGen/RISCV/mem.ll +++ b/test/CodeGen/RISCV/mem.ll @@ -6,7 +6,7 @@ define i32 @lb(i8 *%a) nounwind { ; RV32I-LABEL: lb: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: lb a1, 0(a0) ; RV32I-NEXT: lb a0, 1(a0) ; RV32I-NEXT: jalr zero, ra, 0 @@ -20,7 +20,7 @@ define i32 @lb(i8 *%a) nounwind { define i32 @lh(i16 *%a) nounwind { ; RV32I-LABEL: lh: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: lh a1, 0(a0) ; RV32I-NEXT: lh a0, 4(a0) ; RV32I-NEXT: jalr zero, ra, 0 @@ -34,7 +34,7 @@ define i32 @lh(i16 *%a) nounwind { define i32 @lw(i32 *%a) nounwind { ; RV32I-LABEL: lw: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: lw a1, 0(a0) ; RV32I-NEXT: lw a0, 12(a0) ; RV32I-NEXT: jalr zero, ra, 0 @@ -46,7 +46,7 @@ define i32 @lw(i32 *%a) nounwind { define i32 @lbu(i8 *%a) nounwind { ; RV32I-LABEL: lbu: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: lbu a1, 0(a0) ; RV32I-NEXT: lbu a0, 4(a0) ; RV32I-NEXT: add a0, a0, a1 @@ -62,7 +62,7 @@ define i32 @lbu(i8 *%a) nounwind { define i32 @lhu(i16 *%a) nounwind { ; RV32I-LABEL: lhu: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: lhu a1, 0(a0) ; RV32I-NEXT: lhu a0, 10(a0) ; RV32I-NEXT: add a0, a0, a1 @@ -80,7 +80,7 @@ define i32 @lhu(i16 *%a) nounwind { define void @sb(i8 *%a, i8 %b) nounwind { ; RV32I-LABEL: sb: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: sb a1, 6(a0) ; RV32I-NEXT: sb a1, 0(a0) ; RV32I-NEXT: jalr zero, ra, 0 @@ -92,7 +92,7 @@ define void @sb(i8 *%a, i8 %b) nounwind { define void @sh(i16 *%a, i16 %b) nounwind { ; RV32I-LABEL: sh: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: sh a1, 14(a0) ; RV32I-NEXT: sh a1, 0(a0) ; RV32I-NEXT: jalr zero, ra, 0 @@ -104,7 +104,7 @@ define void @sh(i16 *%a, i16 %b) nounwind { define void @sw(i32 *%a, i32 %b) nounwind { ; RV32I-LABEL: sw: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: sw a1, 32(a0) ; RV32I-NEXT: sw a1, 0(a0) ; RV32I-NEXT: jalr zero, ra, 0 @@ -117,7 +117,7 @@ define void @sw(i32 *%a, i32 %b) nounwind { ; Check load and store to an i1 location define i32 @load_sext_zext_anyext_i1(i1 *%a) nounwind { ; RV32I-LABEL: load_sext_zext_anyext_i1: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: lb a1, 0(a0) ; RV32I-NEXT: lbu a1, 1(a0) ; RV32I-NEXT: lbu a0, 2(a0) @@ -139,7 +139,7 @@ define i32 @load_sext_zext_anyext_i1(i1 *%a) nounwind { define i16 @load_sext_zext_anyext_i1_i16(i1 *%a) nounwind { ; RV32I-LABEL: load_sext_zext_anyext_i1_i16: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: lb a1, 0(a0) ; RV32I-NEXT: lbu a1, 1(a0) ; RV32I-NEXT: lbu a0, 2(a0) @@ -165,7 +165,7 @@ define i16 @load_sext_zext_anyext_i1_i16(i1 *%a) nounwind { define i32 @lw_sw_global(i32 %a) nounwind { ; TODO: the addi should be folded in to the lw/sw operations ; RV32I-LABEL: lw_sw_global: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: lui a1, %hi(G) ; RV32I-NEXT: addi a2, a1, %lo(G) ; RV32I-NEXT: lw a1, 0(a2) @@ -188,7 +188,7 @@ define i32 @lw_sw_global(i32 %a) nounwind { define i32 @lw_sw_constant(i32 %a) nounwind { ; TODO: the addi should be folded in to the lw/sw ; RV32I-LABEL: lw_sw_constant: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: lui a1, 912092 ; RV32I-NEXT: addi a2, a1, -273 ; RV32I-NEXT: lw a1, 0(a2) diff --git a/test/CodeGen/RISCV/mul.ll b/test/CodeGen/RISCV/mul.ll index 41653256debb3..2eb5db79d1b7d 100644 --- a/test/CodeGen/RISCV/mul.ll +++ b/test/CodeGen/RISCV/mul.ll @@ -4,7 +4,7 @@ define i32 @square(i32 %a) { ; RV32I-LABEL: square: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: sw ra, 12(s0) ; RV32I-NEXT: lui a1, %hi(__mulsi3) ; RV32I-NEXT: addi a2, a1, %lo(__mulsi3) @@ -18,7 +18,7 @@ define i32 @square(i32 %a) { define i32 @mul(i32 %a, i32 %b) { ; RV32I-LABEL: mul: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: sw ra, 12(s0) ; RV32I-NEXT: lui a2, %hi(__mulsi3) ; RV32I-NEXT: addi a2, a2, %lo(__mulsi3) @@ -31,7 +31,7 @@ define i32 @mul(i32 %a, i32 %b) { define i32 @mul_constant(i32 %a) { ; RV32I-LABEL: mul_constant: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: sw ra, 12(s0) ; RV32I-NEXT: lui a1, %hi(__mulsi3) ; RV32I-NEXT: addi a2, a1, %lo(__mulsi3) @@ -45,7 +45,7 @@ define i32 @mul_constant(i32 %a) { define i32 @mul_pow2(i32 %a) { ; RV32I-LABEL: mul_pow2: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: slli a0, a0, 3 ; RV32I-NEXT: jalr zero, ra, 0 %1 = mul i32 %a, 8 @@ -54,7 +54,7 @@ define i32 @mul_pow2(i32 %a) { define i64 @mul64(i64 %a, i64 %b) { ; RV32I-LABEL: mul64: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: sw ra, 12(s0) ; RV32I-NEXT: lui a4, %hi(__muldi3) ; RV32I-NEXT: addi a4, a4, %lo(__muldi3) @@ -67,7 +67,7 @@ define i64 @mul64(i64 %a, i64 %b) { define i64 @mul64_constant(i64 %a) { ; RV32I-LABEL: mul64_constant: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: sw ra, 12(s0) ; RV32I-NEXT: lui a2, %hi(__muldi3) ; RV32I-NEXT: addi a4, a2, %lo(__muldi3) diff --git a/test/CodeGen/RISCV/rem.ll b/test/CodeGen/RISCV/rem.ll index 80f79817b742b..c9e2a90521d1f 100644 --- a/test/CodeGen/RISCV/rem.ll +++ b/test/CodeGen/RISCV/rem.ll @@ -4,7 +4,7 @@ define i32 @urem(i32 %a, i32 %b) nounwind { ; RV32I-LABEL: urem: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: sw ra, 12(s0) ; RV32I-NEXT: lui a2, %hi(__umodsi3) ; RV32I-NEXT: addi a2, a2, %lo(__umodsi3) @@ -17,7 +17,7 @@ define i32 @urem(i32 %a, i32 %b) nounwind { define i32 @srem(i32 %a, i32 %b) nounwind { ; RV32I-LABEL: srem: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: sw ra, 12(s0) ; RV32I-NEXT: lui a2, %hi(__modsi3) ; RV32I-NEXT: addi a2, a2, %lo(__modsi3) diff --git a/test/CodeGen/RISCV/rotl-rotr.ll b/test/CodeGen/RISCV/rotl-rotr.ll index bf0689feafab2..b2331051fcdca 100644 --- a/test/CodeGen/RISCV/rotl-rotr.ll +++ b/test/CodeGen/RISCV/rotl-rotr.ll @@ -7,7 +7,7 @@ define i32 @rotl(i32 %x, i32 %y) { ; RV32I-LABEL: rotl: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: addi a2, zero, 32 ; RV32I-NEXT: sub a2, a2, a1 ; RV32I-NEXT: sll a1, a0, a1 @@ -23,7 +23,7 @@ define i32 @rotl(i32 %x, i32 %y) { define i32 @rotr(i32 %x, i32 %y) { ; RV32I-LABEL: rotr: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: addi a2, zero, 32 ; RV32I-NEXT: sub a2, a2, a1 ; RV32I-NEXT: srl a1, a0, a1 diff --git a/test/CodeGen/RISCV/select-cc.ll b/test/CodeGen/RISCV/select-cc.ll index c1a570c5c9812..ddc5983525eee 100644 --- a/test/CodeGen/RISCV/select-cc.ll +++ b/test/CodeGen/RISCV/select-cc.ll @@ -4,55 +4,55 @@ define i32 @foo(i32 %a, i32 *%b) { ; RV32I-LABEL: foo: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: lw a2, 0(a1) ; RV32I-NEXT: beq a0, a2, .LBB0_2 -; RV32I-NEXT: # BB#1: +; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: addi a0, a2, 0 ; RV32I-NEXT: .LBB0_2: ; RV32I-NEXT: lw a2, 0(a1) ; RV32I-NEXT: bne a0, a2, .LBB0_4 -; RV32I-NEXT: # BB#3: +; RV32I-NEXT: # %bb.3: ; RV32I-NEXT: addi a0, a2, 0 ; RV32I-NEXT: .LBB0_4: ; RV32I-NEXT: lw a2, 0(a1) ; RV32I-NEXT: bltu a2, a0, .LBB0_6 -; RV32I-NEXT: # BB#5: +; RV32I-NEXT: # %bb.5: ; RV32I-NEXT: addi a0, a2, 0 ; RV32I-NEXT: .LBB0_6: ; RV32I-NEXT: lw a2, 0(a1) ; RV32I-NEXT: bgeu a0, a2, .LBB0_8 -; RV32I-NEXT: # BB#7: +; RV32I-NEXT: # %bb.7: ; RV32I-NEXT: addi a0, a2, 0 ; RV32I-NEXT: .LBB0_8: ; RV32I-NEXT: lw a2, 0(a1) ; RV32I-NEXT: bltu a0, a2, .LBB0_10 -; RV32I-NEXT: # BB#9: +; RV32I-NEXT: # %bb.9: ; RV32I-NEXT: addi a0, a2, 0 ; RV32I-NEXT: .LBB0_10: ; RV32I-NEXT: lw a2, 0(a1) ; RV32I-NEXT: bgeu a2, a0, .LBB0_12 -; RV32I-NEXT: # BB#11: +; RV32I-NEXT: # %bb.11: ; RV32I-NEXT: addi a0, a2, 0 ; RV32I-NEXT: .LBB0_12: ; RV32I-NEXT: lw a2, 0(a1) ; RV32I-NEXT: blt a2, a0, .LBB0_14 -; RV32I-NEXT: # BB#13: +; RV32I-NEXT: # %bb.13: ; RV32I-NEXT: addi a0, a2, 0 ; RV32I-NEXT: .LBB0_14: ; RV32I-NEXT: lw a2, 0(a1) ; RV32I-NEXT: bge a0, a2, .LBB0_16 -; RV32I-NEXT: # BB#15: +; RV32I-NEXT: # %bb.15: ; RV32I-NEXT: addi a0, a2, 0 ; RV32I-NEXT: .LBB0_16: ; RV32I-NEXT: lw a2, 0(a1) ; RV32I-NEXT: blt a0, a2, .LBB0_18 -; RV32I-NEXT: # BB#17: +; RV32I-NEXT: # %bb.17: ; RV32I-NEXT: addi a0, a2, 0 ; RV32I-NEXT: .LBB0_18: ; RV32I-NEXT: lw a1, 0(a1) ; RV32I-NEXT: bge a1, a0, .LBB0_20 -; RV32I-NEXT: # BB#19: +; RV32I-NEXT: # %bb.19: ; RV32I-NEXT: addi a0, a1, 0 ; RV32I-NEXT: .LBB0_20: ; RV32I-NEXT: jalr zero, ra, 0 diff --git a/test/CodeGen/RISCV/sext-zext-trunc.ll b/test/CodeGen/RISCV/sext-zext-trunc.ll index 7c5f1205b760b..80bd2d2b20402 100644 --- a/test/CodeGen/RISCV/sext-zext-trunc.ll +++ b/test/CodeGen/RISCV/sext-zext-trunc.ll @@ -4,7 +4,7 @@ define i8 @sext_i1_to_i8(i1 %a) { ; RV32I-LABEL: sext_i1_to_i8: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: andi a0, a0, 1 ; RV32I-NEXT: sub a0, zero, a0 ; RV32I-NEXT: jalr zero, ra, 0 @@ -14,7 +14,7 @@ define i8 @sext_i1_to_i8(i1 %a) { define i16 @sext_i1_to_i16(i1 %a) { ; RV32I-LABEL: sext_i1_to_i16: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: andi a0, a0, 1 ; RV32I-NEXT: sub a0, zero, a0 ; RV32I-NEXT: jalr zero, ra, 0 @@ -24,7 +24,7 @@ define i16 @sext_i1_to_i16(i1 %a) { define i32 @sext_i1_to_i32(i1 %a) { ; RV32I-LABEL: sext_i1_to_i32: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: andi a0, a0, 1 ; RV32I-NEXT: sub a0, zero, a0 ; RV32I-NEXT: jalr zero, ra, 0 @@ -34,7 +34,7 @@ define i32 @sext_i1_to_i32(i1 %a) { define i64 @sext_i1_to_i64(i1 %a) { ; RV32I-LABEL: sext_i1_to_i64: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: andi a0, a0, 1 ; RV32I-NEXT: sub a0, zero, a0 ; RV32I-NEXT: addi a1, a0, 0 @@ -45,7 +45,7 @@ define i64 @sext_i1_to_i64(i1 %a) { define i16 @sext_i8_to_i16(i8 %a) { ; RV32I-LABEL: sext_i8_to_i16: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: slli a0, a0, 24 ; RV32I-NEXT: srai a0, a0, 24 ; RV32I-NEXT: jalr zero, ra, 0 @@ -55,7 +55,7 @@ define i16 @sext_i8_to_i16(i8 %a) { define i32 @sext_i8_to_i32(i8 %a) { ; RV32I-LABEL: sext_i8_to_i32: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: slli a0, a0, 24 ; RV32I-NEXT: srai a0, a0, 24 ; RV32I-NEXT: jalr zero, ra, 0 @@ -65,7 +65,7 @@ define i32 @sext_i8_to_i32(i8 %a) { define i64 @sext_i8_to_i64(i8 %a) { ; RV32I-LABEL: sext_i8_to_i64: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: slli a1, a0, 24 ; RV32I-NEXT: srai a0, a1, 24 ; RV32I-NEXT: srai a1, a1, 31 @@ -76,7 +76,7 @@ define i64 @sext_i8_to_i64(i8 %a) { define i32 @sext_i16_to_i32(i16 %a) { ; RV32I-LABEL: sext_i16_to_i32: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: slli a0, a0, 16 ; RV32I-NEXT: srai a0, a0, 16 ; RV32I-NEXT: jalr zero, ra, 0 @@ -86,7 +86,7 @@ define i32 @sext_i16_to_i32(i16 %a) { define i64 @sext_i16_to_i64(i16 %a) { ; RV32I-LABEL: sext_i16_to_i64: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: slli a1, a0, 16 ; RV32I-NEXT: srai a0, a1, 16 ; RV32I-NEXT: srai a1, a1, 31 @@ -97,7 +97,7 @@ define i64 @sext_i16_to_i64(i16 %a) { define i64 @sext_i32_to_i64(i32 %a) { ; RV32I-LABEL: sext_i32_to_i64: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: srai a1, a0, 31 ; RV32I-NEXT: jalr zero, ra, 0 %1 = sext i32 %a to i64 @@ -106,7 +106,7 @@ define i64 @sext_i32_to_i64(i32 %a) { define i8 @zext_i1_to_i8(i1 %a) { ; RV32I-LABEL: zext_i1_to_i8: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: andi a0, a0, 1 ; RV32I-NEXT: jalr zero, ra, 0 %1 = zext i1 %a to i8 @@ -115,7 +115,7 @@ define i8 @zext_i1_to_i8(i1 %a) { define i16 @zext_i1_to_i16(i1 %a) { ; RV32I-LABEL: zext_i1_to_i16: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: andi a0, a0, 1 ; RV32I-NEXT: jalr zero, ra, 0 %1 = zext i1 %a to i16 @@ -124,7 +124,7 @@ define i16 @zext_i1_to_i16(i1 %a) { define i32 @zext_i1_to_i32(i1 %a) { ; RV32I-LABEL: zext_i1_to_i32: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: andi a0, a0, 1 ; RV32I-NEXT: jalr zero, ra, 0 %1 = zext i1 %a to i32 @@ -133,7 +133,7 @@ define i32 @zext_i1_to_i32(i1 %a) { define i64 @zext_i1_to_i64(i1 %a) { ; RV32I-LABEL: zext_i1_to_i64: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: andi a0, a0, 1 ; RV32I-NEXT: addi a1, zero, 0 ; RV32I-NEXT: jalr zero, ra, 0 @@ -143,7 +143,7 @@ define i64 @zext_i1_to_i64(i1 %a) { define i16 @zext_i8_to_i16(i8 %a) { ; RV32I-LABEL: zext_i8_to_i16: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: andi a0, a0, 255 ; RV32I-NEXT: jalr zero, ra, 0 %1 = zext i8 %a to i16 @@ -152,7 +152,7 @@ define i16 @zext_i8_to_i16(i8 %a) { define i32 @zext_i8_to_i32(i8 %a) { ; RV32I-LABEL: zext_i8_to_i32: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: andi a0, a0, 255 ; RV32I-NEXT: jalr zero, ra, 0 %1 = zext i8 %a to i32 @@ -161,7 +161,7 @@ define i32 @zext_i8_to_i32(i8 %a) { define i64 @zext_i8_to_i64(i8 %a) { ; RV32I-LABEL: zext_i8_to_i64: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: andi a0, a0, 255 ; RV32I-NEXT: addi a1, zero, 0 ; RV32I-NEXT: jalr zero, ra, 0 @@ -171,7 +171,7 @@ define i64 @zext_i8_to_i64(i8 %a) { define i32 @zext_i16_to_i32(i16 %a) { ; RV32I-LABEL: zext_i16_to_i32: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: lui a1, 16 ; RV32I-NEXT: addi a1, a1, -1 ; RV32I-NEXT: and a0, a0, a1 @@ -182,7 +182,7 @@ define i32 @zext_i16_to_i32(i16 %a) { define i64 @zext_i16_to_i64(i16 %a) { ; RV32I-LABEL: zext_i16_to_i64: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: lui a1, 16 ; RV32I-NEXT: addi a1, a1, -1 ; RV32I-NEXT: and a0, a0, a1 @@ -194,7 +194,7 @@ define i64 @zext_i16_to_i64(i16 %a) { define i64 @zext_i32_to_i64(i32 %a) { ; RV32I-LABEL: zext_i32_to_i64: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: addi a1, zero, 0 ; RV32I-NEXT: jalr zero, ra, 0 %1 = zext i32 %a to i64 @@ -206,7 +206,7 @@ define i64 @zext_i32_to_i64(i32 %a) { define i1 @trunc_i8_to_i1(i8 %a) { ; RV32I-LABEL: trunc_i8_to_i1: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: jalr zero, ra, 0 %1 = trunc i8 %a to i1 ret i1 %1 @@ -214,7 +214,7 @@ define i1 @trunc_i8_to_i1(i8 %a) { define i1 @trunc_i16_to_i1(i16 %a) { ; RV32I-LABEL: trunc_i16_to_i1: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: jalr zero, ra, 0 %1 = trunc i16 %a to i1 ret i1 %1 @@ -222,7 +222,7 @@ define i1 @trunc_i16_to_i1(i16 %a) { define i1 @trunc_i32_to_i1(i32 %a) { ; RV32I-LABEL: trunc_i32_to_i1: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: jalr zero, ra, 0 %1 = trunc i32 %a to i1 ret i1 %1 @@ -230,7 +230,7 @@ define i1 @trunc_i32_to_i1(i32 %a) { define i1 @trunc_i64_to_i1(i64 %a) { ; RV32I-LABEL: trunc_i64_to_i1: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: jalr zero, ra, 0 %1 = trunc i64 %a to i1 ret i1 %1 @@ -238,7 +238,7 @@ define i1 @trunc_i64_to_i1(i64 %a) { define i8 @trunc_i16_to_i8(i16 %a) { ; RV32I-LABEL: trunc_i16_to_i8: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: jalr zero, ra, 0 %1 = trunc i16 %a to i8 ret i8 %1 @@ -246,7 +246,7 @@ define i8 @trunc_i16_to_i8(i16 %a) { define i8 @trunc_i32_to_i8(i32 %a) { ; RV32I-LABEL: trunc_i32_to_i8: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: jalr zero, ra, 0 %1 = trunc i32 %a to i8 ret i8 %1 @@ -254,7 +254,7 @@ define i8 @trunc_i32_to_i8(i32 %a) { define i8 @trunc_i64_to_i8(i64 %a) { ; RV32I-LABEL: trunc_i64_to_i8: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: jalr zero, ra, 0 %1 = trunc i64 %a to i8 ret i8 %1 @@ -262,7 +262,7 @@ define i8 @trunc_i64_to_i8(i64 %a) { define i16 @trunc_i32_to_i16(i32 %a) { ; RV32I-LABEL: trunc_i32_to_i16: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: jalr zero, ra, 0 %1 = trunc i32 %a to i16 ret i16 %1 @@ -270,7 +270,7 @@ define i16 @trunc_i32_to_i16(i32 %a) { define i16 @trunc_i64_to_i16(i64 %a) { ; RV32I-LABEL: trunc_i64_to_i16: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: jalr zero, ra, 0 %1 = trunc i64 %a to i16 ret i16 %1 @@ -278,7 +278,7 @@ define i16 @trunc_i64_to_i16(i64 %a) { define i32 @trunc_i64_to_i32(i64 %a) { ; RV32I-LABEL: trunc_i64_to_i32: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: jalr zero, ra, 0 %1 = trunc i64 %a to i32 ret i32 %1 diff --git a/test/CodeGen/RISCV/shifts.ll b/test/CodeGen/RISCV/shifts.ll index d773a6ad62ab0..c4033c574efe8 100644 --- a/test/CodeGen/RISCV/shifts.ll +++ b/test/CodeGen/RISCV/shifts.ll @@ -7,7 +7,7 @@ define i64 @lshr64(i64 %a, i64 %b) nounwind { ; RV32I-LABEL: lshr64: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: sw ra, 12(s0) ; RV32I-NEXT: lui a3, %hi(__lshrdi3) ; RV32I-NEXT: addi a3, a3, %lo(__lshrdi3) @@ -20,7 +20,7 @@ define i64 @lshr64(i64 %a, i64 %b) nounwind { define i64 @ashr64(i64 %a, i64 %b) nounwind { ; RV32I-LABEL: ashr64: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: sw ra, 12(s0) ; RV32I-NEXT: lui a3, %hi(__ashrdi3) ; RV32I-NEXT: addi a3, a3, %lo(__ashrdi3) @@ -33,7 +33,7 @@ define i64 @ashr64(i64 %a, i64 %b) nounwind { define i64 @shl64(i64 %a, i64 %b) nounwind { ; RV32I-LABEL: shl64: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: sw ra, 12(s0) ; RV32I-NEXT: lui a3, %hi(__ashldi3) ; RV32I-NEXT: addi a3, a3, %lo(__ashldi3) diff --git a/test/CodeGen/RISCV/wide-mem.ll b/test/CodeGen/RISCV/wide-mem.ll index 18ab52aaf1386..cbb89f631a5d4 100644 --- a/test/CodeGen/RISCV/wide-mem.ll +++ b/test/CodeGen/RISCV/wide-mem.ll @@ -6,7 +6,7 @@ define i64 @load_i64(i64 *%a) nounwind { ; RV32I-LABEL: load_i64: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: lw a2, 0(a0) ; RV32I-NEXT: lw a1, 4(a0) ; RV32I-NEXT: addi a0, a2, 0 @@ -21,7 +21,7 @@ define i64 @load_i64(i64 *%a) nounwind { ; generate two addi define i64 @load_i64_global() nounwind { ; RV32I-LABEL: load_i64_global: -; RV32I: # BB#0: +; RV32I: # %bb.0: ; RV32I-NEXT: lui a0, %hi(val64) ; RV32I-NEXT: addi a0, a0, %lo(val64) ; RV32I-NEXT: lw a0, 0(a0) diff --git a/test/CodeGen/SPARC/LeonItinerariesUT.ll b/test/CodeGen/SPARC/LeonItinerariesUT.ll index 87e0c4621c084..5a6be134686bb 100644 --- a/test/CodeGen/SPARC/LeonItinerariesUT.ll +++ b/test/CodeGen/SPARC/LeonItinerariesUT.ll @@ -47,4 +47,4 @@ entry: %6 = fmul float %5, %3 %7 = fdiv float %6, %4 ret float %7 -} \ No newline at end of file +} diff --git a/test/CodeGen/SPARC/analyze-branch.ll b/test/CodeGen/SPARC/analyze-branch.ll index 7d2096033a03c..c39dde5a2b88b 100644 --- a/test/CodeGen/SPARC/analyze-branch.ll +++ b/test/CodeGen/SPARC/analyze-branch.ll @@ -18,7 +18,7 @@ define void @test_Bcc_fallthrough_taken(i32 %in) nounwind { ; CHECK: cmp {{%[goli][0-9]+}}, 42 ; CHECK: bne [[FALSE:.LBB[0-9]+_[0-9]+]] ; CHECK-NEXT: nop -; CHECK-NEXT: ! BB# +; CHECK-NEXT: ! %bb. ; CHECK-NEXT: call test_true ; CHECK: [[FALSE]]: @@ -42,7 +42,7 @@ define void @test_Bcc_fallthrough_nottaken(i32 %in) nounwind { ; CHECK: be [[TRUE:.LBB[0-9]+_[0-9]+]] ; CHECK-NEXT: nop -; CHECK-NEXT: ! BB# +; CHECK-NEXT: ! %bb. ; CHECK-NEXT: call test_false ; CHECK: [[TRUE]]: diff --git a/test/CodeGen/SPARC/vector-extract-elt.ll b/test/CodeGen/SPARC/vector-extract-elt.ll index 702f063bfcc6a..47f39d5b9fbb2 100644 --- a/test/CodeGen/SPARC/vector-extract-elt.ll +++ b/test/CodeGen/SPARC/vector-extract-elt.ll @@ -5,7 +5,7 @@ ; look-thru for extractelement then we we know that the add will yield a ; non-negative result. define i1 @test1(<4 x i16>* %in) { -; CHECK-LABEL: ! BB#0: +; CHECK-LABEL: ! %bb.0: ; CHECK-NEXT: retl ; CHECK-NEXT: sethi 0, %o0 %vec2 = load <4 x i16>, <4 x i16>* %in, align 1 diff --git a/test/CodeGen/SystemZ/DAGCombiner_isAlias.ll b/test/CodeGen/SystemZ/DAGCombiner_isAlias.ll index 8c31f073276af..a42f625a5363e 100644 --- a/test/CodeGen/SystemZ/DAGCombiner_isAlias.ll +++ b/test/CodeGen/SystemZ/DAGCombiner_isAlias.ll @@ -9,7 +9,7 @@ ; store i1 true, i1* %g_717.sink.i, align 4 ; %.b = load i1, i1* @g_2, align 4 -; CHECK: # BB#6: # %crc32_gentab.exit +; CHECK: # %bb.6: # %crc32_gentab.exit ; CHECK: larl %r2, g_2 ; CHECK-NEXT: llc %r3, 0(%r2) ; CHECK-NOT: %r2 diff --git a/test/CodeGen/SystemZ/RAbasic-invalid-LR-update.mir b/test/CodeGen/SystemZ/RAbasic-invalid-LR-update.mir index 2f532f0a5efb2..e4365f605cbc4 100644 --- a/test/CodeGen/SystemZ/RAbasic-invalid-LR-update.mir +++ b/test/CodeGen/SystemZ/RAbasic-invalid-LR-update.mir @@ -149,7 +149,7 @@ body: | %11 = VGBM 0 %43 = LHIMux 0 %44 = LARL %const.0 - %45 = VL64 %44, 0, _ :: (load 8 from constant-pool) + %45 = VL64 %44, 0, %noreg :: (load 8 from constant-pool) bb.1: ADJCALLSTACKDOWN 0, 0 @@ -160,19 +160,19 @@ body: | KILL killed %f0d bb.2: - %17 = VLGVH %11, _, 0 + %17 = VLGVH %11, %noreg, 0 %19 = LHR %17.subreg_l32 undef %20.subreg_l64 = LGHI 0 %20 = DSGFR %20, %19 - %22 = VLGVH %11, _, 3 + %22 = VLGVH %11, %noreg, 3 %24 = LHR %22.subreg_l32 undef %25.subreg_l64 = LGHI 0 %25 = DSGFR %25, %24 - %31 = VLGVH %11, _, 1 + %31 = VLGVH %11, %noreg, 1 %33 = LHR %31.subreg_l32 undef %34.subreg_l64 = LGHI 0 %34 = DSGFR %34, %33 - %37 = VLGVH %11, _, 2 + %37 = VLGVH %11, %noreg, 2 %39 = LHR %37.subreg_l32 undef %40.subreg_l64 = LGHI 0 %40 = DSGFR %40, %39 @@ -191,10 +191,10 @@ body: | bb.4: %36 = VLVGP %25.subreg_l64, %25.subreg_l64 - %36 = VLVGH %36, %20.subreg_l32, _, 0 - %36 = VLVGH %36, %34.subreg_l32, _, 1 - dead %36 = VLVGH %36, %40.subreg_l32, _, 2 - %4 = LG undef %42, 0, _ :: (load 8 from `i64* undef`) + %36 = VLVGH %36, %20.subreg_l32, %noreg, 0 + %36 = VLVGH %36, %34.subreg_l32, %noreg, 1 + dead %36 = VLVGH %36, %40.subreg_l32, %noreg, 2 + %4 = LG undef %42, 0, %noreg :: (load 8 from `i64* undef`) undef %57.subreg_h64 = LLILL 0 undef %66.subreg_h64 = LLILL 0 undef %79.subreg_h64 = LLILL 0 @@ -204,27 +204,27 @@ body: | bb.5: bb.6: - %51 = VLGVH undef %7, _, 0 + %51 = VLGVH undef %7, %noreg, 0 %53 = LLHRMux %51.subreg_l32 - %54 = VLGVH undef %1, _, 0 + %54 = VLGVH undef %1, %noreg, 0 %57.subreg_l32 = LLHRMux %54.subreg_l32 %58 = COPY %57 %58 = DLR %58, %53 - %60 = VLGVH undef %7, _, 3 + %60 = VLGVH undef %7, %noreg, 3 %62 = LLHRMux %60.subreg_l32 - %63 = VLGVH undef %1, _, 3 + %63 = VLGVH undef %1, %noreg, 3 %66.subreg_l32 = LLHRMux %63.subreg_l32 %67 = COPY %66 %67 = DLR %67, %62 - %73 = VLGVH undef %7, _, 1 + %73 = VLGVH undef %7, %noreg, 1 %75 = LLHRMux %73.subreg_l32 - %76 = VLGVH undef %1, _, 1 + %76 = VLGVH undef %1, %noreg, 1 %79.subreg_l32 = LLHRMux %76.subreg_l32 %80 = COPY %79 %80 = DLR %80, %75 - %83 = VLGVH undef %7, _, 2 + %83 = VLGVH undef %7, %noreg, 2 %85 = LLHRMux %83.subreg_l32 - %86 = VLGVH undef %1, _, 2 + %86 = VLGVH undef %1, %noreg, 2 %89.subreg_l32 = LLHRMux %86.subreg_l32 %90 = COPY %89 %90 = DLR %90, %85 @@ -248,12 +248,12 @@ body: | bb.9: %82 = VLVGP %67.subreg_h64, %67.subreg_h64 - %82 = VLVGH %82, %58.subreg_hl32, _, 0 - %82 = VLVGH %82, %80.subreg_hl32, _, 1 - dead %82 = VLVGH %82, %90.subreg_hl32, _, 2 + %82 = VLVGH %82, %58.subreg_hl32, %noreg, 0 + %82 = VLVGH %82, %80.subreg_hl32, %noreg, 1 + dead %82 = VLVGH %82, %90.subreg_hl32, %noreg, 2 %96 = AFIMux %96, 1879048192, implicit-def dead %cc - %96 = SRL %96, _, 31 - dead %11 = VLVGF %11, %96, _, 1 + %96 = SRL %96, %noreg, 31 + dead %11 = VLVGF %11, %96, %noreg, 1 %100 = LHIMux 0 bb.10: diff --git a/test/CodeGen/SystemZ/clear-liverange-spillreg.mir b/test/CodeGen/SystemZ/clear-liverange-spillreg.mir index 0ab969b56cc73..06729f0b91a63 100644 --- a/test/CodeGen/SystemZ/clear-liverange-spillreg.mir +++ b/test/CodeGen/SystemZ/clear-liverange-spillreg.mir @@ -223,14 +223,14 @@ body: | bb.11: %4 = COPY %60 - %6 = SLLG %120, _, 1 + %6 = SLLG %120, %noreg, 1 %7 = LA %6, 64, %41 %6 = AGR %6, %42, implicit-def dead %cc - %45 = SRLK %120.subreg_l32, _, 31 + %45 = SRLK %120.subreg_l32, %noreg, 31 %45 = AR %45, %120.subreg_l32, implicit-def dead %cc %45 = NIFMux %45, 536870910, implicit-def dead %cc %47 = SRK %120.subreg_l32, %45, implicit-def dead %cc - %47 = SLL %47, _, 3 + %47 = SLL %47, %noreg, 3 %81 = LGFR %47 bb.12: @@ -284,43 +284,43 @@ body: | MVHI %0, 332, 2 :: (store 4) %60 = COPY %126 %60 = AR %60, %4, implicit-def dead %cc - %18 = LHMux %6, 0, _ :: (load 2) + %18 = LHMux %6, 0, %noreg :: (load 2) CHIMux %38, 0, implicit-def %cc BRC 14, 6, %bb.19, implicit killed %cc J %bb.18 bb.18: - %62 = SLLG %81, _, 1 + %62 = SLLG %81, %noreg, 1 %64 = LA %62, 0, %63 - %65 = LG undef %66, 0, _ :: (load 8) - %67 = LGF undef %68, 0, _ :: (load 4) + %65 = LG undef %66, 0, %noreg :: (load 8) + %67 = LGF undef %68, 0, %noreg :: (load 4) MVC undef %69, 0, 2, %64, 0 :: (store 2), (load 2) %70 = COPY %81 %70 = OILL64 %70, 3, implicit-def dead %cc - %71 = LA %70, 2, _ - %72 = SLLG %71, _, 1 + %71 = LA %70, 2, %noreg + %72 = SLLG %71, %noreg, 1 %73 = LHMux %72, 0, %63 :: (load 2) %74 = LA %70, 2, %67 - %75 = SLLG %74, _, 1 - %76 = LG %65, 0, _ :: (load 8) + %75 = SLLG %74, %noreg, 1 + %76 = LG %65, 0, %noreg :: (load 8) STHMux %73, %76, 0, %75 :: (store 2) - %77 = LG undef %78, 0, _ :: (load 8) + %77 = LG undef %78, 0, %noreg :: (load 8) %79 = LHRL @rec_mbY8x8 :: (load 2) - STHMux %79, %77, 0, _ :: (store 2) + STHMux %79, %77, 0, %noreg :: (store 2) %80 = LHMux %72, 0, %63 :: (load 2) STHMux %80, %77, 0, %75 :: (store 2) %81 = OILL64 %81, 7, implicit-def dead %cc - %82 = SLLG %81, _, 1 + %82 = SLLG %81, %noreg, 1 %83 = LHMux %82, 0, %63 :: (load 2) - STHMux %83, %77, 0, _ :: (store 2) + STHMux %83, %77, 0, %noreg :: (store 2) %84 = LA %62, 64, %63 MVC undef %85, 0, 2, %84, 0 :: (store 2), (load 2) - %86 = SLLG %70, _, 1 + %86 = SLLG %70, %noreg, 1 %87 = LHMux %86, 64, %63 :: (load 2) - %88 = SLLG %67, _, 3 + %88 = SLLG %67, %noreg, 3 %89 = LG %65, 16, %88 :: (load 8) %90 = LA %70, 0, %67 - %91 = SLLG %90, _, 1 + %91 = SLLG %90, %noreg, 1 STHMux %87, %89, 0, %91 :: (store 2) %92 = LA %72, 64, %63 MVC undef %93, 0, 2, %92, 0 :: (store 2), (load 2) @@ -332,8 +332,8 @@ body: | bb.19: successors: %bb.20(0x04000000), %bb.11(0x7c000000) - %98 = LGH %7, 0, _ :: (load 2) - %99 = LGH undef %100, 0, _ :: (load 2) + %98 = LGH %7, 0, %noreg :: (load 2) + %99 = LGH undef %100, 0, %noreg :: (load 2) ADJCALLSTACKDOWN 0, 0 %101 = LGFR %120.subreg_l32 %102 = LGFR %18 @@ -347,7 +347,7 @@ body: | ADJCALLSTACKDOWN 0, 0 CallBRASL @reset_coding_state, undef %r2d, csr_systemz, implicit-def dead %r14d, implicit-def dead %cc ADJCALLSTACKUP 0, 0 - %120 = LA %120, 1, _ + %120 = LA %120, 1, %noreg CGHI %120, 4, implicit-def %cc BRC 14, 6, %bb.11, implicit killed %cc J %bb.20 @@ -410,7 +410,7 @@ body: | bb.30: successors: %bb.33(0x00000001), %bb.31(0x7fffffff) - VST64 %130, undef %117, 0, _ :: (store 8) + VST64 %130, undef %117, 0, %noreg :: (store 8) CHIMux undef %118, 2, implicit-def %cc BRC 14, 8, %bb.33, implicit killed %cc J %bb.31 @@ -470,7 +470,7 @@ body: | bb.44: bb.45: - %0 = LG undef %22, 0, _ :: (load 8) + %0 = LG undef %22, 0, %noreg :: (load 8) %38 = LHIMux 0 STRL %38, @bi_pred_me :: (store 4) %120 = LGHI 0 diff --git a/test/CodeGen/SystemZ/dag-combine-02.ll b/test/CodeGen/SystemZ/dag-combine-02.ll new file mode 100644 index 0000000000000..2d96aafb93870 --- /dev/null +++ b/test/CodeGen/SystemZ/dag-combine-02.ll @@ -0,0 +1,192 @@ +; Test that adjustSubwordCmp() maintains the chains properly when creating a +; new extending load. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 -O3 | FileCheck %s + +@g_56 = external hidden unnamed_addr global i64, align 8 +@func_22.l_91 = external hidden unnamed_addr constant [4 x [7 x i16*]], align 8 +@g_102 = external hidden unnamed_addr global i16**, align 8 +@.str = external hidden unnamed_addr constant [2 x i8], align 2 +@.str.1 = external hidden unnamed_addr constant [15 x i8], align 2 +@crc32_context = external hidden unnamed_addr global i32, align 4 +@crc32_tab = external hidden unnamed_addr global [256 x i32], align 4 +@.str.2 = external hidden unnamed_addr constant [36 x i8], align 2 +@.str.3 = external hidden unnamed_addr constant [15 x i8], align 2 +@g_181.0.4.5 = external hidden unnamed_addr global i1, align 2 + +; Function Attrs: argmemonly nounwind +declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) #0 + +; Function Attrs: argmemonly nounwind +declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture writeonly, i8* nocapture readonly, i64, i32, i1) #0 + +; Function Attrs: argmemonly nounwind +declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) #0 + +; Function Attrs: nounwind +define signext i32 @main(i32 signext, i8** nocapture readonly) local_unnamed_addr #1 { + %3 = alloca [4 x [7 x i16*]], align 8 + %4 = icmp eq i32 %0, 2 + br i1 %4, label %5, label %11 + +;