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Basic+SSE2+SSSE3 implementation of SipHash-2-4 based off the paper. On an E5200, icc gives the best speeds for all SSE versions & 32bit versions, gcc gives the best speed for 64bit basic

done to see how difficult implementing the spec was as their source is not up (yet), and curious about 32bit performance

Performance on an E5200

Best Impl.7 bytes128 bytes1024 bytes
icc 32bit202 cycles1015 cycles6.7 cpb
icc 32bit sse2135 cycles688 cycles4.48 cpb
icc 32bit ssse3125 cycles614 cycles3.98 cpb
gcc 64bit61 cycles276 cycles1.81 cpb


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