This project is my practice Digital Curcuit design with SPARTAN3 FPGA, onAZPR SoC.
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sim
ALU.v
CLK_gen.v
CPU自作メモ.txt
GPregistor.v
README.md
a.out
bus.v
cpu.v
ctlr_cpu.v
my_Processing_system_top.v
processor.v
rom.v
spm.v
stage_EX.v
stage_ID.v
stage_IF.v
stage_MEM.v
stage_WR.v
timer.v
uart.v

README.md

my_CPU_with_SPARTAN3

This project is my practice Digital Curcuit design with SPARTAN3 FPGA, onAZPR SoC.

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