Commits on May 6, 2014
  1. removed freescale

    committed May 6, 2014
Commits on May 5, 2014
  1. remove freescale

    Joseph Moschini committed May 5, 2014
  2. Remove freescale

    Joseph Moschini committed May 5, 2014
  3. remove freescale from IN:

    Joseph Moschini committed May 5, 2014
  4. a little test factor

    Joseph Moschini committed May 5, 2014
  5. Port driver

    Joseph Moschini committed May 5, 2014
  6. this file contains the configuration of the 6805

    Joseph Moschini committed May 5, 2014
  7. ccr is replaced by alu

    Joseph Moschini committed May 5, 2014
  8. add the documentation directory

    Joseph Moschini committed May 5, 2014
  9. Files updated from the freescale directory

    Joseph Moschini committed May 5, 2014
Commits on Oct 17, 2013
  1. Updated to indicate that the project has been moved

    Joseph Moschini committed Oct 17, 2013
Commits on Oct 13, 2013
  1. make some changes to cpu structures

    Joseph Moschini committed Oct 13, 2013
Commits on Jan 18, 2013
  1. fix the effects on read-instruction

    Signed-off-by: Joseph Moschini <jmos@iprimus.com.au>
    Joseph Moschini committed Jan 18, 2013
Commits on Jan 16, 2013
  1. Opps Fix a commit that went wrong way

    Joseph Moschini committed Jan 16, 2013
  2. Opp fix a commit that is wrong

    Joseph Moschini committed Jan 16, 2013
  3. Opps fix a commit that is wrong

    Joseph Moschini committed Jan 16, 2013
Commits on Jan 15, 2013
  1. Revert "Still experimenting with port control"

    This reverts commit 7e3b433.
    Joseph Moschini committed Jan 15, 2013
Commits on Dec 30, 2012
  1. Still experimenting with port control

    Joseph Moschini committed Dec 30, 2012
Commits on Dec 29, 2012
  1. Read instruction routine

    Joseph Moschini committed Dec 29, 2012
Commits on Oct 23, 2012
  1. Add memory routines

    Joseph Moschini committed Oct 24, 2012
Commits on Oct 14, 2012
  1. Changed Ports with DDR

    port-read fixed
    port-write fixed
    Joseph Moschini committed Oct 14, 2012
Commits on Oct 12, 2012
  1. Update port design

    Joseph Moschini committed Oct 12, 2012
Commits on Oct 11, 2012
  1. Add an output

    Joseph Moschini committed Oct 11, 2012
Commits on Oct 10, 2012
  1. Port A change to a model

    Joseph Moschini committed Oct 10, 2012
Commits on Oct 9, 2012
  1. Updating Data Direction Register DDR

    Memory now creates ports
    Added PORTA module
    upadated ports
    
    Signed-off-by: Joseph Moschini <jmos@iprimus.com.au>
    Joseph Moschini committed Oct 9, 2012
Commits on Oct 2, 2012
  1. Update emulator

    Redesign of memory
    changed port to ports
    Joseph Moschini committed Oct 2, 2012
Commits on Aug 14, 2012
  1. Port simulation mm! needs work

    I thinking the model approch may not work
    Joseph Moschini committed Aug 14, 2012
Commits on Aug 9, 2012
  1. Testing some ideas for port routine

    Joseph Moschini committed Aug 9, 2012
  2. general git ignore

    Joseph Moschini committed Aug 9, 2012
  3. Added Data Direction Register

    The DDR affects the Port Input and out port so we need to connect port
    and ddr together.
    Joseph Moschini committed Aug 9, 2012
  4. Added port

    Still up in the air about how I am going to do this, I think models is
    the way to go.
    Joseph Moschini committed Aug 9, 2012