diff --git a/tests/test_config.py b/tests/test_config.py
new file mode 100644
index 0000000..d6b8c18
--- /dev/null
+++ b/tests/test_config.py
@@ -0,0 +1 @@
+TEST_FREQUENCY_HZ = 1000000
\ No newline at end of file
diff --git a/tests/test_spi.py b/tests/test_spi.py
index ecd73d9..911d406 100644
--- a/tests/test_spi.py
+++ b/tests/test_spi.py
@@ -7,7 +7,7 @@
     SDI    -> SQ1 and LA4
     SPI.CS -> LA3
 """
-
+from test_config import TEST_FREQUENCY_HZ
 import pytest
 import re
 from numpy import ndarray
@@ -30,7 +30,8 @@
 CS = "LA3"
 SPIMaster._primary_prescaler = PPRE = 0
 SPIMaster._secondary_prescaler = SPRE = 0
-PWM_FERQUENCY = SPIMaster._frequency * 2 / 3
+# Hardcoded to 1MHz for testing
+PWM_FERQUENCY = TEST_FREQUENCY_HZ * 2 / 3
 MICROSECONDS = 1e-6
 RELTOL = 0.05
 # Number of expected logic level changes.
diff --git a/tests/test_uart.py b/tests/test_uart.py
index fd861e5..8a3bc35 100644
--- a/tests/test_uart.py
+++ b/tests/test_uart.py
@@ -7,6 +7,7 @@
 """
 
 import pytest
+from test_config import TEST_FREQUENCY_HZ
 
 from pslab.bus.uart import UART
 from pslab.instrument.logic_analyzer import LogicAnalyzer
@@ -16,7 +17,8 @@
 WRITE_DATA = 0x55
 TXD2 = "LA1"
 RXD2 = "SQ1"
-PWM_FERQUENCY = UART._baudrate // 2
+# Hardcoded to 1MHz for testing
+PWM_FREQUENCY = TEST_FREQUENCY_HZ // 2
 MICROSECONDS = 1e-6
 RELTOL = 0.05
 # Number of expected logic level changes.