From 88af2792e6a6ed2fe72038abb524378fea848dc9 Mon Sep 17 00:00:00 2001 From: Sehaj Modi Date: Mon, 15 Dec 2025 13:03:07 +0530 Subject: [PATCH 1/3] Fix tests: Use hardcoded constants to fix TypeError --- tests/test_spi.py | 3 ++- tests/test_uart.py | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/tests/test_spi.py b/tests/test_spi.py index ecd73d9..b075912 100644 --- a/tests/test_spi.py +++ b/tests/test_spi.py @@ -30,7 +30,8 @@ CS = "LA3" SPIMaster._primary_prescaler = PPRE = 0 SPIMaster._secondary_prescaler = SPRE = 0 -PWM_FERQUENCY = SPIMaster._frequency * 2 / 3 +# Hardcoded to 1MHz for testing +PWM_FERQUENCY = 1000000.0 * 2 / 3 MICROSECONDS = 1e-6 RELTOL = 0.05 # Number of expected logic level changes. diff --git a/tests/test_uart.py b/tests/test_uart.py index fd861e5..f83f6f8 100644 --- a/tests/test_uart.py +++ b/tests/test_uart.py @@ -16,7 +16,8 @@ WRITE_DATA = 0x55 TXD2 = "LA1" RXD2 = "SQ1" -PWM_FERQUENCY = UART._baudrate // 2 +# Hardcoded to 1MHz for testing +PWM_FERQUENCY = 1000000 // 2 MICROSECONDS = 1e-6 RELTOL = 0.05 # Number of expected logic level changes. From 58a5d2f0d824a2be3316055f3501a2cb05f5ec1a Mon Sep 17 00:00:00 2001 From: Sehaj Modi Date: Mon, 15 Dec 2025 13:25:30 +0530 Subject: [PATCH 2/3] Refactor: Centralize test frequency and fix typos --- tests/test_config.py.py | 1 + tests/test_spi.py | 4 ++-- tests/test_uart.py | 3 ++- 3 files changed, 5 insertions(+), 3 deletions(-) create mode 100644 tests/test_config.py.py diff --git a/tests/test_config.py.py b/tests/test_config.py.py new file mode 100644 index 0000000..d6b8c18 --- /dev/null +++ b/tests/test_config.py.py @@ -0,0 +1 @@ +TEST_FREQUENCY_HZ = 1000000 \ No newline at end of file diff --git a/tests/test_spi.py b/tests/test_spi.py index b075912..911d406 100644 --- a/tests/test_spi.py +++ b/tests/test_spi.py @@ -7,7 +7,7 @@ SDI -> SQ1 and LA4 SPI.CS -> LA3 """ - +from test_config import TEST_FREQUENCY_HZ import pytest import re from numpy import ndarray @@ -31,7 +31,7 @@ SPIMaster._primary_prescaler = PPRE = 0 SPIMaster._secondary_prescaler = SPRE = 0 # Hardcoded to 1MHz for testing -PWM_FERQUENCY = 1000000.0 * 2 / 3 +PWM_FERQUENCY = TEST_FREQUENCY_HZ * 2 / 3 MICROSECONDS = 1e-6 RELTOL = 0.05 # Number of expected logic level changes. diff --git a/tests/test_uart.py b/tests/test_uart.py index f83f6f8..8a3bc35 100644 --- a/tests/test_uart.py +++ b/tests/test_uart.py @@ -7,6 +7,7 @@ """ import pytest +from test_config import TEST_FREQUENCY_HZ from pslab.bus.uart import UART from pslab.instrument.logic_analyzer import LogicAnalyzer @@ -17,7 +18,7 @@ TXD2 = "LA1" RXD2 = "SQ1" # Hardcoded to 1MHz for testing -PWM_FERQUENCY = 1000000 // 2 +PWM_FREQUENCY = TEST_FREQUENCY_HZ // 2 MICROSECONDS = 1e-6 RELTOL = 0.05 # Number of expected logic level changes. From b96a30e7493bd70c5234d08415a6f0f391d829b5 Mon Sep 17 00:00:00 2001 From: Sehaj Modi Date: Mon, 15 Dec 2025 13:26:43 +0530 Subject: [PATCH 3/3] Fix double file extension --- tests/{test_config.py.py => test_config.py} | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename tests/{test_config.py.py => test_config.py} (100%) diff --git a/tests/test_config.py.py b/tests/test_config.py similarity index 100% rename from tests/test_config.py.py rename to tests/test_config.py